WO2023279857A1

WO2023279857A1 - Measurement method and system for semiconductor structure

Info

Publication number: WO2023279857A1
Application number: PCT/CN2022/093275
Authority: WO
Inventors: 李宗翰; 刘志拯
Original assignee: 长鑫存储技术有限公司
Priority date: 2021-07-06
Filing date: 2022-05-17
Publication date: 2023-01-12
Also published as: CN115588622A

Abstract

The present disclosure relates to the technical field of semiconductors. Provided are a measurement method and system for a semiconductor structure. The measurement method for a semiconductor structure comprises the following steps: providing a first semiconductor structure and a second semiconductor structure. In the present disclosure, capacitance values of the first semiconductor structure and the second semiconductor structure are respectively acquired; on the premise that the second semiconductor structure and the first semiconductor structure are prepared on the same wafer, the ratio of a capacitance value of a first central area to a capacitance value of a second central area and the ratio of a capacitance value of a first edge area to a capacitance value of a second edge area are obtained, and the ratio of the capacitance value of the first central area to the capacitance value of the first edge area is then obtained according to the numerical values; and the thickness uniformity of an active layer is determined by means of the magnitude of the ratio, so as to provide a theoretical support for the preparation of semiconductor structures.

Description

Measurement method and measurement system for semiconductor structure

This disclosure claims the priority of the Chinese patent application with the application number 202110764167.5 and the application name "Measurement method and measurement system for semiconductor structures" submitted to the China Patent Office on July 06, 2021, the entire contents of which are incorporated in this disclosure by reference middle.

technical field

The present disclosure relates to the technical field of semiconductors, and in particular, to a measurement method and a measurement system for a semiconductor structure.

Background technique

Dynamic random access memory (DRAM for short) is a semiconductor memory that writes and reads data at high speed and randomly, and is widely used in data storage modules or devices.

The DRAM usually includes an array area and a peripheral circuit area arranged around the array area, wherein a transistor is arranged in the peripheral circuit area, and the transistor usually includes an active layer, a gate oxide layer and a gate arranged on the active layer, In related technologies, a capacitance-voltage measurement method is usually used to measure the capacitance between the active layer and the gate, and the capacitance is used to ensure the performance of the DRAM.

However, the above measurement method can only obtain the capacitance value between the active layer and the gate, and cannot characterize the uniformity of the active layer.

Contents of the invention

A first aspect of an embodiment of the present disclosure provides a method for measuring a semiconductor structure, which includes the following steps:

A first semiconductor structure is provided, the first semiconductor structure includes a first active layer and a first gate oxide layer and a first gate stacked on the first active layer, and the first gate is on the first active layer The projection on the first active layer includes a first central area and a first edge area surrounding the first central area;

A second semiconductor structure is provided, the second semiconductor structure is prepared on the same wafer as the first semiconductor structure, and the second semiconductor structure includes a second active layer and is stacked on the second active layer A second gate oxide layer and a second gate on the second active layer, the second gate projects on the second active layer including a second central region and a second edge region surrounding the second central region; the first the lengths of the central area and the second central area are different, and the lengths of the first edge area and the second edge area are the same;

Acquiring the capacitance C ₁ of the first semiconductor structure and the capacitance C ₂ of the second semiconductor structure;

acquiring a ratio of the capacitance value of the first central region to a capacitance value of the second central region, and obtaining a ratio of the capacitance value of the first edge region to the capacitance value of the second edge region;

According to the C _{total 1} , the C _{total 2} , the ratio of the capacitance value of the first central area to the capacitance value of the second central area, and the capacitance value of the first edge area to the second edge The ratio of the capacitance value of the region is to obtain the ratio of the capacitance value of the first central region to the capacitance value of the first edge region.

In some embodiments, the step of obtaining the capacitance value Call1 of the first semiconductor structure and the capacitance value _Call22 of the _second semiconductor structure includes:

Acquiring the capacitance value between the first gate and the first active layer in the first semiconductor structure, the capacitance value is denoted as C ₁ ;

Acquiring a capacitance value between the second gate and the second active layer in the second semiconductor structure, the capacitance value is denoted as C ₂ .

In some embodiments, the step of obtaining the capacitance value between the first gate and the first active layer in the first semiconductor structure, where the capacitance value is denoted as _C1 , includes:

providing a first power module, the first power module is connected to the first gate, and is used to provide a voltage to the first gate;

A first detection module is provided, the first detection module is connected to the first active layer, and is used to measure the amplitude and phase shift of the current flowing through the first gate and the first gate oxide layer;

According to the voltage value, the amplitude of the current and the phase offset, C _{total 1} is obtained.

In some embodiments, the first power module is connected to the first gate through a first connecting wire;

The first detection module is connected to the first active layer through a second connecting wire.

In some embodiments, there is a first pad between the first connecting wire and the first gate, and there is a second pad between the second connecting wire and the first active layer.

In some embodiments, there are multiple first semiconductor structures, and the multiple first semiconductor structures are arranged in an array;

The number of the first connecting wires is multiple, and each of the first connecting wires is connected to the first pads of the first semiconductor structures on the same row;

The number of the second connecting wires is multiple, and each of the second connecting wires is connected to the second pads of the first semiconductor structures on the same row.

In some embodiments, when the number of the first semiconductor structures is multiple, and the multiple first semiconductor structures are arranged in an array, the step of obtaining the capacitance value C of the first semiconductor structure of ₁ includes: :

obtaining a total capacitance value between the first active layer and the first gate of a plurality of the first semiconductor structures;

According to the total capacitance value between the first active layer of the first semiconductor structure and the first gate, the first active layer and the first gate of the first semiconductor structure are obtained. An average of the capacitance values between the gates, this average value is taken as C ₁ .

In some embodiments, the step of obtaining the capacitance value between the second gate and the second active layer in the second semiconductor structure includes:

providing a second power module, the second power module is connected to the second grid, and is used to provide a voltage to the second grid;

A second detection module is provided, the second detection module is connected to the second active layer, and is used to measure the amplitude and phase shift of the current flowing through the second gate and the second gate oxide layer;

According to the voltage value, the amplitude of the current and the phase offset, C _{total 2} is obtained.

In some embodiments, the second power module is connected to the second gate through a third connecting wire;

The second detection module is connected to the second active layer through a fourth connection wire.

In some embodiments, there is a third pad between the third connecting wire and the second gate, and there is a fourth pad between the fourth connecting wire and the second active layer.

In some embodiments, there are multiple second semiconductor structures, and the multiple second semiconductor structures are arranged in an array;

The number of the third connecting wires is multiple, and each of the third connecting wires is connected to the third pads of the second semiconductor structures on the same row;

The number of the fourth connecting wires is multiple, and each of the fourth connecting wires is connected to the fourth pads of the second semiconductor structures on the same row.

In some embodiments, when the number of the second semiconductor structures is multiple, and the multiple second semiconductor structures are arranged in an array, the second gate and the The step of capacitance value between the second active layer comprises:

acquiring a total capacitance value between the second active layer and the second gate of a plurality of the second semiconductor structures;

According to the total capacitance between the second active layer and the second gate of the plurality of second semiconductor structures, the relationship between the second active layer and the second gate of the second semiconductor structure is obtained. The average value of the capacitance value between, this average value is taken as C _{total 2} .

In some embodiments, obtaining the ratio of the capacitance value of the first central region to the capacitance value of the second central region, and obtaining the capacitance value of the second edge region and the capacitance value of the second edge region The steps of the ratio include:

Along the first direction, the widths of the first central region and the first edge region are both A;

Along the second direction, the length of the first central region is a, the length of the first edge region is A-a, the area of the first central region is A×a, and the area of the first edge region is A ×(A-a);

Along the first direction, the widths of the second central region and the second edge region are nA;

Along the second direction, the length of the second central region is (n-1)A+a, the length of the second edge region is A-a, and the area of the second central region is [(n-1 )A+a]×nA, the area of the second edge region is nA(A-a);

The ratio of the capacitance value of the first central area to the capacitance value of the second central area is

The ratio of the capacitance value of the first edge region to the capacitance value of the second edge region is

In some embodiments, the ratio of the capacitance value of the first central region to the capacitance value of the first edge region is obtained by the following formula:

Wherein, C _c1 represents the capacitance value of the first central area, C ₂ represents the capacitance value of the first edge area, and m represents the ratio of C _{total 1} to C _{total 2} .

In some embodiments, the first central region includes oppositely disposed first and second edges;

The first edge region includes a first region and a second region, the first region is arranged in close contact with the first edge, and the second region is arranged in contact with the second edge;

The capacitance value of the first edge region is equal to the sum of the capacitance value of the first region and the capacitance value of the second region.

A second aspect of an embodiment of the present disclosure provides a semiconductor structure measurement system, including:

A first semiconductor structure, the first semiconductor structure includes a first active layer and a first gate oxide layer and a first gate stacked on the first active layer, the first gate is on the first active layer The projection on the first active layer comprises a first central area and a first edge area surrounding said first central area;

a second semiconductor structure, and the second semiconductor structure includes a second active layer and a second gate oxide layer and a second gate stacked on the second active layer, and the second gate is on the second active layer The projection on the second active layer includes a second central area and a second edge area surrounding the second central area;

The first central area and the second central area have different widths, and the first edge area and the second edge area have the same width;

A processor, the processor is used to obtain the capacitance value C _{total 1} of the first semiconductor structure and the capacitance value C _{total 2} of the second semiconductor structure; obtain the capacitance value of the first central region and the capacitance value of the second semiconductor structure The ratio of the capacitance value of the central area, and the ratio of the capacitance value of the first edge area to the capacitance value of the second edge area; and according to the C _{total 1} , the C _{total 2} , the first The ratio of the capacitance value of the central area to the capacitance value of the second central area and the ratio of the capacitance value of the first edge area to the capacitance value of the second edge area are obtained to obtain the capacitance value of the first central area and the ratio of the capacitance value of the first edge region.

In some embodiments, the processor includes a first power module, a first detection module, a second power module, and a second detection module;

The first power module is connected to the first grid, and is used to provide voltage to the first grid;

The first detection module is connected to the first active layer, and is used to measure the amplitude and phase shift of the current flowing through the first gate and the first gate oxide layer;

The second power module is connected to the second grid, and is used to provide voltage to the second grid;

The second detection module is connected to the second active layer, and is used for measuring the amplitude and phase shift of the current flowing through the second gate and the second gate oxide layer.

In some embodiments, the first power supply module is connected to the first gate through a first connection wire; the first detection module is connected to the first active layer through a second connection wire;

The second power supply module is connected to the second gate through a third connection wire; the second detection module is connected to the second active layer through a fourth connection wire.

In some embodiments, there are multiple first semiconductor structures, and the multiple first semiconductor structures are arranged in a rectangular array;

The number of the first connecting wires is multiple, and each of the first connecting wires is connected to the first gates of the first semiconductor structures located in the same row;

The number of the second connecting wires is multiple, and each of the second connecting wires is connected to the first active layer of the first semiconductor structure on the same row.

In some embodiments, there are multiple second semiconductor structures, and the multiple second semiconductor structures are arranged in a rectangular array;

The number of the third connecting wires is multiple, and each of the third connecting wires is connected to the second gates of the second semiconductor structures on the same row;

The number of the fourth connecting wires is multiple, and each of the fourth connecting wires is connected to the second active layer of the first semiconductor structure on the same row.

In the semiconductor structure measurement method and measurement system provided by the embodiments of the present disclosure, by obtaining the capacitance values of the first semiconductor structure and the second semiconductor structure respectively, at the same time, when the second semiconductor structure and the first semiconductor structure are on the same wafer Under the premise of preparation, the ratio of the capacitance value of the first central region to the capacitance value of the second central region, and the ratio of the capacitance value of the first edge region to the capacitance value of the second edge region are known, and according to the above values, The ratio of the capacitance value of the first central region to the capacitance value of the first edge region is obtained, and the thickness uniformity of the active layer is judged by the magnitude of the ratio.

In addition to the technical problems solved by the embodiments of the present disclosure described above, the technical features that constitute the technical solutions, and the beneficial effects brought by the technical features of these technical solutions, the measurement method and measurement system for semiconductor structures provided by the embodiments of the present disclosure Other technical problems that can be solved, other technical features contained in the technical solution, and the beneficial effects brought by these technical features will be further described in detail in the specific implementation manner.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description These are some embodiments of the present disclosure. For those skilled in the art, other drawings can also be obtained according to these drawings without creative work.

FIG. 1 is a process flow diagram of a method for measuring a semiconductor structure provided by an embodiment of the present disclosure;

FIG. 2 is a schematic diagram of a first semiconductor structure provided by an embodiment of the present disclosure;

FIG. 3 is a top view of a first semiconductor structure provided by an embodiment of the present disclosure;

FIG. 4 is a top view of a second semiconductor structure provided by an embodiment of the present disclosure;

FIG. 5 is an arrangement diagram of a first semiconductor structure provided by an embodiment of the present disclosure;

FIG. 6 is an arrangement diagram of a second semiconductor structure provided by an embodiment of the present disclosure.

detailed description

When preparing transistors, the epitaxial growth process is usually used to form a sequentially stacked active layer, gate oxide layer, and gate on the substrate. Due to the limitation of the epitaxial growth process, it is difficult to ensure the uniformity of the thickness of the active layer, making the active layer The thickness of the central region will be greater than the thickness of the edge region of the active layer, thereby affecting the performance of the transistor. In related technologies, the capacitance value between the active layer and the gate is usually measured, and the capacitance value is used to characterize the performance of the transistor. However, the above method cannot measure the capacitance value between the central region of the active layer and the gate, and the capacitance value between the edge region of the active layer and the gate, and cannot characterize the thickness uniformity of the active layer.

In view of the above technical problems, in this embodiment, by obtaining the capacitance values of the first semiconductor structure and the second semiconductor structure respectively, and at the same time, under the premise that the second semiconductor structure and the first semiconductor structure are prepared on the same wafer, Know the ratio of the capacitance value of the first central area to the capacitance value of the second central area, and the ratio of the capacitance value of the first edge area to the capacitance value of the second edge area, and obtain the first central area according to the above values The ratio of the capacitance value of the first edge region to the capacitance value of the first edge region, the thickness uniformity of the active layer can be judged by the size of the ratio.

In order to make the above objects, features and advantages of the embodiments of the present disclosure more obvious and understandable, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present disclosure. Apparently, the described embodiments are only some of the embodiments of the present disclosure, not all of them. Based on the embodiments in the present disclosure, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present disclosure.

This embodiment does not limit the semiconductor structure. The semiconductor structure will be described below as an example of a dynamic random access memory (DRAM). However, this embodiment is not limited to this. The semiconductor structure in this embodiment can also be other structures. .

As shown in FIG. 1, the method for preparing a semiconductor structure provided by an embodiment of the present disclosure includes the following steps:

Step S100: providing a first semiconductor structure, the first semiconductor structure includes a first active layer and a first gate oxide layer and a first gate stacked on the first active layer, the first gate is on the first active layer The projection on the layer includes a first central area and a first edge area surrounding the first central area.

As shown in FIG. 2, the first semiconductor structure 100 may further include a substrate 110, which is used as a supporting component of the DRAM for supporting other components disposed thereon, wherein the substrate 110 may be made of a semiconductor material, and the semiconductor The material can be one or more of silicon, germanium, silicon-germanium compound and silicon-carbon compound.

As shown in FIG. 2 , the first active layer 120 is disposed on the substrate 110. The first active layer 120 is usually formed by an epitaxial growth process. Affected by the epitaxial growth process, the first active layer 120 usually has an intermediate thickness. The thin structure on both sides makes the longitudinal cross-section of the first active layer 120 a trapezoidal structure with a small top and a large bottom, wherein the material of the first active layer 120 may include silicon germanium.

The first gate oxide layer 130 is disposed on the first active layer 120, wherein the first gate oxide layer 130 can be a single film layer, or can be a stacked structure, when the first gate oxide layer 130 can include an oxide layer 131 and Dielectric layer 132, the oxide layer 131 is disposed on the surface of the first active layer 120 away from the substrate 110, the dielectric layer 132 is disposed on the surface of the oxide layer 131 away from the first active layer 120, and the material of the oxide layer 131 may include silicon oxide and other insulating materials, the dielectric layer 132 may include HfO2, HfSiO, HfSiON, HfAlO, HfZrO, Al2O3, TaO2, etc., and this material has a high dielectric constant.

The first gate 140 is disposed on the first gate oxide layer 130, and the first gate 140 has an overlapping area with the first active layer 120, when there is a voltage difference between the first gate 140 and the first active layer 120 At this time, there will be an electrostatic field distribution between the first gate 140 and the first active layer 120, thereby storing charges under the action of the electrostatic field, and the amount of stored charges Q is always proportional to its voltage U, and the ratio is called capacitance, expressed in C express.

The projection of the first gate 140 on the first active layer 120 includes a first central region 150 and a first edge region 160 , wherein the first edge region 160 is disposed around the first central region 150 .

At this time, the capacitance value C between the _first gate 140 and the first active layer 120 is equal to the sum of the capacitance value of the first central region and the capacitance value of the first edge region, and the formula is as follows:

C _{total 1} ＝C _c1 +C _e1 (Formula 1.1)

C _c1 represents the capacitance value of the first central region, and C _e1 represents the capacitance value of the first edge region.

It should be noted that, as shown in FIG. 2 , the capacitance value of the first central region refers to the capacitance value of the capacitance formed between the first gate and the first active layer in the middle box, and the capacitance value of the first edge The capacitance value of the region refers to the capacitance value of the capacitance formed between the first gate and the first active layer located in the left and right boxes.

In this embodiment, the first edge area 160 is arranged around the first central area 150, which can be understood as the first edge area 160 semi-encloses the first central area 150, for example, as shown in FIG. 3 , along the second direction, namely X direction in Fig. 3, the first central area 150 has the first edge 151 and the second edge 152 that are arranged oppositely, the first edge area 160 comprises the first area 161 and the second area 162, the first area 161 and the first edge 151 Adhesively disposed, the second region 162 is disposed in adheringly with the second edge 152 .

When the first edge region 160 includes the first region 161 and the second region 162 , the capacitance of the first edge region 160 is equal to the sum of the capacitance of the first region 161 and the capacitance of the second region 162 .

Step S200: providing a second semiconductor structure, the second semiconductor structure is prepared on the same wafer as the first semiconductor structure, and the second semiconductor structure includes a second active layer and a second gate stacked on the second active layer an oxide layer and a second gate, where the projection of the second gate on the second active layer includes a second central region and a second edge region surrounding the second central region, the widths of the first central region and the second central region are different, The first edge region and the second edge region have the same length.

It should be noted that since the second semiconductor structure is prepared on the same wafer as the first semiconductor structure, it can be considered that the structure of the second semiconductor structure is similar to that of the first semiconductor structure in the embodiment under the same preparation conditions. That is, the shape of the first edge area and the second edge area are the same, only the length of the first central area and the second central area is different.

As shown in FIG. 4 , the projection of the second gate 240 on the second active layer 220 includes a second central region 250 and a second edge region 260 , and the second edge region 260 is disposed around the second central region 250 .

The capacitance C _total of the second semiconductor structure is equal to the sum of the capacitance of the second central region and the capacitance of the second edge region, and its formula is as follows:

C _{total 2} ＝C _c2 +C _e2 (Formula 1.2)

C _c2 represents the capacitance value of the second central region, and C _e2 represents the capacitance value of the second edge region.

Step S300: Obtain the capacitance Call1 of the first semiconductor structure and the capacitance _Call2 of the _second semiconductor structure.

Exemplarily, as shown in FIG. 5 , a first power module 300 is provided, and the first power module 300 is connected to the first grid 140 for providing voltage to the first grid 140. For example, the first power module 300 can provide The first grid 140 applies a voltage of known amplitude and frequency.

A first detection module 400 is provided, the first detection module 400 is connected to the first active layer 120, and is used to measure the amplitude and phase shift of the current flowing through the first gate 140 and the first gate oxide layer 130;

According to the voltage value, current amplitude and phase offset, C _{total 1} is obtained, that is to say, C total ₁ is calculated based on voltage, current amplitude and phase offset, and its calculation formula is as follows:

Wherein, V represents the voltage value of the first power supply module, and I represents the amplitude of the current,

stands for phase shift.

The first grid 140 and the first power module 300 may be connected directly or indirectly. For example, as shown in FIG. 5 , a first connection wire 310 is provided between the first grid 140 and the first power module 300 .

In order to facilitate the connection between the first connecting wire 310 and the first grid 140, a first pad 141 can be set on the first grid 140, the first connecting wire 310 is connected to the first pad 141, and the first pad 141 transmits the electrical signal on the first grid 140 , which can improve the accuracy of detecting the voltage of the first grid 140 .

A second connection wire 410 is arranged between the first active layer 120 and the first detection module 400. In order to facilitate the connection between the second connection wire 410 and the first active layer 120, a A second pad 121 is provided, and the second connection wire 410 is connected to the second pad 121 .

In some embodiments, the number of first semiconductor structures 100 may be multiple, and the plurality of first semiconductor structures 100 are arranged in an array. For example, as shown in FIG. 5, the number of first semiconductor structures 100 is nine, The nine first semiconductor structures 100 are arranged in three rows and three columns.

There are multiple first connecting wires 310 , and each first connecting wire is connected to the first pads 141 of the respective first semiconductor structures 100 on the same row.

There are multiple second connecting wires 410 , and each second connecting wire 410 is connected to the second pads 121 of the first semiconductor structures 100 on the same row.

At this time, it is necessary to use the above measurement method to measure the capacitance value of each first semiconductor structure 100 to obtain the total capacitance value between the first active layer 120 and the first gate 140 of the plurality of first semiconductor structures 100 .

According to the total capacitance value between the first active layer 120 of the first semiconductor structure 100 and the first gate 140, the capacitance between the first active layer 120 of the first semiconductor structure 100 and the first gate 140 is obtained. The average value of the capacitance value, this average value is used as C _{total 1} .

This embodiment provides a plurality of first semiconductor structures, and by calculating the average value of the capacitance values of the first semiconductor structures as C ₁ , the accuracy of the capacitance value C ₁ of the first semiconductor structures can be ensured, and then for subsequent accurate The ratio of the capacitance values of the first central area to the first edge area provides protection.

In this embodiment, the method of obtaining the capacitance value C of _the second semiconductor structure can be carried out according to the following steps:

Exemplarily, as shown in FIG. 6, a second power supply module 500 is provided, and the second power supply module 500 is connected to the second grid 240 for providing voltage to the second grid 240, and the second grid is supplied to the second grid through the second voltage module. Pole 240 applies a voltage of known amplitude and frequency.

A second detection module 600 is provided, and the second detection module 600 is connected to the second active layer 220 for measuring the amplitude and phase shift of the current flowing through the second gate 240 and the second gate oxide layer;

According to the voltage value, the amplitude of the current and the phase offset, _{Ctotal 2} is obtained, that is to say, Ctotal ₂ is calculated based on the voltage, current and phase offset.

It should be noted that the calculation formula of the capacitance C ₂ of the second semiconductor structure is the same as the calculation formula of the above C ₁ , which will not be repeated in this embodiment.

The second grid 240 and the second power module 500 may be connected directly or indirectly. For example, as shown in FIG. 4 , a third connection wire 510 is provided between the second grid 240 and the second power module 500 .

In order to facilitate the connection between the third connecting wire 510 and the second grid 240, a third pad 241 may be provided on the second grid 240, and the third connecting wire 510 is connected to the third pad 241.

A fourth connection wire 610 is arranged between the second active layer 220 and the second detection module 600. In order to facilitate the connection between the fourth connection wire 610 and the second active layer 220, the second active layer 220 can A fourth pad 221 is provided, and the fourth connection wire 610 is connected to the fourth pad 221 .

In some embodiments, the number of second semiconductor structures 200 may be multiple, and the plurality of second semiconductor structures 200 are arranged in an array. For example, as shown in FIG. 4, the number of second semiconductor structures 200 is nine, The nine second semiconductor structures 200 are arranged in three rows and three columns.

There are multiple third connecting wires 510 , and each third connecting wire 510 is connected to the first pads 141 of the respective second semiconductor structures 200 on the same row.

There are multiple fourth connecting wires 610 , and each fourth connecting wire 610 is connected to the second pads 121 of the second semiconductor structures 200 on the same row.

At this time, it is necessary to use the above measurement method to measure the capacitance value of each second semiconductor structure 200 to obtain the total capacitance value between the second active layer 220 and the second gate 240 of the plurality of second semiconductor structures 200 .

According to the total capacitance value between the second active layer 220 of the second semiconductor structure 200 and the second gate 240, the capacitance between the second active layer 220 of the second semiconductor structure 200 and the second gate 240 is obtained. The average value of capacitance, this average value is taken as C _{total 2} .

This embodiment provides a plurality of second semiconductor structures, and by calculating the average value of the capacitance values of the second semiconductor structures as C2, the accuracy of the capacitance value C2 of _the _second semiconductor structures can be ensured, and then for subsequent accurate The ratio of the capacitance values of the first central area to the first edge area provides protection.

Step S400: Obtain the ratio of the capacitance value of the first central region to the capacitance value of the second central region, and obtain the ratio of the capacitance value of the second edge region to the capacitance value of the second edge region.

In this embodiment, it is assumed that the shape of the projection of the first grid 140 on the first active layer 120 is a square, and it is also assumed that the shape of the projection of the second grid 240 on the second active layer 220 is also a square. .

As shown in FIG. 3 , along the first direction, that is, the Y direction in FIG. 3 , the widths of the first central region 150 and the first edge region 160 are both A.

Along the second direction, that is, the X direction in FIG. 3 , the length of the first central region 150 is a, and the length of the first edge region is A-a. Correspondingly, the area of the first central region 150 is A×a, and the first edge region The area of the region 160 is A×(A-a).

As shown in FIG. 4 , along the first direction, that is, the Y direction in FIG. 4 , the width of the second central region 250 and the width of the second edge region 260 are both nA.

Since the first semiconductor structure 100 and the second semiconductor structure 200 are prepared on the same wafer, the length of the first edge region 160 and the length of the second edge region 260 are the same under the premise of the same epitaxial growth process, therefore, the second The length of the second edge area 260 is A-a, correspondingly, the length of the second central area 250 is equal to nA-(A-a), that is, the length of the second central area 250 is equal to (n-1)A+a.

The area of the second central region 250 is the length of the second central region 250 multiplied by the width of the second central region 250, and its formula is [(n-1)A+a]×nA, and the area of the second edge region 260 is equal to the width of the second central region 250. The length of the second edge region 260 is multiplied by the width of the second edge region 260, and the formula is nA(A-a).

Capacitance Based Formula

Among them, ε is a dielectric constant, S is the facing area of the capacitor plate, d is the distance of the capacitor plate, and k is the dielectric constant. Under the same dielectric constant, the capacitance and the area are proportional.

Therefore, the ratio of the capacitance value of the first central region 150 to the capacitance value of the second central region 250 is

Its formula is as follows:

Wherein, C _c1 represents the capacitance value of the first central area, and C _c2 represents the capacitance value of the second central area.

The ratio of the capacitance value of the first edge region 160 to the capacitance value of the second edge region 260 is

Its formula is as follows:

Wherein, C _e1 represents the capacitance value of the first edge region, and C _e2 represents the capacitance value of the second edge region.

Dividing Equation 1.1 and Equation 1.2 gives the following equation:

Substituting the above formula 1.3 and formula 1.4 into formula 1.5 to obtain the ratio of the capacitance value of the first central area to the first edge area, specifically as follows:

Wherein, C _c1 represents the capacitance value of the first central region, C _c2 represents the capacitance value of the first edge region, and m represents the ratio of C _{total 1} to C _{total 2} .

In this embodiment, the capacitance values of the first semiconductor structure and the second semiconductor structure are respectively obtained through the above method, and at the same time, under the premise that the second semiconductor structure and the first semiconductor structure are prepared on the same wafer, the first central region The ratio of the capacitance value of the capacitance value to the capacitance value of the second central area, and the ratio of the capacitance value of the first edge area to the capacitance value of the second edge area, and according to the above values, the capacitance value of the first central area and the first The ratio of capacitance values in the edge region, the thickness uniformity of the active layer can be judged by the size of the ratio.

Embodiment two

An embodiment of the present disclosure also provides a measurement system for a semiconductor structure. As shown in FIG. 2 to FIG. The first gate oxide layer 130 and the first gate 140 on the first active layer 120, the projection of the first gate 140 on the first active layer 120 includes a first central region 150 and surrounding first central region 150 a first edge region 160;

The second semiconductor structure 200, and the second semiconductor structure 200 includes a second active layer 220 and a second gate oxide layer and a second gate 240 stacked on the second active layer 220, the second gate 240 is The projection on the second active layer 220 includes a second central area 250 and a second edge area 260 surrounding the second central area 250 .

The widths of the first central area 150 and the second central area 250 are different, and the widths of the first edge area 160 and the second edge area 260 are the same.

Processor, the processor is used to obtain the capacitance value C _{total 1} of the first semiconductor structure and the capacitance value C _{total 2} of the second semiconductor structure; obtain the ratio of the capacitance value of the first central region and the capacitance value of the second central region, and obtain The ratio of the capacitance value of the _first edge region to the capacitance value of the _second edge region; The ratio of the capacitance value of the first central region to the capacitance value of the second edge region is obtained to obtain the ratio of the capacitance value of the first central region to the capacitance value of the first edge region.

In this embodiment, the ratio of the capacitance value of the first central region of the first semiconductor structure to the capacitance value of the first edge region is obtained through the setting of the processor, and the thickness uniformity of the active layer is judged by the magnitude of the ratio, which is The preparation of the first semiconductor structure provides a theoretical basis.

In some embodiments, the detection module may include a first power module 300 , a first detection module 400 , a second power module 500 and a second detection module 600 .

The first power module 300 is connected to the first grid 140 for providing voltage to the first grid 140 .

The first detection module 400 is connected to the first active layer 120 and is used for measuring the amplitude and phase shift of the current flowing through the first gate and the first gate oxide layer.

The first grid 140 and the first power module 300 may be connected directly or indirectly. For example, as shown in FIG. 4 , a first connection wire 310 is provided between the first grid 140 and the first power module 300 .

In order to facilitate the connection between the first connecting wire 310 and the first grid 140 , a first pad 141 may be provided on the first grid 140 , and the first connecting wire 310 is connected to the first pad 141 .

It should be noted that when there are multiple first semiconductor structures 100, the multiple first semiconductor structures 100 are arranged in a matrix array. For example, as shown in FIG. 5, the number of first semiconductor structures 100 is nine The nine first semiconductor structures 100 are arranged in three rows and three columns.

The second power module 500 is connected to the second grid 240 for providing voltage to the second grid 240 .

The second detection module 600 is connected to the second active layer 220 and is used for measuring the amplitude and phase shift of the current flowing through the second gate 240 and the second gate oxide layer.

In order to facilitate the connection between the third connecting wire 510 and the second grid 240 , a third pad 241 may be provided on the second grid 240 , and the third connecting wire 510 is connected to the third pad 241 .

When the number of second semiconductor structures 200 can be multiple, a plurality of second semiconductor structures 200 are arranged in an array. For example, as shown in FIG. 6, the number of second semiconductor structures 200 is nine, and the nine second semiconductor structures 200 The structures 200 are arranged in three rows and three columns.

When forming the active layer, the active layer tends to form a structure that is thick in the middle and thin on both sides. Therefore, based on the above technical problems, this embodiment designs a semiconductor structure measurement system to measure the center area of the active layer. The ratio of the capacitance value to the capacitance value of the edge region, which is used to measure the thickness uniformity of the active layer.

Each embodiment or implementation manner in this specification is described in a progressive manner, each embodiment focuses on the differences from other embodiments, and the same and similar parts of each embodiment can be referred to each other.

In the description of this specification, descriptions referring to the terms "one embodiment", "some embodiments", "exemplary embodiments", "examples", "specific examples", or "some examples" etc. mean that the embodiments are combined Specific features, structures, materials, or characteristics described in or examples are included in at least one embodiment or example of the present disclosure.

In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the described specific features, structures, materials or characteristics may be combined in any suitable manner in any one or more embodiments or examples.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present disclosure, not to limit them; although the present disclosure has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: It is still possible to modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the technical solutions of the various embodiments of the present disclosure. scope.

Claims

A method for measuring a semiconductor structure, comprising the steps of:

A first semiconductor structure is provided, the first semiconductor structure includes a first active layer and a first gate oxide layer and a first gate stacked on the first active layer, and the first gate is on the first active layer The projection on the first active layer includes a first central area and a first edge area surrounding the first central area;

A second semiconductor structure is provided, the second semiconductor structure is prepared on the same wafer as the first semiconductor structure, and the second semiconductor structure includes a second active layer and is stacked on the second active layer A second gate oxide layer and a second gate on the second active layer, the second gate projects on the second active layer including a second central region and a second edge region surrounding the second central region; the first the lengths of the central area and the second central area are different, and the lengths of the first edge area and the second edge area are the same;

Acquiring the capacitance C 1 of the first semiconductor structure and the capacitance C 2 of the second semiconductor structure;

acquiring a ratio of the capacitance value of the first central region to a capacitance value of the second central region, and obtaining a ratio of the capacitance value of the first edge region to the capacitance value of the second edge region;

According to the C total 1 , the C total 2 , the ratio of the capacitance value of the first central area to the capacitance value of the second central area, and the capacitance value of the first edge area to the second edge The ratio of the capacitance value of the region is to obtain the ratio of the capacitance value of the first central region to the capacitance value of the first edge region.
The method for measuring a semiconductor structure according to claim 1, wherein the step of obtaining the capacitance Call1 of the first semiconductor structure and the capacitance Call2 of the second semiconductor structure comprises:

Acquiring the capacitance value between the first gate and the first active layer in the first semiconductor structure, the capacitance value is denoted as C 1 ;

Acquiring a capacitance value between the second gate and the second active layer in the second semiconductor structure, and the capacitance value is denoted as C 2 .
The method for measuring a semiconductor structure according to claim 2, wherein the capacitance value between the first gate and the first active layer in the first semiconductor structure is obtained, and the capacitance value is denoted as C 1 step, including:

providing a first power module, the first power module is connected to the first gate, and is used to provide a voltage to the first gate;

A first detection module is provided, the first detection module is connected to the first active layer, and is used to measure the amplitude and phase shift of the current flowing through the first gate and the first gate oxide layer;

According to the voltage value, the amplitude of the current and the phase offset, C total 1 is obtained.
The method for measuring a semiconductor structure according to claim 3, wherein,

The first power module is connected to the first gate through a first connecting wire;

The first detection module is connected to the first active layer through a second connecting wire.
The method for measuring a semiconductor structure according to claim 4, wherein there is a first pad between the first connection wire and the first gate, and the second connection wire is connected to the first active layer. There is a second pad in between.
The method for measuring a semiconductor structure according to claim 5, wherein there are multiple first semiconductor structures, and the multiple first semiconductor structures are arranged in an array;

The number of the first connecting wires is multiple, and each of the first connecting wires is connected to the first pads of the first semiconductor structures on the same row;

The number of the second connecting wires is multiple, and each of the second connecting wires is connected to the second pads of the first semiconductor structures on the same row.
The method for measuring a semiconductor structure according to claim 6, wherein when the number of the first semiconductor structures is multiple, and the multiple first semiconductor structures are arranged in an array, the measurement of the first semiconductor structure is obtained. The steps of capacitance value C total 1 include:

acquiring a total capacitance value between the first active layer and the first gate of a plurality of the first semiconductor structures;

According to the total capacitance value between the first active layer of the first semiconductor structure and the first gate, the first active layer and the first gate of the first semiconductor structure are obtained. An average of the capacitance values between the gates, this average value is taken as C 1 .
The method for measuring a semiconductor structure according to claim 2, wherein the step of obtaining the capacitance value between the second gate and the second active layer in the second semiconductor structure comprises:

providing a second power module, the second power module is connected to the second grid, and is used to provide a voltage to the second grid;

A second detection module is provided, the second detection module is connected to the second active layer, and is used to measure the amplitude and phase shift of the current flowing through the second gate and the second gate oxide layer;

According to the voltage value, the amplitude of the current and the phase offset, C total 2 is obtained.
The method for measuring a semiconductor structure according to claim 8, wherein the second power module is connected to the second gate through a third connecting wire;

The second detection module is connected to the second active layer through a fourth connection wire.
The method for measuring a semiconductor structure according to claim 9, wherein there is a third pad between the third connection wire and the second gate, and the fourth connection wire and the second active layer There is a fourth pad in between.
The method for measuring a semiconductor structure according to claim 10, wherein there are multiple second semiconductor structures, and the multiple second semiconductor structures are arranged in an array;

The number of the third connecting wires is multiple, and each of the third connecting wires is connected to the third pads of the second semiconductor structures on the same row;

The number of the fourth connecting wires is multiple, and each of the fourth connecting wires is connected to the fourth pads of the second semiconductor structures on the same row.
The method for measuring a semiconductor structure according to claim 11, wherein when the number of the second semiconductor structures is multiple, and the plurality of second semiconductor structures are arranged in an array, the The step of the capacitance value between the second grid and the second active layer, comprising:

acquiring a total capacitance value between the second active layer and the second gate of a plurality of the second semiconductor structures;

According to the total capacitance between the second active layer and the second gate of the plurality of second semiconductor structures, the relationship between the second active layer and the second gate of the second semiconductor structure is obtained. The average value of the capacitance value between, this average value is taken as C total 2 .
The method for measuring a semiconductor structure according to any one of claims 2-12, wherein the ratio of the capacitance value of the first central region to the capacitance value of the second central region is obtained, and the second edge is obtained In the step of the ratio of the capacitance value of the region to the capacitance value of the second edge region, comprising:

Along the first direction, the widths of the first central region and the first edge region are both A;

Along the second direction, the length of the first central region is a, the length of the first edge region is A-a, the area of the first central region is A×a, and the area of the first edge region is A ×(A-a);

Along the first direction, the widths of the second central region and the second edge region are both nA;

Along the second direction, the length of the second central region is (n-1)A+a, the length of the second edge region is A-a, and the area of the second central region is [(n-1 )A+a]×nA, the area of the second edge region is nA(A-a);

The ratio of the capacitance value of the first central area to the capacitance value of the second central area is

The ratio of the capacitance value of the first edge region to the capacitance value of the second edge region is
The method for measuring a semiconductor structure according to claim 13, wherein the ratio of the capacitance value of the first central region to the capacitance value of the first edge region is obtained by the following formula:

Wherein, C c1 represents the capacitance value of the first central area, C 2 represents the capacitance value of the first edge area, and m represents the ratio of C total 1 to C total 2 .
The method for measuring a semiconductor structure according to any one of claims 1-12, wherein the first central region includes a first edge and a second edge that are oppositely arranged;

The first edge region includes a first region and a second region, the first region is arranged in close contact with the first edge, and the second region is arranged in contact with the second edge;

The capacitance value of the first edge region is equal to the sum of the capacitance value of the first region and the capacitance value of the second region.
A measurement system for a semiconductor structure comprising:

A first semiconductor structure, the first semiconductor structure includes a first active layer and a first gate oxide layer and a first gate stacked on the first active layer, the first gate is on the first active layer The projection on the first active layer comprises a first central area and a first edge area surrounding said first central area;

a second semiconductor structure, and the second semiconductor structure includes a second active layer and a second gate oxide layer and a second gate stacked on the second active layer, and the second gate is on the second active layer The projection on the second active layer includes a second central area and a second edge area surrounding the second central area;

The first central area and the second central area have different widths, and the first edge area and the second edge area have the same width;

A processor, the processor is used to obtain the capacitance value C total 1 of the first semiconductor structure and the capacitance value C total 2 of the second semiconductor structure; obtain the capacitance value of the first central region and the capacitance value of the second semiconductor structure The ratio of the capacitance value of the central area, and the ratio of the capacitance value of the first edge area to the capacitance value of the second edge area; and according to the C total 1 , the C total 2 , the first The ratio of the capacitance value of the central area to the capacitance value of the second central area and the ratio of the capacitance value of the first edge area to the capacitance value of the second edge area are obtained to obtain the capacitance value of the first central area and the ratio of the capacitance value of the first edge region.
The measurement system for semiconductor structures according to claim 16, wherein the processor includes a first power supply module, a first detection module, a second power supply module, and a second detection module;

The first power module is connected to the first grid, and is used to provide voltage to the first grid;

The first detection module is connected to the first active layer, and is used to measure the amplitude and phase shift of the current flowing through the first gate and the first gate oxide layer;

The second power module is connected to the second grid, and is used to provide voltage to the second grid;

The second detection module is connected to the second active layer, and is used for measuring the amplitude and phase shift of the current flowing through the second gate and the second gate oxide layer.
The measurement system for semiconductor structures according to claim 17, wherein, the first power supply module is connected to the first gate through a first connection wire; the first detection module is connected to the first active gate through a second connection wire. source connection;

The second power supply module is connected to the second gate through a third connection wire; the second detection module is connected to the second active layer through a fourth connection wire.
The measurement system for a semiconductor structure according to claim 18, wherein the number of the first semiconductor structures is multiple, and the plurality of first semiconductor structures are arranged in a rectangular array;

The number of the first connecting wires is multiple, and each of the first connecting wires is connected to the first gates of the first semiconductor structures located in the same row;

The number of the second connecting wires is multiple, and each of the second connecting wires is connected to the first active layer of the first semiconductor structure on the same row.
The measurement system for semiconductor structures according to claim 18, wherein the number of the second semiconductor structures is multiple, and the multiple second semiconductor structures are arranged in a rectangular array;

The number of the third connecting wires is multiple, and each of the third connecting wires is connected to the second gates of the second semiconductor structures on the same row;

The number of the fourth connecting wires is multiple, and each of the fourth connecting wires is connected to the second active layer of the first semiconductor structure on the same row.