WO2019132890A1

WO2019132890A1 - Ferroelectric memory devices with integrated capacitors and methods of manufacturing the same

Info

Publication number: WO2019132890A1
Application number: PCT/US2017/068562
Authority: WO
Inventors: Ian Young; Uygar AVCI; Daniel Morris
Original assignee: Intel Corporation
Priority date: 2017-12-27
Filing date: 2017-12-27
Publication date: 2019-07-04

Abstract

Ferroelectric memory devices with integrated capacitors and methods of manufacturing the same. An example memory device includes a semiconductor fin, and a transistor associated with a first portion of the semiconductor fin. The memory device further includes a ferroelectric capacitor adjacent the transistor. A second portion of the semiconductor fin including a doped region corresponds to an electrode of the ferroelectric capacitor.

Description

FERROELECTRIC MEMORY DEVICES WITH INTEGRATED CAPACITORS AND METHODS OF MANUFACTURING THE SAME

FIELD OF THE DISCLOSURE

[0001] This disclosure relates generally to memory devices and, more particularly, to ferroelectric memory devices with integrated capacitors and methods of manufacturing the same.

BACKGROUND

[0002] Many memory devices include a matrix or array of individual memory cells arranged in rows and columns. The memory cells in each row are connected to a conductive line referred to as a wordline. The memory cells in each column are connected to a conductive line referred to as a bitline. Thus, each memory cell is associated with a particular intersection of one bitline and one wordline. By controlling the voltages applied along individual ones of the bitlines and wordlines, information (e.g., individual bits) may be stored or read from the corresponding memory cells.

[0003] There are different ways to implement memory cells. For instance, a memory cell for dynamic random access memory (DRAM) is typically implemented using one transistor and one capacitor. For this reason, DRAM cells are sometimes referred to as 1T-1C cells. In recent years, some research has begun focusing on using ferroelectric materials in memory cells. Ferroelectric random access memory (FeRAM) cells are typically 1T-1C cells similar to DRAM cells except that a ferroelectric material is used between the capacitor electrodes rather than a dielectric material.

BRIEF DESCRIPTION OF THE DRAWINGS

[0004] FIG. 1 is a schematic illustration of a single 1T-1C memory cell that includes one transistor and one capacitor.

[0005] FIG. 2A is top view of an example memory array constructed in accordance with the teaching of this disclosure. [0006] FIG. 2B is a cross-sectional view of the example memory array of FIG. 2A taken along line B-B.

[0007] FIG. 2C is a cross-sectional view of the example memory array of FIG. 2A taken along line C-C.

[0008] FIG. 2D is a cross-sectional view of the example memory array of FIG. 2A taken along line D-D.

[0009] FIG. 3A-3D, 4A-4C, 5A-5C, 6A-6C, 7A-7C, and 8A-8C illustrate stages in an example method of manufacturing the example memory array of FIGS. 2A-2D.

[0010] FIG. 9 is a flowchart representative of an example method of manufacturing the example memory array of FIGS. 2A-2D.

[0011] FIG. 10 is a top view of a wafer and dies that may include a memory array, in accordance with any of the examples disclosed herein.

[0012] FIG. 11 is a cross-sectional side view of an integrated circuit (IC) device that may include a memory cell, in accordance with any of the examples disclosed herein.

[0013] FIG. 12 is a cross-sectional side view of an IC package that may include a memory cell, in accordance with various examples.

[0014] FIG. 13 is a cross-sectional side view of an IC device assembly that may include a memory cell, in accordance with any of the examples disclosed herein.

[0015] FIG. 14 is a block diagram of an example electrical device that may include a memory cell, in accordance with any of the examples disclosed herein.

[0016] The figures are not to scale. Instead, the thickness of the layers or regions may be enlarged in the drawings. In general, the same reference numbers will be used throughout the drawing(s) and accompanying written description to refer to the same or like parts. As used in this patent, stating that any part (e.g., a layer, film, area, region, or plate) is in any way on (e.g., positioned on, located on, disposed on, or formed on, etc.) another part, indicates that the referenced part is either in contact with the other part, or that the referenced part is above the other part with one or more intermediate part(s) located therebetween. Stating that any part is in contact with another part means that there is no intermediate part between the two parts.

DETAILED DESCRIPTION

[0017] FIG. 1 is a schematic illustration of a 1T-1C memory cell 100 that includes one access transistor 102 and one capacitor 104. Such 1T-1C cells are typically implemented by electrically connecting a gate 106 of the transistor 102 to a wordline 108 of a memory array. A first terminal or electrode 110 of the capacitor 104 is electrically connected to one side (source or drain) of the transistor 102 while the other side of the transistor 102 is electrically connected to a bitline 112 of the memory array. The second electrode 114 of the capacitor 104 is connected to a third line 116 referred to herein as the capacitor line. Often, the capacitor line 116 is connected to a constant voltage (e.g., a VDD/2 voltage).

[0018] The 1T-1C memory cell 100 may store data (e.g., a logic 0 or logic 1) based on the electric charge (or lack thereof) in the capacitor 104. In the typical approach used for DRAM, the first and second electrodes 110 of the capacitor 104 are separated by a dielectric material. A similar construction of the memory cell 100 may alternatively include a ferroelectric material between the first and second electrodes 110 of the capacitor 104. A capacitor incorporating the ferroelectric material between its electrodes is referred to herein as a ferroelectric capacitor. The memory cell 100 implemented with a ferroelectric capacitor may store data (e.g., a logic 0 or logic 1) based on the electric polarization (e.g., positive or negative) of the ferroelectric material. A charge resulting from a change in the polarization may be sensed at the bitline 112 when the transistor 102 is turned on via the wordline 108 and a voltage is applied across the ferroelectric material, thereby enabling the data stored in the capacitor to be read.

[0019] Ferroelectric materials exhibit a nonlinear electric polarization under the application of an external electric field that can be reversed with an electric field applied in the opposite direction. Furthermore, ferroelectric materials retain at least some polarization (e.g., a remnant polarization) even when the electric field is removed. These properties make ferroelectric materials a candidate for embedded memory technology (e.g., memory integrated into a semiconductor chip). Further, ferroelectric materials may be used for non-volatile memory or dense high-performance memory (e.g., enhanced dynamic random access memory (eDRAM)).

[0020] Currently, ferroelectric capacitors are formed during back-end- of-line processes. Generally speaking, semiconductor device fabrication can be broadly separated into two sequential phases including (1) front-end-of-line (FEOL) processing, and (2) back-end-of-line (BEOL) processing. FEOL processing typically involves the formation of individual transistors on a semiconductor substrate (e.g., a silicon wafer). BEOL processing involves the formation of metal wiring to interconnect the transistors previously formed on the substrate. The types of processes available to form the metallization layers (e.g., the metal wiring to interconnect separate transistors) during the BEOL are relatively limited. In particular, the BEOL fabrication is typically limited to processes that do not exceed temperatures of around 400°C because the BEOL materials (e.g., the metal wiring) begin to degrade at higher

temperatures. The thermal limitations of BEOL processes may deleteriously impact the formation of ferroelectric capacitors because they limit the anneal temperatures that may be used to improve (e.g., optimize) the properties of the ferroelectric capacitor. Furthermore, forming ferroelectric capacitors during the BEOL limits integration of such capacitors with state-of-the-art complementary metal-oxide-semiconductor (CMOS) technology. As a result of these problems, the standard approach is to not integrate ferroelectric memory devices at all, but to instead fabricate stand-alone memory on separate semiconductor dies. Stand-alone memory is not suitable for certain types of electrical devices and can come with a cost to performance and power consumption when compared with embedded (integrated) memory technology.

[0021] Examples disclosed herein enable the fabrication of ferroelectric capacitors before the BEOL processing (e.g., during the FEOL or after the end of typical FEOL processes). In some examples, ferroelectric capacitors are integrated with associated transistors on a common surface of a single semiconductor substrate. More particularly, in some examples, ferroelectric capacitors are formed on the sidewall of a semiconductor fin that is also used to form associated transistors. Forming the capacitor at this stage of processing removes the effect of high-temperature anneals performed on ferroelectric materials formed during the BEOL, thereby enabling ferroelectric capacitors with improved properties for enhanced performance while also improving the performance of BEOL interconnects. In addition, processing the ferroelectric capacitor at a FEOL level removes the uniformity issues with BEOL interconnects that may otherwise result from the capacitor being formed on the same level as the BEOL interconnects. Furthermore, the integration of ferroelectric capacitors on the same die as transistors enables the integration of ferroelectric memory with high performance processors, thereby improving the performance of both the memory and the processor.

[0022] FIG. 2A is top view of an example memory array 200 constructed in accordance with the teaching of this disclosure. FIG. 2B, 2C, and 2D are cross-sectional views of the example memory array 200 of FIG.

2A taken along line B-B, line C-C, and line D-D, respectively. The illustrated example includes four individual bitcells or memory cells 202, 204, 206, 208 demarcated by dashed lines. In the illustrated example, two of the memory cells 202, 204 (at the top of FIG. 2A) are formed on a first semiconductor fin 210 and the other two memory cells 206, 208 (at the bottom of FIG. 2A) are formed on a second semiconductor fin 212. Each of the memory cells 202, 204, 206, 208 includes a corresponding access transistor 214 and a corresponding ferroelectric capacitor 216 that are adjacent one another on the corresponding fins 210, 212.

[0023] The fins 210, 212 are not visible in FIG. 2 A because the transistors 214 and capacitors 216 are formed on and, thus, cover a top surface 218 (FIGS. 2B, 2C, and 2D) of the fins 210, 212. More particularly, each of the transistors 214 includes a gate conductor 220 with first and second contact regions 222, 224 positioned on either side of the gate conductor 220. The contact regions 222, 224 are associated with the source and drain of the transistor 214. In this example, the first contact region 222 is farther away from the capacitor 216 than the gate conductor 220. By contrast, the second contact region 222 is closer to the capacitor 216 than the gate conductor 220. That is, the second contact region 224 is positioned between the gate conductor 220 and the capacitor 216. The gate conductor 220 may be any suitable metal (e.g., aluminum (Al), tungsten (W), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), etc.) or a layered stack of two or more different metals.

[0024] As shown in FIG. 2B, the first and second contact regions 222, 224 are respectively positioned over corresponding doped regions 228, 230 within the fins 210, 212. The space between the first contact region 222 of the adjacent fins 210, 212 shown in FIG. 2A is filled with shallow trench isolation (STI) material 232. Similarly, the space between the second contact region 224 of the adjacent fins 210, 212 is filled with the STI material 232. The STI material 232 may be formed of any suitable dielectric (e.g., silicon dioxide (S1O2)).

[0025] The gate conductor 220 may be separated from the contact regions 222, 224 by a spacer 226. In this example, the spacer 226 lines the lateral sides of the gate conductor 220 (and, therefore, is not shown in the cross-sectional views of FIGS. 2C and 2D). The spacer 226 may be formed from any suitable dielectric material (e.g., an oxide). Further, the gate conductors 220 are separated from their respective fins 210, 212 by gate dielectric 234 as shown in FIGS. 2B and 2C. The gate dielectric 234 may be formed of silicon dioxide (S1O2) or any other suitable high-K dielectric material such as, for example, alumina (AI2O3), hafhia (FlfC ), zirconia (ZrC ), silicon nitride (S13N4), etc. As illustrated in FIG. 2C, the gate dielectric 234 not only separates the gate conductor 220 from the fins 210, 212 at the top surface 218 of the fins but also down a portion of sidewalls 238 of the fins 210, 212. The spaces between the fins 210, 212 below the gate dielectric 234 shown in FIG. 2C are filled with the STI material 232.

[0026] As illustrated in FIGS. 2A, 2B, and 2D, the respective ferroelectric capacitors 216 of the memory cells 202, 204, 206, 208 include a first terminal or electrode 236 that surrounds the top surface 218 and portions of the sidewalls 238 of the corresponding semiconductor fin 210, 212. In some examples, the first electrodes 236 of the capacitors 216 are separated from the second contact regions 224 by spacers 226 similar to the spacers 226 described above that extend along the lateral sides of the transistors 214.

[0027] The portion of the fins 210, 212 associated with the capacitors 216 include deep doped regions 240. That is, the deep doped regions 240 are in alignment with the ferroelectric material 244 and the first electrode 236 along the length of the fins 210, 212. As shown in FIG. 2B, the deep doped regions 240 are adjacent the ones of the doped regions 230 associated with the transistors 214. In some examples, the deep doped regions 240 are in contact with or overlap with the doped regions 230. In some examples, the deep doped regions 240 are doped similarly to the doped regions 230 such that different doped regions 240 are effectively extension of one another. In some examples, while the dopant in both doped regions 230, 240 may be the same, the concentration of the dopant in each region may be different than the other. In some examples, the deep doped regions 240 extend deeper into the semiconductor fins 210, 212 than the doped region 228, 230 associated with the source and drain of the transistors 214. In some examples, the deep doped regions 240 extend at least twice the depth of the doped region 228, 230 associated with the source and drain of the transistors 214. In some examples, the deep doped regions 240 extend much more than twice the depth of the other doped regions 228, 230 (e.g., three times the depth, five times the depth, ten times the depth, etc.).

[0028] In some examples, the doped regions 240 are highly doped (e.g., via implantation) with any suitable material to make the deep doped regions 240 electrically conductive. For instance, in some examples, where the transistors 214 are NMOS transistors, the dopant used in the deep doped regions 240 is at least one of phosphorus (P), antimony (Sb), or arsenic (As). Where the transistors 214 are PMOS transistors, the dopant used in the deep doped regions 240 may be at least one of boron (B), aluminum (Al), or gallium (Ga). As used herein,“highly doped” refers to a dopant concentration of at least 5el9 atoms/cm³. In some examples, the dopant concentration ranges from 5el9 atoms/cm³ and le2l atoms/cm³. In some examples, a dosage of the dopant during implantation is provided in the range of at least lel3 atoms/cm² to lel5 atoms/cm² implanted with up to 30kV of energy. Doping the semiconductor fins 210, 212 in this manner enables the deep doped regions 240 of the fins to serve as the second electrode 242 for the capacitors 216.

[0029] To properly function as a ferroelectric capacitor, the first and second electrodes 236, 242 are separated by a ferroelectric oxide material 244 as shown in FIGS. 2B and 2D. In some examples, the conductive material used for the first electrode 236 is titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), aluminum (Al), tungsten (W), and/or any other suitable metal. The ferroelectric material 244 may be formed of barium titanate (BaTiCh), Bismuth ferrite (BiFeCb), Europium titanate (EU2T13O9), or hafnium oxide HfOx) doped with materials including, for example, at least one of zirconium (Zr), silicon (Si), yttrium (Y), germanium (Ge), nitrogen (N), or aluminum (Al).

[0030] As shown in the illustrated examples, the first electrodes 236 and the associated ferroelectric material 244 of the capacitors 216 are similar in structure to the gate conductors 220 and the associated gate dielectric 234 of the transistors 214. As a result, as described more fully below, the processes used to create the capacitors 216 are similar to those used in forming the transistors 214, thereby facilitating the integration of the separate components. A difference between the structures of the gate conductors 220 (and the associated gate dielectric 234) and the first electrodes 236 (and the associated ferroelectric material 244) is the distance or depth each extends down the sidewalls 238 of the fins 210, 212. In particular, as shown by a comparison of FIGS. 2C and 2D, the first electrode 236 (and the ferroelectric material 244) extends a farther distance down the sidewalls 238 than the gate conductor 220 (and the gate dielectric 234). In some examples, the first electrode 236 extends approximately the same depth as the deep doped region 240, corresponding to the second electrode 242. Extending both the first and second electrodes 236, 242 farther into the fins 210, 212 increases the total surface area of the first and second electrodes 236, 242 that face one another (separated by the ferroelectric material 244). In this manner, the capacitance of the capacitor 216 is increased because capacitance is proportional to the surface area of the electrodes. Although the first and second electrodes 236, 242 are shown as having substantially the same depth in FIG. 2D, in other examples, either one of the first or second electrodes 236, 242 may extend deeper than the other. The space between the fins 210, 212 and below the ferroelectric material 244 shown in FIG. 2D is filled with the STI material 232.

[0031] In the illustrated examples, the gate conductors 220 of the individual transistors 214 correspond to and/or are integrated with a corresponding wordline 246 of the memory array 200. As shown, the wordlines 246 include a conductive material that extends across multiple transistors 214 positioned on adjacent fins 210, 212 to serve as the gate conductor 220 for each transistor 214 associated with the wordline. Similarly, in the illustrated examples, the first electrodes 236 of the individual capacitors 216 correspond to and/or are integrated with a corresponding capacitor line 248. As shown, the capacitor lines 248 include a conductive material that extends across multiple capacitors 216 on adjacent fins 210, 212 to serve as the first electrode 236 for each capacitor 216 associated with the capacitor line. Because a number of capacitors are attached to a same wordline, multiple capacitors can be read simultaneously to access bits of data in any desired number (e.g., 8 bits, 32 bits, 64 bits, etc.).

[0032] In some examples, separate bitlines of the memory array 200 are oriented to extend in alignment with the fins 210, 212. The stage of fabrication of the memory array 200 shown in FIGS. 2A-2D is before conductive metal for the bitline has been deposited. More particularly, bitlines may extend in alignment with the fins 210, 212 in a metal layer formed above the transistors 214 and capacitors 216 shown in the illustrated examples. In such examples, the transistors 214 on a particular fin 210, 212 (associated with a particular bitline) are electrically connected to the bitline via metal contacts formed on the first contact region 222 adjacent the gate conductor 220 on the side farthest away from the corresponding capacitor 216.

[0033] As shown in the illustrated example, individual memory cells 202, 204, 206, 208 that are adjacent one another on separate fins 210, 212 (e.g., the first and third memory cells 202, 206 of the second and fourth memory cells 204, 208) are oriented in a same direction. In this manner, the transistor 214 and capacitor 216 of a given memory cell respectively aligns with the transistors 214 and capacitors 216 of the adjacent memory cells along corresponding wordlines 246 and capacitor lines 248. That is, while two of the memory cells 202, 204, 206, 208 correspond to each of the wordlines 246 in the illustrated example, additional memory cells may be associated with the same wordline. In such examples, the additional memory cells may be oriented on additional fins in the same manner as the memory cells 202, 204, 206, 208 shown in the illustrated examples. In other words, in some examples, the memory array 200 of FIG. 2A may be extended either up or down relative to the view shown in FIG. 2A by repeating the portion of the memory array 200 represented in the figure.

[0034] By contrast, individual memory cells that are adjacent one another on the same fin 210, 212 (associated with a single bitline) are oriented in a reverse direction relative to one another so that the relative position of the transistor 214 and capacitor 216 for each memory cell is opposite that of the adjacent memory cells. In this manner, any two adjacent memory cells 202, 204, 206, 208 on a single fin 210, 212 may have either their respective transistors 214 proximate one another (with their capacitors 216 farther apart) or their respective capacitors 216 proximate one another (with their transistors 214 father apart). Thus, as shown in FIGS. 2A and 2B, the capacitors 216 of the adjacent memory cells 202, 204, 206, 208 on the same fin 210, 212 are proximate one another with the corresponding transistors 214 farther apart. As shown in the figures, the capacitors 216 of the adjacent memory cells 202,

204, 206, 208 that are proximate one another are separated by an isolation material 250. In some examples, as shown in FIG. 2B, the isolation material 250 extends into a trench cut into the fin 210 to a depth greater than the depth of the deep doped regions 240 to electrically isolate the separate capacitors 216. The isolation material 250 may be formed of any suitable dielectric material (e.g., an oxide). In some examples, the isolation material 250 is made of the same material as the STI material 232.

[0035] While two of the memory cells 202, 204, 206, 208 are aligned on each of the fins 210, 212 (associated with a corresponding bitline) in the illustrated example, additional memory cells may be positioned on either fin (e.g., either to the left or right of the drawings in FIGS. 2A and 2B). In such examples, the next adjacent memory cells on either side of the memory cells 202, 204, 206, 208 shown in the illustrated examples are oriented so that their transistors 214 are proximate to the transistors 214 shown in FIGS. 2A and 2B. In other words, in some examples, the memory array 200 of FIG. 2A may be extended to the left, the right, or both the left and right of the view shown in FIG. 2A by repeating the portion of the memory array 200 represented in the figure. Unlike the proximate capacitors 216, which are separated by the isolation material 250, there is no need to isolate transistors 214 that are proximate one another on the same semiconductor fin because both transistors 214 are associated with the same bitline. That is, signals for both transistors 214 are carried on the same bitline. However, the bitline signals for each transistor 214 occur at different times by selectively energizing the different wordlines associated with each of the transistors at different times. In some examples, two proximate transistors 214 on the same fin may share a common first contact region 222 positioned over a single one of the first doped regions 228. In such examples, a single metal contact on the first contact region 222 may serve to connect two transistors 214 associated with two separate memory cells on two separate wordlines 246 to the associated bitline. The bitline is formed in a subsequent metal layer above the corresponding fin.

[0036] FIGS. 3A-3D, 4A-4C, 5A-5C, 6A-6C, 7A-7C, and 8A-8C illustrate stages in an example method of manufacturing the example memory array 200 of FIGS. 2A-2D. FIG. 3 A is top view of an example transistor array 300 used as the basis to manufacture the example memory array of FIG. 2A. FIGS. 3B, 3C, and 3D are cross-sectional views of the example transistor array of FIG. 3 A taken along the line B-B, line C-C, and line D-D

respectively. FIGS. 3A-3D correspond to the views of FIGS. 2A-2D except at an earlier stage of the manufacturing process. In particular, FIGS. 3A-3D represent the array at the end of standard FEOL processes at a time before BEOL processes have begun. As described above, FEOL processes proceed up to the formation of transistors, such as the transistors 214 corresponding to the wordlines 246 of FIGS. 2A-2D. The transistor array 300 shown in FIG.

3A includes additional transistors 302 that are not positioned in line with the wordlines 246. Rather, the additional transistors 302 are positioned in the place where the ferroelectric capacitors 216 of FIG. 2A are to be subsequently formed.

[0037] The primary difference between the transistors 214 associated with the wordlines 246 of FIG. 2A and the additional transistors 302 not associated with the wordlines 246 is that the additional transistors 302 are intended to be sacrificial or temporary. That is, although structurally similar to the other transistors 214, the additional (sacrificial) transistors 302 merely serve as placeholders for the subsequent fabrication of ferroelectric capacitors as described in greater detail below. For purposes of explanation, the transistors 214 associated with the wordlines 246 are referred to herein as wordline transistors, whereas the additional transistors 302 are referred to as sacrificial transistors. In the illustrated examples, the sacrificial transistors 302 have the same structure as the wordline transistors 214 and are formed at the same time using the same materials and the same processes. Thus, at the point in time of the manufacturing process represented in FIGS. 3A-3D, each of the transistors 214, 302 includes a corresponding gate conductor 220 that is separated from the corresponding fin 210, 212 by the gate dielectric 234. Further, the gate conductor 220 is separated from first and second contact regions 222, 224 by spacer(s) 226. As shown in the illustrated examples, the first and second contact regions 222, 224 are positioned on corresponding first and second doped regions 228, 230.

[0038] While all of the transistors 214, 302 in the illustrated example are described as being formed at the same time using the same materials and the same processes, this may not always be the case. For instance, in some examples, the sacrificial transistors 302 may be formed in separate processes (at separate times) using different materials than the wordline transistors 214. Different materials may be used for the sacrificial transistors 302 to facilitate their subsequent removal.

[0039] FIG. 4A is a cross-sectional view corresponding to the example transistor array 300 shown in FIG. 3B except that the gate conductor 220 and gate dielectric 234 associated with the sacrificial transistors 302 have been removed via one or more lithographic processes. FIGS. 4B and 4C are cross- sectional views of the example transistor array 300 of FIG. 4A taken along the line B-B and the line CC, respectively. More particularly, FIGS. 4A-4C represent the application of a hard mask 402 over the transistors 214, 302 that is patterned to expose the sacrificial transistors 302 while protecting the wordline transistors 214. As shown in FIG. 4A, the hard mask 402 is open for two pitches and remains for two pitches on either side of the opening. As used herein, a pitch refers to the distance between two consecutive transistors along a fin. Therefore, the lithography is less dense than every pitch and, therefore, may be accomplished with relative ease (as compared with lithography that involves separate openings at every pitch). Furthermore, the lithographic processes involved in patterning the hard mask 402 are self-aligning by the first and second contact regions 222, 224. Thus, the lithography does not need to precisely define an opening corresponding to the area to be etched (i.e., the sacrificial gate conductor 220), but may define the opening to have edges that are anywhere above the second contact regions 224. Subsequent to the application of the hard mask 402, the gate conductor 220 and the gate dielectric 234 associated with sacrificial transistors 302 are removed (e.g., via etching). Thus, as shown in FIG. 4C, the STI material 232 underneath the gate dielectric 234 becomes exposed.

[0040] FIG. 5A is a cross-sectional view corresponding to the example transistor array 300 of FIG. 4A after additional processing has occurred. FIGS. 5B and 5C are cross-sectional views of the example transistor array 300 of FIG. 5A taken along the line B-B and the line CC, respectively. In particular, as shown in FIG. 5C, the STI material 232 that was exposed with the removal of the gate conductor 220 and gate dielectric 234 of the sacrificial transistors 302 is etched down to expose a larger portion of the fins 210, 212 at that location. In some examples, the STI material 232 is etched down to the depth shown in FIG. 5C during the same etching process used to remove the gate conductor 220 and gate dielectric 234 represented in FIG. 4C. That is, in some examples, the STI material 232 is removed during an over-etching of the sacrificial gate conductor 220 and gate dielectric 234 disposed on the STI material 232. In other examples, the etching of the STI material 232 is accomplished through a different etching procedure. FIGS. 5A-5C also represent the formation of the deep doped regions 240, which is accomplished by doping (e.g., via implantation) the exposed portion of the fins 210, 212. With the fins 210, 212 being highly doped, the deep doped regions 240 are capable of functioning as electrical conductors and, thus, may serve as the second electrode 242 for the ferroelectric capacitors 216.

[0041] With the second electrode 242 for the ferroelectric capacitors 216 formed, the rest of the capacitor may be formed as represented in FIGS. 6A-6C. In particular, FIG. 6A is a cross-sectional view of the example transistor array 300 of FIG. 5 A after depositing the ferroelectric material 244 and then the material for the first electrode 236 of the capacitors 216 over the deep doped regions 240 of the fins 210, 212. FIGS. 6B and 6C are cross- sectional views of the example transistor array 300 of FIG. 6A taken along the line B-B and the line C-C, respectively. In some examples, depending on the annealing time and the ramp-up of the furnace temperature, the ferroelectric material 244 undergoes an annealing process after being deposited to improve its characteristics for the capacitor 216. In some examples, the annealing process involves the application of temperatures ranging from approximately 400°C up to approximately 900°C. Such temperatures are not available during BEOL processes because they may degrade metal interconnects. However, the temperatures involved in annealing are an issue in this example because the annealing occurs prior to any metal interconnects being added. [0042] FIGS. 6A-6C further represent the removal of the hard mask 402 and any excess conductive material deposited for the first electrode 236. In some example, removal of the hard mask 402 involves a polishing procedure to remove the conductive material of the first electrode 236 deposited on the surface of the hard mask 402. Thereafter, the hard mask 402 may be removed via etching. Finally, in some examples, a second polishing process may be implemented to remove the excess conductive material that filled the opening in the hard mask 402. In this manner, the top surface of the capacitors 216 will be made substantially even or coplanar (e.g., within 10 nanometers) with the top surface of the transistors 214 as shown in the illustrated examples. Alternatively, the excess conductive material within the opening of the hard mask 402 may be removed first using a timed etching. Thereafter, a polishing process may remove the conductive material deposited on the hard mask 402 followed by etching of the hard mask 402. This alternative approach does not need a second polishing process because the timed etching will have reduced the top surface of the capacitors 216 to be generally even with the top surface of the transistors 214 as shown in the illustrated examples.

[0043] Although the structure for the capacitors 216 are completely formed at the stage of manufacture represented in FIGS. 6A-6C, the adjacent capacitors 216 still need to be isolated from one another. Accordingly, FIG. 7A is a cross-sectional view of the example transistor array 300 of FIG. 6A after etching a trench 702 in the fins 210, 212 between the deep doped regions 240 associated with adjacent capacitors 216. FIGS. 7B and 7C are cross- sectional views of the example transistor array 300 of FIG. 7A taken along the line B-B and the line C-C, respectively. The trench 702 is formed through the implementation of a second lithographic process. In particular, a second hard mask 704 is applied and patterned to cover the wordline transistors 214 and the capacitors 216 except for the area between proximate capacitors 216 that remains exposed for subsequent processing as shown in the illustrated example of FIGS. 7A-7C. This lithographic process involves openings that are only a single pitch wide making the process somewhat more difficult than the first lithographic process discussed in connection with FIGS. 4A-4C. However, the lithographic process of FIGS. 7A-7C is self-aligning by the first electrodes 242 of the adjacent capacitors 216, thereby making the process easier to implement. That is, the region to be etched is defined by the edges of the two adjacent electrodes 242 such that the boundary for the opening of the hard mask 704 does not need to be exact but merely positioned at some location on the electrodes 240 as shown in FIG. 7A. Furthermore, while the opening is one pitch wide, separate openings are spaced four pitches apart such that the lithographic process has a relatively low density.

[0044] FIGS. 7A-7C further represent the removal (e.g., via etching) of contact region 222 in the exposed area between the capacitors 216 as well as the fin 210, 212 underneath the contact region 222 to form the trench 702. Additionally, the spacer 226 in the exposed area adjacent the capacitors 216 may also be etched away. As shown in FIG. 7A, the trench 702 is etched to a greater depth into the fins 210, 212 than the depth of the deep doped regions 240.

[0045] FIG. 8A is a cross-sectional view of the transistor array 300 of FIG. 7A after depositing the isolation material 250 within the trench 702 of FIG. 7A. FIGS. 8B and 8C are cross-sectional views of the example transistor array 300 of FIG. 8A taken along the line B-B and the line C-C, respectively. FIGS. 8A-8C also represent the removal (e.g., via etching) of the second hard mask 704 to complete the fabrication of the memory array 200 of FIGS. 2A- 2D. That is, FIGS. 8A-8C represent the same stage in the manufacturing process as represented by FIGS. 2A-2D. In some example, removal of the hard mask 704 involves a polishing procedure to remove the isolation material 250 that was deposited on the hard mask 402. Thereafter, the hard mask 704 may be removed via etching. In some examples, a second polishing process may be implemented to make the top surface of the isolation material 250 even with the capacitors 216.

[0046] After forming the example memory array 200 of FIGS. 2A-2D (and FIGS. 8A-8C), standard processes associated with the BEOL may be implemented to add metal contacts and metal layers as is known in the art. Thus, all of the processes described in connection with FIGS. 3A-3D, 4A-4C, 5A-5C, 6A-6C, 7A-7C, and 8A-8C may be performed before being subject to the limitations of BEOL processing. As a result, the formation of the ferroelectric material 244 for the capacitors 216 may be implemented at any suitable annealing temperature than would be possible if the capacitors 216 were formed during BEOL processes. Furthermore, the processes used to form the capacitors 216 may directly follow the completion of the transistors 214 (e.g., at the end of the FEOL procedures) without many intermediate process or additional complex structures. More particularly, the capacitors 216 are directly integrated with the associated wordline transistors 214 by being formed using sacrificial transistors 302 as the basis for the structures of the capacitors 216. Thus, the capacitors 216 are formed on the same semiconductor material (e.g., the same fins 210, 212) and on the same surface of such semiconductor material.

[0047] FIG. 9 is a flowchart representative of an example method of manufacturing the example memory array 200 of FIGS. 2A-2D and 8A-8C. The process begins at block 902 with the formation of a transistor array 300 on semiconductor fins 210, 212. The transistor array 300 may be formed using known techniques general corresponding to processes that complete the FEOL processes. At block 904, a first hard mask 402 is deposited on the transistor array 300 to protect wordline transistors 214 and expose sacrificial transistors 302. At block 906, the gate conductor 220 and the gate dielectric 234 of the sacrificial transistors 302 are etched away. At block 908, the STI material 232 to expose the semiconductor fins 210, 212 at location of the sacrificial transistors 302. In some examples, the etching processes of blocks 906 and 908 are combined into a single etch process.

[0048] At block 910, the exposed portions of the semiconductor fins 210, 212 are doped to form a bottom electrode (e.g., the second electrode 242) for a capacitor (e.g., the capacitor 216). That is, the exposed portions of the semiconductor fins 210, 212 become highly doped regions (e.g., the deep doped regions 240) that are conductive and, thus, may function as one of the electrodes of a ferroelectric capacitor. In some examples, the doping is accomplished through an implantation process. At block 912, a ferroelectric material is deposited and annealed on the bottom electrode 242. In some examples, the annealing occurs at temperatures higher than what is available during BEOL processes.

[0049] At block 914, a conductive material is deposited on the ferroelectric material to form the top electrode (e.g., the first electrode 236) for the capacitor 216. In some examples, this top electrode also corresponds to the capacitor line 248 for the memory array 200. At block 916, the hard mask 402 (applied at block 904) and any excess conductive material (applied at block 914) are removed. In some examples, this may involve polishing the conductive material off of the hard mask and then etching the hard mask 402 away. In some examples, a second polishing process may be implemented to even out the conductive material for the top electrodes 236 of the capacitors 216 relative to the top surface of the wordline transistors 214. In other examples, the excess material on the top electrodes 236 may be removed by a timed etch before the polishing and removal of the hard mask 402.

[0050] At block 918, a second hard mask 704 is deposited to protect the wordline transistors 214 and the capacitors 216 and expose region between adjacent capacitors 216. At block 920, the exposed regions between the adjacent capacitors 216 are etched to form a trench 702. At block 922, isolation material 250 is deposited within the trench 702. At block 924, the second hard mask 704 (applied at block 918) and any excess isolation material 250 (applied at block 922) are removed. In some examples, this may involve polishing the conductive material off of the hard mask 704 and then etching the hard mask 704 away. Thereafter, the example process of FIG. 9 ends and the manufacturing may proceed to BEOL processes.

[0051] Although the example method of FIG. 9 is described with reference to the flowchart shown in FIG. 9, many other methods of manufacturing the example memory array 200 of FIGS. 2A-2D may alternatively be used. For example, the order of execution of the blocks in FIG. 9 may be changed, and/or some of the blocks described may be changed, eliminated, or combined. Further, additional operations may be included in the manufacturing process before, in between, or after the blocks shown in FIG. 9. In particular, additional processing to add metal contacts and metal layers may be performed during the BEOL.

[0052] From the foregoing, it will be appreciated that example methods, apparatus and articles of manufacture have been disclosed that integrate ferroelectric capacitors onto the same semiconductor substrate (e.g., same fin) as associated transistors for 1T-1C ferroelectric memory cells. More particularly, example capacitors disclosed herein have a structure similar to the corresponding transistors and are formed using similar processes used in the formation of transistors. Indeed, in some examples, the capacitors are formed from sacrificial transistors formed at the same time as other transistors intended to be access transistors on a corresponding wordline of a memory array. In such examples, a doped region of the semiconductor fin serves as one of the electrodes for the capacitor. Integrating ferroelectric capacitors in the manner disclosed may be performed before BEOL processes. As a result, the ferroelectric material used in the capacitors may be annealed at temperatures above what is available during the BEOL for improved characteristics. The example memory arrays disclosed herein may be included in any suitable electronic component. FIGS. 10-14 illustrate various examples of apparatus that may include any of the example memory cells 202, 204, 206, 208 of the example memory array 200 disclosed herein.

[0053] FIG. 10 is a top view of a wafer 1000 and dies 1002 that may include one or more memory cells 202, 204, 206, 208, or may be included in an IC package whose substrate includes one or more memory cells (e.g., as discussed below with reference to FIG. 12) in accordance with any of the examples disclosed herein. The wafer 1000 may be composed of

semiconductor material and may include one or more dies 1002 having IC structures formed on a surface of the wafer 1000. Each of the dies 1002 may be a repeating unit of a semiconductor product that includes any suitable IC. After the fabrication of the semiconductor product is complete, the wafer 1000 may undergo a singulation process in which the dies 1002 are separated from one another to provide discrete’’chips” of the semiconductor product. The die 1002 may include one or more memory cells (e.g., as discussed below with reference to FIG. 11), one or more transistors (e.g., some of the transistors 1140 of FIG. 11, discussed below) and/or supporting circuitry to route electrical signals to the transistors, as well as any other IC components. In some examples, the wafer 1000 or the die 1002 may include a memory device (e.g., a random access memory (RAM) device, such as a static RAM (SRAM) device, a magnetic RAM (MRAM) device, a resistive RAM (RRAM) device, a conductive-bridging RAM (CBRAM) device, etc.), a logic device (e.g., an AND, OR, NAND, or NOR gate), or any other suitable circuit element.

Multiple ones of these devices may be combined on a single die 1002. For example, a memory array formed by multiple memory devices may be formed on a same die 1002 as a processing device (e.g., the processing device 1402 of FIG. 14) or other logic that is configured to store information in the memory devices or execute instructions stored in the memory array.

[0054] FIG. 11 is a cross-sectional side view of an IC device 1100 that may include one or more memory cells , or may be included in an IC package whose substrate includes one or more memory cells (e.g., as discussed below with reference to FIG. 12), in accordance with any of the examples disclosed herein. One or more of the IC devices 1100 may be included in one or more dies 1002 (FIG. 10). The IC device 1100 may be formed on a substrate 1102 (e.g., the wafer 1000 of FIG. 10) and may be included in a die (e.g., the die 1002 of FIG. 10). The substrate 1102 may be a semiconductor substrate composed of semiconductor material systems including, for example, n-type or p-type materials systems (or a combination of both). The substrate 1102 may include, for example, a crystalline substrate formed using a bulk silicon or a silicon-on-insulator (SOI) substructure. In some examples, the substrate 1102 may be formed using alternative materials, which may or may not be combined with silicon, that include but are not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Further materials classified as group II-VI, III-V, or IV may also be used to form the substrate 1102. Although a few examples of materials from which the substrate 1102 may be formed are described here, any material that may serve as a foundation for an IC device 1100 may be used. The substrate 1102 may be part of a singulated die (e.g., the dies 1002 of FIG. 10) or a wafer (e.g., the wafer 1000 of FIG. 10).

[0055] The IC device 1100 may include one or more device layers 1104 disposed on the substrate 1102. The device layer 1104 may include features of one or more transistors 1140 (e.g., metal oxide semiconductor field-effect transistors (MOSFETs)) formed on the substrate 1102. The device layer 1104 may include, for example, one or more source and/or drain (S/D) regions 1120, a gate 1122 to control current flow in the transistors 1140 between the S/D regions 1120, and one or more S/D contacts 1124 to route electrical signals to/from the S/D regions 1120. The transistors 1140 may include additional features not depicted for the sake of clarity, such as device isolation regions, gate contacts, and the like. The transistors 1140 are not limited to the type and configuration depicted in FIG. 11 and may include a wide variety of other types and configurations such as, for example, planar transistors, non-planar transistors, or a combination of both. Non-planar transistors may include FinFET transistors, such as double-gate transistors or tri-gate transistors, and wrap-around or all-around gate transistors, such as nanoribbon and nanowire transistors.

[0056] Each transistor 1140 may include a gate 1122 formed of at least two layers, a gate dielectric and a gate electrode. The gate dielectric may include one layer or a stack of layers. The one or more layers may include silicon oxide, silicon dioxide, silicon carbide, and/or a high-k dielectric material. The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some examples, an annealing process may be carried out on the gate dielectric to improve its quality when a high-k material is used.

[0057] The gate electrode may be formed on the gate dielectric and may include at least one p-type work function metal or n-type work function metal, depending on whether the transistor 1140 is to be a p-type metal oxide semiconductor (PMOS) or an n-type metal oxide semiconductor (NMOS) transistor. In some implementations, the gate electrode may consist of a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Further metal layers may be included for other purposes, such as a barrier layer. For a PMOS transistor, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides (e.g., ruthenium oxide), and any of the metals discussed below with reference to an NMOS transistor (e.g., for work function tuning). For an NMOS transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any of the metals discussed above with reference to a PMOS transistor (e.g., for work function tuning).

[0058] In some examples, when viewed as a cross-section of the transistor 1140 along the source-channel-drain direction, the gate electrode may consist of a U-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate. In other examples, at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate. In other examples, the gate electrode may consist of a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode may consist of one or more U- shaped metal layers formed atop one or more planar, non-U-shaped layers. [0059] In some examples, a pair of sidewall spacers may be formed on opposing sides of the gate stack to bracket the gate stack. The sidewall spacers may be formed from materials such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process steps. In some examples, a plurality of spacer pairs may be used; for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.

[0060] The S/D regions 1120 may be formed within the substrate 1102 adjacent to the gate 1122 of each transistor 1140. The S/D regions 1120 may be formed using an implantation/diffusion process or an etching/deposition process, for example. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the substrate 1102 to form the S/D regions 1120. An annealing process that activates the dopants and causes them to diffuse farther into the substrate 1102 may follow the ion-implantation process. In the latter process, the substrate 1102 may first be etched to form recesses at the locations of the S/D regions 1120. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the S/D regions 1120. In some implementations, the S/D regions 1120 may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some examples, the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In some examples, the S/D regions 1120 may be formed using one or more alternate semiconductor materials such as germanium or a group III-V material or alloy. In further examples, one or more layers of metal and/or metal alloys may be used to form the S/D regions 1120.

[0061] In some examples, the device layer 1104 may include one or more memory cells as disclosed herein (e.g., the example memory cells 202, 204, 206, 208), in addition to or instead of transistors 1140. FIG. 11 illustrates a single memory cell 202 in the device layer 1104 for illustration purposes, but any number and structure of memory cells may be included in a device layer 1104. A memory cell included in a device layer 1104 may be referred to as a "front end" device. In some examples, the IC device 1100 may not include any front end memory cell . One or more memory cells 202, 204, 206, 208in the device layer 1104 may be coupled to any suitable other ones of the devices in the device layer 1104, to any devices in the metallization stack 1119 (discussed below), and/or to one or more of the conductive contacts 1136 (discussed below).

[0062] Electrical signals, such as power and/or input/output (I/O) signals, may be routed to and/or from the devices (e.g., transistors 1140 and/or memory cell 202) of the device layer 1104 through one or more interconnect layers disposed on the device layer 1104 (illustrated in FIG. 11 as interconnect layers 1106-1110). For example, electrically conductive features of the device layer 1104 (e.g., the gate 1122 and the S/D contacts 1124) may be electrically coupled with the interconnect structures 1128 of the interconnect layers 1106- 1110. The one or more interconnect layers 1106-1110 may form a metallization stack (also referred to as an "ILD stack") 1119 of the IC device 1100. In some examples, one or more memory cells 202, 204, 206, 208may be disposed in one or more of the interconnect layers 1106-1110, in accordance with any of the techniques disclosed herein. A memory cell 202, 204, 206, 208included in the metallization stack 1119 may be referred to as a "back-end" device. In some examples, the IC device 1100 may not include any back-end memory cells 202, 204, 206, 208; in some examples, the IC device 1100 may include both front- and back-end memory cells 202, 204, 206, 208. One or more memory cells in the metallization stack 1119 may be coupled to any suitable ones of the devices in the device layer 1104, and/or to one or more of the conductive contacts 1136 (discussed below).

[0063] The interconnect structures 1128 may be arranged within the interconnect layers 1106-1110 to route electrical signals according to a wide variety of designs (in particular, the arrangement is not limited to the particular configuration of interconnect structures 1128 depicted in FIG. 11). Although a particular number of interconnect layers 1106-1110 is depicted in FIG. 11, examples of the present disclosure include IC devices having more or fewer interconnect layers than depicted.

[0064] In some examples, the interconnect structures 1128 may include lines 1 l28a and/or vias 1 l28b filled with an electrically conductive material such as a metal. The lines 1 l28a may be arranged to route electrical signals in a direction of a plane that is substantially parallel with a surface of the substrate 1102 upon which the device layer 1104 is formed. For example, the lines 1 l28a may route electrical signals in a direction in and out of the page from the perspective of FIG. 11. The vias 1 l28b may be arranged to route electrical signals in a direction of a plane that is substantially perpendicular to the surface of the substrate 1102 upon which the device layer 1104 is formed. In some examples, the vias 1 l28b may electrically couple lines 1 l28a of different interconnect layers 1106-1110 together.

[0065] The interconnect layers 1106-1110 may include a dielectric material 1126 disposed between the interconnect structures 1128, as shown in FIG. 11. In some examples, the dielectric material 1126 disposed between the interconnect structures 1128 in different ones of the interconnect layers 1106- 1110 may have different compositions; in other examples, the composition of the dielectric material 1126 between different interconnect layers 1106-1110 may be the same.

[0066] A first interconnect layer 1106 (referred to as Metal 1 or "Ml") may be formed directly on the device layer 1104. In some examples, the first interconnect layer 1106 may include lines 1 l28a and/or vias 1 l28b, as shown. The lines 1 l28a of the first interconnect layer 1106 may be coupled with contacts (e.g., the S/D contacts 1124) of the device layer 1104.

[0067] A second interconnect layer 1108 (referred to as Metal 2 or "M2") may be formed directly on the first interconnect layer 1106. In some examples, the second interconnect layer 1108 may include vias 1 l28b to couple the lines 1 l28a of the second interconnect layer 1108 with the lines 1 l28a of the first interconnect layer 1106. Although the lines 1 l28a and the vias 1 l28b are structurally delineated with a line within each interconnect layer (e.g., within the second interconnect layer 1108) for the sake of clarity, the lines 1 l28a and the vias 1 l28b may be structurally and/or materially contiguous (e.g., simultaneously filled during a dual-damascene process) in some examples.

[0068] A third interconnect layer 1110 (referred to as Metal 3 or "M3") (and additional interconnect layers, as desired) may be formed in succession on the second interconnect layer 1108 according to similar techniques and configurations described in connection with the second interconnect layer 1108 or the first interconnect layer 1106. In some examples, the interconnect layers that are’’higher up” in the metallization stack 1119 in the IC device 1100 (i.e., further away from the device layer 1104) may be thicker.

[0069] The IC device 1100 may include a solder resist material 1134 (e.g., polyimide or similar material) and one or more conductive contacts 1136 formed on the interconnect layers 1106-1110. In FIG. 11, the conductive contacts 1136 are illustrated as taking the form of bond pads. The conductive contacts 1136 may be electrically coupled with the interconnect structures 1128 and configured to route the electrical signals of the transistor(s) 1140 to other external devices. For example, solder bonds may be formed on the one or more conductive contacts 1136 to mechanically and/or electrically couple a chip including the IC device 1100 with another component (e.g., a circuit board). The IC device 1100 may include additional or alternate structures to route the electrical signals from the interconnect layers 1106-1110; for example, the conductive contacts 1136 may include other analogous features (e.g., posts) that route the electrical signals to external components.

[0070] FIG. 12 is a cross-sectional view of an example IC package 1200 that may include one or more memory cells structured in accordance with the teachings disclosed herein (e.g., the memory cells 202, 204, 206,

208). The package substrate 1202 may be formed of a dielectric material, and may have conductive pathways extending through the dielectric material between upper and lower faces 1222, 1224, or between different locations on the upper face 1222, and/or between different locations on the lower face 1224. These conductive pathways may take the form of any of the interconnects 1128 discussed above with reference to FIG. 11. In some examples, one or more memory cells 202, 204, 206, 208 (with any suitable structure) may be included in a package substrate 1202. In some examples, no memory cells 202, 204, 206, 208 may be included in the package substrate 1202

[0071] The IC package 1200 may include a die 1206 coupled to the package substrate 1202 via conductive contacts 1204 of the die 1206, first- level interconnects 1208, and conductive contacts 1210 of the package substrate 1202. The conductive contacts 1210 may be coupled to conductive pathways 1212 through the package substrate 1202, allowing circuitry within the die 1206 to electrically couple to various ones of the conductive contacts 1214 or to the memory cells 202, 204, 206, 208 (or to other devices included in the package substrate 1202, not shown). The first-level interconnects 1208 illustrated in FIG. 12 are solder bumps, but any suitable first-level interconnects 1208 may be used. As used herein, a "conductive contact" may refer to a portion of conductive material (e.g., metal) serving as an electrical interface between different components; conductive contacts may be recessed in, flush with, or extending away from a surface of a component, and may take any suitable form (e.g., a conductive pad or socket).

[0072] In some examples, an underfill material 1216 may be disposed between the die 1206 and the package substrate 1202 around the first-level interconnects 1208, and a mold compound 1218 may be disposed around the die 1206 and in contact with the package substrate 1202. In some examples, the underfill material 1216 may be the same as the mold compound 1218. Example materials that may be used for the underfill material 1216 and the mold compound 1218 are epoxy mold materials, as suitable. Second-level interconnects 1220 may be coupled to the conductive contacts 1214. The second-level interconnects 1220 illustrated in FIG. 12 are solder balls (e.g., for a ball grid array arrangement), but any suitable second-level interconnects 1220 may be used (e.g., pins in a pin grid array arrangement or lands in a land grid array arrangement). The second-level interconnects 1220 may be used to couple the IC package 1200 to another component, such as a circuit board (e.g., a motherboard), an interposer, or another IC package, as known in the art and as discussed below with reference to FIG. 13.

[0073] In FIG. 12, the IC package 1200 is a flip chip package, and includes a memory cell 202, 204, 206, 208 in the package substrate 1202. The number and location of memory cells in the package substrate 1202 of the IC package 1200 is simply illustrative, and any number of memory cells (with any suitable structure) may be included in a package substrate 1202. In some examples, no memory cells may be included in the package substrate 1202.

The die 1206 may take the form of any of the examples of the die 1002 discussed herein (e.g., may include any of the examples of the IC device 1100). In some examples, the die 1206 may include one or more memory cells 202, 204, 206, 208 (e.g., as discussed above with reference to FIG. 10 and FIG. 11); in other examples, the die 1206 may not include any memory cells.

[0074] Although the IC package 1200 illustrated in FIG. 12 is a flip chip package, other package architectures may be used. For example, the IC package 1200 may be a ball grid array (BGA) package, such as an embedded wafer-level ball grid array (eWLB) package. In another example, the IC package 1200 may be a wafer-level chip scale package (WLCSP) or a panel fanout (FO) package. Although a single die 1206 is illustrated in the IC package 1200 of FIG. 12, an IC package 1200 may include multiple dies 1206 (e.g., with one or more of the multiple dies 1206 coupled to memory cells included in the package substrate 1202). An IC package 1200 may include additional passive components, such as surface-mount resistors, capacitors, and inductors disposed on the first face 1222 or the second face 1224 of the package substrate 1202. More generally, an IC package 1200 may include any other active or passive components known in the art.

[0075] FIG. 13 is a cross-sectional side view of an IC device assembly 1300 that may include one or more IC packages or other electronic components (e.g., a die) including one or more memory cells 202, 204, 206, 208, in accordance with any of the examples disclosed herein. The IC device assembly 1300 includes a number of components disposed on a circuit board 1302 (which may be, for example, a motherboard). The IC device assembly 1300 includes components disposed on a first face 1340 of the circuit board 1302 and an opposing second face 1342 of the circuit board 1302; generally, components may be disposed on one or both faces 1340 and 1342. Any of the IC packages discussed below with reference to the IC device assembly 1300 may take the form of any of the examples of the IC package 1200 discussed above with reference to FIG. 12 (e.g., may include one or more memory cells in a package substrate 1202 or in a die).

[0076] In some examples, the circuit board 1302 may be a printed circuit board (PCB) including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board 1302. In other examples, the circuit board 1302 may be a non-PCB substrate.

[0077] The IC device assembly 1300 illustrated in FIG. 13 includes a package-on-interposer structure 1336 coupled to the first face 1340 of the circuit board 1302 by coupling components 1316. The coupling components 1316 may electrically and mechanically couple the package-on-interposer structure 1336 to the circuit board 1302, and may include solder balls (as shown in FIG. 13), male and female portions of a socket, an adhesive, an underfill material, and/or any other suitable electrical and/or mechanical coupling structure.

[0078] The package-on-interposer structure 1336 may include an IC package 1320 coupled to an interposer 1304 by coupling components 1318. The coupling components 1318 may take any suitable form for the application, such as the forms discussed above with reference to the coupling components 1316. Although a single IC package 1320 is shown in FIG. 13, multiple IC packages may be coupled to the interposer 1304; indeed, additional interposers may be coupled to the interposer 1304. The interposer 1304 may provide an intervening substrate used to bridge the circuit board 1302 and the IC package 1320. The IC package 1320 may be or include, for example, a die (the die 1002 of FIG. 10), an IC device (e.g., the IC device 1100 of FIG. 11), or any other suitable component. Generally, the interposer 1304 may spread a connection to a wider pitch or reroute a connection to a different connection. For example, the interposer 1304 may couple the IC package 1320 (e.g., a die) to a set of BGA conductive contacts of the coupling components 1316 for coupling to the circuit board 1302. In the example illustrated in FIG. 13, the IC package 1320 and the circuit board 1302 are attached to opposing sides of the interposer 1304; in other examples, the IC package 1320 and the circuit board 1302 may be attached to a same side of the interposer 1304. In some examples, three or more components may be interconnected by way of the interposer 1304.

[0079] The interposer 1304 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, an epoxy resin with inorganic fillers, a ceramic material, or a polymer material such as polyimide. In some examples, the interposer 1304 may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials. The interposer 1304 may include metal interconnects 1308 and vias 1310, including but not limited to through-silicon vias (TSVs) 1306. The interposer 1304 may further include embedded devices 1314, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the interposer 1304. The package-on-interposer structure 1336 may take the form of any of the package-on-interposer structures known in the art. In some examples, the interposer 1304 may include one or more memory cells 202, 204, 206, 208.

[0080] The IC device assembly 1300 may include an IC package 1324 coupled to the first face 1340 of the circuit board 1302 by coupling components 1322. The coupling components 1322 may take the form of any of the examples discussed above with reference to the coupling components 1316, and the IC package 1324 may take the form of any of the examples discussed above with reference to the IC package 1320.

[0081] The IC device assembly 1300 illustrated in FIG. 13 includes a package-on-package structure 1334 coupled to the second face 1342 of the circuit board 1302 by coupling components 1328. The package-on-package structure 1334 may include a first IC package 1326 and a second IC package 1332 coupled together by coupling components 1330 such that the first IC package 1326 is disposed between the circuit board 1302 and the second IC package 1332. The coupling components 1328, 1330 may take the form of any of the examples of the coupling components 1316 discussed above, and the IC packages 1326, 1332 may take the form of any of the examples of the IC package 1320 discussed above. The package-on-package structure 1334 may be configured in accordance with any of the package-on-package structures known in the art.

[0082] FIG. 14 is a block diagram of an example electrical device 1400 that may include one or more memory cells 202, 204, 206, 208, in accordance with any of the examples disclosed herein. For example, any suitable ones of the components of the electrical device 1400 may include one or more of the IC packages 1200, IC devices 1100, or dies 1002 disclosed herein. A number of components are illustrated in FIG. 14 as included in the electrical device 1400, but any one or more of these components may be omitted or duplicated, as suitable for the application. In some examples, some or all of the components included in the electrical device 1400 may be attached to one or more motherboards. In some examples, some or all of these components are fabricated onto a single system-on-a-chip (SoC) die.

[0083] Additionally, in various examples, the electrical device 1400 may not include one or more of the components illustrated in FIG. 14, but the electrical device 1400 may include interface circuitry for coupling to the one or more components. For example, the electrical device 1400 may not include a display device 1406, but may include display device interface circuitry (e.g., a connector and driver circuitry) to which a display device 1406 may be coupled. In another set of examples, the electrical device 1400 may not include an audio input device 1424 or an audio output device 1408, but may include audio input or output device interface circuitry (e.g., connectors and supporting circuitry) to which an audio input device 1424 or audio output device 1408 may be coupled.

[0084] The electrical device 1400 may include a processing device 1402 (e.g., one or more processing devices). As used herein, the term

"processing device" or "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. The processing device 1402 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing devices. The electrical device 1400 may include a memory 1404, which may itself include one or more memory devices such as volatile memory (e.g., dynamic random access memory (DRAM)), nonvolatile memory (e.g., read-only memory (ROM)), flash memory, solid state memory, and/or a hard drive. In some examples, the memory 1404 may include memory that shares a die with the processing device 1402. This memory may be used as cache memory and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random access memory (STT-MRAM).

[0085] In some examples, the electrical device 1400 may include a communication chip 1412 (e.g., one or more communication chips). For example, the communication chip 1412 may be configured for managing wireless communications for the transfer of data to and from the electrical device 1400. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium. The term does not imply that the associated devices do not contain any wires, although in some examples they might not.

[0086] The communication chip 1412 may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultra mobile broadband (UMB) project (also referred to as "3GPP2"), etc.). IEEE 802.16 compatible

Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformity and interoperability tests for the IEEE 802.16 standards. The communication chip 1412 may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip 1412 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 1412 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT),

Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The communication chip 1412 may operate in accordance with other wireless protocols in other examples. The electrical device 1400 may include an antenna 1422 to facilitate wireless communications and/or to receive other wireless communications (such as AM or FM radio transmissions).

[0087] In some examples, the communication chip 1412 may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., the Ethernet). As noted above, the

communication chip 1412 may include multiple communication chips. For instance, a first communication chip 1412 may be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth, and a second communication chip 1412 may be dedicated to longer-range wireless communications such as global positioning system (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some examples, a first communication chip 1412 may be dedicated to wireless communications, and a second communication chip 1412 may be dedicated to wired

communications.

[0088] The electrical device 1400 may include battery/power circuitry 1414. The battery/power circuitry 1414 may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the electrical device 1400 to an energy source separate from the electrical device 1400 (e.g., AC line power).

[0089] The electrical device 1400 may include a display device 1406 (or corresponding interface circuitry, as discussed above). The display device 1406 may include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display.

[0090] The electrical device 1400 may include an audio output device 1408 (or corresponding interface circuitry, as discussed above). The audio output device 1408 may include any device that generates an audible indicator, such as speakers, headsets, or earbuds.

[0091] The electrical device 1400 may include an audio input device 1424 (or corresponding interface circuitry, as discussed above). The audio input device 1424 may include any device that generates a signal

representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output).

[0092] The electrical device 1400 may include a GPS device 1418 (or corresponding interface circuitry, as discussed above). The GPS device 1418 may be in communication with a satellite-based system and may receive a location of the electrical device 1400, as known in the art.

[0093] The electrical device 1400 may include an other output device 1410 (or corresponding interface circuitry, as discussed above). Examples of the other output device 1410 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.

[0094] The electrical device 1400 may include an other input device 1420 (or corresponding interface circuitry, as discussed above). Examples of the other input device 1420 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a bar code reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.

[0095] The electrical device 1400 may have any desired form factor, such as a hand-held or mobile electrical device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra mobile personal computer, etc.), a desktop electrical device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable electrical device. In some examples, the electrical device 1400 may be any other electronic device that processes data.

[0096] The following paragraphs provide various examples of the examples disclosed herein.

[0097] Example 1 is a memory device that includes a semiconductor fin, a transistor associated with a first portion of the semiconductor fin, and a ferroelectric capacitor adjacent the transistor. A second portion of the semiconductor fin including a doped region corresponds to an electrode of the ferroelectric capacitor.

[0098] Example 2 includes the subject matter of Example 1, wherein the electrode of the ferroelectric capacitor is a first electrode. The ferroelectric capacitor further includes a second electrode corresponding to a metal, and a ferroelectric material between the first and second electrodes.

[0099] Example 3 includes the subject matter of Example 2, wherein the second portion of the semiconductor fin includes a first doped region. The transistor includes a second doped region of the semiconductor fin.

[0100] Example 4 includes the subject matter of Example 3, wherein a first depth of the first doped region is greater than a second depth of the second doped region.

[0101] Example 5 includes the subject matter of any one of Examples 3 or 4, wherein the first doped region includes at least one of phosphorus or arsenic.

[0102] Example 6 includes the subject matter of any one of Examples 2-5, wherein the transistor includes a gate conductor, and a dielectric material positioned between the gate conductor and the semiconductor fin. The dielectric material and the ferroelectric material are in contact with a same surface of the semiconductor fin.

[0103] Example 7 includes the subject matter of any one of Examples 2-6, wherein the ferroelectric material includes hafnium, oxygen, and a dopant.

[0104] Example 8 includes the subject matter of Example 7, wherein the dopant includes at least one of zirconium, silicon, yttrium, or aluminum.

[0105] Example 9 includes the subject matter of any one of Examples 1-8, wherein the transistor includes a first conductive material extending down a sidewall of the semiconductor fin. The ferroelectric capacitor includes a second conductive material extending down the sidewall of the semiconductor fin. The second conductive material is to extend farther down the sidewall than the first conductive material.

[0106] Example 10 includes the subject matter of any one of Examples 1-9, wherein the transistor is a first transistor and the ferroelectric capacitor is a first ferroelectric capacitor. The memory device further includes a second transistor associated with a third portion of the semiconductor fin and a second ferroelectric capacitor associated with a fourth portion of the semiconductor fin.

[0107] Example 11 includes the subject matter of Example 10, wherein the first transistor and the first ferroelectric capacitor correspond to a first cell of the memory device. The second transistor and the second ferroelectric capacitor correspond to a second cell of the memory device.

[0108] Example 12 includes the subject matter of any one of Examples 10 or 11, and further includes an isolation material disposed between the first and second ferroelectric capacitors. The first and second ferroelectric capacitors are positioned between the first and second transistors.

[0109] Example 13 includes the subject matter of any one of Examples 10-12, wherein the first transistor is adjacent the second transistor. The first and second transistors are positioned between the first and second ferroelectric capacitors.

[0110] Example 14 is a memory device that includes a semiconductor fin, a dielectric material on the semiconductor fin, and a ferroelectric material on the semiconductor fin. The ferroelectric material is adjacent the dielectric material. The memory device further includes a gate conductor on the dielectric material, and a capacitor electrode on the ferroelectric material.

[0111] Example 15 includes the subject matter of Example 14, and further includes: a first doped region in the semiconductor fin. The first doped region is positioned between the dielectric material and the ferroelectric material. A second doped region in the semiconductor fin is positioned in alignment with the ferroelectric material along the semiconductor fin.

[0112] Example 16 includes the subject matter of Example 15, wherein the second doped region extends deeper into the semiconductor fin than the first doped region.

[0113] Example 17 includes the subject matter of any one of Examples 15 or 16, wherein the second doped region includes at least one of phosphorus or arsenic. [0114] Example 18 includes the subject matter of any one of Examples 15-17, wherein the capacitor electrode is a first capacitor electrode. The second doped region corresponds to a second capacitor electrode.

[0115] Example 19 includes the subject matter of any one of Examples 14-18, wherein the gate conductor and the capacitor electrode are positioned around a top surface and sidewalls of the semiconductor fin.

[0116] Example 20 includes the subject matter of Example 19, wherein the capacitor electrode extends farther along a height of the sidewalls of the semiconductor fin than the gate conductor.

[0117] Example 21 includes the subject matter of any one of Examples 14-20, wherein the ferroelectric material includes hafnium, oxygen, and a dopant.

[0118] Example 22 includes the subject matter of Example 21, wherein the dopant includes at least one of zirconium, silicon, yttrium, or aluminum.

[0119] Example 23 includes the subject matter of any one of Examples 14-22, wherein the capacitor electrode is a first capacitor electrode of a first capacitor. The first capacitor electrode is on a first portion of the ferroelectric material. The memory device further includes a second capacitor electrode on a second portion of the ferroelectric material. The second capacitor electrode associated with a second capacitor. The memory device further includes an isolation material separating the first and second capacitor electrodes.

[0120] Example 24 includes the subject matter of Example 23, wherein the isolation material separates a first doped region in the semiconductor fin from a second doped region in the semiconductor fin. The first doped region is proximate the first portion of the ferroelectric material. The second doped region is proximate the second portion of the ferroelectric material.

[0121] Example 25 includes the subject matter of any one of Examples 23 or 24, wherein a top surface of the gate conductor is substantially even with a top surface of the capacitor electrode.

[0122] Example 26 is a system that includes a processing device, and a memory array including: a gate conductor for a transistor. The transistor is positioned along a semiconductor fin. The gate conductor corresponds to a wordline of the memory array. The memory array further includes a first electrode for a ferroelectric capacitor. The ferroelectric capacitor is positioned along the semiconductor fin adjacent the transistor. A portion of the semiconductor fin corresponds to a second electrode of the ferroelectric capacitor.

[0123] Example 27 includes the subject matter of Example 26, wherein the memory array further includes a ferroelectric material between the first and second electrodes.

[0124] Example 28 includes the subject matter of Example 27, wherein the portion of the semiconductor fin includes a first doped region. The transistor is associated with a second doped region of the semiconductor fin.

[0125] Example 29 includes the subject matter of Example 28, wherein a first depth of the first doped region is greater than a second depth of the second doped region.

[0126] Example 30 includes the subject matter of any one of Examples 28 or 29, wherein the first doped region includes at least one of phosphorus or arsenic.

[0127] Example 31 includes the subject matter of any one of Examples 27-30, wherein the memory array further includes a dielectric material positioned between the gate conductor and the semiconductor fin. The dielectric material and the ferroelectric material are in contact with a same surface of the semiconductor fin.

[0128] Example 32 includes the subject matter of any one of Examples 27-31, wherein the ferroelectric material includes hafnium, oxygen, and a dopant.

[0129] Example 33 includes the subject matter of Example 32, wherein the dopant includes at least one of zirconium, silicon, yttrium, or aluminum.

[0130] Example 34 includes the subject matter of any one of Examples 26-33, wherein the gate conductor and the first electrode extend down a sidewall of the semiconductor fin. The first electrode is to extend farther down the sidewall than the gate conductor. [0131] Example 35 includes the subject matter of any one of Examples 26-34, wherein the transistor is a first transistor and the ferroelectric capacitor is a first ferroelectric capacitor. The memory array further includes a second gate conductor for a second transistor. The second transistor is positioned along the semiconductor fin and spaced apart from the first transistor. The memory array further includes a third electrode for a second ferroelectric capacitor. The second ferroelectric capacitor is spaced apart from the first ferroelectric capacitor.

[0132] Example 36 includes the subject matter of Example 35, wherein the first transistor and the first ferroelectric capacitor are associated with a first cell of the memory array. The second transistor and the second ferroelectric capacitor are associated with a second cell of the memory array.

[0133] Example 37 includes the subject matter of any one of Examples 35 or 36, and further includes an isolation material disposed between the first and second ferroelectric capacitors. The first and second ferroelectric capacitors are positioned between the first and second transistors.

[0134] Example 38 includes the subject matter of any one of Examples 35-37, wherein the first transistor is adjacent the second transistor. The first and second transistors are positioned between the first and second ferroelectric capacitors.

[0135] Example 39 a method of manufacturing a memory device. The method includes forming a transistor at a first portion of a semiconductor fin, and forming a ferroelectric capacitor at a second portion of the semiconductor fin adjacent the first portion. The second portion of the semiconductor fin corresponds to an electrode of the ferroelectric capacitor.

[0136] Example 40 includes the subject matter of Example 39, wherein the transistor is a first transistor and the forming of the ferroelectric capacitor includes: forming a second transistor adjacent the first transistor, the second transistor includes a gate conductor and a dielectric material; removing the gate conductor and the dielectric material to expose a portion of the semiconductor fin; and doping the exposed portion of the semiconductor fin. [0137] Example 41 includes the subject matter of Example 40, wherein the forming of the ferroelectric capacitor further includes etching shallow trench isolation material adjacent the exposed portion of the semiconductor fin to increase a height of the exposed portion of the semiconductor fin.

[0138] Example 42 includes the subject matter of any one of Examples 40 or 41, and further includes doping the exposed portion of the

semiconductor fin to a first depth. The first depth is greater than a second depth associated with a doped region in the semiconductor fin associated with transistor.

[0139] Example 43 includes the subject matter of Example 42, and further includes doping the exposed portion of the semiconductor fin with at least one of phosphorus or arsenic.

[0140] Example 44 includes the subject matter of any one of Examples 39-43, wherein the forming of the ferroelectric capacitor further includes: depositing a ferroelectric material on sidewalls and a top surface of the exposed portion of the semiconductor fin, and annealing the ferroelectric material.

[0141] Example 45 includes the subject matter of Example 44, wherein the annealing of the ferroelectric material is performed at a temperature greater than 400 degrees Celsius.

[0142] Example 46 includes the subject matter of any one of Examples 44 or 45, wherein the electrode is a first electrode. The forming of the ferroelectric capacitor further includes depositing a conductive material on the ferroelectric material to define a second electrode of the ferroelectric capacitor.

[0143] Example 47 includes the subject matter of Example 46, wherein the transistor includes a gate conductor extending a first distance down a sidewall of the semiconductor fin. The second electrode extends a second distance down the sidewall of the semiconductor fin. The second distance is greater than the second distance.

[0144] Example 48 includes the subject matter of any one of Examples 39-47, wherein the transistor is a first transistor and the ferroelectric capacitor is a first ferroelectric capacitor. The method further includes forming a second transistor at a third portion of the semiconductor fin, and forming a second ferroelectric capacitor at a fourth portion of the semiconductor fin.

[0145] Example 49 includes the subject matter of Example 48, and further includes: etching a trench between the first and second ferroelectric capacitors, the first and second ferroelectric capacitors positioned between the first and second transistors, and depositing an isolation material within the trench.

[0146] Although certain example methods, apparatus and articles of manufacture have been disclosed herein, the scope of coverage of this patent is not limited thereto. On the contrary, this patent covers all methods, apparatus and articles of manufacture fairly falling within the scope of the claims of this patent.

Claims

What Is Claimed Is:

1. A memory device, comprising:

a semiconductor fin;

a transistor associated with a first portion of the semiconductor fin; and a ferroelectric capacitor adjacent the transistor, a second portion of the semiconductor fin including a doped region corresponding to an electrode of the ferroelectric capacitor.

2. The memory device as defined in claim 1, wherein the electrode of the ferroelectric capacitor is a first electrode, the ferroelectric capacitor further including:

a second electrode corresponding to a metal; and

a ferroelectric material between the first and second electrodes.

3. The memory device as defined in claim 2, wherein the doped region is a first doped region, the transistor including a second doped region of the semiconductor fin.

4. The memory device as defined in claim 3, wherein a first depth of the first doped region is greater than a second depth of the second doped region.

5. The memory device as defined in any one of claims 2-4, wherein the transistor includes:

a gate conductor; and

a dielectric material positioned between the gate conductor and the semiconductor fin, the dielectric material and the ferroelectric material in contact with a same surface of the semiconductor fin.

6. The memory device as defined in any one of claims 2-4, wherein the ferroelectric material includes hafnium, oxygen, and a dopant.

7. The memory device as defined in claim 6, wherein the dopant includes at least one of zirconium, silicon, yttrium, or aluminum.

8. The memory device as defined in any one of claims 1-4, wherein the transistor includes a first conductive material extending down a sidewall of the semiconductor fin, the ferroelectric capacitor including a second conductive material extending down the sidewall of the semiconductor fin, the second conductive material to extend farther down the sidewall than the first conductive material.

9. The memory device as defined in any one of claims 1-4, wherein the transistor is a first transistor and the ferroelectric capacitor is a first ferroelectric capacitor, the memory device further including:

a second transistor associated with a third portion of the semiconductor fin; and

a second ferroelectric capacitor associated with a fourth portion of the semiconductor fin.

10. The memory device as defined in claim 9, wherein the first transistor and the first ferroelectric capacitor correspond to a first cell of the memory device, the second transistor and the second ferroelectric capacitor correspond to a second cell of the memory device.

11. The memory device as defined in claim 9, further including an isolation material disposed between the first and second ferroelectric capacitors, the first and second ferroelectric capacitors positioned between the first and second transistors.

12. The memory device as defined in claim 9, wherein the first transistor is adjacent the second transistor, the first and second transistors positioned between the first and second ferroelectric capacitors.

13. A memory device, comprising:

a semiconductor fin;

a dielectric material on the semiconductor fin;

a ferroelectric material on the semiconductor fin, the ferroelectric material adjacent the dielectric material;

a gate conductor on the dielectric material; and

a capacitor electrode on the ferroelectric material.

14. The memory device as defined in claim 13, further including: a first doped region in the semiconductor fin, the first doped region positioned between the dielectric material and the ferroelectric material; and a second doped region in the semiconductor fin positioned in alignment with the ferroelectric material along the semiconductor fin.

15. The memory device as defined in claim 14, wherein the second doped region extends deeper into the semiconductor fin than the first doped region.

16. The memory device as defined in any one of claims 13 or 14, wherein the gate conductor and the capacitor electrode are positioned around a top surface and sidewalls of the semiconductor fin.

17. The memory device as defined in claim 16, wherein the capacitor electrode extends farther along a height of the sidewalls of the semiconductor fin than the gate conductor.

18. A system comprising:

a processing device; and

a memory array including:

a gate conductor for a transistor, the transistor positioned along a semiconductor fin, the gate conductor corresponding to a wordline of the memory array; and

a first electrode for a ferroelectric capacitor, the ferroelectric capacitor positioned along the semiconductor fin adjacent the transistor, a portion of the semiconductor fin corresponding to a second electrode of the ferroelectric capacitor.

19. The system as defined in claim 18, wherein the memory array further includes a ferroelectric material between the first and second electrodes.

20. The system as defined in claim 19, wherein the portion of the semiconductor fin includes a first doped region, the transistor associated with a second doped region of the semiconductor fin.

21. The system as defined in any one of claims 19 or 20, wherein the memory array further includes a dielectric material positioned between the gate conductor and the semiconductor fin, the dielectric material and the ferroelectric material in contact with a same surface of the semiconductor fin.

22. A method of manufacturing a memory device, the method comprising:

forming a transistor at a first portion of a semiconductor fin; and forming a ferroelectric capacitor at a second portion of the semiconductor fin adjacent the first portion, the second portion of the semiconductor fin corresponding to an electrode of the ferroelectric capacitor.

23. The method as defined in claim 22, wherein the transistor is a first transistor and the forming of the ferroelectric capacitor includes:

forming a second transistor adjacent the first transistor, the second transistor including a gate conductor and a dielectric material;

removing the gate conductor and the dielectric material to expose a portion of the semiconductor fin; and

doping the exposed portion of the semiconductor fin.

24. The method as defined in any one of claims 22 or 23, wherein the forming of the ferroelectric capacitor further includes:

depositing a ferroelectric material on sidewalls and a top surface of the exposed portion of the semiconductor fin; and

annealing the ferroelectric material.

25. The method as defined in claim 24, wherein the annealing of the ferroelectric material is performed at a temperature greater than 400 degrees Celsius.