WO2023273589A1 - 一种信号判决均衡方法以及装置 - Google Patents

一种信号判决均衡方法以及装置 Download PDF

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Publication number
WO2023273589A1
WO2023273589A1 PCT/CN2022/090347 CN2022090347W WO2023273589A1 WO 2023273589 A1 WO2023273589 A1 WO 2023273589A1 CN 2022090347 W CN2022090347 W CN 2022090347W WO 2023273589 A1 WO2023273589 A1 WO 2023273589A1
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Prior art keywords
decision
equalization
value
input signal
group
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PCT/CN2022/090347
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English (en)
French (fr)
Inventor
王玮钰
李焕路
黄志雷
陆玉春
张海洋
周勤煜
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华为技术有限公司
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Priority to EP22831416.7A priority Critical patent/EP4351095A4/en
Publication of WO2023273589A1 publication Critical patent/WO2023273589A1/zh
Priority to US18/397,782 priority patent/US20240129168A1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H04L25/4917—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using multilevel codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H04L25/03012—Arrangements for removing intersymbol interference operating in the time domain
    • H04L25/03019—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception
    • H04L25/03057—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception with a recursive structure
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/02—Amplitude-modulated carrier systems, e.g. using on-off keying; Single sideband or vestigial sideband modulation
    • H04L27/06—Demodulator circuits; Receiver circuits

Definitions

  • the present application relates to the communication field, and in particular to a signal decision equalization method and device.
  • the optical link transmission signal has gradually transitioned from non-return-to-zero (NRZ) to pulse amplitude modulation (PAM).
  • NRZ non-return-to-zero
  • PAM pulse amplitude modulation
  • the multi-level modulation method makes each The nonlinear characteristics of various optoelectronic devices and channels begin to appear, which is mainly caused by the interaction between the chirp at the transmitting end in the optical link and the dispersion of the fiber.
  • CTLE continuous time linear equalizer
  • the nonlinear characteristics in the link not only introduce intersymbol interference, but also lead to signal distortion, which greatly affects the transmission characteristics of the system and hinders the further improvement of the system data transmission rate.
  • Embodiments of the present application provide a signal decision equalization method and device, which are used to implement optimal equalization and decision for a signal, thereby improving equalization performance and reducing a bit error rate after equalization.
  • the embodiment of the present application provides a signal decision equalization method, which specifically includes: the decision equalization device acquires an input signal, the input signal is a pulse amplitude modulation (PAM) signal or the PAM signal is pre-prepared The pre-equalized signal output after equalization (such as the pre-equalized signal output by the PAM signal through a feedforward equalizer (feed forward equalizer, FFE) pre-equalized output); then the decision equalization device determines the decision circuit of the input signal; at the same time the The decision equalization device also obtains the first group of decision thresholds and the first equalization expectation corresponding to the decision circuit; then the decision equalization device determines the decision of the input signal according to the first group of equalization expectations, the first group of decision thresholds, and the input signal value, and output the judgment value; at the same time, the decision equalization signal updates the first equilibrium expectation value in the first group of equilibrium expectation values to the second equilibrium expectation value according to the decision value and the input signal to obtain a second group of equilibrium expectation values, where
  • PAM
  • the decision equalization device independently iteratively updates each decision threshold of the decision circuit according to the input signal of the decision circuit, the decision value corresponding to the input signal, and the equalization expectation value corresponding to the decision value, which can be more effective. Realize optimal equalization and judgment on the signal, thereby improving the equalization performance and reducing the bit error rate after equalization.
  • the decision equalization device updates the first balanced expected value in the first group of balanced expected values to the second balanced expected value according to the decision value and the input signal
  • the following possible implementation methods may be adopted:
  • the decision equalization device updates the equalization expectation value corresponding to the iterative decision circuit after each decision equalization is performed to obtain a decision value.
  • the solution specifically includes: the decision equalization device determines a decision error of the decision circuit according to the first equalization expectation value and the input signal; and then updates the first equalization expectation value to the second equalization value according to the decision error expectations. In this way, the convergence process of the equalization expected value and the decision threshold can be quickly realized, thereby realizing linear and nonlinear equalization of signals.
  • the decision error is equal to the first equalization expectation value minus the input signal.
  • the method for the decision equalization device to update the first equalization expected value to the second equalization expected value according to the decision error specifically includes:
  • the decision equalization device updates the first equalization expected value to the second equalization expected value according to the decision error and the first formula
  • the first formula is:
  • the EV new is used to indicate the second expected equalization value
  • the EV old is used to indicate the first expected equalized value
  • the e k is used to indicate the decision error
  • the k is used to indicate the current moment.
  • the decision equalization device updates the first equalization expected value to the second equalization expected value according to the decision error and the second formula
  • the EV new is used to indicate the second equalization expected value
  • the EV old is used to indicate the first equalized expected value
  • the e k is used to indicate the decision error
  • the ⁇ is used to indicate a preset constant
  • the k is used to indicate the current moment.
  • the decision equalization device updates and iterates the equalization expectation value after a certain equalization expectation value on the decision circuit performs a preset number of decision equalizations (that is, the decision times of a certain equalization expectation value on the decision circuit reach the preset number of times). Set the number of times, for example, after the decision value corresponding to the balanced expected value EV 33 has been output 4 times, the balanced expected value EV 33 is updated to be EV 33, new ).
  • the solution specifically includes: the decision equalization device obtains a decision error according to the input signal and the first equalization expectation value, the decision equalization device records the decision error to generate a decision error set, and the decision error set includes the first A decision error corresponding to an equalized expected value; when the number of decision errors in the decision error set reaches a preset number, the decision equalization device determines the final decision error according to the decision errors in the decision error set; and updates the decision error according to the final decision error
  • the first balanced expected value is the second balanced expected value.
  • the decision equalization device when the decision equalization device records the decision error, it can directly calculate the sign of the decision error, and then record the calculated value as a decision error set; finally, in the decision error set After the number of values corresponding to the decision error reaches a preset number, the final decision error is determined according to the values in the decision error set, and the first balanced expected value is updated to the second balanced expected value according to the final decision error.
  • the decision errors corresponding to the first balanced expectation value are (-2, +4, +1, -5) respectively, then the decision error set obtained after the sign calculation of the decision errors is recorded as (-1, +1, +1, -1), then the final decision error is 0, and the first equilibrium expected value does not need to be updated in this update.
  • the decision errors corresponding to the first equilibrium expectation value are respectively (-2, +4, +1, +1)
  • the set of decision errors obtained after the sign calculation of the decision errors is recorded as (-1, +1 , +1, +1)
  • the final decision error is 2
  • the first balanced expected value is updated to the second balanced expected value according to the final decision error. In this way, the operational complexity of the decision equalization device in recording decision errors can be reduced.
  • the final decision error is equal to the sum of the multiple decision errors.
  • updating the first expected equalization value to the second expected equalization value by the decision equalization device according to the final decision error specifically includes:
  • the decision equalization device updates the first equalization expected value to the second equalization expected value according to the final decision error and the first formula
  • the first formula is:
  • the EV new is used to indicate the second expected equalization value
  • the EV old is used to indicate the first expected equalized value
  • the e k is used to indicate the decision error
  • the k is used to indicate the current moment.
  • the decision equalization device updates the first equalization expected value to the second equalization expected value according to the decision error and the second formula
  • the EV new is used to indicate the second equalization expected value
  • the EV old is used to indicate the first equalized expected value
  • the e k is used to indicate the decision error
  • the ⁇ is used to indicate a preset constant
  • the k is used to indicate the current moment.
  • the decision equalization device updates and iterates the equalization expectation value corresponding to the decision circuit after a preset time period.
  • the decision equalization device counts input signals corresponding to each equalization expected value on each decision circuit within a preset time period, and then obtains a decision error corresponding to each equalized expected value according to the input signal corresponding to each equalized expected value; finally the The decision equalization device updates each equalization expected value according to the decision error corresponding to each equalization expected value.
  • the manner of updating the expected equilibrium value may be the same as the technical solutions described in the above two solutions, and details will not be repeated here. In this way, the convergence process of the equalization expected value and the decision threshold can be quickly realized, thereby realizing linear and nonlinear equalization of signals.
  • the decision equalization device updates the first equalization expected value to the second equalization expected value
  • the decision equalization device updates at least one of the first set of decision thresholds according to the second equalization expectation and the third equalization expectation
  • a second group of decision thresholds is obtained as a decision threshold
  • the third balanced expected value is an balanced expected value adjacent to the second balanced expected value in the second group of balanced expected values.
  • the decision equalizer can also receive the initial convergence parameter output by the decision feedback equalizer (decision feedback equalizer, DFE) system, and the initial convergence parameter is used as the input signal to make a decision in the decision equalizer provided in this embodiment
  • DFE decision feedback equalizer
  • the initial equilibrium expected value at equilibrium In this way, the reliability of the equalized expected value and the decision threshold can be ensured when the initial decision equalization is performed, and the convergence process of the equalized expected value and the decision threshold can be accelerated.
  • the decision equalization device may also receive an adaptive parameter output by the FFE, and the adaptive parameter is used as an initial equalization expectation value of the input signal when performing decision equalization in the decision equalization device provided in this embodiment.
  • the reliability of the equalized expected value and the decision threshold can be ensured when the initial decision equalization is performed, and the convergence process of the equalized expected value and the decision threshold can be accelerated.
  • this embodiment is applied to PAM signals, and when the decision equalization device performs signal decision equalization, it is necessary to determine the decision equalization device according to the level number N of the PAM signal and the number M of equalized signals in the decision value set The number of decision circuits and the number of decision thresholds of the decision equalization device, where N and M both take positive integers.
  • the decision equalization device uses a third formula to determine the number of decision circuits and the number of decision thresholds according to the level number N of the PAM signal and the number M of equalized signals in the decision value set, wherein the first The three formulas are:
  • the S is used to indicate the number of the decision circuits
  • the P is used to indicate the number of the decision thresholds
  • the N is used to indicate the level number of the PAM signal
  • the M is used to indicate the The number of equalized signals in the decision value set.
  • the decision equalization device determining the decision value of the input signal according to the first group of equalization expectation values, the first group of decision thresholds and the input signal includes:
  • the decision equalization device determines the decision value of the input signal by using maximum likelihood sequence estimation according to the first group of decision thresholds, the first group of equalization expectation values and the input signal.
  • the decision equalization device may adopt the following technical solution when determining the decision circuit of the input signal: the decision equalization device determines the decision circuit of the input signal according to a decision value set, and the decision value set includes at least one decision value , the occurrence moment of the at least one decision value is earlier than the occurrence moment of the input signal.
  • the number of decision values in the decision value set can be determined according to the structure of the decision equalization device. For example, if the decision equalization device has a tap structure, the decision value set includes the decision value output at the first moment . If the decision equalization device is a two-tap structure, the decision value set includes the decision value output at the second moment. Wherein, the second moment is earlier than the first moment, and the first moment is earlier than the occurrence moment of the current input signal.
  • the present application provides a signal decision equalization method, which specifically includes: the decision equalization device acquires an input signal, and the input signal is a PAM signal or a pre-equalized signal output by the PAM signal after pre-equalization (for example, the The PAM signal is pre-equalized by a feedforward equalizer (feed forward equalizer, FFE) output pre-equalized signal); then the decision equalizer determines the decision circuit of the input signal; at the same time, the decision equalizer also obtains the first decision circuit corresponding to the decision circuit A set of decision thresholds and a first equalization expectation value; then the decision equalization device determines the decision value of the input signal according to the first group of equalization expectation values, the first group of decision thresholds and the input signal, and outputs the decision value; at the same time, the decision The equalization signal updates all the equalization expected values in the first group of equalized expected values according to the decision value and the input signal to obtain a second group of equalized expected values; finally, the decision equalization device
  • the process of updating all the decision thresholds in the decision circuit can be implemented by means of existing technologies, and details are not described here.
  • the decision equalization device iteratively updates all the decision thresholds of the decision circuit according to the equalized signal output by the decision circuit, that is, the update iterations of each decision circuit are independent of each other, but the decision in each decision circuit
  • the threshold is associated iterative update, which realizes the independent iterative update of each judgment circuit, which can effectively realize the optimal equalization and judgment of the signal, thereby improving the equalization performance and reducing the bit error rate after equalization.
  • the decision equalization device updates all the balance expectation values in the first group of balance expectation values according to the decision value and the input signal to obtain the second group of balance expectation values
  • the following possible implementation methods may be adopted:
  • the decision equalization device updates the equalization expectation value corresponding to the iterative decision circuit after each decision equalization is performed to obtain a decision value.
  • the decision equalization device updates and iterates the equalization expectation value after a certain equalization expectation value on the decision circuit performs a preset number of decision equalizations (that is, the decision times of a certain equalization expectation value on the decision circuit reach the preset number of times). Set the number of times, for example, after the decision value corresponding to the balanced expected value EV 33 has been output 4 times, the balanced expected value EV 33 is updated to be EV 33, new ).
  • the decision equalization device updates and iterates the equalization expectation value corresponding to the decision circuit after a preset time period.
  • the decision equalization device updates the first group of equalization expected values to the second group of equalization expectation values
  • the decision equalization device updates the first group of decision thresholds according to each equalization expectation value in the second group of equalization expectation values. All the decision thresholds of are obtained the second set of decision thresholds.
  • the decision equalization device may also receive an initial convergence parameter output by the DFE system, and the initial convergence parameter is used as an initial equalization expected value of the input signal when performing decision equalization in the decision equalization device provided in this embodiment.
  • the reliability of the equalized expected value and the decision threshold can be ensured when the initial decision equalization is performed, and the convergence process of the equalized expected value and the decision threshold can be accelerated.
  • the decision equalization device may also receive an adaptive parameter output by the FFE, and the adaptive parameter is used as an initial equalization expectation value of the input signal when performing decision equalization in the decision equalization device provided in this embodiment.
  • the reliability of the equalized expected value and the decision threshold can be ensured when the initial decision equalization is performed, and the convergence process of the equalized expected value and the decision threshold can be accelerated.
  • this embodiment is applied to PAM signals, and when the decision equalization device performs signal decision equalization, it is necessary to determine the decision equalization device according to the level number N of the PAM signal and the number M of equalized signals in the decision value set The number of decision circuits and the number of decision thresholds of the decision equalization device, where N and M both take positive integers.
  • the decision equalization device uses a third formula to determine the number of decision circuits and the number of decision thresholds according to the level number N of the PAM signal and the number M of equalized signals in the decision value set, wherein the first The three formulas are:
  • the S is used to indicate the number of the decision circuits
  • the P is used to indicate the number of the decision thresholds
  • the N is used to indicate the level number of the PAM signal
  • the M is used to indicate the The number of equalized signals in the decision value set.
  • the decision equalization device determining the decision value of the input signal according to the first group of equalization expectation values, the first group of decision thresholds and the input signal includes:
  • the decision equalization device determines the decision value of the input signal by using maximum likelihood sequence estimation according to the first group of decision thresholds, the first group of equalization expectation values and the input signal.
  • the decision equalization device may adopt the following technical solution when determining the decision circuit of the input signal: the decision equalization device determines the decision circuit of the input signal according to a decision value set, and the decision value set includes at least one decision value , the occurrence moment of the at least one decision value is earlier than the occurrence moment of the input signal.
  • the number of decision values in the decision value set can be determined according to the structure of the decision equalization device. For example, if the decision equalization device has a tap structure, the decision value set includes the decision value output at the first moment . If the decision equalization device is a two-tap structure, the decision value set includes the decision value output at the second moment. Wherein, the second moment is earlier than the first moment, and the first moment is earlier than the occurrence moment of the current input signal.
  • the embodiment of the present application provides a signal decision equalization device, which specifically includes: the decision equalization device acquires an input signal, the input signal is a pulse amplitude modulation (PAM) signal or the PAM signal is pre-prepared The pre-equalized signal output after equalization (such as the pre-equalized signal output by the PAM signal through a feedforward equalizer (feed forward equalizer, FFE) pre-equalized output); then the decision equalization device determines the decision circuit of the input signal; at the same time the The decision equalization device also obtains a first set of decision thresholds and a first equalization expectation corresponding to the decision circuit, the distribution of the first set of decision thresholds is an asymmetric distribution, and the distribution of the first set of equalization expectations is an asymmetric distribution; then The decision equalization device determines the decision value of the input signal according to the first group of equalization expectation values, the first group of decision thresholds and the input signal.
  • PAM pulse amplitude modulation
  • FFE feed forward equalizer
  • the distribution of the decision threshold and equalization expected value in the decision equalization device is related to the nonlinear characteristics of the signal, and presents an asymmetric distribution, so that the optimal equalization and decision of the signal can be realized more effectively, and then the equalization can be improved. Performance, reduce the bit error rate after equalization.
  • the number of decision thresholds in the first group of decision thresholds is equal to the number of levels of the PAM signal minus one;
  • the number of equalization expected values in the first set of equalized expected values is equal to the number of levels of the PAM signal.
  • the first group of equalization expectation values is obtained by updating the equalization expectation values at the previous moment according to the input signal at the previous moment and the decision value of the input signal decision output at the previous moment, and the previous moment is earlier than the The occurrence moment of the input signal, the first group of decision thresholds is obtained by updating according to the first group of equalization expectation values;
  • the first group of equalization expectation values is obtained by updating the equalization expectation values at the first N moments according to the input signal at the first N moments and the judgment output of the input signal at the first N moments, and the first N moments are earlier than the The occurrence moment of the input signal, the first group of decision thresholds is obtained by updating according to the first group of equalization expectation values.
  • the decision circuit is included in a set of decision circuits, the decision thresholds of the decision circuits in the set of decision circuits are different, and the expected equalization values of the decision circuits in the set of decision circuits are different. That is, each decision circuit in the decision equalization device can be adjusted independently, so that the optimal equalization and decision can be realized for nonlinear signals, thereby improving the equalization performance and reducing the bit error rate after equalization.
  • the decision equalization device may adopt the following technical solution when determining the decision circuit of the input signal: the decision equalization device determines the decision circuit of the input signal according to a decision value set, and the decision value set includes at least one decision value , the occurrence moment of the at least one decision value is earlier than the occurrence moment of the input signal.
  • the number of decision values in the decision value set can be determined according to the structure of the decision equalization device. For example, if the decision equalization device has a tap structure, the decision value set includes the decision value output at the first moment . If the decision equalization device is a two-tap structure, the decision value set includes the decision value output at the second moment. Wherein, the second moment is earlier than the first moment, and the first moment is earlier than the occurrence moment of the current input signal.
  • the present application provides a decision equalization device, and the system has the function of realizing the behavior of the decision equalization device in the first aspect above.
  • This function may be implemented by hardware, or may be implemented by executing corresponding software on the hardware.
  • the hardware or software includes one or more modules corresponding to the above functions.
  • the device for decision equalization includes a unit or a module for performing each step of the above first aspect.
  • the decision equalization device includes: an acquisition module for an input signal, the input signal is a pulse amplitude modulation (pulse amplitude modulation, PAM) signal or a pre-equalized signal output by the PAM signal after pre-equalization;
  • PAM pulse amplitude modulation
  • a processing module configured to determine a decision circuit for the input signal
  • the obtaining module is also used to obtain a first group of decision thresholds and a first group of equalization expectation values of the decision circuit;
  • the processing module is further configured to determine a decision value of the input signal according to the first set of equalization expectation values, the first set of decision thresholds, and the input signal;
  • an output module configured to output the decision value
  • the processing module is further configured to update the first balanced expected value in the first group of balanced expected values to a second balanced expected value to obtain a second balanced expected value according to the decision value and the input signal, and the first balanced expected value is The equalization expectation value corresponding to the decision value; updating at least one decision threshold in the first set of decision thresholds according to the second equalization expectation value to obtain a second set of decision thresholds, the second set of decision thresholds and the second set of decision thresholds
  • the equalization expectation value is used for the next decision equalization of the decision circuit.
  • a storage module is also included for storing necessary program instructions and data of the decision equalization device.
  • the device for decision equalization includes: a processor and a transceiver, where the processor is configured to support the device for decision equalization to perform corresponding functions in the method provided by the foregoing first aspect.
  • the transceiver is used to instruct communication between the decision equalization device and other devices, receive the PAM signal output by the signal input device, and output the equalization signal of the PAM signal.
  • the device may further include a memory, which is used to be coupled with the processor, and stores necessary program instructions and data of the decision equalization device.
  • the chip when the system is a chip in a decision equalization device, the chip includes: a processing module and a transceiver module.
  • the transceiver module can be, for example, an input/output interface, a pin, or a circuit on the chip, and the transceiver module is used to obtain an input signal, the input signal is a pulse amplitude modulation (pulse amplitude modulation, PAM) signal or the PAM signal
  • PAM pulse amplitude modulation
  • the processing module can be, for example, a processor, and the processor is used to determine the decision circuit of the input signal;
  • the transceiver module also uses Obtaining the first set of decision thresholds and the first set of equalization expected values of the decision circuit, and sending the first set of decision thresholds and the first set of equalized expected values to the processing module;
  • the processing module can execute the computer-executable instructions stored in the storage unit, so as to support the decision equalization device to execute the method provided in the first aspect above.
  • the storage unit may be a storage unit in the chip, such as a register, a cache, etc., or a storage unit located outside the chip, such as a read-only memory (read-only memory, ROM) or a Other types of static storage devices that store static information and instructions, random access memory (random access memory, RAM), etc.
  • the system includes a communication interface and a logic circuit, the communication interface is used for an input signal, the input signal is a pulse amplitude modulation (pulse amplitude modulation, PAM) signal or the PAM signal is pre-equalized The output pre-equalization signal; the logic circuit is used to determine the decision circuit of the input signal; the communication interface is also used to obtain the first group of decision thresholds and the first group of equalization expected values of the decision circuit; the logic circuit, It is also used to determine the decision value of the input signal according to the first group of equalization expectation values, the first group of decision thresholds and the input signal; the communication interface is also used to output the decision value; the logic circuit, It is also used to update the first balanced expected value in the first group of balanced expected values according to the decision value and the input signal to obtain a second balanced expected value, and the first balanced expected value corresponds to the decision value The equalization expectation value; update at least one decision threshold in the first set of decision thresholds according to the second equalization expectation value to obtain a pulse amplitude
  • the processor mentioned in any of the above can be a general-purpose central processing unit (Central Processing Unit, CPU), a microprocessor, a specific application integrated circuit (application-specific integrated circuit, ASIC), or one or more An integrated circuit for controlling the program execution of the data transmission method in the above aspects.
  • CPU Central Processing Unit
  • ASIC application-specific integrated circuit
  • the embodiment of the present application provides a decision equalization device, and the system has the function of implementing the behavior of the decision equalization device in the second aspect above.
  • This function may be implemented by hardware, or may be implemented by executing corresponding software on the hardware.
  • the hardware or software includes one or more modules corresponding to the above functions.
  • the device for decision equalization includes a unit or module for performing each step of the above second aspect.
  • the decision equalization device includes: an acquisition module, configured to acquire an input signal, the input signal is a pulse amplitude modulation (pulse amplitude modulation, PAM) signal or a pre-equalized signal output by the PAM signal after pre-equalization;
  • PAM pulse amplitude modulation
  • a processing module configured to determine a decision circuit for the input signal
  • the obtaining module is also used to obtain a first group of decision thresholds and a first group of equalization expectation values of the decision circuit;
  • the processing module is further configured to determine a decision value of the input signal according to the first set of equalization expectation values, the first set of decision thresholds, and the input signal;
  • an output module configured to output the decision value
  • the processing module is further configured to update all equalization expected values in the first set of equalized expected values according to the decision value and the input signal to obtain a second set of equalized expected values; update the first set of equalized expected values according to the second equalized expected value All the decision thresholds in the decision thresholds obtain a second group of decision thresholds, and the second group of decision thresholds and the second group of equalization expectation values are used for next decision equalization of the decision circuit.
  • a storage module is also included for storing necessary program instructions and data of the decision equalization device.
  • the device for decision equalization includes: a processor and a transceiver, where the processor is configured to support the device for decision equalization to perform corresponding functions in the method provided in the second aspect above.
  • the transceiver is used to instruct communication between the decision equalization device and other devices, receive the PAM signal output by the signal input device, and output the equalization signal of the PAM signal.
  • the device may further include a memory, which is used to be coupled with the processor, and stores necessary program instructions and data of the decision equalization device.
  • the chip when the system is a chip in a decision equalization device, the chip includes: a processing module and a transceiver module.
  • the transceiver module can be, for example, an input/output interface, a pin, or a circuit on the chip, and the transceiver module is used to obtain an input signal, the input signal is a pulse amplitude modulation (pulse amplitude modulation, PAM) signal or the PAM signal
  • PAM pulse amplitude modulation
  • the processing module can be, for example, a processor, and the processor is used to determine the decision circuit of the input signal;
  • the transceiver module also uses Obtaining the first set of decision thresholds and the first set of equalization expected values of the decision circuit, and sending the first set of decision thresholds and the first set of equalized expected values to the processing module;
  • the processing module can execute the computer-executable instructions stored in the storage unit, so as to support the decision equalization device to execute the method provided by the second aspect above.
  • the storage unit may be a storage unit in the chip, such as a register, a cache, etc., or a storage unit located outside the chip, such as a read-only memory (read-only memory, ROM) or a Other types of static storage devices that store static information and instructions, random access memory (random access memory, RAM), etc.
  • the system includes a communication interface and a logic circuit, and the communication interface is used to obtain an input signal, the input signal is a pulse amplitude modulation (pulse amplitude modulation, PAM) signal or the PAM signal is pre-equalized The post-output pre-equalization signal; the logic circuit is used to determine the decision circuit of the input signal; the communication interface is also used to obtain the first group of decision thresholds and the first group of equalization expected values of the decision circuit; the logic circuit is also used to determine the decision value of the input signal according to the first group of equalization expectation values, the first group of decision thresholds and the input signal; the communication interface is also used to output the decision value; the logic circuit , is also used to update all the balanced expected values in the first group of balanced expected values according to the decision value and the input signal to obtain a second group of balanced expected values; update the first group of decision thresholds according to the second balanced expected value All decision thresholds obtain a second group of decision thresholds, and the second group of decision thresholds
  • the processor mentioned in any of the above-mentioned places may be a CPU, a microprocessor, an ASIC, or one or more integrated circuits for controlling the program execution of the data transmission method in the above-mentioned aspects.
  • the embodiment of the present application provides a decision equalization device, which has the function of realizing the behavior of the decision equalization device in the second aspect above.
  • This function may be implemented by hardware, or may be implemented by executing corresponding software on the hardware.
  • the hardware or software includes one or more modules corresponding to the above functions.
  • the apparatus for decision equalization includes a unit or a module for performing each step of the above third aspect.
  • the decision equalization device includes: an acquisition module, configured to acquire an input signal, the input signal being a PAM signal or a pre-equalized signal output by the PAM signal after pre-equalization; a processing module, configured to determine the input signal Judgment circuit; the acquisition module is also used to acquire a first group of decision thresholds and a first group of equalization expectation values of the decision circuit, the distribution of the first group of decision thresholds is an asymmetric distribution, and the first group of equalization expectation values The distribution of is an asymmetric distribution; the processing module is further configured to determine the decision value of the input signal according to the first group of equalization expectation values, the first group of decision thresholds and the input signal.
  • a storage module is also included for storing necessary program instructions and data of the decision equalization device.
  • the device for decision equalization includes: a processor and a transceiver, where the processor is configured to support the device for decision equalization to perform corresponding functions in the method provided in the third aspect above.
  • the transceiver is used to instruct communication between the decision equalization device and other devices, receive the PAM signal output by the signal input device, and output the decision value of the PAM signal.
  • the device may further include a memory, which is used to be coupled with the processor, and stores necessary program instructions and data of the decision equalization device.
  • the chip when the system is a chip in a decision equalization device, the chip includes: a processing module and a transceiver module.
  • the transceiver module can be, for example, an input/output interface, a pin, or a circuit on the chip, and the transceiver module is used to obtain an input signal, which is a PAM signal or a pre-equalized output of the PAM signal after pre-equalization signal, and transmit the input signal to the processing module;
  • the processing module may be, for example, a processor, and the processor is used to determine the decision circuit of the input signal;
  • the transceiver module is also used to obtain the first decision circuit of the decision circuit A group of decision thresholds and a first group of equalization expected values, and the first group of decision thresholds and the first group of equalized expected values are sent to the processing module;
  • the decision threshold and the input signal determine the decision value of the input signal; the transceiver module is also used to output the decision value.
  • the processing module can execute the computer-executable instructions stored in the storage unit, so as to support the decision equalization device to execute the method provided by the second aspect above.
  • the storage unit may be a storage unit in the chip, such as a register, a cache, etc., or a storage unit located outside the chip, such as a ROM or other types of static memory that can store static information and instructions. Storage devices, RAM, etc.
  • the system includes a communication interface and a logic circuit, where the communication interface is used to obtain an input signal, where the input signal is a PAM signal or a pre-equalized signal output by the PAM signal after pre-equalization; the logic The circuit is used to determine the decision circuit of the input signal; the communication interface is also used to obtain the first group of decision thresholds and the first group of equalization expected values of the decision circuit; the logic circuit is also used to The group equalization expectation value, the first group of decision thresholds and the input signal determine the decision value of the input signal; the communication interface is also used to output the decision value.
  • the processor mentioned in any of the above-mentioned places may be a CPU, a microprocessor, an ASIC, or one or more integrated circuits for controlling the program execution of the data transmission method in the above-mentioned aspects.
  • the embodiments of the present application provide a computer-readable storage medium, where the computer storage medium stores computer instructions, and the computer instructions are used to execute the method in any possible implementation mode of any one of the above-mentioned aspects.
  • the embodiments of the present application provide a computer program product including instructions, which, when run on a computer, cause the computer to execute the method in any one of the above aspects.
  • the present application provides a chip system, which includes a processor, configured to support the decision equalization device to implement the functions involved in the above aspect, such as generating or processing the data and/or information involved in the above method .
  • the system-on-a-chip further includes a memory, and the memory is used to store necessary program instructions and data of the decision equalization device, so as to realize functions in any one of the above-mentioned aspects.
  • the system-on-a-chip may consist of chips, or may include chips and other discrete devices.
  • an embodiment of the present application provides a communication system, the system including the decision equalization apparatus in the above aspect.
  • FIG. 1 is a schematic diagram of a DFE architecture of one tap
  • FIG. 2 is a schematic diagram of an application scenario of an embodiment of the present application
  • FIG. 3a is a schematic diagram of a functional module of a decision equalization device in an embodiment of the present application.
  • FIG. 3b is a schematic diagram of another functional module of the decision equalization device in the embodiment of the present application.
  • FIG. 3c is a schematic diagram of another functional module of the decision equalization device in the embodiment of the present application.
  • FIG. 3d is a schematic diagram of another functional module of the decision equalization device in the embodiment of the present application.
  • FIG. 4 is a schematic diagram of a signal decision equalization in which the decision equalization device and the FFE are combined in the embodiment of the present application;
  • FIG. 5 is a schematic structural diagram of a decision equalization device in an embodiment of the present application.
  • FIG. 6 is a schematic diagram of an embodiment of a decision equalization method for a nonlinear signal in an embodiment of the present application
  • FIG. 7 is a schematic diagram of a decision equalization of a nonlinear signal in an embodiment of the present application.
  • FIG. 8 is another schematic diagram of the architecture of the decision equalization of the nonlinear signal in the embodiment of the present application.
  • FIG. 9 is a schematic diagram of a decision circuit and a decision threshold in an embodiment of the present application.
  • FIG. 10 is an exemplary schematic diagram of a decision circuit and a decision threshold in an embodiment of the present application.
  • FIG. 11 is a schematic diagram of an architecture combining an FFE and a decision equalization device in an embodiment of the present application.
  • FIG. 12 is a schematic diagram of the structure of the combination of FFE, DFE and decision equalization device in the embodiment of the present application;
  • FIG. 13 is a schematic diagram of an iterative update of a decision threshold and an equilibrium expected value in an embodiment of the present application
  • Figures 14 to 17 are performance comparison diagrams of the decision equalization method for non-linear signals in the embodiment of the present application and the decision equalization under the DFE architecture;
  • FIG. 18 is a schematic diagram of a combination of FFE, decision equalization device and MLSE;
  • Fig. 19 is a calculation architecture diagram of the branch metric value of MLSE under the combination of FFE, decision equalization device and MLSE;
  • Figure 20 is a working principle diagram of MLSE
  • FIG. 21 is a comparison diagram of the equalization performance of the combined architecture of the decision equalization device and MLSE in the embodiment of the application and the traditional MLSE;
  • FIG. 22 is a schematic structural diagram of a decision equalization device in an embodiment of the present application.
  • FIG. 23 is another schematic structural diagram of a decision equalization device in an embodiment of the present application.
  • the naming or numbering of the steps in this application does not mean that the steps in the method flow must be executed in the time/logic sequence indicated by the naming or numbering.
  • the execution order of the technical purpose is changed, as long as the same or similar technical effect can be achieved.
  • the division of units presented in this application is a logical division. In actual application, there may be other division methods. For example, multiple units can be combined or integrated in another system, or some features can be ignored. , or not, in addition, the shown or discussed mutual coupling or direct coupling or communication connection may be through some interfaces, and the indirect coupling or communication connection between units may be electrical or other similar forms, this Applications are not limited.
  • the units or subunits described as separate components may or may not be physically separated, may or may not be physical units, or may be distributed into multiple circuit units, and some or all of them may be selected according to actual needs unit to realize the purpose of the application scheme.
  • At least one item (piece) of a, b, or c can represent: a, b, c, a-b, a-c, b-c, or a-b-c, where a, b, c can be single or multiple .
  • the optical link transmission signal has gradually transitioned from NRZ to pulse amplitude modulation (PAM).
  • PAM pulse amplitude modulation
  • the multi-level modulation method makes the nonlinear characteristics of various optoelectronic devices and channels begin to appear, which causes The reason for is mainly the interaction between the chirp at the transmitting end in the optical link and the fiber dispersion.
  • CTLE continuous time linear equalizer
  • nonlinear characteristics in the link not only introduce intersymbol interference, but also lead to signal distortion, which greatly affects the transmission characteristics of the system and hinders the further improvement of the system data transmission rate.
  • the traditional linear adaptive filter can't deal with this characteristic well because the linear characteristic limits its ability to approximate nonlinear function, which makes the filtering performance unsatisfactory.
  • nonlinear filtering theory has become a research hotspot in the industry. For the current 100Gbps and future higher-speed transmission systems, nonlinear equalization will become a key technical capability.
  • DFE is a commonly used intersymbol interference equalizer.
  • the one-tap DFE architecture of the PAM-4 signal shown in Figure 1 the received FFE output value y k is respectively judged in the 4-way judgment circuit to obtain an equalized signal, and then according to the last signal The decision value of selects the final decision value corresponding to this y k .
  • the decision thresholds of the four decision circuits are the same. That is, the decision threshold of each path is the same.
  • the decision threshold of each decision circuit is (-2, 0, +2) as shown in Figure 1, and at the second moment after the decision threshold is updated, each decision The decision threshold of the circuit is (-1.5, 0, +1.5). Since the decision thresholds of each decision circuit are the same, there is no difference in equalization for signals of different levels, and the nonlinear characteristics of the channel cannot be equalized.
  • PAM signal that is, a signal generated by PAM modulation.
  • the PAM modulation refers to a modulation method in which the amplitude of the pulse carrier varies with the baseband signal.
  • the pre-equalized signal is an equalized signal obtained by equalizing the PAM signal through other equalizers before being input to the decision equalization device provided in the embodiment of the present application.
  • the PAM signal can be equalized by the FFE to obtain an equalized signal.
  • Judgment threshold the median value of adjacent level amplitudes.
  • the number of decision thresholds is related to the number of levels of the PAM signal. For example, the four levels of the PAM-4 signal are (+3, +1, -1, -3), the number of decision thresholds in the decision device is 3, and the decision thresholds are (+2, 0, -2) .
  • Equalization Expected Value It is the expected result value after the equalizer equalizes the signal under the current configuration.
  • the equalization expectation value may be (+30, +10, -10, -30).
  • Judgment value the decision result corresponding to the signal to be equalized is determined in the decision device according to the decision threshold.
  • an exemplary value of the decision value may be (+3, +1, -1, -3).
  • the embodiment of the present application provides the following technical solution: the decision equalization device obtains an input signal, the input signal is a PAM signal or a pre-equalized signal output by the PAM signal after pre-equalization; then the decision equalization device Determine the decision circuit of the input signal; at the same time, the decision equalization device also obtains a first set of decision thresholds and a first equalization expectation value corresponding to the decision circuit; And the input signal determines the decision value of the input signal, and outputs the decision value; at the same time, the decision equalization device updates the first equalization expectation value in the first group of equalization expectation values according to the decision value and the input signal to the second equalization expectation value to obtain The second set of equalization expected values, wherein the first equalized expected value is the equalized expected value corresponding to the decision value; finally, the decision equalization device updates at least one decision threshold in the first set of decision thresholds according to the second equalized expected value to obtain the second set of A decision threshold, wherein the second set of decision thresholds
  • A Chip-to-chip in the interface board (line processing unit, LPU) (such as fabric interface controller (fabric interface controller, FIC), network chip (networking processor, NP), media access control (media access control, MAC) );
  • LPU line processing unit
  • FIC fabric interface controller
  • NP network chip
  • MAC media access control
  • the functional module architecture of the decision equalization device may be as shown in FIG. 3a.
  • the PAM signal is initially equalized by the FFE equalizer to obtain an equalized pre-equalized signal (as the input signal of the decision equalization device).
  • the decision equalization device receives the pre-equalization signal output by the FFE, and outputs a final decision value through a decision module and a decision value selection module.
  • the specific process of the signal passing through the judgment module and the judgment value selection module is as follows: all the judgment circuits in the judgment module re-equalize the pre-equalized signal and output a judgment value, and the judgment value selection module is used to The decision value at one moment determines the final decision value.
  • the functional module architecture of the decision equalization device can be implemented in a specific chip in the form of an IP core.
  • the specific chip can be a switch chip or an interface chip used in a router, a switch, an optical transport network (OTN) transmission device, or any chip that requires a high-speed communication interface.
  • OTN optical transport network
  • the sequence of realization of the schemes is different, and the functional module architecture of the decision equalization device can also be shown in Figure 3b.
  • the PAM signal first undergoes preliminary equalization by the FFE equalizer to obtain an equalized pre-equalized signal (as the decision equalizer device input signal).
  • the decision equalization device receives the pre-equalized signal output by the FFE, and outputs the final decision value through the decision value selection module and the decision module.
  • the specific process when the signal passes through the judgment value selection module and the judgment module is: the judgment value selection module determines the judgment circuit of the signal according to the judgment value at the previous moment; Equalize again to get the final decision value.
  • the functional module architecture of the decision equalization device can be implemented in a specific chip in the form of an IP core.
  • the specific chip can be a switch chip or an interface chip used in a router, a switch, an optical transport network (OTN) transmission device, or any chip that requires a high-speed communication interface.
  • OTN optical transport network
  • the functional module architecture of the decision equalization device may be as shown in FIG. 3c.
  • the decision equalization device receives a PAM signal (the PAM signal is used as an input signal of the decision equalization module), and outputs a final decision value through a decision module and a decision value selection module.
  • the specific process of the PAM signal passing through the decision module and the decision value selection module is as follows: all the decision circuits in the decision module equalize the PAM signal and output a decision value, and the decision value selection module is used to The decision value at each moment determines the final decision value and outputs the final decision value.
  • the functional module architecture of the decision equalization device can be implemented in a specific chip in the form of an IP core.
  • the specific chip can be a switch chip or an interface chip used in a router, a switch, an optical transport network (OTN) transmission device, or any chip that requires a high-speed communication interface.
  • OTN optical transport network
  • the functional module architecture of the decision equalization device may also be as shown in FIG. 3d.
  • the decision equalization device receives a PAM signal (the PAM signal is used as an input signal of the decision equalization module), and outputs a final decision value through a decision module and a decision value selection module.
  • the specific flow of the PAM signal when passing through the decision module and the decision value selection module is: the decision value selection module determines the decision circuit of the PAM signal according to the decision value at the last moment; then the decision module selects the decision circuit for the PAM signal Perform equalization to obtain the final decision value.
  • the functional module architecture of the decision equalization device can be implemented in a specific chip in the form of an IP core.
  • the specific chip can be a switch chip or an interface chip applied in a router, a switch, an optical transport network (OTN) transmission device, and any chip that requires a high-speed communication interface.
  • OTN optical transport network
  • FIG. 4 which mainly includes FFE and a decision equalization device.
  • the FFE performs preliminary equalization on the PAM signal to obtain an equalized pre-equalized signal, and then the judgment module and the judgment value selection module in the judgment equalization device perform judgment equalization on the pre-equalized signal again and output a judgment value.
  • FIG. 5 is a schematic diagram of a hardware structure of a decision equalization device in an embodiment of the present application.
  • the decision equalization device includes at least a processor 501 , a memory 502 , and a transceiver 503 , and the memory 502 is further used to store instructions 5021 and data 5022 .
  • the decision equalization device may further include an I/O (Input/Output, Input/Output) interface 504 and a bus 505 .
  • the transceiver 503 further includes a transmitter 5031 and a receiver 5032 .
  • the processor 501 , the transceiver 503 , the memory 502 and the I/O interface 504 are communicatively connected to each other through the bus 505 .
  • Processor 501 may be a general processor, such as but not limited to, a central processing unit (central processing unit, CPU), and may also be a special purpose processor, such as but not limited to, a digital signal processor (digital signal processor, DSP), application Application Specific Integrated Circuit (ASIC) and Field Programmable Gate Array (FPGA), etc.
  • the processor 501 may also be a neural network processing unit (neural processing unit, NPU).
  • the processor 501 may also be a combination of multiple processors.
  • the processor 501 may be configured to execute relevant steps of the method for generating an Ethernet packet in the subsequent method embodiments.
  • the processor 501 may be a processor specially designed to perform the above steps and/or operations, or may be a processor that performs the above steps and/or operations by reading and executing instructions 5021 stored in the memory 502.
  • the processor 501 The data 5022 may be needed during the execution of the above steps and/or operations.
  • the transceiver 503 includes a transmitter 5031 and a receiver 5032 .
  • the transmitter 5031 and the receiver 5032 can perform operations performed by the receiving module or the sending module in the decision equalization device when the decision equalization method in the subsequent method embodiments is applied to the decision equalization device.
  • the transceiver 503 is used to support the decision equalization apparatus to perform the aforementioned receiving function and sending function.
  • a processor having a processing function is regarded as the processor 501 .
  • the receiver 5032 can also be called an input port, a receiving circuit, etc., and the transmitter 5031 can be called a transmitter or a transmitting circuit, etc.
  • the processor 501 can be used to execute the instructions stored in the memory 502 to control the transceiver 503 to receive messages and/or send messages, so as to complete the function of the decision equalization device in the method embodiment of the present application.
  • the function of the transceiver 503 may be implemented by a transceiver circuit or a dedicated chip for transceiver.
  • receiving a message by the transceiver 503 may be understood as an input message by the transceiver 503, and sending a message by the transceiver 503 may be understood as an output message by the transceiver 503.
  • Memory 502 can be various types of storage media, such as random access memory (Random Access Memory, RAM), read-only memory (Read Only Memory, ROM), non-volatile RAM (Non-Volatile RAM, NVRAM), can Programmable ROM (Programmable ROM, PROM), erasable PROM (Erasable PROM, EPROM), electrically erasable PROM (Electrically Erasable PROM, EEPROM), flash memory, optical memory and registers, etc.
  • the memory 502 is specifically used to store instructions 5021 and data 5022.
  • the processor 501 can execute the steps and/or operations described in the method embodiments of the present application by reading and executing the instructions 5021 stored in the memory 502.
  • the data 5022 may be required during the operations and/or steps in the method embodiments.
  • the decision equalization apparatus may further include an I/O interface 504, which is used for receiving instructions and/or data from peripheral devices and outputting instructions and/or data to peripheral devices.
  • I/O interface 504 is used for receiving instructions and/or data from peripheral devices and outputting instructions and/or data to peripheral devices.
  • GSM Global System of Mobile Communication
  • CDMA Code Division Multiple Access
  • WCDMA Wideband Code Division Multiple Access
  • LTE Long Term Evolution
  • FDD Frequency Division Duplex
  • TDD Time Division Duplex
  • UMTS Universal Mobile Telecommunication System
  • 5G communication system and future wireless communication system, etc.
  • An embodiment of the signal decision equalization method in the embodiment of the present application includes:
  • the decision equalization device acquires an input signal, where the input signal is a PAM signal or a pre-equalized signal output from the PAM signal after pre-equalization.
  • the decision equalization device receives the input signal, wherein the input signal may be a PAM signal or an equalized signal that has undergone preliminary equalization by the FFE. For example, if the equalized signal output by the FFE is 30 at the first moment, then the input signal received by the decision equalization device is 30. Or at the first moment, the judging device directly receives the PAM signal that has not been equalized.
  • the decision equalization device determines a decision circuit of the input signal according to a decision value set, where the decision value set includes at least one decision value, and an occurrence time of the at least one decision value is earlier than an occurrence time of the input signal.
  • the decision equalization device acquires a set of decision values between occurrence times of the input signal, and then determines a decision circuit for the input signal according to the decision values corresponding to the set of decision values.
  • the decision circuit is the decision circuit that finally selects the decision value for the decision equalization device, but it is not limited here whether other decision circuits perform decision equalization on the input signal. That is, the working mode of the decision equalization device includes the following possible situations:
  • the decision equalization device After the decision equalization device receives the input signal, it inputs the input signal to all the decision circuits, and the decision circuits all perform decision equalization and output a decision value; then the decision equalization device according to the Determining the input signal selects the decision circuit for the final decision value.
  • the decision equalization device After the decision equalization device receives the input signal, it determines the decision circuit for selecting the final decision value for the input signal according to the decision value set; and then inputs the input signal into the decision circuit for decision equalize, and output the corresponding decision value.
  • the decision value set includes at least one equalized signal.
  • the decision value set includes an equalized signal.
  • the equalized signal in the decision value set is the equalized signal at time d k-1 .
  • the PAM-4 is used to indicate the number of levels of the PAM signal, and the PAM signal may include the number of levels in various situations, for example, the number of levels may be 8.
  • the level number and the number of equalized signals in the decision value set can affect the number of decision circuits and the number of decision thresholds in the decision equalization device, which specifically includes: the decision equalization device according to the level number of the PAM signal N and the number M of equalized signals in the decision value set determine the number of decision circuits and the number of decision thresholds using a third formula, wherein the third formula is:
  • the S is used to indicate the number of the decision circuits
  • the P is used to indicate the number of the decision thresholds
  • the N is used to indicate the level number of the PAM signal
  • the M is used to indicate the The number of equalized signals in the set of decision values (also called the number of taps of the equalization architecture, when there is one tap, the value of M is 1, and when there are two taps, the value of M is 2).
  • Its decision equalization architecture can be shown in FIG. 9 .
  • the decision circuit in the decision equalization device may be as shown in FIG. 7 and FIG.
  • each decision circuit includes 3 decision thresholds (2, 0, -2), and there are 12 decision thresholds in total in the decision equalization device. If the number of levels is 4, the decision value set includes 2 equalization signals, and the decision circuit in the decision equalization device can be 16-way decision circuits (+3+3, +3+1, +3) as shown in Figure 10 -1, +3-3, +1+3, +1+1, +1-1, +1-3, -1+3, -1+1, -1-1, -1-3, -3 +3, -3+1, -3-1, -3-3), each decision circuit includes 3 decision thresholds (2, 0, -2), and there are 64 decision thresholds in total in the decision equalization device.
  • the decision equalization apparatus acquires a first set of decision thresholds and a first set of equalization expectation values of the decision circuit.
  • the decision equalization device acquires the first group of decision thresholds and the first group of equalization expectation values corresponding to the decision circuit at the current moment.
  • the decision equalization device can be combined with the FFE to perform signal decision equalization, as shown in FIG.
  • the initial expected value in the decision equalization device may be an adaptive parameter output by the FFE.
  • the initial expected value in the decision equalization device may be a convergence parameter output by the DFE.
  • the initial expected value in the decision equalization device may also be preset, which is not specifically limited here.
  • the decision equalization apparatus determines a decision value of the input signal according to the first group of equalization expectation values, the first group of decision thresholds, and the input signal.
  • the decision equalization device performs decision equalization on the input signal according to the first group of equalization expectation values and the first group of decision thresholds, and outputs a decision value of the input signal.
  • the first set of equalization expectations is (+30, +10, -10, -30)
  • the first set of decision thresholds are (+20, 0, -20)
  • the decision value is (+3 , +1, -1, -3)
  • the input signal is 25, then the decision value is +3, and the equilibrium expected value corresponding to the decision value is +30.
  • the median value of the equalization expected value is the decision threshold, and the decision value corresponding to the decision circuit may have a corresponding relationship with the equalized expected value.
  • the decision threshold is (+2, 0, -2)
  • the equilibrium expectation is (+3, +1, -1, -3)
  • the decision threshold is (+3, +1 , -1, -3)
  • each decision circuit can be set as a decision circuit corresponding to +3, a decision circuit corresponding to +1, a decision circuit corresponding to -1 and a decision circuit corresponding to -3.
  • each decision circuit can also be set as a decision circuit corresponding to +3, a decision circuit corresponding to +1, a decision circuit corresponding to -1 and a decision circuit corresponding to -3.
  • the judgment value when the equalization signal output by the judgment equalization is +30, the judgment value is +3, corresponding to the judgment circuit corresponding to +3; when the equalization signal output by the judgment equalization is +10, the judgment value is +1, corresponding to the The judgment circuit corresponding to +1; when the balanced signal output by the judgment equalization is -10, the judgment value is -1, corresponding to the judgment circuit corresponding to -1; when the equalized signal output by the judgment equalization is -30, the judgment value is -3, corresponding to the decision circuit corresponding to -3.
  • the decision equalization device outputs the decision value.
  • the decision equalization device updates the first equalization expectation value in the first set of equalization expectation values to a second equalization expectation value according to the decision value and the input signal to obtain a second equalization expectation value, and the first equalization expectation value is the Equilibrium expected value corresponding to decision value.
  • the decision equalization device can also update the first equalization expectation value in the first group of equalization expectation values of the decision circuit outputting the decision value as shown in Figure 7 to obtain the second equalization expectation value , so as to obtain a second group of balanced expected values, wherein the first balanced expected value is the balanced expected value corresponding to the decision value.
  • the update process of the equilibrium expected value may include the following possible implementation methods:
  • the decision equalization device updates the equalization expectation value corresponding to the iterative decision circuit after each decision equalization is performed to obtain a decision value.
  • the solution specifically includes: the decision equalization device determines a decision error of the decision circuit according to the first equalization expectation value and the input signal; and then updates the first equalization expectation value to the second equalization value according to the decision error expectations. In this way, the convergence process of the equalization expected value and the decision threshold can be quickly realized, thereby realizing linear and nonlinear equalization of signals.
  • the decision error is equal to the first equalization expectation value minus the input signal.
  • the calculation method of the decision error may be as shown in Table 1:
  • the y k is used to indicate the input signal
  • the e k is used to indicate the decision error
  • the T i0 , T i1 , and T i2 are used to indicate the decision threshold on the i-th decision circuit
  • the EV i0 , EV i1 , EV i2 , EV i3 are used to indicate the expected equalization value on the i-th decision circuit.
  • the first set of decision thresholds T 30 , T of the first path at this moment are respectively -20, 0, and +20, and the values of the first set of equilibrium expectation values EV 30 , EV 31 , EV 32 , and EV 33 are -30, -10, +10, and +30.
  • the decision relationship between the input signal and the decision threshold may also be other relationships, which are not specifically limited here.
  • the method for the decision equalization device to update the first equalization expected value to the second equalization expected value according to the decision error specifically includes:
  • the decision equalization device updates the first balanced expected value to the second balanced expected value according to the decision error and the first formula
  • the first formula is:
  • the EV new is used to indicate the second expected equalization value
  • the EV old is used to indicate the first expected equalized value
  • the e k is used to indicate the decision error
  • the k is used to indicate the current moment.
  • the input signal y k at the current k-th time enters the first path in FIG. 8 (that is, the decision circuit corresponding to +3) for decision
  • y k 25
  • the remaining EV values remain unchanged.
  • the decision equalization device updates the first equalization expected value to the second equalization expected value according to the decision error and the second formula
  • the EV new is used to indicate the second equalization expected value
  • the EV old is used to indicate the first equalized expected value
  • the e k is used to indicate the decision error
  • the ⁇ is used to indicate a preset constant
  • the k is used for Indicates the current moment.
  • the input signal y k at the current k-th time enters the first path in FIG. 8 (that is, the decision circuit corresponding to +3) for decision
  • y k 25
  • the remaining EV values remain unchanged.
  • the decision equalization device updates and iterates the equalization expectation value after a certain equalization expectation value on the decision circuit performs a preset number of decision equalizations (that is, the decision times of a certain equalization expectation value on the decision circuit reach the preset number of times).
  • a preset number of decision equalizations that is, the decision times of a certain equalization expectation value on the decision circuit reach the preset number of times.
  • the scheme specifically includes:
  • the decision equalization device obtains a decision error according to the input signal and the first equalization expectation value, the decision equalization device records the decision error to generate a decision error set, and the decision error set includes the decision error corresponding to the first equalization expectation value; in the decision error When the number of decision errors in the set reaches a preset number, the decision equalization device determines a final decision error according to the decision errors in the decision error set; and updates the first equalized expected value to the second equalized value according to the final decision error expectations. In this way, the convergence process of equalizing expected value and decision threshold can be quickly realized, thereby realizing linear and nonlinear equalization of signals.
  • the decision equalization device when the decision equalization device records the decision error, it can directly calculate the sign of the decision error, and then record the calculated value as a decision error set; finally, in the decision error set After the number of values corresponding to the decision error reaches a preset number, the final decision error is determined according to the values in the decision error set, and the first balanced expected value is updated to the second balanced expected value according to the final decision error.
  • the decision errors corresponding to the first balanced expectation value are (-2, +4, +1, -5) respectively, then the decision error set obtained after the sign calculation of the decision errors is recorded as (-1, +1, +1, -1), then the final decision error is 0, and the first equilibrium expected value does not need to be updated in this update.
  • the decision errors corresponding to the first equilibrium expectation value are respectively (-2, +4, +1, +1)
  • the set of decision errors obtained after the sign calculation of the decision errors is recorded as (-1, +1 , +1, +1)
  • the final decision error is 2
  • the first balanced expected value is updated to the second balanced expected value according to the final decision error. In this way, the operational complexity of the decision equalization device in recording decision errors can be reduced.
  • the final decision error is equal to the sum of the multiple decision errors.
  • updating the first expected equalization value to the second expected equalization value by the decision equalization device according to the final decision error specifically includes:
  • the decision equalization device updates the first equalization expected value to the second equalization expected value according to the final decision error and the first formula
  • the first formula is:
  • the EV new is used to indicate the second expected equalization value
  • the EV old is used to indicate the first expected equalized value
  • the e k is used to indicate the final decision error
  • the k is used to indicate the current moment.
  • the decision equalization device updates the first equalization expected value to the second equalization expected value according to the decision error and the second formula
  • the EV new is used to indicate the second balanced expected value
  • the EV old is used to indicate the first balanced expected value
  • the e k is used to indicate the final decision error
  • the ⁇ is used to indicate a preset constant
  • the k is used to indicate the current moment.
  • the decision equalization device updates and iterates the equalization expectation value corresponding to the decision circuit after a preset time period.
  • the decision equalization device counts decision errors corresponding to each equalization expectation value on each decision circuit within a preset time period; then the decision equalization device updates each equalization expectation value according to the decision error corresponding to each equalization expectation value.
  • the decision equalization device can directly perform sign calculation on the decision error when recording the decision error, and then record the calculated value as a decision error set; finally, the decision error in the decision error set After the number of corresponding values reaches a preset number, the final decision error is determined according to the values in the decision error set, and the first balanced expected value is updated to the second balanced expected value according to the final decision error.
  • the decision errors corresponding to the first balanced expectation value are (-2, +4, +1, -5) respectively, then the decision error set obtained after the sign calculation of the decision errors is recorded as (-1, +1, +1, -1), then the final decision error is 0, and the first equilibrium expected value does not need to be updated in this update.
  • the decision errors corresponding to the first equilibrium expectation value are respectively (-2, +4, +1, +1)
  • the set of decision errors obtained after the sign calculation of the decision errors is recorded as (-1, +1 , +1, +1)
  • the final decision error is 2
  • the first balanced expected value is updated to the second balanced expected value according to the final decision error. In this way, the operational complexity of the decision equalization device in recording decision errors can be reduced.
  • the manner of updating the expected equilibrium value may be the same as the technical solutions described in the above two solutions, and details will not be repeated here.
  • the convergence process of the equalization expected value and the decision threshold can be quickly realized, thereby realizing linear and nonlinear equalization of signals.
  • the decision equalization device updates at least one decision threshold in the first set of decision thresholds according to the second equalization expectation value to obtain a second set of decision thresholds, and the second set of decision thresholds and the second set of equalization expectation values are used In the next decision equalization of the decision circuit.
  • the decision equalization device After the decision equalization device updates and obtains the second equalization expected value, the decision equalization device calculates and updates at least one decision threshold in the first group of decision thresholds according to the second equalization expectation value and its adjacent third equalization expectation value to obtain the The second set of decision thresholds.
  • the third expected equalization value can be determined according to the positional relationship of the second expected equalized value, or the third expected equalized value can be determined according to the position of the second expected equalized value and the position between the input signal and the second expected equalized value The relationship is determined.
  • the first set of decision thresholds are T 30 , T 31 , T 32 , the first set of equalization expected values EV 30 , EV 31 , EV 32 , EV 33 , and the EV 33 is updated, then the first The expected value of triple equilibrium is only EV 32 . If the EV 32 is updated, the third balanced expected value may be EV 33 and/or EV 31 .
  • the values of the first set of decision thresholds T 30 , T 31 , and T 32 are -20, 0, and +20 respectively, the values of the first set of equalization expectation values EV 30 , EV 31 , EV 32 , and EV 33 are -30, -10 .
  • the iterative process of updating the equalization expected value and the decision threshold can be shown in Figure 13, that is, for each error value, it will update an equalized expected value in the decision equalization device, and the balanced expected value will be One or two decision thresholds will be updated.
  • the signal judgment and equalization of the actual channel is used for illustration.
  • the decision device of the DFE architecture since the decision device of the DFE architecture is only related to the current signal, the decision threshold and the equalization expectation generated by the DFE are different at four levels according to the convergence parameters. The difference is evenly distributed.
  • the decision equalization device provided in this embodiment considers both the previous signal and the current signal in the iterative calculation, and for the nonlinear characteristics of the channel, the decision equalization device provided in this embodiment converges to different decision thresholds for different signal sequences And equalize the expected value, and then make a corresponding equalization for the nonlinearity of the channel.
  • the one-tap decision equalization device provided by this embodiment and the one-tap DFE equalizer are compared as examples It can be found that the equalization performance of the one-tap decision equalizer provided in this embodiment is stronger than that of the one-tap DFE equalizer, and the specific effects can be shown in FIGS. 15 to 17 . It can be understood that the dynamic nonlinear slicing (dynamic nonlinear slicing, DNS) in FIG. 14 to FIG. 17 is the decision equalization device provided for the implementation of this application.
  • dynamic nonlinear slicing dynamic nonlinear slicing, DNS
  • the decision equalization device iteratively updates each decision threshold of the decision circuit according to the equalized signal output by the decision circuit, so as to realize independent iterative update of each decision threshold, and can realize optimal equalization and decision on the signal more effectively, thereby improving Equalization performance, reducing the bit error rate after equalization.
  • the decision equalization device is combined with a maximum likelihood sequence estimation (MLSE) architecture to perform signal decision equalization.
  • MLSE maximum likelihood sequence estimation
  • the decision equalization device provided by the embodiment of the present application provides the equalization expectation value as the input of MLSE, and participates in the calculation of the branch metric value, so that the MLSE algorithm is closer to the channel characteristics and effectively realizes the equalization nonlinear characteristics.
  • the calculation architecture of the branch metric value in the MLSE equalization process can be shown in Figure 19, and the calculation can be expressed as:
  • the y k is used to indicate the input signal
  • the EV ij is used to indicate the equalization expected value output by the decision equalization device
  • the bm ij is used to indicate the branch metric value
  • the k is used to indicate the current moment.
  • the MLSE After the MLSE completes the calculation of the branch metric value of each state at each moment, it will select the surviving path (black performance) of each state at the current moment according to the working principle shown in Figure 20, and calculate the surviving path of the entire sequence according to the backtracking length , and according to the maximum likelihood criterion, select the transmission sequence whose distance is closest to the received signal (the gray solid line in Figure 20), and then the state value at time t-D+1 can be obtained.
  • the decision equalization device provided by the embodiment of the present application is combined with MLSE and the equalization performance comparison chart of traditional MLSE shows that the decision equalization device provided by the embodiment of the present application can help MLSE improve the bit error rate Performance is about an order of magnitude.
  • a decision equalization method for nonlinear signals is also provided.
  • the decision equalization device obtains an input signal, and the input signal is a pulse amplitude modulation (PAM) signal or the PAM signal
  • PAM pulse amplitude modulation
  • the decision equalization device determines the decision circuit of the input signal; at the same time, the decision equalization device also obtains the first set of decision thresholds and the first equalization expectation value corresponding to the decision circuit; then the decision The equalization device determines the decision value of the input signal according to the first group of equalization expectation values, the first group of decision thresholds and the input signal, and outputs the decision value; at the same time, the decision equalization signal updates the first decision value according to the decision value and the input signal All balanced expected values in a group of balanced expected values obtain a second group of balanced expected values; finally, the decision equalization device updates all decision thresholds in the first group of decision thresholds according to the second group of balanced expected values to obtain a second group of decision thresholds, where
  • PAM pulse amplitude modul
  • the half eye height (HEH) coefficient of the decision value set that is, the scaling factor is set to 10.
  • the input signal y k at the current k-th time enters the first path in Figure 8 (that is, the judgment circuit corresponding to +3) for judgment, assuming that the first path at this moment
  • the values of the first group of decision thresholds T 30 , T 31 , and T 32 are respectively -20, 0, and +20 (wherein, the -20 is equal to -2*scaling factor, the 0 is equal to 0*scaling factor, and the +20 is equal to + 2*scaling factor), the values of the first group of equalization expected values EV 30 , EV 31 , EV 32 , and EV 33 are -30, -10, +10, +30 (wherein, the -30 is equal to -3*scaling factor, and the -10 is equal to -1*scale factor, the +10 is equal to +1*scale factor, and the +30 is equal to +3*scale factor).
  • the decision equalization device iteratively updates all the decision thresholds of the decision circuit according to the equalized signal output by the decision circuit, that is, the update iterations of each decision circuit are independent of each other, but the decision in each decision circuit
  • the threshold is associated iterative update, which realizes the independent iterative update of each judgment circuit, which can effectively realize the optimal equalization and judgment of the signal, thereby improving the equalization performance and reducing the bit error rate after equalization.
  • the decision equalization device includes corresponding hardware structures and/or software modules for performing various functions.
  • the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a certain function is executed by hardware or computer software drives hardware depends on the specific application and design constraints of the technical solution. Skilled artisans may use different methods to implement the described functions for each specific application, but such implementation should not be regarded as exceeding the scope of the present application.
  • the decision equalization device may be divided into functional modules according to the above method examples.
  • each functional module may be divided corresponding to each function, or two or more functions may be integrated into one processing module.
  • the above-mentioned integrated modules can be implemented in the form of hardware or in the form of software function modules. It should be noted that the division of modules in the embodiment of the present application is schematic, and is only a logical function division, and there may be other division methods in actual implementation.
  • FIG. 22 is a schematic diagram of an embodiment of a decision equalization device in an embodiment of this application.
  • the decision equalization device can be deployed in routers, switches, and OTN transmission equipment, and the decision equalization device 2200 includes:
  • the acquiring module 2201 is configured to acquire an input signal, the input signal is a pulse amplitude modulation (pulse amplitude modulation, PAM) signal or a pre-equalized signal output after the PAM signal is pre-equalized;
  • PAM pulse amplitude modulation
  • a processing module 2202 configured to determine a decision circuit for the input signal
  • the acquiring module 2201 is further configured to acquire a first set of decision thresholds and a first set of equalization expectation values of the decision circuit;
  • the processing module 2202 is further configured to determine a decision value of the input signal according to the first group of equalization expectation values, the first group of decision thresholds and the input signal;
  • An output module 2203 configured to output the decision value
  • the processing module 2202 is further configured to update the first balanced expected value in the first group of balanced expected values to a second balanced expected value according to the decision value and the input signal to obtain a second balanced expected value, and the first balanced expected value is The equalization expectation value corresponding to the decision value; updating at least one decision threshold in the first set of decision thresholds according to the second equalization expectation value to obtain a second set of decision thresholds, the second set of decision thresholds and the second set of decision thresholds
  • the equalization expectation value is used for the next decision equalization of the decision circuit.
  • the processing module 2202 is specifically configured to determine a decision error of the decision circuit according to the first expected equalization value and the input signal; update the first expected equalization value according to the decision error The second equilibrium expected value.
  • the decision error is equal to the first equalization expected value minus the input signal.
  • processing module 2202 is specifically used to
  • the first formula is:
  • the EV new is used to indicate the second expected equalization value
  • the EV old is used to indicate the first expected equalized value
  • the e k is used to indicate the decision error
  • the k is used to indicate the current moment ;
  • the processing module 2202 is specifically configured to update the first balanced expected value to the second balanced expected value according to the decision error and the second formula;
  • the second formula is:
  • the EV new is used to indicate the second equalization expected value
  • the EV old is used to indicate the first equalized expected value
  • the e k is used to indicate the decision error
  • the ⁇ is used to indicate the preset Constant
  • the k is used to indicate the current moment.
  • the processing module 2202 is specifically configured to obtain a decision error according to the input signal and the first equalization expectation value; record the decision error to generate a decision error set, and the decision error set includes the first Equalize the decision error corresponding to the expected value; when the number of decision errors in the decision error set reaches a preset number, determine the final decision error according to the decision error in the decision error signal set; update the first decision error according to the final decision error A balanced expected value is the second balanced expected value.
  • the final decision error is equal to the sum of the multiple decision errors.
  • the processing module 2202 is specifically configured to obtain a second group of decision thresholds according to at least one decision threshold in updating the second balanced expected value and the third balanced expected value, and the third balanced expected value is Balanced expected values adjacent to the second balanced expected value in the second group of balanced expected values.
  • the obtaining module 2201 is also used to
  • An initial convergence parameter output by a decision feedback equalizer DFE mode is received, and the initial convergence parameter is used as an initial equalization expected value of the input signal during decision equalization.
  • the obtaining module 2201 is also used to
  • the adaptive parameter output by the feed-forward equalizer is received, and the adaptive parameter is used as an initial equalization expectation value of the input signal when determining equalization.
  • processing module 2202 is also used to
  • the number of decision circuits and the number of decision thresholds are determined according to the level number N of the PAM signal and the number M of equalized signals in the decision value set, where M is a positive integer.
  • processing module 2202 is specifically used to
  • the number of decision circuits and the number of decision thresholds are determined using a third formula, wherein the third formula is:
  • the S is used to indicate the number of the decision circuits
  • the P is used to indicate the number of the decision thresholds
  • the N is used to indicate the level number of the PAM signal
  • the M is used to indicate the The number of equalized signals in the decision value set.
  • processing module 2202 is specifically used to
  • Determining a decision value of the input signal by using maximum likelihood sequence estimation according to the first group of decision thresholds, the first group of equalization expectation values and the input signal.
  • the processing module 2202 is specifically configured to determine the decision circuit of the input signal according to the decision value set, the equalized signal group includes at least one decision value, and the occurrence time of the at least one decision value is earlier than the The moment of occurrence of the input signal.
  • the decision equalization apparatus in the foregoing embodiments may be a network device or a user device, or may be a chip applied in a network device or other combined devices, components, etc. that can realize the functions of the above network device.
  • the transceiver module may be a transceiver
  • the processing module may be a processor, such as a chip.
  • the part used for receiving in the transceiver module may be the input port of the chip system
  • the part used for sending in the transceiver module may be the output interface of the chip system
  • the processing module may be the processor of the chip system , for example: central processing unit (central processing unit, CPU).
  • the memory included in the decision equalization device is mainly used for storing software programs and data, for example, storing the programs described in the foregoing embodiments.
  • the decision equalization device also has the following functions:
  • the transceiver is used to obtain an input signal, the input signal is a pulse amplitude modulation (pulse amplitude modulation, PAM) signal or a pre-equalized signal output after the PAM signal is pre-equalized;
  • PAM pulse amplitude modulation
  • a processor configured to determine a decision circuit for said input signal
  • the transceiver is also used to obtain a first set of decision thresholds and a first set of equalization expected values of the decision circuit;
  • the processor is further configured to determine a decision value of the input signal according to the first set of equalization expectation values, the first set of decision thresholds, and the input signal;
  • a transceiver configured to output the decision value
  • the processor is further configured to update a first balanced expected value in the first group of balanced expected values to a second balanced expected value according to the input signal of the decision value to obtain a second balanced expected value, and the first balanced expected value is The balanced expected value corresponding to the decision value; update at least one decision threshold in the first group of decision thresholds according to the second balanced expectation value to obtain a second group of decision thresholds, and the second group of decision thresholds is equal to the second group of decision thresholds
  • the expected value is used for the next decision equalization of the decision circuit.
  • the processor is specifically configured to determine a decision error of the decision circuit according to the first expected equalization value and the input signal; and update the first expected equalization value according to the decision error. Describe the second equilibrium expected value.
  • the decision error is equal to the first equalization expected value minus the input signal.
  • the processor is specifically used to
  • the first formula is:
  • the EV new is used to indicate the second expected equalization value
  • the EV old is used to indicate the first expected equalized value
  • the e k is used to indicate the decision error
  • the k is used to indicate the current moment ;
  • the processor is specifically configured to update the first balanced expected value to the second balanced expected value according to the decision error and the second formula
  • the second formula is:
  • the EV new is used to indicate the second equalization expected value
  • the EV old is used to indicate the first equalized expected value
  • the e k is used to indicate the decision error
  • the ⁇ is used to indicate the preset Constant
  • the k is used to indicate the current moment.
  • the processor is specifically configured to obtain a decision error according to the input signal and the first equalization expected value; record the decision error to generate a decision error set, and the decision error set includes the first equalization The decision error corresponding to the expected value; when the number of decision errors in the decision error set reaches a preset number, determine the final decision error according to the decision error in the decision error signal set; update the first decision error according to the final decision error
  • the balanced expected value is the second balanced expected value.
  • the final decision error is equal to the sum of the multiple decision errors.
  • the processor is specifically configured to obtain a second group of decision thresholds according to at least one decision threshold in the update of the second balanced expected value and the third balanced expected value, and the third balanced expected value is the Balanced expected values adjacent to the second balanced expected value in the second group of balanced expected values.
  • the transceiver is also used to
  • An initial convergence parameter output by a decision feedback equalizer DFE mode is received, and the initial convergence parameter is used as an initial equalization expected value of the input signal during decision equalization.
  • the transceiver is also used to
  • the adaptive parameter output by the feed-forward equalizer is received, and the adaptive parameter is used as an initial equalization expectation value of the input signal when determining equalization.
  • the processor is also used to
  • the number of decision circuits and the number of decision thresholds are determined according to the level number N of the PAM signal and the number M of equalized signals in the decision value set, where M is a positive integer.
  • the processor is specifically used to
  • the number of decision circuits and the number of decision thresholds are determined using a third formula, wherein the third formula is:
  • the S is used to indicate the number of the decision circuits
  • the P is used to indicate the number of the decision thresholds
  • the N is used to indicate the level number of the PAM signal
  • the M is used to indicate the The number of equalized signals in the decision value set.
  • the processor is specifically configured to determine a decision circuit for the input signal according to a decision value set, the equalized signal group includes at least one decision value, and the occurrence time of the at least one decision value is earlier than The moment of occurrence of the input signal.
  • Determining a decision value of the input signal by using maximum likelihood sequence estimation according to the first group of decision thresholds, the first group of equalization expectation values and the input signal.
  • the processor is specifically used to
  • the processor is specifically configured to determine a decision circuit for the input signal according to a decision value set, the equalized signal group includes at least one decision value, and the occurrence time of the at least one decision value is earlier than The moment of occurrence of the input signal.
  • the embodiment of the present application also provides a processing device.
  • the processing device includes a processor and an interface; the processor is configured to execute the signal decision equalization method in any one of the above method embodiments.
  • the above-mentioned processing device may be a chip, and the processor may be implemented by hardware or by software.
  • the processor When implemented by hardware, the processor may be a logic circuit, an integrated circuit, etc.; when implemented by software, the processor may be a general-purpose processor, and may be implemented by reading software codes stored in a memory.
  • the memory may be integrated in the processor, or may be located outside the processor and exist independently.
  • the hardware processing circuit can include ASIC (application-specific integrated circuit, application-specific integrated circuit), or PLD (programmable logic device, programmable logic device); wherein, PLD can include FPGA (field programmable gate array, field programmable gate array) , CPLD (complex programmable logic device, complex programmable logic device) and so on.
  • ASIC application-specific integrated circuit, application-specific integrated circuit
  • PLD programmable logic device, programmable logic device
  • FPGA field programmable gate array
  • CPLD complex programmable logic device, complex programmable logic device
  • These hardware processing circuits can be a semiconductor chip packaged separately (such as packaged into an ASIC); they can also be integrated with other circuits (such as CPU, DSP) and packaged into a semiconductor chip, for example, can be formed on a silicon base
  • a variety of hardware circuits and CPUs are packaged separately into a chip.
  • This chip is also called SoC, or circuits and CPUs for realizing FPGA functions can also be formed on a silicon base, and separately sealed into a chip.
  • SoPC system on a programmable chip, programmable system on a chip.
  • FIG. 23 is a schematic diagram of an embodiment of a decision equalization device in an embodiment of the present application.
  • the decision equalization device can be deployed in routers, switches, and OTN transmission equipment.
  • the decision equalization device 2300 includes: an acquisition module 2301, which is used to acquire an input signal.
  • the input signal is a pulse amplitude modulated PAM signal or the PAM signal is pre-equalized The pre-equalized signal output after;
  • a processing module 2302 configured to determine a decision circuit for the input signal
  • the acquiring module 2301 is further configured to acquire a first set of decision thresholds and a first set of equalization expected values of the decision circuit, the distribution of the first set of decision thresholds is an asymmetric distribution, and the distribution of the first set of equalized expected values is an asymmetric distribution,
  • the processing module 2302 is further configured to determine a decision value of the input signal according to the first group of equalization expectation values, the first group of decision thresholds and the input signal.
  • the decision equalization device 2300 also includes an output module 2303, configured to output the decision value.
  • the number of decision thresholds in the first group of decision thresholds is equal to the number of levels of the PAM signal minus one;
  • the number of equalization expected values in the first set of equalized expected values is equal to the number of levels of the PAM signal.
  • the first group of equalization expected values is obtained by updating the equalized expected value at the previous time according to the input signal at the previous time and the judgment output of the input signal at the previous time, and the expected value at the previous time is Earlier than the occurrence moment of the input signal, the first group of decision thresholds is obtained by updating according to the first group of equalization expectation values;
  • the first group of equalization expectation values is obtained by updating the equalization expectation values at the first N moments according to the input signal at the first N moments and the judgment output of the input signal at the first N moments, and the first N moments are earlier than the The occurrence moment of the input signal, the first group of decision thresholds is obtained by updating according to the first group of equalization expectation values.
  • the decision circuit is included in a set of decision circuits, the decision thresholds of the decision circuits in the set of decision circuits are different, and the equalization expectation values of the decision circuits in the set of decision circuits are different .
  • the processing module 2302 is specifically configured to determine the decision circuit of the input signal according to the decision value set, the equalized signal group includes at least one decision value, and the occurrence time of the at least one decision value is earlier than at the time of occurrence of the input signal.
  • the decision equalization apparatus in the foregoing embodiments may be a network device or a user device, or may be a chip applied in a network device or other combined devices, components, etc. that can realize the functions of the above network device.
  • the transceiver module may be a transceiver
  • the processing module may be a processor, such as a chip.
  • the part used for receiving in the transceiver module may be the input port of the chip system
  • the part used for sending in the transceiver module may be the output interface of the chip system
  • the processing module may be the processor of the chip system , for example: central processing unit (central processing unit, CPU).
  • the memory included in the decision equalization device is mainly used for storing software programs and data, for example, storing the programs described in the foregoing embodiments.
  • the decision equalization device also has the following functions:
  • a transceiver configured to obtain an input signal.
  • the input signal is a pulse amplitude modulated PAM signal or a pre-equalized signal output after the PAM signal is pre-equalized;
  • a processor configured to determine a decision circuit for said input signal
  • the transceiver is also used to obtain a first group of decision thresholds and a first group of equalization expected values of the decision circuit, the distribution of the first group of decision thresholds is an asymmetric distribution, and the distribution of the first group of equalization expected values is asymmetric distributed,
  • the processor is further configured to determine a decision value of the input signal according to the first group of equalization expectation values, the first group of decision thresholds and the input signal.
  • the number of decision thresholds in the first group of decision thresholds is equal to the number of levels of the PAM signal minus one;
  • the number of equalization expected values in the first set of equalized expected values is equal to the number of levels of the PAM signal.
  • the first group of equalization expected values is obtained by updating the equalized expected value at the previous time according to the input signal at the previous time and the judgment output of the input signal at the previous time, and the expected value at the previous time is Earlier than the occurrence moment of the input signal, the first group of decision thresholds is obtained by updating according to the first group of equalization expectation values;
  • the first group of equalization expectation values is obtained by updating the equalization expectation values at the first N moments according to the input signal at the first N moments and the judgment output of the input signal at the first N moments, and the first N moments are earlier than the The occurrence moment of the input signal, the first group of decision thresholds is obtained by updating according to the first group of equalization expectation values.
  • the decision circuit is included in a set of decision circuits, the decision thresholds of the decision circuits in the set of decision circuits are different, and the equalization expectation values of the decision circuits in the set of decision circuits are different .
  • the processor is specifically configured to determine a decision circuit for the input signal according to a decision value set, the equalized signal group includes at least one decision value, and the occurrence time of the at least one decision value is earlier than The moment of occurrence of the input signal.
  • the embodiment of the present application also provides a processing device.
  • the processing device includes a processor and an interface; the processor is configured to execute the signal decision equalization method in any one of the above method embodiments.
  • the above-mentioned processing device may be a chip, and the processor may be implemented by hardware or by software.
  • the processor When implemented by hardware, the processor may be a logic circuit, an integrated circuit, etc.; when implemented by software, the processor may be a general-purpose processor, and may be implemented by reading software codes stored in a memory.
  • the memory may be integrated in the processor, or may be located outside the processor and exist independently.
  • the hardware processing circuit can include ASIC (application-specific integrated circuit, application-specific integrated circuit), or PLD (programmable logic device, programmable logic device); wherein, PLD can include FPGA (field programmable gate array, field programmable gate array) , CPLD (complex programmable logic device, complex programmable logic device) and so on.
  • ASIC application-specific integrated circuit, application-specific integrated circuit
  • PLD programmable logic device, programmable logic device
  • FPGA field programmable gate array
  • CPLD complex programmable logic device, complex programmable logic device
  • These hardware processing circuits can be a semiconductor chip packaged separately (such as packaged into an ASIC); they can also be integrated with other circuits (such as CPU, DSP) and packaged into a semiconductor chip, for example, can be formed on a silicon base.
  • a variety of hardware circuits and CPUs are packaged separately into a chip.
  • This chip is also called SoC, or circuits and CPUs for realizing FPGA functions can also be formed on a silicon base, and separately sealed into a chip.
  • SoPC system on a programmable chip, programmable system on a chip.
  • An embodiment of the present application further provides a computer-readable storage medium, including instructions, which, when run on a computer, enable the computer to control the decision equalization device to execute any implementation manner as shown in the foregoing method embodiments.
  • the embodiment of the present application also provides a computer program product, the computer program product includes computer program code, and when the computer program code is run on the computer, the computer is made to execute any one of the implementation manners shown in the foregoing method embodiments.
  • the embodiment of the present application also provides a chip system, including a memory and a processor, the memory is used to store a computer program, and the processor is used to call and run the computer program from the memory, so that the chip performs any implementation as shown in the foregoing method embodiments Way.
  • the embodiment of the present application also provides a chip system, including a processor, and the processor is configured to call and run a computer program, so that the chip executes any one of the implementation manners shown in the foregoing method embodiments.
  • the device embodiments described above are only illustrative, and the units described as separate components may or may not be physically separated, and the components shown as units may or may not be A physical unit can be located in one place, or it can be distributed to multiple network units. Part or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment.
  • the connection relationship between the modules indicates that they have communication connections, which can be specifically implemented as one or more communication buses or signal lines.
  • the essence of the technical solution of this application or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product is stored in a readable storage medium, such as a floppy disk of a computer , U disk, mobile hard disk, ROM, RAM, magnetic disk or optical disk, etc., including several instructions to make a computer device execute the method described in each embodiment of the present application.
  • a readable storage medium such as a floppy disk of a computer , U disk, mobile hard disk, ROM, RAM, magnetic disk or optical disk, etc.
  • all or part of them may be implemented by software, hardware, firmware or any combination thereof.
  • software When implemented using software, it may be implemented in whole or in part in the form of a computer program product.
  • the computer program product includes one or more computer instructions.
  • the computer can be a general purpose computer, a special purpose computer, a computer network, or other programmable devices.
  • the computer instructions may be stored in or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from a website, a computer, a first network device or a second network device, computing device, or data center to another website site, computer, first network device or a second network device, computing device or data center for transmission.
  • the computer-readable storage medium may be any available medium that can be stored by a computer, or a data storage device such as a first network device or a second network device, a data center, etc. integrated with one or more available media.
  • the available medium may be a magnetic medium (such as a floppy disk, a hard disk, or a magnetic tape), an optical medium (such as a DVD), or a semiconductor medium (such as a solid state disk (Solid State Disk, SSD)), etc.
  • B corresponding to A means that B is associated with A, and B can be determined according to A.
  • determining B according to A does not mean determining B only according to A, and B may also be determined according to A and/or other information.
  • the disclosed system, device and method can be implemented in other ways.
  • the device embodiments described above are only illustrative.
  • the division of units is only a logical function division. In actual implementation, there may be other division methods.
  • multiple units or components can be combined or integrated. to another system, or some features may be ignored, or not implemented.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces, and the indirect coupling or communication connection of devices or units may be in electrical, mechanical or other forms.
  • a unit described as a separate component may or may not be physically separated, and a component displayed as a unit may or may not be a physical unit, that is, it may be located in one place, or may be distributed to multiple network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.
  • each functional unit in each embodiment of the present application may be integrated into one processing unit, each unit may exist separately physically, or two or more units may be integrated into one unit.
  • the above-mentioned integrated units can be implemented in the form of hardware or in the form of software functional units.
  • the integrated unit is realized in the form of a software function unit and sold or used as an independent product, it can be stored in a computer-readable storage medium.
  • the technical solution of the present application is essentially or part of the contribution to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium , including several instructions to make a computer device (which may be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the methods in various embodiments of the present application.

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Abstract

一种信号的判决均衡方法以及装置，用于提升均衡性能，降低均衡后的误码率。包括：获取输入信号，输入信号为PAM信号或者为PAM信号经过预均衡后输出的预均衡信号；确定输入信号的判决电路；获取判决电路的第一组判决阈值和第一均衡期望值；根据第一组均衡期望值、第一组判决阈值以及输入信号确定输入信号的判决值并输出判决值；根据判决值和输入信号更新第一组均衡期望值中的判决值对应的第一均衡期望值为第二均衡期望值得到第二组均衡期望值；根据第二均衡期望值更新第一组判决阈值中的至少一个判决阈值得到第二组判决阈值。

Description

一种信号判决均衡方法以及装置
本申请要求于2021年06月30日提交中国国家知识产权局、申请号为202110745652.8、发明名称为“一种信号判决均衡方法以及装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及通信领域，尤其涉及一种信号判决均衡方法以及装置。
背景技术
随着网络用户需求和数据流量的持续增加，高速链路技术成为芯片和接口的基础技术，包括电互联链路和光互联链路。从50Gbps传输系统开始，光电链路传输信号已经从非归零编码(non-return-to-zero，NRZ)逐渐过渡到脉冲幅度调制(pulse amplitude modulation，PAM)，多电平的调制方式使得各种光电器件和信道的非线性特性开始显现出来，其造成的原因主要是光链路中发射端的啁啾与光纤色散的相互作用。电链路中发端的高低电平充放电，以及收端连续时间线性均衡器(continuous time linear equalizer,CTLE)等造成的非线性效应。
链路中的非线性特性不但引入了码间干扰，而且导致信号失真，极大地影响了系统的传输特性，阻碍了系统数据传输速率的进一步提升。
传统的线性自适应滤波器由于线性特性限制了其逼近非线性函数的能力，使滤波性能不尽如人意，无法很好地应对这一特性。近年来非线性滤波理论已成为业界研究的热点，对于目前100Gbps和未来更高速的传输系统，非线性均衡将成为一个关键的技术能力。
发明内容
本申请实施例提供了一种信号判决均衡方法以及装置，用于对信号实现最优化均衡和判决，进而提升均衡性能，降低均衡后的误码率。
第一方面，本申请实施例提供一种信号判决均衡方法，具体包括：该判决均衡装置获取输入信号，该输入信号为脉冲幅度调制(pulse amplitude modulation，PAM)信号或者为该PAM信号在经过预均衡后输出的预均衡信号(如为该PAM信号在经过前馈均衡器(feed forward equalizer，FFE)预均衡输出的预均衡信号)；然后该判决均衡装置确定该输入信号的判决电路；同时该判决均衡装置还获取该判决电路对应的第一组判决阈值和第一均衡期望值；然后该判决均衡装置根据该第一组均衡期望值、该第一组判决阈值以及该输入信号确定该输入信号的判决值，并输出该判决值；同时该判决均衡信号根据该判决值和该输入信号更新该第一组均衡期望值中的第一均衡期望值为第二均衡期望值得到第二组均衡期望值，其中，该第一均衡期望值为该判决值对应的均衡期望值；最后该判决均衡装置根据该第二均衡期望值更新该第一组判决阈值中的至少一个判决阈值得到第二组判决阈值，其中，该第二组判决阈值和该第二组均衡期望值用于该判决电路的下一次判决均衡。
可以理解的是，本实施例是提供的技术方案中，仅选择最终输出该判决值的判决电路的判决均衡过程进行说明，但是并未限定其他判决电路是否进行判决均衡。即在本方案中，一种可能实现方案中，其他判决电路同样也可以进行判决均衡，但是输出的均衡信号并未被选择；另一种可能实现方案中，其他判决电路并未进行判决均衡。
本实施例提供的技术方案中，该判决均衡装置根据判决电路的输入信号、该输入信号对应的判决值以及该判决值对应的均衡期望值对于判决电路的各个判决阈值进行独立迭代更新，可以更加有效的对信号实现最优化均衡和判决，进而提升均衡性能，降低均衡后的误码率。
可选的，该判决均衡装置在根据该判决值和该输入信号更新该第一组均衡期望值中的第一均衡期望值为第二均衡期望值时可以采用如下几种可能实现方式：
一种可能实现方式中，该判决均衡装置在每次进行判决均衡得到判决值之后就更新迭代判决电路对应的均衡期望值。一种示例性方案中，该方案具体包括：该判决均衡装置根据该第一均衡期望值和该输入信号确定该判决电路的判决误差；然后根据该判决误差更新该第一均衡期望值为该第二均衡期望值。这样可以迅速的实现均衡期望值与判决阈值的收敛过程，从而实现对信号的线性和非线性均衡。
可选的，本实施例中，该判决误差等于该第一均衡期望值减去该输入信号。
可选的，该判决均衡装置根据该判决误差更新该第一均衡期望值为该第二均衡期望值的方法具体包括：
一种可能实现方式中，该判决均衡装置根据该判决误差和第一公式更新该第一均衡期望值为该第二均衡期望值；
该第一公式为：
EV new＝EV old-sign(e k)；
其中，该EV new用于指示该第二均衡期望值，该EV old用于指示该第一均衡期望值，所述e k用于指示所述判决误差，所述k用于指示当前时刻。
另一种可能实现方式中，该判决均衡装置根据该判决误差和第二公式更新该第一均衡期望值为该第二均衡期望值；
该第二公式为：
EV new＝EV old-μ*(e k)；
其中，该EV new用于指示该第二均衡期望值，该EV old用于指示该第一均衡期望值，所述e k用于指示所述判决误差，所述μ用于指示预设常数，所述k用于指示当前时刻。
另一种可能实现方式中，该判决均衡装置在判决电路上的某一均衡期望值进行预设次数的判决均衡之后更新迭代该均衡期望值(即该判决电路上的某一个均衡期望值判决次数达到该预设次数，比如，均衡期望值为EV 33对应的判决值输出了4次之后，更新该均衡期望值EV 33为EV 33，new)。一种示例性方案中，该方案具体包括：该判决均衡装置根据该输入信号和该第一均衡期望值得到判决误差，该判决均衡装置记录该判决误差生成判决误差集合，该判决误差集合包括该第一均衡期望值对应的判决误差；在该判决误差集合中判决误差的数量达到预设数量时，该判决均衡装置根据该判决误差集合中的判决误差确定最终判决误差；并根据所述最终判决误差更新所述第一均衡期望值为所述第二均衡期望值。这样可以迅速的实现均衡期望值与判决阈值的收敛过程，从而实现对信号的线性和非线性均衡。
可以理解的是，本实施例中，该判决均衡装置在记录该判决误差时可以直接对该判决误差进行取符号计算，然后将计算得到的值记录为判决误差集合；最后在判决误差集合中的判决误差对应的值的数量达到预设数量之后再根据该判决误差集合中的值确定最终判决误差，并根据该最终判决误差将该第一均衡期望值更新为该第二均衡期望值。一种示例性方案中，该第一均衡期望值对应的判决误差分别为(-2，+4，+1，-5)，则在对该判决误差进行取符号计算之后得到的判决误差集合记录为(-1，+1，+1，-1)，那最终判决误差则为0，则该第一均衡期望值在此次更新中不用更新。若该第一均衡期望值对应的判决误差分别为(-2，+4，+1，+1)，则在对该判决误差进行取符号计算之后得到的判决误差集合记录为(-1，+1，+1，+1)，那最终判决误差则为2，则该第一均衡期望值根据该最终判决误差更新为第二均衡期望值。这样可以降低判决均衡装置在记录判决误差中的操作复杂度。
可选的，本实施例中，该最终判决误差等于该多个判决误差之和。
可选的，本实施例中，该判决均衡装置根据该最终判决误差更新该第一均衡期望值为该第二均衡期望值具体包括：
一种可能实现方式中，该判决均衡装置根据该最终判决误差和第一公式更新该第一均衡期望值为该第二均衡期望值；
该第一公式为：
EV new＝EV old-sign(e k)；
其中，该EV new用于指示该第二均衡期望值，该EV old用于指示该第一均衡期望值，所述e k用于指示所述判决误差，所述k用于指示当前时刻。
另一种可能实现方式中，该判决均衡装置根据该判决误差和第二公式更新该第一均衡期望值为该第二均衡期望值；
该第二公式为：
EV new＝EV old-μ*(e k)；
其中，该EV new用于指示该第二均衡期望值，该EV old用于指示该第一均衡期望值，所述e k用于指示所述判决误差，所述μ用于指示预设常数，所述k用于指示当前时刻。
另一种可能实现方式中，该判决均衡装置在预设时间段之后更新迭代该判决电路对应的均衡期望值。一种可能实现方式中，该判决均衡装置统计在预设时间段内各个判决电路上各个均衡期望值对应的输入信号，然后根据各个均衡期望值对应的输入信号得到各个均衡期望值对应的判决误差；最后该判决均衡装置根据各个均衡期望值对应的判决误差更新该各个均衡期望值。可以理解的是，更新该均衡期望值的方式可以如上述两个方案中所描述的技术方案，具体此处不再赘述。这样可以迅速的实现均衡期望值与判决阈值的收敛过程，从而实现对信号的线性和非线性均衡。
可选的，在该判决均衡装置更新该第一均衡期望值为该第二均衡期望值之后，该判决均衡装置根据该第二均衡期望值和第三均衡期望值更新所述第一组判决阈值中的至少一个判决阈值得到第二组判决阈值，所述第三均衡期望值为所述第二组均衡期望值中与所述第二均衡期望值相邻的均衡期望值。
可选的，该判决均衡装置还可以接收该判决反馈均衡器(decision feedback equalizer，DFE)系统输出的初始收敛参数，该初始收敛参数作为该输入信号在本实施例提供的判决均衡装置中进行判决均衡时的初始均衡期望值。这样可以保证在初始进行判决均衡时均衡期望值和判决阈值的可靠性，且加快均衡期望值和判决阈值的收敛过程。
可选的，该判决均衡装置还可以接收该FFE输出的自适应参数，该自适应参数作为该输入信号在本实施例提供的判决均衡装置中进行判决均衡时的初始均衡期望值。这样可以保证在初始进行判决均衡时均衡期望值和判决阈值的可靠性，且加快均衡期望值和判决阈值的收敛过程。
可选的，本实施例应用于PAM信号，而在该判决均衡装置进行信号判决均衡时，需要根据该PAM信号的电平数N与该判决值集合中的均衡信号数量M确定该判决均衡装置的判决电路的数量以及该判决均衡装置的判决阈值的数量，其中，N与M均取正整数。
可选的，该判决均衡装置根据所述PAM信号的电平数N与所述判决值集合中的均衡信号数量M利用第三公式确定判决电路的数量以及判决阈值的数量，其中，所述第三公式为：
Figure PCTCN2022090347-appb-000001
其中，所述S用于指示所述判决电路的数量，所述P用于指示所述判决阈值的数量，所述N用于指示所述PAM信号的电平数，所述M用于指示所述判决值集合中的均衡信号数量。
可选的，该判决均衡装置根据所述第一组均衡期望值、所述第一组判决阈值和所述输入信号确定所述输入信号的判决值包括：
该判决均衡装置根据所述第一组判决阈值、所述第一组均衡期望值和所述输入信号利用最大似然序列估计确定所述输入信号的判决值。
可选的，该判决均衡装置在确定该输入信号的判决电路时可以采用如下技术方案：该判决均衡装置根据判决值集合确定所述输入信号的判决电路，所述判决值集合包括至少一个判决值，所述至少一个判决值的发生时刻早于所述输入信号的发生时刻。本实施例中，该判决值集合中的判决值数量可以根据判决均衡装置的架构确定，比如，若该判决均衡装置为一抽头架构，则该判决值集合包括的是第一时刻输出的判决值。若该判决均衡装置为二抽头架构，则该判决值集合包括的是第二时刻输出的判决值。其中，该第二时刻早于该第一时刻，该第一时刻早于当前输入信号的发生时刻。
第二方面，本申请提供一种信号判决均衡方法，具体包括：该判决均衡装置获取输入信号，该输入信号为PAM信号或者为该PAM信号在经过预均衡后输出的预均衡信号(如为该PAM信号在经过前馈均衡器(feed forward equalizer，FFE)预均衡输出的预均衡信号)；然后该判决均衡装置确定该输入信号的判决电路；同时该判决均衡装置还获取该判决电路对应的第一组判决阈值和第一均衡期望值；然后该判决均衡装置根据该第一组均衡期望值、该第一组判决阈值以及该输入信号确定该输入信号的判决值，并输出该判决值；同时该判决均衡信号根据该判决值和该输入信号更新该第一组均衡期望值中的全部均衡期望值得到第二组均衡期望值；最后该判决均衡装置根据该第二组均衡期望值更新该第一组判决阈值中的全部判决阈值得到第二组判决阈值，其中，该第二组判决阈值和该第二组均衡期望值 用于该判决电路的下一次判决均衡。
本实施例中，对于该判决电路中的全部判决阈值进行更新的过程可以以现存技术的方法进行实现，具体此处不做赘述。
本实施例提供的技术方案中，该判决均衡装置根据判决电路输出的均衡信号对于判决电路的全部判决阈值进行迭代更新，即各个判决电路的更新迭代是相互独立，但是每一个判决电路中的判决阈值是关联迭代更新，这样实现各个判决电路的独立迭代更新，可以有效的对信号实现最优化均衡和判决，进而提升均衡性能，降低均衡后的误码率。
可选的，该判决均衡装置在根据该判决值和该输入信号更新该第一组均衡期望值中的全部衡期望值得到第二组均衡期望值时可以采用如下几种可能实现方式：
一种可能实现方式中，该判决均衡装置在每次进行判决均衡得到判决值之后就更新迭代判决电路对应的均衡期望值。
另一种可能实现方式中，该判决均衡装置在判决电路上的某一均衡期望值进行预设次数的判决均衡之后更新迭代该均衡期望值(即该判决电路上的某一个均衡期望值判决次数达到该预设次数，比如，均衡期望值为EV 33对应的判决值输出了4次之后，更新该均衡期望值EV 33为EV 33，new)。
另一种可能实现方式中，该判决均衡装置在预设时间段之后更新迭代该判决电路对应的均衡期望值。
可选的，在该判决均衡装置更新该第一组均衡期望值为该第二组均衡期望值之后，该判决均衡装置根据该第二组均衡期望值中的各个均衡期望值更新所述第一组判决阈值中的全部判决阈值得到第二组判决阈值。
可选的，该判决均衡装置还可以接收该DFE系统输出的初始收敛参数，该初始收敛参数作为该输入信号在本实施例提供的判决均衡装置中进行判决均衡时的初始均衡期望值。这样可以保证在初始进行判决均衡时均衡期望值和判决阈值的可靠性，且加快均衡期望值和判决阈值的收敛过程。
可选的，该判决均衡装置还可以接收该FFE输出的自适应参数，该自适应参数作为该输入信号在本实施例提供的判决均衡装置中进行判决均衡时的初始均衡期望值。这样可以保证在初始进行判决均衡时均衡期望值和判决阈值的可靠性，且加快均衡期望值和判决阈值的收敛过程。
可选的，本实施例应用于PAM信号，而在该判决均衡装置进行信号判决均衡时，需要根据该PAM信号的电平数N与该判决值集合中的均衡信号数量M确定该判决均衡装置的判决电路的数量以及该判决均衡装置的判决阈值的数量，其中，N与M均取正整数。
可选的，该判决均衡装置根据所述PAM信号的电平数N与所述判决值集合中的均衡信号数量M利用第三公式确定判决电路的数量以及判决阈值的数量，其中，所述第三公式为：
Figure PCTCN2022090347-appb-000002
其中，所述S用于指示所述判决电路的数量，所述P用于指示所述判决阈值的数量，所述N用于指示所述PAM信号的电平数，所述M用于指示所述判决值集合中的均衡信号数量。
可选的，该判决均衡装置根据所述第一组均衡期望值、所述第一组判决阈值和所述输入信号确定所述输入信号的判决值包括：
该判决均衡装置根据所述第一组判决阈值、所述第一组均衡期望值和所述输入信号利用最大似然序列估计确定所述输入信号的判决值。
可选的，该判决均衡装置在确定该输入信号的判决电路时可以采用如下技术方案：该判决均衡装置根据判决值集合确定所述输入信号的判决电路，所述判决值集合包括至少一个判决值，所述至少一个判决值的发生时刻早于所述输入信号的发生时刻。本实施例中，该判决值集合中的判决值数量可以根据判决均衡装置的架构确定，比如，若该判决均衡装置为一抽头架构，则该判决值集合包括的是第一时刻输出的判决值。若该判决均衡装置为二抽头架构，则该判决值集合包括的是第二时刻输出的判决值。其中，该第二时刻早于该第一时刻，该第一时刻早于当前输入信号的发生时刻。
第三方面，本申请实施例提供一种信号判决均衡装置，具体包括：该判决均衡装置获取输入信号，该输入信号为脉冲幅度调制(pulse amplitude modulation，PAM)信号或者为该PAM信号在经过预均衡后输出的预均衡信号(如为该PAM信号在经过前馈均衡器(feed forward equalizer，FFE)预均衡输出的预均衡信号)；然后该判决均衡装置确定该输入信号的判决电路；同时该判决均衡装置还获取该判决电路对应的第一组判决阈值和第一均衡期望值，所述第一组判决阈值的分布为不对称分布，所述第一组均衡期望值的分布为不对称分布；然后该判决均衡装置根据该第一组均衡期望值、该第一组判决阈值以及该输入信号确定该输入信号的判决值。
本实施例中，该判决均衡装置中的判决阈值和均衡期望值的分布情况与该信号的非线性特性相关，呈现不对称分布，则可以更加有效的对信号实现最优化均衡和判决，进而提升均衡性能，降低均衡后的误码率。
可选的，所述第一组判决阈值中的判决阈值数量等于所述PAM信号的电平数减一；
所述第一组均衡期望值中的均衡期望值数量等于所述PAM信号的电平数。
可选的，所述第一组均衡期望值是根据前一时刻的输入信号和所述前一时刻的输入信号判决输出的判决值更新前一时刻的均衡期望值得到，所述前一时刻早于所述输入信号的发生时刻，所述第一组判决阈值是根据所述第一组均衡期望值更新得到；
或者，
所述第一组均衡期望值是根据前N个时刻的输入信号和所述前N个时刻的输入信号判决输出的判决值更新前N个时刻的均衡期望值得到，所述前N个时刻早于所述输入信号的发生时刻，所述第一组判决阈值是根据所述第一组均衡期望值更新得到。
可选的，所述判决电路包含于判决电路集合，所述判决电路集合中的各路判决电路的判决阈值不相同，所述判决电路集合中的各路判决电路的均衡期望值不相同。即该判决均衡装置中各个判决电路可以实现独立调整，这样对于非线性信号可以实现最优化均衡和判决，进而提升均衡性能，降低均衡后的误码率。
可选的，该判决均衡装置在确定该输入信号的判决电路时可以采用如下技术方案：该判决均衡装置根据判决值集合确定所述输入信号的判决电路，所述判决值集合包括至少一 个判决值，所述至少一个判决值的发生时刻早于所述输入信号的发生时刻。本实施例中，该判决值集合中的判决值数量可以根据判决均衡装置的架构确定，比如，若该判决均衡装置为一抽头架构，则该判决值集合包括的是第一时刻输出的判决值。若该判决均衡装置为二抽头架构，则该判决值集合包括的是第二时刻输出的判决值。其中，该第二时刻早于该第一时刻，该第一时刻早于当前输入信号的发生时刻。
第四方面，本申请提供一种判决均衡装置，该系统具有实现上述第一方面中判决均衡装置行为的功能。该功能可以通过硬件实现，也可以通过硬件执行相应的软件实现。该硬件或软件包括一个或多个与上述功能相对应的模块。
在一个可能的实现方式中，该判决均衡装置包括用于执行以上第一方面各个步骤的单元或模块。例如，该判决均衡装置包括：获取模块，用于输入信号，该输入信号为脉冲幅度调制(pulse amplitude modulation，PAM)信号或者为该PAM信号在经过预均衡后输出的预均衡信号；
处理模块，用于确定所述输入信号的判决电路；
所述获取模块，还用于获取所述判决电路的第一组判决阈值和第一组均衡期望值；
所述处理模块，还用于根据所述第一组均衡期望值、所述第一组判决阈值和所述输入信号确定所述输入信号的判决值；
输出模块，用于输出所述判决值；
所述处理模块，还用于根据所述判决值和该输入信号更新所述第一组均衡期望值中的第一均衡期望值为第二均衡期望值得到第二组均衡期望值，所述第一均衡期望值为所述判决值对应的均衡期望值；根据所述第二均衡期望值更新所述第一组判决阈值中的至少一个判决阈值得到第二组判决阈值，所述第二组判决阈值与所述第二组均衡期望值用于所述判决电路的下一次判决均衡。
可选的，还包括存储模块，用于保存判决均衡装置必要的程序指令和数据。
在一种可能的实现方式中，该判决均衡装置包括：处理器和收发器，该处理器被配置为支持判决均衡装置执行上述第一方面提供的方法中相应的功能。收发器用于指示判决均衡装置和其他装置之间的通信，接收信号输入装置输出的PAM信号，输出PAM信号的均衡信号。可选的，此装置还可以包括存储器，该存储器用于与处理器耦合，其保存判决均衡装置必要的程序指令和数据。
在一种可能的实现方式中，当该系统为判决均衡装置内的芯片时，该芯片包括：处理模块和收发模块。该收发模块例如可以是该芯片上的输入/输出接口、管脚或电路等，该收发模块用于获取输入信号，该输入信号为脉冲幅度调制(pulse amplitude modulation，PAM)信号或者为该PAM信号在经过预均衡后输出的预均衡信号，并将该输入信号传送给该处理模块；该处理模块例如可以是处理器，此处理器用于确定所述输入信号的判决电路；该收发模块，还用于获取所述判决电路的第一组判决阈值和第一组均衡期望值，并将该第一组判决阈值和该第一组均衡期望值传送给该处理模块；该处理模块用于根据所述第一组均衡期望值、所述第一组判决阈值和所述输入信号确定所述输入信号的判决值；该收发模块还用于输出所述判决值，并将该判决值传送给与该芯片耦合的其他芯片或者模块；该处 理模块还用于根据所述判决值和该输入信号更新所述第一组均衡期望值中的第一均衡期望值为第二均衡期望值得到第二组均衡期望值，所述第一均衡期望值为所述判决值对应的均衡期望值；根据所述第二均衡期望值更新所述第一组判决阈值中的至少一个判决阈值得到第二组判决阈值，所述第二组判决阈值与所述第二组均衡期望值用于所述判决电路的下一次判决均衡。该处理模块可执行存储单元存储的计算机执行指令，以支持判决均衡装置执行上述第一方面提供的方法。可选地，该存储单元可以为该芯片内的存储单元，如寄存器、缓存等，该存储单元还可以是位于该芯片外部的存储单元，如只读存储器(read-only memory，ROM)或可存储静态信息和指令的其他类型的静态存储设备，随机存取存储器(random access memory，RAM)等。
在一种可能实现方式中，该系统包括通信接口和逻辑电路，该通信接口用于输入信号，该输入信号为脉冲幅度调制(pulse amplitude modulation，PAM)信号或者为该PAM信号在经过预均衡后输出的预均衡信号；该逻辑电路，用于确定所述输入信号的判决电路；该通信接口，还用于获取所述判决电路的第一组判决阈值和第一组均衡期望值；该逻辑电路，还用于根据所述第一组均衡期望值、所述第一组判决阈值和所述输入信号确定所述输入信号的判决值；该通信接口，还用于输出所述判决值；该逻辑电路，还用于根据所述判决值和该输入信号更新所述第一组均衡期望值中的第一均衡期望值为第二均衡期望值得到第二组均衡期望值，所述第一均衡期望值为所述判决值对应的均衡期望值；根据所述第二均衡期望值更新所述第一组判决阈值中的至少一个判决阈值得到第二组判决阈值，所述第二组判决阈值与所述第二组均衡期望值用于所述判决电路的下一次判决均衡。
其中，上述任一处提到的处理器，可以是一个通用中央处理器(Central Processing Unit，CPU)，微处理器，特定应用集成电路(application-specific integrated circuit，ASIC)，或一个或多个用于控制上述各方面数据传输方法的程序执行的集成电路。
第五方面，本申请实施例提供一种判决均衡装置，该系统具有实现上述第二方面中判决均衡装置行为的功能。该功能可以通过硬件实现，也可以通过硬件执行相应的软件实现。该硬件或软件包括一个或多个与上述功能相对应的模块。
在一个可能的实现方式中，该判决均衡装置包括用于执行以上第二方面各个步骤的单元或模块。例如，该判决均衡装置包括：获取模块，用于获取输入信号，该输入信号为脉冲幅度调制(pulse amplitude modulation，PAM)信号或者为该PAM信号在经过预均衡后输出的预均衡信号；
处理模块，用于确定所述输入信号的判决电路；
所述获取模块，还用于获取所述判决电路的第一组判决阈值和第一组均衡期望值；
所述处理模块，还用于根据所述第一组均衡期望值、所述第一组判决阈值和所述输入信号确定所述输入信号的判决值；
输出模块，用于输出所述判决值；
所述处理模块，还用于根据所述判决值和该输入信号更新所述第一组均衡期望值中的全部均衡期望值得到第二组均衡期望值；根据所述第二均衡期望值更新所述第一组判决阈值中的全部判决阈值得到第二组判决阈值，所述第二组判决阈值与所述第二组均衡期望值 用于所述判决电路的下一次判决均衡。
可选的，还包括存储模块，用于保存判决均衡装置必要的程序指令和数据。
在一种可能的实现方式中，该判决均衡装置包括：处理器和收发器，该处理器被配置为支持判决均衡装置执行上述第二方面提供的方法中相应的功能。收发器用于指示判决均衡装置和其他装置之间的通信，接收信号输入装置输出的PAM信号，输出PAM信号的均衡信号。可选的，此装置还可以包括存储器，该存储器用于与处理器耦合，其保存判决均衡装置必要的程序指令和数据。
在一种可能的实现方式中，当该系统为判决均衡装置内的芯片时，该芯片包括：处理模块和收发模块。该收发模块例如可以是该芯片上的输入/输出接口、管脚或电路等，该收发模块用于获取输入信号，该输入信号为脉冲幅度调制(pulse amplitude modulation，PAM)信号或者为该PAM信号在经过预均衡后输出的预均衡信号，并将该输入信号传送给该处理模块；该处理模块例如可以是处理器，此处理器用于确定所述输入信号的判决电路；该收发模块，还用于获取所述判决电路的第一组判决阈值和第一组均衡期望值，并将该第一组判决阈值和该第一组均衡期望值传送给该处理模块；该处理模块用于根据所述第一组均衡期望值、所述第一组判决阈值和所述输入信号确定所述输入信号的判决值；该收发模块还用于输出所述判决值，并将该判决值传送给与该芯片耦合的其他芯片或者模块；该处理模块还用于根据所述判决值和该输入信号更新所述第一组均衡期望值中的全部均衡期望值得到第二组均衡期望值；根据所述第二均衡期望值更新所述第一组判决阈值中的全部判决阈值得到第二组判决阈值，所述第二组判决阈值与所述第二组均衡期望值用于所述判决电路的下一次判决均衡。该处理模块可执行存储单元存储的计算机执行指令，以支持判决均衡装置执行上述第二方面提供的方法。可选地，该存储单元可以为该芯片内的存储单元，如寄存器、缓存等，该存储单元还可以是位于该芯片外部的存储单元，如只读存储器(read-only memory，ROM)或可存储静态信息和指令的其他类型的静态存储设备，随机存取存储器(random access memory，RAM)等。
在一种可能实现方式中，该系统包括通信接口和逻辑电路，该通信接口用于获取输入信号，该输入信号为脉冲幅度调制(pulse amplitude modulation，PAM)信号或者为该PAM信号在经过预均衡后输出的预均衡信号；该逻辑电路，用于确定所述输入信号的判决电路；该通信接口，还用于获取所述判决电路的第一组判决阈值和第一组均衡期望值；该逻辑电路，还用于根据所述第一组均衡期望值、所述第一组判决阈值和所述输入信号确定所述输入信号的判决值；该通信接口，还用于输出所述判决值；该逻辑电路，还用于根据所述判决值和该输入信号更新所述第一组均衡期望值中的全部均衡期望值得到第二组均衡期望值；根据所述第二均衡期望值更新所述第一组判决阈值中的全部判决阈值得到第二组判决阈值，所述第二组判决阈值与所述第二组均衡期望值用于所述判决电路的下一次判决均衡。
其中，上述任一处提到的处理器，可以是一个CPU，微处理器，ASIC，或一个或多个用于控制上述各方面数据传输方法的程序执行的集成电路。
第六方面，本申请实施例提供一种判决均衡装置，该装置具有实现上述第二方面中判 决均衡装置行为的功能。该功能可以通过硬件实现，也可以通过硬件执行相应的软件实现。该硬件或软件包括一个或多个与上述功能相对应的模块。
在一个可能的实现方式中，该判决均衡装置包括用于执行以上第三方面各个步骤的单元或模块。例如，该判决均衡装置包括：获取模块，用于获取输入信号，该输入信号为PAM信号或者为该PAM信号在经过预均衡后输出的预均衡信号；处理模块，用于确定所述输入信号的判决电路；所述获取模块，还用于获取所述判决电路的第一组判决阈值和第一组均衡期望值，所述第一组判决阈值的分布为不对称分布，所述第一组均衡期望值的分布为不对称分布；所述处理模块，还用于根据所述第一组均衡期望值、所述第一组判决阈值和所述输入信号确定所述输入信号的判决值。
可选的，还包括存储模块，用于保存判决均衡装置必要的程序指令和数据。
在一种可能的实现方式中，该判决均衡装置包括：处理器和收发器，该处理器被配置为支持判决均衡装置执行上述第三方面提供的方法中相应的功能。收发器用于指示判决均衡装置和其他装置之间的通信，接收信号输入装置输出的PAM信号，输出PAM信号的判决值。可选的，此装置还可以包括存储器，该存储器用于与处理器耦合，其保存判决均衡装置必要的程序指令和数据。
在一种可能的实现方式中，当该系统为判决均衡装置内的芯片时，该芯片包括：处理模块和收发模块。该收发模块例如可以是该芯片上的输入/输出接口、管脚或电路等，该收发模块用于获取输入信号，该输入信号为PAM信号或者为该PAM信号在经过预均衡后输出的预均衡信号，并将该输入信号传送给该处理模块；该处理模块例如可以是处理器，此处理器用于确定所述输入信号的判决电路；该收发模块，还用于获取所述判决电路的第一组判决阈值和第一组均衡期望值，并将该第一组判决阈值和该第一组均衡期望值传送给该处理模块；该处理模块用于根据所述第一组均衡期望值、所述第一组判决阈值和所述输入信号确定所述输入信号的判决值；该收发模块还用于输出所述判决值。该处理模块可执行存储单元存储的计算机执行指令，以支持判决均衡装置执行上述第二方面提供的方法。可选地，该存储单元可以为该芯片内的存储单元，如寄存器、缓存等，该存储单元还可以是位于该芯片外部的存储单元，如ROM或可存储静态信息和指令的其他类型的静态存储设备，RAM等。
在一种可能实现方式中，该系统包括通信接口和逻辑电路，该通信接口用于获取输入信号，该输入信号为PAM信号或者为该PAM信号在经过预均衡后输出的预均衡信号；该逻辑电路，用于确定所述输入信号的判决电路；该通信接口，还用于获取所述判决电路的第一组判决阈值和第一组均衡期望值；该逻辑电路，还用于根据所述第一组均衡期望值、所述第一组判决阈值和所述输入信号确定所述输入信号的判决值；该通信接口，还用于输出所述判决值。
其中，上述任一处提到的处理器，可以是一个CPU，微处理器，ASIC，或一个或多个用于控制上述各方面数据传输方法的程序执行的集成电路。
第七方面，本申请实施例提供一种计算机可读存储介质，该计算机存储介质存储有计算机指令，该计算机指令用于执行上述各方面中任意一方面任意可能的实施方式该的方法。
第八方面，本申请实施例提供一种包含指令的计算机程序产品，当其在计算机上运行时，使得计算机执行上述各方面中任意一方面该的方法。
第九方面，本申请提供了一种芯片系统，该芯片系统包括处理器，用于支持判决均衡装置实现上述方面中所涉及的功能，例如生成或处理上述方法中所涉及的数据和/或信息。在一种可能的设计中，该芯片系统还包括存储器，该存储器，用于保存判决均衡装置必要的程序指令和数据，以实现上述各方面中任意一方面的功能。该芯片系统可以由芯片构成，也可以包含芯片和其他分立器件。
第十方面，本申请实施例提供一种通信系统，该系统包括上述方面该的判决均衡装置。
附图说明
图1为一抽头的DFE架构示意图；
图2为本申请实施例的应用场景示意图；
图3a为本申请实施例中判决均衡装置的一个功能模块示意图；
图3b为本申请实施例中判决均衡装置的另一个功能模块示意图；
图3c为本申请实施例中判决均衡装置的另一个功能模块示意图；
图3d为本申请实施例中判决均衡装置的另一个功能模块示意图；
图4为本申请实施例中判决均衡装置与FFE结合的一个信号判决均衡示意图；
图5为本申请实施例中判决均衡装置的一个结构示意图；
图6为本申请实施例中非线性信号的判决均衡方法的一个实施例示意图；
图7为本申请实施例中非线性信号的判决均衡的一个架构示意图；
图8为本申请实施例中非线性信号的判决均衡的另一个架构示意图；
图9为本申请实施例中判决电路与判决阈值的示意图；
图10为本申请实施例中判决电路与判决阈值的一个示例性示意图；
图11为本申请实施例中FFE与判决均衡装置结合的架构示意图；
图12为本申请实施例中FFE、DFE与判决均衡装置结合的架构示意图；
图13为本申请实施例中判决阈值与均衡期望值更新迭代示意图；
图14至图17为应用本申请实施例中非线性信号的判决均衡方法与DFE架构下的判决均衡的性能对比图；
图18为FFE、判决均衡装置与MLSE结合的架构示意图；
图19为FFE、判决均衡装置与MLSE结合下MLSE的分支度量值的计算架构图；
图20为MLSE的工作原理图；
图21为应用本申请实施例中判决均衡装置与MLSE结合架构与传统MLSE的均衡性能对比图；
图22为本申请实施例中判决均衡装置的一个结构示意图；
图23为本申请实施例中判决均衡装置的另一个结构示意图。
具体实施方式
为了使本申请的目的、技术方案及优点更加清楚明白，下面结合附图，对本申请的实 施例进行描述，显然，所描述的实施例仅仅是本申请一部分的实施例，而不是全部的实施例。本领域普通技术人员可知，随着新应用场景的出现，本申请实施例提供的技术方案对于类似的技术问题，同样适用。
本申请的说明书和权利要求书及上述附图中的术语“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便这里描述的实施例能够以除了在这里图示或描述的内容以外的顺序实施。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，例如，包含了一系列步骤或模块的过程、方法、系统、产品或设备不必限于清楚地列出的那些步骤或模块，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或模块。在本申请中出现的对步骤进行的命名或者编号，并不意味着必须按照命名或者编号所指示的时间/逻辑先后顺序执行方法流程中的步骤，已经命名或者编号的流程步骤可以根据要实现的技术目的变更执行次序，只要能达到相同或者相类似的技术效果即可。本申请中所出现的单元的划分，是一种逻辑上的划分，实际应用中实现时可以有另外的划分方式，例如多个单元可以结合成或集成在另一个系统中，或一些特征可以忽略，或不执行，另外，所显示的或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，单元之间的间接耦合或通信连接可以是电性或其他类似的形式，本申请中均不作限定。并且，作为分离部件说明的单元或子单元可以是也可以不是物理上的分离，可以是也可以不是物理单元，或者可以分布到多个电路单元中，可以根据实际的需要选择其中的部分或全部单元来实现本申请方案的目的。
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚地描述。在本申请的描述中，除非另有说明，“/”表示或的意思，例如，A/B可以表示A或B；本申请中的“和/或”仅仅是一种描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。另外，在本申请的描述中，“至少一项”是指一项或者多项，“多项”是指两项或两项以上。“以下至少一项(个)”或其类似表达，是指的这些项中的任意组合，包括单项(个)或复数项(个)的任意组合。例如，a,b,或c中的至少一项(个)，可以表示：a,b,c,a-b,a-c,b-c,或a-b-c，其中a,b,c可以是单个，也可以是多个。
随着网络用户需求和数据流量的持续增加，高速链路技术成为芯片和接口的基础技术，包括电互联链路和光互联链路。从50Gbps传输系统开始，光电链路传输信号已经NRZ逐渐过渡到脉冲幅度调制(pulse amplitude modulation，PAM)，多电平的调制方式使得各种光电器件和信道的非线性特性开始显现出来，其造成的原因主要是光链路中发射端的啁啾与光纤色散的相互作用。电链路中发端的高低电平充放电，以及收端连续时间线性均衡器(continuous time linear equalizer,CTLE)等造成的非线性效应。链路中的非线性特性不但引入了码间干扰，而且导致信号失真，极大地影响了系统的传输特性，阻碍了系统数据传输速率的进一步提升。传统的线性自适应滤波器由于线性特性限制了其逼近非线性函数的能力，使滤波性能不尽如人意，无法很好地应对这一特性。近年来非线性滤波理论已成为业界研究的热点，对于目前100Gbps和未来更高速的传输系统，非线性均衡将成为一 个关键的技术能力。
目前DFE是较为常用的一种码间干扰均衡器。一种示例性方案中，如图1所示的PAM-4信号的一抽头的DFE架构，对接收到的FFE输出值y k在4路判决电路分别做判决得到均衡信号，然后根据上一个信号的判决值选择该y k对应的最终判决值。在图1所示的DFE架构中，4路判决电路的判决器阈值相同。即每一路的判决阈值均相同。一种示例性方案中，比如在第一时刻，每一路判决电路的判决阈值如图1所示为(-2，0，+2)，而在第二时刻在判决阈值更新之后，每一路判决电路的判决阈值为(-1.5，0，+1.5)。由于每一个判决电路的判决阈值相同，因此对于不同电平的信号无区别均衡，无法对于信道的非线性特性进行均衡。
为方便理解，下面对本申请实施例中涉及到的部分名词进行解释:
PAM信号：即通过PAM调制产生的信号。其中该PAM调制是指脉冲载波的幅度随基带信号变化的一种调制方式。
预均衡信号：本实施例中，该预均衡信号为该PAM信号在输入本申请实施例中提供的判决均衡装置之前经过其他均衡器进行均衡处理得到均衡信号。比如该PAM信号可以在经过FFE的均衡之后得到一个均衡信号。
判决阈值：相邻电平幅度的中间值。本实施例中，该判决阈值的数量与PAM信号的电平数相关。比如，PAM-4信号的四个电平分别为(+3，+1，-1，-3)，判决器中的判决阈值的数量为3，判决阈值为(+2，0，-2)。
均衡期望值：为当前配置下均衡器对信号均衡后的期望结果值。比如，PAM-4信号时，该均衡期望值可以取值为(+30，+10，-10，-30)。
判决值：判决器中根据判决阈值确定待均衡信号对应的判决结果。比如判决值的一种示例性取值可以为(+3，+1，-1，-3)。
为了解决这一问题，本申请实施例提供如下技术方案：该判决均衡装置获取输入信号，该输入信号为PAM信号或者为该PAM信号在经过预均衡后输出的预均衡信号；然后该判决均衡装置确定该输入信号的判决电路；同时该判决均衡装置还获取该判决电路对应的第一组判决阈值和第一均衡期望值；然后该判决均衡装置根据该第一组均衡期望值、该第一组判决阈值以及该输入信号确定该输入信号的判决值，并输出该判决值；同时该判决均衡装置根据该判决值和该输入信号更新该第一组均衡期望值中的第一均衡期望值为第二均衡期望值得到第二组均衡期望值，其中，该第一均衡期望值为该判决值对应的均衡期望值；最后该判决均衡装置根据该第二均衡期望值更新该第一组判决阈值中的至少一个判决阈值得到第二组判决阈值，其中，该第二组判决阈值和该第二组均衡期望值用于该判决电路的下一次判决均衡。
具体请参阅图2所示，本申请实施例提供的技术方案可以应用于有线光互联和光电互联等场景。具体包括但不限于：
(A)接口板卡(line processing unit，LPU)中芯片到芯片(比如结构接口控制器(fabric interface controller，FIC)，网络芯片(networking processor，NP)，介质访问控制(media access control，MAC))；
(B)芯片到灰光光模块；
(C)线卡与背板或电缆；
(D)交换网板(switch fabric units，SFU)到路由器集群；
(E)灰光光互联；
(F)长距彩光光光互联。
在上述各个应用场景中，一种示例性的方案中，该判决均衡装置的功能模块架构可以如图3a所示。PAM信号首先经过FFE均衡器进行初步均衡得到均衡后的预均衡信号(作为该判决均衡装置的输入信号)。随后，该判决均衡装置接收FFE输出的预均衡信号，通过判决模块和判决值选择模块，输出最终的判决值。其中，信号在通过判决模块和判决值选择模块时的具体流程为：该判决模块中的全部判决电路均对该预均衡信号进行再次均衡并输出判决值，而该判决值选择模块用于根据上一时刻的判决值确定最终判决值。该判决均衡装置的功能模块架构可以以IP核的形式落地到具体的芯片中。具体的芯片可以是路由器、交换机、光传送网(optical transport network，OTN)传输设备中应用的交换芯片或者接口芯片，以及任何需要高速通信接口的芯片中。
可以理解的是根据方案实现的先后顺序不同，该判决均衡装置的功能模块架构还可以如图3b所示，PAM信号首先经过FFE均衡器进行初步均衡得到均衡后的预均衡信号(作为该判决均衡装置的输入信号)。随后，该判决均衡装置接收FFE输出的预均衡信号，通过判决值选择模块和判决模块，输出最终的判决值。其中，信号在通过判决值选择模块和判决模块时的具体流程为：该判决值选择模块根据上一时刻的判决值确定信号的判决电路；然后该判决模块选择该判决电路对该预均衡信号进行再次均衡得到最终判决值。该判决均衡装置的功能模块架构可以以IP核的形式落地到具体的芯片中。具体的芯片可以是路由器、交换机、光传送网(optical transport network，OTN)传输设备中应用的交换芯片或者接口芯片，以及任何需要高速通信接口的芯片中。
一种示例性的方案中，该判决均衡装置的功能模块架构可以如图3c所示。该判决均衡装置接收PAM信号(该PAM信号作为该判决均衡模块的输入信号)，通过判决模块和判决值选择模块，输出最终的判决值。其中，PAM信号在通过判决模块和判决值选择模块时的具体流程为：该判决模块中的全部判决电路均对该PAM信号进行均衡并输出判决值，而该判决值选择模块用于根据上一时刻的判决值确定最终判决值，并输出该最终判决值。该判决均衡装置的功能模块架构可以以IP核的形式落地到具体的芯片中。具体的芯片可以是路由器、交换机、光传送网(optical transport network，OTN)传输设备中应用的交换芯片或者接口芯片，以及任何需要高速通信接口的芯片中。
可以理解的是根据方案实现的先后顺序不同，该判决均衡装置的功能模块架构还可以如图3d所示。该判决均衡装置接收PAM信号(该PAM信号作为该判决均衡模块的输入信号)，通过判决模块和判决值选择模块，输出最终的判决值。其中，PAM信号在通过判决模块和判决值选择模块时的具体流程为：该判决值选择模块根据上一时刻的判决值确定PAM信号的判决电路；然后该判决模块选择该判决电路对该PAM信号进行均衡得到最终判决值。该判决均衡装置的功能模块架构可以以IP核的形式落地到具体的芯片中。具体的芯片可以是 路由器、交换机、光传送网(optical transport network，OTN)传输设备中应用的交换芯片或者接口芯片，以及任何需要高速通信接口的芯片中。
而在整体信号的均衡过程中，其主要包括的功能模块架构的一个示例性方案可以如图4所示，主要包括FFE和判决均衡装置。而该FFE对PAM信号进行初步均衡得到均衡后的预均衡信号，然后该判决均衡装置中的判决模块和判决值选择模块对该预均衡信号进行再次的判决均衡并输出判决值。
图5为本申请实施例中判决均衡装置的硬件结构示意图。如图5所示，判决均衡装置至少包括处理器501，存储器502，和收发器503，存储器502进一步用于存储指令5021和数据5022。可选的，该判决均衡装置还可以包括I/O(输入/输出，Input/Output)接口504和总线505。收发器503进一步包括发射器5031和接收器5032。此外，处理器501，收发器503，存储器502和I/O接口504通过总线505彼此通信连接。
处理器501可以是通用处理器，例如但不限于，中央处理器(central processing unit，CPU)，也可以是专用处理器，例如但不限于，数字信号处理器(digital signal processor，DSP)，应用专用集成电路(application specific integrated circuit，ASIC)和现场可编程门阵列(field programmable gate array，FPGA)等。该处理器501还可以是神经网络处理单元(neural processing unit，NPU)。此外，处理器501还可以是多个处理器的组合。特别的，在本申请实施例提供的技术方案中，处理器501可以用于执行，后续方法实施例中生成以太报文的方法的相关步骤。处理器501可以是专门设计用于执行上述步骤和/或操作的处理器，也可以是通过读取并执行存储器502中存储的指令5021来执行上述步骤和/或操作的处理器，处理器501在执行上述步骤和/或操作的过程中可能需要用到数据5022。
收发器503包括发射器5031和接收器5032。发射器5031和接收器5032可以执行后续方法实施例中判决均衡的方法应用于判决均衡装置时，判决均衡装置中接收模块或发送模块所执行的操作。
在本申请实施例中，收发器503用于支持判决均衡装置执行前述的接收功能和发送功能。将具有处理功能的处理器视为处理器501。接收器5032也可以称为输入口、接收电路等，发射器5031可以称为发射器或者发射电路等。
处理器501可用于执行该存储器502存储的指令，以控制收发器503接收消息和/或发送消息，完成本申请方法实施例中判决均衡装置的功能。作为一种实现方式，收发器503的功能可以考虑通过收发电路或者收发的专用芯片实现。本申请实施例中，收发器503接收消息可以理解为收发器503输入消息，收发器503发送消息可以理解为收发器503输出消息。
存储器502可以是各种类型的存储介质，例如随机存取存储器(Random Access Memory，RAM)，只读存储器(Read Only Memory，ROM)，非易失性RAM(Non-Volatile RAM，NVRAM)，可编程ROM(Programmable ROM，PROM)，可擦除PROM(Erasable PROM，EPROM)，电可擦除PROM(Electrically Erasable PROM，EEPROM)，闪存，光存储器和寄存器等。存储器502具体用于存储指令5021和数据5022，处理器501可以通过读取并执行存储器502中存储的指令5021，来执行本申请方法实施例中所述的步骤和/或操作，在执行本申请方法实施 例中操作和/或步骤的过程中可能需要用到数据5022。
可选的，该判决均衡装置还可以包括I/O接口504，该I/O接口504用于接收来自外围设备的指令和/或数据，以及向外围设备输出指令和/或数据。
本申请实施例的技术方案可以应用于各种通信系统，例如：全球移动通讯(Global System of Mobile Communication，GSM)系统、码分多址(Code Division Multiple Access，CDMA)系统、宽带码分多址(Wideband Code Division Multiple Access，WCDMA)系统、长期演进(Long Term Evolution，LTE)系统、LTE频分双工(Frequency Division Duplex，FDD)系统、LTE时分双工(Time Division Duplex，TDD)、通用移动通信系统(Universal Mobile Telecommunication System，UMTS)、5G通信系统、以及未来的无线通信系统等。
具体请参阅图6所示，本申请实施例中信号判决均衡方法的一个实施例包括：
601、该判决均衡装置获取输入信号，该输入信号为PAM信号或该PAM信号在经过预均衡后输出的预均衡信号。
该判决均衡装置接收该输入信号，其中，该输入信号可以是PAM信号也可以是已经经过该FFE初步均衡后的均衡信号。比如，第一时刻该FFE输出的均衡信号为30，则该判决均衡装置接收到的输入信号为30。或者该第一时刻该判决装置直接接收到未进行均衡过的PAM信号。
602、该判决均衡装置根据判决值集合确定该输入信号的判决电路，该判决值集合包括至少一个判决值，该至少一个判决值的发生时刻早于该输入信号的发生时刻。
该判决均衡装置获取该输入信号发生时刻之间的判决值集合，然后根据该判决值集合对应的判决值确定该输入信号的判决电路。
本实施例中，该判决电路为该判决均衡装置最终选择判决值的判决电路，但是此处并未限定其他判决电路对该输入信号是否进行判决均衡。即该判决均衡装置的工作模式包括如下几种可能情况：
一种可能实现方式如图7所示，该判决均衡装置接收该输入信号之后，将该输入信号输入至全部的判决电路，判决电路均进行判决均衡并输出判决值；然后该判决均衡装置根据该确定该输入信号选择最终判决值的判决电路。
另一种可能实现方式如图8所示，该判决均衡装置接收该输入信号之后，根据该判决值集合确定该输入信号选择最终判决值的判决电路；然后将该输入信号输入该判决电路进行判决均衡，并输出对应的判决值。
可以理解的是，该判决值集合包括至少一个均衡信号。如图7和图8所示的一抽头的PAM-4信号中，该判决值集合中包括一个均衡信号。如图7和图8所示，假设当前时刻为d k，则该判决值集合中的均衡信号为d k-1时刻的均衡信号。
本实施例中，该PAM-4中的4用于指示该PAM信号的电平数，而该PAM信号可以包括多种情况的电平数，比如电平数可以为8。该电平数和该判决值集合中的均衡信号的数量可以影响该判决均衡装置中的判决电路的数量和判决阈值的数量，其具体包括：该判决均衡装置根据所述PAM信号的电平数N与所述判决值集合中的均衡信号数量M利用第三公式确定判决电路的数量以及判决阈值的数量，其中，所述第三公式为：
Figure PCTCN2022090347-appb-000003
其中，所述S用于指示所述判决电路的数量，所述P用于指示所述判决阈值的数量，所述N用于指示所述PAM信号的电平数，所述M用于指示所述判决值集合中的均衡信号数量(也可以称为均衡架构的抽头数，一抽头时，该M取值为1，二抽头时，该M取值为2)。其判决均衡架构可以如图9所示。一种示例性方案中，在该电平数为4，该判决值集合中包括一个均衡信号(也称为一抽头架构)时，该判决均衡装置中的判决电路可以如图7和图8所示为4路判决电路(+3，+1，-1，-3)，每路判决电路包括3个判决阈值(2，0，-2)，该判决均衡装置中总共有12个判决阈值。若该电平数为4，该判决值集合包括2个均衡信号，该判决均衡装置中的判决电路可以如图10所示为16路判决电路(+3+3，+3+1，+3-1，+3-3，+1+3，+1+1，+1-1，+1-3，-1+3，-1+1，-1-1，-1-3，-3+3，-3+1，-3-1，-3-3)，每路判决电路包括3个判决阈值(2，0，-2)，该判决均衡装置中总共有64个判决阈值。
603、该判决均衡装置获取所述判决电路的第一组判决阈值和第一组均衡期望值。
该判决均衡装置获取该判决电路当前时刻对应的第一组判决阈值和该第一组均衡期望值。
本实施例中，该判决均衡装置可以与FFE组合进行信号判决均衡，具体如图11所示；同时该判决均衡装置、FFE跟DFE组合进行信号判决均衡，具体如图12所示。在图11所示的架构中，该判决均衡装置中初始期望值可以是由该FFE输出的自适应参数。在图12所示的架构中，该判决均衡装置中初始期望值可以是由该DFE输出的收敛参数。可选的，该判决均衡装置中初始期望值也可以是预设，具体此处不做限定。
604、该判决均衡装置根据所述第一组均衡期望值、所述第一组判决阈值和所述输入信号确定所述输入信号的判决值。
该判决均衡装置根据该第一组均衡期望值、该第一组判决阈值对该输入信号进行判决均衡输出该输入信号的判决值。
本实施例中，假设该第一组均衡期望为(+30，+10，-10，-30)，该第一组判决阈值为(+20，0，-20)，判决值为(+3，+1，-1，-3)，该输入信号为25，则该判决值为+3，该判决值对应的均衡期望值为+30。
可以理解的是，该均衡期望值、判决阈值、判决电路，判决值之间的关系可以如下：
该均衡期望值的中间值为该判决阈值，而该判决电路对应的判决值可以与该均衡期望值存在对应关系。如图7所示的架构，该判决阈值为(+2，0，-2)，该均衡期望值为(+3，+1，-1，-3)，该判决值为(+3，+1，-1，-3)，各个判决电路可设置为+3对应的判决电路，+1对应的判决电路，-1对应的判决电路以及-3对应的判决电路。同时，若该图7所示的架构中，该判决阈值为(+20，0，-20)，该均衡期望值为(+30，+10，-10，-30)，该判决值为(+3，+1，-1，-3)，而各个判决电路同样也可以设置为+3对应的判决电路，+1对应的判决电路，-1对应的判决电路以及-3对应的判决电路。即判决均衡输出的均衡信号为+30时，该判决值为+3，对应的是+3对应的判决电路；判决均衡输出的均衡信号为+10时，该判决值为+1，对应的是+1对应的判决电路；判决均衡输出的均衡信号为-10时，该判决值 为-1，对应的是-1对应的判决电路；判决均衡输出的均衡信号为-30时，该判决值为-3，对应的是-3对应的判决电路。
605、该判决均衡装置输出该判决值。
606、该判决均衡装置根据所述判决值和该输入信号更新所述第一组均衡期望值中的第一均衡期望值为第二均衡期望值得到第二组均衡期望值，所述第一均衡期望值为所述判决值对应的均衡期望值。
在该判决均衡装置得到该判决值后，该判决均衡装置还可以如图7所示，对输出该判决值的判决电路的第一组均衡期望值中的第一均衡期望值进行更新得到第二均衡期望值，从而得到第二组均衡期望值，其中该第一均衡期望值为该判决值对应的均衡期望值。
具体来说，该均衡期望值的更新过程可以包括如下几种可能实现方式：
一种可能实现方式中，该判决均衡装置在每次进行判决均衡得到判决值之后就更新迭代判决电路对应的均衡期望值。一种示例性方案中，该方案具体包括：该判决均衡装置根据该第一均衡期望值和该输入信号确定该判决电路的判决误差；然后根据该判决误差更新该第一均衡期望值为该第二均衡期望值。这样可以迅速的实现均衡期望值与判决阈值的收敛过程，从而实现对信号的线性和非线性均衡。
可选的，本实施例中，该判决误差等于该第一均衡期望值减去该输入信号。一种示例性方案中，该判决误差的计算方式可以如表1所示：
表1
y k≤T i0 e k＝EV i0-y k
T i0＜y k≤T i1 e k＝EV i1-y k
T i1<y k≤T i2 e k＝EV i2-y k
y k>T i2 e k＝EV i3-y k
其中，该y k用于指示该输入信号，该e k用于指示该判决误差，该T i0、T i1、T i2用于指示第i路判决电路上的判决阈值，该EV i0、EV i1、EV i2、EV i3用于指示第i路判决电路上的均衡期望值。一种示例性方案中，假设当前第k时刻输入信号y k进入图8的第一路(即+3对应的判决电路)进行判决，此时刻第一路的第一组判决阈值T 30，T 31，T 32的值分别为-20，0，+20，第一组均衡期望值EV 30，EV 31，EV 32，EV 33的值为-30，-10，+10，+30。如果y k＝25，那么判决输出判决值d k＝+3，判决误差e k为EV 33-y k＝5；如果y k＝15，那么判决输出判决值d k＝+1，判决误差e k为EV 32-y k＝-5；如果y k＝-15，那么判决输出判决值d k＝-1，判决误差e k为EV 31-y k＝+5；如果y k＝-25，那么判决输出判决值d k＝-3，判决误差e k为EV 32-y k＝-5。
可以理解的是，该输入信号与该判决阈值之间的判决关系还可以是其他关系，具体此处不做限定。
可选的，该判决均衡装置根据该判决误差更新该第一均衡期望值为该第二均衡期望值的方法具体包括：
一种可能实现方式中，该判决均衡装置根据该判决误差和第一公式更新该第一均衡期 望值为该第二均衡期望值；
该第一公式为：
EV new＝EV old-sign(e k)；
其中，该EV new用于指示该第二均衡期望值，该EV old用于指示该第一均衡期望值，该e k用于指示该判决误差，所述k用于指示当前时刻。
一种示例性方案中，如果k-1时刻的判决值d k-1＝+3，当前第k时刻输入信号y k进入图8的第一路(即+3对应的判决电路)进行判决，假设此时刻第一路的第一组判决阈值T 30，T 31，T 32的值分别为-20，0，+20，第一组均衡期望值EV 30，EV 31，EV 32，EV 33的值为-30，-10，+10，+30。如果y k＝25，那么判决输出判决值d k＝+3，判决误差e k为EV 33-y k＝5。此例中，EV 33，new＝EV 33-sign(e k)＝30-sign(5)＝29。其余的EV的值保持不变。
另一种可能实现方式中，该判决均衡装置根据该判决误差和第二公式更新该第一均衡期望值为该第二均衡期望值；
该第二公式为：
EV new＝EV old-μ*(e k)；
其中，该EV new用于指示该第二均衡期望值，该EV old用于指示该第一均衡期望值，该e k用于指示该判决误差，该μ用于指示预设常数，所述k用于指示当前时刻。
一种示例性方案中，如果k-1时刻的判决值d k-1＝+3，当前第k时刻输入信号y k进入图8的第一路(即+3对应的判决电路)进行判决，假设此时刻第一路的第一组判决阈值T 30，T 31，T 32的值分别为-20，0，+20，第一组均衡期望值EV 30，EV 31，EV 32，EV 33的值为-30，-10，+10，+30。如果y k＝25，那么判决输出判决值d k＝+3，判决误差e k为EV 33-y k＝5。此例中，EV 33，new＝EV 33-μ*e k＝30-0.1*5＝29.5。其余的EV的值保持不变。
另一种可能实现方式中，该判决均衡装置在判决电路上的某一均衡期望值进行预设次数的判决均衡之后更新迭代该均衡期望值(即该判决电路上的某一个均衡期望值判决次数达到该预设次数，比如，均衡期望值为EV 33对应的判决值输出了4次之后，更新该均衡期望值EV 33为EV 33，new)。一种示例性方案中，该方案具体包括：
该判决均衡装置根据该输入信号和该第一均衡期望值得到判决误差，该判决均衡装置记录该判决误差生成判决误差集合，该判决误差集合包括该第一均衡期望值对应的判决误差；在该判决误差集合中判决误差的数量达到预设数量时，该判决均衡装置根据该判决误差集合中的判决误差确定最终判决误差；并根据所述最终判决误差更新所述第一均衡期望值为所述第二均衡期望值。这样可以迅速的实现均衡期望值与判决阈值的收敛过程，从而 实现对信号的线性和非线性均衡。
可以理解的是，本实施例中，该判决均衡装置在记录该判决误差时可以直接对该判决误差进行取符号计算，然后将计算得到的值记录为判决误差集合；最后在判决误差集合中的判决误差对应的值的数量达到预设数量之后再根据该判决误差集合中的值确定最终判决误差，并根据该最终判决误差将该第一均衡期望值更新为该第二均衡期望值。一种示例性方案中，该第一均衡期望值对应的判决误差分别为(-2，+4，+1，-5)，则在对该判决误差进行取符号计算之后得到的判决误差集合记录为(-1，+1，+1，-1)，那最终判决误差则为0，则该第一均衡期望值在此次更新中不用更新。若该第一均衡期望值对应的判决误差分别为(-2，+4，+1，+1)，则在对该判决误差进行取符号计算之后得到的判决误差集合记录为(-1，+1，+1，+1)，那最终判决误差则为2，则该第一均衡期望值根据该最终判决误差更新为第二均衡期望值。这样可以降低判决均衡装置在记录判决误差中的操作复杂度。
可选的，本实施例中，该最终判决误差等于该多个判决误差之和。
可选的，本实施例中，该判决均衡装置根据该最终判决误差更新该第一均衡期望值为该第二均衡期望值具体包括：
一种可能实现方式中，该判决均衡装置根据该最终判决误差和第一公式更新该第一均衡期望值为该第二均衡期望值；
该第一公式为：
EV new＝EV old-sign(e k)；
其中，该EV new用于指示该第二均衡期望值，该EV old用于指示该第一均衡期望值，该e k用于指示该最终判决误差，所述k用于指示当前时刻。
另一种可能实现方式中，该判决均衡装置根据该判决误差和第二公式更新该第一均衡期望值为该第二均衡期望值；
该第二公式为：
EV new＝EV old-μ*(e k)；
其中，该EV new用于指示该第二均衡期望值，该EV old用于指示该第一均衡期望值，该e k用于指示该最终判决误差，该μ用于指示预设常数，所述k用于指示当前时刻。
例如：系统设置为每个参数进行4次判决后更新该参数，即P＝4。假设+3对应的判决电路中EV 33的四次的判决误差分别为+2、-4、-1、+1，e k＝+2-4-1+1＝-2。如果采用“取符号”算法，则EV 33，new＝EV 33-sign(e k)＝30-sign(-2)＝31。如果采用“乘系数”算法，则EV 33，new＝EV 33-μ*e k＝30-0.1*(-2)＝30.2。
另一种可能实现方式中，该判决均衡装置在预设时间段之后更新迭代该判决电路对应的均衡期望值。一种可能实现方式中，该判决均衡装置统计在预设时间段内各个判决电路上各个均衡期望值对应的判决误差；然后该判决均衡装置根据各个均衡期望值对应的判决误差更新该各个均衡期望值。同理，本实施例中，该判决均衡装置在记录该判决误差时可以直接对该判决误差进行取符号计算，然后将计算得到的值记录为判决误差集合；最后在判决误差集合中的判决误差对应的值的数量达到预设数量之后再根据该判决误差集合中的 值确定最终判决误差，并根据该最终判决误差将该第一均衡期望值更新为该第二均衡期望值。一种示例性方案中，该第一均衡期望值对应的判决误差分别为(-2，+4，+1，-5)，则在对该判决误差进行取符号计算之后得到的判决误差集合记录为(-1，+1，+1，-1)，那最终判决误差则为0，则该第一均衡期望值在此次更新中不用更新。若该第一均衡期望值对应的判决误差分别为(-2，+4，+1，+1)，则在对该判决误差进行取符号计算之后得到的判决误差集合记录为(-1，+1，+1，+1)，那最终判决误差则为2，则该第一均衡期望值根据该最终判决误差更新为第二均衡期望值。这样可以降低判决均衡装置在记录判决误差中的操作复杂度。
可以理解的是，更新该均衡期望值的方式可以如上述两个方案中所描述的技术方案，具体此处不再赘述。这样可以迅速的实现均衡期望值与判决阈值的收敛过程，从而实现对信号的线性和非线性均衡。例如：系统设置每隔1个小时对各个参数进行更新。而在这一个小时内，+3对应的判决电路中EV 33的四次的判决误差分别为+2、-4、-1、+1，e k＝+2-4-1+1＝-2。如果采用“取符号”算法，则
EV 33，new＝EV 33-sign(e k)＝30-sign(-2)＝31。
如果采用“乘系数”算法，则
EV 33，new＝EV 33-μ*e k＝30-0.1*(-2)＝30.2。
而+1对应的判决电路中EV 33的四次的判决误差分别为+2、+4、-1、+1，e k＝+2+4-1+1＝6。如果采用“取符号”算法，则
EV 33，new＝EV 33-sign(e k)＝30-sign(6)＝29。
如果采用“乘系数”算法，则
EV 33，new＝EV 33-μ*e k＝30-0.1*(6)＝29.4。
607、该判决均衡装置根据所述第二均衡期望值更新所述第一组判决阈值中的至少一个判决阈值得到第二组判决阈值，所述第二组判决阈值与所述第二组均衡期望值用于所述判决电路的下一次判决均衡。
在该判决均衡装置在更新得到该第二均衡期望值之后，该判决均衡装置根据该第二均衡期望值以及与其相邻的第三均衡期望值计算更新该第一组判决阈值中的至少一个判决阈值得到该第二组判决阈值。
本实施例中，该第三均衡期望值可以根据该第二均衡期望值的位置关系确定或者该第三均衡期望值可以根据该第二均衡期望值的位置以及该输入信号与该第二均衡期望值之间的位置关系确定。
一种示例性方案中，若第一组判决阈值为T 30，T 31，T 32，第一组均衡期望值EV 30，EV 31，EV 32，EV 33，而该EV 33进行了更新，则第三均衡期望值则只有EV 32。若EV 32进行了更新，则该第三均衡期望值可以为EV 33和/或EV 31。
比如，第一组判决阈值T 30，T 31，T 32的值分别为-20，0，+20，第一组均衡期望值EV 30， EV 31，EV 32，EV 33的值为-30，-10，+10，+30，而该EV 33由+30更新为29，则该T 32将更新为T 32，new＝(EV 33+EV 32)/2＝(29+10)/2＝19.5。
若第一组判决阈值T 30，T 31，T 32的值分别为-20，0，+20，第一组均衡期望值EV 30，EV 31，EV 32，EV 33的值为-30，-10，+10，+30，而该EV 32由+10更新为11，则该T 32将更新为T 32，new＝(EV 33+EV 32)/2＝(30+11)/2＝20.5，同时，该T 31将更新为
T 31，new＝(EV 31+EV 32)/2＝(-10+11)/2＝0.5。
若第一组判决阈值T 30，T 31，T 32的值分别为-20，0，+20，第一组均衡期望值EV 30，EV 31，EV 32，EV 33的值为-30，-10，+10，+30，而该EV 32由+10更新为11，但是该输入信号位于该EV 32和EV 33之间，则只更新T 32，并将T 32更新为T 32，new＝(EV 33+EV 32)/2＝(30+11)/2＝20.5。
若第一组判决阈值T 30，T 31，T 32的值分别为-20，0，+20，第一组均衡期望值EV 30，EV 31，EV 32，EV 33的值为-30，-10，+10，+30，y k＝15，而该EV 32由+10更新为11，但是该输入信号位于该EV 32和EV 33之间，则只更新T 32，并将T 32更新为T 32，new＝(EV 33+EV 32)/2＝(30+11)/2＝20.5。
若第一组判决阈值T 30，T 31，T 32的值分别为-20，0，+20，第一组均衡期望值EV 30，EV 31，EV 32，EV 33的值为-30，-10，+10，+30，y k＝5，而该EV 32由+10更新为9，但是该输入信号位于该EV 32和EV 31之间，则只更新T 31，并将T 31更新为T 31，new＝(EV 31+EV 32)/2＝(-10+9)/2＝-0.5。
一种示例性方案中，该均衡期望值与该判决阈值的更新迭代流程可以如图13所示，即对于每一个误差值，其将更新该判决均衡装置中的一个均衡期望值，而该均衡期望值将会更新一个或者两个判决阈值。
本实施例中以实际信道的信号判决均衡进行说明，如图14所示，由于DFE架构的判决 器只与当前信号有关，所以DFE产生的判决阈值和均衡期望值根据收敛参数在四个电平无区别均匀分布。而本实施例提供的判决均衡装置把之前信号和当前信号的情况都考虑在迭代计算中，针对信道的非线性特征，本实施例提供的判决均衡装置对不同的信号序列收敛为不同的判决阈值和均衡期望值，进而对信道的非线性做出对应的均衡。而由于本实施例提供的判决均衡装置产生的非均匀判决阈值(或均衡期望值)更加接近信道的非线性特性，以本实施例提供的一抽头判决均衡装置与一抽头DFE均衡器为例进行对比可发现，本本实施例提供的一抽头判决均衡装置的均衡性能将强于一抽头DFE均衡器，具体效果可以如图15至图17所示。可以理解的是，图14至图17中的动态非线性判决(dynamic nonlinear slicing，DNS)即为本申请实施提供的判决均衡装置。
本实施例中该判决均衡装置根据判决电路输出的均衡信号对于判决电路的各个判决阈值进行迭代更新，从而实现各个判决阈值独立迭代更新，可以更加有效的对信号实现最优化均衡和判决，进而提升均衡性能，降低均衡后的误码率。
上面描述了该判决均衡装置本身进行信号均衡的方案，实际应用中，该判决均衡装置还可以与其他信号判决均衡架构进行结合，从而实现信号均衡。具体请参阅图18所示，该判决均衡装置与最大似然序列估计(maximum likelihood sequence estimation，MLSE)架构结合，并进行信号判决均衡。在该架构中，本申请实施例提供的判决均衡装置提供均衡期望值作为MLSE的输入，参与至分支度量值的计算中，使得在MLSE算法更加贴近信道特性，有效地实现均衡非线性特性。此时，MLSE均衡过程中分支度量值的计算架构可以如图19所示，而该计算可以表达为：
bm ij＝[y k-EV ij] 2；
其中，该y k用于指示该输入信号，该EV ij用于指示该判决均衡装置输出的均衡期望值，该bm ij用于指示分支度量值，所述k用于指示当前时刻。
该MLSE完成每一时刻每一状态的分支度量值计算后，会根据如图20所示工作原理选择出当前时刻每个状态的幸存路径(黑色实绩)，根据回溯长度，计算整个序列的幸存路径，并根据最大似然准则，选择距离最接近接收信号的发射序列(图20灰色实线)，即可得到t-D+1时刻的状态值。
通过如图21所示的本申请实施例提供的判决均衡装置与MLSE结合之后均衡性和传统MLSE的均衡性能对比图可以看到，本申请实施例提供的判决均衡装置可以帮助MLSE提高误码率性能约一个量级。
本实施例中，还提供一种非线性信号的判决均衡方法，在此方案中，该判决均衡装置获取输入信号，该输入信号为脉冲幅度调制(pulse amplitude modulation，PAM)信号或者为该PAM信号在经过预均衡后输出的预均衡信号；然后该判决均衡装置确定该输入信号的判决电路；同时该判决均衡装置还获取该判决电路对应的第一组判决阈值和第一均衡期望值；然后该判决均衡装置根据该第一组均衡期望值、该第一组判决阈值以及该输入信号确定该输入信号的判决值，并输出该判决值；同时该判决均衡信号根据该判决值和该输入 信号更新该第一组均衡期望值中的全部均衡期望值得到第二组均衡期望值；最后该判决均衡装置根据该第二组均衡期望值更新该第一组判决阈值中的全部判决阈值得到第二组判决阈值，其中，该第二组判决阈值和该第二组均衡期望值用于该判决电路的下一次判决均衡。
本实施例中，在更新一路判决电路的判决阈值与均衡期望值时可以采用现存的技术方案，具体此处不再赘述。一种示例性方案中，设置判决值集合的半眼高(HEH)系数，即缩放系数为10。如果k-1时刻的判决值d k-1＝+3，当前第k时刻输入信号y k进入图8的第一路(即+3对应的判决电路)进行判决，假设此时刻第一路的第一组判决阈值T 30，T 31，T 32的值分别为-20，0，+20(其中，该-20等于-2*缩放系数，该0等于0*缩放系数，该+20等于+2*缩放系数)，第一组均衡期望值EV 30，EV 31，EV 32，EV 33的值为-30，-10，+10，+30(其中，该-30等于-3*缩放系数，该-10等于-1*缩放系数，该+10等于+1*缩放系数，该+30等于+3*缩放系数)。如果y k＝25，那么判决输出d k＝+3，判决误差e k为EV 33-y k＝5。如果选择“取符号”算法，那么参数更新过程取误差的符号，此例中缩放系统将更新为HEH new＝HEH old-sign(e k)＝10-sign(5)＝9。因此，该第一路判决电路的判决阈值将更新为-18，0，+18，该第一路判决电路的均衡期望值更新为-27，-9，+9，+27。
此外该方案的其他操作与上述实施例相同，此处不再赘述。
本实施例提供的技术方案中，该判决均衡装置根据判决电路输出的均衡信号对于判决电路的全部判决阈值进行迭代更新，即各个判决电路的更新迭代是相互独立，但是每一个判决电路中的判决阈值是关联迭代更新，这样实现各个判决电路的独立迭代更新，可以有效的对信号实现最优化均衡和判决，进而提升均衡性能，降低均衡后的误码率。
上面描述了本申请实施例中信号的判决均衡方法，可以理解的是，判决均衡装置为了实现上述功能，其包含了执行各个功能相应的硬件结构和/或软件模块。本领域技术人员应该很容易意识到，结合本文中所公开的实施例描述的各示例的模块及算法步骤，本申请能够以硬件或硬件和计算机软件的结合形式来实现。某个功能究竟以硬件还是计算机软件驱动硬件的方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
本申请实施例可以根据上述方法示例对判决均衡装置进行功能模块的划分，例如，可以对应各个功能划分各个功能模块，也可以将两个或两个以上的功能集成在一个处理模块中。上述集成的模块既可以采用硬件的形式实现，也可以采用软件功能模块的形式实现。需要说明的是，本申请实施例中对模块的划分是示意性的，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式。
下面对本申请中的判决均衡装置进行详细描述，请参阅图22，图22为本申请实施例中判决均衡装置的一种实施例示意图。判决均衡装置可以部署于路由器、交换机、OTN传输设备中，判决均衡装置2200包括：
获取模块2201，用于获取输入信号，该输入信号为脉冲幅度调制(pulse amplitude modulation，PAM)信号或者为该PAM信号在经过预均衡后输出的预均衡信号；
处理模块2202，用于确定所述输入信号的判决电路；
所述获取模块2201，还用于获取所述判决电路的第一组判决阈值和第一组均衡期望值；
所述处理模块2202，还用于根据所述第一组均衡期望值、所述第一组判决阈值和所述输入信号确定所述输入信号的判决值；
输出模块2203，用于输出所述判决值；
所述处理模块2202，还用于根据所述判决值和输入信号更新所述第一组均衡期望值中的第一均衡期望值为第二均衡期望值得到第二组均衡期望值，所述第一均衡期望值为所述判决值对应的均衡期望值；根据所述第二均衡期望值更新所述第一组判决阈值中的至少一个判决阈值得到第二组判决阈值，所述第二组判决阈值与所述第二组均衡期望值用于所述判决电路的下一次判决均衡。
一种可能实现方式中，所述处理模块2202，具体用于根据所述第一均衡期望值和所述输入信号确定所述判决电路的判决误差；根据所述判决误差更新所述第一均衡期望值为所述第二均衡期望值。
一种可能实现方式中，所述判决误差等于所述第一均衡期望值减去所述输入信号。
一种可能实现方式中，所述处理模块2202，具体用于
根据所述判决误差和第一公式更新所述第一均衡期望值为所述第二均衡期望值；
所述第一公式为：
EV new＝EV old-sign(e k)；
其中，所述EV new用于指示所述第二均衡期望值，所述EV old用于指示所述第一均衡期望值，所述e k用于指示所述判决误差，所述k用于指示当前时刻；
或者，
所述处理模块2202，具体用于根据所述判决误差和第二公式更新所述第一均衡期望值为所述第二均衡期望值；
所述第二公式为：
EV new＝EV old-μ*(e k)；
其中，所述EV new用于指示所述第二均衡期望值，所述EV old用于指示所述第一均衡期望值，所述e k用于指示所述判决误差，所述μ用于指示预设常数，所述k用于指示当前时刻。
一种可能实现方式中，所述处理模块2202，具体用于根据输入信号和所述第一均衡期望值得到判决误差；记录所述判决误差生成判决误差集合，所述判决误差集合包括所述第一均衡期望值对应的判决误差；在所述判决误差集合中判决误差的数量达到预设数量时，根据所述判决误差信号集合中的判决误差确定最终判决误差；根据所述最终判决误差更新所述第一均衡期望值为所述第二均衡期望值。一种可能实现方式中，所述最终判决误差等于所述多个判决误差之和。
一种可能实现方式中，所述处理模块2202，具体用于根据所述第二均衡期望值与第三均衡期望值更新中的至少一个判决阈值得到第二组判决阈值，所述第三均衡期望值为所述第二组均衡期望值中与所述第二均衡期望值相邻的均衡期望值。
一种可能实现方式中，所述获取模块2201，还用于
接收判决反馈均衡器DFE模式输出的初始收敛参数，所述初始收敛参数作为所述输入信号在判决均衡时的初始均衡期望值。
一种可能实现方式中，所述获取模块2201，还用于
接收前馈均衡器输出的自适应参数，所述自适应参数作为所述输入信号在判决均衡时的初始均衡期望值。
一种可能实现方式中，所述处理模块2202，还用于
根据所述PAM信号的电平数N与所述判决值集合中的均衡信号数量M确定判决电路的数量以及判决阈值的数量，所述M为正整数。
一种可能实现方式中，所述处理模块2202，具体用于
根据所述PAM信号的电平数N与所述判决值集合中的均衡信号数量M利用第三公式确定判决电路的数量以及判决阈值的数量，其中，所述第三公式为：
Figure PCTCN2022090347-appb-000004
其中，所述S用于指示所述判决电路的数量，所述P用于指示所述判决阈值的数量，所述N用于指示所述PAM信号的电平数，所述M用于指示所述判决值集合中的均衡信号数量。
一种可能实现方式中，所述处理模块2202，具体用于
根据所述第一组判决阈值、所述第一组均衡期望值和所述输入信号利用最大似然序列估计确定所述输入信号的判决值。
可选的，所述处理模块2202，具体用于根据判决值集合确定所述输入信号的判决电路，所述均衡信号组包括至少一个判决值，所述至少一个判决值的发生时刻早于所述输入信号的发生时刻。
上述实施例中的判决均衡装置可以是网络设备或者用户设备，也可以是应用于网络设备中的芯片或者其他可实现上述网络设备功能的组合器件、部件等。当判决均衡装置是网络设备时，收发模块可以是收发器，处理模块可以是处理器，例如芯片等。当判决均衡装置是芯片系统时，收发模块中用于接收的部分可以是芯片系统的输入端口，收发模块中用于发送的部分可以是芯片系统的输出接口、处理模块可以是芯片系统的处理器，例如：中央处理器(central processing unit，CPU)。
在本申请实施例中，该判决均衡装置所包括的存储器主要用于存储软件程序和数据，例如存储上述实施例中所描述的程序等。该判决均衡装置还具有以下功能：
收发器，用于获取输入信号，该输入信号为脉冲幅度调制(pulse amplitude modulation，PAM)信号或者为该PAM信号在经过预均衡后输出的预均衡信号；
处理器，用于确定所述输入信号的判决电路；
收发器，还用于获取所述判决电路的第一组判决阈值和第一组均衡期望值；
所述处理器，还用于根据所述第一组均衡期望值、所述第一组判决阈值和所述输入信号确定所述输入信号的判决值；
收发器，用于输出所述判决值；
所述处理器，还用于根据所述判决值的输入信号更新所述第一组均衡期望值中的第一均衡期望值为第二均衡期望值得到第二组均衡期望值，所述第一均衡期望值为所述判决值对应的均衡期望值；根据所述第二均衡期望值更新所述第一组判决阈值中的至少一个判决阈值得到第二组判决阈值，所述第二组判决阈值与所述第二组均衡期望值用于所述判决电路的下一次判决均衡。
一种可能实现方式中，所述处理器，具体用于根据所述第一均衡期望值和所述输入信号确定所述判决电路的判决误差；根据所述判决误差更新所述第一均衡期望值为所述第二均衡期望值。
一种可能实现方式中，所述判决误差等于所述第一均衡期望值减去所述输入信号。
一种可能实现方式中，所述处理器，具体用于
根据所述判决误差和第一公式更新所述第一均衡期望值为所述第二均衡期望值；
所述第一公式为：
EV new＝EV old-sign(e k)；
其中，所述EV new用于指示所述第二均衡期望值，所述EV old用于指示所述第一均衡期望值，所述e k用于指示所述判决误差，所述k用于指示当前时刻；
或者，
所述处理器，具体用于根据所述判决误差和第二公式更新所述第一均衡期望值为所述第二均衡期望值；
所述第二公式为：
EV new＝EV old-μ*(e k)；
其中，所述EV new用于指示所述第二均衡期望值，所述EV old用于指示所述第一均衡期望值，所述e k用于指示所述判决误差，所述μ用于指示预设常数，所述k用于指示当前时刻。
一种可能实现方式中，所述处理器，具体用于根据输入信号和所述第一均衡期望值得到判决误差；记录所述判决误差生成判决误差集合，所述判决误差集合包括所述第一均衡期望值对应的判决误差；在所述判决误差集合中判决误差的数量达到预设数量时，根据所述判决误差信号集合中的判决误差确定最终判决误差；根据所述最终判决误差更新所述第一均衡期望值为所述第二均衡期望值。
一种可能实现方式中，所述最终判决误差等于所述多个判决误差之和。
一种可能实现方式中，所述处理器，具体用于根据所述第二均衡期望值与第三均衡期望值更新中的至少一个判决阈值得到第二组判决阈值，所述第三均衡期望值为所述第二组均衡期望值中与所述第二均衡期望值相邻的均衡期望值。
一种可能实现方式中，所述收发器，还用于
接收判决反馈均衡器DFE模式输出的初始收敛参数，所述初始收敛参数作为所述输入信号在判决均衡时的初始均衡期望值。
一种可能实现方式中，所述收发器，还用于
接收前馈均衡器输出的自适应参数，所述自适应参数作为所述输入信号在判决均衡时的初始均衡期望值。
一种可能实现方式中，所述处理器，还用于
根据所述PAM信号的电平数N与所述判决值集合中的均衡信号数量M确定判决电路的数量以及判决阈值的数量，所述M为正整数。
一种可能实现方式中，所述处理器，具体用于
根据所述PAM信号的电平数N与所述判决值集合中的均衡信号数量M利用第三公式确定判决电路的数量以及判决阈值的数量，其中，所述第三公式为：
Figure PCTCN2022090347-appb-000005
其中，所述S用于指示所述判决电路的数量，所述P用于指示所述判决阈值的数量，所述N用于指示所述PAM信号的电平数，所述M用于指示所述判决值集合中的均衡信号数量。
一种可能实现方式中，所述处理器，具体用于根据判决值集合确定所述输入信号的判决电路，所述均衡信号组包括至少一个判决值，所述至少一个判决值的发生时刻早于所述输入信号的发生时刻。
根据所述第一组判决阈值、所述第一组均衡期望值和所述输入信号利用最大似然序列估计确定所述输入信号的判决值。
一种可能实现方式中，所述处理器，具体用于
一种可能实现方式中，所述处理器，具体用于根据判决值集合确定所述输入信号的判决电路，所述均衡信号组包括至少一个判决值，所述至少一个判决值的发生时刻早于所述输入信号的发生时刻。
本申请实施例还提供了一种处理装置。处理装置包括处理器和接口；该处理器，用于执行上述任一方法实施例的信号判决均衡方法。
应理解，上述处理装置可以是一个芯片，该处理器可以通过硬件实现也可以通过软件来实现，当通过硬件实现时，该处理器可以是逻辑电路、集成电路等；当通过软件来实现时，该处理器可以是一个通用处理器，通过读取存储器中存储的软件代码来实现，该存储器可以集成在处理器中，可以位于该处理器之外，独立存在。
其中，“通过硬件实现”是指通过不具有程序指令处理功能的硬件处理电路来实现上述模块或者单元的功能，该硬件处理电路可以通过分立的硬件元器件组成，也可以是集成电路。为了减少功耗、降低尺寸，通常会采用集成电路的形式来实现。硬件处理电路可以包括ASIC(application-specific integrated circuit，专用集成电路)，或者PLD(programmable logic device，可编程逻辑器件)；其中，PLD又可包括FPGA(field programmable gate array，现场可编程门阵列)、CPLD(complex programmable logic device，复杂可编程逻辑器件)等等。这些硬件处理电路可以是单独封装的一块半导体芯片(如封装成一个ASIC)；也可以跟其他电路(如CPU、DSP)集成在一起后封装成一个半导体芯片， 例如，可以在一个硅基上形成多种硬件电路以及CPU，并单独封装成一个芯片，这种芯片也称为SoC，或者也可以在硅基上形成用于实现FPGA功能的电路以及CPU，并单独封闭成一个芯片，这种芯片也称为SoPC(system on a programmable chip，可编程片上系统)。
请参阅图23，图23为本申请实施例中判决均衡装置的一种实施例示意图。判决均衡装置可以部署于路由器、交换机、OTN传输设备中，判决均衡装置2300包括：获取模块2301，用于获取输入信号所述输入信号为脉冲幅度调制PAM信号或者为所述PAM信号在经过预均衡后输出的预均衡信号；
处理模块2302，用于确定所述输入信号的判决电路；
所述获取模块2301，还用于获取所述判决电路的第一组判决阈值和第一组均衡期望值，所述第一组判决阈值的分布为不对称分布，所述第一组均衡期望值的分布为不对称分布，
所述处理模块2302，还用于根据所述第一组均衡期望值、所述第一组判决阈值和所述输入信号确定所述输入信号的判决值。
该判决均衡装置2300还包括输出模块2303，用于输出该判决值。
一种可能实现方式中，所述第一组判决阈值中的判决阈值数量等于所述PAM信号的电平数减一；
所述第一组均衡期望值中的均衡期望值数量等于所述PAM信号的电平数。
一种可能实现方式中，所述第一组均衡期望值是根据前一时刻的输入信号和所述前一时刻的输入信号判决输出的判决值更新前一时刻的均衡期望值得到，所述前一时刻早于所述输入信号的发生时刻，所述第一组判决阈值是根据所述第一组均衡期望值更新得到；
或者，
所述第一组均衡期望值是根据前N个时刻的输入信号和所述前N个时刻的输入信号判决输出的判决值更新前N个时刻的均衡期望值得到，所述前N个时刻早于所述输入信号的发生时刻，所述第一组判决阈值是根据所述第一组均衡期望值更新得到。
一种可能实现方式中，所述判决电路包含于判决电路集合，所述判决电路集合中的各路判决电路的判决阈值不相同，所述判决电路集合中的各路判决电路的均衡期望值不相同。
一种可能实现方式中，所述处理模块2302，具体用于根据判决值集合确定所述输入信号的判决电路，所述均衡信号组包括至少一个判决值，所述至少一个判决值的发生时刻早于所述输入信号的发生时刻。
上述实施例中的判决均衡装置可以是网络设备或者用户设备，也可以是应用于网络设备中的芯片或者其他可实现上述网络设备功能的组合器件、部件等。当判决均衡装置是网络设备时，收发模块可以是收发器，处理模块可以是处理器，例如芯片等。当判决均衡装置是芯片系统时，收发模块中用于接收的部分可以是芯片系统的输入端口，收发模块中用于发送的部分可以是芯片系统的输出接口、处理模块可以是芯片系统的处理器，例如：中央处理器(central processing unit，CPU)。
在本申请实施例中，该判决均衡装置所包括的存储器主要用于存储软件程序和数据，例如存储上述实施例中所描述的程序等。该判决均衡装置还具有以下功能：
收发器，用于获取输入信号所述输入信号为脉冲幅度调制PAM信号或者为所述PAM信号在经过预均衡后输出的预均衡信号；
处理器，用于确定所述输入信号的判决电路；
收发器，还用于获取所述判决电路的第一组判决阈值和第一组均衡期望值，所述第一组判决阈值的分布为不对称分布，所述第一组均衡期望值的分布为不对称分布，
处理器，还用于根据所述第一组均衡期望值、所述第一组判决阈值和所述输入信号确定所述输入信号的判决值。
一种可能实现方式中，所述第一组判决阈值中的判决阈值数量等于所述PAM信号的电平数减一；
所述第一组均衡期望值中的均衡期望值数量等于所述PAM信号的电平数。
一种可能实现方式中，所述第一组均衡期望值是根据前一时刻的输入信号和所述前一时刻的输入信号判决输出的判决值更新前一时刻的均衡期望值得到，所述前一时刻早于所述输入信号的发生时刻，所述第一组判决阈值是根据所述第一组均衡期望值更新得到；
或者，
所述第一组均衡期望值是根据前N个时刻的输入信号和所述前N个时刻的输入信号判决输出的判决值更新前N个时刻的均衡期望值得到，所述前N个时刻早于所述输入信号的发生时刻，所述第一组判决阈值是根据所述第一组均衡期望值更新得到。
一种可能实现方式中，所述判决电路包含于判决电路集合，所述判决电路集合中的各路判决电路的判决阈值不相同，所述判决电路集合中的各路判决电路的均衡期望值不相同。
一种可能实现方式中，所述处理器，具体用于根据判决值集合确定所述输入信号的判决电路，所述均衡信号组包括至少一个判决值，所述至少一个判决值的发生时刻早于所述输入信号的发生时刻。
本申请实施例还提供了一种处理装置。处理装置包括处理器和接口；该处理器，用于执行上述任一方法实施例的信号判决均衡方法。
应理解，上述处理装置可以是一个芯片，该处理器可以通过硬件实现也可以通过软件来实现，当通过硬件实现时，该处理器可以是逻辑电路、集成电路等；当通过软件来实现时，该处理器可以是一个通用处理器，通过读取存储器中存储的软件代码来实现，该存储器可以集成在处理器中，可以位于该处理器之外，独立存在。
其中，“通过硬件实现”是指通过不具有程序指令处理功能的硬件处理电路来实现上述模块或者单元的功能，该硬件处理电路可以通过分立的硬件元器件组成，也可以是集成电路。为了减少功耗、降低尺寸，通常会采用集成电路的形式来实现。硬件处理电路可以包括ASIC(application-specific integrated circuit，专用集成电路)，或者PLD(programmable logic device，可编程逻辑器件)；其中，PLD又可包括FPGA(field programmable gate array，现场可编程门阵列)、CPLD(complex programmable logic device，复杂可编程逻辑器件)等等。这些硬件处理电路可以是单独封装的一块半导体芯片(如封装成一个ASIC)；也可以跟其他电路(如CPU、DSP)集成在一起后封装成一个半导体芯片，例如，可以在一个硅基上形成多种硬件电路以及CPU，并单独封装成一个芯片，这种芯片 也称为SoC，或者也可以在硅基上形成用于实现FPGA功能的电路以及CPU，并单独封闭成一个芯片，这种芯片也称为SoPC(system on a programmable chip，可编程片上系统)。
本申请实施例还提供的一种计算机可读存储介质，包括指令，当其在计算机上运行时，使得计算机控制判决均衡装置执行如前述方法实施例所示任一项实现方式。
本申请实施例还提供的一种计算机程序产品，计算机程序产品包括计算机程序代码，当计算机程序代码在计算机上运行时，使得计算机执行如前述方法实施例所示任一项实现方式。
本申请实施例还提供一种芯片系统，包括存储器和处理器，存储器用于存储计算机程序，处理器用于从存储器中调用并运行计算机程序，使得芯片执行如前述方法实施例所示任一项实现方式。
本申请实施例还提供一种芯片系统，包括处理器，处理器用于调用并运行计算机程序，使得芯片执行如前述方法实施例所示任一项实现方式。
另外需说明的是，以上所描述的装置实施例仅仅是示意性的，其中所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部模块来实现本实施例方案的目的。另外，本申请提供的装置实施例附图中，模块之间的连接关系表示它们之间具有通信连接，具体可以实现为一条或多条通信总线或信号线。
通过以上的实施方式的描述，所属领域的技术人员可以清楚地了解到本申请可借助软件加必需的通用硬件的方式来实现，当然也可以通过专用硬件包括专用集成电路、专用CPU、专用存储器、专用元器件等来实现。一般情况下，凡由计算机程序完成的功能都可以很容易地用相应的硬件来实现，而且，用来实现同一功能的具体硬件结构也可以是多种多样的，例如模拟电路、数字电路或专用电路等。但是，对本申请而言更多情况下软件程序实现是更佳的实施方式。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分可以以软件产品的形式体现出来，该计算机软件产品存储在可读取的存储介质中，如计算机的软盘、U盘、移动硬盘、ROM、RAM、磁碟或者光盘等，包括若干指令用以使得一台计算机设备执行本申请各个实施例所述的方法。
在上述实施例中，可以全部或部分地通过软件、硬件、固件或者其任意组合来实现。当使用软件实现时，可以全部或部分地以计算机程序产品的形式实现。
所述计算机程序产品包括一个或多个计算机指令。在计算机上加载和执行所述计算机程序指令时，全部或部分地产生按照本申请实施例所述的流程或功能。所述计算机可以是通用计算机、专用计算机、计算机网络、或者其他可编程装置。所述计算机指令可以存储在计算机可读存储介质中，或者从一个计算机可读存储介质向另一计算机可读存储介质传输，例如，所述计算机指令可以从一个网站站点、计算机、第一网络设备或第二网络设备、计算设备或数据中心通过有线(例如同轴电缆、光纤、数字用户线(DSL))或无线(例如红外、无线、微波等)方式向另一个网站站点、计算机、第一网络设备或第二网络设备、计算设备或数据中心进行传输。所述计算机可读存储介质可以是计算机能够存储的任何可 用介质或者是包含一个或多个可用介质集成的第一网络设备或第二网络设备、数据中心等数据存储设备。所述可用介质可以是磁性介质，(例如，软盘、硬盘、磁带)、光介质(例如，DVD)、或者半导体介质(例如固态硬盘(Solid State Disk，SSD))等。
应理解，说明书通篇中提到的“一个实施例”或“一实施例”意味着与实施例有关的特定特征、结构或特性包括在本申请的至少一个实施例中。因此，在整个说明书各处出现的“在一个实施例中”或“在一实施例中”未必一定指相同的实施例。此外，这些特定的特征、结构或特性可以任意适合的方式结合在一个或多个实施例中。应理解，在本申请的各种实施例中，上述各过程的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本申请实施例的实施过程构成任何限定。
另外，本文中术语“系统”和“网络”在本文中常被可互换使用。应理解，在本申请实施例中，“与A相应的B”表示B与A相关联，根据A可以确定B。但还应理解，根据A确定B并不意味着仅仅根据A确定B，还可以根据A和/或其它信息确定B。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、计算机软件或者二者的结合来实现，为了清楚地说明硬件和软件的可互换性，在上述说明中已经按照功能一般性地描述了各示例的组成及步骤。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
所属领域的技术人员可以清楚地了解到，为了描述的方便和简洁，上述描述的系统、装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统，装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。
集成的单元如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的全部或部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本申请各个实施例方法的全部或部分步骤。
总之，以上所述仅为本申请技术方案的较佳实施例而已，并非用于限定本申请的保护范围。凡在本申请的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本申请的保护范围之内。

Claims (40)

  1. 一种信号判决均衡方法，其特征在于，包括：
    获取输入信号，所述输入信号为脉冲幅度调制PAM信号或者为所述PAM信号在经过预均衡后输出的预均衡信号；
    确定所述输入信号的判决电路；
    获取所述判决电路的第一组判决阈值和第一组均衡期望值；
    根据所述第一组均衡期望值、所述第一组判决阈值和所述输入信号确定所述输入信号的判决值，并输出所述判决值；
    根据所述判决值和所述输入信号更新所述第一组均衡期望值中的第一均衡期望值为第二均衡期望值得到第二组均衡期望值，所述第一均衡期望值为所述判决值对应的均衡期望值；
    根据所述第二均衡期望值更新所述第一组判决阈值中的至少一个判决阈值得到第二组判决阈值，所述第二组判决阈值与所述第二组均衡期望值用于所述判决电路的下一次判决均衡。
  2. 根据权利要求1所述的方法，其特征在于，所述根据所述判决值和所述输入信号更新所述第一组均衡期望值中的第一均衡期望值为第二均衡期望值得到第二组均衡期望值包括：
    根据所述第一均衡期望值和所述输入信号确定所述判决电路的判决误差；
    根据所述判决误差更新所述第一均衡期望值为所述第二均衡期望值。
  3. 根据权利要求2所述的方法，其特征在于，所述判决误差等于所述第一均衡期望值减去所述输入信号。
  4. 根据权利要求2或3所述的方法，其特征在于，所述根据所述判决误差更新所述第一均衡期望值为所述第二均衡期望值包括：
    根据所述判决误差和第一公式更新所述第一均衡期望值为所述第二均衡期望值；
    所述第一公式为：
    EV new＝EV old-sign(e k)；
    其中，所述EV new用于指示所述第二均衡期望值，所述EV old用于指示所述第一均衡期望值，所述e k用于指示所述判决误差，所述k用于指示当前时刻；
    或者，
    根据所述判决误差和第二公式更新所述第一均衡期望值为所述第二均衡期望值；
    所述第二公式为：
    EV new＝EV old-μ*(e k)；
    其中，所述EV new用于指示所述第二均衡期望值，所述EV old用于指示所述第一均衡期 望值，所述e k用于指示所述判决误差，所述μ用于指示预设常数，所述k用于指示当前时刻。
  5. 根据权利要求1所述的方法，其特征在于，所述根据所述判决值和所述输入信号更新所述第一组均衡期望值中的第一均衡期望值为第二均衡期望值得到第二组均衡期望值包括：
    根据所述输入信号和所述第一均衡期望值得到判决误差；
    记录所述判决误差生成判决误差集合，所述判决误差集合包括所述第一均衡期望值对应的判决误差；
    在所述判决误差集合中判决误差的数量达到预设数量时，
    根据所述判决误差信号集合中的判决误差确定最终判决误差；
    根据所述最终判决误差更新所述第一均衡期望值为所述第二均衡期望值。
  6. 根据权利要求5所述的方法，其特征在于，所述最终判决误差等于所述多个判决误差之和。
  7. 根据权利要求1至6中任一项所述的方法，其特征在于，所述根据所述第二均衡期望值更新所述第一组判决阈值中的至少一个判决阈值得到第二组判决阈值包括：
    根据所述第二均衡期望值与第三均衡期望值更新所述第一组判决阈值中的至少一个判决阈值得到第二组判决阈值，所述第三均衡期望值为所述第二组均衡期望值中与所述第二均衡期望值相邻的均衡期望值。
  8. 根据权利要求1至7中任一项所述的方法，其特征在于，所述方法还包括：
    接收判决反馈均衡器DFE系统输出的初始收敛参数，所述初始收敛参数作为所述输入信号在判决均衡时的初始均衡期望值。
  9. 根据权利要求1至7中任一项所述的方法，其特征在于，所述方法还包括：
    接收前馈均衡器输出的自适应参数，所述自适应参数作为所述输入信号在判决均衡时的初始均衡期望值。
  10. 根据权利要求1至9中任一项所述的方法，其特征在于，所述方法还包括：
    根据所述PAM信号的电平数N与所述判决值集合中的均衡信号数量M确定判决电路的数量以及判决阈值的数量，所述M为正整数。
  11. 根据权利要求10所述的方法，其特征在于，所述根据所述PAM信号的电平数N与所述判决值集合中的均衡信号数量M确定判决电路的数量以及判决阈值的数量包括：
    根据所述PAM信号的电平数N与所述判决值集合中的均衡信号数量M利用第三公式确定判决电路的数量以及判决阈值的数量，其中，所述第三公式为：
    Figure PCTCN2022090347-appb-100001
    其中，所述S用于指示所述判决电路的数量，所述P用于指示所述判决阈值的数量，所述N用于指示所述PAM信号的电平数，所述M用于指示所述判决值集合中的均衡信号数量。
  12. 根据权利要求1至11中任一项所述的方法，其特征在于，所述根据所述第一组均衡期望值、所述第一组判决阈值和所述输入信号确定所述输入信号的判决值包括：
    根据所述第一组判决阈值、所述第一组均衡期望值和所述输入信号利用最大似然序列估计确定所述输入信号的判决值。
  13. 根据权利要求1至12中任一项所述的方法，其特征在于，所述确定所述输入信号的判决电路包括：
    根据判决值集合确定所述输入信号的判决电路，所述均衡信号组包括至少一个判决值，所述至少一个判决值的发生时刻早于所述输入信号的发生时刻。
  14. 一种判决均衡装置，其特征在于，包括：
    获取模块，用于获取输入信号，所述输入信号为脉冲幅度调制PAM信号或者为所述PAM信号在经过预处理后输出的预均衡信号；
    处理模块，用于确定所述输入信号的判决电路；
    所述获取模块，还用于获取所述判决电路的第一组判决阈值和第一组均衡期望值；
    所述处理模块，还用于根据所述第一组均衡期望值、所述第一组判决阈值和所述输入信号确定所述输入信号的判决值；
    输出模块，用于输出所述判决值；
    所述处理模块，还用于根据所述判决值和所述输入信号更新所述第一组均衡期望值中的第一均衡期望值为第二均衡期望值得到第二组均衡期望值，所述第一均衡期望值为所述判决值对应的均衡期望值；根据所述第二均衡期望值更新所述第一组判决阈值中的至少一个判决阈值得到第二组判决阈值，所述第二组判决阈值与所述第二组均衡期望值用于所述判决电路的下一次判决均衡。
  15. 根据权利要求14所述的装置，其特征在于，所述处理模块，具体用于根据所述第一均衡期望值和所述输入信号确定所述判决电路的判决误差；
    根据所述判决误差更新所述第一均衡期望值为所述第二均衡期望值。
  16. 根据权利要求15所述的装置，其特征在于，所述判决误差等于所述第一均衡期望值减去所述输入信号。
  17. 根据权利要求15或16所述的装置，其特征在于，所述处理模块，具体用于根据所 述判决误差和第一公式更新所述第一均衡期望值为所述第二均衡期望值；
    所述第一公式为：
    EV new＝EV old-sign(e k)；
    其中，所述EV new用于指示所述第二均衡期望值，所述EV old用于指示所述第一均衡期望值，所述e k用于指示所述判决误差，所述k用于指示当前时刻；
    或者，
    所述处理模块，具体用于根据所述判决误差和第二公式更新所述第一均衡期望值为所述第二均衡期望值；
    所述第二公式为：
    EV new＝EV old-μ*(e k)；
    其中，所述EV new用于指示所述第二均衡期望值，所述EV old用于指示所述第一均衡期望值，所述e k用于指示所述判决误差，所述μ用于指示预设常数，所述k用于指示当前时刻。
  18. 根据权利要求14所述的装置，其特征在于，所述处理模块，具体用于根据所述输入信号和所述第一均衡期望值得到判决误差；
    记录所述判决误差生成判决误差集合，所述判决误差集合包括所述第一均衡期望值对应的判决误差；
    在所述判决误差集合中判决误差的数量达到预设数量时，根据所述判决误差信号集合中的判决误差确定最终判决误差；
    根据所述最终判决误差更新所述第一均衡期望值为所述第二均衡期望值。
  19. 根据权利要求18所述的装置，其特征在于，所述最终判决误差等于所述多个判决误差之和。
  20. 根据权利要求14至19中任一项所述的装置，其特征在于，所述处理模块，具体用于根据所述第二均衡期望值与第三均衡期望值更新中的至少一个判决阈值得到第二组判决阈值，所述第三均衡期望值为所述第二组均衡期望值中与所述第二均衡期望值相邻的均衡期望值。
  21. 根据权利要求14至20中任一项所述的装置，其特征在于，所述获取模块，还用于接收判决反馈均衡器DFE模式输出的初始收敛参数，所述初始收敛参数作为所述输入信号在判决均衡时的初始均衡期望值。
  22. 根据权利要求14至20中任一项所述的装置，其特征在于，所述获取模块，还用于接收前馈均衡器输出的自适应参数，所述自适应参数作为所述输入信号在判决均衡时的初始均衡期望值。
  23. 根据权利要求14至22中任一项所述的装置，其特征在于，所述处理模块，还用于根据所述PAM信号的电平数N与所述判决值集合中的均衡信号数量M确定判决电路的数量以及判决阈值的数量，所述M为正整数。
  24. 根据权利要求23所述的装置，其特征在于，所述处理模块，具体用于
    根据所述PAM信号的电平数N与所述判决值集合中的均衡信号数量M利用第三公式确定判决电路的数量以及判决阈值的数量，其中，所述第三公式为：
    Figure PCTCN2022090347-appb-100002
    其中，所述S用于指示所述判决电路的数量，所述P用于指示所述判决阈值的数量，所述N用于指示所述PAM信号的电平数，所述M用于指示所述判决值集合中的均衡信号数量。
  25. 根据权利要求14至24中任一项所述的装置，其特征在于，所述处理模块，具体用于根据所述第一组判决阈值、所述第一组均衡期望值和所述输入信号利用最大似然序列估计确定所述输入信号的判决值。
  26. 根据权利要求14至25中任一项所述的装置，其特征在于，所述处理模块，具体用于根据判决值集合确定所述输入信号的判决电路，所述均衡信号组包括至少一个判决值，所述至少一个判决值的发生时刻早于所述输入信号的发生时刻。
  27. 一种信号判决均衡方法，其特征在于，包括：
    获取输入信号所述输入信号为脉冲幅度调制PAM信号或者为所述PAM信号在经过预均衡后输出的预均衡信号；
    确定所述输入信号的判决电路；
    获取所述判决电路的第一组判决阈值和第一组均衡期望值，所述第一组判决阈值的分布为不对称分布，所述第一组均衡期望值的分布为不对称分布；
    根据所述第一组均衡期望值、所述第一组判决阈值和所述输入信号确定所述输入信号的判决值。
  28. 根据权利要求27所述的方法，其特征在于，
    所述第一组判决阈值中的判决阈值数量等于所述PAM信号的电平数减一；
    所述第一组均衡期望值中的均衡期望值数量等于所述PAM信号的电平数。
  29. 根据权利要求27或28中任一项所述的方法，其特征在于，所述第一组均衡期望值是根据前一时刻的输入信号和所述前一时刻的输入信号判决输出的判决值更新前一时刻的 均衡期望值得到，所述前一时刻早于所述输入信号的发生时刻，所述第一组判决阈值是根据所述第一组均衡期望值更新得到；
    或者，
    所述第一组均衡期望值是根据前N个时刻的输入信号和所述前N个时刻的输入信号判决输出的判决值更新前N个时刻的均衡期望值得到，所述前N个时刻早于所述输入信号的发生时刻，所述第一组判决阈值是根据所述第一组均衡期望值更新得到。
  30. 根据权利要求27至29中任一项所述的方法，其特征在于，所述判决电路包含于判决电路集合，所述判决电路集合中的各路判决电路的判决阈值不相同，所述判决电路集合中的各路判决电路的均衡期望值不相同。
  31. 根据权利要求27至30中作一项所述的方法，其特征在于，所述确定所述输入信号的判决电路包括：
    根据判决值集合确定所述输入信号的判决电路，所述均衡信号组包括至少一个判决值，所述至少一个判决值的发生时刻早于所述输入信号的发生时刻。
  32. 一种判决均衡装置，其特征在于，包括：
    获取模块，用于获取输入信号所述输入信号为脉冲幅度调制PAM信号或者为所述PAM信号在经过预均衡后输出的预均衡信号；
    处理模块，用于确定所述输入信号的判决电路；
    所述获取模块，还用于获取所述判决电路的第一组判决阈值和第一组均衡期望值，所述第一组判决阈值的分布为不对称分布，所述第一组均衡期望值的分布为不对称分布，
    所述处理模块，还用于根据所述第一组均衡期望值、所述第一组判决阈值和所述输入信号确定所述输入信号的判决值。
  33. 根据权利要求32所述的装置，其特征在于，
    所述第一组判决阈值中的判决阈值数量等于所述PAM信号的电平数减一；
    所述第一组均衡期望值中的均衡期望值数量等于所述PAM信号的电平数。
  34. 根据权利要求32或33中任一项所述的装置，其特征在于，所述第一组均衡期望值是根据前一时刻的输入信号和所述前一时刻的输入信号判决输出的判决值更新前一时刻的均衡期望值得到，所述前一时刻早于所述输入信号的发生时刻，所述第一组判决阈值是根据所述第一组均衡期望值更新得到；
    或者，
    所述第一组均衡期望值是根据前N个时刻的输入信号和所述前N个时刻的输入信号判决输出的判决值更新前N个时刻的均衡期望值得到，所述前N个时刻早于所述输入信号的发生时刻，所述第一组判决阈值是根据所述第一组均衡期望值更新得到。
  35. 根据权利要求32至34中任一项所述的装置，其特征在于，所述判决电路包含于判决电路集合，所述判决电路集合中的各路判决电路的判决阈值不相同，所述判决电路集合中的各路判决电路的均衡期望值不相同。
  36. 根据权利要求32至35中任一项所述的装置，其特征在于，所述处理模块，具体用于根据判决值集合确定所述输入信号的判决电路，所述均衡信号组包括至少一个判决值，所述至少一个判决值的发生时刻早于所述输入信号的发生时刻。
  37. 一种计算机程序，其特征在于，当所述计算机程序在计算机上运行时，使得计算机执行如权利要求1至13或权利要求27至31中任意一项所述的方法。
  38. 一种计算机可读存储介质，其特征在于，包括程序，当所述程序在计算机上运行时，使得计算机执行如权利要求1至13或权利要求27至31中任一项所述的方法。
  39. 一种判决均衡装置，其特征在于，包括处理器和存储器，所述处理器与所述存储器耦合，
    所述存储器，用于存储程序；
    所述处理器，用于执行所述存储器中的程序，使得所述通信装置执行如权利要求1至13或权利要求27至31中任一项所述的方法。
  40. 一种芯片系统，其特征在于，所述芯片系统包括一个或多个处理器和存储器，所述存储器中存储有程序指令，当所述程序指令在所述一个或多个处理器中执行时，使得如权利要求1至13或权利要求27至31中任一项所述的方法被执行。
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