WO2023273542A1

WO2023273542A1 - Memory array, preparation method for memory array, phase change memory, and memory chip

Info

Publication number: WO2023273542A1
Application number: PCT/CN2022/088283
Authority: WO
Inventors: 蓝天; 马平
Original assignee: 华为技术有限公司
Priority date: 2021-06-29
Filing date: 2022-04-21
Publication date: 2023-01-05
Also published as: CN115548049A

Abstract

The present application is applicable to the technical field of semiconductors, and provides a memory array, a preparation method for the memory array, a phase change memory, and a memory chip. The memory array comprises a substrate material, and a plurality of phase change memory cells arranged on the substrate material; each of the plurality of phase change memory cells comprises a phase change material; in the plurality of phase change memory cells, the heights of the phase change materials of any two adjacent phase change memory cells are different, and the height of the phase change material refers to the distance between the phase change material and the substrate material. By adjusting the heights of the phase change materials in the phase change memory cells, the phase change materials of any two adjacent phase change memory cells are located at different heights, so that the distance between adjacent phase change materials can be increased, thereby significantly reducing the thermal crosstalk between two adjacent phase change materials, and improving the anti-interference capability of the phase change memory cells.

Description

Storage array, preparation method of storage array, phase-change memory and storage chip

This application claims the priority of the Chinese patent application submitted to the State Intellectual Property Office on June 29, 2021, with the application number 202110730114.1, and the title of the application is "storage array, preparation method of storage array, phase change memory and memory chip". The entire contents are incorporated by reference in this application.

technical field

The present application relates to the technical field of semiconductors, and in particular to a memory array, a method for preparing the memory array, a phase change memory, and a memory chip.

Background technique

Phase change memory (phase change memory, PCM) is a storage medium that uses the difference in conductivity of chalcogenide compounds when they transform between crystalline and amorphous states to store data. The advantage of fast read and write takes into account the non-volatile characteristics of the storage.

Referring to FIG. 1, FIG. 1 is a schematic cross-sectional view of a storage array in a PCM. The storage array of a PCM may include: a substrate 100, an insulating layer 101, a bottom electrode 102, a buffer material 103, a gate material 104, a phase change material 105, a top The arrangement of each layer of the electrodes 106 and the heat insulating material 107 is shown in FIG. 1 . During the working process of the PCM, voltage or current can be applied to the phase change material 105 to generate Joule heat, so that the phase change material 105 undergoes a phase change to realize data storage.

However, the Joule heat generated by the PCM during the working process is centered on the hot spot and spreads outward through a circle or an ellipse, causing thermal crosstalk between adjacent phase change materials 105 .

Contents of the invention

The present application provides a memory array, a preparation method of the memory array, a phase change memory and a memory chip, which solves the problem in the prior art that Joule heat generated by PCM during operation causes thermal crosstalk between adjacent phase change materials.

In order to achieve the above object, the application adopts the following technical solutions:

In a first aspect, a storage array is provided, and the storage array includes:

a substrate material, and a plurality of phase-change memory cells arranged on the substrate material, each of the phase-change memory cells in the plurality of phase-change memory cells includes a phase-change material;

Among the plurality of phase-change memory cells, the heights of the phase-change materials of any two adjacent phase-change memory cells are different, and the height of the phase-change material refers to the distance between the phase-change material and the substrate material .

By adjusting the height of the phase-change material in the phase-change memory unit, the phase-change materials of any two adjacent phase-change memory units are located at different heights, thereby increasing the distance between adjacent phase-change materials, and then The thermal crosstalk phenomenon between two adjacent phase-change materials can be significantly reduced, and the anti-interference ability of each phase-change memory unit can be improved.

In a first possible implementation manner of the first aspect, the any two adjacent phase-change memory cells include a first phase-change memory cell and a second phase-change memory cell;

Both the first phase-change memory unit and the second phase-change memory unit include: a bottom electrode, the phase-change material, and a top electrode sequentially arranged on the substrate material, and the second phase-change memory unit It also includes: a height adjustment material, the height adjustment material is located between the bottom electrode and the phase change material, and the height adjustment material includes at least one of a heating electrode, a gate material and a buffer material.

By setting the height adjustment material in the second phase change memory unit, the distance between the phase change material and the substrate material in the second phase change memory unit is greater than the distance between the phase change material and the substrate material in the first phase change memory unit The distance between them can increase the distance between adjacent phase change materials, thereby significantly reducing the thermal crosstalk between two adjacent phase change materials and improving the anti-interference ability of each phase change memory unit.

Based on the first possible implementation of the first aspect, in a second possible implementation of the first aspect, a Gating material.

By setting the gating material in the first phase-change memory unit, it is possible to control whether the gating material is gating, thereby controlling the first phase-change memory unit where the gating material is located to realize data reading and writing when the gating material is gating , the flexibility and reliability of reading and writing data of the first phase-change memory unit can be improved.

Based on the first or second possible implementation of the first aspect, in the third possible implementation of the first aspect, any adjacent two layers of materials in the first phase-change memory unit are arranged between With cushioning material.

By setting the buffer material in the first phase-change memory unit, the adhesion between the phase-change material and other materials can be enhanced, and the electrical matching between the phase-change material and other materials can be improved to form a good ohmic contact and improve Reliability of the first phase change memory cell.

Based on any one of the first to third possible implementations of the first aspect, in a fourth possible implementation of the first aspect, the height adjustment material is located between the bottom electrode and the phase Between variable materials, specifically including:

The heating electrode is located between the bottom electrode of the second phase change memory unit and the gate material, and the gate material is located between the heating electrode and the phase change memory unit of the second phase change memory unit. between changing materials;

The buffer material is disposed between the heating electrode and the gate material, and the buffer material is disposed between the gate material and the phase change material of the second phase change memory unit.

The height of the phase change material in the second phase change memory unit can be adjusted by arranging height adjustment materials including heating electrodes, gating materials and buffer materials in the second phase change memory unit, or by controlling the gating material, Controlling the data reading and writing of the second phase-change memory unit can also enhance the adhesion between the phase-change material and other materials, and at the same time improve the electrical matching between the phase-change material and other materials, and improve the performance of the second phase-change memory unit. reliability.

Based on any one of the first to fourth possible implementations of the first aspect, in the fifth possible implementation of the first aspect, the phase-change material of the second phase-change memory unit The buffer material is disposed between the top electrode and the second phase change memory unit.

Based on any possible implementation of the first aspect, in a sixth possible implementation of the first aspect, the storage array further includes: a heat insulating material, the side of each phase change storage unit covers There is said insulation material.

By covering the side of each phase change memory unit with heat insulating material, the thermal diffusion of the phase change material in each phase change memory unit can be further slowed down, the thermal crosstalk between two adjacent phase change materials can be reduced, and the performance of each phase change can be improved. The anti-interference ability of the storage unit.

Based on any one of the first to sixth possible implementations of the first aspect, in the seventh possible implementation of the first aspect, any two adjacent phase-change memory cells include the first a phase change memory unit and a second phase change memory unit;

The first phase-change memory cells and the second phase-change memory cells are arranged alternately in a first direction and a second direction, respectively, and the first direction intersects the second direction;

The bottom electrodes of the first phase-change memory cells adjacent in the first direction are connected to the bottom electrodes of the second phase-change memory cells, and the first phase-change memory cells adjacent in the second direction The top electrode of the phase change memory unit is connected to the top electrode of the second phase change memory unit, and the first direction is perpendicular to the second direction.

By arranging the first phase-change memory unit and the second phase-change memory unit to be arranged alternately along two different directions, the phase-change material of each phase-change memory unit is located at the same position as the phase-change material of the adjacent phase-change memory unit Different heights, so as to slow down the thermal diffusion of the phase change material in each phase change memory unit, reduce the thermal crosstalk phenomenon between two adjacent phase change materials, and improve the anti-interference ability of each phase change memory unit.

Moreover, by connecting the bottom electrodes or top electrodes of some phase-change memory cells, the process steps of forming the memory array can be reduced, and the efficiency of forming the memory array can be improved.

In a second aspect, a method for preparing a memory array is provided, the method comprising:

forming an insulating material on the substrate material, and forming a bottom electrode on the insulating material;

Depositing metal on the bottom electrode, and sequentially using photolithography and etching to form a heating electrode;

performing multi-layer film deposition, including from bottom to top: buffer material, gate material, the buffer material, phase change material and the buffer material;

The processes of photolithography and etching are sequentially adopted for each layer of material deposited by the multilayer film, and a top electrode is formed on the upper surface of the buffer material above the phase change material to form a plurality of phase change memory cells, wherein the multiple In a phase-change memory unit, the heights of the phase-change material layers of any two adjacent phase-change memory units are different, and the height of the phase-change material layer refers to the distance between the phase-change material layer and the substrate material .

In a first possible implementation manner of the second aspect, before generating a top electrode on the upper surface of the buffer material above the phase change material, the method further includes:

Wrapping a heat insulating material around each phase change memory unit not including the top electrode;

After the top electrode is generated on the upper surface of the buffer material above the phase change material, the method further includes:

The insulating material is filled between each phase change memory unit.

Based on the first possible implementation of the second aspect, in the second possible implementation of the second aspect, the area of the cross-sectional shape of the heating electrode is larger than the The area of the cross-sectional shape of the cross-section of the phase change material.

In a third aspect, a phase-change memory is provided, and the phase-change memory includes: a control circuit and at least one memory array as described in any one of the first aspects;

The control circuit is connected to the storage array, and the control circuit is used to perform read and write operations on the storage array according to the received read and write instructions.

In a first possible implementation manner of the third aspect, at least one of the storage arrays includes: a first storage array and a second storage array, and the first storage array and the second storage array are vertically stacked;

The bottom electrode connected to the first storage array is in the direction of the projection of the substrate material, and the top electrode connected to the first storage array is respectively connected to the direction of the projection of the substrate material, And the connected bottom electrodes in the second storage array are perpendicular to the direction in which the projection of the substrate material is located.

Based on the first possible implementation manner of the third aspect, in a second possible implementation manner of the third aspect, the top electrode of the first storage array is the bottom electrode of the second storage array.

In a fourth aspect, there is provided a memory chip, the memory chip comprising: a controller and the phase-change memory as described in any one of the third aspects;

The controller is connected to the phase change memory, and the controller is used to send a read and write instruction to the phase change memory, and the read and write instruction is used to instruct the phase change memory to perform a read and write operation.

It can be understood that, for the beneficial effects of the above-mentioned second aspect to the fourth aspect, reference can be made to the relevant description in the above-mentioned first aspect, and details are not repeated here.

Description of drawings

FIG. 1 is a schematic cross-sectional view of a storage array provided in the prior art;

FIG. 2 is a frame structure diagram of a memory chip involved in a memory array provided by an embodiment of the present application;

FIG. 3 is a schematic cross-sectional view of a storage array provided by an embodiment of the present application;

FIG. 4A is a schematic cross-sectional view of another storage array provided by an embodiment of the present application;

FIG. 4B is a schematic cross-sectional view of another storage array provided by the embodiment of the present application;

FIG. 4C is a schematic cross-sectional view of another storage array provided by the embodiment of the present application;

FIG. 5 is a three-dimensional diagram of a storage array provided by an embodiment of the present application;

Fig. 6 is a top view of materials other than the top electrode in a phase-change memory cell provided by an embodiment of the present application;

FIG. 7 is a schematic cross-sectional view of another storage array provided by an embodiment of the present application;

FIG. 8A is a schematic cross-sectional view of another storage array provided by the embodiment of the present application;

FIG. 8B is a schematic cross-sectional view of another storage array provided by the embodiment of the present application;

FIG. 8C is a schematic cross-sectional view of another storage array provided by the embodiment of the present application;

FIG. 8D is a schematic cross-sectional view of another storage array provided by the embodiment of the present application;

FIG. 8E is a schematic cross-sectional view of another storage array provided by the embodiment of the present application;

FIG. 8F is a schematic cross-sectional view of another storage array provided by the embodiment of the present application;

FIG. 8G is a schematic cross-sectional view of another storage array provided by the embodiment of the present application;

FIG. 9 is a schematic cross-sectional view of another storage array provided by an embodiment of the present application;

FIG. 10A is a schematic cross-sectional view of another storage array provided by the embodiment of the present application;

FIG. 10B is a schematic cross-sectional view of another storage array provided by the embodiment of the present application;

FIG. 10C is a schematic cross-sectional view of another storage array provided by the embodiment of the present application;

FIG. 10D is a schematic cross-sectional view of another storage array provided by the embodiment of the present application;

FIG. 10E is a schematic cross-sectional view of another storage array provided by the embodiment of the present application;

FIG. 10F is a schematic cross-sectional view of another storage array provided by the embodiment of the present application;

FIG. 10G is a schematic cross-sectional view of another storage array provided by the embodiment of the present application;

FIG. 11 is a schematic cross-sectional view of another storage array provided by the embodiment of the present application;

FIG. 12 is a schematic cross-sectional view of another storage array provided by the embodiment of the present application;

FIG. 13 is a top view of a storage array provided by an embodiment of the present application;

FIG. 14 is a schematic structural diagram of a multi-layer storage array provided by an embodiment of the present application;

FIG. 15 is a schematic diagram of a process flow for preparing a memory array provided in an embodiment of the present application;

FIG. 16A is a schematic cross-sectional view of a memory array in the process of preparing the memory array provided by the embodiment of the present application;

FIG. 16B is a top view of a storage array in the process of manufacturing the storage array provided by the embodiment of the present application;

FIG. 17A is a schematic cross-sectional view of another memory array in the process of preparing the memory array provided by the embodiment of the present application;

FIG. 17B is another top view of a storage array in the process of manufacturing the storage array provided by the embodiment of the present application;

FIG. 18A is another schematic cross-sectional view of a memory array in the process of preparing the memory array provided by the embodiment of the present application;

FIG. 18B is another top view of the memory array in the process of preparing the memory array provided by the embodiment of the present application;

FIG. 19A is another schematic cross-sectional view of a memory array in the process of preparing the memory array provided by the embodiment of the present application;

FIG. 19B is another top view of the memory array in the process of preparing the memory array provided by the embodiment of the present application;

FIG. 20A is a schematic cross-sectional view of another storage array in the process of preparing the storage array provided by the embodiment of the present application;

FIG. 20B is another top view of a memory array in the process of manufacturing the memory array according to an embodiment of the present application.

detailed description

In the following description, specific details such as specific system structures and technologies are presented for the purpose of illustration rather than limitation, so as to thoroughly understand the embodiments of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced in other embodiments without these specific details. In other instances, detailed descriptions of well-known methods of fabricating memory arrays, phase change memories, and memory chips are omitted so as not to obscure the description of the present application with unnecessary detail.

The terms used in the following examples are for the purpose of describing particular examples only, and are not intended to limit the application. As used in the specification and appended claims of this application, the singular expressions "a", "the", "above" and "the" are intended to also include such terms as "one or more". expressions, unless the context clearly indicates otherwise.

The memory chips involved in a memory array provided in the embodiments of the present application are introduced as follows. Referring to FIG. 2 , FIG. 2 is a frame structure diagram of a memory chip. The memory chip may include: a controller 210 and a PCM 220 . The PCM 220 includes: a control circuit 2201 and a storage array 2202 .

Among them, the controller 210 can send read and write instructions to the PCM220, and the control circuit 2201 of the PCM 220 can perform corresponding read and write operations on the storage array 2202 according to the received read and write instructions, so as to realize operations such as storing, deleting and overwriting data. . Moreover, the control circuit 2201 can be a complementary metal oxide semiconductor memory (complementary metal oxide semiconductor, CMOS) circuit, and can also be a circuit composed of other components with control functions, such as a control circuit composed of diodes. The control circuit 2201 is not limited.

During the working process of the memory chip, the phase-change material based on the memory array 2202 can be switched between crystalline and amorphous states, and the phase-change materials in the crystalline state and the amorphous state correspond to different resistances respectively, then the memory array 2202 According to the switching between different states of the phase change material, the data writing and erasing operations can be completed, thereby realizing the storage of data by the memory chip.

Specifically, if the phase-change material of the storage array 2202 is in a crystalline state, the control circuit 2201 of the PCM 220 can heat the phase-change material of the storage array 2202 according to the received read and write instructions, so that the temperature of the phase-change material is higher than that of recrystallization temperature, but below the melting point. Afterwards, the phase change material is slowly cooled, so that the crystal grains of the phase change material form a whole layer, and an amorphous (high resistance state) phase change material is obtained, and the erasing operation is completed.

If the phase change material of the storage array 2202 is in an amorphous state, the control circuit 2201 of the PCM220 can heat the phase change material of the storage array 2202 according to the received read and write instructions, so that the temperature of the phase change material is slightly higher than the melting point. Afterwards, the phase change material is suddenly quenched to cool the phase change material, thereby obtaining a crystalline (low resistance state) phase change material, and completing the writing operation.

It should be noted that, in practical applications, the PCM 220 of the memory chip may include a plurality of memory arrays 2202, and each memory array 2202 may be vertically stacked. For illustration, the embodiment of the present application does not limit the number of storage arrays 2202 .

The memory array 2202 in the PCM220 is introduced below, and the controller 210 of the memory chip and the control circuit 2201 in the PCM220 can refer to the prior art, and the embodiments of the present application will not repeat the description of the controller 210 and the control circuit 2201 .

Referring to FIG. 3 , FIG. 3 is a schematic cross-sectional view of a memory array provided by an embodiment of the present application. The memory array may include: a substrate material 310 , an insulating material 320 and a plurality of phase-change memory cells 330 from bottom to top.

Wherein, the plurality of phase-change memory cells 330 may include: a plurality of first phase-change memory cells 330A and a plurality of second phase-change memory cells 330B. Each first phase-change memory cell 330A may include: a bottom electrode 3301, a phase-change material 3302, and a top electrode 3303 arranged longitudinally in sequence, and each second phase-change memory cell 330B may include: a bottom electrode 3301 arranged longitudinally in sequence , the height adjustment material 3304, the phase change material 3302 and the top electrode 3303, the height adjustment material 3304 is added between the phase change material 3302 and the bottom electrode 3301, then the phase change material 3302 and the substrate material 310 of the second phase change memory unit 330B The distance between the phase change material 3302 of the first phase change memory unit 330A and the substrate material 310 is greater than the distance between the phase change material 3302 of the first phase change memory unit 330A and the phase change material 3302 of the second phase change memory unit 330B. Variable material 3302 is located at different heights.

Wherein, the phase change material 3302 can be made of germanium-antimony-tellurium (Ge-Sb-Te) material, or can be made of Ge-Sb-Te and carbon (C), nitrogen (N), oxygen (O), silicon (Si ) or copper (Cu) doping compounds, can also be generated from germanium antimonide (GeSb), germanium telluride (GeTe), gallium antimonide (GaSb) or antimony telluride (SbTe) materials, can also be generated by GeSb , GeTe, GaSb or SbTe respectively with titanium (Ti), tantalum (Ta), chromium (Cr), yttrium (Y), tin (Sn), zinc (Zn), zirconium (Zr), scandium (Sc) or Cu The dopant compound is generated, and the embodiment of the present application does not limit the material used to generate the phase change material 3302 .

Further, the height adjustment material 3304 may include: at least one of a heating electrode 33041 , a gate material 33042 and a buffer material 33043 . Wherein, the heating electrode 33041, the gate material 33042 and the buffer material 33043 are arranged vertically.

For example, referring to Fig. 4A, Fig. 4B and Fig. 4C, respectively show the cross-sectional view of the memory array when the height adjustment material 3304 comprises different materials, the height adjustment material 3304 in Fig. 4A only includes the heating electrode 33041, the height in Fig. 4B The adjustment material 3304 includes only the gating material 33042 , and the height adjustment material 3304 in FIG. 4C includes only the cushioning material 33043 .

In addition, the gate material 33042 can be made of selenium arsenic germanium silicide (SeAsGeSi), germanium sulfide (GeS), arsenic tellurium germanium silicon nitride (AsTeGeSiN), germanium selenium antimony nitride (GeSeSbN), tellurium arsenic germanium silicon selenide (TeAsGeSiSe) , arsenic germanium selenide (AsGeSe), germanium selenide (GeSe), GeTe, doped boron carbide (BC-doped), boron-tellurium (B-Te), carbon-tellurium (C-Te), silicon-tellurium (Si—Te) or aluminum-tellurium (Al—Te) material is generated, and the embodiment of the present application does not limit the material for generating the phase change material 3302 .

Moreover, the multiple first phase-change memory cells 330A and the multiple second phase-change memory cells 330B are arranged alternately in the first direction and the second direction respectively, so that the phases of any two adjacent phase-change memory cells 330 The change material 3302 is located at different heights, thereby reducing thermal crosstalk caused between adjacent phase change memory cells 330 .

Wherein, the first direction and the second direction are located on the same horizontal plane and intersect each other. For example, the first direction and the second direction are both on a horizontal plane and perpendicular to each other, and the embodiment of the present application does not specifically limit the angle between the first direction and the second direction.

Further, the bottom electrode 3301 of the first phase-change memory cell 330A adjacent in the first direction is connected to the bottom electrode 3301 of the second phase-change memory cell 330B, and the first phase-change memory cell adjacent in the second direction The top electrode 3303 of the cell 330A is in communication with the top electrode 3303 of the second phase change memory cell 330B.

For example, refer to FIG. 5, which is a three-dimensional diagram of a memory array provided by the embodiment of the present application, which is located in the same row, that is, the bottom electrodes 3301 of multiple adjacent phase-change memory cells 330 in the first direction connected; the top electrodes 3303 of a plurality of adjacent phase-change memory cells 330 located in the same column, that is, in the second direction, are connected. Moreover, the connected bottom electrode 3301 and the connected top electrode 3303 are perpendicular to each other on the horizontal plane. In addition, the first phase-change memory cells 330A and the second phase-change memory cells 330B are alternately arranged in the first direction and the second direction, respectively.

In addition, there are gaps between the multiple phase-change memory cells 330, and an insulating material 320 can be filled between each phase-change memory cell 330, and each phase-change memory cell 330 is isolated by the filled insulating material 320, so that the phase change can be slowed down. The effect of the heat dissipated by the material 3302 on the adjacent phase change material 3302 .

It should be noted that, in the embodiment of the present application, the storage array includes the insulating material 320 as an example for description, but in practical applications, the storage array may not include the insulating material 320, which is not limited in the embodiment of the present application.

Compared with the first phase change memory cell 330A, the second phase change memory cell 330B has a height adjustment material 3304 added between the bottom electrode 3301 and the phase change material 3302, so that the phase change material 3302 of the second phase change memory cell 330B As the distance from the substrate material 310 increases, the phase change material 3302 of the second phase change memory unit 330B and the phase change material 3302 of the first phase change memory unit 330A are located at different heights, and the phase change material 3302 dissipates heat in the horizontal direction , the influence of the phase change material 3302 on thermal crosstalk between adjacent phase change materials 3302 located at different heights can be mitigated.

It should be noted that the height adjustment material 3304 may only include the heating electrode 33041 , the gate material 33042 or the buffer material 33043 . The heater electrode 33041 will be described below when the height adjustment material 3304 includes only the heater electrode 33041 .

Both the cross-sectional shape of the heating electrode 33041 and the cross-sectional shape of the phase-change material 3302 can be regular figures, and the cross-sectional area of the heating electrode 33041 is larger than the cross-sectional area of the phase-change material 3302, that is, Yes, the projected area of the heating electrode 33041 on the substrate material 310 is larger than the projected area of the phase change material 3302 on the substrate material 310 . Moreover, the projection of the phase change material 3302 on the substrate material 310 is located within the projection of the heating electrode 33041 on the substrate material 310 .

Wherein, the distance between the center of the projection of the phase change material 3302 on the substrate material 310 and the center of the projection of the heating electrode 33041 on the substrate material 310 is not greater than the size indicated by the alignment accuracy of the photolithography machine. The ratio between the cross-sectional area of the heating electrode 33041 and the cross-sectional area of the phase change material 3302 is related to the alignment accuracy of the photolithography machine. The higher the alignment accuracy of the lithography machine, the closer the cross-sectional area of the heating electrode 33041 is to the cross-sectional area of the phase-change material 3302; The larger the difference in area. By adjusting the ratio between the cross-sectional area of the heating electrode 33041 and the cross-sectional area of the phase-change material 3302 according to the alignment accuracy of the photolithography machine, the phase-change material 3302 can be controlled to be completely in contact with the heating electrode 33041 without contact with the heating electrode 33041. The bottom electrode 3301 or the insulating material 320 under the electrode 33041 is in contact, so that the difference in height of the phase change material 3302 of the same phase change memory unit 330 can be avoided.

For example, referring to FIG. 6, FIG. 6 shows a top view of materials other than the top electrode 3303 in the phase-change memory cell 330, and the first phase-change memory cell 330A and the second phase-change memory cell 330B alternate along the horizontal and vertical directions, respectively. arranged. The phase change material 3302 of the second phase change memory unit 330B covers the upper surface of the heating electrode 33041 . It can be seen from FIG. 6 that the center of the projection of the second phase-change storage unit 330B on the substrate material 310 coincides with the center of the projection of the heating electrode 3304 on the substrate material 310, and the projection of the phase-change material 3302 on the substrate material 310 The distance between the edge and the edge of the projection of the heating electrode 33041 on the substrate material 310 is equal to half of the dimension indicated by the alignment accuracy.

When the height adjustment material 3304 includes the gating material 33042 and/or the buffer material 33043 , the projection of the gating material 33042 or the buffer material 33043 on the substrate material 310 coincides with the projection of the phase change material 3302 on the substrate material 310 . That is, the projected area of the gate material 33042 or the buffer material 33043 on the substrate material 310 is consistent with the projected area of the phase change material 3302 on the substrate material 310, and the gate material 33042 or the buffer material 33043 is on the substrate The center of the projection of the material 310 coincides with the center of the projection of the phase change material 3302 on the substrate material 310 .

It should be noted that, in practical applications, in the process of forming and etching the gate material 33042 and/or the buffer material 33043, due to the influence of process precision, etc., the gate material 33042 or the buffer material 33043 on the substrate material 310 The area and center of the projection may have certain errors from the area and center of the projection of the phase change material 3302 on the substrate material 310 .

In addition, the gating material 33042 and/or the buffer material 33043 included in the height adjustment material 3304 can also be set in the first phase-change memory unit 330A, so that the first phase-change memory unit 330A is added with the gating material 33042 and/or Or after the buffer material 33043, the reliability of the first phase change memory unit 330A is improved. However, the distance between the phase change material 3302 and the substrate material 310 in the second phase change memory unit 330B is greater than the distance between the phase change material 3302 and the substrate material 310 in the first phase change memory unit 330A.

In an optional embodiment, referring to FIG. 7 , the first phase-change memory unit 330A may further include: a gate material 33042 located between the bottom electrode 3301 and the phase-change material 3302 .

Corresponding to the first phase change memory unit 330A, when the first phase change memory unit 330A includes the gate material 33042, the height adjustment material 3304 in the second phase change memory unit 330B can still include: heating electrode 33041, gate At least one of material 33042 and cushioning material 33043. For example, referring to FIG. 7 , in which the height adjustment material 3304 includes a heating electrode 33041 and a gating material 33042 as an example, a first phase change memory unit 330A and a second phase change memory unit 330B are shown.

The gating material 33042 can control the gate of the phase change memory unit 330 where the gating material 33042 is located under a certain current or voltage. or current to realize reading and writing of data and improve the reliability of the phase change memory unit 330 .

For the phase-change memory unit 330 that does not include the gating material 33042 , the phase-change memory unit 330 can be controlled to be turned on or off through a switching device connected to the phase-change memory unit 330 . For example, the switching device may be a component with a switching function such as a transistor, and the embodiment of the present application does not limit the switching device.

It should be noted that, the above is only an example where the first phase change memory unit 330A includes the gating material 33042 , and the height adjustment material 3304 in the second phase change memory unit 330B includes the heater electrode 33041 and the gating material 33042 . But in actual application, referring to Fig. 8A to Fig. 8G, it is shown that the height adjustment material 3304 includes: heating electrode 33041, gating material 33042, buffer material 33043, heating electrode 33041 and buffer material 33043, gating material 33042 and buffer Material 33043, and materials such as heating electrode 33041, gate material 33042, and buffer material 33043 are schematic cross-sectional diagrams corresponding to the storage array.

In another optional embodiment, referring to FIG. 9, the first phase-change memory unit 330A may further include: a buffer material 33043 in addition to the gate material 33042, and the buffer material 33043 may be arranged in the first phase-change Multiple locations for storage unit 330A. The buffer material 33043 can be used to enhance the adhesion between the phase change material 3302 and other materials, and at the same time can improve the electrical matching between the phase change material 3302 and other materials, form a good ohmic contact, and improve the stability of the phase change memory unit 330. reliability.

Wherein, a buffer material 33043 is provided between any adjacent two layers of materials in the first phase-change memory unit 330A. Referring to FIG. Material 33043, a buffer material 33043 is provided between the gate material 33042 and the phase change material 3302 of the first phase change memory unit 330A, and a buffer is provided between the phase change material 3302 and the top electrode 3303 of the first phase change memory unit 330A Material 33043.

Corresponding to the first phase change memory unit 330A, referring to FIG. 9, the height adjustment material 3304 in the second phase change memory unit 330B also includes a buffer material 33043, and the heating electrode 33041 and the gate material of the second phase change memory unit 330B A buffer material 33043 is provided between 33042, and a buffer material 33043 is provided between the gate material 33042 of the second phase change memory unit 330B and the phase change material 3302, but the heating electrode 33041 of the second phase change memory unit 330B is in contact with the second phase No buffer material 33043 is provided between the bottom electrodes 3301 of the variable memory unit 330B.

Further, referring to FIG. 9 , similar to the first phase-change memory unit 330A, a buffer material 33043 may also be provided between the phase-change material 3302 and the top electrode 3303 of the second phase-change memory unit 330B. The position of 33043 in the phase change memory unit 330 is not limited.

Referring to FIG. 10A to FIG. 10F, it is shown that the height adjustment material 3304 of the second phase change memory unit 330B respectively includes: when any one or any two of the heating electrode 33041, the gate material 33042 and the buffer material 33043, the storage Corresponding cross-sectional view of the array. Referring to Figure 10A to Figure 10C, the height adjustment material 3304 only includes any one of the heating electrode 33041, the gate material 33042 and the buffer material 33043, referring to Figure 10D to Figure 10G, the height adjustment material 3304 only includes the heating electrode 33041, Any two of the gating material 33042 and the buffer material 33043.

In yet another optional embodiment, referring to FIG. 11 , the memory array may further include: a heat insulating material 340 wrapped around the side of each phase change memory unit 330 . On the basis of isolating each phase change memory unit 330 by insulating material 320 , thermal crosstalk between each phase change memory unit 330 is further reduced by heat insulating material 340 .

Wherein, the upper surface of the heat insulating material 340 is not lower than the lower surface of the top electrode 3303, the lower surface of the heat insulating material 340 is not higher than the lower surface of the phase change material 3302, and is not lower than the upper surface of the bottom electrode 3301, so that On the basis of no need for complex process flow, it can completely cover the side of the phase change material 3302 and reduce the thermal crosstalk between the phase change memory units 330 .

For example, referring to FIG. 12 , the upper surface of the insulating material 340 may be at the same height as the lower surface of the top electrode 3303 , and the lower surface of the insulating material 340 may be at the same height as the lower surface of the phase change material 3302 .

It should be noted that a plurality of phase-change memory cells 330 of the memory array may be arranged at equal intervals on the upper surface of the insulating material 320 , and at least three phase-change memory cells 330 are arranged around each phase-change memory cell 330 . For example, referring to FIG. 13, FIG. 13 is a top view of a memory array, including a plurality of phase-change memory cells 330, as shown in FIG. 13, the white circle in the figure represents the first phase-change memory cell 330A, and the black circle Denotes the second phase change memory cell 330B. Among them, there are 4 first phase-

change memory cells

330A and 4 second phase-change memory cells 330B around the phase-change memory cell A, and there are 3 first phase-

change memory cells

330A and 2 second phase-change memory cells 330B around the phase-change memory cell B. There are two first phase-change memory cells 330A and one second phase-change memory cell 330B around the phase-change memory cell 330B and the phase-change memory cell C.

In addition, the cross-sectional shape of the phase-change memory cell 330 can be a regular figure, for example, the cross-sectional shape shown in FIG. Rectangular or other regular shapes, which are not limited in this embodiment of the present application.

In addition, the smaller the distance between any two adjacent phase-change memory cells 330 is, the better, and the distance between any two adjacent phase-change memory cells 330 is related to the minimum lithography dimension of a photolithography machine. If the minimum scale of the lithography machine is smaller, the distance between any two adjacent phase-change memory cells 330 is also smaller.

For example, if the cross-sectional shape of the phase-change memory cell 330 is a circle, the distance between any two adjacent phase-change memory cells 330 can be a circle diameter; if the cross-sectional shape of the phase-change memory cell 330 is a square, then The distance between any two adjacent phase-change memory cells 330 may be the side length of a square.

It should be noted that a plurality of other phase-change memory cells 330 are arranged around each phase-change memory cell 330 among the above-mentioned multiple phase-change memory cells 330 . However, the distance between each phase-change memory cell 330 and other surrounding phase-change memory cells 330 is different, and the distance between each phase-change memory cell 330 and some phase-change memory cells 330 is short, and the distance between each phase-change memory cell 330 and some phase-change memory cells 330 is short. The distance between 330 is far.

Correspondingly, for each phase-change memory cell 330, the distance between the phase-change memory cell 330 and the adjacent phase-change memory cell 330 is the distance between the phase-change memory cell 330 and other surrounding phase-change memory cells 330 The minimum distance among the various distances between each phase-change memory cell 330 , that is, the phase-change memory cell 330 adjacent to each phase-change memory cell 330 is the phase-change memory cell with the shortest distance to the phase-change memory cell 330 .

For example, referring to FIG. 13, the phase-change memory unit adjacent to phase-change memory unit A is the first phase-change memory unit 330A located in the four directions of phase-change memory unit A, up, down, left, and right, and the phase-change memory unit adjacent to phase-change memory unit B is The unit is the second phase-change memory unit 330B located in three directions above, left and right of the phase-change memory unit B, and the phase-change memory unit adjacent to the phase-change memory unit C is located below and on the left side of the phase-change memory unit C 2 directions of the first phase change memory cell 330A.

The above describes one layer of storage array 2202 in PCM 220 , but in practical application, PCM 220 may include multiple layers of storage array 2202 stacked and arranged.

Referring to FIG. 14 , FIG. 14 is a schematic structural diagram of a multi-layer storage array provided by an embodiment of the present application. The multi-layer storage array may include: a first storage array 1410 and a second storage array 1420 . The first storage array 1410 may include: a substrate material 14101 , an insulating material 14102 , a plurality of phase-change memory cells 14103 and a thermal insulation material 14104 , and the second storage array 1420 may include a plurality of phase-change memory cells 14201 and a thermal insulation material 14202 .

Wherein, the first memory array 1410 and the second memory array 1420 are vertically stacked and arranged, and the phase-change memory cells included in the first memory array 1410 and the second memory array 1420 are all the same as the phase-change memory cells shown in Fig. 3 to Fig. 13 similar and will not be repeated here.

The projection direction of each connected bottom electrode in the second storage array 1420 on the substrate material 14101 is perpendicular to the projection direction of each connected bottom electrode in the first storage array 1410 on the substrate material 14101 . That is, the direction in which the projections of the top electrodes connected to each other in the second storage array 1420 on the substrate material 14101 is located, and the direction in which the projections of the bottom electrodes connected with each other in the first storage array 1410 are located on the substrate material 14101 parallel to each other.

Further, in the process of forming the second memory array 1420 through the corresponding process flow, after the top electrode of the first memory array 1410 is formed, the second memory array parallel to the top electrode of the first memory array 1410 can be formed 1420; also can no longer generate the bottom electrode of the second memory array 1420, but the top electrode of the first memory array 1410 is used as the bottom electrode of the second memory array 1420, and the top electrode of the first memory array 1410 On the basis of , a plurality of phase-change memory cells 14201 and heat insulating materials 14202 of the second memory array 1420 are generated.

It should be noted that the embodiment of the present application only takes the PCM 220 including two-layer storage arrays 2202 as an example for illustration, but in practical applications, the PCM 220 may include multi-layer storage arrays, and this application does not limit the number of storage arrays.

Referring to FIG. 15, FIG. 15 is a schematic diagram of a process flow for preparing a storage array provided in the embodiment of the present application, which may include the following steps:

S1. Referring to FIG. 16A and FIG. 16B, a process of chemical vapor deposition (chemical vapor deposition, CVD), physical vapor deposition (physical vapor deposition, PVD) or atomic layer deposition (atomic layer deposition, ALD) is used on the substrate material 15010 The method forms an insulating material 15020, and forms the bottom electrode 150301 of the phase change memory unit on the insulating material 15020 by using a PVD or CVD process. Wherein, the bottom electrode is made of metal material.

S2. Referring to Fig. 17A and Fig. 17B, on the bottom electrode 150301, the material corresponding to the metal heating electrode 150304 is deposited on the bottom electrode 150301 by means of PVD or CVD, and then the heating element shown in Fig. 17A and Fig. 17B is formed by photolithography and etching in sequence. The graph corresponding to electrode 150304.

S3. Referring to FIG. 18A and FIG. 18B , PVD, CVD, and ALD processes are used to deposit multilayer films, including buffer material 150306, gate material 150305, buffer material 150306, phase change material 150302 and buffer material 150306 from bottom to top.

S4. Referring to FIG. 19A and FIG. 19B , sequentially adopt photolithography and etching processes to form phase-change memory cells 15030 each including materials other than the top electrode 150303 .

S5, referring to Fig. 20A and Fig. 20B, using ALD, CVD, chemical mechanical polishing (chemical mechanical polishing, CMP), PVD, photolithography and etching process methods, wrapping heat insulating material 1040 around each phase change memory unit 15030, A top electrode 150303 is formed on the upper surface of the buffer material 150306 above the phase change material 150302 to form a complete phase change memory unit 15030 , and finally the insulating material 15020 is filled between each phase change memory unit 15030 .

To sum up, in the memory array provided by the embodiment of the present application, by adjusting the height of the phase-change material in the phase-change memory unit, the phase-change materials of any two adjacent phase-change memory units are located at different heights, thereby The distance between adjacent phase-change materials can be increased, thereby significantly reducing thermal crosstalk between two adjacent phase-change materials, and improving the anti-interference ability of each phase-change memory unit.

Moreover, by adding a height-adjusting material in the second phase-change memory unit, the phase-change materials in any two adjacent phase-change memory units are located at different heights, thereby increasing the distance between the adjacent two phase-change materials. The distance can significantly reduce the thermal crosstalk phenomenon between two adjacent phase change materials, and improve the anti-interference ability of each phase change memory unit.

In addition, by increasing the distance between two adjacent phase-change materials, in the case of multiple reads and writes to a certain phase-change memory unit, the impact of the phase-change memory unit on other adjacent phase-change memory units can be reduced. , which can improve the reliability of the storage array.

Further, by vertically stacking the memory arrays, the bottom electrode of another memory array is regenerated above the top electrode of the lower memory array, or the top electrode of the lower memory array is used as the bottom electrode of another memory array , thereby generating multiple stacked memory arrays, which can increase the storage capacity of the PCM and memory chips.

Those skilled in the art can clearly understand that for the convenience and brevity of description, only the division of the above-mentioned functional units and modules is used for illustration. In practical applications, the above-mentioned functions can be assigned to different functional units, Completion of modules means that the internal structure of the device is divided into different functional units or modules to complete all or part of the functions described above. Each functional unit and module in the embodiment may be integrated into one processing unit, or each unit may exist separately physically, or two or more units may be integrated into one unit, and the above-mentioned integrated units may adopt hardware It can also be implemented in the form of software functional units. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing each other, and are not used to limit the protection scope of the present application. For the specific working process of the units and modules in the above system, reference may be made to the corresponding process in the foregoing method embodiments, and details will not be repeated here.

In the above-mentioned embodiments, the descriptions of each embodiment have their own emphases, and for parts that are not detailed or recorded in a certain embodiment, refer to the relevant descriptions of other embodiments.

Those of ordinary skill in the art can appreciate that the units and algorithm steps of the examples described in conjunction with the embodiments disclosed herein can be implemented by electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are executed by hardware or software depends on the specific application and design constraints of the technical solution. Skilled artisans may use different methods to implement the described functions for each specific application, but such implementation should not be regarded as exceeding the scope of the present application.

In the embodiments provided in this application, it should be understood that the disclosed devices and methods may be implemented in other ways. For example, the system embodiments described above are only illustrative. For example, the division of the modules or units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be Incorporation may either be integrated into another system, or some features may be omitted, or not implemented. In another point, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces, and the indirect coupling or communication connection of devices or units may be in electrical, mechanical or other forms.

The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or may be distributed to multiple network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, each unit may exist separately physically, or two or more units may be integrated into one unit. The above-mentioned integrated units can be implemented in the form of hardware or in the form of software functional units.

If the integrated unit is realized in the form of a software function unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, all or part of the procedures in the methods of the above embodiments in the present application can be completed by instructing related hardware through computer programs, and the computer programs can be stored in a computer-readable storage medium. The computer program When executed by a processor, the steps in the above-mentioned various method embodiments can be realized. Wherein, the computer program includes computer program code, and the computer program code may be in the form of source code, object code, executable file or some intermediate form. The computer-readable medium may at least include: any entity or device capable of carrying computer program codes to a PCM/storage chip, a recording medium, a computer memory, a read-only memory (ROM, Read-Only Memory), a random access memory ( RAM, Random Access Memory), electrical carrier signals, telecommunication signals, and software distribution media. Such as U disk, mobile hard disk, magnetic disk or optical disk, etc. In some jurisdictions, computer readable media may not be electrical carrier signals and telecommunication signals under legislation and patent practice.

Finally, it should be noted that: the above is only a specific implementation of the application, but the protection scope of the application is not limited thereto, and any changes or replacements within the technical scope disclosed in the application shall be covered by this application. within the scope of the application. Therefore, the protection scope of the present application should be determined by the protection scope of the claims.

Claims

A storage array, characterized in that the storage array includes:

a substrate material, and a plurality of phase-change memory cells arranged on the substrate material, each of the phase-change memory cells in the plurality of phase-change memory cells includes a phase-change material;

Among the plurality of phase-change memory cells, the heights of the phase-change materials of any two adjacent phase-change memory cells are different, and the height of the phase-change material refers to the distance between the phase-change material and the substrate material .
The memory array according to claim 1, wherein any two adjacent phase-change memory cells comprise a first phase-change memory cell and a second phase-change memory cell;

Both the first phase-change memory unit and the second phase-change memory unit include: a bottom electrode, the phase-change material, and a top electrode sequentially arranged on the substrate material, and the second phase-change memory unit It also includes: a height adjustment material, the height adjustment material is located between the bottom electrode and the phase change material, and the height adjustment material includes: at least one of a heating electrode, a gate material and a buffer material.
The memory array according to claim 2, wherein a gate material is disposed between the bottom electrode of the first phase-change memory cell and the phase-change material.
The memory array according to claim 2 or 3, wherein a buffer material is arranged between any adjacent two layers of materials in the first phase change memory unit.
The memory array according to any one of claims 2 to 4, wherein the height adjustment material is located between the bottom electrode and the phase change material, specifically comprising:

The heating electrode is located between the bottom electrode of the second phase change memory unit and the gate material, and the gate material is located between the heating electrode and the phase change memory unit of the second phase change memory unit. between changing materials;

The buffer material is disposed between the heating electrode and the gate material, and the buffer material is disposed between the gate material and the phase change material of the second phase change memory unit.
The memory array according to any one of claims 2 to 5, characterized in that, the phase-change material of the second phase-change memory unit and the top electrode of the second phase-change memory unit are provided with the cushioning material.
The storage array according to any one of claims 1 to 6, characterized in that the storage array further comprises: a thermal insulation material, and the side surfaces of each of the phase change memory cells are covered with the thermal insulation material.
The memory array according to any one of claims 2 to 7, wherein the any two adjacent phase-change memory cells comprise a first phase-change memory cell and a second phase-change memory cell;

The first phase-change memory cells and the second phase-change memory cells are arranged alternately in a first direction and a second direction, respectively, and the first direction intersects the second direction;

The bottom electrodes of the first phase-change memory cells adjacent in the first direction are connected to the bottom electrodes of the second phase-change memory cells, and the first phase-change memory cells adjacent in the second direction The top electrode of the phase change memory unit is connected to the top electrode of the second phase change memory unit, and the first direction is perpendicular to the second direction.
A method for preparing a storage array, characterized in that the method comprises:

forming an insulating material on the substrate material, and forming a bottom electrode on the insulating material;

Depositing metal on the bottom electrode, and sequentially using photolithography and etching to form a heating electrode;

performing multi-layer film deposition, including from bottom to top: buffer material, gate material, the buffer material, phase change material and the buffer material;

The processes of photolithography and etching are sequentially adopted for each layer of material deposited by the multilayer film, and a top electrode is formed on the upper surface of the buffer material above the phase change material to form a plurality of phase change memory cells, wherein the multiple In a phase-change memory unit, the heights of the phase-change material layers of any two adjacent phase-change memory units are different, and the height of the phase-change material layer refers to the distance between the phase-change material layer and the substrate material .
The method for manufacturing a memory array according to claim 9, wherein before the top electrode is formed on the upper surface of the buffer material above the phase change material, the method further comprises:

Wrapping a heat insulating material around each phase change memory unit not including the top electrode;

After the top electrode is generated on the upper surface of the buffer material above the phase change material, the method further includes:

The insulating material is filled between each phase change memory unit.
The method for manufacturing a memory array according to claim 10, wherein the area of the cross-sectional shape of the heating electrode is larger than the area of the cross-sectional shape of the phase-change material in the phase-change memory unit. area.
A phase-change memory, characterized in that the phase-change memory comprises: a control circuit and at least one memory array according to any one of claims 1 to 8;

The control circuit is connected to the storage array, and the control circuit is used to perform read and write operations on the storage array according to the received read and write instructions.
The phase change memory according to claim 12, wherein at least one of the storage arrays comprises: a first storage array and a second storage array, and the first storage array and the second storage array are vertically stacked and arranged ;

The bottom electrode connected to the first storage array is in the direction of the projection of the substrate material, and the top electrode connected to the first storage array is respectively connected to the direction of the projection of the substrate material, And the connected bottom electrodes in the second storage array are perpendicular to the direction in which the projection of the substrate material is located.
The phase change memory according to claim 13, wherein the top electrode of the first memory array is the bottom electrode of the second memory array.
A memory chip, characterized in that the memory chip comprises: a controller and the phase-change memory according to any one of claims 12 to 14;

The controller is connected to the phase change memory, and the controller is used to send a read and write instruction to the phase change memory, and the read and write instruction is used to instruct the phase change memory to perform a read and write operation.