CN112951990B

CN112951990B - Three-dimensional phase change memory and preparation method thereof

Info

Publication number: CN112951990B
Application number: CN202110198002.6A
Authority: CN
Inventors: 刘峻
Original assignee: Yangtze River Advanced Storage Industry Innovation Center Co Ltd
Current assignee: Yangtze River Advanced Storage Industry Innovation Center Co Ltd
Priority date: 2021-02-22
Filing date: 2021-02-22
Publication date: 2021-12-28
Anticipated expiration: 2041-02-22
Also published as: CN112951990A

Abstract

The embodiment of the invention discloses a three-dimensional phase change memory and a preparation method thereof, wherein the three-dimensional phase change memory comprises: a first conductive line extending in a first direction, a second conductive line extending in a second direction, and a phase change memory cell disposed between the first conductive line and the second conductive line in a third direction; the phase change memory unit comprises a first gating layer, a phase change memory layer and a second gating layer which are stacked along a third direction, wherein the first gating layer is located between the phase change memory layer and the first conductive line, the second gating layer is located between the phase change memory layer and the second conductive line, and the third direction is perpendicular to the first direction and the second direction; wherein the thickness D1 of the first conductive line, the thickness D2 of the second conductive line, the thickness D1 of the first gate layer, the thickness D2 of the second gate layer, the coefficient k1 of the thermal conductivity of the first gate layer and the coefficient k2 of the thermal conductivity of the second gate layer satisfy the following conditions:

wherein D1 is not equal to D2, and lambda is 0.7-1.3.

Description

Three-dimensional phase change memory and preparation method thereof

Technical Field

The invention relates to the technical field of memories, in particular to a three-dimensional phase change memory and a preparation method thereof.

Background

Memory (Memory) is a Memory device used in modern information technology to store information. With the increasing demands of various electronic devices for integration and data storage density, it is increasingly difficult for a common two-dimensional memory device to meet the demands, and in such a situation, a three-dimensional (3D) memory has come into play.

The 3D memory includes a memory array and peripheral devices for controlling signals to and from the memory array. For example, a Phase Change Memory (PCM) may drive a Phase Change material to switch between an amorphous Phase and a crystalline Phase based on heating and quenching of the Phase Change material in an electrothermal manner, so as to realize a storage function of 0 and 1 by using a difference in resistivity between the amorphous Phase and the crystalline Phase. With the increasing memory density, how to optimize and solve the problem of thermal crosstalk of memory cells becomes an important research direction in the field.

Disclosure of Invention

In view of the above, embodiments of the present invention provide a three-dimensional phase change memory and a method for manufacturing the same to solve at least one of the problems in the background art.

In order to achieve the purpose, the technical scheme of the invention is realized as follows:

the embodiment of the invention provides a three-dimensional phase change memory, which comprises:

a first conductive line extending in a first direction, a second conductive line extending in a second direction, and a phase change memory cell disposed between the first conductive line and the second conductive line in a third direction; the phase change memory cell comprises a first gating layer, a phase change memory layer and a second gating layer which are stacked along a third direction, wherein the first gating layer is located between the phase change memory layer and the first conductive line, the second gating layer is located between the phase change memory layer and the second conductive line, and the third direction is perpendicular to the first direction and the second direction; wherein the content of the first and second substances,

the thickness D1 of the first conductive line, the thickness D2 of the second conductive line, the thickness D1 of the first gate layer, the thickness D2 of the second gate layer, the coefficient k1 of the thermal conductivity of the first gate layer and the coefficient k2 of the thermal conductivity of the second gate layer satisfy the following conditions:

wherein D1 is not equal to D2, and lambda is 0.7-1.3.

In the above scheme, the coefficient of thermal conductivity k1 of the first pass layer is equal to the coefficient of thermal conductivity k2 of the second pass layer.

In the above scheme, the thickness d1 of the first gate layer is equal to the thickness d2 of the second gate layer.

In the above scheme, the material of the first gate layer includes a first compound, and the second gate layer includes a second compound doped with C or N.

In practice, the first and second compounds are selected from Ge_-One or more of Se series materials, Ge-Te-Pb series materials, Ge-Se-Te series materials, Zn-Te series materials, Ge-Te series materials, Nb-O series materials, Si-As-Te series materials, Si-Te series materials, C-Te series materials, B-Te series materials, Ge-Te series materials, Al-Te series materials, Ge-Sb series materials, Bi-Te series materials, As-Te series materials, or Sn-Te series materials.

In the foregoing solution, the phase change memory cell specifically includes:

the phase change memory device comprises a first gating layer, a first electrode, a second electrode, a phase change memory layer, a third electrode, a fourth electrode and a second gating layer which are sequentially stacked along a third direction; wherein the content of the first and second substances,

the material of the first electrode and the fourth electrode comprises a carbon-containing material;

the material of the second electrode and the third electrode comprises a metal material.

The embodiment of the invention also provides a preparation method of the three-dimensional phase change memory, which comprises the following steps:

forming a first conductive line material layer for forming a first conductive line extending in a first direction;

forming a phase change memory cell material lamination layer on the first conductive line material layer, wherein the phase change memory cell material lamination layer is used for forming a phase change memory cell, the phase change memory cell comprises a first gating layer, a phase change memory layer and a second gating layer which are stacked along a third direction, the first gating layer is positioned between the phase change memory layer and the first conductive line, and the second gating layer is positioned between the phase change memory layer and the second conductive line;

forming a second conductive line extending in a second direction on the phase change memory cell; wherein;

the third direction is perpendicular to the first direction and the second direction;

wherein D1 is not equal to D2, and lambda is 0.7-1.3.

In the above scheme, the material of the first gate layer includes a first compound, and the material of the second gate layer includes a second compound doped with C or N.

In the foregoing solution, the phase change memory cell specifically includes:

According to the embodiment of the invention, the thicknesses of the first conductive wire and the second conductive wire, the thicknesses of the first gating layer and the second gating layer and the heat conductivities of the first gating layer and the second gating layer are set to meet the formula, so that the nonuniformity of the phase change memory layer in the heat diffusion direction towards the first conductive wire and the second conductive wire is balanced, the heat distribution of the whole three-dimensional phase change memory along the first direction and the second direction is more uniform, the influence of thermal crosstalk on the storage program of the three-dimensional phase change memory is reduced, and the accuracy of the read/write program is further improved.

Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.

Drawings

FIG. 1a is a schematic structural diagram of a three-dimensional phase change memory according to the related art; FIG. 1b is a schematic diagram of thermal crosstalk of a 90nm structure three-dimensional phase change memory; FIG. 1c is a schematic diagram of thermal crosstalk of a 45nm structure three-dimensional phase change memory;

FIG. 2 is a schematic structural diagram of a three-dimensional phase change memory according to an embodiment of the present invention;

FIGS. 3a to 3b are schematic structural diagrams of phase change memory cells in a three-dimensional phase change memory according to various embodiments of the invention;

fig. 4 is a schematic flowchart of a method for manufacturing a three-dimensional phase change memory according to an embodiment of the invention;

fig. 5a to 5e are detailed cross-sectional views of a three-dimensional phase change memory according to an embodiment of the invention in different process steps;

FIGS. 6a to 6f are detailed cross-sectional views of a three-dimensional phase change memory according to another embodiment of the present invention in different process steps;

fig. 7 is a TEM image of a three-dimensional phase change memory in the related art.

Detailed Description

Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the invention are shown in the drawings, it should be understood that the invention may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the present invention; that is, not all features of an actual embodiment are described herein, and well-known functions and structures are not described in detail.

In the drawings, the size of layers, regions, elements, and relative sizes may be exaggerated for clarity. Like reference numerals refer to like elements throughout.

It will be understood that when an element or layer is referred to as being "on" … …, "adjacent to … …," "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on … …," "directly adjacent to … …," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention. And the discussion of a second element, component, region, layer or section does not necessarily imply that a first element, component, region, layer or section is present in the invention.

Spatial relationship terms such as "under … …", "under … …", "below", "under … …", "above … …", "above", and the like, may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below … …" and "below … …" can encompass both an orientation of up and down. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

As used in the following description, the term "three-dimensional memory" refers to a semiconductor device having the following memory cells: the memory cells are arranged vertically on a laterally oriented substrate such that the number of memory cells increases in the vertical direction relative to the substrate. As used herein, the term "vertical" means nominally perpendicular to a lateral surface of a substrate.

As shown in fig. 1a, the related art three-dimensional phase change memory is mainly a three-dimensional cross point (3D XPoint) architecture, under which a memory cell 110 is located at an intersection of a Bit Line (BL)111 and a Word Line (WL)112 that perpendicularly cross each other. In a three-dimensional cross-point architecture, the distance between adjacent memory cells is directly related to the line width of the Word Lines (WL) and Bit Lines (BL). As the memory density gradually increases, the memory cells are arranged more densely, and the spacing between adjacent memory cells is smaller, which leads to increased thermal crosstalk between memory cells. Fig. 1b-1c are schematic diagrams illustrating the thermal crosstalk phenomenon of the three-dimensional phase change memory, and when the three-dimensional cross-point memory is scaled down from a 90nm structure (see fig. 1b) to a 45nm structure (see fig. 1c), adjacent memory cells are already very close to respective thermal core regions, and the application of the three-dimensional memory is seriously affected by the unstable storage caused by the thermal crosstalk.

Fig. 7 is a TEM image of a three-dimensional phase change memory in the related art. As shown in fig. 7, in some related arts, thicknesses of word lines and bit lines in a three-dimensional phase change memory structure may be set to be different for the purposes of saving mask times, simplifying a manufacturing process of the three-dimensional phase change memory, improving alignment and stability of a phase change memory cell after etching, and the like. For example, as shown in fig. 1a and 7, the thickness of the word line 112 is greater than the thickness of the bit line 111. When the three-dimensional phase change memory works, the heat generated by the phase change memory layer is more easily transferred to the word line 112 with larger thickness, namely, the heat obtained on the word line 112 is larger than that obtained on the bit line 111. In addition, the bit lines 111 extend along the first direction, and the word lines 112 extend along the second direction, which may cause non-uniformity of thermal diffusion of the three-dimensional phase change memory along the first direction and along the second direction, which may further disturb the storage procedure of the three-dimensional phase change memory, and affect the accuracy of the read/write operation.

An embodiment of the present invention provides a three-dimensional phase change memory 200, as shown in fig. 2, including:

a first conductive line 211 extending in a first direction, a second conductive line 212 extending in a second direction, and a phase change memory cell 210 disposed between the first conductive line 211 and the second conductive line 212 in a third direction; the phase change memory cell 210 comprises a first gate layer 222-1, a phase change memory layer 221 and a second gate layer 222-2 stacked along a third direction, the first gate layer 222-1 is located between the phase change memory layer 221 and the first conductive line 211, the second gate layer 222-2 is located between the phase change memory layer 221 and the second conductive line 212, and the third direction is perpendicular to the first direction and the second direction; wherein the content of the first and second substances,

wherein D1 is not equal to D2, and lambda is 0.7-1.3.

According to the embodiment of the invention, the thicknesses of the first conductive wire and the second conductive wire, the thicknesses of the first gating layer and the second gating layer and the thermal conductivity coefficients of the first gating layer and the second gating layer are set to meet the formula, so that a means for adjusting the thermal diffusion towards the first conductive wire and the second conductive wire by regulating and controlling the thickness of the first conductive wire and the second conductive wire, the thicknesses of the first gating layer and the second gating layer, the thermal conductivity coefficients of the first gating layer and the second gating layer and other parameters is provided, and the controllable thermal distribution of the three-dimensional phase change memory is realized. (the thickness of the first and second conductive lines according to the present invention means the thickness of the first and second conductive lines in the third direction)

In some embodiments, the value of λ may be 0.85-1.15, and in a preferred embodiment, the value of λ may be 1. When the value of λ is 1, the thermal diffusion toward the first and second conductive lines is completely balanced, and the thermal distribution of the three-dimensional phase change memory in the first and second directions reaches complete uniformity. At this time, the influence of the thermal crosstalk on the storage program of the three-dimensional phase change memory will be reduced to a minimum level. Accordingly, the accuracy of storing the read/write program will be greatly improved.

In practical operation, the first direction, the second direction and the third direction may be perpendicular to each other.

In practice, the thickness of the second conductive line may be greater than the thickness of the first conductive line. Illustratively, the thickness of the second conductive line 212 is, for example, 1.5 to 3 times the thickness of the first conductive line 211, and more preferably, the thickness of the second conductive line 212 is, for example, 2 times the thickness of the first conductive line 211. In practice, the first conductive line may have a thickness of 20 to 50nm, such as 37nm for example, and the second conductive line may have a thickness of 40 to 120nm, such as 101nm for example. It should be understood that in some embodiments, the thickness of the first conductive line may be greater than the thickness of the second conductive line, and the thickness parameters included in the above implementations as applied to the second conductive line may also be applied to the first conductive line.

Here, the first and second conductive lines may be formed of 20nm/20nm uniform line width (L/S) conductive lines formed after a patterning process. The first and second conductive lines may be used as word lines and bit lines, respectively. For example, when the first conductive line is a word line, the second conductive line is a bit line, and when the first conductive line is a bit line, the second conductive line is a word line. The material of the first and second conductive lines may include a conductive material including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, a material of the first and second conductive lines is tungsten.

The phase-change memory layer 221 includes a phase-change memory material including, but not limited to, a chalcogenide compound, such as, for example, a germanium-antimony-tellurium (Ge-Sb-Te, GST) material or an indium-antimony-tellurium (In-Sb-Te, IST) material, and the like. In some embodiments, the material of the phase-change memory layer may be Ge₂Sb₂Te₅、Ge₁Sb₄Te₇、In₂Sb₂Te₅Or In₁Sb₂Te₄And so on.

In one embodiment, as shown in fig. 3a, the coefficient of thermal conductivity k1 of the first pass layer is equal to the coefficient of thermal conductivity k2 of the second pass layer.

In practice, the material of the first and second pass layers is selected from Ge_-Se series material, Ge-Te-Pb series material, Ge-Se-Te series material, Zn-Te series material, Ge-Te series material, Nb-O series material, Si-As-Te series materialOne or more of a material, a Si-Te series material, a C-Te series material, a B-Te series material, a Ge-Te series material, an Al-Te series material, a Ge-Sb series material, a Bi-Te series material, an As-Te series material, or an Sn-Te series material, or one or more of the above materials doped with C or N. In some embodiments, the materials of the first and second gate layers may be the same, thereby simplifying the three-dimensional memory component material variety and reducing the process implementation complexity.

When the coefficient of thermal conductivity k1 of the first gate layer is equal to the coefficient of thermal conductivity k2 of the second gate layer, the thicknesses D1 and D2 of the first and second gate layers, and the thicknesses D1 and D2 of the first and second conductive lines should satisfy the following condition:

wherein D1 is not equal to D2 and lambda is 0.7-1.3.

In practice, the thickness D2 of the second conductive line 212 may be greater than the thickness D1 of the first conductive line 211. Illustratively, the thickness of the second conductive line 212 is, for example, 1.5 to 3 times, more preferably, 2 times, the thickness of the first conductive line 211. In practice, the thickness of the first conductive line may be 20-50nm, for example, 37nm, and the thickness of the second conductive line may be 40-120nm, for example, 101 nm. Correspondingly, the thickness of the second gate layer may be 30-60nm, for example 40nm, and the thickness of the first gate layer may be 15-30nm, for example 20 nm.

In one embodiment, as shown in FIG. 3a, the thickness d1 of the first pass layer is equal to the thickness d2 of the second pass layer.

In practice, the thickness of the first and second gate layers may be, for example, 15-60nm, for example, 20 nm.

When the thickness D1 of the first gate layer is equal to the thickness D2 of the second gate layer, the thermal conductivity coefficients k1 and k2 of the first and second gate layers, and the thicknesses D1 and D2 of the first and second conductive lines should satisfy the following condition: k1D1 ═ λ k2D2, where D1 is not equal to D2 and λ is from 0.7 to 1.3.

In practice, the thickness D2 of the second conductive line 212 may be greater than the thickness D1 of the first conductive line 211. Illustratively, the thickness of the second conductive line 212 is, for example, 1.5 to 3 times the thickness of the first conductive line 211, and more preferably, the thickness of the second conductive line 212 is, for example, 2 times the thickness of the first conductive line 211. In practice, the first conductive line may have a thickness of 20 to 50nm, such as 37nm for example, and the second conductive line may have a thickness of 40 to 120nm, such as 101nm for example.

In practice, the material of the first gate layer may comprise a first compound, and the second gate layer may comprise a second compound doped with C or N, wherein the first compound and the second compound are selected from Ge_-One or more of Se series materials, Ge-Te-Pb series materials, Ge-Se-Te series materials, Zn-Te series materials, Ge-Te series materials, Nb-O series materials, Si-As-Te series materials, Si-Te series materials, C-Te series materials, B-Te series materials, Ge-Te series materials, Al-Te series materials, Ge-Sb series materials, Bi-Te series materials, As-Te series materials, or Sn-Te series materials. The selection of the materials can realize that the thermal conductivity coefficient of the second gating layer can be adjusted and controlled by adjusting the content of C or N.

In some embodiments, as shown in fig. 2, the phase change memory cell 210 specifically includes:

a first gate layer 222-1, a first electrode 231, a second electrode 232, a phase change memory layer 221, a third electrode 233, a fourth electrode 234, and a second gate layer 222-2 stacked in sequence along a third direction; wherein the content of the first and second substances,

the material of the first electrode 231 and the fourth electrode 234 includes a carbon-containing material;

the material of the second electrode 232 and the third electrode 233 includes a metal material.

In practice, the metal material includes, but is not limited to, tungsten, the carbon-containing material includes, but is not limited to, amorphous carbon, carbon nanotubes, graphene, etc., and in some specific embodiments, the material of the first electrode and the fourth electrode is amorphous carbon, and the material of the second electrode and the third electrode is tungsten. In some embodiments, the thickness of the first electrode and the fourth electrode may be the same, illustratively 5-50nm, specifically, for example, 15 nm. The thickness of the second electrode and the third electrode may be the same, and is illustratively 5 to 20nm, specifically, for example, 5 nm. Through the arrangement of the double-layer electrodes, on one hand, the first electrode and the fourth electrode made of the carbon-containing materials have low thermal conductivity, so that heat can be sealed and locked near the phase change storage layer as much as possible, and thermal diffusion and thermal crosstalk brought correspondingly are reduced.

In some embodiments, as shown in FIG. 2, the phase change memory cell 210 further includes a fifth electrode 235 between the first conductive line 211 and the first pass layer 222-1 and a sixth electrode 236 between the second conductive line 212 and the second pass layer 222-2. The material of the fifth electrode and the sixth electrode comprises a carbon-containing material, and the carbon-containing material comprises but is not limited to amorphous carbon, carbon nanotubes, graphene or the like. In practice, the fifth electrode and the sixth electrode have the same thickness, exemplarily 5-50nm, in particular, for example, 15 nm.

In some embodiments, as shown in fig. 2, 3a-3b, the cross-sections of the first and second pass-through layers 222-1, 222-2 may coincide.

The embodiment of the invention also provides a preparation method of the three-dimensional phase change memory, and fig. 4 is a flow schematic diagram of the preparation method of the three-dimensional phase change memory provided by the embodiment of the invention. As shown in fig. 4, the method includes:

step 401, forming a first conductive line material layer for forming a first conductive line extending along a first direction;

step 402, forming a phase change memory cell material lamination layer on the first conductive line material layer, wherein the phase change memory cell material lamination layer is used for forming a phase change memory cell, the phase change memory cell comprises a first gate layer, a phase change memory layer and a second gate layer which are laminated along a third direction, the first gate layer is located between the phase change memory layer and the first conductive line, and the second gate layer is located between the phase change memory layer and the second conductive line;

step 403, forming a second conductive line extending along a second direction on the phase change memory cell; wherein the third direction is perpendicular to the first direction and the second direction; the thickness D1 of the first conductive line, the thickness D2 of the second conductive line, the thickness D1 of the first gate layer, the thickness D2 of the second gate layer, the coefficient k1 of the thermal conductivity of the first gate layer and the coefficient k2 of the thermal conductivity of the second gate layer satisfy the following conditions:

wherein D1 is not equal to D2, and lambda is 0.7-1.3.

The preparation method can also comprise a plurality of different embodiments according to different process details. For example, FIGS. 5 a-5eFig. 6a to 6b are schematic structural diagrams of three-dimensional phase change memory in each process step in an embodimentfThe structure diagram of the three-dimensional phase change memory in each process link in another embodiment is shown.

First, a method for fabricating a three-dimensional phase change memory according to an embodiment of the invention is described in detail with reference to fig. 5a to 5 e.

The method starts with step 401, as shown in fig. 5a, forming a first conductive line material layer 211 ', the first conductive line material layer 211' being used to form a first conductive line 211 extending along a first direction.

In an actual process, referring to fig. 5a, a substrate 201 may be provided first, and the substrate is located below a process-performing surface, so as to provide a supporting function for the process. Here, the substrate may be a semiconductor substrate, and may include at least one elemental semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate), at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art.

A first conductive line material layer 211' is then formed on the substrate 201. The material of the first conductive line material layer 211' may include a conductive material including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof.

Next, step 402 is executed, referring to fig. 5b, forming a phase change memory cell material stack 210 ' on the first conductive line material layer 211 ', wherein the phase change memory cell material stack 210 ' is used to form a phase change memory cell, and the phase change memory cell includes a first gate layer 222-1, a phase change memory layer 221 and a second gate layer 222-2 stacked along a third direction, the first gate layer is located between the phase change memory layer and the first conductive line, and the second gate layer is located between the phase change memory layer and the second conductive line.

In a practical process, a phase change memory cell material stack 210 'is first formed on a first conductive line material layer 211'. In some embodiments, the phase change memory cell material stack 210 'includes a first gate material layer 222-1', a phase change memory material layer 221 ', and a second gate material layer 222-2' stacked in a third direction.

In some embodiments, the phase change memory cell material stack 210 'includes a fifth electrode material layer 235', a first gate material layer 222-1 ', a first electrode material layer 231', a second electrode material layer 232 ', a phase change memory material layer 221', a third electrode material layer 233 ', a fourth electrode material layer 234', a second gate material layer 222-2 ', and a sixth electrode material layer 236' stacked along a third direction. The fifth electrode material layer 235 ', the first gate material layer 222-1 ', the first electrode material layer 231 ', the second electrode material layer 232 ', the phase change memory material layer 221 ', the third electrode material layer 233 ', the fourth electrode material layer 234 ', the second gate material layer 222-2 ' and the sixth electrode material layer 236 ' are respectively used for forming the fifth electrode 235, the first gate layer 222-1, the first electrode 231, the second electrode 232, the phase change memory layer 221, the third electrode 233, the fourth electrode 234, the second gate layer 222-2 and the sixth electrode 236.

The material of the phase change memory material layer comprises a chalcogenide based alloy (chalcogenide glass), such as a GST (Ge-Sb-Te) alloy, or comprises any other suitable phase change material.

Next, the phase change memory cell material stack 210 'and the first conductive line material layer 211' are etched along a first direction, the first conductive line material layer 211 'becomes a first conductive line 211 extending along the first direction, and the phase change memory cell material stack 210' becomes a phase change memory cell structure 210 ″.

Next, as shown in FIG. 5d to FIG. 5e, step 403 is performed to form a second conductive line extending along a second direction on the phase change memory cell.

Specifically, first, as shown in fig. 5d, a second conductive line material layer 212' is formed on the phase change memory cell structure 210 ″.

The material of the second conductive line material layer 212' may include a conductive material including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof.

Next, the second conductive line material layer 212 'and the phase change memory cell structure 210 ″ are etched along the second direction, the second conductive line material layer 212' becomes a second conductive line 212 extending along the second direction, and the phase change memory cell structure 210 ″ becomes a phase change memory cell 210. Specifically, the fifth electrode material layer 235 ', the first gate material layer 222-1 ', the first electrode material layer 231 ', the second electrode material layer 232 ', the phase change memory material layer 221 ', the third electrode material layer 233 ', the fourth electrode material layer 234 ', the second gate material layer 222-2 ' and the sixth electrode material layer 236 ' are the fifth electrode 235, the first gate layer 222-1, the first electrode 231, the second electrode 232, the phase change memory layer 221, the third electrode 233, the fourth electrode 234, the second gate layer 222-2 and the sixth electrode 236. The first pass layer 222-1 is located between the phase change memory layer 221 and the first conductive line 211, and the second pass layer 222-2 is located between the phase change memory layer 221 and the second conductive line 212.

Wherein the third direction is perpendicular to the first direction and the second direction; the thickness D1 of the first conductive line, the thickness D2 of the second conductive line, the thickness D1 of the first gate layer, the thickness D2 of the second gate layer, the coefficient k1 of the thermal conductivity of the first gate layer and the coefficient k2 of the thermal conductivity of the second gate layer satisfy the following conditions:

wherein D1 is not equal to D2, and lambda is 0.7-1.3.

In practice, the gap between the phase change memory cell structures 210 ″ may also be filled with a filler material before the second conductive material layer 212' is formed.

Next, a method for manufacturing a three-dimensional phase change memory according to another embodiment of the present invention is further described in detail with reference to fig. 6a to 6 f.

The embodiment corresponding to fig. 6a to 6f is identical to the embodiment corresponding to fig. 5a to 5e in the specific processes (see fig. 5a to 5c) when step 401 and step 402 are performed, and the difference between the two processes is the specific process when step 403 is performed. Fig. 6a to 6d are schematic structural cross-sectional views of the three-dimensional memory in each process segment during the execution of step 403 in the embodiment corresponding to fig. 6a to 6 f. The method specifically comprises the following steps:

step 403 is performed to form a second conductive line extending in a second direction overlying the phase change memory cell.

As shown in fig. 6a, first, after forming the first conductive line 211 and the phase change memory cell structure body 210 ″ (see fig. 5c) extending in the first direction, a second conductive line lower sub-line material layer 212-1 'is formed on the phase change memory cell structure body 210 ″, and then, as shown in fig. 6b, the second conductive line lower sub-line material layer 212-1' and the phase change memory cell structure body 210 ″ are etched in the second direction, resulting in the second conductive line lower sub-line 212-1 and the phase change memory cell 210 extending in the second direction.

Thereafter, as shown in FIG. 6c, a second conductive over-line interlevel sub-line material layer 212-2 ' is formed over the phase change memory cell 210 and an upper phase change memory cell material stack 310 ' is formed over the second conductive over-line interlevel sub-line material layer 212-2 '. On the basis, as shown in fig. 6d, the upper phase change memory cell material stacked layer 310 'and the second conductive line upper layer sub-line material layer 212-2' are etched along the second direction, so as to obtain the second conductive line upper layer sub-line 212-2 and the upper phase change memory cell structure body 310 ″ extending along the second direction.

The process is performed so far, resulting in a second conductive line 212 (including a lower sub-line 212-1 of the second conductive line and an upper sub-line 212-2 of the second conductive line) extending in a second direction over the phase change memory cell 210.

The upper phase change memory cell structure 310 ″ obtained in the above process can be used to form an upper phase change memory cell to construct a multi-stack phase change memory. Fig. 6 e-6 f illustrate one embodiment of forming an upper phase change memory cell. The method specifically comprises the following steps:

as shown in fig. 6e to 6f, a third conductive line lower sub-line material layer 311-1 'is formed on the upper phase-change memory cell structure 310 ″, and the third conductive line lower sub-line material layer 311-1' is etched along the first direction, so as to obtain a third conductive line lower sub-line 311-1 extending along the first direction and an upper phase-change memory cell 310.

FIGS. 6a to 6fCorresponding embodiments and FIGS. 5a to 5eThe main difference between the three-dimensional phase change memory fabricated according to the corresponding embodiments is that fig. 5a to 5beThe second conductive line 212 in the corresponding embodiment comprises a layer of conductive lines, while fig. 6a to 6bfThe second conductive line 212 in the corresponding embodiment is formed by etching the second conductive line lower sub-line material layer 212-1 'and the second conductive line upper sub-line material layer 212-2', and comprises two conductive lines, namely a second conductive line lower sub-line 212-1 and a second conductive line upper sub-line 212-2, wherein the thickness D2 of the second conductive line 212 is equal to that of the second conductive line lower sub-line 212-1 and the second conductive line upper sub-line 212-2 in thickness. In practice, the material of the second conductive line lower sub-wire material layer 212-1 ' and the second conductive line upper sub-wire material layer 212-2 ' includes, but is not limited to, the material type of the second conductive line material layer 212 ' disclosed in the foregoing embodiments. It should be understood that fig. 6a to 6bfThe same components included in the corresponding embodiments as those in the previous embodiments may be of the same material kind as those disclosed in the previous embodiments.

In practice, the material of the first and second pass layers is selected from Ge_-One or more of Se series materials, Ge-Te-Pb series materials, Ge-Se-Te series materials, Zn-Te series materials, Ge-Te series materials, Nb-O series materials, Si-As-Te series materials, Si-Te series materials, C-Te series materials, B-Te series materials, Ge-Te series materials, Al-Te series materials, Ge-Sb series materials, Bi-Te series materials, As-Te series materials, or Sn-Te series materials, or one or more of the above materials doped with C or N. In some embodiments, the materials of the first and second gate layers may be the same, thereby simplifying the three-dimensional memory component material variety and reducing the process implementation complexity.

wherein D1 is not equal to D2 and lambda is 0.7-1.3.

In one embodiment, as shown in FIG. 3b, the thickness d1 of the first pass layer is equal to the thickness d2 of the second pass layer.

In practice, the thickness D2 of the second conductive line 212 may be greater than the thickness D1 of the first conductive line 211. Illustratively, the thickness of the second conductive line 212 is, for example, 1.5 to 3 times the thickness of the first conductive line 211, and more preferably, the thickness of the second conductive line 212 is, for example, 2 times the thickness of the first conductive line 211. In practice, the thickness of the first conductive line may be 20-50nm, for example, 37nm, and the thickness of the second conductive line may be 40-120nm, for example, 101 nm.

In practice, the material of the first gate layer may comprise a first compound, and the second gate layer may comprise a second compound doped with C or N, wherein the first compound and the second compound are selected from Ge_-One or more of Se series materials, Ge-Te-Pb series materials, Ge-Se-Te series materials, Zn-Te series materials, Ge-Te series materials, Nb-O series materials, Si-As-Te series materials, Si-Te series materials, C-Te series materials, B-Te series materials, Ge-Te series materials, Al-Te series materials, Ge-Sb series materials, Bi-Te series materials, As-Te series materials, or Sn-Te series materials. The selection of the above materials can be realizedAnd regulating the thermal conductivity coefficient of the second gating layer by regulating the content of C or N.

In some embodiments, the material of the second and

third electrodes

232, 233 comprises a metallic material; the materials of the first electrode 231, the fourth electrode 234, the fifth electrode 235, and the sixth electrode include carbon-containing materials. In practice, the metal material includes, but is not limited to, tungsten, the carbon-containing material includes, but is not limited to, amorphous carbon, carbon nanotubes, graphene, etc., and in some specific embodiments, the material of the second electrode and the third electrode is tungsten. In some embodiments, the thickness of the first and fourth electrodes and the thickness of the fifth and sixth electrodes may be the same, illustratively 5-50nm, specifically, for example, 15 nm. The thickness of the second electrode and the third electrode may be the same, and is illustratively 5 to 20nm, specifically, for example, 5 nm. Through the arrangement, on one hand, the first electrode and the fourth electrode made of the carbon-containing materials have low thermal conductivity, heat can be sealed and locked near the phase change memory layer as much as possible, thermal diffusion and thermal crosstalk brought correspondingly are reduced, and on the other hand, due to the arrangement of the second electrode and the third electrode made of the metal materials, impurities in the first electrode and the fourth electrode can be prevented from diffusing into the phase change memory layer to cause performance deterioration of the device.

It should be noted that the embodiment of the three-dimensional phase change memory provided by the invention and the embodiment of the preparation method of the three-dimensional phase change memory belong to the same concept; the technical features of the technical means described in the embodiments may be arbitrarily combined without conflict.

The above description is only exemplary of the present invention and should not be taken as limiting the scope of the present invention, and any modifications, equivalents, improvements, etc. that are within the spirit and principle of the present invention should be included in the present invention.

Claims

1. A three-dimensional phase change memory, comprising:

wherein D1 is not equal to D2, and lambda is 0.7-1.3.

2. The three-dimensional phase change memory according to claim 1, wherein:

the coefficient of thermal conductivity k1 of the first pass layer is equal to the coefficient of thermal conductivity k2 of the second pass layer.

3. The three-dimensional phase change memory according to claim 1, wherein:

the thickness d1 of the first pass layer is equal to the thickness d2 of the second pass layer.

4. The three-dimensional phase change memory according to claim 1 or 3, wherein:

the material of the first gate layer comprises a first compound, and the second gate layer comprises a second compound doped with C or N.

5. The three-dimensional phase-change memory according to claim 3, wherein the phase-change memory cell specifically comprises:

6. A preparation method of a three-dimensional phase change memory is characterized by comprising the following steps:

forming a second conductive line extending in a second direction on the phase change memory cell; wherein the content of the first and second substances,

wherein D1 is not equal to D2, and lambda is 0.7-1.3.

7. The method for manufacturing a three-dimensional phase change memory according to claim 6, wherein:

8. The method for manufacturing a three-dimensional phase change memory according to claim 6, wherein:

9. The method of manufacturing a three-dimensional phase change memory according to claim 6 or 8, wherein:

10. The method for manufacturing a three-dimensional phase change memory according to claim 6, wherein:

the phase change memory cell specifically includes: