KR101923428B1 - Phase Change Random Access Memory and method for manufacturing of the same - Google Patents

Abstract

The present invention relates to a phase-change memory device and a method of manufacturing the same. In the present invention, a separation membrane is formed by using a material having a crystallization temperature of 400 ° C or higher, a low-k material or a high-k material, a material having a low electrical conductivity, or a material having a low thermal conductivity, During cell switching, elemental volatilization of the phase change material constituting the phase change material film is prevented to minimize compositional deviation per unit area. Also, the crystallinity of the phase-change memory device can be improved by controlling the size of crystal grains during crystal-amorphization through the separation film and inducing an increase in cell resistance.

Description

[0001] The present invention relates to a phase change memory device and a manufacturing method thereof,

The present invention relates to a phase-change memory device and a method of manufacturing the same, and more particularly, to a phase-change memory device capable of minimizing a compositional deviation of a phase-change material and a method of manufacturing the same.

With the rapid development of the information and communication field and the rapid popularization of information media, there is an increasing demand for a next generation semiconductor memory device capable of high-speed operation and having a large memory capacity.

Such a next-generation semiconductor memory device has been developed by taking advantage of a volatile memory device such as a DRAM and a non-volatile memory device such as a flash memory. The memory device includes a phase change random access memory (PCRAM), a resistive random access memory (RRAM) Spin Transfer Torque Random Access Memory) or PoRAM (Polymer Random Access Memory).

Among the next-generation semiconductor memory devices, PCRAM using a phase-change material is a device in which data is stored by using the difference in resistance due to the crystal structure change of the phase change material film. As the phase change material, a chalcogenide compound (GST) composed of germanium (Ge), antimony (Sb) and tellurium (Te) can be used. .

That is, when the temperature of the phase change material film is increased to the vicinity of the melting point by applying a high-magnitude current pulse to the phase change material film for a short time, and then quenched (about 1 ns), the heat-affected phase change material film portion becomes amorphous with high resistance (Reset). On the other hand, when a relatively low-sized current pulse is applied for a long time to crystallize the phase-change material layer at a crystallization temperature lower than the melting temperature, and then cooled, the heat-affected phase change material layer portion becomes a crystalline state with low resistance (set).

As described above, the phase-change material film has characteristics of varying the resistance depending on the crystal structure (the crystalline state has a small resistance and the amorphous state has a large resistance). By using such a resistance difference, data of "1" or "0" It is programmed and erased.

On the other hand, the region where the phase change material film changes into the amorphous / crystalline state depending on the magnitude of the supplied current and the supply time is referred to as a phase change region. This is because, as the phase change region is smaller, a smaller amount of current is applied to obtain a desired crystal structure, and amorphous / crystal change control and formation speed are improved.

However, since the upper electrode is usually disposed on the phase change material film, most of the applied current flows upward. A phase change region which is changed into an amorphous state is not uniformly formed in the phase change material film and is formed in a biased state on the upper portion of the lower electrode.

Further, during the crystallization-amorphization, the phase change material is volatilized according to the temperature applied to the phase change material film, and the distribution of the element per unit area varies depending on the bonding state of the element during the crystallization, thereby adversely affecting the reliability.

FIGS. 1A and 1B illustrate a crystal-amorphization process in a planar cell type phase change memory device.

Referring to FIG. 1A, a lower electrode 100 is formed on a semiconductor substrate (not shown) on which a conventional access element is formed. A contact 104 penetrating the interlayer insulating layer 102 is formed on the lower electrode 100 and a phase change material layer 106 is formed on the contact layer 104. An upper electrode 108 is formed on the phase change material layer 106.

Here, the phase-change material layer 106 is cooled after a low-magnitude current is applied for a long time, and a crystalline state with a low resistance is maintained, that is, a set state is maintained.

Referring to FIG. 1B, a high-magnitude current is applied to the crystalline phase-change material layer 106, followed by quenching (less than about 1 ns). Then, a part of the phase-change material film 106 in the crystalline state becomes an amorphous state 110 having a high resistance, that is, a reset state.

1B, the amorphized phase change region 110 is concentrated on a portion of the phase change material film 106 during crystallization-amorphization of the phase change material film. More specifically, the phase change region 110 is biased toward the upper region of the contact 104. This biasing phenomenon is caused by the current flow between the lower electrode and the upper electrode, and the applied current flows toward the upper portion where the upper electrode is located, so that amorphization occurs only in a part of the entire phase change material film region.

However, when the phase change region is biased to the contact upper region as described above, the compositional deviation per unit region becomes large, which results in a problem that the electrical characteristics of the phase change memory element deteriorate.

On the other hand, such biasing phenomenon of the phase change region occurs in a convolved cell type phase change memory element in which a phase change material film is surrounded by an insulating film.

FIGS. 2A and 2B illustrate a crystal-amorphization process in a confined cell type phase change memory device.

Referring to FIG. 2A, a lower electrode contact 200 is formed on a semiconductor substrate (not shown) on which a conventional access element is formed. An interlayer insulating layer 202 is formed on the lower electrode contact 200 and a lower electrode 204 is formed in a hole formed by partially etching the interlayer insulating layer. A phase change material film 208 surrounded by a spacer insulating film 206 is formed on the lower electrode 204. An upper electrode 210 is formed on the spacer insulating film 206 and the phase change material film 208.

Here, the phase change material film 208 is cooled after a low-magnitude current is applied for a long time to maintain a crystalline state with a low resistance, that is, a set state.

Referring to FIG. 2B, a high-magnitude current is applied to the phase-change material layer 208 in the crystalline state, followed by rapid cooling. Then, a part of the phase-change material film 208 in the crystalline state becomes a resistive amorphous state 212, that is, a reset state.

As described above, biasing phenomenon of the phase change region 212 occurs in the crystal-amorphous state as in the planar cell type phase change memory device. That is, as shown in FIG. 2B, an amorphous phase change region 212 appears in a partial region of the phase change material film 208. More specifically, the phase change region 212 is concentrated on the upper center of the lower electrode 204.

The bias phenomenon in such a confined cell type phase change memory device is also caused by the current flow between the lower electrode and the upper electrode. When the amorphization occurs only in a partial region of the entire phase change material film, the compositional deviation per unit region is increased As a result, the electrical characteristics of the phase change memory element deteriorate.

The compositional deviation of the phase change material layer in the planar cell type and the confined cell type phase change memory device is also caused by the volatilization of the phase change material element depending on the temperature applied at the time of cell switching.

It is an object of the present invention to provide a phase-change memory device capable of preventing elemental volatilization of a phase-change material and a method of manufacturing the same.

It is another object of the present invention to provide a phase-change memory device capable of minimizing a compositional deviation of a phase-change material and a method of manufacturing the same.

It is another object of the present invention to provide a phase-change memory device capable of controlling the size of crystal grains during crystal-amorphization and a method of manufacturing the same.

It is another object of the present invention to provide a phase change memory device and a method of manufacturing the same, which can increase the cell resistance and improve the reliability.

A phase-change memory device according to an embodiment of the present invention includes: a lower electrode formed on a semiconductor substrate; A phase change material layer formed on the lower electrode and having a separation layer for preventing elemental volatilization of the phase change material; And an upper electrode formed on the phase change material layer.

A phase-change memory device according to an embodiment of the present invention includes: a lower electrode formed on a semiconductor substrate; A contact formed by filling a conductive film in a hole formed through the interlayer insulating film on the lower electrode; A phase change material film formed on the contact, the phase change material film having a barrier film type barrier film for preventing elemental volatilization of the phase change material; And an upper electrode formed on the phase change material layer.

A phase change memory device according to an embodiment of the present invention includes: a lower electrode contact formed on a semiconductor substrate; A lower electrode formed by depositing a conductive film on a lower portion of a hole formed through an interlayer insulating film on an upper portion of the lower electrode contact; A spacer insulating film formed on a sidewall of the hole in which the lower electrode is formed; A separation layer formed in the form of a vertical film inside the trench in which the spacer insulating film is formed to prevent elemental volatilization of the phase change material; A phase change material layer comprising a plurality of unit phase change material layers formed by filling a phase change material in a trench in which the separation layer is formed; And an upper electrode formed on the phase change material layer.

According to an aspect of the present invention, there is provided a method of fabricating a phase change memory device, including: forming a lower electrode on a semiconductor substrate; Forming a phase change material film on the lower electrode, the phase change material film including a separation film for preventing elemental volatilization of the phase change material; And forming an upper electrode on the phase change material layer.

According to an aspect of the present invention, there is provided a method of fabricating a phase change memory device, including: forming a lower electrode on a semiconductor substrate; Forming a hole through the interlayer insulating film on the lower electrode, filling the hole with a conductive film to form a contact; Forming a first unit phase change material layer on the contact; Forming a separation membrane on the first unit phase change material film to prevent elemental volatilization of the phase change material; Forming a second unit phase change material layer on the separation layer to form a phase change material layer; And forming an upper electrode on the first / second unit phase change material layer and the separation layer.

A method of fabricating a phase change memory device, comprising: forming a lower electrode contact on a semiconductor substrate; Forming a hole through the interlayer insulating film on the lower electrode contact, and depositing a conductive film on the lower portion of the hole to form a lower electrode; Forming a spacer insulating film on a sidewall of the hole in which the lower electrode is formed; Forming a separation film in a trench shape in the trench in which the spacer insulation film is formed to prevent elemental volatilization of the phase change material; Forming a phase change material layer including a plurality of unit phase change material layers separated by the separation layer by filling a phase change material in the trench in which the separation layer is formed; And forming an upper electrode on the phase change material layer.

According to the present invention, a phase-change material layer is formed by using a material having a crystallization temperature of at least 400 ° C., a low-k material or a high-k material, a material having a low electrical conductivity, or a material having a low thermal conductivity. Thereby preventing the elemental volatilization of the phase change material constituting the phase change material film during cell switching, thereby minimizing the composition deviation per unit area. In addition, it is possible to improve the reliability of the phase-change memory device by controlling the size of crystal grains during crystal-amorphization through the separation film and inducing an increase in cell resistance.

FIGS. 1A and 1B illustrate a crystal-amorphization process in a planar cell type phase change memory device according to the prior art.
FIGS. 2A and 2B illustrate a crystallization-amorphization process in a confined cell type phase change memory device according to the prior art.
3A through 3E illustrate a planar cell type phase change memory device fabrication method according to a preferred embodiment of the present invention.
4A through 4E illustrate a method of fabricating a confined cell type phase change memory device according to a preferred embodiment of the present invention.

Hereinafter, a phase change memory device and a method of manufacturing the same according to embodiments of the present invention will be described in detail with reference to the following drawings.

First, in FIG. 3D, a planar cell type phase change memory device according to a preferred embodiment of the present invention is shown.

Referring to FIG. 3D, a lower electrode 300 is formed on a semiconductor substrate (not shown) on which a conventional access element is formed. An interlayer insulating layer 302 is formed on the lower electrode 300 and a contact 304 is formed through the interlayer insulating layer 302. A phase change material layer 306-306a, 306b, or 306c having a multilayer structure is formed on the contact 304, and an upper electrode 310 is formed on the phase change material layer 306-306a, 306b, or 306c.

The phase change material layer 306 of the multi-layer structure is a core constituent of the present invention, and includes a material having a crystallization temperature of 400 degrees or more and a material having a crystallization temperature of less than 400 degrees Between the unit phase change material layers 306a, 306b, -k material or a high-k material, (3) a material having a low electrical conductivity, or (4) a material having a low thermal conductivity.

As described above, when the isolation film 308 is formed between the phase change material films 306, the entire phase change material film 306 is formed by the separation film 308 to have thinner unit phase change material films 306a and 306b , And 306c. As a result, diffusion of the phase change material element having volatility at a low temperature (about 400 degrees or less) is prevented by the separation membrane 308 to maintain a uniform composition, and the area of the crystalline phase- The compositional deviation of the phase change material can be minimized.

Meanwhile, FIG. 4D illustrates a convolved cell type phase change memory device according to a preferred embodiment of the present invention.

Referring to FIG. 4D, a lower electrode contact 400 is formed on a semiconductor substrate (not shown) on which a conventional access element is formed. An interlayer insulating layer 402 is formed on the lower electrode contact 400 and a lower electrode 404 is formed in a hole formed by partially etching the interlayer insulating layer 402. A multi-layered phase change material film 412 surrounded by a spacer insulating film 406 is formed on the lower electrode 404, and an upper electrode 414 is formed on the phase change material film 412.

The phase-change material layer 412 of the multi-layer structure is a core constituent of the present invention. The phase-change material layer 412 includes a material having a crystallization temperature of 400 ° C or more, a low-k material, or a high- k material, (3) a material having a low electrical conductivity, or (4) a material having a low thermal conductivity.

When the vertical membrane 410 is formed between the phase change material layers 412, the entire phase change material layer 412 is separated from the thinner unit phase change material layers 412a, 412b, and 412c. As a result, diffusion of a phase change material element having a volatility at a low temperature (about 400 degrees or less) is prevented by the separation membrane 410 to maintain a uniform composition, and the area of the crystalline phase- The compositional deviation of the phase change material can be minimized.

Hereinafter, a manufacturing process of the planar cell type and the confined cell type phase change memory device will be described in more detail with reference to the drawings.

3A and 3E illustrate a planar cell type phase change memory device fabrication method according to a preferred embodiment of the present invention.

Referring to FIG. 3A, a lower electrode 300 is formed on a semiconductor substrate (not shown) on which a conventional access element is formed. After the interlayer insulating layer 302 is deposited on the lower electrode 300, a hole is formed through the interlayer insulating layer 302. Then, a conductive film is filled in the hole to form a contact 304.

Referring to FIG. 3B, a first phase change material layer 306a is formed on a semiconductor substrate on which the contact 304 is formed. Next, a first separation layer 308a is formed on the first phase-change material layer 306a.

Here, the first phase change material layer 306a may be formed of a material selected from the group consisting of Ge, Se, Te, a mixture thereof, and an alloy thereof. More specifically, it can be formed of Ge, Se, Te, Sb, Bi, Pb, Sn, As, S, Si, P, O, N and mixtures or alloys thereof.

The first separator 308a may be formed of a material having a crystallization temperature of 400 degrees or more, a low-k material or a high-k material, a material having a low electrical conductivity, or a material having a low thermal conductivity. More specifically, the material having a crystallization temperature of 400 ° C or higher may be an oxide or nitride such as SiO ₂ , Si ₃ N ₄ , and Nb ₂ O ₅ . The low-k material may be a metal oxide or a metal nitride such as Si ₃ N ₄ , SiO ₂ , SION, or SIOC. The high-k material may be Ta ₂ O ₅ , TiO ₂ , HfO ₂ , ZrO ₂ , HfSiO _3, may be a metal oxide and metal nitride, such as HfZrO _3. The material having a low electrical conductivity may be a metal oxide such as Si ₃ N ₄ , SiO ₂ , SION, SIOC, Ta ₂ O ₅ , TiO ₂ , HfO ₂ , ZrO ₂ , HfSiO ₃ , HfZrO ₃ , . The low thermal conductivity material may be a metal oxide or metal nitride such as Si ₃ N ₄ , SiO ₂ , SION, SIOC, Ta ₂ O ₅ , TiO ₂ , HfO ₂ , ZrO ₂ , HfSiO ₃ , HfZrO ₃ and the like.

The first separation layer 308a may be formed by conventional chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or spin coating.

Referring to FIG. 3C, a second phase change material layer 306b is formed on the first separation layer 308a. A second separation layer 308b is formed on the second phase-change material layer 306b. The third phase change material layer 306c is formed on the second separation layer 308b to form a plurality of unit phase change material layers 306a, 306b, and 306c and a plurality of unit separation layers 308a, and 308b) is formed.

Here, the second phase change material layer 306b and the third phase change material layer 306c may be formed of the same material or different materials as the first phase change material layer 306a. That is, the first phase change material layer 306a, the second phase change material layer 306b, and the third phase change material layer 306c may be formed of the same phase change material or may be formed of different materials. have.

The second separation layer 308b may be formed of the same material as that of the first separation layer 308a or may be formed of a different material using CVD, PVD, ALD, or spin coating.

Referring to FIG. 3D, an upper electrode 310 is formed on the third phase-change material layer 306c.

Referring to FIG. 3E, a high-magnitude current is applied to the crystalline phase-change material layer 306 and then quenched (less than about 1 ns). Then, a part of each of the unit phase change material films 306a, 306b, and 306c that have been in the crystalline state transitions to the amorphous state to form the phase change regions 312a, 312b, and 312c. That is, the first phase change material film 306a has the first phase change region 312a, the second phase change material film 306b has the second phase change region 312b, the third phase change material film 306c The third phase change region 312c is formed independently of each other.

Two unit separation membranes 308a and 308b are formed at equal intervals in the phase change material layer 306 so that the total phase change material layer 306 includes a plurality of unit phase change material layers 306a , 306b, and 306c. During the cell switching by the separation membranes 308a and 308b, the phase change material elements are prevented from being volatilized and the composition of the unit phase change material layers 306a, 306b, and 306c is uniformly maintained. In addition, The area of the material film itself becomes small, and the phase change regions 312a, 312b, and 312c are uniformly formed in the unit phase change material films 306a, 306b, and 306c.

In the planar cell type phase change memory device according to the related art, there is a problem that the compositional deviation of the entire phase change material film is concentrated in a part of the deep phase change region and the electrical characteristics of the phase change memory element are poor. However, in the present invention, since the phase change region is uniformly formed in the unit phase change material film divided into a plurality of unit film by the diaphragm type separation membrane, the electrical characteristics of the phase change memory element can be improved.

Meanwhile, in forming the multi-layered phase change material layer 306 composed of the plurality of unit phase change material layers 306a, 306b, and 306c and the plurality of unit separation layers 308a and 308b, The number and thickness of the unit separation membranes can be freely changed by the designer.

Typically, in the case of PCRAM, the cell resistance can be controlled by adjusting the size of the crystal grains or by using additives (e.g., Si, C, N, etc.). Therefore, it is preferable to determine the type and thickness of the phase change material layer, and the type and thickness of the separation layer after previously calculating the size of the crystal grain to obtain a desired cell resistance. Therefore, as shown in FIG. 3D, two unit separation films 308a and 308b may be arranged at equal intervals in the phase change material film, or may be arranged at specified intervals by calculation of crystal grain size, A phase change memory element having a low operating current can be manufactured.

3E shows a state where the phase change regions 312a, 312b, and 312c in the unit phase change material layers 306a, 306b, and 306c are formed in the same area. However, the areas of these phase change areas 312a, 312b, and 312c can also be individually controlled. That is, the amount of current applied to the unit phase change material layers 306a, 306b, and 306c is individually controlled so that the phase change regions 312a, 312b, and 306c formed in the unit phase change material layers 306a, 312c can be independently formed, a desired cell resistance can be obtained.

4A and 4E illustrate a method of fabricating a conformed cell type phase change memory device according to a preferred embodiment of the present invention.

Referring to FIG. 4A, a lower electrode contact 400 is formed on a semiconductor substrate (not shown) on which a conventional access element is formed. After the interlayer insulating layer 402 is deposited on the lower electrode contact layer 400, a hole is formed through the interlayer insulating layer 402. A conductive film is deposited on the bottom region of the hole to form the lower electrode 404.

A spacer insulating layer 406 is formed on a sidewall of the hole in which the lower electrode 404 is formed to form a trench 408 in which a phase change material layer is to be formed.

Referring to FIG. 4B, a separation layer 410 including a first separation layer 410a and a second separation layer 410b is formed in the trench 408. Referring to FIG. The first and second separation membranes 410a and 410b may be formed of a material having a crystallization temperature of 400 degrees or more, a low-k material or a high-k material, a material having a low electrical conductivity, or a material having a low thermal conductivity . More specifically, the material having a crystallization temperature of 400 ° C or higher may be an oxide or nitride such as SiO ₂ , Si ₃ N ₄ , and Nb ₂ O ₅ . The low-k material may be a metal oxide or a metal nitride such as Si ₃ N ₄ , SiO ₂ , SION, or SIOC. The high-k material may be Ta ₂ O ₅ , TiO ₂ , HfO ₂ , ZrO ₂ , HfSiO _3, may be a metal oxide and metal nitride, such as HfZrO _3. The material having a low electrical conductivity may be a metal oxide such as Si ₃ N ₄ , SiO ₂ , SION, SIOC, Ta ₂ O ₅ , TiO ₂ , HfO ₂ , ZrO ₂ , HfSiO ₃ , HfZrO ₃ , . The low thermal conductivity material may be a metal oxide or metal nitride such as Si ₃ N ₄ , SiO ₂ , SION, SIOC, Ta ₂ O ₅ , TiO ₂ , HfO ₂ , ZrO ₂ , HfSiO ₃ , HfZrO ₃ and the like.

The first and second separation membranes 410a and 410b may be formed by conventional chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or spin coating.

Referring to FIG. 4C, a phase change material is filled in the trench 408 in which the separation layer 410 is formed. At this time, the phase change material may be formed of a material selected from the group consisting of Ge, Se, Te, a mixture thereof, and an alloy thereof. More specifically, it can be formed of Ge, Se, Te, Sb, Bi, Pb, Sn, As, S, Si, P, O, N and mixtures or alloys thereof.

When the phase change material is filled in the trenches in which the two unit separation membranes 410a and 410b are formed, the unit separation layers 410a and 410b, which are already spaced apart at predetermined intervals, The change material films 412-412a, 412b, and 412c are formed. Thus, a multi-layered phase change material film 412 composed of a plurality of unit phase change material films 412a, 412b, and 412c and a plurality of unit separation films 410a and 410b, which is a core structure of the present invention, is implemented.

Referring to FIG. 4D, an upper electrode 414 is formed on the phase change material layer 412 of the multi-ply structure.

Referring to FIG. 4E, a high-magnitude current is applied to the crystalline phase-change material layer 412, followed by quenching (less than about 1 ns). Then, a part of each of the unit phase change material films 412a, 412b, and 412c that have been in the crystalline state transitions to an amorphous state to form respective phase change regions. That is, the first phase change material film 412a has the first phase change region 416a, the second phase change material film 412b has the second phase change region 416b, and the third phase change material film 412c The third phase change region 416c is formed independently of each other.

At this time, two separation membranes 410a and 410b are inserted at equal intervals in the phase change material layer 412, and the total phase change material layer 412 includes a plurality of unit phase change material layers 412a, 412b, and 412c. By the unit separation membranes 410a and 410b, the phase change material elements are prevented from being volatilized during the cell switching, the composition of the unit phase change material layers 412a, 412b, and 412c is uniformly maintained, and the phase- The area of the material film itself is reduced, and the phase change regions 416a, 416b, and 416c are uniformly formed in the unit phase change material films 412a, 412b, and 412c.

In the convolved cell type phase-change memory device according to the related art, there is a problem that the compositional deviation of the entire phase-change material film is concentrated in a part of the deep-sea phase change region and the electrical characteristics of the phase-change memory device are poor. However, in the present invention, since the phase change region is uniformly formed in the unit phase change material film divided into a plurality of unit film by the longitudinal film type separation membrane, the electrical characteristics of the phase change memory element can be improved.

Meanwhile, in forming the multi-layered phase change material film 412 composed of the plurality of unit phase change material films 412a, 412b, and 412c and the plurality of unit separation films 410a and 410b, The number and thickness of the unit separation membranes can be freely changed by the designer.

Typically, in the case of PCRAM, the cell resistance can be controlled by adjusting the size of the crystal grains or by using additives (e.g., Si, C, N, etc.). Therefore, it is preferable to determine the type and thickness of the phase change material layer, and the type and thickness of the separation layer after previously calculating the size of the crystal grain to obtain a desired cell resistance. Therefore, as shown in FIG. 4B, two unit separating films 410a and 410b are arranged at equal intervals in the trench to be filled with the phase change material film, or arranged at specified intervals by the grain size calculation, A phase change memory element having a low operating current can be manufactured.

4E, the phase change regions 416a, 416b, and 416c in the unit phase change material films 412a, 412b, and 412c are formed in the same area. However, the areas of these phase change regions 416a, 416b, and 416c can also be individually controlled. That is, the amount of current applied to the unit phase change material layers 412a, 412b, and 412c is individually controlled so that the phase change regions 416a, 416b, and 416c formed in the unit phase change material layers 412a, 416c can be independently formed, a desired cell resistance can be obtained.

As described above, in the present invention, a material having a crystallization temperature of 400 ° C or higher, a low-k material or a high-k material, a material having a low electrical conductivity, or a material having a low thermal conductivity is inserted By forming a separation membrane, elemental volatilization of the phase change material constituting the phase change material film is prevented during cell switching, thereby minimizing compositional deviation per unit area. In addition, it is possible to improve the reliability of the phase-change memory device by controlling the size of crystal grains during crystal-amorphization through the separation film and inducing an increase in cell resistance.

The planar cell type and the confined cell type are described as an example, but the present invention is not limited thereto, and the present invention can be generally applied to a phase change memory device using a phase change material film.

While the present invention has been particularly shown and described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, It can be understood that It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive.

300: lower electrode 302: interlayer insulating film
304: contact 306: phase change material film
308: separator 310: upper electrode
312a, 312b, and 312c: phase change region 400: lower electrode contact
402: interlayer insulating film 404: lower electrode
406: spacer insulating film 408: trench
410: separator 412: phase change material film
414: upper electrode 416a, 416b, 416c: phase change region

Claims (30)

A lower electrode formed on a semiconductor substrate;
A phase change material layer formed on the lower electrode and having a separation layer for preventing elemental volatilization of the phase change material; And
And an upper electrode formed on the phase change material layer,
The separation membrane is formed in the phase-change material layer in a plurality of or more than one, to separate the phase-change material layer into a plurality of thin films,
The separation membrane may be formed of a material having a crystallization temperature of 400 ° C or higher, a low-k material or a high-k material, a material having a low electrical conductivity, or a material having a low thermal conductivity,
Material wherein the crystallization temperature is at least 400 degrees is SiO _2, Si ₃ N _4, and an oxide or nitride, such as Nb ₂ O _5, wherein the low-k materials are metal oxides such as _{Si 3 N 4, SiO 2,} SiON, SiOC , and Wherein the high-k material is a metal oxide or a metal nitride such as Ta ₂ O ₅ , TiO ₂ , HfO ₂ , ZrO ₂ , HfSiO ₃ , or HfZrO _3, and the low electrical conductivity material is Si ₃ N ₄ , A metal oxide such as SiO ₂ , SiON, SiOC, Ta ₂ O ₅ , TiO ₂ , HfO ₂ , ZrO ₂ , HfSiO ₃ and HfZrO ₃ and a metal nitride, and the low thermal conductivity material is Si ₃ N ₄ , SiO ₂ , SiON , SiOC, Ta ₂ O ₅ , TiO ₂ , HfO ₂ , ZrO ₂ , HfSiO ₃ , HfZrO ₃ and metal nitride. delete delete delete ◈ Claim 5 is abandoned due to the registration fee. The phase-change memory device according to claim 1, wherein the separation membrane is disposed at equal intervals or at specified intervals in the phase change material film. Forming a lower electrode on a semiconductor substrate;
Forming a phase change material film on the lower electrode, the phase change material film including a separation film for preventing elemental volatilization of the phase change material; And
Forming an upper electrode over the phase change material layer,
The separation membrane is formed in the phase-change material layer in a plurality of or more than one, to separate the phase-change material layer into a plurality of thin films,
The separation membrane may be formed of a material having a crystallization temperature of 400 ° C or higher, a low-k material or a high-k material, a material having a low electrical conductivity, or a material having a low thermal conductivity,
Material wherein the crystallization temperature is at least 400 degrees is SiO _2, Si ₃ N _4, and an oxide or nitride, such as Nb ₂ O _5, wherein the low-k materials are metal oxides such as _{Si 3 N 4, SiO 2,} SiON, SiOC , and Wherein the high-k material is a metal oxide or a metal nitride such as Ta ₂ O ₅ , TiO ₂ , HfO ₂ , ZrO ₂ , HfSiO ₃ , or HfZrO _3, and the low electrical conductivity material is Si ₃ N ₄ , SiO ₂ , SION, SIOC, Ta ₂ O ₅ , TiO ₂ , HfO ₂ , ZrO ₂ , HfSiO ₃ , HfZrO ₃ and the like, and the low thermal conductivity material is Si ₃ N ₄ , SiO ₂ , SiON , SiOC, Ta ₂ O ₅ , TiO ₂ , HfO ₂ , ZrO ₂ , HfSiO ₃ , HfZrO ₃ , and metal nitride. delete delete delete ◈ Claim 10 is abandoned due to the registration fee. 7. The method of claim 6, wherein the separation layer is disposed in the phase change material layer at regular intervals or at specified intervals. delete delete delete delete delete delete delete delete delete delete A lower electrode contact formed on a semiconductor substrate;
A lower electrode formed by depositing a conductive film on a lower portion of a hole formed through an interlayer insulating film on an upper portion of the lower electrode contact;
A spacer insulating film formed on a sidewall of the hole in which the lower electrode is formed;
A separation layer formed in the form of a vertical film inside the trench in which the spacer insulating film is formed to prevent elemental volatilization of the phase change material;
A phase change material layer comprising a plurality of unit phase change material layers formed by filling a phase change material in a trench in which the separation layer is formed; And
And an upper electrode formed on the phase change material layer,
The separation membrane is formed in the phase-change material layer in a plurality of or more than one, to separate the phase-change material layer into a plurality of thin films,
The separation membrane may be formed of a material having a crystallization temperature of 400 ° C or higher, a low-k material or a high-k material, a material having a low electrical conductivity, or a material having a low thermal conductivity,
The low-k material may be a metal oxide such as Si ₃ N ₄ , SiO ₂ , SiON, or SiOC. The low-k material may be an oxide or nitride of SiO ₂ , Si ₃ N ₄ , Nb ₂ O ₅ , Wherein the high-k material is a metal oxide or a metal nitride such as Ta ₂ O ₅ , TiO ₂ , HfO ₂ , ZrO ₂ , HfSiO ₃ or HfZrO _3, and the low electrical conductivity material is Si ₃ N ₄ , A metal oxide such as SiO ₂ , SiON, SiOC, Ta ₂ O ₅ , TiO ₂ , HfO ₂ , ZrO ₂ , HfSiO ₃ and HfZrO ₃ and a metal nitride, and the low thermal conductivity material is Si ₃ N ₄ , SiO ₂ , SiON , SiOC, Ta ₂ O ₅ , TiO ₂ , HfO ₂ , ZrO ₂ , HfSiO ₃ , HfZrO ₃ and metal nitride. delete delete delete ◈ Claim 25 is abandoned due to registration fee. 22. The phase change memory element of claim 21, wherein the isolation layer is disposed at regular intervals or at specified intervals within the trench. Forming a lower electrode contact over the semiconductor substrate;
Forming a hole through the interlayer insulating film on the lower electrode contact, and depositing a conductive film on the lower portion of the hole to form a lower electrode;
Forming a spacer insulating film on a sidewall of the hole in which the lower electrode is formed;
Forming a separation film in a trench shape in the trench in which the spacer insulation film is formed to prevent elemental volatilization of the phase change material;
Forming a phase change material layer including a plurality of unit phase change material layers separated by the separation layer by filling a phase change material in the trench in which the separation layer is formed; And
Forming an upper electrode over the phase change material layer,
The separation membrane is formed in the phase-change material layer in a plurality of or more than one, to separate the phase-change material layer into a plurality of thin films,
The separation membrane may be formed of a material having a crystallization temperature of 400 ° C or higher, a low-k material or a high-k material, a material having a low electrical conductivity, or a material having a low thermal conductivity,
The low-k material may be a metal oxide such as Si ₃ N ₄ , SiO ₂ , SiON, or SiOC. The low-k material may be an oxide or nitride of SiO ₂ , Si ₃ N ₄ , Nb ₂ O ₅ , Wherein the high-k material is a metal oxide or a metal nitride such as Ta ₂ O ₅ , TiO ₂ , HfO ₂ , ZrO ₂ , HfSiO ₃ , or HfZrO _3, and the low electrical conductivity material is Si ₃ N ₄ , SiO ₂ , SiON, SiOC, Ta ₂ O ₅ , TiO ₂ , HfO ₂ , ZrO ₂ , HfSiO ₃ and HfZrO _3, and the low thermal conductivity material is Si ₃ N ₄ , SiO ₂ , Wherein the metal oxide is a metal oxide such as SiON, SiOC, Ta ₂ O ₅ , TiO ₂ , HfO ₂ , ZrO ₂ , HfSiO ₃ , HfZrO ₃ and metal nitride. delete delete delete ◈ Claim 30 has been abandoned due to registration fee. 27. The method of claim 26, wherein the isolation layer is disposed in the trench at regular intervals or at specified intervals.

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