WO2023272373A1

WO2023272373A1 - Overcurrent detection using a programmable logic device

Info

Publication number: WO2023272373A1
Application number: PCT/CA2022/000028
Authority: WO
Inventors: Michael NEUDORFHOFER; Oliver OBERLEITNER
Original assignee: Magna International Inc.
Priority date: 2021-06-29
Filing date: 2022-06-27
Publication date: 2023-01-05

Abstract

An analog-to-digital converter (ADC) circuit for measuring an analog input signal comprises a comparator including a non-inverting input having a reference value and an inverting input coupled to the analog input signal. The comparator is configured to assert a comparator output based on a comparison between values on the inverting and non-inverting inputs. A sampling element receives a clock signal is configured to hold a first output terminal at a digital logic level of the comparator output in response to receiving each pulse of the clock signal, to provide a high-frequency pulse-width modulated (PWM) signal representing a value of the analog input signal. A programmable logic device (PLD) includes a digital comparator receiving a digital value based on the high-frequency PWM signal, and generating an error signal based on comparing the digital value to one or more error levels.

Description

OVERCURRENT DETECTION USING A PROGRAMMABLE LOGIC DEVICE

CROSS-REFERENCE TO RELATED APPLICATION [0001] This PCT International Patent Application claims the benefit of U.S. Provisional

Patent Application Serial No. 63/216,473 filed on June 29, 2021 titled “Overcurrent Detection Using A Programmable Logic Device,” the entire disclosure of which is hereby incorporated by reference.

FIELD

[0002] The present disclosure relates generally to measurement of isolated voltage signals.

BACKGROUND

[0003] Several different electrical systems may require comparison of a sensor signal against a reference value. In some applications, for example, applications requiring fast response and/or reliable function, this comparison may be done in hardware. One example of such an arrangement is for protecting power switches in an automotive traction drive inverter against over- current.

SUMMARY

[0004] The present disclosure provides an analog-to-digital converter (ADC) circuit for measuring an analog input signal. The ADC circuit comprises: a comparator including a noninverting input having a reference value and an inverting input coupled to the analog input signal and configured to assert an output terminal based on a comparison between values on the inverting input and the non-inverting input; a clock signal having a series of pulses at regular time intervals; a sampling element receiving the clock signal and having an input connected to the output terminal of the comparator and a first output terminal, the sampling element configured to hold the first output terminal at a digital logic level of the input in response to receiving each pulse of the clock signal, the first output terminal providing a pulse-width modulated (PWM) signal representing a value of the analog input signal; and a programmable logic device (PLD) including a digital comparator configured to receive a digital value based on the PWMF signal and to compare the digital value to one or more error levels, the digital comparator further configured to generate an error signal based on the comparison between the digital value and the one or more error levels.

BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Further details, features and advantages of designs of the invention result from the following description of embodiment examples in reference to the associated drawings.

[0006] FIG. 1 shows a schematic diagram of a conventional comparator circuit for determining if a voltage signal is within a window of predetermined values.

[0007] FIG. 2 shows a schematic diagram of an analog-to-digital converter (ADC) circuit, in accordance with an aspect of the present disclosure.

[0008] FIG. 3 shows a block diagram of a digital filter, in accordance with an aspect of the present disclosure.

DETAILED DESCRIPTION

[0009] Referring to the drawings, the present invention will be described in detail in view of following embodiments. The present disclosure provides a comparator circuit to determine if an analog input signal is below a low error value and/or above a high error value.

[0010] As shown in FIG. 1, a conventional comparator circuit 10 is configured to receive an input voltage signal U_in on an analog input terminal 12 and to determine if the input voltage signal U_in is within a window of predetermined values. The predetermined values may correspond to a first reference voltage Urefjop, and a second reference voltage Uref_bot. The first reference voltage U_{ref_ top} may correspond to a highest voltage of a normal operating window, and the second reference voltage Urefjot may correspond to a lowest voltage of a normal operating window. Each of the reference voltages U_{ref_ top}, Urefjot may have fixed values. Alternatively, one or both of the reference voltages U_{ref_ top}, U_{ref_ bot} may have a variable value. Various methods can be used to provide the reference voltages U_{ref_ bop}, U_{ref_ bot}, such as, a resistor voltage divider, a diode, or a precision band-gap voltage reference device. The input voltage signal U_in, and the Zener reference voltages U_{ref_ top}, U_{ref_ bot} may all be referenced to a common signal ground. The input voltage signal Uin may be provided by a current sensor and may correspond to a line current, such as a current provided to a traction motor by a traction drive inverter in a vehicle.

[0011] The conventional comparator circuit 10 includes a first comparator 20 having a first non-inverting input 22, a first inverting input 24, and a first output terminal 26. The first noninverting input 22 is connected to the first reference voltage U_{ref_ bop}, and the first inverting input 24 is connected to the analog input terminal 12. The first comparator 20 may be configured to energize, or to drive the first output terminal 26 to a high logic state in response to determining a voltage on the first non-inverting input 22 being greater than a voltage on the first inverting input 24. The first comparator 20 may include, for example, an operational amplifier (op-amp) device. [0012] The conventional comparator circuit 10 also includes a second comparator 30 having a second non-inverting input 32, a second inverting input 34, and a second output terminal 36. The second non-inverting input 32 is connected to the analog input terminal 12, and the second inverting input 34 is connected to the second reference voltage Urefjot. The second comparator 30 may be configured to energize, or to drive the second output terminal 36 to a high logic state in response to determining a voltage on the second non-inverting input 23 being greater than a voltage on the second inverting input 34. The second comparator 30 may include, for example, an operational amplifier (op-amp) device. [0013] The conventional comparator circuit 10 also includes an AND gate 40 having a first input terminal 42, a second input terminal 44, and an output terminal 46. The first input terminal 42 of the AND gate 40 is connected to the first output terminal 26 of the first comparator 20. The second input terminal 44 of the AND gate 40 is connected to the second output terminal 36 of the second comparator 30. The AND gate 40 may be configured to energize, or to drive the output terminal 46 to a high logic state in response to determining both the input terminals 42, 44 having a high logic condition. An output signal on the output terminal 46 may be used to shutdown current flow through power switches in case the input voltage signal Uin, is outside of the window defined by the reference voltages U_{ref_ top}, U_{ref_ bot}, which may indicate an overcurrent condition.

[0014] Together, the comparators 20, 30, and the AND gate 40 of the conventional comparator circuit 10 function to drive the output terminal 46 to the high logic state if and only if the input voltage signal U_in is within a window of values between the reference voltages Urefjop, U_{ref_ bot}.

[0015] FIG. 2 shows a schematic diagram of an analog-to-digital converter (ADC) circuit

110, in accordance with an aspect of the present disclosure. The ADC circuit 110 includes a Sigma- Delta ADC (SSD ADC) that may be implemented using a combination of internal and external components, including: an analog comparator 140, a low-pass filter 132, 134, a sampling element 150, a two-stage digital filter 170, and a digital comparator 180. In a programmable logic device (PLD), such as a complex programmable logic device (CPLD) or a field-programmable gate array (FPGA) that supports low-voltage differential signaling (LVDS) inputs and/or outputs { I/O}, only the RC network may need to be implemented externally, reducing parts count and cost.

[0016] The ADC circuit 110 includes a resistor-capacitor (RC) network 122 connected to the analog input terminal 12 having a voltage representing an analog input signal. The RC network 122 is also connected to a reference terminal 14 having a fixed reference voltage. Various methods can be used to provide the fixed reference voltage, such as, a resistor voltage divider, a Zener diode, or a precision band-gap voltage reference device. The RC network 122 includes a first resistor 128 connected between the reference terminal 14 and a first intermediate node 124a. The RC network 122 also includes a second resistor 130 connected between the analog input terminal 12 and a second intermediate node 124b. The RC network 122 also includes the low-pass filter 132, 134, which includes a third resistor 132, and a capacitor 134. The third resistor 132 is connected between a feedback conductor 126 and the second intermediate node 124b. The capacitor 134 is connected between a signal ground and the second intermediate node 124b. The low-pass filter 132, 134 may function to pass low-frequency signals from the feedback conductor 126 to the second intermediate node 124b, while blocking higher-frequency signals therebetween. The frequency characteristics of the low-pass filter 132, 134, such as a cutoff frequency, may depend on a resistance value of the third resistor 132, and/or a capacitance value of the capacitor 134.

[0017] The ADC circuit 110 also includes a programmable logic device (PLD) 120, such as a complex programmable logic device (CPLD) or a field-programmable gate array (FPGA). The PLD 120 may be integrated with or separate from a processor configured to receive digital data from the ADC circuit 110 regarding the analog input signal from the analog input terminal

12.

[0018] The ADC circuit 110 includes a comparator 140 having a non-inverting input 142, an inverting input 144 and an output terminal 146. The non-inverting input 142 is connected to the first intermediate node 124a, and the inverting input 144 is connected to the second intermediate node 124b. The comparator 140 may be configured to energize, or to drive the output terminal 146 to a high logic state in response to determining a voltage on the non-inverting input 142 being greater than a voltage on the inverting input 144. The comparator 140 may be implemented in the PLD 120, as shown in FIG. 2. Alternatively, the comparator 140 may include one or more discrete devices, such as an operational amplifier (op-amp) or a discrete comparator device, such as a National Semiconductor LMV311 or equivalent. Alternatively, several CPLD and FPGA devices support LVDS signaling with on-board LVDS input buffers.

[0019] The PLD 120 includes a sampling element 150, such as a flip-flop, having an input terminal 152, and an output terminal 156. The sampling element 150 is connected to a clock signal 154 having a series of pulses at regular time intervals. The clock signal 164 may operate at an over-sampling rate, which may be faster than a sampling rate for sampling the analog input signal on the analog input terminal 12. For example, the over-sampling rate may operate at a frequency that is a multiple of a sampling frequency required to sample the analog input signal.

[0020] The sampling element 150 is configured to transfer a logic value from the input terminal 152 to the output terminal 156 upon each pulse of the clock signal 154 and to hold that logic value on the output terminal 156 until a subsequent pulse of the clock signal 154. The input terminal 152 of the sampling element 150 is connected to the output terminal 146 of the comparator 140, and the output terminal 156 of the sampling element 160 is connected to the feedback conductor 126. The output terminal 156 of the sampling element 160 provides a high-frequency pulse-width modulated (PWM) signal representing a value of the analog input signal on the analog input terminal 12, which can be used for further processing.

[0021] The output of the RC network 122 may represent an average of the PWM signal over a period of time, and is used to accurately track the analog input voltage at the input terminals 142, 144 of the comparator 140. [0022] The PLD 120 also includes a two-stage digital filter 170 to provide basic integration of the PWM signal and some amount of anti-aliasing. The two-stage digital filter 170 includes an input port 172 and an output port 174. The input port 172 of the two-stage digital filter 170 is connected to the output terminal 156 of the sampling element 150 for receiving the high-frequency pulse-width modulated (PWM) signal, therefrom. The two-stage digital filter 170 is detailed in FIG. 3 and discussed, below.

[0023] The PLD 120 also includes a digital comparator 180 having an input port 182 and an error output port 184. The input port 182 of the digital comparator 180 is connected to the output port 174 of the two-stage digital filter 170 and configured to receive a digital value therefrom. The digital comparator 180 may be configured compare the digital value to one or more error levels in order to generate an error signal on the error output port 184. This error levels may be adjusted during operation with any kind of communication through a microcontroller, so functional testing during operation can be done without any additional components.

[0024] Implementing the digital comparator 180 within the PLD 120 may provide for much faster response and higher reliability than implementing similar functionality within a microcontroller. In some embodiments, the digital comparator 180 and other related processing may be considered to be a hardware function, which may satisfy a given standard for functional safety, such as IS026262.

[0025] FIG. 3 shows a block diagram of the two-stage digital filter 170. The two-stage digital filter 170 includes a first stage filter 176, which may include an integrator or accumulator, and which is coupled to the input port 172 for receiving the high-frequency pulse-width modulated (PWM) signal. The first stage filter 176 converts the PWM stream from a 1-bit, high-frequency data stream to a multi-bit, intermediate-frequency data stream 177. [0026] The two-stage digital filter 170 also includes a second stage 178, configured to receive the multi-bit, intermediate-frequency data stream 177 from the first stage filter 176 and to perform an arithmetic average function on the intermediate-frequency data stream 177. The second stage 178 may provide further decimation to the output frequency of the ADC and/or an antialiasing function. The second stage 178 is coupled to the output port 174 of the two-stage digital filter 170 and outputs filtered data thereto, with the filtered data representing a digital value corresponding to the analog input signal on the analog input terminal 12.

[0027] According to an aspect of the disclosure, the sigma delta design of the ADC circuit

110 utilizes a comparator as a 1-bit analog- to-digital converter. This comparator may be a discrete external device or alternatively, several CPLD and FPGA devices support LVDS signaling with on-board LVDS input buffers. These buffers may be very fast analog comparators. While optimized for use within the LVDS specifications, these buffers are very serviceable for use as a 1-bit ADC, especially in conjunction with the RC -Network input topology shown above.

[0028] The Sigma-Delta ADC of the ADC circuit 110 may employ over-sampling. A single flip-flop may be utilized for the sampling element 150 to capture the output of the comparator 140, driven at the over-sampling clock rate, fCLK. The output of the sampling element 150 is a high-frequency pulse-width modulated (PWM) representation of the analog input signal on the analog input terminal 12.

[0029] The foregoing description is not intended to be exhaustive or to limit the disclosure.

Individual elements or features of a particular embodiment are generally not limited to that particular embodiment, but, where applicable, are interchangeable and can be used in a selected embodiment, even if not specifically shown or described. The same may also be varied in many ways. Such variations are not to be regarded as a departure from the disclosure, and all such modifications are intended to be included within the scope of the disclosure.

Claims

CLAIMS What is claimed is:

1. An analog-to-digital converter (ADC) circuit for measuring an analog input signal, comprising: a comparator including a non-inverting input having a reference value, and an inverting input coupled to the analog input signal and configured to assert an output terminal based on a comparison between values on the inverting input and the non-inverting input; a clock signal having a series of pulses at regular time intervals; a sampling element receiving the clock signal and having an input connected to the output terminal of the comparator and a first output terminal, the sampling element configured to hold the first output terminal at a digital logic level of the input in response to receiving each pulse of the clock signal, the first output terminal providing a pulse-width modulated (PWM) signal representing a value of the analog input signal; and a programmable logic device (PLD) including a digital comparator configured to receive a digital value based on the PWM signal and to compare the digital value to one or more error levels, the digital comparator further configured to generate an error signal based on the comparison between the digital value and the one or more error levels.

2. The ADC circuit of claim 1 , wherein the sampling element includes a flip-flop.

3. The ADC circuit of claim 1, wherein the PLD includes the comparator.

4. The ADC circuit of claim 1 , wherein the PLD includes sampling element.

5. The ADC circuit of claim 1. further comprising a field-programmable gate array

(FPGA), the FPGA including the PLD.

6. The ADC circuit of claim 1 , further comprising a low-pass filter connected between the output terminal of the sampling element and the inverting input of the comparator and configured to pass low-frequency signals lfom the sampling element to the inverting input of the comparator, while blocking higher-frequency signals therebetween.

7. The ADC circuit of claim 6, wherein the low-pass filter includes a resistor-capacitor (RC) circuit having a filter resistor and a filter capacitor.

8. The ADC circuit of claim 1 , wherein the reference value of the non-inverting input is a reference voltage.

9. The ADC circuit of claim 8, wherein the reference voltage is a fixed reference voltage.

10. The ADC circuit of claim 9, wherein the fixed reference voltage is generated by a resistor voltage divider.

11. The ADC circuit of claim 9, wherein the fixed reference voltage is generated by a

Zener diode.

12. The ADC circuit of claim 9, wherein the fixed reference voltage is generated by a precision band-gap voltage reference device.

13. The ADC circuit of claim 1, further comprising: a first resistor connected between a reference terminal having a fixed reference voltage and the non-inverting input of the comparator; wherein the analog input signal comprises an analog voltage applied to an analog input terminal; and wherein the ADC circuit further comprises a second resistor connected between the analog input terminal and the inverting input of the comparator.

14. The ADC circuit of claim 1, further comprising a two-stage digital filter located between the first output terminal of the sampling element and the digital comparator and configured to provide at least one of a decimation of the PWM signal and an anti-aliasing function.

15. A traction drive inverter comprising the ADC circuit of claim 1.