WO2023272381A1

WO2023272381A1 - Measurement of isolated signals with a programmable logic device

Info

Publication number: WO2023272381A1
Application number: PCT/CA2022/051029
Authority: WO
Inventors: Michael NEUDORFHOFER; Oliver OBERLEITNER
Original assignee: Magna International Inc.
Priority date: 2021-06-29
Filing date: 2022-06-28
Publication date: 2023-01-05

Abstract

An isolated analog-to-digital converter (ADC) circuit for measuring an analog input signal comprises a comparator including a non-inverting input having a reference value, and an inverting input coupled to the analog input signal and configured to assert an output terminal based on a comparison between values on the inverting input and the non-inverting input. A sampling element has an input terminal coupled to the output terminal of the comparator and a first output terminal, the sampling element is configured to hold the first output terminal at a digital logic level of the input terminal in response to receiving each pulse of a clock signal, the first output terminal providing a high-frequency pulse-width modulated (PWM) signal representing a value of the analog input signal. A digital isolator provides electrical isolation between the output terminal of the comparator and the input terminal of the sampling element.

Description

MEASUREMENT OF ISOLATED SIGNALS WITH A PROGRAMMABLE LOGIC DEVICE

CROSS-REFERENCE TO RELATED APPLICATION [0001] This PCT International Patent Application claims the benefit of U.S. Provisional

Patent Application Serial No. 63/216,291 filed on June 29, 2021 titled “Measurement of Isolated Signals with a Programmable Logic Device,” the entire disclosure of which is hereby incorporated by reference.

FIELD

[0002] The present disclosure relates generally to measurement of isolated electrical signals.

BACKGROUND

[0003] Several different electrical systems may require measurement of a sensor signal by a controller having a different common potential as the sensor signal. An isolated amplifier may provide isolation between the sensor signal and the controller. One example of such an electrical system and sensor is in a high-voltage traction drive inverter for automotive applications.

SUMMARY

[0004] The present disclosure provides an isolated analog-to-digital converter (ADC) circuit for measuring an analog input signal. The isolated ADC circuit comprises: a comparator including a non-inverting input having a reference value, and an inverting input coupled to the analog input signal and configured to assert an output terminal based on a comparison between values on the inverting input and the non-inverting input; a clock signal having a series of pulses at regular time intervals; a sampling element receiving the clock signal and having an input terminal coupled to the output terminal of the comparator and a first output terminal, the sampling element configured to hold the first output terminal at a digital logic level of the input terminal in response to receiving each pulse of the clock signal, the first output terminal providing a high- frequency pulse-width modulated (PWM) signal representing a value of the analog input signal; and a digital isolator providing electrical isolation between the output terminal of the comparator and the input terminal of the sampling element.

BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Further details, features and advantages of designs of the invention result from the following description of embodiment examples in reference to the associated drawings.

[0006] FIG. 1 shows a schematic diagram of a conventional isolator circuit for measuring an isolated input signal.

[0007] FIG. 2 shows a schematic diagram of an isolated analog-to-digital converter (ADC) circuit for measuring an isolated input signal, in accordance with an aspect of the present disclosure.

DETAILED DESCRIPTION

[0008] Referring to the drawings, the present invention will be described in detail in view of following embodiments. The present disclosure provides an isolated ADC circuit to provide conversion of an analog input signal to corresponding digital data, while maintaining electrical isolation therebetween.

[0009] FIG. 1 shows a schematic diagram of a conventional isolator circuit 10 for supplying an isolated input signal to a controller 20 having an analog-to-digital converter (ADC) 22, based on an analog input signal, which may be a voltage applied to an analog input terminal 12. The conventional isolator circuit 10 uses an isolated amplifier 24 to provide electrical isolation between the analog input terminal 12 and the controller 20. The controller 20 may include a microcontroller having the ADC 22 integrated therewith. Alternatively, the ADC 22 may be a separate device configured to provide a digital signal to a separate processor based on the isolated input signal. Such isolated amplifiers 24 can be costly, so other solutions for supplying an isolated input signal to a controller 20 that do not require use of an isolated amplifiers 24 may be beneficial. [0010] The conventional isolator circuit 10 includes an analog input terminal 12 carrying an analog input signal, such as a voltage or current. The analog input terminal 12 may be connected to a sensor and the analog input signal may represent a process value measured by the sensor. For example, the sensor may be a motor current sensor, and the analog input signal may represent a phase current supplied to a traction motor of a vehicle. The isolated amplifier 24 is connected to the analog input terminal 12 and configured to supply an output voltage between a set of intermediate conductors 26a, 26b corresponding to the analog input signal, while providing electrical isolation between the analog input terminal 12 and the intermediate conductors 26a, 26b. [0011] The conventional isolator circuit 10 also includes a filter network 28 connected between the isolated amplifier 24 and the ADC 22 of the controller 20. The filter network 28 includes a first resistor 32 connected between a first intermediate conductor 26a of the intermediate conductors 26a, 26b and a corresponding first input terminal 30a of the ADC 22. The filter network 28 also includes a second resistor 34 connected between a second intermediate conductor 26b of the intermediate conductors 26a, 26b and a corresponding second input terminal 30b of the ADC 22. The filter network 28 also includes a capacitor 36 connected between the first and second input terminals 30a, 30b of the ADC 22.

[0012] FIG. 2 shows a schematic diagram of an isolated ADC circuit 110 for measuring an analog input signal, in accordance with an aspect of the present disclosure. The isolated ADC circuit 110 includes a Sigma-Delta ADC (SSD ADC) that may be implemented using a combination of internal and external components: analog comparator 140, a digital isolator 150, a low-pass filter 132, 134 and a sampling element 160. The SSD ADC utilizes the analog comparator 140 as a 1-bit ADC.

[0013] The isolated ADC circuit 110 includes a resistor-capacitor (RC) network 122 connected to the analog input terminal 12 having a voltage representing an analog input signal. The RC network 122 is also connected to a reference terminal 14 having a fixed reference voltage. Various methods can be used to provide the fixed reference voltage, such as, a resistor voltage divider, a Zener diode, or a precision band-gap voltage reference device. The RC network 122 includes a first resistor 128 connected between the reference terminal 14 and a first intermediate node 124a. The RC network 122 also includes a second resistor 130 connected between the analog input terminal 12 and a second intermediate node 124b. The first resistor 128 and/or the second resistor 130 may function to limit current supplied to the analog comparator 140, which can protect the analog comparator 140 from damage.

[0014] The RC network 122 also includes the low-pass filter 132, 134, which includes a third resistor 132, and a filter capacitor 134. The third resistor 132 is connected between a feedback conductor 126 and the second intermediate node 124b. The filter capacitor 134 is connected between a signal ground and the second intermediate node 124b. The low-pass filter 132, 134 may function to pass low-frequency signals from the feedback conductor 126 to the second intermediate node 124b, while blocking higher-frequency signals therebetween. The frequency characteristics of the low-pass filter 132, 134, such as a cutoff frequency, may depend on a resistance value of the third resistor 132, and/or a capacitance value of the filter capacitor 134. The low-pass filter 132, 134 could have another configuration and/or different constituent components.

[0015] The isolated ADC circuit 110 includes a comparator 140 having a non-inverting input 142, an inverting input 144 and an output terminal 146. The non-inverting input 142 is connected to the first intermediate node 124a, and the inverting input 144 is connected to the second intermediate node 124b. The comparator 140 may be configured to energize, or to drive the output terminal 146 to a high logic state in response to determining a voltage on the non inverting input 142 being greater than a voltage on the inverting input 144. The comparator 140 may include, for example, an operational amplifier (op-amp) device.

[0016] The isolated ADC circuit 110 also includes a digital isolator 150 having a first input terminal 152, a first output terminal 154, a second input terminal 156, and a second output terminal 158. The first input terminal 152 is connected to the output terminal 146 of the comparator 140, and the second output terminal 158 is connected to the feedback conductor 126. The digital isolator 150 is configured to provide a digital logic level (i.e., a high or low voltage signal) upon the first output terminal 154 corresponding to a digital logic level applied to the first input terminal 152, while providing electrical isolation therebetween. The digital isolator 150 is also configured to provide a digital logic level (i.e., a high or low voltage signal) upon the second output terminal 158 corresponding to a digital logic level applied to the second input terminal 156, while providing electrical isolation therebetween.

[0017] The digital isolator 150 may be configured with two or more channels, with the first input terminal 152 and the first output terminal 154 being associated with a first channel, and with the second input terminal 156 and the second output terminal 158 being associated with a second channel. Alternatively, two or more independent devices may be used to implement the different channels of the digital isolator 150.

[0018] The isolated ADC circuit 110 also includes a programmable logic device (PLD)

120, such as a complex programmable logic device (CPLD) or a field-programmable gate array (FPGA). The PLD 120 may be integrated with or separate from a processor configured to receive digital data from the isolated ADC circuit 110 regarding the analog input signal from the analog input terminal 12. The PLD 120 includes a sampling element 160, such as a flip-flop, and which has an input terminal 162, a first output terminal 166, and a second output terminal 168. The sampling element 160 is connected to a clock signal 164 having a series of pulses at regular time intervals. The clock signal 164 may operate at an over-sampling rate, which may be faster than a sampling rate for sampling the analog input signal on the analog input terminal 12. For example, the over-sampling rate may operate at a frequency that is a multiple of a sampling frequency required to sample the analog input signal.

[0019] The sampling element 160 is configured to transfer a logic value from the input terminal 162 to the first output terminal 166 upon each pulse of the clock signal 164 and to hold that logic value on the first output terminal 166 until a subsequent pulse of the clock signal 164. The input terminal 162 of the sampling element 160 is connected to the first output terminal 154 of the digital isolator 150, and the first output terminal 166 of the sampling element 160 is connected to the second input terminal 156 of the digital isolator 150 for use as a feedback signal to be provided to the low-pass filter 132, 134 of the RC network 122. The first output terminal 166 of the sampling element 160 provides a high-frequency pulse-width modulated (PWM) signal representing a value of the analog input signal on the analog input terminal 12, which can also be used for further processing.

[0020] The output of the RC network 132, 134 may represent an average of the PWM signal over a period of time, and is used to accurately track the analog input voltage at the input terminals 142, 144 of the comparator 140.

[0021] The isolated ADC circuit 110 may be especially useful for designs that already include a PLD 120, such as an FPGA or CPLD, which can be expanded to measure isolated signals. The isolated ADC circuit 110 may provide a significant cost savings over the conventional isolator circuit 10, especially in systems that already include a PLD 120. The isolated ADC circuit 110 may require only addition of an analog comparator 140 and digital isolators 150.

[0022] The foregoing description is not intended to be exhaustive or to limit the disclosure.

Individual elements or features of a particular embodiment are generally not limited to that particular embodiment, but, where applicable, are interchangeable and can be used in a selected embodiment, even if not specifically shown or described. The same may also be varied in many ways. Such variations are not to be regarded as a departure from the disclosure, and all such modifications are intended to be included within the scope of the disclosure.

Claims

CLAIMS What is claimed is:

1. An isolated analog-to-digital converter (ADC) circuit for measuring an analog input signal, comprising: a comparator including a non-inverting input having a reference value, and an inverting input coupled to the analog input signal and configured to assert an output terminal based on a comparison between values on the inverting input and the non-inverting input; a clock signal having a series of pulses at regular time intervals; a sampling element receiving the clock signal and having an input terminal coupled to the output terminal of the comparator and a first output terminal, the sampling element configured to hold the first output terminal at a digital logic level of the input terminal in response to receiving each pulse of the clock signal, the first output terminal providing a high-frequency pulse-width modulated (PWM) signal representing a value of the analog input signal; and a digital isolator providing electrical isolation between the output terminal of the comparator and the input terminal of the sampling element.

2. The isolated ADC circuit of claim 1, wherein the sampling element includes a flip- flop.

3. The isolated ADC circuit of claim 1, further comprising a programmable logic device (PLD), the PLD including the sampling element.

4. The isolated ADC circuit of claim 1, further comprising a field-programmable gate array (FPGA), the FPGA including the sampling element.

5. The isolated ADC circuit of claim 1, further comprising a low-pass filter coupled between the output terminal of the sampling element and the inverting input of the comparator and configured to pass low-frequency signals from the sampling element to the inverting input of the comparator, while blocking higher-frequency signals therebetween.

6. The isolated ADC circuit of claim 5, further comprising a second digital isolator providing electrical isolation between the output terminal of the sampling element and the low- pass filter.

7. The isolated ADC circuit of claim 5, wherein the low-pass filter includes a resistor- capacitor (RC) circuit having a filter resistor and a filter capacitor.

8. The isolated ADC circuit of claim 1, wherein the reference value of the non inverting input is a reference voltage.

9. The isolated ADC circuit of claim 8, wherein the reference voltage is a fixed reference voltage.

10. The isolated ADC circuit of claim 9, wherein the fixed reference voltage is generated by a resistor voltage divider.

11. The isolated ADC circuit of claim 9, wherein the fixed reference voltage is generated by a Zener diode.

12. The isolated ADC circuit of claim 9, wherein the fixed reference voltage is generated by a precision band-gap voltage reference device.

13. The isolated ADC circuit of claim 1, further comprising a first resistor connected between a reference terminal having a fixed reference voltage and the non-inverting input of the comparator.

14. The isolated ADC circuit of claim 1, wherein the analog input signal comprises an analog voltage applied to an analog input terminal; and wherein the isolated ADC circuit further comprises a second resistor connected between the analog input terminal and the inverting input of the comparator.

15. A traction drive inverter comprising the isolated ADC circuit of claim 1.