WO2023246039A1 - 子像素电路 - Google Patents

子像素电路 Download PDF

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Publication number
WO2023246039A1
WO2023246039A1 PCT/CN2022/140930 CN2022140930W WO2023246039A1 WO 2023246039 A1 WO2023246039 A1 WO 2023246039A1 CN 2022140930 W CN2022140930 W CN 2022140930W WO 2023246039 A1 WO2023246039 A1 WO 2023246039A1
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WO
WIPO (PCT)
Prior art keywords
thin film
film transistor
voltage
sub
electrode
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PCT/CN2022/140930
Other languages
English (en)
French (fr)
Inventor
陈书志
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上海闻泰电子科技有限公司
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Publication of WO2023246039A1 publication Critical patent/WO2023246039A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters
    • G09G2320/0626—Adjustment of display parameters for control of overall brightness
    • G09G2320/064—Adjustment of display parameters for control of overall brightness by time modulation of the brightness of the illumination source

Definitions

  • This disclosure relates to subpixel circuits.
  • Micro LED technology is a technology that miniaturizes and matrixes light-emitting diodes (LEDs).
  • Micro LED displays have many advantages such as high display brightness, short response time, and low power consumption. They are also self-luminous and do not require a backlight. The characteristics are the mainstream trend of future display technology and have good development prospects.
  • Micro LED displays mainly use active drive design, but uneven brightness occurs when displaying low gray levels.
  • the existing technology mainly improves the problem of uneven brightness by reducing the driving voltage when displaying low gray levels. However, this method will cause some gray levels to be lost, resulting in poor display.
  • a subpixel circuit is provided.
  • An embodiment of the present disclosure discloses a sub-pixel circuit.
  • the sub-pixel circuit includes a passive drive circuit, an internal compensation circuit, and a light-emitting diode; the passive drive circuit is connected to the internal compensation circuit, and the light-emitting diode is connected to the internal compensation circuit.
  • the internal compensating circuit includes a first data writing interface; the first data writing interface is used to write the first data voltage; the passive driving circuit includes a second data writing interface and a frequency sweep signal Input interface; the second data writing interface is used to write the second data voltage, the frequency sweep signal input interface is used to receive the frequency sweep signal; the passive driving circuit is used to operate according to the second data voltage and The frequency sweep signal changes the voltage of the connection point between the passive driving circuit and the internal compensation circuit; the internal compensation circuit is used to conduct or cut off the first data write according to the voltage of the connection point.
  • a path between the input interface and the light-emitting diode when the path is turned on, the light-emitting diode emits light driven by the first data voltage; when the path is cut off, the light-emitting diode goes out.
  • the passive driving circuit further includes a ninth thin film transistor; the first electrode of the ninth thin film transistor is connected to the connection point, and the second electrode of the ninth thin film transistor is connected to the connection point.
  • the electrode is used to receive the input of the power supply voltage; the gate of the ninth thin film transistor is connected to the second data writing interface and the frequency sweep signal input interface respectively; the gate voltage of the ninth thin film transistor is in the The second data voltage changes under the coupling with the sweep signal; the ninth thin film transistor is configured to turn off when the gate voltage is higher than the turn-on voltage of the ninth thin film transistor; when the ninth thin film transistor When the thin film transistor is turned off, the voltage at the connection point is the first voltage; the internal compensation circuit is used to turn on the first data writing interface when the voltage at the connection point is the first voltage.
  • the ninth thin film transistor is used to turn on when the gate voltage is lower than the turn-on voltage of the ninth thin film transistor; when the ninth thin film transistor turns on, the The voltage of the connection point is the power supply voltage; the power supply voltage is higher than the first voltage; the internal compensation circuit is used to cut off the third voltage when the voltage of the connection point is the power supply voltage.
  • the passive driving circuit further includes a tenth thin film transistor and a second capacitor;
  • the second data writing interface includes a first electrode of the tenth thin film transistor, so The second electrode of the tenth thin film transistor is connected to the gate electrode of the ninth thin film transistor; one end of the second capacitor is connected to the second electrode of the tenth thin film transistor and the gate electrode of the ninth thin film transistor respectively;
  • the frequency sweep signal input interface includes the other end of the second capacitor.
  • the passive driving circuit further includes an eleventh thin film transistor; the internal compensation circuit further includes a sixth thin film transistor; the first electrode of the eleventh thin film transistor One end of the second capacitor is connected to the second electrode of the tenth thin film transistor, and the second electrode of the eleventh thin film transistor is connected to the first electrode of the sixth thin film transistor.
  • the gate electrode of the thin film transistor is connected to the gate electrode of the sixth thin film transistor; the second electrode of the sixth thin film transistor is connected to the connection point between the passive driving circuit and the internal compensation circuit.
  • the sub-pixel circuit is connected to a controller; the controller is configured to input the first data voltage and the second data voltage to the sub-pixel circuit. and the sweep signal.
  • the controller is connected to a plurality of sub-pixel circuits respectively; the controller is configured to write to the second data interface of each sub-pixel circuit respectively. Write a different second data voltage.
  • the first data writing interfaces of each of the sub-pixel circuits are connected to each other; the controller is configured to write the first data to each of the sub-pixel circuits at the same time.
  • the interface writes the first data voltage.
  • the passive driving circuit further includes a twelfth thin film transistor; the first electrode of the ninth thin film transistor is also connected to the first electrode of the twelfth thin film transistor. ;
  • the second electrode and gate of the twelfth thin film transistor are respectively connected to the controller; the controller is used to cut off the path between the passive drive circuit and the internal compensation circuit, and The frequency sweep signal is maintained at a fixed level; the controller is also configured to detect the flow through the ninth thin film transistor and the second electrode of the twelfth thin film transistor when the light emitting diode is turned off.
  • the current of the twelfth thin film transistor is adjusted, and the second data voltage written to the second data writing interface is adjusted according to the current.
  • the controller is configured to write to The second data voltage of the second data writing interface is increased to a preset voltage value.
  • the sub-pixel circuit further includes an eighth thin film transistor; the passive driving circuit is connected to the first electrode of the eighth thin film transistor, and the internal compensation circuit is connected to the first electrode of the eighth thin film transistor.
  • the controller is configured to input a control signal to the second electrode and gate of the twelfth thin film transistor when the light-emitting diode is turned off. After the twelfth thin film transistor is turned on according to the control signal, the controller detects the current flowing through the ninth thin film transistor and the twelfth thin film transistor to detect the current driving capability of the ninth thin film transistor.
  • the path between the first data writing interface and the light-emitting diode includes a fifth thin film transistor; the fifth thin film transistor is used to receive an enable signal, The switch state is switched according to the enable signal.
  • the enable signal causes the gate voltage of the fifth thin film transistor to be lower than the turn-on voltage, the fifth thin film transistor is turned on.
  • the sub-pixel circuit further includes a first thin film transistor, the first electrode of the first thin film transistor is connected to the first data writing interface for controlling when Write the first data voltage to the first data writing interface.
  • a plurality of the sub-pixel circuits are connected to a controller; the controller is configured to write different data to the second data writing interface of each of the sub-pixel circuits respectively. of the second data voltage.
  • the first data writing interfaces of multiple sub-pixel circuits are connected to each other; and the controller is configured to simultaneously write data to the first data writing interfaces of each sub-pixel circuit.
  • the first data writing interface writes the first data voltage.
  • Figure 1 is a structural block diagram of a sub-pixel circuit provided by the prior art
  • Figure 2 is a structural block diagram of a sub-pixel circuit provided by one or more embodiments of the present disclosure
  • Figure 3 is a structural block diagram of another sub-pixel circuit provided by one or more embodiments of the present disclosure.
  • Figure 4 is a structural block diagram of another sub-pixel circuit provided by one or more embodiments of the present disclosure.
  • Figure 5 is a structural block diagram of another sub-pixel circuit in one or more embodiments of the present disclosure.
  • Figure 6 is a structural block diagram of a display panel in one or more embodiments of the present disclosure.
  • Figure 7 is a schematic diagram of the process of changing the light emitting duration of a sub-pixel by a passive driving circuit in one or more embodiments of the present disclosure
  • Figure 8 is a schematic diagram of driving signals within one frame of a display panel provided by one or more embodiments of the present disclosure
  • FIG. 9 is a schematic diagram of driving signals within one frame of another display panel provided by one or more embodiments of the present disclosure.
  • FIG. 1 is a schematic structural diagram of a sub-pixel circuit in the prior art.
  • the sub-pixel circuit has a 7T1C structure and is an internal compensation circuit.
  • the 7T1C structure is composed of 7 thin film transistors (TFTs) and 1 storage capacitor.
  • the sub-pixel circuit includes a first thin film transistor 101, a second thin film transistor 102, a third thin film transistor 103, a fourth thin film transistor 104, a fifth thin film transistor 105, a sixth thin film transistor 106, a seventh thin film transistor 107, and a light emitting diode 203 , the first capacitor 109.
  • the thin film transistor is a voltage-type switching device.
  • the thin film transistor includes 3 electrodes, namely source, drain and gate. When the gate voltage of the thin film transistor is greater than the turn-on voltage of the thin film transistor, the source and drain will be connected; when the gate voltage of the thin film transistor is less than the turn-on voltage of the thin film transistor, the source and drain will be cut off.
  • Each sub-pixel circuit includes a light-emitting diode 203, that is, a Micro LED.
  • Micro LED displays generally adopt active drive designs, they will comply with the gamma2.2 standard for displaying colors ranging from 0 to 255 gray levels.
  • the formula for Gamma2.2 is:
  • L is the brightness of the sub-pixel
  • L255 is the gray-scale value of the sub-pixel under the 255-level gray level (i.e., the maximum gray level)
  • L is the gray-scale value under the i gray level
  • i can be in the range of 0 to 255 an integer
  • gamma is 2.2.
  • Gamma2.2 is the best value for human eyes to perceive brightness. Therefore, Micro LED displays a 255-level gray-scale color that conforms to the brightness-current (LI) curve of gamma2.2, which is the curve of the LED chip driving current versus brightness.
  • LI brightness-current
  • Micro LEDs with active drive design will have uneven brightness when displaying low gray levels (such as 0 to 32 gray levels), the main reason is that the LI curve of Micro LED is too steep, resulting in low gray levels when displaying low gray levels.
  • the non-uniformity in brightness is caused by the non-uniformity of the first data voltage and the electrical properties of the TFT device.
  • the data line voltage that drives the display panel to emit light is usually reduced when displaying low gray scale, and affects the current flowing through the TFT device to limit the passing current of Micro LED.
  • the current flowing through the Micro LED becomes smaller, the Micro LED emits light with lower brightness.
  • This method of controlling the brightness of the light through an active device can be called a display driver for active devices.
  • the Micro LED display is a current-type driven light-emitting display unit, it is different from the liquid crystal voltage-type drive. Current-type control needs to control the passing current of the TFT to control the passing current of the Micro LED.
  • the data line voltage that drives the display panel to emit light is relatively small and changes within a minimum unit voltage range. Therefore, in this case, the brightness difference of Micro LED due to the difference in current is not obvious. As a result, some grayscales cannot be displayed and are lost.
  • the disclosed embodiment discloses a sub-pixel circuit that can solve the problems of gray scale loss and poor display when Micro LED displays display low gray scales. Each is explained in detail below.
  • Micro LED can be an LED chip with a size less than 50 microns ( ⁇ m)*50 ⁇ m, a thickness of about 7-10 ⁇ m, and no sapphire substrate.
  • FIG. 2 is a schematic structural diagram of a sub-pixel circuit disclosed in an embodiment of the present disclosure.
  • the sub-pixel circuit includes a passive drive circuit 201, an internal compensation circuit 202, and a light-emitting diode 203; the passive drive circuit 201 is connected to the internal compensation circuit 202, and the light-emitting diode 203 is connected to the internal compensation circuit 202;
  • the internal compensation circuit 202 includes a first data writing interface 204; the first data writing interface 204 is used to write the first data voltage; the passive driving circuit 201 includes a second data writing interface 206 and a sweep signal input interface 205; The second data writing interface 206 is used to write the second data voltage, and the frequency sweep signal input interface 205 is used to receive the frequency sweep signal;
  • the passive driving circuit 201 is used to change the voltage of the connection point 207 between the passive driving circuit 201 and the internal compensation circuit 202 according to the second data voltage and the frequency sweep signal;
  • the internal compensation circuit 202 is used to conduct or cut off the path 208 between the first data writing interface 204 and the light-emitting diode 203 according to the voltage of the connection point 207; when the path 208 is turned on, the light-emitting diode 203 is at the first data voltage. It emits light when driven by; when the path 208 is cut off, the light-emitting diode 203 goes out.
  • the internal compensation circuit 202 can be a sub-pixel circuit as shown in FIG. 1, and the circuit structure is 7T1C, which is not specifically limited.
  • the first data voltage and the second data voltage are data line voltages that drive the display panel to emit light. Different data line voltages correspond to different brightnesses of the display panel.
  • the first data writing interface 204 may be a circuit interface used for reset, compensation, and writing in the internal compensation circuit 202, and may be used for writing the first data voltage.
  • the first data writing interface 204 can also be a port of an electronic device such as a switch or a transistor.
  • the electronic device such as a switch or a transistor can control when to write the first data voltage.
  • the first data voltage can adjust the brightness of the light-emitting diode 203; the first data voltage can be 2 volts (V) to 6V, and is not specifically limited.
  • the light-emitting diode 203 may be a Micro LED with a size of about 50 micrometers ( ⁇ m)*50 ⁇ m.
  • the path 208 between the first data writing interface 204 and the light-emitting diode 203 may include a voltage-driven device, such as a field effect transistor (MOSFET), an insulated gate bipolar transistor (IGBT), etc., which are not specifically limited. Therefore, the path 208 The conduction state can be determined based on the voltage at the connection point 207 between the passive drive circuit and the internal compensation circuit. The conductive state of the path 208 determines the light-emitting state of the light-emitting diode 203.
  • a voltage-driven device such as a field effect transistor (MOSFET), an insulated gate bipolar transistor (IGBT), etc.
  • the second data voltage may be a data line voltage that drives the display panel to emit light.
  • the second data voltage may affect the light-emitting brightness of the light-emitting diode 203; the second data voltage may be 2 volts (V) to 6V, specifically Not limited.
  • the frequency sweep signal can be a signal whose frequency changes linearly within a limited range.
  • the frequency sweep signal can be coupled with the second data voltage to obtain a variable voltage. Therefore, the passive driving circuit 201 outputs the signal to the frequency sweep signal according to the second data voltage and the frequency sweep signal.
  • the voltage of the internal compensation circuit 202 is variable, and the passive driving circuit 201 can change the voltage of the connection point 207 so that the internal compensation circuit 202 controls the light-emitting state of the light-emitting diode 203 according to the voltage of the connection point 207 .
  • the passive driving circuit 201 can indirectly control when the light-emitting diode 203 emits light and when it goes out by changing the voltage of the connection point 207, and therefore can control the light-emitting time of the light-emitting diode.
  • the sub-pixel circuit of the embodiment of the present disclosure introduces a passive drive circuit, so that the internal compensation circuit can switch the light-emitting state of the light-emitting diode according to the second data voltage and frequency sweep signal input to the passive drive circuit, so that the sub-pixel circuit can switch the light-emitting state according to the second data voltage and frequency sweep signal input to the passive drive circuit.
  • Different grayscale display requirements control the emitting time of the light-emitting diode, thereby improving the brightness uniformity of the display when displaying low grayscales, and at the same time solving the problems of grayscale loss and poor display when displaying low grayscales.
  • FIG. 3 is a schematic structural diagram of another sub-pixel circuit disclosed in an embodiment of the present disclosure.
  • the passive driving circuit 201 also includes a ninth thin film transistor 301; a first electrode of the ninth thin film transistor 301 is connected to the connection point 207, and a second electrode of the ninth thin film transistor 301 is used to receive the input of the power supply voltage; a gate of the ninth thin film transistor 301 The gate electrodes of the ninth thin film transistor 301 change under the coupling of the second data voltage and the frequency sweep signal.
  • Thin film transistor is an insulated gate field effect transistor, which can be divided into n-type TFT and p-type TFT.
  • Each thin film transistor used in the embodiment of the present disclosure is a p-type TFT.
  • the working principle of a p-type TFT is: when the gate voltage of the thin film transistor is less than the turn-on voltage of the thin film transistor, the thin film transistor turns on; when the gate voltage of the thin film transistor When the voltage is greater than the turn-on voltage of the thin film transistor, the thin film transistor is cut off.
  • the turn-on voltage of the thin film transistor is the device parameter of the thin film transistor, which is the gate voltage when the source and drain of the thin film transistor are just turned on.
  • the first electrode and the second electrode of the ninth thin film transistor 301 may respectively represent the source electrode and the drain electrode of the ninth thin film transistor 301.
  • the first electrode and the second electrode of each thin film transistor in the embodiment of the present disclosure may respectively represent the source electrode and the drain electrode of the thin film transistor. Which one of the first electrode and the second electrode is the source electrode and which one is the drain electrode is not specifically limited.
  • the second electrode of the ninth thin film transistor 301 is used to receive the input of a power supply voltage, where the power supply voltage may be 3.3 volts or 5 volts, and is not specifically limited.
  • the ninth thin film transistor 301 is used to turn off when the gate voltage is higher than the turn-on voltage of the ninth thin film transistor 301; when the ninth thin film transistor 301 turns off, the voltage of the connection point 207 is the first voltage.
  • the internal compensation circuit 202 is used to conduct the path 208 between the first data writing interface 204 and the light-emitting diode 203 when the voltage of the connection point 207 is the first voltage.
  • the ninth thin film transistor 301 is used to turn on when the gate voltage is lower than the turn-on voltage of the ninth thin film transistor 301; when the ninth thin film transistor 301 is turned on, the voltage of the connection point 207 is the power supply voltage; the power supply voltage is higher than the first voltage .
  • the gate voltage of the ninth thin film transistor 301 may be a voltage coupled to the second data voltage and the sweep signal, the coupled voltage is variable, and the voltage value gradually decreases starting from the second data voltage.
  • the second data voltage is 4V
  • the voltage coupled between the second data voltage and the sweep signal gradually decreases from 4V, that is, the gate voltage of the ninth thin film transistor 301 gradually decreases from 4V.
  • the turn-on voltage of the transistor 301 is 0.8V.
  • the first voltage may be a low level lower than 0.5V, and is not specifically limited.
  • the ninth thin film transistor 301 When the gate voltage of the ninth thin film transistor 301 is reduced below the turn-on voltage, the ninth thin film transistor 301 is turned on, and the second electrode of the ninth thin film transistor 301 can receive the input of the power supply voltage. At this time, the voltage of the connection point 207 will be Pull it to the same voltage as the power supply voltage, that is, the voltage at the connection point 207 is the power supply voltage.
  • the power supply voltage can be a high level higher than 3V, and there is no specific limit.
  • the internal compensation circuit 202 is used to cut off the path 208 between the first data writing interface 204 and the light-emitting diode 203 when the voltage of the connection point 207 is the power supply voltage.
  • the internal compensation circuit 202 can conduct the path 208 between the first data writing interface 204 and the light-emitting diode 203 .
  • the internal compensation circuit 202 can control the switching device on the path 208 by inputting a control signal to control the conduction or interruption of the path 208.
  • the internal compensation circuit 202 can be controlled by a voltage-driven device on the path 208. The path 208 is turned on or off.
  • the voltage-driven device can be closed when the voltage of the connection point 207 is the first voltage, and opened when the voltage of the connection point 207 is the power supply voltage.
  • the passive driving circuit switches the working state of the ninth thin film transistor through the second data voltage and the frequency sweep signal, so that the internal compensation circuit can flexibly control the light emitting diode directly according to the working state of the ninth thin film transistor.
  • the light-emitting state so the sub-pixel circuit can control the light-emitting time of the light-emitting diode according to different gray-scale display requirements, thereby improving the brightness uniformity of the Micro LED display when displaying low gray-scale, and at the same time solving the gray-scale problems that occur when displaying low gray-scale. Missing and poor display issues.
  • the sub-pixel circuit is connected to the controller 303; the controller 303 is used to input the first data voltage, the second data voltage and the frequency sweep signal to the sub-pixel circuit.
  • the controller 303 may be a central processing unit (CPU) of an electronic device such as a mobile phone, a computer, or a television, and is not specifically limited.
  • the controller 303 can input the first data voltage, the second data voltage and the frequency sweep signal to the sub-pixel circuit in the display panel of the electronic device to switch the light-emitting state of the light-emitting diode in the sub-pixel circuit, thereby adjusting the brightness, color, etc. of the display panel. parameter.
  • the passive driving circuit 201 also includes a twelfth thin film transistor 302; the first electrode of the ninth thin film transistor 301 is also connected to the first electrode of the twelfth thin film transistor 302; the second electrode and the gate electrode of the twelfth thin film transistor 302 are respectively Connected to controller 303.
  • the controller 303 is used to cut off the path between the passive driving circuit 201 and the internal compensation circuit 202 and maintain the frequency sweep signal at a fixed level.
  • the controller 303 cuts off the path between the passive driving circuit 201 and the internal compensation circuit 202. At this time, the light-emitting diode 203 goes out and maintains the frequency sweep signal at a fixed level, that is, the frequency sweep signal will not affect the third The two data voltages produce a coupling effect.
  • the controller 303 is also configured to detect the current flowing through the ninth thin film transistor 301 and the twelfth thin film transistor 302 through the second electrode of the twelfth thin film transistor 302 when the light-emitting diode 203 is turned off, and adjust the writing to A second data voltage of the second data write interface 206 .
  • the second electrode and gate of the twelfth thin film transistor 302 may be used to receive a control signal sent by the controller 303 to switch the switch state.
  • the controller 303 is configured to increase the second data voltage written to the second data writing interface 206 to the preset voltage when the current flowing through the ninth thin film transistor 301 and the twelfth thin film transistor 302 is less than the current preset value. Set value.
  • the controller 303 When the light-emitting diode 203 turns off, the controller 303 inputs a control signal to the second electrode and the gate of the twelfth thin film transistor 302. After the twelfth thin film transistor 302 is turned on according to the control signal, the controller 303 detects the flow through the ninth thin film.
  • the currents of the transistor 301 and the twelfth thin film transistor 302 are used to detect the current driving capability of the ninth thin film transistor 301.
  • the current preset value may be a current value used to ensure that the ninth thin film transistor 301 is at the optimal current driving capability.
  • the second data voltage used to drive the ninth thin film transistor 301 is less than the preset voltage value.
  • the second data voltage can be increased to the preset voltage value.
  • the ninth thin film transistor 301 may cause voltage losses such as driving loss and conduction loss due to the switching of working states and changes in current. Therefore, by introducing the twelfth thin film transistor 301 The transistor 302 detects the current driving capability of the ninth thin film transistor 301 every time the light-emitting diode 203 is turned off, and feedbacks and compensates the second data voltage written into the second data writing interface 206, which can effectively improve the Subpixel circuit stability.
  • FIG. 4 is a schematic structural diagram of another sub-pixel circuit disclosed in an embodiment of the present disclosure.
  • the sub-pixel circuit also includes an eighth thin film transistor 401; the passive driving circuit 201 is connected to the first electrode of the eighth thin film transistor 401, and the internal compensation circuit 202 is connected to the second electrode of the eighth thin film transistor 401; the passive driving circuit 201 and the internal compensation type
  • the connection point of the circuit 202 includes the connection point between the second electrode of the eighth thin film transistor 401 and the internal compensation circuit 202; the gate electrode of the eighth thin film transistor 401 is used to receive the control signal; the eighth thin film transistor 401 switches different modes according to the control signal. switch status;
  • the path between the passive driving circuit 201 and the internal compensation circuit 202 is in a conductive state, and the light-emitting diode 203 emits light;
  • the switching state of the eighth thin film transistor 401 When the switching state of the eighth thin film transistor 401 is in the off state, the path between the passive driving circuit 201 and the internal compensation circuit 202 is in a cut-off state, and the light-emitting diode 203 is extinguished.
  • the gate of the eighth thin film transistor 401 can be used to receive a control signal sent by the controller for controlling the switching state of the eighth thin film transistor.
  • the eighth thin film transistor 401 can switch between the on state and the off state according to the control signal.
  • the light emitting diode 203 can be switched between lighting and extinguishing according to the switching state of the eighth thin film transistor 401.
  • the eighth thin film transistor 401 is in the on state, which means that the current between the first electrode and the second electrode of the eighth thin film transistor 401 can be conducted; the eighth thin film transistor 401 is in the off state, which means that the eighth thin film transistor 401 is in the off state. No current passes between the first electrode and the second electrode of the thin film transistor 401 .
  • the eighth thin film transistor 401 and the ninth thin film transistor 301 can jointly control the light emitting diode to emit light or extinguish it.
  • the eighth thin film transistor 401 is in the on state and the ninth thin film transistor 301 is in the off state, the light emitting diode 203 emits light; when the eighth thin film transistor 401 is in the on state and the ninth thin film transistor 301 is also in the on state, the light emitting diode 203 goes out. .
  • the light-emitting process of the light-emitting diode 203 is as follows: the eighth thin film transistor 401 is turned on, and the second data voltage causes the gate voltage of the ninth thin film transistor 301 to be higher than the turn-on voltage. Therefore, the ninth thin film transistor 301 is turned off, and the passive driving circuit 201 communicates with the internal
  • the voltage of the connection point 207 of the compensation circuit 202 is the first voltage, the path 208 is turned on, and the light-emitting diode 203 starts to emit light; the second data voltage is coupled with the frequency sweep signal, causing the gate voltage of the ninth thin film transistor 301 to continuously decrease.
  • the ninth thin film transistor 301 When the gate voltage of the ninth thin film transistor 301 is lower than the turn-on voltage, the ninth thin film transistor 301 is turned on, and the voltage of the connection point 207 of the passive driving circuit 201 and the internal compensation circuit 202 is pulled to the same voltage as the power supply voltage, that is, connected The voltage at point 207 is the power supply voltage, the path 208 is cut off, and the light-emitting diode 203 goes out.
  • the eighth thin film transistor 401 is equivalent to a master control switch, which determines the conduction state between the passive driving circuit 201 and the internal compensation circuit 202 and determines whether the light-emitting diode 203 can emit light; when the eighth thin film transistor 401 is turned on Under the premise of the status, the ninth thin film transistor 301 is used to control the lighting duration of the light-emitting diode 203 and determines when the light-emitting diode 203 will go out.
  • the passive driving circuit 201 also includes a tenth thin film transistor 402 and a second capacitor 403;
  • the second data writing interface 206 includes a first electrode of the tenth thin film transistor 402, and the second electrode of the tenth thin film transistor 402 is connected to the ninth thin film transistor 301
  • the gate electrode of the second capacitor 403 is connected to the second electrode of the tenth thin film transistor 402 and the gate electrode of the ninth thin film transistor 301 respectively;
  • the frequency sweep signal input interface 205 includes the other end of the second capacitor 403 .
  • the second data writing interface 206 includes a first electrode of the tenth thin film transistor 402 , and the first electrode of the tenth thin film transistor 402 may be used to receive the written second data voltage.
  • the gate of the tenth thin film transistor 402 can be used to receive a control signal input from the controller, and the tenth thin film transistor 402 switches the switch state according to the control signal.
  • the tenth thin film transistor 402 may control when to receive the written second data voltage based on different switching states.
  • the other end of the second capacitor 403 can be used to receive the input frequency sweep signal, and the second capacitor 403 can be used to store the frequency sweep signal.
  • the passive driving circuit 201 further includes an eleventh thin film transistor 404; the internal compensation circuit 202 further includes a sixth thin film transistor 106; the first electrode of the eleventh thin film transistor 404 is respectively connected to one end of the second capacitor 403 and the tenth thin film transistor 402.
  • the second electrode of the eleventh thin film transistor 404 is connected to the first electrode of the sixth thin film transistor 106, and the gate of the eleventh thin film transistor 404 is connected to the gate of the sixth thin film transistor 106; the sixth thin film
  • the second electrode of the transistor 106 is connected to the connection point between the passive driving circuit 201 and the internal compensation circuit 202 .
  • the path connected between the eleventh thin film transistor 404 and the sixth thin film transistor 106 allows an additional current path between the passive driving circuit 201 and the internal compensation circuit 202.
  • the eighth thin film transistor 401 is turned on and the ninth thin film transistor 201 When turned off, the internal compensation circuit 202 can receive current from the passive driving circuit 201, and the brightness of the light-emitting diode 203 is not only affected by the first data voltage but also by the second data voltage.
  • the embodiments of the present disclosure can drive the light-emitting diode to emit light through the internal compensation circuit and the passive driving circuit when the display panel displays low gray scale, change the luminous brightness of the light-emitting diode through the internal compensation circuit, and change the luminescence through the passive driving circuit.
  • the emitting time of the diode can improve the brightness uniformity of the Micro LED display when displaying low gray levels, and at the same time solve the problems of gray level loss and poor display when displaying low gray levels.
  • FIG. 5 is a schematic structural diagram of another sub-pixel circuit disclosed in an embodiment of the present disclosure.
  • the sub-pixel circuit has a 12T2C structure and includes 12 thin film transistors and 2 capacitors.
  • Each thin film transistor in Figure 5 is a p-type TFT. It can be seen that the path 208 between the first data writing interface 204 and the light emitting diode 203 may include a third thin film transistor 103 and a fifth thin film transistor 105 .
  • the eighth thin film transistor 401 and the fifth thin film transistor 105 are both turned on and the ninth thin film transistor 301 is turned off, the light emitting diode 203 starts to emit light.
  • the gate of the fifth thin film transistor 105 receives the enable signal sent by the controller, and the fifth thin film transistor switches the switch state according to the enable signal.
  • the enable signal causes the gate voltage of the fifth thin film transistor to be lower than the turn-on voltage, The fifth thin film transistor is turned on.
  • the ninth thin film transistor 301 turns on.
  • the passive driving circuit 201 communicates with the internal
  • the connection point 207 of the compensation circuit 202 will be pulled to the same voltage as the power supply voltage, that is, the voltage of the connection point 207 is the power supply voltage.
  • the connection point 207 is connected to the gate of the third thin film transistor 103, so the third thin film transistor 103
  • the gate voltage is also the power supply voltage, the third thin film transistor 103 is in a closed state, and no current flows through it, so the light emitting diode 203 does not emit light.
  • the first electrode of the first thin film transistor 101 is connected to the first data writing interface, and the first thin film transistor 101 can control when to write the first data voltage to the first data writing interface.
  • the gates of the thin film transistor 404 and the twelfth thin film transistor 302 can each be connected to the controller 303, and the switching states of the thin film transistors can be determined according to the control signals sent by the controller 303 for each thin film transistor.
  • the control signal may include a first turn-on signal, a second turn-on signal, an enable signal, a first detection control signal, a second detection control signal, etc., but is not limited thereto.
  • the gates of the first thin film transistor 101 , the fourth thin film transistor 104 and the tenth thin film transistor 402 can be used to receive the same first turn-on signal sent by the controller 303 ;
  • the sixth thin film transistor 106 , the gates of the seventh thin film transistor 107 and the eleventh thin film transistor 404 can be used to receive the same second turn-on signal sent by the controller 303;
  • the gates of the second thin film transistor 102 and the fifth thin film transistor 105 can be used to receive The same enable signal sent by the controller 303;
  • the gate electrode of the eighth thin film transistor 401 can be used to receive the control signal;
  • the second electrode of the twelfth thin film transistor 302 can be used to receive the first detection control sent by the controller 303 signal, the gate of the twelfth thin film transistor 302 may be used to receive the second detection control signal sent by the controller 303 .
  • FIG. 6 is a schematic structural diagram of a display panel disclosed in an embodiment of the present disclosure.
  • the display panel is a MicroLED panel with a resolution of 480*270.
  • the sub-pixel 60 has a total of 270 rows and 1440 columns, that is, the number of sub-pixel 60 is 388,800.
  • Each sub-pixel 60 corresponds to a sub-pixel circuit.
  • the sub-pixel circuit may be any one of the sub-pixel circuits described in FIGS. 2 to 5 .
  • D1, D2, D3...D1438, D1439, D1440 respectively represent sub-pixel circuits in each column.
  • the first data writing interface 204 in the sub-pixel circuits in each row can share wiring, and the second data writing interface 204 in the sub-pixel circuits in each row
  • the data writing interface 206 may share wiring lines, and the gate electrodes of the first thin film transistor 101 , the fourth thin film transistor 104 and the tenth thin film transistor 402 used to receive the first turn-on signal in each row of sub-pixel circuits may share wiring lines.
  • G(1), G(2), G(3)...G(268), G(269), G(270) respectively represent the first turn-on signal received by each row of sub-pixel circuits in the display panel.
  • the gates of the first thin film transistor 101, the fourth thin film transistor 104 and the tenth thin film transistor 402 in a row of sub-pixel circuits share common wiring, they can be used to jointly receive the same first turn-on signal. That is to say, in each row of sub-pixel circuits, each first thin film transistor 101 and the tenth thin film transistor 402 switch states under the same first turn-on signal, so the controller 303 can switch the first thin film transistor 101 to the first thin film transistor 402 in the same timing sequence.
  • the transistor 101 writes the first data voltage
  • the tenth thin film transistor 402 writes the second data voltage.
  • FIG. 7 is a schematic diagram of the process of changing the light emitting duration of a sub-pixel by a passive driving circuit disclosed in an embodiment of the present disclosure.
  • the controller 303 is connected to multiple sub-pixel circuits respectively; the controller 303 is configured to write different second data voltages to the second data writing interface 206 of each sub-pixel circuit respectively.
  • the sub-pixel circuit may be any one of the sub-pixel circuits described in FIGS. 2 to 5 .
  • the passive driving circuit 201 starts to work when the eighth thin film transistor 401 is turned on.
  • the controller 303 writes different second data voltages to the second data writing interface 206 of each sub-pixel circuit, such as 4 volts and 5 volts respectively. , 6 volts. Since the turn-on voltages of the ninth thin film transistor 301 in each sub-pixel circuit are consistent, the gate voltage of the ninth thin film transistor 301 in each sub-pixel circuit changes from the second data voltage to the second data voltage under the coupling effect of the frequency sweep signal. The time point when the voltage drops below the turn-on voltage is different, that is, the time point when the ninth thin film transistor 301 is turned off is different.
  • the time point when the current through the light-emitting diode 203 is cut off is different, that is, the time point when the light-emitting diode 203 is turned off is different.
  • the lighting duration of each sub-pixel circuit can be controlled, so that the sub-pixel circuit can control the lighting duration of the light-emitting diode according to different gray-scale display requirements, thereby improving the brightness uniformity of the display when displaying low gray-scale, and at the same time solving the problem of low-gray display.
  • the problem of grayscale loss and poor display occurs when using grayscale.
  • FIG. 8 is a schematic diagram of driving signals within one frame of a display panel disclosed in an embodiment of the present disclosure.
  • each sub-pixel circuit can include three stages, which are the "reset + compensation + data writing” stage, the "light-emitting” stage, and the "external detection” stage.
  • G(1) to G(270) may represent the first turn-on signals received by each row of sub-pixel circuits in the display panel.
  • G(1) ⁇ G(270) are the first voltage (low level) in sequence.
  • the controller can write the first data voltage to the first data writing interface 204, and to the first data writing interface 204.
  • the second data writing interface 206 writes the second data voltage.
  • the enable signal EM and the control signal Control input by the controller to each sub-pixel circuit are at a high level, which means that the second thin film transistor 102, the fifth thin film transistor 105, and the third thin film transistor 105 are at a high level.
  • Eight thin film transistors 401 are turned off.
  • Data1_1 to Data1_270 represent the first data voltages input to the first data writing interface 204 .
  • Data2_1 to Data2_270 represent the second data voltages input to the second data writing interface 206 .
  • the sweep signal sweep gradually decreases and is coupled with the second data voltage to affect the switching state of the ninth thin film transistor 301 in each sub-pixel circuit.
  • G_det(1 ⁇ 270) is the first detection control signal sent by the controller 303 to the second electrode of the twelfth thin film transistor 302, and V_det(1 ⁇ 270) is the gate electrode of the twelfth thin film transistor 302 sent by the controller 303.
  • Each sub-pixel circuit requires a twelfth thin film transistor 302 to detect the current driving capability of the ninth thin film transistor 301.
  • the enable signal EM and the control signal Control are the power supply voltage (high level), that is, the fifth thin film transistor 105 and the eighth thin film transistor 401 are both in In the off state, the sweep signal Sweep maintains a fixed level, the first detection control signal G_det and the second detection control signal V_det are at the first voltage (low level), and the twelfth thin film transistor 302 is turned on.
  • the frequency sweep signal Sweep maintains a fixed level, as shown in the frequency sweep signal Sweep in the "external detection” stage in FIG. 8 .
  • the controller 303 can select one row of sub-pixel circuits from the 270 rows of sub-pixel circuit clocks for detecting the current driving capability of the ninth thin film transistor 301.
  • the controller 303 selects sub-pixel circuits in different rows in each frame, and can complete traversing each row of sub-pixel circuits after 270 frames.
  • the controller 303 can randomly select one row of sub-pixel circuits at a time, but the sub-pixel circuits selected in each frame within 270 frames are different, or the controller 303 can also select in sequence.
  • the controller 303 randomly selects a set of second data voltages and first turn-on voltages from Data2 (1 ⁇ 270) and G (1 ⁇ 270), for example, the second data voltage corresponding to the sub-pixel circuit to be detected.
  • the data voltage is Data2_1
  • the first turn-on voltage is G(1)
  • the second data writing interface 206 inputs the second data voltage Data2_1.
  • the detection current will flow to the external controller 303 through the ninth thin film transistor 301 and the twelfth thin film transistor 302 to detect the current driving capability, and the corresponding The current change is fed back to the voltage value of the second data voltage Data2_1.
  • the detection current is less than the preset current value, that is, the driving capability of the ninth thin film transistor 301 is insufficient, it is necessary to increase the voltage value of the second data voltage Data2_1 to the preset voltage value.
  • FIG. 9 is a schematic diagram of driving signals within one frame of another display panel disclosed in an embodiment of the present disclosure.
  • the first data writing interfaces 204 of each sub-pixel circuit are connected to each other; the controller 303 is configured to write the first data voltage to the first data writing interface 204 of each sub-pixel circuit simultaneously.
  • the sub-pixel circuit may be any one of the sub-pixel circuits described in FIGS. 2 to 5 .
  • G1_1 ⁇ G1_270 are the first turn-on signals received by the gate of the first thin film transistor 101 of the internal compensation circuit 202 in each row of sub-pixel circuits
  • G2_1 ⁇ G2_270 are the tenth thin film of the passive driving circuit 201 in each row of sub-pixel circuits.
  • the gate electrode of the transistor 402 and the gate electrode of the fourth thin film transistor 104 receive the first turn-on signal.
  • the G1_1 ⁇ G1_270 lines are all merged, and the Data1_1 ⁇ Data1_270 lines are all merged, that is, the first data writing interface 204 of the internal compensation circuit 202 in each sub-pixel circuit is connected to each other, and each internal The gates of the first thin film transistors 101 in the compensation circuit 202 are connected to each other. Therefore, the internal compensation circuit 202 can achieve global illumination.
  • the controller 303 performs global reset, compensation, and data writing on the internal compensation circuit 202, that is, the controller 303 writes each first data
  • the interface 204 writes the same first data voltage at the same time, and then independently controls the light-emitting time of each sub-pixel in each row of sub-pixel circuits of the display panel through the passive driving circuit 201, that is, the light-emitting time of each light-emitting diode. Therefore, the circuit layout and driving can be simplified. design effect.
  • the G1_1 ⁇ G1_270 traces are all merged, and the Data1_1 ⁇ Data1_270 traces are all merged.
  • the first thin film transistor 101 of the internal compensation circuit 202 is turned on at the same time, and the controller 303 writes the same first data voltage to each first data writing interface 204 at the same time, so that the overall brightness of the display panel can be adjusted.
  • the G2_1 ⁇ G2_270 lines are independent, and the Data2_1 ⁇ Data2_270 lines are independent. That is, the controller still writes different second data voltages to the second data writing interface 206 of the passive driving circuit 201 in each row of sub-pixel circuits according to the sequential timing. Therefore, the lighting duration of each row of sub-pixels can be controlled to be different.
  • the passive driving circuit 201 is used to adjust the lighting duration of each sub-pixel circuit, which is beneficial to solving the problem of uneven brightness and at the same time solving the problem of Micro LED displays.
  • the problem of grayscale loss and poor display occurs when displaying low grayscale.
  • the controller can use different first data voltages for different gray-scale values, such as dividing the gray-scale value into three gray-scale value intervals, and the three gray-scale value intervals are 0 respectively. ⁇ 32, 32 ⁇ 128, 128 ⁇ 255, different first data voltages are used for different gray scale value intervals, so that global luminescence with different brightness can be achieved. For example, a higher first data voltage is used when the gray level is low, and a lower first data voltage is used when the gray level is high, and the passive driving circuit 201 adjusts each component through the coupling of the frequency sweep signal and the second data voltage.
  • the units described above as separate components may or may not be physically separated.
  • the components shown as units may or may not be physical units, that is, they may be located in one place, or they may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of this embodiment.
  • each functional unit in each embodiment of the present disclosure may be integrated into one processing unit, or each unit may exist physically alone, or two or more units may be integrated into one unit.
  • the above integrated units can be implemented in the form of hardware or software functional units.
  • the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-accessible memory.
  • the technical solution of the present disclosure is essentially, or the part that contributes to the existing technology, or all or part of the technical solution, can be embodied in the form of a software product, and the computer software product is stored in a memory , including several requests to cause a computer device (which can be a personal computer, a server or a network device, etc., specifically a processor in a computer device) to execute some or all of the steps of the above methods in various embodiments of the present disclosure.
  • a computer device which can be a personal computer, a server or a network device, etc., specifically a processor in a computer device
  • the program can be stored in a computer-readable storage medium, and the storage medium includes a read-only storage medium.
  • Memory Read-Only Memory, ROM), Random Access Memory (RAM), Programmable Read-only Memory (PROM), Erasable Programmable Read Only Memory, EPROM), One-time Programmable Read-Only Memory (OTPROM), Electronically Erasable Programmable Read-Only Memory (EEPROM), Compact Disc Read-Only Memory (CD-ROM) or other optical disk storage, magnetic disk storage, magnetic tape storage, or any other computer-readable medium that can be used to carry or store data.
  • Memory Read-Only Memory, ROM
  • RAM Random Access Memory
  • PROM Programmable Read-only Memory
  • EPROM Erasable Programmable Read Only Memory
  • OTPROM One-time Programmable Read-Only Memory
  • EEPROM Electronically Erasable Programmable Read-Only Memory
  • CD-ROM Compact Disc Read-Only Memory
  • the sub-pixel circuit provided by the present disclosure introduces a passive drive circuit, so that the internal compensation circuit can switch the light-emitting state of the light-emitting diode according to the second data voltage and frequency sweep signal input to the passive drive circuit, so that the sub-pixel circuit can switch according to different gray levels.
  • Level display needs to control the lighting time of the light-emitting diode, thereby improving the brightness uniformity of the display when displaying low gray levels, and at the same time solving the problems of gray level loss and poor display when displaying low gray levels, which has strong industrial practicability .

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Abstract

一种子像素电路，该子像素电路包括被动驱动电路（201）、内部补偿型电路（202）、发光二极管（203）；内部补偿型电路（202）包括第一数据写入接口（204）；被动驱动电路（201）包括第二数据写入接口（206）以及扫频信号输入接口（205）；第二数据写入接口（206）用于写入第二数据电压，扫频信号输入接口（205）用于接收扫频信号；被动驱动电路（201），用于根据第二数据电压和扫频信号改变被动驱动电路（201）与内部补偿型电路（202）的连接点（207）的电压；内部补偿型电路（202），用于根据连接点（207）的电压导通或截断第一数据写入接口（204）与发光二极管（203）之间的通路（208）；当通路（208）导通时，发光二极管（203）在第一数据电压的驱动下发光；当通路（208）截断时，发光二极管（203）熄灭。

Description

子像素电路
相关交叉引用
本公开要求于2021年6月22日提交中国专利局、申请号为202210715530.9、发明名称为“子像素电路”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及子像素电路。
背景技术
微米发光二极管(Micro LED)技术是将发光二极管(LED)微缩化和矩阵化的技术，Micro LED显示器具有显示亮度高、响应时间短、低功耗等众多优势，而且具有自发光、无需背光源的特性，是未来显示技术的主流趋势，具有很好的发展前景。Micro LED显示器主要采用主动驱动设计，但是在显示低灰阶时出现亮度不均匀的情况。现有技术主要是通过降低显示低灰阶时的驱动电压来改善亮度不均匀的问题，但是这种方法会使得某些灰阶丢失，从而导致显示不良。
发明内容
(一)要解决的技术问题
在现有技术中，通过降低显示低灰阶时的驱动电压来改善亮度不均匀的问题，但是这种方法会使得某些灰阶丢失，从而导致显示不良。
(二)技术方案
根据本公开公开的各种实施例，提供一种子像素电路。
本公开实施例公开一种子像素电路，所述子像素电路包括被动驱动电路、内部补偿型电路、发光二极管；所述被动驱动电路与所述内部补偿型电路连接，所述发光二极管与所述内部补偿型电路连接；所述内部补偿性电路包括第一数据写入接口；第一数据写入接口用于写入第一数据电压；所述被动驱动电路包括第二数据写入接口以及扫频信号输入接口；所述第二数据写入接口用于写入第二数据电压，所述扫频信号输入接口用于接收扫频信号；所述被动驱动电路，用于根据所述第二数据电压和所述扫频信号改变所述被动驱动电路与所述内部补偿型电路的连接点的电压；所述内部补偿型电路，用于根据所述连接点的电压导通或截断所述第一数据写入接口与所述发光二极管之间的通路；当所述通路导通时，所述发光二极管在所述第一数据电压的驱动下发光；当所述通路截断时，所述发光二极管熄灭。
作为本公开实施例一种可选的实施方式，所述被动驱动电路还包括第九薄膜晶体管；所述第九薄膜晶体管的第一电极连接所述连接点，所述第九薄膜晶体管的第二电极用于接收电源电压的输入；所述第九薄膜晶体管的栅极分别连接所述第二数据写入接口和所述扫频信号输入接口；所述第九薄膜晶体管的栅极电压在所述第二数据电压和所述扫频信号的耦合下发生变化；所述第九薄膜晶体管，用于在所述栅极电压高于所述第九薄膜晶体管的开启电压时关闭；在所述第九薄膜晶体管关闭时，所述连接点的电压为第一电压；所述内部补偿型电路，用于在所述连接点的电压为所述第一电压时，导通所述第一数据写入接口 与所述发光二极管之间的通路；所述第九薄膜晶体管，用于在所述栅极电压低于所述第九薄膜晶体管的开启电压时开启；在所述第九薄膜晶体管开启时，所述连接点的电压为所述电源电压；所述电源电压高于所述第一电压；所述内部补偿型电路，用于在所述连接点的电压为所述电源电压时，截断所述第一数据写入接口与所述发光二极管之间的通路。
作为本公开实施例一种可选的实施方式，所述被动驱动电路还包括第十薄膜晶体管和第二电容；所述第二数据写入接口包括所述第十薄膜晶体管的第一电极，所述第十薄膜晶体管的第二电极连接所述第九薄膜晶体管的栅极；所述第二电容的一端分别连接所述第十薄膜晶体管的第二电极与所述第九薄膜晶体管的栅极；所述扫频信号输入接口包括所述第二电容的另一端。
作为本公开实施例一种可选的实施方式，所述被动驱动电路还包括第十一薄膜晶体管；所述内部补偿型电路还包括第六薄膜晶体管；所述第十一薄膜晶体管的第一电极分别连接所述第二电容的一端和所述第十薄膜晶体管的第二电极，所述第十一薄膜晶体管的第二电极与所述第六薄膜晶体管的第一电极连接，所述第十一薄膜晶体管的栅极与所述第六薄膜晶体管的栅极连接；所述第六薄膜晶体管的第二电极连接所述被动驱动电路与所述内部补偿型电路的连接点。
作为本公开实施例一种可选的实施方式，所述子像素电路与控制器连接；所述控制器，用于向所述子像素电路输入所述第一数据电压、所述第二数据电压和所述扫频信号。
作为本公开实施例一种可选的实施方式，所述控制器分别与多个所述子像素电路连接；所述控制器，用于分别向各个所述子像素电路的第二数据写入接口写入不同的第二数据电压。
作为本公开实施例一种可选的实施方式，各个所述子像素电路的第一数据写入接口相互连接；所述控制器，用于同时向各个所述子像素电路的第一数据写入接口写入所述第一数据电压。
作为本公开实施例一种可选的实施方式，所述被动驱动电路还包括第十二薄膜晶体管；所述第九薄膜晶体管的第一电极还与所述第十二薄膜晶体管的第一电极连接；所述第十二薄膜晶体管的第二电极和栅极分别与所述控制器连接；所述控制器，用于截断所述被动驱动电路与所述内部补偿型电路之间的通路，并将所述扫频信号维持在固定准位；所述控制器，还用于在所述发光二极管熄灭时，通过所述第十二薄膜晶体管的第二电极检测流过所述第九薄膜晶体管和所述第十二薄膜晶体管的电流，并根据所述电流调整写入到所述第二数据写入接口的第二数据电压。
作为本公开实施例一种可选的实施方式，所述控制器，用于在流过所述第九薄膜晶体管和所述第十二薄膜晶体管的电流小于电流预设值时，将写入到所述第二数据写入接口的第二数据电压提高至电压预设值。
作为本公开实施例一种可选的实施方式，所述子像素电路还包括第八薄膜晶体管；所述被动驱动电路连接所述第八薄膜晶体管的第一电极，所述内部补偿型电路连接所述第八薄膜晶体管的第二电极；所述被动驱动电路与所述内部补偿型电路的连接点包括所述第八薄膜晶体管的第二电极与所述内部补偿型电路的连接点；所述第八薄膜晶体管的栅极用于接收控制信号；所述第八薄膜晶体管根据所述控制信号切换不同的开关状态；在所述第八薄膜晶体管的开关状态为开启状态时，所述被动驱动电路与所述内部补偿型电路之间的通路处于导通状态；在所述第八薄膜晶体管的开关状态为关闭状态时，所述被动驱动电路与所述内部补偿型电路之间的通路处于截断状态。
作为本公开实施例一种可选的实施方式，所述控制器，用于当所述发光二极管熄灭时，向所述第十二薄膜晶体管的第二电极和栅极输入控制信号，在所述第十二薄膜晶体管根据控制信号开启后，控制器检测流过所述第九薄膜晶体管和所述第十二薄膜晶体管的电流， 以对所述第九薄膜晶体管的电流驱动能力进行侦测。
作为本公开实施例一种可选的实施方式，所述第一数据写入接口与所述发光二极管之间的通路包括第五薄膜晶体管；所述第五薄膜晶体管，用于接收使能信号，根据所述使能信号切换开关状态，当所述使能信号使得所述第五薄膜晶体管的栅极电压低于开启电压时，所述第五薄膜晶体管开启。
作为本公开实施例一种可选的实施方式，所述子像素电路还包括第一薄膜晶体管，所述第一薄膜晶体管的第一电极连接所述第一数据写入接口，用于控制何时向所述第一数据写入接口写入所述第一数据电压。
作为本公开实施例一种可选的实施方式，多个所述子像素电路与控制器连接；所述控制器，用于分别向各个所述子像素电路的第二数据写入接口写入不同的所述第二数据电压。
作为本公开实施例一种可选的实施方式，多个所述子像素电路的所述第一数据写入接口相互连接；所述控制器，用于同时向各个所述子像素电路的所述第一数据写入接口写入所述第一数据电压。
本公开的其他特征和优点将在随后的说明书中阐述，并且，部分地从说明书中变得显而易见，或者通过实施本公开而了解。本公开的目的和其他优点在说明书、权利要求书以及附图中所特别指出的结构来实现和获得，本公开的一个或多个实施例的细节在下面的附图和描述中提出。
为使本公开的上述目的、特征和优点能更明显易懂，下文特举可选实施例，并配合所附附图，作详细说明如下。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用来解释本公开的原理。
为了更清楚地说明本公开实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，对于本领域普通技术人员而言，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1为现有技术提供的子像素电路的结构框图；
图2为本公开一个或多个实施例提供的一种子像素电路的结构框图；
图3为本公开一个或多个实施例提供的另一种子像素电路的结构框图；
图4为本公开一个或多个实施例提供的另一种子像素电路的结构框图；
图5为本公开一个或多个实施例中另一种子像素电路的结构框图；
图6为本公开一个或多个实施例中一种显示器面板的结构框图；
图7为本公开一个或多个实施例中一种被动驱动电路改变子像素发光时长的过程示意图；
图8为本公开一个或多个实施例提供的一种显示器面板的一帧内的驱动信号示意图；
图9为本公开一个或多个实施例提供的另一种显示器面板一帧内的驱动信号示意图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
需要说明的是，本公开实施例及附图中的术语“包括”和“具有”以及它们任何变 形，意图在于覆盖不排他的包含。例如包含了一系列步骤或单元的过程、方法、系统、产品或设备没有限定于已列出的步骤或单元，而是可选地还包括没有列出的步骤或单元，或可选地还包括对于这些过程、方法、产品或设备固有的其它步骤或单元。
请参阅图1，图1是一种现有技术的子像素电路的结构示意图。如图1所示，该子像素电路为7T1C结构，为内部补偿型电路。7T1C结构是由7个薄膜晶体管(TFT)和1个存储电容组成。该子像素电路包括第一薄膜晶体管101、第二薄膜晶体管102、第三薄膜晶体管103、第四薄膜晶体管104、第五薄膜晶体管105、第六薄膜晶体管106、第七薄膜晶体管107、发光二极管203、第一电容109。
其中，薄膜晶体管(TFT)为电压型开关的器件。薄膜晶体管包括3个电极，分别为源极、漏极、栅极。当薄膜晶体管的栅极电压大于薄膜晶体管的开启电压，源极和漏极之间会导通；当薄膜晶体管的栅极电压小于薄膜晶体管的开启电压，源极和漏极之间会截断。
每个子像素电路包括一个发光二极管203，即Micro LED。
由于Micro LED显示器一般采用主动驱动设计，对于显示0～255级灰阶的颜色会符合gamma2.2的标准。Gamma2.2的公式为：
L＝L255*(L/L255)^gamma；
其中，L为子像素的亮度，L255为子像素在255级灰阶(即最大灰阶)下的灰阶值，L为在i灰阶下的灰阶值，i可以是0～255范围内的整数；gamma为2.2。Gamma2.2是人眼感受亮度的最佳值。因此，Micro LED显示255级灰阶的颜色会符合gamma2.2的亮度-电流(light-current，LI)曲线，即LED芯片驱动电流对亮度的曲线图。
由于采用主动驱动设计的Micro LED在显示低灰阶(比如0～32级灰阶)时，会出现亮度不均匀的情况，主要原因是Micro LED的LI曲线过于陡峭，导致在显示低灰阶时因第一数据电压以及TFT器件的电性不均匀导致亮度上的不均匀。
在相关技术中，为了解决显示亮度不均匀的问题，通常在显示低灰阶时会降低驱动显示器面板发光的数据线电压，并影响流过TFT器件的电流大小来限制Micro LED的通过电流。当流过Micro LED的电流变小，Micro LED就发出较低亮度的光，这种通过主动器件控制发光亮度的方法可以称为主动型器件的显示驱动。但是由于Micro LED显示器是电流型驱动的发光显示单元，与液晶电压型驱动相比是不同的，电流型控制需要控制TFT的通过电流来控制Micro LED的通过电流。因此在低灰阶的情形下，驱动显示器面板发光的数据线电压是比较小的，在一个最小单位电压范围内变化，因此在该情形下，Micro LED因电流差异导致的亮度差异并不明显，导致某些灰阶无法显示而丢失。
本公开实施例公开了一种子像素电路，能够解决Micro LED显示器在显示低灰阶时出现的灰阶丢失和显示不良的问题。以下分别进行详细说明。
本公开实施例公开的子像素电路能够应用于电子设备的Micro LED显示器中，其中，电子设备可以包括手机、电脑、电视机等，但不限于此。Micro LED可以为尺寸小于50微米(μm)*50μm的LED芯片，厚度约7～10μm，没有蓝宝石衬底。
每个像素由红蓝绿(RGB)三原色组成，每个像素上的每种颜色叫做一个子像素，示例性的，一个解析度为480*270的Micro LED显示器面板上的子像素个数为270*(480*3)＝388800。Micro LED显示器面板上每一个子像素都对应有一个子像素电路。
请参阅图2，图2是本公开实施例公开的一种子像素电路的结构示意图。该子像素电路包括被动驱动电路201、内部补偿型电路202、发光二极管203；被动驱动电路201与内部补偿型电路202连接，发光二极管203与内部补偿型电路202连接；
内部补偿性电路202包括第一数据写入接口204；第一数据写入接口204用于写入第一数据电压；被动驱动电路201包括第二数据写入接口206以及扫频信号输入接口205；第二数据写入接口206用于写入第二数据电压，扫频信号输入接口205用于接收扫频信号；
被动驱动电路201，用于根据第二数据电压和扫频信号改变被动驱动电路201与内部补偿型电路202的连接点207的电压；
内部补偿型电路202，用于根据连接点207的电压导通或截断第一数据写入接口204与发光二极管203之间的通路208；当通路208导通时，发光二极管203在第一数据电压的驱动下发光；当通路208截断时，发光二极管203熄灭。
其中，内部补偿型电路202可以为如图1所示的子像素电路，电路结构为7T1C，具体不作限定。
第一数据电压和第二数据电压为驱动显示器面板发光的数据线电压，不同的数据线电压会对应不同的显示器面板的亮度。
第一数据写入接口204可以是内部补偿型电路202中用于复位、补偿、写入的电路接口，可以用于写入第一数据电压。可选的，第一数据写入接口204还可以是开关、晶体管等电子器件的一个端口，开关、晶体管等电子器件可以控制何时写入第一数据电压。
第一数据电压可以调整发光二极管203的发光亮度；第一数据电压可以为2伏(V)～6V，具体不作限定。
发光二极管203可以是尺寸为50微米(μm)*50μm左右的Micro LED。
第一数据写入接口204与发光二极管203之间的通路208可以包括电压驱动型器件，比如场效晶体管(MOSFET)、绝缘栅双极型晶体管(IGBT)等，具体不作限定，因此通路208的导通状态可以根据被动驱动电路与内部补偿型电路的连接点207的电压确定。通路208的导通状态决定发光二极管203的发光状态。
第二数据电压可以是驱动显示器面板发光的数据线电压，在发光二极管203发光时，第二数据电压可以影响发光二极管203的发光亮度；第二数据电压可以为2伏(V)～6V，具体不作限定。
扫频信号可以为频率在限定范围内作线性变化的信号，扫频信号可以与第二数据电压进行耦合得到可变的电压，因此，被动驱动电路201根据第二数据电压和扫频信号输出到内部补偿型电路202的电压是可变的，被动驱动电路201可以通过改变连接点207的电压，使得内部补偿型电路202根据连接点207的电压控制发光二极管203的发光状态。也就是说，被动驱动电路201通过改变连接点207的电压，可以间接控制发光二极管203何时发光，何时熄灭，因此可以控制发光二极管的发光时长。
可见，本公开实施例的子像素电路通过引入被动驱动电路，使得内部补偿型电路能够根据输入到被动驱动电路的第二数据电压和扫频信号切换发光二极管的发光状态，使得子像素电路可以根据不同的灰阶显示需求控制发光二极管的发光时长，从而提高显示器在显示低灰阶时的亮度均匀性，同时解决在显示低灰阶时出现的灰阶丢失和显示不良的问题。
请进一步参阅图3，图3是本公开实施例公开的另一种子像素电路的结构示意图。
被动驱动电路201还包括第九薄膜晶体管301；第九薄膜晶体管301的第一电极连接连接点207，第九薄膜晶体管301的第二电极用于接收电源电压的输入；第九薄膜晶体管301的栅极分别连接第二数据写入接口206和扫频信号输入接口205；第九薄膜晶体管301的栅极电压在第二数据电压和扫频信号的耦合下发生变化。
薄膜晶体管(TFT)是一种绝缘栅场效应晶体管，可以分为n型TFT和p型TFT。本公开实施例采用的各个薄膜晶体管都是p型TFT，p型TFT的工作原理是：当薄膜晶体管的栅极电压小于薄膜晶体管的开启电压时，薄膜晶体管导通；当薄膜晶体管的栅极电压大于薄膜晶体管的开启电压时，薄膜晶体管截断。其中，薄膜晶体管的开启电压为薄膜晶体管的器件参数，是使薄膜晶体管源级和漏极之间刚导通时的栅极电压。
第九薄膜晶体管301的第一电极和第二电极可以分别表示第九薄膜晶体管301的源极和漏极。本公开实施例中各个薄膜晶体管的第一电极和第二电极均可分别表示该薄膜晶体 管的源极和漏极。第一电极和第二电极中哪个是源极、哪个是漏极，具体不作限定。
第九薄膜晶体管301的第二电极用于接收电源电压的输入，其中，电源电压可以是3.3伏或者5伏，具体不作限定。
第九薄膜晶体管301，用于在栅极电压高于第九薄膜晶体管301的开启电压时关闭；在第九薄膜晶体管301关闭时，连接点207的电压为第一电压。
内部补偿型电路202，用于在连接点207的电压为第一电压时，导通第一数据写入接口204与发光二极管203之间的通路208。
第九薄膜晶体管301，用于在栅极电压低于第九薄膜晶体管301的开启电压时开启；在第九薄膜晶体管301开启时，连接点207的电压为电源电压；电源电压高于第一电压。
第九薄膜晶体管301的栅极电压可以是第二数据电压和扫频信号耦合的电压，该耦合的电压是可变的，并且电压数值从第二数据电压开始逐渐减小。示例性的，第二数据电压为4V，第二数据电压和扫频信号耦合的电压从4V开始逐渐减小，即第九薄膜晶体管301的栅极电压从4V开始逐渐减小，假设第九薄膜晶体管301的开启电压为0.8V，当第九薄膜晶体管301的栅极电压还未减小到开启电压以下时，第九薄膜晶体管301关闭，此时被动驱动电路201与内部补偿型电路202的连接点207的电压为第一电压。
其中，第一电压可以为低于0.5V的低电平，具体不作限定。
当第九薄膜晶体管301的栅极电压减小到开启电压以下时，第九薄膜晶体管301开启，第九薄膜晶体管301的第二电极可以接收电源电压的输入，此时连接点207的电压会被拉至与电源电压同样的电压，即连接点207的电压为电源电压。
其中，电源电压可以为高于3V的高电平，具体不作限定。
内部补偿型电路202，用于在连接点207的电压为电源电压时，截断第一数据写入接口204与发光二极管203之间的通路208。
当连接点207的电压为第一电压时，内部补偿型电路202可以导通第一数据写入接口204与发光二极管203之间的通路208。可选的，内部补偿型电路202可以通过输入控制信号控制通路208上的开关器件，从而控制通路208的导通或截断，或者，内部补偿型电路202可以通过通路208上的电压驱动型器件控制通路208的导通或截断。可选的，电压驱动型器件可以在连接点207的电压为第一电压时闭合，在连接点207的电压为电源电压时断开。
可见，本公开实施例中，被动驱动电路通过第二数据电压和扫频信号切换第九薄膜晶体管的工作状态，使得内部补偿型电路可以直接根据第九薄膜晶体管的工作状态灵活地控制发光二极管的发光状态，因此子像素电路可以根据不同的灰阶显示需求控制发光二极管的发光时长，从而提高Micro LED显示器在显示低灰阶时的亮度均匀性，同时解决在显示低灰阶时出现的灰阶丢失和显示不良的问题。
在一些实施例中，子像素电路与控制器303连接；控制器303用于向子像素电路输入第一数据电压、第二数据电压和扫频信号。
控制器303可以是手机、电脑、电视机等电子设备的中央处理器(CPU)，具体不作限定。控制器303可以向电子设备的显示器面板中的子像素电路输入第一数据电压、第二数据电压和扫频信号以切换子像素电路中发光二极管地发光状态，从而调节显示器面板的亮度、色彩等参数。
被动驱动电路201还包括第十二薄膜晶体管302；第九薄膜晶体管301的第一电极还与第十二薄膜晶体管302的第一电极连接；第十二薄膜晶体管302的第二电极和栅极分别与控制器303连接。
控制器303，用于截断被动驱动电路201与内部补偿型电路202之间的通路，并将扫频信号维持在固定准位。
需要说明的是，控制器303截断被动驱动电路201与内部补偿型电路202之间的通路，此时发光二极管203熄灭，且将扫频信号维持在固定准位，即扫频信号不会对第二数据电压产生耦合作用。
控制器303，还用于在发光二极管203熄灭时，通过第十二薄膜晶体管302的第二电极检测流过第九薄膜晶体管301和第十二薄膜晶体管302的电流，并根据电流调整写入到第二数据写入接口206的第二数据电压。
第十二薄膜晶体管302的第二电极和栅极可以用于接收控制器303发送的控制信号切换开关状态。
控制器303，用于在流过第九薄膜晶体管301和第十二薄膜晶体管302的电流小于电流预设值时，将写入到第二数据写入接口206的第二数据电压提高至电压预设值。
当发光二极管203熄灭时，控制器303向第十二薄膜晶体管302的第二电极和栅极输入控制信号，在第十二薄膜晶体管302根据控制信号开启后，控制器303检测流过第九薄膜晶体管301和第十二薄膜晶体管302的电流，以对第九薄膜晶体管301的电流驱动能力进行侦测。电流预设值可以是用于保证第九薄膜晶体管301处于最佳电流驱动能力的电流值，因此，如果流过第九薄膜晶体管301和第十二薄膜晶体管302的电流小于电流预设值，说明用于驱动第九薄膜晶体管301的第二数据电压小于电压预设值，为了提高第九薄膜晶体管的驱动能力，可以将第二数据电压提高至电压预设值。
可见，本公开实施例在发光二极管203发光和熄灭过程中，第九薄膜晶体管301可能会因为工作状态的切换以及电流的变化产生驱动损耗、导通损耗等电压损耗，因此通过引入第十二薄膜晶体管302，在每次发光二极管203熄灭时，对第九薄膜晶体管301的电流驱动能力进行侦测，并对写入第二数据写入接口206的第二数据电压进行反馈和补偿，能够有效提高子像素电路的稳定性。
请进一步参阅图4，图4是本公开实施例公开的另一种子像素电路的结构示意图。
子像素电路还包括第八薄膜晶体管401；被动驱动电路201连接第八薄膜晶体管401的第一电极，内部补偿型电路202连接第八薄膜晶体管401的第二电极；被动驱动电路201与内部补偿型电路202的连接点包括第八薄膜晶体管401的第二电极与内部补偿型电路202的连接点；第八薄膜晶体管401的栅极用于接收控制信号；第八薄膜晶体管401根据控制信号切换不同的开关状态；
在第八薄膜晶体管401的开关状态为开启状态时，被动驱动电路201与内部补偿型电路202之间的通路处于导通状态，发光二极管203发光；
在第八薄膜晶体管401的开关状态为关闭状态时，被动驱动电路201与内部补偿型电路202之间的通路处于截断状态，发光二极管203熄灭。
第八薄膜晶体管401的栅极可以用于接收控制器发送的用于控制第八薄膜晶体管开关状态的控制信号，第八薄膜晶体管401根据控制信号可以在开启状态和关闭状态之间切换，发光二极管203根据第八薄膜晶体管401的开关状态可以在发光和熄灭之间切换。
需要说明的是，第八薄膜晶体管401处于开启状态，意味着第八薄膜晶体管401的第一电极和第二电极之间的电流可以导通；第八薄膜晶体管401处于关闭状态，意味着第八薄膜晶体管401的第一电极和第二电极之间没有电流经过。
第八薄膜晶体管401和第九薄膜晶体管301可以共同控制发光二极管的发光或熄灭。在第八薄膜晶体管401处于开启状态，第九薄膜晶体管301处于关闭状态时，发光二极管203发光；在第八薄膜晶体管401处于开启状态，第九薄膜晶体管301也处于开启状态时，发光二极管203熄灭。
因此，发光二极管203的发光过程如下：第八薄膜晶体管401开启，第二数据电压使得第九薄膜晶体管301的栅极电压高于开启电压，因此第九薄膜晶体管301关闭，被动驱 动电路201与内部补偿型电路202的连接点207的电压为第一电压，通路208导通，发光二极管203开始发光；第二数据电压与扫频信号耦合，使得第九薄膜晶体管301的栅极电压不断下降，当第九薄膜晶体管301的栅极电压低于开启电压时，第九薄膜晶体管301开启，被动驱动电路201与内部补偿型电路202的连接点207的电压被拉至与电源电压相同的电压，即连接点207的电压为电源电压，通路208截断，发光二极管203熄灭。
因此，第八薄膜晶体管401相当于一个总控开关，决定了被动驱动电路201与内部补偿型电路202之间的导通状态，决定了发光二极管203是否能够发光；在第八薄膜晶体管401处于开启状态的前提下，第九薄膜晶体管301用于控制发光二极管203的发光时长，决定了发光二极管203何时会熄灭。
被动驱动电路201还包括第十薄膜晶体管402和第二电容403；第二数据写入接口206包括第十薄膜晶体管402的第一电极，第十薄膜晶体管402的第二电极连接第九薄膜晶体管301的栅极；第二电容403的一端分别连接第十薄膜晶体管402的第二电极与第九薄膜晶体管301的栅极；扫频信号输入接口205包括第二电容403的另一端。
在本公开实施例中，第二数据写入接口206包括第十薄膜晶体管402的第一电极，第十薄膜晶体管402的第一电极可以用于接收写入的第二数据电压。第十薄膜晶体管402的栅极可以用于接收控制器输入的控制信号，第十薄膜晶体管402会根据控制信号切换开关状态。第十薄膜晶体管402可以基于不同的开关状态控制何时接收写入的第二数据电压。
第二电容403的另一端可以用于接收输入的扫频信号，第二电容403可以用于存储扫频信号。
被动驱动电路201还包括第十一薄膜晶体管404；内部补偿型电路202还包括第六薄膜晶体管106；第十一薄膜晶体管404的第一电极分别连接第二电容403的一端和第十薄膜晶体管402的第二电极，第十一薄膜晶体管404的第二电极与第六薄膜晶体管106的第一电极连接，第十一薄膜晶体管404的栅极与第六薄膜晶体管106的栅极连接；第六薄膜晶体管106的第二电极连接被动驱动电路201与内部补偿型电路202的连接点。
第十一薄膜晶体管404与第六薄膜晶体管106之间连接的通路使得被动驱动电路201可以与内部补偿型电路202之间多了一个电流通路，在第八薄膜晶体管401开启而第九薄膜晶体管201关闭时，内部补偿型电路202可以接收来自被动驱动电路201的电流，发光二极管203的亮度不仅受到第一数据电压的影响，还受到第二数据电压的影响。
可见，本公开实施例可以在显示器面板显示低灰阶时通过内部补偿型电路和被动驱动电路来驱动发光二极管发光，通过内部补偿型电路来改变发光二极管的发光亮度以及通过被动驱动电路来改变发光二极管的发光时长，由此可以提高Micro LED显示器在显示低灰阶时的亮度均匀性，同时解决在显示低灰阶时出现的灰阶丢失和显示不良的问题。
请进一步参阅图5，图5是本公开实施例公开的另一种子像素电路的结构示意图。该子像素电路为12T2C结构，包括12个薄膜晶体管和2个电容。图5中各个薄膜晶体管为p型TFT。可见，第一数据写入接口204与发光二极管203之间的通路208可以包括第三薄膜晶体管103和第五薄膜晶体管105。
当第八薄膜晶体管401和第五薄膜晶体管105均处于开启状态，且第九薄膜晶体管301关闭时，发光二极管203开始发光。其中，第五薄膜晶体管105的栅极接收控制器发送的使能信号，第五薄膜晶体管根据使能信号切换开关状态，当使能信号使得第五薄膜晶体管的栅极电压低于开启电压时，第五薄膜晶体管开启。
当第九薄膜晶体管301的栅极电压在第二数据电压和扫频信号的耦合作用下变化到第九薄膜晶体管301的开启电压以下，第九薄膜晶体管301开启,此时被动驱动电路201与内部补偿型电路202的连接点207会被拉至与电源电压相同的电压，即连接点207的电压为电源电压，连接点207与第三薄膜晶体管103的栅极连接，因此第三薄膜晶体管103 的栅极电压也为电源电压，第三薄膜晶体管103处于关闭状态，不会有电流通过，因此发光二极管203不会发光。
第一薄膜晶体管101的第一电极连接第一数据写入接口，第一薄膜晶体管101可以控制何时向第一数据写入接口写入第一数据电压。
第一薄膜晶体管101、第二薄膜晶体管102、第四薄膜晶体管104、第五薄膜晶体管105、第六薄膜晶体管106、第七薄膜晶体管107、第八薄膜晶体管401、第十薄膜晶体管402、第十一薄膜晶体管404、第十二薄膜晶体管302的栅极均可以连接控制器303，上述薄膜晶体管的开关状态可以分别根据控制器303发送针对各个薄膜晶体管的控制信号确定。示例性的，控制信号可以包括第一开启信号、第二开启信号、使能信号、第一侦测控制信号、第二侦测控制信号等，但不限于此。
作为一种可选的实施方式，第一薄膜晶体管101、第四薄膜晶体管104和第十薄膜晶体管402的栅极可以用于接收控制器303发送的相同的第一开启信号；第六薄膜晶体管106、第七薄膜晶体管107、第十一薄膜晶体管404的栅极可以用于接收控制器303发送的相同的第二开启信号；第二薄膜晶体管102和第五薄膜晶体管105的栅极可以用于接收控制器303发送的相同的使能信号；第八薄膜晶体管401的栅极可以用于接收控制信号；第十二薄膜晶体管302的第二电极可以用于接收控制器303发送的第一侦测控制信号，第十二薄膜晶体管302的栅极可以用于接收控制器303发送的第二侦测控制信号。
如图6所示，图6是本公开实施例公开的一种显示器面板的结构示意图。该显示器面板为480*270解析度的MicroLED面板，子像素60一共有270行、1440列，即子像素60的个数为388800个。每一个子像素60都对应于一个子像素电路。其中，子像素电路可以为图2～图5任一所述子像素电路。D1、D2、D3……D1438、D1439、D1440分别表示每一列子像素电路，每一行的子像素电路中的第一数据写入接口204可以共用走线，每一行的子像素电路中的第二数据写入接口206可以共用走线，每一行的子像素电路中用于接收第一开启信号的第一薄膜晶体管101、第四薄膜晶体管104和第十薄膜晶体管402的栅极可以共用走线。G(1)、G(2)、G(3)……G(268)、G(269)、G(270)分别表示显示器面板中每一行子像素电路分别接收到的第一开启信号，每一行子像素电路中的各个第一薄膜晶体管101、第四薄膜晶体管104和第十薄膜晶体管402的栅极由于共用走线，可以用于共同接收相同的第一开启信号。也就是说，在每一行子像素电路中，各个第一薄膜晶体管101和第十薄膜晶体管402在同样的第一开启信号作用下切换开关状态，因此控制器303可以按照相同的时序向第一薄膜晶体管101写入第一数据电压，以及向第十薄膜晶体管402写入第二数据电压。
如图7所示，图7是本公开实施例公开的一种被动驱动电路改变子像素发光时长的过程示意图。
在一些实施例中，控制器303分别与多个子像素电路连接；控制器303，用于分别向各个子像素电路的第二数据写入接口206写入不同的第二数据电压。其中，子像素电路可以是图2～图5任一所述子像素电路。
被动驱动电路201在第八薄膜晶体管401开启时开始工作，当控制器303分别向各个子像素电路的第二数据写入接口206写入不同的第二数据电压，比如分别是4伏、5伏、6伏，由于各个子像素电路中第九薄膜晶体管301的开启电压是一致的，因此各个子像素电路中第九薄膜晶体管301的栅极电压在扫频信号的耦合作用下从第二数据电压下降到开启电压以下的时间点不同，即第九薄膜晶体管301关闭的时间点不同，因此通过发光二极管203的电流截断的时间点不同，即发光二极管203熄灭的时间点不同。由此可以控制各个子像素电路的发光时长，使得子像素电路可以根据不同的灰阶显示需求控制发光二极管的发光时长，从而提高显示器在显示低灰阶时的亮度均匀性，同时解决在显示低灰阶时 出现的灰阶丢失和显示不良的问题。
请进一步参阅图8，图8是本公开实施例公开的一种显示器面板的一帧内的驱动信号示意图。
示例性的，显示器面板显示一帧的时间可以为1/60秒。在一帧内，每一个子像素电路可以包括三个阶段，三个阶段分别为“复位+补偿+资料写入”阶段、“发光”阶段、“外侦测”阶段。如图8所示，G(1)～G(270)可以表示显示器面板中每一行子像素电路分别接收到的第一开启信号。
在“复位+补偿+资料写入”阶段中，G(1)～G(270)按照先后时序为第一电压(低电平)，对于显示器面板中每一行子像素电路来说，如果第一开启信号为第一电压时，该行的子像素电路中的第一薄膜晶体管101、第十薄膜晶体管402开启，控制器可以向第一数据写入接口204写入第一数据电压，以及向第二数据写入接口206写入第二数据电压。
在整个“复位+补偿+资料写入”阶段，控制器向各个子像素电路输入的使能信号EM和控制信号Control处于高电平，意味着第二薄膜晶体管102、第五薄膜晶体管105、第八薄膜晶体管401关闭。
Data1_1～Data1_270表示用于输入到第一数据写入接口204的第一数据电压。Data2_1～Data2_270表示用于输入到第二数据写入接口206的第二数据电压。在“发光”阶段，扫频信号sweep逐渐减小，与第二数据电压耦合，以影响各个子像素电路中第九薄膜晶体管301的开关状态。
G_det(1～270)为控制器303向第十二薄膜晶体管302的第二电极发送的第一侦测控制信号、V_det(1～270)为控制器303向第十二薄膜晶体管302的栅极发送的第二侦测控制信号。每一个子像素电路都需要第十二薄膜晶体管302来实现侦测第九薄膜晶体管301的电流驱动能力。如图8所示，在一帧结束前的“外侦测”阶段，使能信号EM和控制信号Control为电源电压(高电平)，即第五薄膜晶体管105和第八薄膜晶体管401都处于关闭状态，扫频信号Sweep维持固定准位,第一侦测控制信号G_det和第二侦测控制信号V_det处于第一电压(低电平)，第十二薄膜晶体管302会开启。其中，扫频信号Sweep维持固定准位可以如图8中“外侦测”阶段的扫频信号Sweep所示。
在一帧时间内，第十二薄膜晶体管302开启时，控制器303可以从270行子像素电路钟选取出一行子像素电路，用于侦测第九薄膜晶体管301的电流驱动能力。控制器303每一帧选取不同行的子像素电路，在270帧后可以遍历完每一行子像素电路。控制器303可以每次随机选取一行子像素电路，但是在270帧内每一帧选取的子像素电路不同，或者，控制器303也可以按顺序选取。
也就是说，控制器303从Data2(1～270)和G(1～270)中随机挑选出一组第二数据电压和第一开启电压，比如，要侦测的子像素电路对应的第二数据电压为Data2_1，第一开启电压为G(1)，在第十二薄膜晶体管302开启后，第一开启电压G(1)为低电平，第十薄膜晶体管402处于开启状态，控制器向第二数据写入接口206输入第二数据电压Data2_1，此时侦测电流会通过第九薄膜晶体管301以及第十二薄膜晶体管302流到外部控制器303进行电流驱动能力的侦测，并将对应的电流改变反馈到第二数据电压Data2_1的电压值。比如，侦测电流小于预设电流值，即第九薄膜晶体管301的驱动能力不足，需要提高将第二数据电压Data2_1的电压值提高到电压预设值。
请进一步参阅图9，图9是本公开实施例公开的另一种显示器面板一帧内的驱动信号示意图。
在一些实施例中，各个子像素电路的第一数据写入接口204相互连接；控制器303，用于同时向各个子像素电路的第一数据写入接口204写入第一数据电压。其中，子像素电路可以是图2～图5任一所述子像素电路。
G1_1～G1_270为每行子像素电路中内部补偿型电路202的第一薄膜晶体管101的栅极接收到的第一开启信号，G2_1～G2_270为每行子像素电路中被动驱动电路201的第十薄膜晶体管402的栅极以及第四薄膜晶体管104的栅极接收到的第一开启信号。
在一些可选的实施方式中，G1_1～G1_270走线全部合并，Data1_1～Data1_270走线全部合并，即各个子像素电路中内部补偿型电路202的第一数据写入接口204相互连接，以及各个内部补偿型电路202中的第一薄膜晶体管101的栅极相互连接。因此，内部补偿型电路202可以实现全局发光，在一帧的一开始，控制器303对内部补偿型电路202进行全局的复位、补偿、资料写入，即控制器303向各个第一数据写入接口204同时写入相同的第一数据电压，再通过被动驱动电路201独立控制显示器面板各行子像素电路中各个子像素的发光时长，即各个发光二极管的发光时长，因此可以达到简化电路布局以及驱动设计的效果。
如图9所示，G1_1～G1_270走线全部合并，Data1_1～Data1_270走线全部合并，在“复位+补偿+资料写入”阶段，内部补偿型电路202的第一薄膜晶体管101同时开启，控制器303同时向各个第一数据写入接口204写入相同的第一数据电压，由此可以调节显示器面板的整体亮度。G2_1～G2_270走线独立，Data2_1～Data2_270走线独立，即控制器依然是按照先后时序分别对各行子像素电路中被动驱动电路201的第二数据写入接口206写入不同的第二数据电压，因此可以控制各行子像素的发光时长不同。
在现有的一般设计中，G1_1～G1_270之间以及Data1_1～Data1_270之间存在时序差异，因此在驱动设计上会比较复杂；因此通过整并G1_1～G1_270走线以及整并Data1_1～Data1_270走线可以通过内部补偿型电路202实现全局发光，可简化驱动设计,也可以在一帧的一开始提高全局内部补偿的效率，因此通过走线合并以及驱动简化可以增大版图设计空间，因此提高对电路版图设计与驱动设计的弹性，同时可以简化芯片设计，减少成本。在保证内部补偿型电路202驱动各个子像素电路实现全局发光的基础上，利用被动驱动电路201对各个子像素电路的发光时长进行调整，有利于解决亮度不均匀的问题，同时解决Micro LED显示器在显示低灰阶时出现的灰阶丢失和显示不良的问题。
在另一些可选的实施方式中，控制器可以对不同的灰阶值采用不同的第一数据电压，比如将灰阶值划分成三个灰阶值区间，三个灰阶值区间分别是0～32、32～128、128～255，对于不同的灰阶值区间采用不同的第一数据电压，这样可以实现不同亮度的全局发光。比如在低灰阶时采用较高的第一数据电压，在高灰阶时采用较低的第一数据电压，并且搭配被动驱动电路201中通过扫频信号与第二数据电压的耦合调整各个子像素电路不同的发光时长，通过不同灰阶值区间对应不同的第一数据电压设计搭配各个子像素电路对应不同的第二数据电压的方法，可以实现不同灰阶值区间的子像素发光亮度不同、以及各个子像素发光时长不同，来组合改善microLED发光的均匀性问题。
应理解，说明书通篇中提到的“一个实施例”或“一实施例”意味着与实施例有关的特定特征、结构或特性包括在本公开的至少一个实施例中。因此，在整个说明书各处出现的“在一个实施例中”或“在一实施例中”未必一定指相同的实施例。此外，这些特定特征、结构或特性可以以任意适合的方式结合在一个或多个实施例中。本领域技术人员也应该知悉，说明书中所描述的实施例均属于可选实施例，所涉及的动作和模块并不一定是本公开所必须的。
在本公开的各种实施例中，应理解，上述各过程的序号的大小并不意味着执行顺序的必然先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本公开实施例的实施过程构成任何限定。
上述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物单元，即可位于一个地方，或者也可以分布到多个网络单元 上。可根据实际的需要选择其中的部分或全部单元来实现本实施例方案的目的。
另外，在本公开各实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。
上述集成的单元若以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可获取的存储器中。基于这样的理解，本公开的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的全部或者部分，可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储器中，包括若干请求用以使得一台计算机设备(可以为个人计算机、服务器或者网络设备等，具体可以是计算机设备中的处理器)执行本公开的各个实施例上述方法的部分或全部步骤。
本领域普通技术人员可以理解上述实施例的各种方法中的全部或部分步骤是可以通过程序来指令相关的硬件来完成，该程序可以存储于一计算机可读存储介质中，存储介质包括只读存储器(Read-Only Memory，ROM)、随机存储器(Random Access Memory，RAM)、可编程只读存储器(Programmable Read-only Memory，PROM)、可擦除可编程只读存储器(Erasable Programmable Read Only Memory，EPROM)、一次可编程只读存储器(One-time Programmable Read-Only Memory，OTPROM)、电子抹除式可复写只读存储器(Electrically-Erasable Programmable Read-Only Memory，EEPROM)、只读光盘(Compact Disc Read-Only Memory，CD-ROM)或其他光盘存储器、磁盘存储器、磁带存储器、或者能够用于携带或存储数据的计算机可读的任何其他介质。
以上对本公开实施例公开的一种子像素电路进行了详细介绍，本文中应用了具体个例对本公开的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本公开的方法及其核心思想。同时，对于本领域的一般技术人员，依据本公开的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本公开的限制。
工业实用性
本公开提供的子像素电路通过引入被动驱动电路，使得内部补偿型电路能够根据输入到被动驱动电路的第二数据电压和扫频信号切换发光二极管的发光状态，使得子像素电路可以根据不同的灰阶显示需求控制发光二极管的发光时长，从而提高显示器在显示低灰阶时的亮度均匀性，同时解决在显示低灰阶时出现的灰阶丢失和显示不良的问题，具有很强的工业实用性。

Claims (15)

  1. 一种子像素电路，所述子像素电路包括被动驱动电路、内部补偿型电路、发光二极管；所述被动驱动电路与所述内部补偿型电路连接，所述发光二极管与所述内部补偿型电路连接；
    所述内部补偿性电路包括第一数据写入接口；第一数据写入接口用于写入第一数据电压；所述被动驱动电路包括第二数据写入接口以及扫频信号输入接口；所述第二数据写入接口用于写入第二数据电压，所述扫频信号输入接口用于接收扫频信号；
    所述被动驱动电路，用于根据所述第二数据电压和所述扫频信号改变所述被动驱动电路与所述内部补偿型电路的连接点的电压；
    所述内部补偿型电路，用于根据所述连接点的电压导通或截断所述第一数据写入接口与所述发光二极管之间的通路；当所述通路导通时，所述发光二极管在所述第一数据电压的驱动下发光；当所述通路截断时，所述发光二极管熄灭。
  2. 根据权利要求1所述的子像素电路，其中，所述被动驱动电路还包括第九薄膜晶体管；所述第九薄膜晶体管的第一电极连接所述连接点，所述第九薄膜晶体管的第二电极用于接收电源电压的输入；所述第九薄膜晶体管的栅极分别连接所述第二数据写入接口和所述扫频信号输入接口；所述第九薄膜晶体管的栅极电压在所述第二数据电压和所述扫频信号的耦合下发生变化；
    所述第九薄膜晶体管，用于在所述栅极电压高于所述第九薄膜晶体管的开启电压时关闭；在所述第九薄膜晶体管关闭时，所述连接点的电压为第一电压；
    所述内部补偿型电路，用于在所述连接点的电压为所述第一电压时，导通所述第一数据写入接口与所述发光二极管之间的通路；
    所述第九薄膜晶体管，用于在所述栅极电压低于所述第九薄膜晶体管的开启电压时开启；在所述第九薄膜晶体管开启时，所述连接点的电压为所述电源电压；所述电源电压高于所述第一电压；
    所述内部补偿型电路，用于在所述连接点的电压为所述电源电压时，截断所述第一数据写入接口与所述发光二极管之间的通路。
  3. 根据权利要求2所述的子像素电路，其中，所述被动驱动电路还包括第十薄膜晶体管和第二电容；所述第二数据写入接口包括所述第十薄膜晶体管的第一电极，所述第十薄膜晶体管的第二电极连接所述第九薄膜晶体管的栅极；所述第二电容的一端分别连接所述第十薄膜晶体管的第二电极与所述第九薄膜晶体管的栅极；所述扫频信号输入接口包括所述第二电容的另一端。
  4. 根据权利要求3所述的子像素电路，其中，所述被动驱动电路还包括第十一薄膜晶体管；所述内部补偿型电路还包括第六薄膜晶体管；所述第十一薄膜晶体管的第一电极分别连接所述第二电容的一端和所述第十薄膜晶体管的第二电极，所述第十一薄膜晶体管的第二电极与所述第六薄膜晶体管的第一电极连接，所述第十一薄膜晶体管的栅极与所述第六薄膜晶体管的栅极连接；所述第六薄膜晶体管的第二电极连接所述被动驱动电路与所述内部补偿型电路的连接点。
  5. 根据权利要求1所述的子像素电路，其中，所述子像素电路与控制器连接；
    所述控制器，用于向所述子像素电路输入所述第一数据电压、所述第二数据电压和所述扫频信号。
  6. 根据权利要求5所述的子像素电路，其中，所述控制器分别与多个所述子像素电路连接；
    所述控制器，用于分别向各个所述子像素电路的第二数据写入接口写入不同的第二数 据电压。
  7. 根据权利要求5所述的子像素电路，其中，各个所述子像素电路的第一数据写入接口相互连接；
    所述控制器，用于同时向各个所述子像素电路的第一数据写入接口写入所述第一数据电压。
  8. 根据权利要求5所述的子像素电路，其中，所述被动驱动电路还包括第十二薄膜晶体管；所述第九薄膜晶体管的第一电极还与所述第十二薄膜晶体管的第一电极连接；所述第十二薄膜晶体管的第二电极和栅极分别与所述控制器连接；
    所述控制器，用于截断所述被动驱动电路与所述内部补偿型电路之间的通路，并将所述扫频信号维持在固定准位；
    所述控制器，还用于在所述发光二极管熄灭时，通过所述第十二薄膜晶体管的第二电极检测流过所述第九薄膜晶体管和所述第十二薄膜晶体管的电流，并根据所述电流调整写入到所述第二数据写入接口的第二数据电压。
  9. 根据权利要求8所述的子像素电路，其中：
    所述控制器，用于在流过所述第九薄膜晶体管和所述第十二薄膜晶体管的电流小于电流预设值时，将写入到所述第二数据写入接口的第二数据电压提高至电压预设值。
  10. 根据权利要求1所述的子像素电路，其中，所述子像素电路还包括第八薄膜晶体管；所述被动驱动电路连接所述第八薄膜晶体管的第一电极，所述内部补偿型电路连接所述第八薄膜晶体管的第二电极；所述被动驱动电路与所述内部补偿型电路的连接点包括所述第八薄膜晶体管的第二电极与所述内部补偿型电路的连接点；所述第八薄膜晶体管的栅极用于接收控制信号；所述第八薄膜晶体管根据所述控制信号切换不同的开关状态；
    在所述第八薄膜晶体管的开关状态为开启状态时，所述被动驱动电路与所述内部补偿型电路之间的通路处于导通状态；
    在所述第八薄膜晶体管的开关状态为关闭状态时，所述被动驱动电路与所述内部补偿型电路之间的通路处于截断状态。
  11. 根据权利要求9所述的子像素电路，其中：
    所述控制器，用于当所述发光二极管熄灭时，向所述第十二薄膜晶体管的第二电极和栅极输入控制信号，在所述第十二薄膜晶体管根据控制信号开启后，所述控制器检测流过所述第九薄膜晶体管和所述第十二薄膜晶体管的电流，以对所述第九薄膜晶体管的电流驱动能力进行侦测。
  12. 根据权利要求1所述的子像素电路，其中，所述第一数据写入接口与所述发光二极管之间的通路包括第五薄膜晶体管；
    所述第五薄膜晶体管，用于接收使能信号，根据所述使能信号切换开关状态，当所述使能信号使得所述第五薄膜晶体管的栅极电压低于开启电压时，所述第五薄膜晶体管开启。
  13. 根据权利要求1所述的子像素电路，其中，所述子像素电路还包括第一薄膜晶体管，所述第一薄膜晶体管的第一电极连接所述第一数据写入接口，用于控制何时向所述第一数据写入接口写入所述第一数据电压。
  14. 根据权利要求2所述的子像素电路，其中，多个所述子像素电路与控制器连接；
    所述控制器，用于分别向各个所述子像素电路的所述第二数据写入接口写入不同的所述第二数据电压。
  15. 根据权利要求14所述的子像素电路，其中，多个所述子像素电路的所述第一数据写入接口相互连接；
    所述控制器，用于同时向各个所述子像素电路的所述第一数据写入接口写入所述第一 数据电压。
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CN115050313A (zh) * 2022-06-22 2022-09-13 上海闻泰信息技术有限公司 子像素电路
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