WO2023241150A1 - 基于son的热电红外传感器及制备方法 - Google Patents

基于son的热电红外传感器及制备方法 Download PDF

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Publication number
WO2023241150A1
WO2023241150A1 PCT/CN2023/082764 CN2023082764W WO2023241150A1 WO 2023241150 A1 WO2023241150 A1 WO 2023241150A1 CN 2023082764 W CN2023082764 W CN 2023082764W WO 2023241150 A1 WO2023241150 A1 WO 2023241150A1
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layer
son
silicon
cavity
substrate
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PCT/CN2023/082764
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English (en)
French (fr)
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徐德辉
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上海烨映微电子科技股份有限公司
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Publication of WO2023241150A1 publication Critical patent/WO2023241150A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N10/00—Thermoelectric devices comprising a junction of dissimilar materials, i.e. devices exhibiting Seebeck or Peltier effects
    • H10N10/01—Manufacture or treatment
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
    • B81B7/0009—Structural features, others than packages, for protecting a device against environmental influences
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
    • B81B7/02—Microstructural systems; Auxiliary parts of microstructural devices or systems containing distinct electrical or optical devices of particular relevance for their function, e.g. microelectro-mechanical systems [MEMS]
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00023—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems without movable or flexible elements
    • B81C1/00047—Cavities
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N10/00—Thermoelectric devices comprising a junction of dissimilar materials, i.e. devices exhibiting Seebeck or Peltier effects
    • H10N10/10—Thermoelectric devices comprising a junction of dissimilar materials, i.e. devices exhibiting Seebeck or Peltier effects operating with only the Peltier or Seebeck effects
    • H10N10/17—Thermoelectric devices comprising a junction of dissimilar materials, i.e. devices exhibiting Seebeck or Peltier effects operating with only the Peltier or Seebeck effects characterised by the structure or configuration of the cell or thermocouple forming the device
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2201/00—Specific applications of microelectromechanical systems
    • B81B2201/02—Sensors

Definitions

  • the invention belongs to the field of semiconductors and relates to a SON-based pyroelectric infrared sensor and a preparation method.
  • Micro-Electro-Mechanical-System refers to a micro system that can integrate mechanical components, drive components, optical systems, and electronic control systems into a whole. It uses microelectronics technology and micro-machining technology. , such as silicon body micromachining, silicon surface micromachining, wafer bonding and other combined manufacturing processes, to create a variety of sensors, actuators, actuators and microsystems with excellent performance, low price and miniaturization.
  • thermoelectric infrared sensor based on MEMS technology has an infrared absorption layer in the center, which is responsible for absorbing external infrared radiation to increase its own temperature.
  • a hot junction is formed near the infrared absorption layer, and a cold junction is located on the heat dissipation substrate, and the hot junction is suspended.
  • a thermopile structure is connected in series between the hot junction and the cold junction. The temperature difference electromotive force is output through the pin, thus forming a structure that can connect multiple thermopile in series and Sensor for contactless measurement of temperature differences.
  • thermoelectric infrared sensors generally make the thermopile structure first, and then form a cavity to release the thermopile suspension structure. The smaller the size of the thermopile structure, the more difficult the release process is. For integrated CMOS circuit structures For the thermopile structure, the release process also needs to consider the compatibility with the CMOS process, and the corrosion accuracy needs to be precisely controlled to avoid corrosion of the CMOS circuit area; in order to reduce the thermal convection loss of the thermopile structure, thermoelectric infrared sensors generally require Hermetic packaging, especially for thermoelectric infrared sensor arrays, is more difficult to release the thermopile suspension structure due to the small size of the thermopile structure, and vacuum packaging is required to reduce thermal convection losses of the thermopile sensor.
  • the purpose of the present invention is to provide a SON-based pyroelectric infrared sensor and a preparation method to solve the above series of preparation problems faced by the pyroelectric infrared sensor in the prior art.
  • the present invention provides a preparation method of a SON-based pyroelectric infrared sensor, which includes the following steps:
  • the SON substrate including a substrate silicon, a top layer of silicon, and a cavity located between the substrate silicon and the top layer of silicon;
  • a metal interconnection layer connected to the N-type thermocouple layer and the P-type thermocouple layer is formed.
  • the method of forming the SON substrate includes a bonding method or an epitaxial method.
  • the formed cavity includes an air cavity or a vacuum cavity, where, when it is a vacuum cavity, the vacuum degree is between 10 -3 and 10 Pa; the size of a single cavity is less than 500 ⁇ 500 ⁇ m 2 ; The depth of the cavity is 1 to 400 ⁇ m; the thickness of the top silicon formed is 0.5 to 5 ⁇ m.
  • the N-type thermocouple layer and the P-type thermocouple layer are isolated by the top layer of silicon.
  • the formed SON substrate further includes a silicon oxide layer located between the substrate silicon and the top silicon, and the cavity is located under the silicon oxide layer.
  • a step of removing the top layer of silicon is also included to form a groove exposing the silicon oxide layer between the N-type thermocouple layer and the P-type thermocouple layer, and the N-type thermocouple layer
  • the couple layer is isolated from the P-type thermocouple layer by the silicon oxide layer.
  • the silicon oxide layer is produced through an oxidation process; the thickness of the formed silicon oxide layer is 0.01-2 ⁇ m.
  • the step of forming a CMOS circuit structure in the SON substrate is included, wherein the source and drain doped regions in the CMOS circuit structure are formed simultaneously with the corresponding thermocouple layers, and the metal in the CMOS circuit structure The layer is formed simultaneously with the metal interconnect layer.
  • the present invention also provides a SON-based pyroelectric infrared sensor.
  • the pyroelectric infrared sensor includes:
  • the SON substrate includes substrate silicon, top layer silicon, and a cavity located between the substrate silicon and the top layer silicon;
  • N-type thermocouple layer and P-type thermocouple layer, the N-type thermocouple layer and the P-type thermocouple layer are located in the top silicon above the cavity;
  • a metal interconnection layer is connected to the N-type thermocouple layer and the P-type thermocouple layer.
  • the cavity includes an air cavity or a vacuum cavity, where, when it is a vacuum cavity, the degree of vacuum is between 10 -3 and 10 Pa; the size of a single cavity is less than 500 ⁇ 500 ⁇ m 2 ; so The depth of the cavity is 1-400 ⁇ m; the thickness of the formed top layer silicon is 0.5-5 ⁇ m.
  • the SON substrate further includes a silicon oxide layer located between the substrate silicon and the top silicon, and the cavity is located below the silicon oxide layer; the thickness of the silicon oxide layer is 0.01 ⁇ 2 ⁇ m.
  • the SON substrate further includes a CMOS circuit structure, wherein the source and drain doping regions in the CMOS circuit structure are made of the same material as the corresponding thermocouple layer, and the metal layer in the CMOS circuit structure is made of the same material as the corresponding thermocouple layer.
  • the metal interconnection layers are made of the same material.
  • the SON-based thermoelectric infrared sensor and preparation method of the present invention use SON technology to prefabricate the SON substrate with a cavity, which avoids the release process of the thermopile structure, thereby simplifying the manufacturing process; based on the SON substrate
  • the suspended top silicon is used to make a thermocouple structure, which avoids the separate deposition of thermoelectric materials, and can take advantage of the high Seebeck coefficient of the top silicon
  • the SON substrate can include a CMOS circuit structure, a doped thermocouple layer and a metal interconnect layer.
  • thermopile structure is prepared on the top silicon of the SON substrate, and the entire thermopile suspension structure is a closed membrane structure without an opening structure, thereby improving the mechanical strength of the thermopile suspension structure; the present invention can be applied to thermoelectric applications Devices with small stack structure size and integrated thermopile and CMOS circuits.
  • Figure 1 shows a schematic structural diagram of a SON substrate in Embodiment 1 of the present invention.
  • FIG. 2 shows a schematic structural diagram after ion implantation is performed to form an N-type thermocouple layer and a P-type thermocouple layer in Embodiment 1 of the present invention.
  • FIG. 3 shows a schematic structural diagram after forming a metal interconnection layer in Embodiment 1 of the present invention.
  • FIG. 4 shows a partial top view of the pyroelectric infrared sensor formed in Embodiment 1 of the present invention.
  • Figure 5 shows a schematic structural diagram of the SON substrate in Embodiment 2 of the present invention.
  • FIG. 6 shows a schematic structural diagram after ion implantation is performed to form an N-type thermocouple layer and a P-type thermocouple layer in Embodiment 2 of the present invention.
  • FIG. 7 is a schematic structural diagram after forming a metal interconnection layer in Embodiment 2 of the present invention.
  • FIG. 8 shows a schematic structural diagram after removing the top layer of silicon to form a groove in Embodiment 2 of the present invention.
  • FIG. 9 shows a partial top view of the pyroelectric infrared sensor formed in Embodiment 2 of the present invention.
  • thermocouple layer 201 N-type thermocouple layer
  • thermocouple layer 202 P-type thermocouple layer
  • spatial relationship words such as “below”, “below”, “below”, “below”, “above”, “on”, etc. may be used herein to describe an element or element shown in the drawings.
  • a layer is referred to as being “between” two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
  • structures described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, as well as may include additional features formed between the first and second features. Embodiments between second features such that the first and second features may not be in direct contact.
  • illustrations provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner, so the illustrations only show the components related to the present invention and are not based on the number, shape and number of components during actual implementation. Dimension drawing, in actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complex.
  • this embodiment provides a method for preparing a SON-based pyroelectric infrared sensor, which includes the following steps:
  • S1-1 Form a SON substrate 100, which includes a substrate silicon 101, a top layer of silicon 102, and a cavity 103 located between the substrate silicon 101 and the top layer of silicon 102;
  • S1-2 Perform ion implantation to form an N-type thermocouple layer 201 and a P-type thermocouple layer 202 in the top silicon 102 above the cavity 103;
  • S1-3 Form a metal interconnection layer 300 connected to the N-type thermocouple layer 201 and the P-type thermocouple layer 202.
  • step S1-1 is performed to form a SON substrate 100.
  • the SON substrate 100 includes a substrate silicon 101, a top layer of silicon 102, and a space between the substrate silicon 101 and the top layer of silicon 102. Cavity 103.
  • the material of the top layer of silicon 102 may be single crystal silicon, so that the high-performance pyroelectric infrared sensor can be subsequently prepared based on the advantage of the high Seebeck coefficient of the top layer of single crystal silicon.
  • SON technology is used to pre-prepare the cavity with the The SON substrate 100 of 103 can avoid the release process during the subsequent preparation of the thermopile structure, thereby simplifying the manufacturing process.
  • a method of forming the SON substrate 100 may include a bonding method or an epitaxial method.
  • the method of forming the SON substrate 100 may include a bonding method or an epitaxial method, such as providing the substrate silicon 101, forming the cavity 103 by etching the substrate silicon 101, and forming the cavity 103 through bonding and smart stripping.
  • the top layer of silicon 102 is formed on the substrate silicon 101; or the substrate silicon 101 is provided first, and after the spacing trench is formed by etching the substrate silicon 101, the substrate silicon 101 An epitaxial method is used to form the top layer of silicon 102 and convert the trench into the cavity 103 .
  • the preparation method of the SON substrate 100 is not excessively limited here, and can be specifically selected according to needs.
  • the formed cavity 103 may include an air cavity or a vacuum cavity, where, when it is a vacuum cavity, the vacuum degree is between 10 -3 and 10 Pa; the size of a single cavity 103 is less than 500 ⁇ 500 ⁇ m 2 ; the depth of the cavity 103 is 1 to 400 ⁇ m; and the thickness of the formed top layer silicon is 0.5 to 5 ⁇ m.
  • the cavity 103 when the cavity 103 is a vacuum cavity, the heat convection loss can be further reduced, thereby improving the performance of the subsequently prepared thermoelectric infrared sensor.
  • the cavity can be
  • the cavity 103 can also be an air cavity, which can be selected according to needs.
  • the vacuum degree of the vacuum cavity is between 10 -3 and 10 Pa, such as 10 -3 Pa, 1 Pa, 10 Pa, etc.; the size of a single cavity 103 is less than 500 ⁇ 500 ⁇ m 2 , such as 400 ⁇ 400 ⁇ m. 2 , 300 ⁇ 300 ⁇ m 2 , etc.; the depth of the cavity 103 can be 1-400 ⁇ m, such as 1 ⁇ m, 10 ⁇ m, 100 ⁇ m, 400 ⁇ m, etc.; so that the vacuum cavity can avoid excessive deformation of the top silicon 102 , affecting subsequent micromachining processes.
  • the thickness of the top layer silicon 102 may be 0.5-5 ⁇ m, such as 0.5 ⁇ m, 1 ⁇ m, 2 ⁇ m, 5 ⁇ m, etc. Regarding the size and shape of the cavity 103, the thickness of the top silicon 102, etc., there are no excessive restrictions here.
  • step S1 - 2 is performed to perform ion implantation to form an N-type thermocouple layer 201 and a P-type thermocouple layer 202 in the top silicon 102 above the cavity 103 .
  • N-type ion implantation can be performed first to create the N-type thermocouple layer 201 above the cavity 103 on the top silicon 102; and then P-type ion implantation is completed to form the N-type thermocouple layer 201 on the top layer of silicon 102.
  • a P-type thermocouple layer 202 located above the cavity 103 is fabricated on the silicon 102 .
  • the electrical isolation between the formed N-type thermocouple layer 201 and the P-type thermocouple layer 202 is performed by the non-doped high-resistance top layer silicon 102 .
  • step S1 - 3 is performed to form a metal interconnection layer 300 connected to the N-type thermocouple layer 201 and the P-type thermocouple layer 202 .
  • the production of passivation layers (not shown), metal lead holes (not shown), and metal layer deposition can be continued.
  • Preparation steps are performed to form the metal interconnection layer 300 to produce a complete pyroelectric infrared sensor.
  • 4 shows a schematic diagram of the connection between the metal interconnection layer 300 and the N-type thermocouple layer 201 and P-type thermocouple layer 202 in the thermoelectric infrared sensor.
  • the metal interconnection layer 300 and the N-type thermocouple layer 202 are connected to each other.
  • the positional relationship between the thermocouple layer 201 and the P-type thermocouple layer 202 is not limited to this.
  • the type of the passivation layer the type and preparation of the metal layer, no details are given here, and the existing relatively conventional preparation process can be used.
  • the step of forming a CMOS circuit structure in the SON substrate 100 may also be included, wherein the source and drain doped regions in the CMOS circuit structure may be formed synchronously with the corresponding thermocouple layers respectively.
  • the CMOS circuit structure The metal layer in may be formed simultaneously with the metal interconnection layer 300 .
  • the metal interconnection layer 300 can be understood as a CMOS circuit structure area to achieve monolithic integration of the pyroelectric infrared sensor and the CMOS circuit structure in the SON substrate 100, and in When preparing the N-type thermocouple layer 201, N-type ion implantation can be completed simultaneously with the N-type doped region in the CMOS circuit structure, and when preparing the P-type thermocouple layer 202, P-type ion implantation can also be completed. It can be completed synchronously with the P-type doped region in the CMOS circuit structure.
  • the metal interconnection layer 300 in the pyroelectric infrared sensor can also be completed synchronously with the metal layer in the CMOS circuit structure, so that the The monolithic integration of the pyroelectric infrared sensor and the CMOS circuit structure is completed in the SON substrate 100, achieving good preparation convenience and compatibility, but the preparation method is not limited to this.
  • the N-type thermocouple layer 201, the The P-type thermocouple layer 202, the metal interconnection layer 300, and the doped source and drain regions and metal layers in the CMOS circuit structure can also be prepared separately, and are not overly limited here.
  • this embodiment also provides a SON-based pyroelectric infrared sensor.
  • the pyroelectric infrared sensor includes:
  • the SON substrate 100 includes a substrate silicon 101, a top layer of silicon 102, and a cavity 103 located between the substrate silicon 101 and the top layer of silicon 102;
  • N-type thermocouple layer 201 and P-type thermocouple layer 202, the N-type thermocouple layer 201 and the P-type thermocouple layer 202 are located in the top silicon 102 above the cavity 103;
  • Metal interconnection layer 300 is connected to the N-type thermocouple layer 201 and the P-type thermocouple layer 202.
  • the cavity 103 may include an air cavity or a vacuum cavity, where, when it is a vacuum cavity, the vacuum degree is between 10 -3 and 10 Pa; the size of a single cavity 103 is less than 500 ⁇ 500 ⁇ m 2 ; The depth of the cavity 103 is 1 to 400 ⁇ m; the thickness of the top silicon formed is 0.5 to 5 ⁇ m.
  • the cavity 103 in this embodiment is a vacuum cavity to further reduce thermal convection losses, thereby improving the performance of the subsequently prepared pyroelectric infrared sensor.
  • the cavity can be
  • the cavity 103 can also be an air cavity, which can be selected according to needs.
  • the vacuum degree of the vacuum cavity is between 10 -3 and 10 Pa, such as 10 -3 Pa, 1 Pa, 10 Pa, etc.; the size of a single cavity 103 is less than 500 ⁇ 500 ⁇ m 2 , such as 400 ⁇ 400 ⁇ m. 2 , 300 ⁇ 300 ⁇ m 2 , etc.; the depth of the cavity 103 can be 1-400 ⁇ m, such as 1 ⁇ m, 10 ⁇ m, 100 ⁇ m, 400 ⁇ m, etc.; so that the vacuum cavity can avoid excessive deformation of the top silicon 102 , affecting subsequent micromachining processes.
  • the thickness of the top silicon 102 may be 0.5-5 ⁇ m, such as 0.5 ⁇ m, 1 ⁇ m, 2 ⁇ m, 5 ⁇ m, etc. Regarding the size and shape of the cavity 103, the thickness of the top silicon 102, etc., there are no excessive restrictions here.
  • the SON substrate 100 further includes a CMOS circuit structure, wherein the source and drain doped regions in the CMOS circuit structure are made of the same material as the corresponding thermocouple layer, and the metal layer in the CMOS circuit structure is made of the same material as the corresponding thermocouple layer.
  • the metal interconnection layers are made of the same material. For details, please refer to the preparation of the CMOS circuit structure, which will not be described again here.
  • this embodiment also provides another SON-based pyroelectric infrared sensor and a preparation method.
  • the main difference between the pyroelectric infrared sensor and the pyroelectric infrared sensor in the first embodiment is that :
  • the SON substrate 100 further includes a silicon oxide layer 104 located between the substrate silicon 101 and the top silicon 102 , and the cavity 103 is located below the silicon oxide layer 104 .
  • the steps of forming the pyroelectric infrared sensor may include:
  • step S2-1 is performed: forming a SON substrate 100.
  • the SON substrate 100 includes a substrate silicon 101, a top layer of silicon 102, and a silicon oxide layer 104 located between the substrate silicon 101 and the top layer of silicon 102. , and the cavity 103 located under the silicon oxide layer 104.
  • the silicon oxide layer 104 can be made using an oxidation process, and the thickness of the formed silicon oxide layer 104 can be 0.01-2 ⁇ m, such as 0.01 ⁇ m, 1 ⁇ m, 2 ⁇ m, etc.
  • the method of forming the SON substrate 100 may include a bonding method or an epitaxial method. For details, please refer to Embodiment 1, which will not be described in detail here.
  • step S2-2 perform ion implantation to form an N-type thermocouple layer 201 and a P-type thermocouple layer 202 in the top silicon 102 above the cavity 103. This step can be performed at the same time.
  • Example 1
  • step S2-3 is performed: forming a metal interconnection layer 300 connected to the N-type thermocouple layer 201 and the P-type thermocouple layer 202. This step can be the same as the first embodiment.
  • step S2-4 is performed: removing the top layer of silicon 102 to form a recess exposing the silicon oxide layer 104 between the N-type thermocouple layer 201 and the P-type thermocouple layer 202 . groove.
  • the area of the top silicon 102 that has not been ion implanted can be etched to expose the silicon oxide layer 104, so that the N-type thermocouple layer 201 and the P-type thermocouple layer 202 pass through the The silicon oxide layer 104 is used for isolation.
  • Figure 9 it is schematically shown that in the thermoelectric infrared sensor, the metal interconnection layer 300 and the N-type thermocouple layer 201 and P
  • the connection relationship between the N-type thermocouple layer 202 and the N-type thermocouple layer 201 and the P-type thermocouple layer 202 is not limited to this.
  • the step of forming a CMOS circuit structure in the SON substrate 100 may also be included, wherein the source and drain doping regions in the CMOS circuit structure are formed simultaneously with the corresponding thermocouple layers.
  • the metal layer is formed simultaneously with the metal interconnection layer.
  • the metal interconnection layer 300 can be understood as a CMOS circuit structure area to achieve monolithic integration of the pyroelectric infrared sensor and the CMOS circuit structure in the SON substrate 100, and in When preparing the N-type thermocouple layer 201, N-type ion implantation can be completed simultaneously with the N-type doped region in the CMOS circuit structure, and when preparing the P-type thermocouple layer 202, P-type ion implantation can also be completed. It can be completed synchronously with the P-type doped region in the CMOS circuit structure.
  • the metal interconnection layer 300 in the pyroelectric infrared sensor can also be completed synchronously with the metal layer in the CMOS circuit structure, so that the The monolithic integration of the pyroelectric infrared sensor and the CMOS circuit structure is completed in the SON substrate 100, achieving good preparation convenience and compatibility, but the preparation method is not limited to this.
  • the N-type thermocouple layer 201, the The P-type thermocouple layer 202, the metal interconnection layer 300, and the doped source and drain regions and metal layers in the CMOS circuit structure can also be prepared separately, and are not overly limited here.
  • this embodiment also provides a SON-based pyroelectric infrared sensor.
  • the pyroelectric infrared sensor includes:
  • the SON substrate 100 includes a substrate silicon 101, a top silicon 102, a silicon oxide layer 104 located between the substrate silicon 101 and the top silicon 102, and a silicon oxide layer 104 located below the silicon oxide layer 104. cavity 103;
  • N-type thermocouple layer 201 and P-type thermocouple layer 202, the N-type thermocouple layer 201 and the P-type thermocouple layer 202 are located in the top silicon 102 above the cavity 103;
  • Metal interconnection layer 300 is connected to the N-type thermocouple layer 201 and the P-type thermocouple layer 202.
  • Embodiment 1 Regarding the structure and preparation of the pyroelectric infrared sensor, please refer to Embodiment 1 and will not be described in detail here.
  • the SON-based thermoelectric infrared sensor and preparation method of the present invention use SON technology to prefabricate the SON substrate with a cavity, which avoids the release process of the thermopile structure, thereby simplifying the manufacturing process; based on the SON substrate
  • the suspended top-layer silicon is used to make a thermocouple structure, which avoids the separate deposition of thermoelectric materials and can take advantage of the high Seebeck coefficient of the top-layer silicon.
  • the SON substrate can include CMOS circuit structures, doped thermocouple layers and metal interconnection layers.
  • thermopile structures are prepared simultaneously with the doped regions and metal layers in the CMOS circuit structure, thus having good preparation convenience and compatibility; the prefabricated sealed vacuum cavity in the SON substrate can reduce thermal convection losses and is not required in the subsequent packaging process. Carrying out vacuum requirements; the thermopile structure is prepared on the top silicon of the SON substrate, and the entire thermopile suspension structure is a closed membrane structure without an opening structure, thereby improving the mechanical strength of the thermopile suspension structure; the present invention can be applied to thermopile Small structural dimensions as well as thermopile and CMOS circuit integrated devices.

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Abstract

本发明提供一种基于SON的热电红外传感器及制备方法，采用SON技术预制带有空腔的SON基底，避免了热电堆结构的释放工艺，从而简化了制作工艺；基于SON基底中的悬浮顶层硅制作热电偶结构，避免了热电材料的单独沉积，并且可利用顶层硅的塞贝克系数高的优点，SON基底中的CMOS电路结构的掺杂区及金属层均可分别与掺杂热电偶层及金属互联层同时制备，从而具有良好的制备便捷性及兼容性；SON基底中预制的密封真空腔，可减少热对流损耗，且在后续封装工艺中无需进行真空要求；整个热电堆悬浮结构为封闭膜结构，可提高热电堆悬浮结构的机械强度；本发明可适用于热电堆结构尺寸小及热电堆和CMOS电路集成的器件。

Description

基于SON的热电红外传感器及制备方法 技术领域
本发明属于半导体领域，涉及一种基于SON的热电红外传感器及制备方法。
背景技术
微机电系统(Micro-Electro-Mechanical-System，MEMS)技术是指一种可将机械构件、驱动部件、光学系统、电控系统集成为一个整体的微型系统，它采用微电子技术和微加工技术，如硅体微加工、硅表面微加工、晶片键合等相结合的制造工艺，制造出各种性能优异、价格低廉、微型化的传感器、执行器、驱动器和微系统。
基于MEMS技术的热电红外传感器，其中央是红外吸收层，负责吸收外界红外辐射，以升高自身的温度，红外吸收层附近位置构成热结，冷结则位于散热衬底上，且热节悬浮于衬底中的空腔上，以实现良好的散热性，热结与冷结之间为串联的热电堆结构，温差电动势通过引脚对外输出，从而构成一种可串联多个热电堆结构且无接触测量温度差的传感器。
现有的热电红外传感器一般都是先进行热电堆结构的制作，最后再形成空腔以进行热电堆悬浮结构的释放，热电堆结构尺寸越小，释放工艺难度越大，对于集成了CMOS电路结构的热电堆结构，释放工艺还需要考虑和CMOS工艺的兼容性，并且需要精确控制腐蚀精度，以避免CMOS电路区被腐蚀；而为了减小热电堆结构的热对流损耗，热电红外传感器一般要求进行气密封装，尤其对于热电红外传感器阵列，因为热电堆结构尺寸较小，热电堆悬浮结构的释放难度更大，并且需要真空封装以减小热电堆传感器的热对流损耗。
因此，提供一种新的热电红外传感器及制备方法，以解决上述问题，实属必要。
发明内容
鉴于以上所述现有技术的缺点，本发明的目的在于提供一种基于SON的热电红外传感器及制备方法，用于解决现有技术的热电红外传感器所面临的上述一系列制备问题。
为实现上述目的及其他相关目的，本发明提供一种基于SON的热电红外传感器的制备方法，包括以下步骤：
形成SON基底，所述SON基底包括衬底硅、顶层硅，以及位于所述衬底硅与所述顶层硅之间的空腔；
进行离子注入，于所述空腔上方的所述顶层硅中分别形成N型热电偶层及P型热电偶层；
形成与所述N型热电偶层及P型热电偶层相连接的金属互联层。
可选地，形成所述SON基底的方法包括键合法或外延法。
可选地，形成的所述空腔包括空气空腔或真空空腔，其中，当为真空空腔时，真空度介于10-3～10Pa；单个所述空腔的尺寸小于500×500μm2；所述空腔的深度为1～400μm；形成的所述顶层硅的厚度为0.5～5μm。
可选地，所述N型热电偶层与所述P型热电偶层之间通过所述顶层硅进行隔离。
可选地，形成的所述SON基底中，还包括位于所述衬底硅与所述顶层硅之间的氧化硅层，且所述空腔位于所述氧化硅层下方。
可选地，还包括去除所述顶层硅的步骤，以在所述N型热电偶层与所述P型热电偶层之间形成显露所述氧化硅层的凹槽，且所述N型热电偶层与所述P型热电偶层通过所述氧化硅层进行隔离。
可选地，所述氧化硅层通过氧化工艺制作；形成的所述氧化硅层的厚度为0.01～2μm。
可选地，包括于所述SON基底中形成CMOS电路结构的步骤，其中，所述CMOS电路结构中的源漏掺杂区分别与对应的热电偶层同步形成，所述CMOS电路结构中的金属层与所述金属互联层同步形成。
本发明还提供一种基于SON的热电红外传感器，所述热电红外传感器包括：
SON基底，所述SON基底包括衬底硅、顶层硅，以及位于所述衬底硅与所述顶层硅之间的空腔；
N型热电偶层及P型热电偶层，所述N型热电偶层及所述P型热电偶层位于所述空腔上方的所述顶层硅中；
金属互联层，所述金属互联层与所述N型热电偶层及P型热电偶层相连接。
可选地，所述空腔包括空气空腔或真空空腔，其中，当为真空空腔时，真空度介于10-3～10Pa；单个所述空腔的尺寸小于500×500μm2；所述空腔的深度为1～400μm；形成的所述顶层硅的厚度为0.5～5μm。
可选地，所述SON基底中，还包括位于所述衬底硅与所述顶层硅之间的氧化硅层，且所述空腔位于所述氧化硅层下方；所述氧化硅层的厚度为0.01～2μm。
可选地，所述SON基底中，还包括CMOS电路结构，其中，所述CMOS电路结构中的源漏掺杂区与对应的热电偶层同材质，所述CMOS电路结构中的金属层与所述金属互联层同材质。
如上所述，本发明的基于SON的热电红外传感器及制备方法，采用SON技术预制带有空腔的SON基底，避免了热电堆结构的释放工艺，从而简化了制作工艺；基于SON基底中 的悬浮顶层硅制作热电偶结构，避免了热电材料的单独沉积，并且可利用顶层硅的塞贝克系数高的优点，且SON基底中可包括CMOS电路结构，掺杂热电偶层及金属互联层均可分别与CMOS电路结构中的掺杂区及金属层同时制备，从而具有良好的制备便捷性及兼容性；SON基底中预制的密封真空腔，可减少热对流损耗，且在后续封装工艺中可无需进行真空要求；热电堆结构是在SON基底的顶层硅上制备，整个热电堆悬浮结构为封闭膜结构，无开孔结构，从而可提高热电堆悬浮结构的机械强度；本发明可适用于热电堆结构尺寸小以及热电堆和CMOS电路集成的器件。
附图说明
图1显示为本发明实施例一中SON基底的结构示意图。
图2显示为本发明实施例一中进行离子注入形成N型热电偶层及P型热电偶层后的结构示意图。
图3显示为本发明实施例一中形成金属互联层后的结构示意图。
图4显示为本发明实施例一中形成的热电红外传感器的局部俯视图。
图5显示为本发明实施例二中SON基底的结构示意图。
图6显示为本发明实施例二中进行离子注入形成N型热电偶层及P型热电偶层后的结构示意图。
图7显示为本发明实施例二中形成金属互联层后的结构示意图。
图8显示为本发明实施例二中去除顶层硅形成凹槽后的结构示意图。
图9显示为本发明实施例二中形成的热电红外传感器的局部俯视图。
元件标号说明
100                    SON基底
101                    衬底硅
102                    顶层硅
103                    空腔
104                    氧化硅层
201                    N型热电偶层
202                    P型热电偶层
300                    金属互联层
具体实施方式
以下通过特定的具体实例说明本发明的实施方式，本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本发明的精神下进行各种修饰或改变。
如在详述本发明实施例时，为便于说明，表示器件结构的剖面图会不依一般比例作局部放大，而且所述示意图只是示例，其在此不应限制本发明保护的范围。此外，在实际制作中应包含长度、宽度及深度的三维空间尺寸。
为了方便描述，此处可能使用诸如“之下”、“下方”、“低于”、“下面”、“上方”、“上”等的空间关系词语来描述附图中所示的一个元件或特征与其他元件或特征的关系。将理解到，这些空间关系词语意图包含使用中或操作中的器件的、除了附图中描绘的方向之外的其他方向。此外，当一层被称为在两层“之间”时，它可以是所述两层之间仅有的层，或者也可以存在一个或多个介于其间的层。
在本申请的上下文中，所描述的第一特征在第二特征“之上”的结构可以包括第一和第二特征形成为直接接触的实施例，也可以包括另外的特征形成在第一和第二特征之间的实施例，这样第一和第二特征可能不是直接接触。
需要说明的是，本实施例中所提供的图示仅以示意方式说明本发明的基本构想，遂图示中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制，其实际实施时各组件的型态、数量及比例可为一种随意的改变，其组件布局型态也可能更为复杂。
实施例一
如图1～图4，本实施例提供一种基于SON的热电红外传感器的制备方法，包括以下步骤：
S1-1：形成SON基底100，所述SON基底100包括衬底硅101、顶层硅102，以及位于所述衬底硅101与所述顶层硅102之间的空腔103；
S1-2：进行离子注入，于所述空腔103上方的所述顶层硅102中分别形成N型热电偶层201及P型热电偶层202；
S1-3：形成与所述N型热电偶层201及P型热电偶层202相连接的金属互联层300。
首先，如图1，执行步骤S1-1，形成SON基底100，所述SON基底100包括衬底硅101、顶层硅102，以及位于所述衬底硅101与所述顶层硅102之间的空腔103。其中，所述顶层硅102的材质可为单晶硅，以便于后续基于所述顶层硅102利用顶层单晶硅的塞贝克系数高的优点，制备高性能的所述热电红外传感器。本实施例采用SON技术预先制备带有所述空腔 103的所述SON基底100，可避免后续热电堆结构制备时的释放工艺，从而可简化制作工艺。
作为示例，形成所述SON基底100的方法可包括键合法或外延法。
具体的，形成所述SON基底100的方法可包括键合法或外延法，如提供所述衬底硅101，通过刻蚀所述衬底硅101形成所述空腔103，通过键合及智能剥离的方式形成位于所述衬底硅101上的所述顶层硅102；或者先提供所述衬底硅101，通过刻蚀所述衬底硅101形成间隔沟槽后，在所述衬底硅101上采用外延法形成所述顶层硅102，以及将所述沟槽转化为所述空腔103。关于所述SON基底100的制备方法此处不作过分限制，具体可根据需要进行选择。
作为示例，形成的所述空腔103可包括空气空腔或真空空腔，其中，当为真空空腔时，真空度介于10-3～10Pa；单个所述空腔103的尺寸小于500×500μm2；所述空腔103的深度为1～400μm；形成的所述顶层硅的厚度为0.5～5μm。
具体的，当形成的所述空腔103为真空空腔时，可进一步的减少热对流损耗，从而提供后续制备的所述热电红外传感器的性能，但并非局限于此，根据需要，所述空腔103也可为空气空腔，具体可根据需要进行选择。
本实施例中，所述真空空腔的真空度介于10-3～10Pa，如10-3Pa、1Pa、10Pa等；单个所述空腔103的尺寸小于500×500μm2、如400×400μm2、300×300μm2等；所述空腔103的深度可为1～400μm，如1μm、10μm、100μm、400μm等；以使得所述真空空腔可避免对所述顶层硅102造成形变过大，影响后续微加工工艺。其中，形成的所述顶层硅102的厚度可为0.5～5μm，如0.5μm、1μm、2μm、5μm等。关于所述空腔103的尺寸、形貌、顶层硅102的厚度等，此处不作过分限制。
接着，如图2，执行步骤S1-2，进行离子注入，于所述空腔103上方的所述顶层硅102中分别形成N型热电偶层201及P型热电偶层202。
具体的，可先进行N型离子注入，以在所述顶层硅102上制作出位于所述空腔103上方的所述N型热电偶层201；而后完成P型离子注入，以在所述顶层硅102上制作出位于所述空腔103上方的P型热电偶层202。关于所述N型离子注入及P型离子注入的先后顺序此处不作限制。
本实施例中，如图2，形成的所述N型热电偶层201及所述P型热电偶层202之间的电隔离是通过非掺杂的高阻的所述顶层硅102进行隔离。
接着，如图3，执行步骤S1-3，形成与所述N型热电偶层201及P型热电偶层202相连接的金属互联层300。
具体的，可继续进行有关钝化层(未图示)、金属引线孔(未图示)以及金属层沉积等制 备步骤，以形成所述金属互联层300，制作出完整的热电红外传感器。如图4示意了所述热电红外传感器中，所述金属互联层300与所述N型热电偶层201及P型热电偶层202的连接示意图，但所述金属互联层300与所述N型热电偶层201及P型热电偶层202的位置关系并非局限于此。关于所述钝化层的种类、金属层的种类及制备，此处不作赘述，可采用现有较为常规的制备工艺。
作为示例，还可包括于所述SON基底100中形成CMOS电路结构的步骤，其中，所述CMOS电路结构中的源漏掺杂区可分别与对应的热电偶层同步形成，所述CMOS电路结构中的金属层可与所述金属互联层300同步形成。
具体的，如图3中，所述金属互联层300，可理解为CMOS电路结构区，以在所述SON基底100中实现所述热电红外传感器与所述CMOS电路结构的单片集成，且在制备所述N型热电偶层201时，N型离子注入可以和所述CMOS电路结构中的N型掺杂区同步完成，以及在制备所述P型热电偶层202时，P型离子注入也可以和所述CMOS电路结构中的P型掺杂区同步完成，当然，所述热电红外传感器中的所述金属互联层300也可以和所述CMOS电路结构中的金属层同步完成，从而在所述SON基底100中完成所述热电红外传感器与所述CMOS电路结构的单片集成，实现良好的制备便捷性及兼容性，但制备方法并非局限于此，所述N型热电偶层201、所述P型热电偶层202、金属互联层300及所述CMOS电路结构中的掺杂源漏区及金属层也可均单独制备，此处不作过分限制。
如图3，本实施例还提供一种基于SON的热电红外传感器，所述热电红外传感器包括：
SON基底100，所述SON基底100包括衬底硅101、顶层硅102，以及位于所述衬底硅101与所述顶层硅102之间的空腔103；
N型热电偶层201及P型热电偶层202，所述N型热电偶层201及所述P型热电偶层202位于所述空腔103上方的所述顶层硅102中；
金属互联层300，所述金属互联层300与所述N型热电偶层201及P型热电偶层202相连接。
作为示例，所述空腔103可包括空气空腔或真空空腔，其中，当为真空空腔时，真空度介于10-3～10Pa；单个所述空腔103的尺寸小于500×500μm2；所述空腔103的深度为1～400μm；形成的所述顶层硅的厚度为0.5～5μm。
具体的，本实施例中所述空腔103为真空空腔，以进一步的减少热对流损耗，从而提供后续制备的所述热电红外传感器的性能，但并非局限于此，根据需要，所述空腔103也可为空气空腔，具体可根据需要进行选择。
本实施例中，所述真空空腔的真空度介于10-3～10Pa，如10-3Pa、1Pa、10Pa等；单个所述空腔103的尺寸小于500×500μm2、如400×400μm2、300×300μm2等；所述空腔103的深度可为1～400μm，如1μm、10μm、100μm、400μm等；以使得所述真空空腔可避免对所述顶层硅102造成形变过大，影响后续微加工工艺。其中，所述顶层硅102的厚度可为0.5～5μm，如0.5μm、1μm、2μm、5μm等。关于所述空腔103的尺寸、形貌、顶层硅102的厚度等，此处不作过分限制。
作为示例，所述SON基底100中，还包括CMOS电路结构，其中，所述CMOS电路结构中的源漏掺杂区与对应的热电偶层同材质，所述CMOS电路结构中的金属层与所述金属互联层同材质，具体可参阅所述CMOS电路结构的制备，此处不作赘述。
实施例二
如图5～图9，本实施例还提供另一种基于SON的热电红外传感器及制备方法，本实施例中，所述热电红外传感器与实施例一种的所述热电红外传感器的区别主要在于：所述SON基底100中，还包括位于所述衬底硅101与所述顶层硅102之间的氧化硅层104，且所述空腔103位于所述氧化硅层104下方。
具体的，形成所述热电红外传感器的步骤可包括：
如图5，执行步骤S2-1：形成SON基底100，所述SON基底100包括衬底硅101、顶层硅102、位于所述衬底硅101与所述顶层硅102之间的氧化硅层104，以及位于所述氧化硅层104下方的空腔103。
具体的，可采用氧化工艺制作所述氧化硅层104，且形成的所述氧化硅层104的厚度可为0.01～2μm，如0.01μm、1μm、2μm等。形成所述SON基底100的方法可包括键合法或外延法，具体可参阅实施例一，此处不作赘述。
接着，如图6，执行步骤S2-2：进行离子注入，于所述空腔103上方的所述顶层硅102中分别形成N型热电偶层201及P型热电偶层202，此步骤可同实施例一。
接着，如图7，执行步骤S2-3：形成与所述N型热电偶层201及P型热电偶层202相连接的金属互联层300，此步骤可同实施例一。
接着，如图8，执行步骤S2-4：去除所述顶层硅102，以在所述N型热电偶层201与所述P型热电偶层202之间形成显露所述氧化硅层104的凹槽。
具体的，可将所述顶层硅102中未进行离子注入的区域进行刻蚀，以显露所述氧化硅层104，使得所述N型热电偶层201与所述P型热电偶层202通过所述氧化硅层104进行隔离。如图9，示意了所述热电红外传感器中，所述金属互联层300与所述N型热电偶层201及P 型热电偶层202的连接关系，但所述金属互联层300与所述N型热电偶层201及P型热电偶层202的位置关系并非局限于此。
作为示例，还可包括于所述SON基底100中形成CMOS电路结构的步骤，其中，所述CMOS电路结构中的源漏掺杂区分别与对应的热电偶层同步形成，所述CMOS电路结构中的金属层与所述金属互联层同步形成。
具体的，如图8中，所述金属互联层300，可理解为CMOS电路结构区，以在所述SON基底100中实现所述热电红外传感器与所述CMOS电路结构的单片集成，且在制备所述N型热电偶层201时，N型离子注入可以和所述CMOS电路结构中的N型掺杂区同步完成，以及在制备所述P型热电偶层202时，P型离子注入也可以和所述CMOS电路结构中的P型掺杂区同步完成，当然，所述热电红外传感器中的所述金属互联层300也可以和所述CMOS电路结构中的金属层同步完成，从而在所述SON基底100中完成所述热电红外传感器与所述CMOS电路结构的单片集成，实现良好的制备便捷性及兼容性，但制备方法并非局限于此，所述N型热电偶层201、所述P型热电偶层202、金属互联层300及所述CMOS电路结构中的掺杂源漏区及金属层也可均单独制备，此处不作过分限制。
如图8，本实施例还提供一种基于SON的热电红外传感器，所述热电红外传感器包括：
SON基底100，所述SON基底100包括衬底硅101、顶层硅102、位于所述衬底硅101与所述顶层硅102之间的氧化硅层104，以及位于所述氧化硅层104下方的空腔103；
N型热电偶层201及P型热电偶层202，所述N型热电偶层201及所述P型热电偶层202位于所述空腔103上方的所述顶层硅102中；
金属互联层300，所述金属互联层300与所述N型热电偶层201及P型热电偶层202相连接。
关于所述热电红外传感器的结构及制备，均可参阅实施例一，此处不作赘述。
综上所述，本发明的基于SON的热电红外传感器及制备方法，采用SON技术预制带有空腔的SON基底，避免了热电堆结构的释放工艺，从而简化了制作工艺；基于SON基底中的悬浮顶层硅制作热电偶结构，避免了热电材料的单独沉积，并且可利用顶层硅的塞贝克系数高的优点，且SON基底中可包括CMOS电路结构，掺杂热电偶层及金属互联层均可分别与CMOS电路结构中的掺杂区及金属层同时制备，从而具有良好的制备便捷性及兼容性；SON基底中预制的密封真空腔，可减少热对流损耗，且在后续封装工艺中可无需进行真空要求；热电堆结构是在SON基底的顶层硅上制备，整个热电堆悬浮结构为封闭膜结构，无开孔结构，从而可提高热电堆悬浮结构的机械强度；本发明可适用于热电堆结构尺寸小以及热电堆和 CMOS电路集成的器件。
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改变。因此，举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本发明的权利要求所涵盖。

Claims (12)

  1. 一种基于SON的热电红外传感器的制备方法，其特征在于，包括以下步骤：
    形成SON基底，所述SON基底包括衬底硅、顶层硅，以及位于所述衬底硅与所述顶层硅之间的空腔；
    进行离子注入，于所述空腔上方的所述顶层硅中分别形成N型热电偶层及P型热电偶层；
    形成与所述N型热电偶层及P型热电偶层相连接的金属互联层。
  2. 根据权利要求1所述的基于SON的热电红外传感器的制备方法，其特征在于：形成所述SON基底的方法包括键合法或外延法。
  3. 根据权利要求1所述的基于SON的热电红外传感器的制备方法，其特征在于：形成的所述空腔包括空气空腔或真空空腔，其中，当为真空空腔时，真空度介于10-3～10Pa；单个所述空腔的尺寸小于500×500μm2；所述空腔的深度为1～400μm；形成的所述顶层硅的厚度为0.5～5μm。
  4. 根据权利要求1所述的基于SON的热电红外传感器的制备方法，其特征在于：所述N型热电偶层与所述P型热电偶层之间通过所述顶层硅进行隔离。
  5. 根据权利要求1所述的基于SON的热电红外传感器的制备方法，其特征在于：形成的所述SON基底中，还包括位于所述衬底硅与所述顶层硅之间的氧化硅层，且所述空腔位于所述氧化硅层下方。
  6. 根据权利要求5所述的基于SON的热电红外传感器的制备方法，其特征在于：还包括去除所述顶层硅的步骤，以在所述N型热电偶层与所述P型热电偶层之间形成显露所述氧化硅层的凹槽，且所述N型热电偶层与所述P型热电偶层通过所述氧化硅层进行隔离。
  7. 根据权利要求6所述的基于SON的热电红外传感器的制备方法，其特征在于：所述氧化硅层通过氧化工艺制作；形成的所述氧化硅层的厚度为0.01～2μm。
  8. 根据权利要求1所述的基于SON的热电红外传感器的制备方法，其特征在于：包括于所述SON基底中形成CMOS电路结构的步骤，其中，所述CMOS电路结构中的源漏掺杂 区分别与对应的热电偶层同步形成，所述CMOS电路结构中的金属层与所述金属互联层同步形成。
  9. 一种基于SON的热电红外传感器，其特征在于，所述热电红外传感器包括：
    SON基底，所述SON基底包括衬底硅、顶层硅，以及位于所述衬底硅与所述顶层硅之间的空腔；
    N型热电偶层及P型热电偶层，所述N型热电偶层及所述P型热电偶层位于所述空腔上方的所述顶层硅中；
    金属互联层，所述金属互联层与所述N型热电偶层及P型热电偶层相连接。
  10. 根据权利要求9所述的基于SON的热电红外传感器，其特征在于：所述空腔包括空气空腔或真空空腔，其中，当为真空空腔时，真空度介于10-3～10Pa；单个所述空腔的尺寸小于500×500μm2；所述空腔的深度为1～400μm；形成的所述顶层硅的厚度为0.5～5μm。
  11. 根据权利要求9所述的基于SON的热电红外传感器，其特征在于：所述SON基底中，还包括位于所述衬底硅与所述顶层硅之间的氧化硅层，且所述空腔位于所述氧化硅层下方；所述氧化硅层的厚度为0.01～2μm。
  12. 根据权利要求9所述的基于SON的热电红外传感器，其特征在于：所述SON基底中，还包括CMOS电路结构，其中，所述CMOS电路结构中的源漏掺杂区与对应的热电偶层同材质，所述CMOS电路结构中的金属层与所述金属互联层同材质。
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