WO2023240683A1 - Test device, failure analysis method and test system - Google Patents

Abstract

A test device (10), a failure analysis method and a test system. The test device (10) comprises a chip carrier (101) and a support base (102) used for supporting the chip carrier (101), wherein a comparison module (103) and an adjustable resistor module (104) are provided in the support base (102); the chip carrier (101) is used for bearing a chip (20) under test; and the comparison module (103) is connected to the adjustable resistor module (104) and is used for comparing the grounding voltage of a layer to be tested in said chip (20) with the grounding voltage of the chip carrier (101), and adjusting the grounding resistance of said layer according to a comparison result and by means of the adjustable resistor module (104), such that the surface charging effect of said layer is reduced.

Description

Test equipment, failure analysis method and test system

Related cross-references

This disclosure is based on the Chinese patent application with the application number 202210692461.4, the filing date is June 17, 2022, and the invention name is "a testing equipment, failure analysis method and testing system", and claims the priority of the Chinese patent application, The entire content of this Chinese patent application is hereby incorporated by reference into this disclosure.

Technical field

The present disclosure relates to the technical field of integrated circuit failure analysis, and in particular to a testing device, a failure analysis method and a testing system.

Background technique

As the critical dimensions of chips continue to shrink, the interconnection and integration of metals inside the chip is getting higher and higher. Whether it is between the same layer of metal or between different metal layers, the isolation material is getting thinner and thinner, resulting in the occurrence of Various failure phenomena, such as: short circuit, open circuit, micro leakage or high resistance, etc.

When analyzing these failure phenomena of the metal layer, for short circuits or open circuits, obvious abnormalities can be observed through optical or electron microscopes; for micro leaks or high resistance, such failures usually appear as very small gaps between metal lines. It is difficult to locate the failure location due to tiny broken wires; the Electron Beam Absorbed Current (EBAC) function of the nanoprobe is an effective positioning technology for micro-leakage and high resistance.

Contents of the invention

Embodiments of the present disclosure provide a testing device, a failure analysis method and a testing system:

In a first aspect, an embodiment of the present disclosure provides a test equipment. The test equipment includes a chip carrier and a support base for supporting the chip carrier, and a comparison module and an adjustable resistor are provided in the support base. module; where:

The chip carrier is used to carry the chip under test;

The comparison module is connected to the adjustable resistance module and is used to compare the ground voltage of the layer to be tested in the chip under test with the ground voltage of the chip carrier. According to the comparison result and the adjustable resistance The module adjusts the ground resistance of the layer to be tested to reduce the surface charging effect of the layer to be tested.

In some embodiments, the support base is further provided with a first metal probe and a second metal probe; wherein:

One end of the first metal probe is connected to the first input end of the comparison module, and the other end of the first metal probe is connected to the ground point on the layer to be tested for obtaining the The ground voltage of the layer;

One end of the second metal probe is connected to the second input end of the comparison module, and the other end of the second metal probe is connected to the ground point on the chip carrier for obtaining the information on the chip carrier. The ground voltage of the station.

In some embodiments, the first metal probe and the second metal probe each independently comprise a nanoprobe.

In some embodiments, the support base is also provided with a first signal test unit and a second signal test unit; wherein:

The first signal test unit is used to measure the ground voltage of the layer to be tested through the first metal probe, and provide the measured ground voltage of the layer to be tested to the first part of the comparison module. input terminal;

The second signal test unit is used to measure the ground voltage of the chip carrier through the second metal probe, and provide the measured ground voltage of the chip carrier to the second component of the comparison module. input terminal;

Wherein, the first signal test unit is connected between one end of the first metal probe and the first input end of the comparison module, and the second signal test unit is connected between one end of the second metal probe and Between one end and the second input end of the comparison module.

In some embodiments, the adjustable resistance module is used to control the adjustable resistance module to correspond to the voltage difference between the ground voltage of the layer to be tested and the ground voltage of the chip carrier. The resistance value is adjusted to the ground resistance value corresponding to the voltage difference.

In some embodiments, there is a corresponding relationship between the voltage difference and the ground resistance; where:

If the voltage difference increases, the ground resistance decreases;

If the voltage difference decreases, the ground resistance increases.

In some embodiments, the chip under test includes at least one metal layer and at least one dielectric layer, and the at least one metal layer includes the layer under test; wherein:

The comparison module is also configured to perform a differential comparison based on the ground voltage of the layer to be tested and the ground voltage of the chip carrier, so as to reduce the difference between the layer to be tested and the chip carrier in the chip under test. Interference signals generated by the metal layers and dielectric layers contained between them.

In some embodiments, the comparison module includes a first operational amplifier, a second operational amplifier, a first transistor, a second transistor, a first resistor, a second resistor, and a third transistor, and the adjustable resistance module includes an adjustable Resistor; where:

The negative input terminal of the first operational amplifier is connected to the ground point on the layer to be tested, and the positive input terminal of the second operational amplifier is connected to the ground point on the chip carrier. The positive input terminal of the operational amplifier is connected to the negative input terminal of the second operational amplifier;

The output terminal of the first operational amplifier is connected to the input terminal of the first transistor, and the output terminal of the second operational amplifier is connected to the input terminal of the second transistor;

The output terminal of the first transistor is connected to the output terminal of the second transistor and connected to the first terminal of the first resistor;

The first end of the second resistor is connected to the input end of the third transistor, and the second end of the first resistor, the second end of the second resistor and the output end of the third transistor are all connected. At the output end of the comparison module;

The output end of the comparison module is connected to the input end of the adjustable resistor, the input end of the adjustable resistor is also connected to the adjustment end of the adjustable resistor, and the output end of the adjustable resistor is connected to ground.

In some embodiments, the first transistor, the second transistor and the third transistor are all diodes, and the third transistor is a Zener diode.

In some embodiments, the support base is further provided with a third metal probe and a fourth metal probe; wherein:

In the layer to be tested, the third metal probe is connected to the first test point of the layer to be tested, and the fourth metal probe is connected to the second test point of the layer to be tested for measurement. Whether there is a failure point between the first test point and the second test point.

In a second aspect, embodiments of the present disclosure provide a failure analysis method, which is applied to the test equipment according to any one of the first aspects, and the method includes:

Provide the chip under test;

Place the chip under test on the upper surface of the chip carrier;

Provide driving current to the layer to be tested in the chip under test;

Obtain an analysis image of the layer to be tested under the driving current;

According to the analyzed image, it is determined whether there is a failure point in the layer to be tested.

In some embodiments, before providing a driving current to the layer to be tested in the chip under test, the method further includes:

Obtain the ground voltage of the layer to be tested through a first metal probe, and obtain the ground voltage of the chip carrier through a second metal probe;

Determine the ground resistance value according to the ground voltage of the layer to be tested and the ground voltage of the chip carrier;

Adjust the resistance value of the adjustable resistance module so that the adjusted resistance value is equal to the ground resistance value;

Wherein, one end of the first metal probe is connected to the first input end of the comparison module, and the other end of the first metal probe is connected to the ground point on the layer to be tested; the second metal probe One end of the probe is connected to the second input end of the comparison module, and the other end of the second metal probe is connected to the ground point on the chip carrier.

In some embodiments, obtaining the ground voltage of the layer to be tested through a first metal probe includes:

When one end of the first metal probe is connected to the ground point on the layer to be tested, and the other end of the first metal probe is connected to the first signal test unit, the first signal test The unit measures the ground voltage of the layer to be tested and provides the measured ground voltage of the layer to be tested to the first input terminal of the comparison module;

Obtaining the ground voltage of the chip carrier through the second metal probe includes:

When one end of the second metal probe is connected to the ground point on the chip carrier and the other end of the second metal probe is connected to the second signal test unit, the second signal test The unit measures the ground voltage of the chip carrier and provides the measured ground voltage of the chip carrier to the second input terminal of the comparison module.

In some embodiments, determining the ground resistance value based on the ground voltage of the layer to be tested and the ground voltage of the chip carrier includes:

Perform a differential operation on the ground voltage of the layer to be tested and the ground voltage of the chip carrier to determine the voltage difference;

Based on the preset corresponding relationship between the voltage difference and the ground resistance, the ground resistance corresponding to the voltage difference is determined.

In some embodiments, based on the corresponding relationship between the preset voltage difference and the ground resistance, the method further includes:

If the voltage difference increases, it is determined that the ground resistance decreases;

If the voltage difference decreases, it is determined that the ground resistance increases.

In some embodiments, providing a driving current to the layer under test of the chip under test includes:

Provide the driving current to the layer to be tested through a third metal probe and a fourth metal probe;

Wherein, one end of the third metal probe is connected to the first test point of the layer to be tested, the other end of the third metal probe is connected to a current source; one end of the fourth metal probe is connected to the first test point of the layer to be tested. The second test point of the layer to be tested is connected, and the other end of the fourth metal probe is connected to ground.

In some embodiments, providing a chip under test includes:

Obtain the chip under test;

The chip under test is preprocessed to expose the layer to be tested of the chip under test.

In some embodiments, the failure point includes a high resistance failure point and/or a micro-leakage failure point.

In a third aspect, embodiments of the present disclosure provide a testing system, including a chip under test and a testing device as described in any one of the first aspects; wherein the testing device is used to perform failure analysis on the chip under test. .

Embodiments of the present disclosure provide a test equipment, a failure analysis method and a test system. The test equipment includes a chip carrier and a support base for supporting the chip carrier, and a comparison module and an adjustable resistance module are provided in the support base; wherein : The chip carrier is used to carry the chip under test; the comparison module is connected to the adjustable resistance module and is used to compare the ground voltage of the layer to be tested in the chip under test with the ground voltage of the chip carrier. According to the comparison result and the available The resistance adjustment module adjusts the ground resistance of the layer to be tested to reduce the surface charging effect of the layer to be tested. In this way, by setting the comparison module and the adjustable resistance module inside the test equipment, it can not only reduce the signal interference between the layer to be tested and the chip carrier, but also dynamically adjust the grounding resistance of the layer to be tested through the adjustable resistance module. Reduce the surface charge effect of the layer to be tested, effectively avoiding the risk of damaging the probe or the chip under test due to discharge at the tip of the probe. It can also improve the imaging effect of EBAC, which is conducive to quickly and accurately locating the failure point in the layer to be tested. , improve the efficiency of failure analysis.

Description of the drawings

Figure 1A is a schematic diagram of a failure phenomenon;

Figure 1B is a schematic diagram 2 of a failure phenomenon;

Figure 2A is a schematic structural diagram of a testing machine;

Figure 2B is a schematic structural diagram of a chip under test;

Figure 3 is a schematic diagram of an EBAC image;

Figure 4 is a schematic structural diagram of a test device provided by an embodiment of the present disclosure;

Figure 5 is a schematic diagram 1 of the specific structure of a test device provided by an embodiment of the present disclosure;

Figure 6 is a detailed structural diagram of a layer to be tested provided by an embodiment of the present disclosure;

Figure 7 is a schematic second structural diagram of a test device provided by an embodiment of the present disclosure;

Figure 8 is a schematic flow chart of a failure analysis method provided by an embodiment of the present disclosure;

Figure 9 is a schematic structural diagram of a test system provided by an embodiment of the present disclosure.

Detailed ways

The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure. It can be understood that the specific embodiments described here are only used to explain the relevant disclosure, but not to limit the disclosure. It should also be noted that, for convenience of description, only parts relevant to the relevant disclosure are shown in the drawings.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of the disclosure only and is not intended to limit the disclosure.

In the following description, reference is made to "some embodiments" which describe a subset of all possible embodiments, but it is understood that "some embodiments" may be the same subset or a different subset of all possible embodiments, and Can be combined with each other without conflict.

It should be noted that the terms "first\second\third" involved in the embodiments of this disclosure are only used to distinguish similar objects and do not represent a specific ordering of objects. It is understandable that "first\second\third" Where permitted, the specific order or sequence may be interchanged so that the disclosed embodiments described herein can be practiced in other sequences than illustrated or described herein.

Chip failure is inevitable during the development, production and use process. Failure analysis is a necessary means to determine the chip failure mechanism. It provides necessary information for effective fault diagnosis. It also provides design engineers with the ability to continuously improve or repair the chip design. direction. For example, through failure analysis, we can identify potential failures in the product production process, analyze their causes and mechanisms, and find design defects, mismatches in process parameters, or improper design and operation for designers of integrated circuits, etc. It is of great significance to seek improvement measures, avoid failures, improve product quality and reliability, and reduce cost losses.

As the critical dimensions of chips continue to shrink, the interconnection and integration of metals inside the chip is getting higher and higher. Whether it is between the same layer of metal or between different metal layers, the isolation material is getting thinner and thinner; various types of interconnections usually appear inside the chip. failure phenomenon, such as: short circuit, micro leakage, high resistance or open circuit, etc.

Figure 1A shows a schematic diagram of a failure phenomenon. As shown in Figure 1A, the nth metal layer and the n+1th metal layer are connected through contact plugs. In the contact plugs used to connect the nth metal layer and the n+1th metal layer, as shown in the figure, failure point. Figure 1B is a schematic diagram 2 of a failure phenomenon. As shown in Figure 1B, a high-resistance failure point appears in the chip shown.

When analyzing the failure phenomenon of the metal layer, for short circuit or open circuit, obvious abnormalities can be observed through optical or electron microscopes; for micro leakage or high resistance, this type of failure usually manifests as very small gaps between metal lines. It is difficult to locate the failure location due to broken wire connections; the EBAC function of the nanoprobe is an effective positioning technology.

Figure 2A shows a schematic structural diagram of a testing machine. As shown in Figure 2A, the dotted circle outlines the chip under test placed on the surface of the test machine (Holder, also called the stage). That is, when performing failure analysis on the chip under test, the chip under test is placed on the test bench. On the upper surface of the machine, probe 1 and probe 2 are respectively connected to two detection points of the current test layer of the chip under test, where probe 1 and probe 2 are both nanoprobes. Figure 2B is a schematic structural diagram of the chip under test enclosed by the dotted circle in Figure 2A. As shown in Figure 2B, probe 1 is connected to one detection point, probe 2 is connected to another detection point, and between the two detection points is A section of the circuit under test in the chip under test. The circuit between the two detection points contains the tiny failure point where the failure phenomenon exists. It can be understood that the closer the two detection points are to the failure point, the more beneficial it will be. detection. Among them, probe 1 can be connected to a current source, which can provide a current of 10 nanoamps (nA) (or other current values) to the chip under test. Probe 2 can be grounded. Under DC bias, electrons are generated. Induced changes, due to the existence of tiny failure points, the conductivity of different positions of the circuit under test is different. In the obtained EBAC image, the tiny failure points will show obvious abnormalities, so that the failure point can be located.

By way of example, Figure 3 shows a schematic diagram of an EBAC image. As shown in Figure 3, in the EBAC image, an abnormal point (EBAC hotspot) that is obviously different from other positions in the image can be located, and this abnormal point is the failure point.

It should be noted that EBAC can locate high-resistance problems in the kiloohm (KΩ) to megaohm (MΩ) (ΔI low) level, and can also locate low-resistance leakage problems in the 100Ω to KΩ (ΔI high) level. Among them, ΔI refers to the current change between probe 1 and probe 2 in the EBAC test mode of the test machine. It can be understood as ΔI = current value at probe 1 - current value at probe 2.

When using EBAC to perform failure analysis on the chip under test, micro-leakage or high-resistance phenomena are easily affected by stray signals (noise) and are covered. It takes a lot of time to adjust the machine to minimize the stray signals, and it is successful. Rates are also susceptible to various factors.

Based on this, embodiments of the present disclosure provide a test equipment, including a chip carrier and a support base for supporting the chip carrier, and a comparison module and an adjustable resistance module are provided in the support base; wherein: the chip carrier, It is used to carry the chip under test; the comparison module is connected to the adjustable resistance module and is used to compare the ground voltage of the layer to be tested in the chip under test with the ground voltage of the chip carrier. According to the comparison result and the adjustable resistance module, the layer to be tested is The grounding resistance is adjusted to reduce the surface charging effect of the layer to be tested. In this way, by setting the comparison module and the adjustable resistance module inside the test equipment, it can not only reduce the signal interference between the layer to be tested and the chip carrier, but also dynamically adjust the grounding resistance of the layer to be tested through the adjustable resistance module, which can also reduce the The surface charging effect of the layer to be tested can effectively avoid the risk of damaging the probe or the chip under test due to discharge at the tip of the probe. It can also improve the imaging effect of EBAC, which is conducive to quickly and accurately locating the failure point in the layer to be tested. Improve efficiency during failure analysis.

Each embodiment of the present disclosure will be described in detail below with reference to the accompanying drawings.

In an embodiment of the present disclosure, see FIG. 4 , which shows a schematic structural diagram of a testing device 10 provided by an embodiment of the present disclosure. As shown in Figure 4, the test equipment 10 may include a chip carrier 101 and a support base 102 for supporting the chip carrier 101, and the support base 102 is provided with a comparison module 103 and an adjustable resistance module 104; wherein,

The chip carrier 101 is used to carry the chip under test 20;

The comparison module 103 is connected to the adjustable resistance module 104 and is used to compare the ground voltage of the layer to be tested in the chip under test 20 with the ground voltage of the chip carrier 101. According to the comparison result and the voltage of the layer to be tested in the adjustable resistance module 104 The ground resistance is adjusted to reduce the surface charging effect of the layer under test.

It should be noted that the test equipment 10 provided by the embodiment of the present disclosure can be a test machine, used to perform failure analysis on the chip under test 20 to determine small failure points such as high resistance and micro leakage in the chip under test 20 .

It should also be noted that when performing failure analysis on the chip under test 20 , the chip under test 20 is placed on the upper surface of the chip carrier 20 , and the two input terminals of the comparison module 103 receive the layers to be tested in the chip under test 20 respectively. The ground voltage of the chip carrier 101 and the ground voltage of the chip carrier 101 (specifically, it can be the ground voltage of the upper surface of the chip carrier 101), and then differentially compare the ground voltage of the layer to be tested and the ground voltage of the chip carrier 101, so that the ground voltage to be tested can be The interference signal existing between the ground point of the layer to be tested in the chip under test and the ground point of the chip carrier is effectively shielded to achieve noise reduction on the surface of the chip under test, improve the signal-to-noise ratio of the signal at the failure point, and reduce the impact of interference signals. ; Then, when performing failure analysis on the chip under test, the imaging effect of EBAC can be improved, the failure point can be accurately and quickly located, and efficiency can be improved.

It should also be noted that after comparing the ground voltage of the layer to be tested with the ground voltage of the chip carrier 101, the resistance value of the adjustable resistance module 104 is adjusted according to the comparison result, which can also realize the adjustment of the ground voltage of the chip under test 20. The ground resistance of the test layer.

Here, the resistance of the ground resistor is directly related to the efficiency of the electron guiding ground terminal of the layer to be tested in the chip 20 under test, that is, it directly affects the charging effect (Charging Effect), based on the ground voltage of the layer to be tested and the chip carrier. The comparison result of the ground voltage of 101 is used to adjust the resistance value of the adjustable resistance module 104 to reduce the charging effect on the surface of the layer to be tested. In this way, when using EBAC to perform failure analysis on the chip under test, not only can the ground resistance of the layer under test be dynamically adjusted and the charging effect reduced, thereby obtaining high-quality EBAC images, but also the charge on the surface of the layer under test can be reduced. The effect can also reduce the risk of trial and error when the probe reaches the surface of the layer to be tested, and effectively avoid tip discharge of the probe, which may cause damage to the probe or the chip under test.

Further, refer to FIG. 5 , which shows a specific structural schematic diagram 1 of a testing device 10 provided by an embodiment of the present disclosure. In some embodiments, as shown in Figure 5, the support base 102 is also provided with a first metal probe 105 and a second metal probe 106; wherein:

One end of the first metal probe 105 is connected to the first input end of the comparison module 103, and the other end of the first metal probe 105 is connected to the ground point GND1 on the layer to be tested, for obtaining the ground voltage of the layer to be tested;

One end of the second metal probe 106 is connected to the second input end of the comparison module 103 , and the other end of the second metal probe 106 is connected to the ground point GND2 on the chip carrier 101 for obtaining the ground voltage of the chip carrier 101 .

It should be noted that the comparison module 103 may include two input terminals: a first input terminal and a second input terminal. Among them, the first metal probe 105 connects the first input terminal to the ground point GND1 of the layer to be tested of the chip 20 under test, so that the ground voltage U _RH on the surface of the layer to be tested can be obtained through the first metal probe 105; The two-metal probe 106 connects the second input terminal to the ground point GND2 on the upper surface of the chip carrier 101, so that the ground voltage _URL on the surface of the chip carrier 101 can be obtained.

It should also be noted that, as shown in FIG. 5 , in the support base 102 , two interfaces are provided on the left side of the comparison module 103 . Among them, the interface marked U _RH is the interface that connects the first input end of the comparison module 103 and the first metal probe 105. That is to say, the first metal probe 105 can be set on a connection line, and the first metal probe 105 can be connected to the first input end of the comparison module 103. The connecting wire is inserted into the interface to connect the first metal probe to the first input end of the comparison module 103; the interface marked with _URL is used to connect the second input end of the comparison module 103 to the second metal probe 106. The interface, that is to say, the second metal probe 106 can be provided on a connection line, and the connection line is inserted into the interface, so that the second metal probe can be connected to the second input end of the comparison module 103 .

Further, as shown in Figure 5, in some embodiments, the support base 102 is also provided with a third metal probe 107 and a fourth metal probe 108; wherein:

On the layer to be tested, the third metal probe 107 is connected to the first test point of the layer to be tested, and the fourth metal probe 108 is connected to the second test point of the layer to be tested, for measuring the first test point and the second test point. Are there any failure points between the points?

It should be noted that the aforementioned first metal probe 105 and the second metal probe 106 are respectively connected to the ground point GND1 of the layer to be tested and the ground point GND2 of the chip carrier 101 for measuring the ground voltage at the corresponding position. In the testing equipment 10, a third metal probe 107 and a fourth metal probe 108 are also provided. The third metal probe 107 and the fourth metal probe 108 are respectively connected to the first test point and the second test point of the layer to be tested. Point connection, between the first test point and the second test point is the circuit under test in the layer to be tested. The third metal probe 107 and the fourth metal probe 108 provide driving current to the circuit under test through the third metal probe 107 and the fourth metal probe 108, and use An imaging device such as a microscope acquires an EBAC image of the layer to be tested under the driving current, so that it can be determined in the acquired EBAC image whether there is a failure point in the layer to be tested of the chip under test.

Normally, if there is no failure point, then the overall EBAC image is uniform, and if there is a failure point, then there will be obvious abnormal points in the EBAC image that are different from other locations; among them, the abnormal points in the EBAC image correspond to The location is the failure point in the chip under test.

In the embodiment of the present disclosure, the first metal probe and the second metal probe each independently include a nanoprobe; for example, they may both be nanoprobes, and the third metal probe and the fourth metal probe may both be nanoprobes. probe. In this way, nanoprobes can be used to conduct nanoscale failure analysis on the chip under test, such as measuring electrical characteristic parameters (such as ground voltage measurement) and locating nanoscale failure points (such as high resistance or micro-leakage).

For example, see FIG. 6 , which shows a detailed structural diagram of a layer to be tested provided by an embodiment of the present disclosure. As shown in Figure 6, the first test point and the second test point are the two end points of the metal line, and the metal line between the first test point and the second test point is the circuit under test. Figure 6 also shows The ground point GND1 of the chip under test is determined.

Figure 6 shows two failure points: high resistance and micro-leakage. These failure points may be caused by circuit design or process defects. Among them, at the high-resistance failure point, the resistance of the metal wire increases significantly, and the resistance is higher than at other locations; at the micro-leakage failure point, two metal wires that should be insulated from each other are in contact, causing leakage. High resistance and micro leakage are very small defects in the circuit. Unlike larger defects such as short circuit or open circuit, the positioning of high resistance and micro leakage is more difficult and complicated.

It should also be noted that one end of the third metal probe 107 is connected to the first test point of the layer to be tested, the other end can be connected to a current source, and one end of the fourth metal probe 108 is connected to the second test point of the layer to be tested. connection, the other end can be connected to ground, thereby providing drive current to the chip under test through a current source. In this way, EBAC can be used to locate tiny defects such as high resistance/micro leakage.

That is to say, in the embodiment of the present disclosure, there are at least two pairs of metal probes in the testing equipment, wherein one pair is a first metal probe and a second metal probe, and the first metal probe is used to connect the chip under test The ground point of the layer to be tested is connected to the first input terminal of the comparison module, the second metal probe is used to connect the ground point of the chip carrier to the second input terminal of the comparison module, and the ground voltages of the two ground points are Provided to the comparison module, the comparison module compares the two ground voltages, and adjusts the resistance of the adjustable resistance module according to the comparison results to reduce the charging effect on the surface of the chip under test, so that when locating the failure point through EBAC , can obtain high-quality EBAC pictures and achieve rapid and accurate location of failure points; the other pair is the third metal probe 107 and the fourth metal probe 108, which are used to introduce driving current and realize the use of EBAC to detect the chip under test. Failure points in the layer.

It should also be noted that the first metal probe 105 , the second metal probe 106 , the third metal probe 107 and the fourth metal probe 108 may all be nanoprobes. In FIG. 5 , for distinction, Different padding representations.

It should also be noted that, as shown in FIG. 5 , the chip under test 20 may include multiple metal layers (a first metal layer 203 and a second metal layer 205 are shown in FIG. 5 ), and the failure point may exist at a certain point. In one or several metal layers, when performing failure analysis on the chip under test 20, it is necessary to preprocess the chip under test 20 first to remove the layer to be tested (in Figure 5, the layer to be tested is the second metal layer). Layer 205) is exposed to facilitate analysis and detection.

Further, in some embodiments, the support base is also provided with a first signal test unit and a second signal test unit; wherein:

The first signal testing unit is used to measure the ground voltage of the layer to be tested through the first metal probe, and provide the measured ground voltage of the layer to be tested to the first input end of the comparison module;

a second signal testing unit, configured to measure the ground voltage of the chip carrier through a second metal probe, and provide the measured ground voltage of the chip carrier to the second input end of the comparison module;

Wherein, the first signal testing unit is connected between one end of the first metal probe and the first input terminal of the comparison module, and the second signal testing unit is connected between one end of the second metal probe and the second input terminal of the comparison module. between.

It should be noted that the ground voltage can be tested through the Signal Measurement Unit (SMU). In the embodiment of the present disclosure, two signal test units (a first signal test unit and a second signal test unit) are provided in the support base, respectively used to measure the ground voltage of the layer to be tested and the ground voltage of the chip carrier, and connect the two The test voltages are respectively provided to the first input terminal and the second input terminal of the comparison module. In addition, the test equipment can also be configured with a display screen or be connected to the display screen. After the first signal test unit and the second signal test unit measure the two ground voltages, the specific voltage value can be displayed on the display screen.

As mentioned above, micro-leakage or high-resistance phenomena are easily affected by stray signals and are covered. After analysis, this is related to the grounding resistance of the test machine on the one hand, and on the other hand, it is affected by the layer to be tested and the underlying metal layer, The influence of stray signals (also called interference signals) from dielectric layers (insulating layers) etc.

Theoretically, the potential of the ground point of the layer to be tested and the ground point on the upper surface of the chip carrier are the same at all times. However, due to the interference of the metal layer, dielectric layer, etc., interference signals exist. The comparison module 103 is used to perform differential reduction. It can effectively shield interference signals and achieve surface noise reduction of the chip under test. Therefore, in some embodiments, as shown in FIG. 5 , the chip under test 20 includes at least one metal layer and at least one dielectric layer, and the at least one metal layer includes the layer to be tested; wherein:

The comparison module 103 is also used to perform a differential comparison based on the ground voltage of the layer to be tested and the ground voltage of the chip carrier 101 to reduce the metal layer and dielectric contained between the layer to be tested and the chip carrier 101 in the chip under test 20 Interference signals generated by the layer.

It should be noted that in FIG. 5 , the chip under test 20 may include a silicon substrate 201 , a first dielectric layer 202 , a first metal layer 203 , a second dielectric layer 204 and a second metal layer 205 . Among them, the second metal layer 205 is the layer to be tested.

In the embodiment of the present disclosure, the comparison module 103 performs a differential comparison between the ground voltage of the layer to be tested and the ground voltage of the chip carrier 101, and compares several metal layers and dielectric layers existing between the layer to be tested and the upper surface of the chip carrier 101. Effectively shielding the interference signal generated by the layer, etc., when performing failure analysis on the chip under test 20, can effectively reduce the interference signal and improve the signal-to-noise ratio of the failure point signal, so as to obtain better EBAC imaging effect and quickly find the failure point. .

Further, in the embodiment of the present disclosure, the comparison module can be implemented by a differential comparator (such as a window comparator), and the adjustable resistance module can be implemented by an adjustable resistor (such as a rheostat). See Figure 7, which shows Schematic diagram 2 of the specific structure of a testing device 10 provided by an embodiment of the present disclosure. In some embodiments, as shown in FIG. 7 , the comparison module 103 includes a first operational amplifier A1, a second operational amplifier A2, a first transistor D1, a second transistor D2, a first resistor R1, a second resistor R2 and a third resistor. Transistor D3, the adjustable resistance module 104 includes an adjustable resistor R; where:

The negative input terminal of the first operational amplifier A1 is connected to the ground point GND1 on the layer to be tested. The positive input terminal of the second operational amplifier A2 is connected to the ground point GND2 on the chip carrier 101. The positive terminal of the first operational amplifier A1 The phase input terminal is connected to the negative phase input terminal of the second operational amplifier A2;

The output terminal of the first operational amplifier A1 is connected to the input terminal of the first transistor D1, and the output terminal of the second operational amplifier A2 is connected to the input terminal of the second transistor D2;

The output terminal of the first transistor D1 is connected to the output terminal of the second transistor D2 and connected to the first terminal of the first resistor R1;

The first terminal of the second resistor R2 is connected to the input terminal of the third transistor D3. The second terminal of the first resistor R1, the second terminal of the second resistor R2 and the output terminal of the third transistor D3 are all connected to the comparison module 103. output terminal;

The output end of the comparison module 103 is connected to the input end of the adjustable resistor R, the input end of the adjustable resistor R is also connected to the adjustment end of the adjustable resistor R, and the output end of the adjustable resistor R is connected to ground.

It should be noted that, as shown in Figure 7, in order to conveniently illustrate the circuit composition and connection relationship between the comparison module 103 and the adjustable resistance module 104, the specific structure of the comparison module 103 is shown in the dotted line box in the upper right corner. The specific structure of the resistance adjustment module 104 is shown in the dotted box in the lower right corner. The ground point GND1 of the layer to be tested of the chip under test 20 is connected to the negative input terminal of the first operational amplifier A1 (i.e., the first input terminal of the comparison module 103). The first operational amplifier A1 conducts the ground voltage U _RH of the layer to be tested. amplification process to obtain the first voltage U _o1 ; the ground point GND2 on the surface of the chip carrier 101 is connected to the forward input terminal of the second operational amplifier A2 (ie, the second input terminal of the comparison module 103 ), and the second operational amplifier A2 is connected to the chip The ground voltage U _RL of the carrier 101 is amplified to obtain the second voltage U _o2 ; and then passes through the first transistor D1, the second transistor D2, the first resistor R1, the second resistor R2 and the third transistor D3, and finally in the comparison module The output voltage U _o of the comparison module is obtained at the output end of 103, and the input voltage U _o is used as the input voltage of the adjustable resistance module 104.

It should also be noted that, as shown in FIG. 7 , the adjustable resistance module 104 can be implemented by an adjustable resistor R. The adjustable resistor R can specifically be a rheostat, the resistance of which can be adjusted. The input voltage U _in of the input terminal of the adjustable resistor R is the output voltage U _o of the comparison module 103 . By sliding the adjustment terminal of the adjustable resistor R, the resistance value of the adjustable resistor R can be changed. In Figure 7, when the adjusting end slides up, the resistance of the adjustable resistor R increases, and when the adjusting end slides down, the resistance of the adjustable resistor R decreases. The voltage at the output end of the adjustable resistor R is U _out , adjustable The output terminal of resistor R is connected to ground.

It should also be noted that, as shown in Figure 7 (or Figure 6), in the support base 102, the right side of the comparison module is provided with an interface marked U _o , and the left and right sides of the adjustable resistance module 104 are respectively provided with There are interfaces identified as U _in and U _out . Among them, the interface on the right side of the comparison module 103 and the interface on the left side of the adjustable resistance module 104 can be connected through a connection line, so that the voltage U _o output by the output end of the comparison module 103 can be provided to the adjustable resistance module 104 The input end serves as the input voltage U _in of the adjustable resistance module 104; the interface at the right end of the adjustable resistance module 104 can be grounded through a connecting wire, thereby grounding the output end of the adjustable resistance module 104. It should also be noted that the first transistor D1, the second transistor D2 and the third transistor D3 are all diodes, and the third transistor D3 is a voltage stabilizing diode. In this way, the third transistor D3 can also have a voltage stabilizing effect, so that the output voltage of the comparison module 103 is stable.

Further, for the adjustable resistance module, in some embodiments, the adjustable resistance module is used to control the adjustable resistance module after determining the voltage difference between the ground voltage of the layer to be tested and the ground voltage of the chip carrier. The corresponding resistance value is adjusted to the ground resistance value corresponding to the voltage difference.

It should be noted that, as shown in Figure 7, a resistance adjustment knob 109 can also be provided in the support base. The resistance of the adjustable resistance module 104 can be adjusted by rotating the resistance adjustment knob 109 to achieve the ground resistance of the layer to be tested. value adjustment. In this way, by dynamically changing the ground resistance of the layer to be tested, the charging effect on the surface of the layer to be tested is reduced.

In the embodiment of the present disclosure, the resistance adjustment of the adjustable resistance module is based on the ground voltage of the layer to be tested and the ground voltage of the chip carrier. The difference between the ground voltage of the layer to be tested and the ground voltage of the chip carrier is determined as the voltage difference. There is a corresponding relationship between the voltage difference and the ground resistance. After analysis, if the voltage difference increases, the ground resistance decreases; if the voltage difference decreases, the grounding resistance increases.

It should also be noted that for the specific corresponding relationship between the voltage difference and the ground resistance, failure analysis can be performed on several sample chips, and during the analysis process, the resistance value of the adjustable resistance module 104 is adjusted to maximize the imaging effect. The corresponding resistance value is determined as the ground resistance corresponding to the current voltage difference.

Exemplarily, Table 1 is an exemplary correspondence table between voltage differences and ground resistance.

Table 1

Voltage difference (V)=U RH -U RL	R W (Ω)
-5	150
-4	120
-3	100
-2	80
0	60
+2	50
+3	40
+4	25
+5	10

It should be noted that Table 1 is an example of the corresponding relationship between the voltage difference (UR _RH -UR _RL ) (unit: volt/V) and the ground resistance (R _W ) (unit: ohm/Ω), where, The voltage difference is the difference between the ground voltage of the layer to be tested and the ground voltage of the chip carrier. The ground resistance is the resistance value of the adjustable resistance module corresponding to the voltage difference when the imaging effect is best. It can also be understood as The resistance value of the ground resistance of the layer under test of the chip under test.

In this way, based on the corresponding relationship shown in Table 1, when performing failure analysis on the chip under test, the resistance value of the adjustable resistance module can be adjusted to the corresponding ground resistance value according to the voltage difference, thereby achieving dynamic adjustment of the ground resistance value. Improve the charging effect on the surface of the chip under test and obtain the optimal EBAC imaging effect.

In short, the embodiment of the present disclosure designs a new type of test machine (ie, test equipment 10) to solve the problem of difficulty in locating micro-leakage or high-resistance defects, which can reduce the impact of stray signals and improve the efficiency of locating failure points. and success rate. The overall idea of the disclosed embodiment is to integrate a window comparator and a rheostat on the basis of an existing test machine to achieve the functions of reducing noise on the surface of the sample (i.e., the chip under test) and dynamically adjusting the ground resistance. in:

For the window comparator, the differential comparison method is used to effectively shield the interference signals generated by several metal layers and dielectric layers existing between the ground point of the layer to be tested and the upper surface of the chip carrier.

For varistor, dynamically adjusting the grounding resistance of the grounding point of the layer to be tested can improve the charging effect on the sample surface and obtain the optimal imaging effect; at the same time, since the grounding resistance can be adjusted according to the voltage difference, there is no need to adjust it multiple times. The probe can also reduce the risk of trial and error when the probe is lowered (tip discharge).

The embodiment of the present disclosure provides a test equipment, including a chip carrier and a support base for supporting the chip carrier, and a comparison module and an adjustable resistance module are provided in the support base; wherein: the chip carrier is used to carry the Test chip; comparison module, connected to the adjustable resistance module, used to compare the ground voltage of the layer to be tested in the chip under test with the ground voltage of the chip carrier, and calculate the ground resistance of the layer to be tested based on the comparison result and the adjustable resistance module Adjustments are made to reduce surface charging effects on the layer under test. In this way, by setting the comparison module and the adjustable resistance module inside the test equipment, it can not only reduce the signal interference between the layer to be tested and the chip carrier, but also dynamically adjust the grounding resistance of the layer to be tested through the adjustable resistance module, which can also reduce the The surface charging effect of the layer to be tested can effectively avoid the risk of damaging the probe or the chip under test due to discharge at the tip of the probe. It can also shorten the time required to debug the test equipment, improve the imaging effect of EBAC, and facilitate rapid and accurate positioning. Failure points in the layer to be tested improve the efficiency of failure analysis.

In another embodiment of the present disclosure, see FIG. 8 , which shows a schematic flow chart of a failure analysis method provided by an embodiment of the present disclosure. As shown in Figure 8, the method may include:

S301. Provide the chip under test.

S302. Place the chip under test on the upper surface of the chip carrier.

It should be noted that the testing method provided by the embodiment of the present disclosure is applied to the testing equipment 10 in the aforementioned embodiment, and failure analysis of the chip under test is implemented based on the testing equipment.

It should also be noted that when performing failure analysis on the chip under test, the layer to be tested of the chip under test needs to be exposed first. Therefore, in some embodiments, providing the chip under test may include:

Get the chip under test;

Preprocess the chip under test to expose the layer to be tested of the chip under test.

It should be noted that the chip under test that requires failure analysis is first obtained, and then the chip under test is preprocessed to expose the layer to be tested for analysis of the layer to be tested. Among them, the pretreatment method can be: grinding or etching, etc., to remove the upper packaging structure or all packaging structures of the chip under test, and then use devices such as photoelectron detectors to initially locate the defect, and then locate the approximate location of the defect. After that, the metal layer, dielectric layer, etc. in the chip under test are further removed to expose the layer to be tested. The pre-processed chip under test is then placed on the upper surface of the chip carrier to perform failure analysis on it.

S303. Provide driving current to the layer to be tested in the chip under test.

S304. Obtain the analysis image of the layer to be tested under the driving current.

It should be noted that the embodiment of the present disclosure uses EBAC to locate the failure point of the chip under test. In order to eliminate the interference of interference signals on the EBAC imaging effect and the impact of ground resistance on the EBAC imaging effect, a comparison module is integrated in the test equipment. and an adjustable resistance module to achieve differential noise reduction and dynamic adjustment of the ground resistance of the layer to be tested, thereby obtaining an EBAC image with good imaging effect for analysis.

Therefore, in some embodiments, before providing the driving current to the layer to be tested in the chip under test, the method may further include:

Obtain the ground voltage of the layer to be tested through the first metal probe, and obtain the ground voltage of the chip carrier through the second metal probe;

Determine the ground resistance value based on the ground voltage of the layer to be tested and the ground voltage of the chip carrier;

Adjust the resistance value of the adjustable resistance module so that the adjusted resistance value is equal to the ground resistance value;

One end of the first metal probe is connected to the first input end of the comparison module, the other end of the first metal probe is connected to the ground point on the layer to be tested; one end of the second metal probe is connected to the second input end of the comparison module. The input end is connected, and the other end of the second metal probe is connected to the ground point on the chip carrier.

It should be noted that the first metal probe is connected between the first input terminal of the comparison module and the ground point on the layer to be tested, so as to obtain the ground voltage of the layer to be tested through the first metal probe; the second metal probe It is connected between the second input terminal of the comparison module and the ground point on the chip carrier, so as to obtain the ground voltage of the chip carrier through the second metal probe.

More specifically, embodiments of the present disclosure can determine specific values of the ground voltage of the layer to be tested and the ground voltage of the chip carrier through the signal test unit. Therefore, in some embodiments, obtaining the ground voltage of the layer to be tested through the first metal probe may include:

When one end of the first metal probe is connected to the ground point on the layer to be tested, and the other end of the first metal probe is connected to the first signal test unit, the ground voltage of the layer to be tested is measured through the first signal test unit. , and provide the measured ground voltage of the layer under test to the first input terminal of the comparison module;

Obtaining the ground voltage of the chip carrier through the second metal probe may include:

When one end of the second metal probe is connected to the ground point on the chip carrier and the other end of the second metal probe is connected to the second signal test unit, the ground voltage of the chip carrier is measured through the second signal test unit. , and provide the measured ground voltage of the chip carrier to the second input terminal of the comparison module.

It should be noted that the first signal test unit can be connected between the first metal probe and the first input end of the comparison module, and is used to measure the ground voltage of the layer to be tested of the chip under test through the first metal probe; The two-signal test unit may be connected between the second metal probe and the second input end of the comparison module, and is used to measure the ground voltage of the layer to be tested on the chip carrier through the second metal probe.

After the first signal test unit and the second signal test measure the ground voltage of the test layer of the chip under test and the ground voltage of the test layer of the chip carrier, the specific voltage values can be displayed on a display screen.

According to the measured ground voltage of the layer to be tested and the ground voltage of the chip carrier, the ground resistance value is determined, and the resistance value of the adjustable resistance module is adjusted to the ground resistance value. In this way, by adjusting the resistance value of the adjustable resistance module, the ground resistance of the layer to be tested of the chip under test can be dynamically adjusted, and a better image can be obtained during the EBAC test.

In some embodiments, determining the ground resistance value based on the ground voltage of the layer to be tested and the ground voltage of the chip carrier may include:

Perform a differential operation on the ground voltage of the layer to be tested and the ground voltage of the chip carrier to determine the voltage difference;

Based on the preset corresponding relationship between the voltage difference and the ground resistance, the ground resistance corresponding to the voltage difference is determined.

It should be noted that the ground voltage of the chip carrier is subtracted from the ground voltage of the layer to be tested to obtain the voltage difference. The corresponding voltage difference is determined from the correspondence between the preset voltage difference and the ground resistance. ground resistance.

In some embodiments, based on the preset correspondence between the voltage difference and the ground resistance, the method may further include:

If the voltage difference increases, it is determined that the ground resistance decreases;

If the voltage difference decreases, it is determined that the ground resistance has increased.

It should be noted that there can be a positive correlation between the voltage difference and the grounding resistance. The specific corresponding relationship can be as shown in the aforementioned Table 1. Each voltage difference corresponds to a grounding resistance. Accordingly, the adjustable resistor The module performs resistance adjustment.

Among them, the corresponding relationship can be obtained experimentally, based on the voltage difference and grounding resistance recorded when the imaging effect is optimal. Specifically, when determining the preset relationship, embodiments of the present disclosure can provide multiple sample chips, determine the voltage difference and corresponding ground resistance of each sample chip, and finally determine the preset voltage difference and ground resistance. The corresponding relationship between them is as shown in Table 1.

Taking any sample chip as an example, use the test equipment provided by the embodiment of the present disclosure to perform failure analysis on the sample chip according to the normal failure analysis process. Here, by default, the components of the test equipment have been connected, and the sample chip is placed on the chip carrier. On the stage, connect the grounding point of the layer to be tested of the sample chip to one end of the first metal probe, and the second metal probe has been connected to the grounding point of the chip carrier; connect the first test point in the layer to be tested to the third Three-metal probe connection connects the second test point in the layer to be tested with the fourth metal probe. The driving current is provided to the layer to be tested through the third metal probe and the fourth metal probe, and the resistance value of the adjustable resistance module is changed. The adjustment method can be to adjust the resistance value on the rotating test equipment. At this time, it can be observed that EBAC images under different resistance values. When the imaging effect is the best, that is, when the failure point can be clearly observed from the EBAC image, the corresponding resistance value is determined as the grounding resistance value. The grounding of the layer to be tested of the sample chip The difference between the voltage and the ground voltage of the chip carrier is the voltage difference, and a corresponding set of voltage difference and ground resistance values are obtained.

Each sample chip is tested and analyzed in the same way, and finally multiple sets of corresponding voltage differences and grounding resistances can be obtained. Among them, there may be multiple sample chips that correspond to the same voltage difference, but the corresponding grounding resistance The resistance values differ within the error range, or the voltage difference and ground resistance values both have differences within the error range. In this case, multiple voltage differences and/or multiple ground resistance values can be averaged separately. The resulting average is determined as a pair of voltage differences and ground resistance. In addition, there may be some data that obviously deviates from the error range due to operational errors and other reasons, and these data will be discarded directly. In this way, the corresponding relationship between the preset voltage difference and ground resistance is obtained. Therefore, after measuring the voltage difference, the corresponding ground resistance value can be determined based on the corresponding relationship to adjust the resistance value of the adjustable resistance module, thereby improving the imaging effect.

Furthermore, the comparison module can implement differential noise reduction for the ground voltage of the layer to be tested and the ground voltage of the chip carrier. There are several metal layers, dielectric layers, etc. between the test layer of the chip under test and the upper surface of the chip carrier. These metal layers and dielectric layers will generate interference signals and affect the imaging effect of EBAC. The embodiment of the present disclosure uses a comparison module to perform a differential comparison between the ground voltage of the layer to be tested and the ground voltage of the chip carrier to achieve a noise reduction effect, which can reduce the metal layer and intermediary contained between the layer to be tested and the chip carrier in the chip under test. The interference signal generated by the electrical layer improves the imaging effect of EBAC, which is conducive to failure analysis of the chip under test and quickly locates the failure point.

In some embodiments, providing a driving current to the layer under test of the chip under test may include:

Provide the driving current to the layer to be tested through the third metal probe and the fourth metal probe;

Among them, one end of the third metal probe is connected to the first test point of the layer to be tested, the other end of the third metal probe is connected to the current source; one end of the fourth metal probe is connected to the second test point of the layer to be tested. , the other end of the fourth metal probe is grounded.

It should be noted that the circuit between the first test point and the second test point is the circuit being tested in the test layer of the chip under test. The closer the first test point and the second test point are to the failure point, the more beneficial it is. Locate the failure point. One end of the third metal probe is connected to the first test point, and the other end can be connected to a current source. One end of the fourth metal probe is connected to the second test point, and the other end can be connected to the ground. Therefore, the driving current can be provided through the current source and introduced into the chip under test through the third metal probe and the fourth metal probe.

When the driving current is passed through, an EBAC image (that is, an analysis image) of the layer to be tested is obtained, wherein the method of obtaining the EBAC image of the layer to be tested can be through any suitable microscope.

S305. Determine whether there is a failure point in the layer to be tested based on the analyzed image.

It should be noted that after obtaining the analysis image, it is determined from the analysis image whether there is a failure point in the layer to be tested. Among them, if there is no failure point in the layer to be tested, the overall analysis image will be relatively uniform. If there is a failure point, the imaging of the failure point will be significantly different from other parts of the image, so that the failure point can be located. The analyzed image can be seen in Figure 3. The failure point may include a high-resistance failure point and/or a micro-leakage failure point, so that the method provided based on the embodiments of the present disclosure can achieve rapid and accurate positioning of high-resistance, micro-leakage, and other failure points that are difficult to locate.

It should also be noted that if there is no failure point in the layer to be tested, it means that the failure point may exist in other metal layers. At this time, the tested layer to be tested can be removed and the new metal layer is exposed as the layer to be tested. Continue failure analysis using this method to determine the failure point.

Details not disclosed in the embodiments of the present disclosure can be understood with reference to the description of the foregoing embodiments.

The embodiment of the present disclosure integrates the window comparator and the rheostat into the nanoprobe test machine, which is especially used for precise positioning of high resistance and micro-leakage circuits under the EBAC function. Using the differential noise reduction function of the window comparator, the noise generated by the metal layer and insulation layer between the ground terminal of the layer under test in the chip under test and the surface of the chip carrier can be effectively removed, effectively improving high resistance and micro leakage under EBAC The signal-to-noise ratio of the signal. Use the resistance adjustment function of the variable resistor to dynamically adjust the ground resistance from the layer to be tested to the ground terminal to obtain a better EBAC image. In addition, dynamically adjusting the ground resistance can also reduce the risk of trial and error when the probe reaches the sample surface. , to prevent tip discharge from damaging the probe or sample.

Embodiments of the present disclosure provide a failure analysis method, which is applied to the test equipment described in the previous embodiments. The method includes: providing a chip under test; placing the chip under test on the upper surface of the chip carrier; The layer to be tested of the chip provides a driving current; an analysis image of the layer to be tested is obtained under the driving current; and based on the analysis image, it is determined whether there is a failure point in the layer to be tested. Not only can it reduce the signal interference between the layer to be tested and the chip carrier, but also by dynamically adjusting the ground resistance of the layer to be tested, it can also reduce the surface charging effect of the layer to be tested, effectively preventing the probe tip from being discharged and damaging the probe or It can also improve the imaging effect of EBAC, help to quickly and accurately locate the failure point in the layer to be tested, and improve the efficiency of failure analysis.

In yet another embodiment of the present disclosure, see FIG. 9 , which shows a schematic structural diagram of a test system 40 provided by an embodiment of the present disclosure. As shown in FIG. 9 , the test system 40 includes a chip under test 20 and the test equipment 10 as described in any of the previous embodiments; wherein the test equipment 10 is used to perform failure analysis on the chip under test 20 .

In the embodiment of the present disclosure, since the test system 40 includes the test equipment 10 described in the previous embodiment, when performing failure analysis on the chip under test 20, the debugging time can be shortened and high-resistance and high-resistance faults can be quickly located. Micro-leak defect locations to improve efficiency.

The above descriptions are only preferred embodiments of the present disclosure and are not intended to limit the scope of the present disclosure.

It should be noted that in the present disclosure, the terms "comprising", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article or device that includes a series of elements not only includes those elements , but also includes other elements not expressly listed or inherent in such process, method, article or apparatus. Without further limitation, an element defined by the statement "comprises a..." does not exclude the presence of additional identical elements in a process, method, article or apparatus that includes that element.

The above serial numbers of the embodiments of the present disclosure are only for description and do not represent the advantages and disadvantages of the embodiments.

The methods disclosed in several method embodiments provided in this disclosure can be combined arbitrarily without conflict to obtain new method embodiments.

The features disclosed in several product embodiments provided in this disclosure can be combined arbitrarily without conflict to obtain new product embodiments.

The features disclosed in several method or device embodiments provided in this disclosure can be combined arbitrarily without conflict to obtain new method embodiments or device embodiments.

The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure. should be covered by the protection scope of this disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Industrial applicability

Embodiments of the present disclosure provide a test equipment, a failure analysis method and a test system. The test equipment includes a chip carrier and a support base for supporting the chip carrier, and a comparison module and an adjustable resistance module are provided in the support base; wherein : The chip carrier is used to carry the chip under test; the comparison module is connected to the adjustable resistance module and is used to compare the ground voltage of the layer to be tested in the chip under test with the ground voltage of the chip carrier. According to the comparison result and the available The resistance adjustment module adjusts the ground resistance of the layer to be tested to reduce the surface charging effect of the layer to be tested. In this way, by setting the comparison module and the adjustable resistance module inside the test equipment, it can not only reduce the signal interference between the layer to be tested and the chip carrier, but also dynamically adjust the grounding resistance of the layer to be tested through the adjustable resistance module. Reduce the surface charge effect of the layer to be tested, effectively avoiding the risk of damaging the probe or the chip under test due to discharge at the tip of the probe. It can also improve the imaging effect of EBAC, which is conducive to quickly and accurately locating the failure point in the layer to be tested. , improve the efficiency of failure analysis.

Claims (19)

1. A kind of test equipment, the test equipment includes a chip carrier and a support base for supporting the chip carrier, and a comparison module and an adjustable resistance module are provided in the support base; wherein:

   The chip carrier is used to carry the chip under test;

   The comparison module is connected to the adjustable resistance module and is used to compare the ground voltage of the layer to be tested in the chip under test with the ground voltage of the chip carrier. According to the comparison result and the adjustable resistance The module adjusts the ground resistance of the layer to be tested to reduce the surface charging effect of the layer to be tested.
2. The testing equipment according to claim 1, wherein the support base is further provided with a first metal probe and a second metal probe; wherein:

   One end of the first metal probe is connected to the first input end of the comparison module, and the other end of the first metal probe is connected to the ground point on the layer to be tested for obtaining the The ground voltage of the layer;

   One end of the second metal probe is connected to the second input end of the comparison module, and the other end of the second metal probe is connected to the ground point on the chip carrier for obtaining the information on the chip carrier. The ground voltage of the station.
3. The testing device of claim 2, wherein the first metal probe and the second metal probe each independently comprise a nanoprobe.
4. The test equipment according to claim 2 or 3, wherein the support base is further provided with a first signal test unit and a second signal test unit; wherein:

   The first signal test unit is used to measure the ground voltage of the layer to be tested through the first metal probe, and provide the measured ground voltage of the layer to be tested to the first part of the comparison module. input terminal;

   The second signal test unit is used to measure the ground voltage of the chip carrier through the second metal probe, and provide the measured ground voltage of the chip carrier to the second component of the comparison module. input terminal;

   Wherein, the first signal test unit is connected between one end of the first metal probe and the first input end of the comparison module, and the second signal test unit is connected between one end of the second metal probe and Between one end and the second input end of the comparison module.
5. The test equipment according to any one of claims 1-4, wherein,

   The adjustable resistance module is used to control the corresponding resistance value of the adjustable resistance module to adjust to the desired value after determining the voltage difference between the ground voltage of the layer to be tested and the ground voltage of the chip carrier. The grounding resistance corresponding to the voltage difference mentioned above.
6. The testing equipment according to claim 5, wherein there is a corresponding relationship between the voltage difference and the ground resistance; wherein:

   If the voltage difference increases, the ground resistance decreases;

   If the voltage difference decreases, the ground resistance increases.
7. The testing device according to any one of claims 1 to 6, wherein the chip under test includes at least one metal layer and at least one dielectric layer, the at least one metal layer includes the layer to be tested ;in:

   The comparison module is also configured to perform a differential comparison based on the ground voltage of the layer to be tested and the ground voltage of the chip carrier, so as to reduce the difference between the layer to be tested and the chip carrier in the chip under test. Interference signals generated by the metal layers and dielectric layers contained between them.
8. The test device according to any one of claims 1-7, wherein the comparison module includes a first operational amplifier, a second operational amplifier, a first transistor, a second transistor, a first resistor, a second resistor and a third resistor. Three transistors, the adjustable resistance module includes an adjustable resistance; wherein:

   The negative input terminal of the first operational amplifier is connected to the ground point on the layer to be tested, and the positive input terminal of the second operational amplifier is connected to the ground point on the chip carrier. The positive input terminal of the operational amplifier is connected to the negative input terminal of the second operational amplifier;

   The output terminal of the first operational amplifier is connected to the input terminal of the first transistor, and the output terminal of the second operational amplifier is connected to the input terminal of the second transistor;

   The output terminal of the first transistor is connected to the output terminal of the second transistor and connected to the first terminal of the first resistor;

   The first end of the second resistor is connected to the input end of the third transistor, and the second end of the first resistor, the second end of the second resistor and the output end of the third transistor are all connected. At the output end of the comparison module;

   The output end of the comparison module is connected to the input end of the adjustable resistor, the input end of the adjustable resistor is also connected to the adjustment end of the adjustable resistor, and the output end of the adjustable resistor is connected to ground.
9. The testing device of claim 8, wherein the first transistor, the second transistor and the third transistor are diodes, and the third transistor is a Zener diode.
10. The testing equipment according to any one of claims 1-9, wherein the support base is further provided with a third metal probe and a fourth metal probe; wherein:

    In the layer to be tested, the third metal probe is connected to the first test point of the layer to be tested, and the fourth metal probe is connected to the second test point of the layer to be tested for measurement. Whether there is a failure point between the first test point and the second test point.
11. A failure analysis method, applied to the test equipment according to any one of claims 1-10, the method includes:

    Provide the chip under test;

    Place the chip under test on the upper surface of the chip carrier;

    Provide driving current to the layer to be tested in the chip under test;

    Obtain an analysis image of the layer to be tested under the driving current;

    According to the analyzed image, it is determined whether there is a failure point in the layer to be tested.
12. The method according to claim 11, wherein before providing the driving current to the layer to be tested in the chip under test, the method further includes:

    Obtain the ground voltage of the layer to be tested through a first metal probe, and obtain the ground voltage of the chip carrier through a second metal probe;

    Determine the ground resistance value according to the ground voltage of the layer to be tested and the ground voltage of the chip carrier;

    Adjust the resistance value of the adjustable resistance module so that the adjusted resistance value is equal to the ground resistance value;

    Wherein, one end of the first metal probe is connected to the first input end of the comparison module, and the other end of the first metal probe is connected to the ground point on the layer to be tested; the second metal probe One end of the probe is connected to the second input end of the comparison module, and the other end of the second metal probe is connected to the ground point on the chip carrier.
13. The method of claim 12, wherein obtaining the ground voltage of the layer to be tested through a first metal probe includes:

    When one end of the first metal probe is connected to the ground point on the layer to be tested, and the other end of the first metal probe is connected to the first signal test unit, through the first signal test The unit measures the ground voltage of the layer to be tested and provides the measured ground voltage of the layer to be tested to the first input terminal of the comparison module;

    Obtaining the ground voltage of the chip carrier through the second metal probe includes:

    When one end of the second metal probe is connected to the ground point on the chip carrier and the other end of the second metal probe is connected to the second signal test unit, the second signal test The unit measures the ground voltage of the chip carrier and provides the measured ground voltage of the chip carrier to the second input terminal of the comparison module.
14. The method according to claim 12 or 13, wherein determining the ground resistance value according to the ground voltage of the layer to be tested and the ground voltage of the chip carrier includes:

    Perform a differential operation on the ground voltage of the layer to be tested and the ground voltage of the chip carrier to determine the voltage difference;

    Based on the preset corresponding relationship between the voltage difference and the ground resistance, the ground resistance corresponding to the voltage difference is determined.
15. The method according to claim 14, wherein based on the corresponding relationship between the preset voltage difference value and the ground resistance value, the method further includes:

    If the voltage difference increases, it is determined that the ground resistance decreases;

    If the voltage difference decreases, it is determined that the ground resistance increases.
16. The method according to any one of claims 11-15, wherein said providing a driving current to the layer to be tested of the chip under test includes:

    Provide the driving current to the layer to be tested through a third metal probe and a fourth metal probe;

    Wherein, one end of the third metal probe is connected to the first test point of the layer to be tested, the other end of the third metal probe is connected to a current source; one end of the fourth metal probe is connected to the The second test point of the layer to be tested is connected, and the other end of the fourth metal probe is connected to ground.
17. The method according to any one of claims 11-16, wherein said providing a chip under test includes:

    Obtain the chip under test;

    The chip under test is preprocessed to expose the layer to be tested of the chip under test.
18. The method according to any one of claims 11-17, wherein the failure point includes a high-resistance failure point and/or a micro-leakage failure point.
19. A test system, including a chip under test and the test equipment according to any one of claims 1 to 10; wherein the test equipment is used to perform failure analysis on the chip under test.

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