WO2023236624A1 - 一种并联apf的控制方法及装置 - Google Patents

一种并联apf的控制方法及装置 Download PDF

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Publication number
WO2023236624A1
WO2023236624A1 PCT/CN2023/082793 CN2023082793W WO2023236624A1 WO 2023236624 A1 WO2023236624 A1 WO 2023236624A1 CN 2023082793 W CN2023082793 W CN 2023082793W WO 2023236624 A1 WO2023236624 A1 WO 2023236624A1
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Prior art keywords
voltage
axis component
harmonic
real
apf
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PCT/CN2023/082793
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English (en)
French (fr)
Inventor
李李
范辉
李铁成
梁纪峰
罗蓬
李安燚
陈二松
Original Assignee
国网河北省电力有限公司电力科学研究院
国家电网有限公司
国网河北能源技术服务有限公司
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Publication of WO2023236624A1 publication Critical patent/WO2023236624A1/zh

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Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J3/00—Circuit arrangements for ac mains or ac distribution networks
    • H02J3/12—Circuit arrangements for ac mains or ac distribution networks for adjusting voltage in ac networks by changing a characteristic of the network load
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J3/00—Circuit arrangements for ac mains or ac distribution networks
    • H02J3/01—Arrangements for reducing harmonics or ripples
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J3/00—Circuit arrangements for ac mains or ac distribution networks
    • H02J3/18—Arrangements for adjusting, eliminating or compensating reactive power in networks
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E40/00—Technologies for an efficient electrical power generation, transmission or distribution
    • Y02E40/20—Active power filtering [APF]

Definitions

  • the present invention relates to the technical field of electric power grid, and in particular to a control method and device for parallel APF.
  • APF parallel active power filter
  • proportional integral (PI) control is often used. Since the active power filter needs to compensate for current harmonics of multiple frequencies, the PI controller cannot achieve static error-free tracking of AC signals. In order to achieve high-precision compensation of various current harmonics, multi-pulse rectifier (MPR) control needs to be used in parallel APFs. Since the gain of resonance control is infinite at the resonant frequency, compensation of current harmonics of various frequencies can be achieved.
  • MPR multi-pulse rectifier
  • the invention provides a control method and device for a parallel APF, which can reduce the error when the parallel APF compensates for current harmonics and improve the compensation accuracy of the parallel APF for the current harmonics.
  • the present invention provides a control method for a parallel APF, which includes: obtaining the real-time current of the load side of the power grid and the AC side of the parallel APF, as well as the positive bus voltage and negative bus voltage of the DC side of the parallel APF; based on the positive The bus voltage and negative bus voltage, as well as the real-time current on the AC side of the parallel APF, are calculated by PI to obtain the fundamental voltage, which is in the same phase as the voltage on the power supply side of the power grid; based on the real-time current on the load side and the AC side of the parallel APF Conduct harmonic analysis to obtain the harmonic voltage.
  • the harmonic voltage is used to characterize the harmonic situation on the load side; based on the fundamental voltage and harmonic voltage, determine the target voltage on the AC side of the parallel APF, and determine the parallel APF based on the target voltage.
  • the duty cycle of each switch tube is adjusted to adjust the real-time voltage of the AC side of the parallel APF to the target voltage.
  • the present invention provides a control method for a parallel APF. It performs PI calculation through the positive bus voltage, the negative bus voltage, and the real-time current of the AC side of the parallel APF to obtain the fundamental voltage based on the real-time current of the load side and the AC side of the parallel APF. Conduct harmonic analysis to obtain the harmonic voltage. Based on the fundamental voltage and harmonic voltage, determine the target voltage on the AC side of the parallel APF. Based on the target voltage, determine the duty cycle of each switch tube in the parallel APF to adjust the parallel APF. the real-time voltage of the AC side to the target voltage.
  • the fundamental wave voltage Since the fundamental wave voltage has the same phase as the voltage on the power supply side of the power grid, it can characterize the fundamental wave situation on the power supply side; the harmonic voltage is used to characterize the harmonic situation on the load side, that is, it represents the real-time changes in the parameters of the grid components on the load side.
  • the target voltage of the AC side of the parallel APF determined in this way takes into account not only the fundamental wave situation on the power supply side, but also the real-time changes in the grid component parameters on the load side, so that the final harmonic compensation on the load side is consistent with the grid component parameters. Adapting to the changes reduces the error when the parallel APF compensates for current harmonics and improves the compensation accuracy of the parallel APF for current harmonics.
  • PI calculation is performed based on the positive bus voltage and negative bus voltage, as well as the real-time current on the AC side of the parallel APF, to obtain the fundamental voltage.
  • the previous steps also include: separately calculating the load side of the power grid and the parallel APF. Perform DQ conversion on the real-time current on the AC side to obtain the D-axis component, Q-axis component and zero-axis component of the real-time current on the load side of the power grid, as well as the D-axis component, Q-axis component and zero-axis component of the real-time current on the AC side of the parallel APF.
  • axis component Perform DQ conversion on the real-time current on the AC side to obtain the D-axis component, Q-axis component and zero-axis component of the real-time current on the load side of the power grid, as well as the D-axis component, Q-axis component and zero-axis component of the real-time current on the AC side of the parallel APF.
  • PI calculation is performed based on the positive bus voltage, the negative bus voltage, and the real-time current on the AC side of the parallel APF to obtain the fundamental voltage, including: based on the positive bus voltage and the negative bus voltage, the total voltage is calculated Control and voltage equalization control to obtain the target value of the D-axis component of the fundamental wave voltage and the target value of the zero-axis component; based on the target value of the D-axis component of the fundamental wave voltage and the D-axis component of the real-time current on the AC side of the parallel APF
  • the error between zero and the Q-axis component of the real-time current on the AC side of the parallel APF, as well as the CVPI controller, are used to perform PI calculations to obtain the D-axis component of the fundamental voltage.
  • obtain the Q-axis component of the fundamental voltage based on the error between the target value of the zero-axis component of the fundamental voltage and the zero-axis component of the real-time current on the AC side of the parallel APF, and the CVPI controller, perform PI calculations to obtain the fundamental The zero-axis component of the wave voltage; determine the fundamental wave voltage based on the D-axis component, Q-axis component and zero-axis component of the fundamental wave voltage.
  • total voltage control and voltage equalization control are performed to obtain the target value of the D-axis component and the target value of the zero-axis component of the fundamental voltage, including: calculating the positive The sum of the bus voltage and the negative bus voltage, and use the error between the target value of the sum and the real-time value to perform PI calculation to obtain the target value of the D-axis component of the fundamental voltage; calculate the difference between the positive bus voltage and the negative bus voltage , and use the error between the target value of the difference and the real-time value to perform PI calculation to obtain the target value of the zero-axis component of the fundamental wave voltage.
  • the transfer function of the CVPI controller is:
  • harmonic analysis is performed based on the real-time current on the load side and the AC side of the parallel APF to obtain the harmonic voltage, including: the D-axis component based on the real-time current on the load side, the AC side of the parallel APF
  • the D-axis component of the real-time current, and the multi-harmonic controller determine the D-axis component of the harmonic voltage; the Q-axis component of the real-time current based on the load side, the Q-axis component of the real-time current on the AC side of the parallel APF, and the multi-harmonic
  • the wave controller determines the Q-axis component of the harmonic voltage; based on the zero-axis component of the real-time current on the load side, the zero-axis component of the real-time current on the AC side of the parallel APF, and the multi-harmonic controller, determines the zero-axis component of the harmonic voltage.
  • Axis component determine the harmonic voltage based on the D-axis component, Q-axis component and zero-axis component of
  • the transfer function of the multi-harmonic controller is:
  • embodiments of the present invention provide a control device for a parallel APF, including: a communication module and a processing module.
  • the communication module is used to obtain the real-time current of the load side of the power grid and the AC side of the parallel APF, and the The positive bus voltage and negative bus voltage on the DC side;
  • the processing module is used to perform PI calculation based on the positive bus voltage and negative bus voltage, as well as the real-time current on the AC side of the parallel APF, to obtain the fundamental voltage, the fundamental voltage and the power supply of the grid
  • the voltage phases of both sides are the same;
  • the processing module is also used to conduct harmonic analysis based on the real-time current of the load side and the AC side of the parallel APF to obtain the harmonic voltage, which is used to characterize the harmonic situation on the load side;
  • the processing module It is also used to determine the target voltage of the AC side of the parallel APF based on the fundamental voltage and harmonic voltage, and determine the duty cycle of each switch tube in the parallel APF based on the target voltage to
  • the processing module is also used to perform DQ conversion on the real-time current on the load side of the power grid and the AC side of the parallel APF, respectively, to obtain the D-axis component and Q-axis of the real-time current on the load side of the power grid. component and zero-axis component, as well as the D-axis component, Q-axis component and zero-axis component of the real-time current on the AC side of the parallel APF.
  • the processing module is specifically configured to perform total voltage control and voltage equalization control based on the positive bus voltage and the negative bus voltage, and obtain the target value of the D-axis component of the fundamental voltage and the target value of the zero-axis component. value; based on the error between the target value of the D-axis component of the fundamental voltage and the D-axis component of the real-time current on the AC side of the parallel APF, and the CVPI controller, perform PI calculation to obtain the D-axis component of the fundamental voltage; based on The error between the zero and Q-axis components of the real-time current on the AC side of the parallel APF, and the CVPI controller, perform PI calculations to obtain the Q-axis component of the fundamental voltage; based on the target value of the zero-axis component of the fundamental voltage and the parallel The error between the zero-axis component of the real-time current on the AC side of the APF, and the CVPI controller, perform PI calculations to obtain the zero-axis component of the fundamental voltage; based on the target value of the zero
  • the processing module is specifically used to calculate the sum of the positive bus voltage and the negative bus voltage, and perform PI calculation based on the error between the target value of the sum and the real-time value to obtain the fundamental voltage
  • the target value of the D-axis component calculate the difference between the positive bus voltage and the negative bus voltage, and use the error between the target value of the difference and the real-time value to perform PI calculation to obtain the target value of the zero-axis component of the fundamental voltage.
  • the transfer function of the CVPI controller is:
  • the processing module is specifically configured to determine the harmonic voltage based on the D-axis component of the real-time current on the load side, the D-axis component of the real-time current on the AC side of the parallel APF, and the multi-harmonic controller.
  • the D-axis component based on the Q-axis component of the real-time current on the load side, the Q-axis component of the real-time current on the AC side of the parallel APF, and the multi-harmonic controller, determine the Q-axis component of the harmonic voltage; based on the real-time load side
  • the zero-axis component of the current, the zero-axis component of the real-time current on the AC side of the parallel APF, and the multi-harmonic controller determine the zero-axis component of the harmonic voltage; based on the D-axis component, Q-axis component and zero-axis of the harmonic voltage component to determine the harmonic voltage.
  • the transfer function of the multi-harmonic controller is:
  • embodiments of the present invention provide an electronic device, characterized in that the electronic device includes a memory and a processor.
  • the memory stores a computer program.
  • the processor is configured to call and run the computer program stored in the memory to execute the above-mentioned step.
  • embodiments of the present invention provide a computer-readable storage medium.
  • the computer-readable storage medium stores a computer program. It is characterized in that when the computer program is executed by a processor, the above-mentioned first aspect and the first aspect are implemented. Any possible implementation method.
  • Figure 1 is a schematic diagram of the structure of a three-phase four-wire three-level parallel active power filter provided by an embodiment of the present invention
  • Figure 2 is a control logic diagram of a parallel APF control method provided by an embodiment of the present invention.
  • Figure 3 is a schematic flow chart of a parallel APF control method provided by an embodiment of the present invention.
  • Figure 4 is a complex vector-based fundamental wave current loop control block diagram provided by an embodiment of the present invention.
  • Figure 5 is a Bode diagram corresponding to a current open-loop transfer function provided by an embodiment of the present invention.
  • Figure 6 is a Bode diagram corresponding to a current closed-loop transfer function based on a CVPI controller provided by an embodiment of the present invention
  • Figure 7 is a Bode diagram corresponding to another current closed-loop transfer function based on a CVPI controller provided by an embodiment of the present invention.
  • Figure 8 is a composite current control block diagram based on CVPI and multi-resonance control provided by an embodiment of the present invention.
  • Figure 9 is a Nyquist diagram of the current open-loop transfer function under a resonant controller with CVPI+18th resonant frequency with different gain coefficients provided by an embodiment of the present invention.
  • Figure 10 is a Bode diagram of the current open-loop transfer function of the resonant controller at CVPI+18th resonant frequency before and after adding a phase compensation link to the resonant controller provided by the embodiment of the present invention
  • Figure 11 is a Bode diagram of a resonant control current open-loop system based on CVPI+ multi-harmonic frequencies provided by an embodiment of the present invention
  • Figure 12 is a current waveform and grid current spectrum diagram during CVPI+ multi-resonance control provided by an embodiment of the present invention.
  • Figure 13 is a compensation current waveform diagram of a load and a parallel APF when a load is suddenly added according to an embodiment of the present invention
  • Figure 14 is a schematic structural diagram of a parallel APF control device provided by an embodiment of the present invention.
  • Figure 15 is a schematic structural diagram of an electronic device provided by an embodiment of the present invention.
  • words such as “exemplary” or “for example” are used to represent examples, illustrations or explanations. Any embodiment or design described as “exemplary” or “such as” in the embodiments of the present application is not to be construed as preferred or advantageous over other embodiments or designs. Rather, the use of words such as “exemplary” or “such as” is intended to present related concepts in a concrete manner that is easier to understand.
  • references to the terms “including” and “having” and any variations thereof in the description of this application are intended to cover non-exclusive inclusion.
  • a process, method, system, product or device that includes a series of steps or modules is not limited to the listed steps or modules, but optionally also includes other unlisted steps or modules, or optionally also Includes other steps or modules that are inherent to such processes, methods, products, or devices.
  • FIG. 1 is a schematic diagram of the structure of a three-phase four-wire three-level parallel active power filter provided by an embodiment of the present invention.
  • the nonlinear load of the three-phase power grid is a three-phase four-wire diode rectifier bridge; the three-level voltage source converter is connected to the power grid through the output filter to form a parallel active filter.
  • FIG. 2 is a control logic diagram of a parallel APF control method provided by an embodiment of the present invention.
  • the current control part consists of a fundamental current loop and a harmonic current loop.
  • the instruction of the fundamental d-axis current component control loop is the output of the total voltage loop to achieve stable control of the bus voltage.
  • the q-axis current component control loop The command is 0 to achieve the same phase of the fundamental current and voltage.
  • Both the d and q-axis current loops use CVPI controllers.
  • the zero-sequence current loop command is the output of the voltage equalization control loop. By adjusting the zero-sequence current, the positive and negative values are ensured.
  • the bus voltage is equalized, and the loop uses a PI controller; the harmonic current control loop introduces a multi-resonance controller to achieve high-precision compensation for each harmonic on the load side.
  • the resonance controller can be flexibly designed for any harmonic.
  • Figure 3 is a schematic flow chart of a parallel APF control method provided by an embodiment of the present invention.
  • the execution subject of this method is the control device of the parallel APF.
  • the method includes steps S101-S103.
  • the fundamental wave voltage has the same phase as the voltage on the power supply side of the power grid.
  • control device may determine the fundamental wave voltage based on steps S1021-S1025.
  • control device may determine the target value of the D-axis component and the target value of the zero-axis component of the fundamental wave voltage based on steps A1-A2.
  • A1 Calculate the sum of the positive bus voltage and the negative bus voltage, and use the error between the target value of the sum and the real-time value to perform PI calculation to obtain the target value of the D-axis component of the fundamental voltage.
  • A2 Calculate the difference between the positive bus voltage and the negative bus voltage, and use the error between the target value of the difference and the real-time value to perform PI calculation to obtain the target value of the zero-axis component of the fundamental voltage.
  • the transfer function of the CVPI controller is:
  • control device can perform DQ conversion on the real-time current on the load side of the power grid and the AC side of the parallel APF respectively to obtain the D-axis component, Q-axis component and zero of the real-time current on the load side of the power grid.
  • the PI controller is improved into a CVPI controller to realize current decoupling, and the zero point of the CVPI controller is set as the pole of the complex vector model in the dq0 coordinate system to design the current control loop.
  • the complex vector of the dq complex plane as , from the control logic diagram in Figure 2, the control block diagram of the fundamental current loop based on complex vectors is shown in Figure 4.
  • CVPI Controller Transfer Function for Current Control Loop for:
  • the current control loop bandwidth is much smaller than the switching frequency fs, the influence of SPWM modulation can be ignored, and the corresponding transfer function is approximately 1. Therefore, the current open-loop transfer function of the CVPI controller is introduced It can be expressed as:
  • the Bode plot corresponding to the current open-loop transfer function is shown in Figure 5.
  • the current loop phase margin is 90°, and the control system is stable. Among them, (a) in Figure 5 is the amplitude-frequency characteristic curve, and (b) in Figure 5 is the phase-frequency characteristic curve.
  • the zero-axis current control loop For the zero-axis current control loop, it is independent from the dq current control loop, so it can be designed separately. From the model of the controlled object, it can be seen that the corresponding loop is a first-order link.
  • the harmonic voltage is used to characterize the harmonic situation on the load side.
  • control device may determine the harmonic voltage based on steps S1031-S1034.
  • the transfer function of the multi-harmonic controller is:
  • the load current The harmonic frequencies are mainly negative sequence 5, 11, and 17 times, positive sequence 7, 13, and 19 times, and zero sequence 6 and 9 times.
  • the positive and negative sequence currents become 6. 12 and 18th order (the order of positive sequence harmonics is positive, and the order of negative sequence harmonics is negative). Since the resonant controller is the internal mode of the cosine signal and the cosine function is an even function, the resonant controller can realize open loop at positive and negative angular frequencies. High gain control. Based on the above analysis, resonant controllers for the 6th, 12th and 18th harmonic frequencies are designed to achieve high-precision control of harmonic currents. Let the transfer function GR(s) of the multi-resonance controller be:
  • h is the harmonic order
  • khr is the gain of the resonant controller at the h-th harmonic frequency.
  • the open-loop cutoff frequency ⁇ c of the resonant controller is set, thus forming a quasi-resonant control. device.
  • the resonant controller will cause a 90° phase lag on the right side of the resonant frequency.
  • the phase curve of the current open-loop transfer function based on the CVPI controller in Figure 3 it can be seen that the phase at the compensated harmonic frequency is -90°.
  • the resonance controller will inevitably affect the stability of the control system. Therefore, it is necessary to design a phase compensation link for the resonant controller.
  • the improved resonant controller GR1(s) can be expressed as:
  • Figure 8 is a composite current control block diagram based on CVPI and multi-resonance control. Since each resonant controller and the CVPI controller are connected in parallel, the parameter design method of a certain resonant controller can be analyzed in combination with the current control loop with a CVPI controller, and the parameter design of other resonant controllers can be deduced in the same way.
  • the corresponding delay time is 1.5Ts. Ts is the switching period of the converter.
  • This delay link can be equivalent to a first-order inertial link, corresponding to The transfer function Gd(s) is:
  • ⁇ c is between 3 and 5
  • the phase margin (PM) at the resonant frequency is greater than zero
  • the gain coefficient khr determines the gain coefficient
  • Figure 9 is a Nyquist plot of the current open-loop transfer function under a resonant controller with CVPI+18th resonant frequency with different gain coefficients.
  • Figure 10 shows the Bode diagram of the current open-loop transfer function of the resonant controller at the CVPI+18th resonant frequency before and after adding a phase compensation link to the resonant controller.
  • (a) in Figure 10 is the amplitude-frequency characteristic curve
  • (b) in Figure 10 is the phase-frequency characteristic curve. It can be seen from Figure 10 that after the introduction of phase compensation, the phase margin of the current control loop at the resonant frequency is significantly improved.
  • Figure 11 is the Bode diagram of the resonant control current open-loop system based on CVPI+ multi-harmonic frequency.
  • the bandwidth of the current control loop is not affected, but due to the consideration of the SPWM link and the delay of digital implementation, the current control loop
  • the phase margin is reduced to 45°, but the control system still has a certain stability margin.
  • the zero-axis current is mainly the third harmonic, and a resonant controller with three times the fundamental frequency can be superimposed.
  • the present invention provides a control method for a parallel APF. It performs PI calculation through the positive bus voltage, the negative bus voltage, and the real-time current of the AC side of the parallel APF to obtain the fundamental voltage based on the real-time current of the load side and the AC side of the parallel APF. Conduct harmonic analysis to obtain the harmonic voltage. Based on the fundamental voltage and harmonic voltage, determine the target voltage on the AC side of the parallel APF. Based on the target voltage, determine the duty cycle of each switch tube in the parallel APF to adjust the parallel APF. the real-time voltage of the AC side to the target voltage.
  • the fundamental wave voltage Since the fundamental wave voltage has the same phase as the voltage on the power supply side of the power grid, it can characterize the fundamental wave situation on the power supply side; the harmonic voltage is used to characterize the harmonic situation on the load side, that is, it represents the real-time changes in the parameters of the grid components on the load side.
  • the target voltage of the AC side of the parallel APF determined in this way takes into account not only the fundamental wave situation on the power supply side, but also the real-time changes in the grid component parameters on the load side, so that the final harmonic compensation on the load side is consistent with the grid component parameters. Adapting to the changes reduces the error when the parallel APF compensates for current harmonics and improves the compensation accuracy of the parallel APF for current harmonics.
  • a three-phase, four-wire, three-level parallel APF is used as an example.
  • the hardware circuit and controller parameters of the system are shown in Table 1.
  • the control system is composed of TMS320F2812.
  • Figure 12 is a current waveform and grid current spectrum diagram during CVPI+ multi-resonance control of the parallel APF control method provided by the embodiment of the present invention.
  • (a) in Figure 12 is the current waveform diagram
  • (b) in Figure 12 is the grid current spectrum diagram.
  • phase a related current waveform and grid current harmonic distribution, where , and They are the load current, grid current and compensation current of phase A respectively. From the spectrum distribution of the grid current, it can be seen that the characteristic sub-harmonic current of the load is obviously compensated, the quality of the grid current is good, and the total harmonic distortion THD is 3.5%.
  • Figure 13 shows the compensation current waveform of the load and parallel APF when the load is suddenly added. It can be seen that the dynamic adjustment time of the control system is within one power frequency cycle, and the current control system has fast tracking performance.
  • sequence number of each step in the above embodiment does not mean the order of execution.
  • the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiment of the present invention.
  • FIG 14 shows a schematic structural diagram of a parallel APF control device provided by an embodiment of the present invention.
  • the determination device 200 includes: a communication module 201 and a processing module 202.
  • the communication module 201 is used to obtain the real-time current of the load side of the power grid and the AC side of the parallel APF, as well as the positive bus voltage and negative bus voltage of the DC side of the parallel APF.
  • the processing module 202 is configured to perform PI calculation based on the positive bus voltage, the negative bus voltage, and the real-time current on the AC side of the parallel APF to obtain the fundamental voltage, which has the same phase as the voltage on the power supply side of the power grid.
  • the processing module 202 is also used to perform harmonic analysis based on the real-time current on the load side and the AC side of the parallel APF to obtain the harmonic voltage.
  • the harmonic voltage is used to characterize the harmonic situation on the load side;
  • the processing module 202 is also used to determine the target voltage of the AC side of the parallel APF based on the fundamental voltage and the harmonic voltage, and determine the duty cycle of each switch tube in the parallel APF based on the target voltage to adjust the AC side of the parallel APF. the real-time voltage to the target voltage.
  • the processing module 202 is also used to perform DQ conversion on the real-time current on the load side of the power grid and the AC side of the parallel APF, respectively, to obtain the D-axis component, Q, of the real-time current on the load side of the power grid.
  • the processing module 202 is specifically configured to perform total voltage control and voltage equalization control based on the positive bus voltage and the negative bus voltage to obtain the target value of the D-axis component and the zero-axis component of the fundamental voltage.
  • Target value based on the error between the target value of the D-axis component of the fundamental voltage and the D-axis component of the real-time current on the AC side of the parallel APF, and the CVPI controller, perform PI calculation to obtain the D-axis component of the fundamental voltage;
  • the PI calculation is performed to obtain the Q-axis component of the fundamental voltage; the target value based on the zero-axis component of the fundamental voltage and The error between the zero-axis component of the real-time current on the AC side of the parallel APF, and the CVPI controller, perform PI calculations to obtain the zero-axis component of the fundamental voltage; based on the D-axis
  • the processing module 202 is specifically used to calculate the sum of the positive bus voltage and the negative bus voltage, and perform PI calculation based on the error between the target value of the sum and the real-time value to obtain the fundamental voltage.
  • the target value of the D-axis component calculate the difference between the positive bus voltage and the negative bus voltage, and use the error between the target value of the difference and the real-time value to perform PI calculation to obtain the target value of the zero-axis component of the fundamental voltage.
  • the transfer function of the CVPI controller is:
  • the processing module 202 is specifically configured to determine harmonics based on the D-axis component of the real-time current on the load side, the D-axis component of the real-time current on the AC side of the parallel APF, and the multi-harmonic controller.
  • the D-axis component of the voltage; the Q-axis component of the real-time current on the load side, the Q-axis component of the real-time current on the AC side of the parallel APF, and the multi-harmonic controller determine the Q-axis component of the harmonic voltage; based on the load-side
  • the zero-axis component of the real-time current, the zero-axis component of the real-time current on the AC side of the parallel APF, and the multi-harmonic controller determine the zero-axis component of the harmonic voltage; based on the D-axis component, Q-axis component and zero-axis component of the harmonic voltage axis component to determine the harmonic voltage.
  • the transfer function of the multi-harmonic controller is:
  • FIG. 15 is a schematic structural diagram of an electronic device provided by an embodiment of the present invention.
  • the electronic device 300 of this embodiment includes: a processor 301 , a memory 302 , and a computer program 303 stored in the memory 302 and executable on the processor 301 .
  • the processor 301 executes the computer program 303, it implements the steps in each of the above method embodiments, such as steps 101 to 104 shown in Figure 3.
  • the processor 301 executes the computer program 303, it implements the functions of each module/unit in each of the above device embodiments, for example, the functions of the communication module 201 and the processing module 202 shown in Figure 14.
  • the computer program 303 can be divided into one or more modules/units, the one or more modules/units are stored in the memory 302 and executed by the processor 301 to complete this invention.
  • the one or more modules/units may be a series of computer program instruction segments capable of completing specific functions.
  • the instruction segments are used to describe the execution process of the computer program 303 in the electronic device 300 .
  • the computer program 303 can be divided into the communication module 201 and the processing module 202 shown in FIG. 14 .
  • the so-called processor 301 can be a central processing unit (CPU), or other general-purpose processor, a digital signal processor (Digital Signal Processor, DSP), an application specific integrated circuit (Application Specific Integrated Circuit, ASIC), Field-Programmable Gate Array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc.
  • a general-purpose processor may be a microprocessor or the processor may be any conventional processor, etc.
  • the memory 302 may be an internal storage unit of the electronic device 300 , such as a hard disk or memory of the electronic device 300 .
  • the memory 302 may also be an external storage device of the electronic device 300, such as a plug-in hard disk, a smart memory card (Smart Media Card, SMC), or a secure digital (SD) equipped on the electronic device 300. card, Flash Card, etc.
  • the memory 302 may also include both an internal storage unit of the electronic device 300 and an external storage device.
  • the memory 302 is used to store the computer program and other programs and data required by the terminal.
  • the memory 302 can also be used to temporarily store data that has been output or is to be output.
  • Module completion means dividing the internal structure of the device into different functional units or modules to complete all or part of the functions described above.
  • Each functional unit and module in the embodiment can be integrated into one processing unit, or each unit can exist physically alone, or two or more units can be integrated into one unit.
  • the above-mentioned integrated unit can be hardware-based. It can also be implemented in the form of software functional units.
  • the specific names of each functional unit and module are only for the convenience of distinguishing each other and are not used to limit the scope of protection of the present application.
  • For the specific working processes of the units and modules in the above system please refer to the corresponding processes in the foregoing method embodiments, and will not be described again here.
  • the disclosed device/terminal and method can be implemented in other ways.
  • the device/terminal embodiments described above are only illustrative.
  • the division of modules or units is only a logical function division. In actual implementation, there may be other division methods, such as multiple units or units. Components may be combined or may be integrated into another system, or some features may be ignored, or not implemented.
  • the coupling or direct coupling or communication connection between each other shown or discussed may be through some interfaces, indirect coupling or communication connection of devices or units, which may be in electrical, mechanical or other forms.
  • the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place, or they may be distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.
  • each functional unit in various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically alone, or two or more units can be integrated into one unit.
  • the above integrated units can be implemented in the form of hardware or software functional units.
  • the integrated module/unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium.
  • the present invention can implement all or part of the processes in the methods of the above embodiments, and can also be completed by instructing relevant hardware through a computer program.
  • the computer program can be stored in a computer-readable storage medium, and the computer program can be stored in a computer-readable storage medium.
  • the computer program includes computer program code, which may be in the form of source code, object code, executable file or some intermediate form.
  • the computer-readable medium may include: any entity or device capable of carrying the computer program code, recording media, U disk, mobile hard disk, magnetic disk, optical disk, computer memory, read-only memory (Read-Only Memory, ROM) , random access memory (Random Access Memory, RAM), electrical carrier signals, telecommunications signals, and software distribution media, etc.
  • the content contained in the computer-readable medium can be appropriately added or deleted according to the requirements of legislation and patent practice in the jurisdiction.
  • the computer-readable medium Excluded are electrical carrier signals and telecommunications signals.

Abstract

本发明提供一种并联APF的控制方法及装置。该方法包括：获取电网的负荷侧和并联APF的交流侧的实时电流，以及并联APF的直流侧的正母线电压和负母线电压；基于正母线电压和负母线电压，以及并联APF的交流侧的实时电流进行PI计算，得到基波电压，基波电压与电网的供电侧的电压相位相同；基于负荷侧和并联APF的交流侧的实时电流进行谐波分析，得到谐波电压，谐波电压用于表征负荷侧的谐波情况；基于基波电压和谐波电压，确定并联APF的交流侧的目标电压，并基于目标电压，确定并联APF中各开关管的占空比，以调整并联APF的交流侧的实时电压至目标电压。本发明能够提高并联APF对电流谐波的补偿精度。

Description

一种并联APF的控制方法及装置 技术领域
本发明涉及电力电网技术领域，尤其涉及一种并联APF的控制方法及装置。
 背景技术
随着大数据、云计算、物联网时代的来临，大型服务器等非线性负荷日益增多，逐渐成为配电网谐波污染的重要来源之一。谐波污染导致电能质量的下降，对供、用电设备的安全经济运行造成了重大影响。谐波抑制是现代电力发展亟需解决的重要问题。并联型有源电力滤波器（active power filter，APF）可被控制成电流源，经过适当的控制算法，可用于补偿电力系统中的电流谐波。因此，APF受到广泛关注。
对于传统并联有源电力滤波器，多采用比例积分（proportion integral，PI）控制。由于有源电力滤波器需补偿多种频率的电流谐波，PI控制器无法实现交流信号的无静差跟踪。为了实现多种电流谐波的高精度补偿，需将多比例谐振(multi-pulse rectifier，MPR)控制用于并联APF。由于谐振控制在谐振频率处的增益无穷大，可实现各种频率电流谐波的补偿。
但目前电流控制环路的设计均没有考虑电网元件参数的变化。实际应用中，由于负载经常变化，且随着工作环境温度的不同，变换器和电网的电感元件参数会发生改变，导致并联APF对各种频率电流谐波进行补偿时存在较大误差，补偿精度较低。
 发明内容
本发明提供了一种并联APF的控制方法及装置，能够减小并联APF对电流谐波进行补偿时的误差，提高并联APF对电流谐波的补偿精度。
第一方面，本发明提供了一种并联APF的控制方法，包括：获取电网的负荷侧和并联APF的交流侧的实时电流，以及并联APF的直流侧的正母线电压和负母线电压；基于正母线电压和负母线电压，以及并联APF的交流侧的实时电流进行PI计算，得到基波电压，基波电压与电网的供电侧的电压相位相同；基于负荷侧和并联APF的交流侧的实时电流进行谐波分析，得到谐波电压，谐波电压用于表征负荷侧的谐波情况；基于基波电压和谐波电压，确定并联APF的交流侧的目标电压，并基于目标电压，确定并联APF中各开关管的占空比，以调整并联APF的交流侧的实时电压至目标电压。
本发明提供一种并联APF的控制方法，通过正母线电压和负母线电压，以及并联APF的交流侧的实时电流进行PI计算，得到基波电压，基于负荷侧和并联APF的交流侧的实时电流进行谐波分析，得到谐波电压，基于基波电压和谐波电压，确定并联APF的交流侧的目标电压，并基于目标电压，确定并联APF中各开关管的占空比，以调整并联APF的交流侧的实时电压至目标电压。由于基波电压与电网的供电侧的电压相位相同，可以表征供电侧的基波情况；谐波电压用于表征负荷侧的谐波情况，也即表征了负荷侧的电网元件参数的实时变化情况，如此确定的并联APF的交流侧的目标电压，既考量了供电侧的基波情况，又考量了负荷侧的电网元件参数的实时变化情况，使得最终负荷侧的谐波补偿与电网元件参数的变化相适应，减小了并联APF对电流谐波进行补偿时的误差，提高并联APF对电流谐波的补偿精度。
在一种可能的实现方式中，基于正母线电压和负母线电压，以及并联APF的交流侧的实时电流进行PI计算，得到基波电压，之前还包括：分别对电网的负荷侧和并联APF的交流侧的实时电流，进行DQ转换，得到电网的负荷侧的实时电流的D轴分量、Q轴分量和零轴分量，以及并联APF的交流侧的实时电流的D轴分量、Q轴分量和零轴分量。
在一种可能的实现方式中，基于正母线电压和负母线电压，以及并联APF的交流侧的实时电流进行PI计算，得到基波电压，包括：基于正母线电压和负母线电压，进行总压控制和均压控制，得到基波电压的D轴分量的目标值和零轴分量的目标值；基于基波电压的D轴分量的目标值和并联APF的交流侧的实时电流的D轴分量之间的误差，以及CVPI控制器，进行PI计算，得到基波电压的D轴分量；基于零和并联APF的交流侧的实时电流的Q轴分量之间的误差，以及CVPI控制器，进行PI计算，得到基波电压的Q轴分量；基于基波电压的零轴分量的目标值和并联APF的交流侧的实时电流的零轴分量之间的误差，以及CVPI控制器，进行PI计算，得到基波电压的零轴分量；基于基波电压的D轴分量、Q轴分量和零轴分量，确定基波电压。
在一种可能的实现方式中，基于正母线电压和负母线电压，进行总压控制和均压控制，得到基波电压的D轴分量的目标值和零轴分量的目标值，包括：计算正母线电压和负母线电压之和，并以该和的目标值和实时值之间的误差，进行PI计算，得到基波电压的D轴分量的目标值；计算正母线电压和负母线电压之差，并以该差的目标值和实时值之间的误差，进行PI计算，得到基波电压的零轴分量的目标值。
在一种可能的实现方式中，CVPI控制器的传递函数为：
；
其中， 为CVPI控制器的传递函数的函数值， 为CVPI控制器的比例增益系数， 为CVPI控制器的积分增益系数， 为基波电压的角频率， 为并联APF与电网之间的等效电感， 为电网供电侧的等效电感， 为电网供电侧的等效电感和并联APF与电网之间的等效电感之和， 为并联APF与电网之间的等效电阻， 为CVPI控制器的传递函数的输入量， 为虚数单位。
在一种可能的实现方式中，基于负荷侧和并联APF的交流侧的实时电流进行谐波分析，得到谐波电压，包括：基于负荷侧的实时电流的D轴分量、并联APF的交流侧的实时电流的D轴分量，以及多谐波控制器，确定谐波电压的D轴分量；基于负荷侧的实时电流的Q轴分量、并联APF的交流侧的实时电流的Q轴分量，以及多谐波控制器，确定谐波电压的Q轴分量；基于负荷侧的实时电流的零轴分量、并联APF的交流侧的实时电流的零轴分量，以及多谐波控制器，确定谐波电压的零轴分量；基于谐波电压的D轴分量、Q轴分量和零轴分量，确定谐波电压。
在一种可能的实现方式中，多谐波控制器的传递函数为：
；
其中， 为多谐波控制器的传递函数的函数值， 为谐波次数， 为第h次谐波频率下多谐振控制器的增益， 为谐振控制器的开环截止频率， ， 为基波电压的周期， 为基波电压的角频率， 为多谐波控制器的传递函数的输入量。
第二方面，本发明实施例提供了一种并联APF的控制装置，包括：通信模块和处理模块， 通信模块，用于获取电网的负荷侧和并联APF的交流侧的实时电流，以及并联APF的直流侧的正母线电压和负母线电压；处理模块，用于基于正母线电压和负母线电压，以及并联APF的交流侧的实时电流进行PI计算，得到基波电压，基波电压与电网的供电侧的电压相位相同；处理模块，还用于基于负荷侧和并联APF的交流侧的实时电流进行谐波分析，得到谐波电压，谐波电压用于表征负荷侧的谐波情况；处理模块，还用于基于基波电压和谐波电压，确定并联APF的交流侧的目标电压，并基于目标电压，确定并联APF中各开关管的占空比，以调整并联APF的交流侧的实时电压至目标电压。
在一种可能的实现方式中，处理模块，还用于分别对电网的负荷侧和并联APF的交流侧的实时电流，进行DQ转换，得到电网的负荷侧的实时电流的D轴分量、Q轴分量和零轴分量，以及并联APF的交流侧的实时电流的D轴分量、Q轴分量和零轴分量。
在一种可能的实现方式中，处理模块，具体用于基于正母线电压和负母线电压，进行总压控制和均压控制，得到基波电压的D轴分量的目标值和零轴分量的目标值；基于基波电压的D轴分量的目标值和并联APF的交流侧的实时电流的D轴分量之间的误差，以及CVPI控制器，进行PI计算，得到基波电压的D轴分量；基于零和并联APF的交流侧的实时电流的Q轴分量之间的误差，以及CVPI控制器，进行PI计算，得到基波电压的Q轴分量；基于基波电压的零轴分量的目标值和并联APF的交流侧的实时电流的零轴分量之间的误差，以及CVPI控制器，进行PI计算，得到基波电压的零轴分量；基于基波电压的D轴分量、Q轴分量和零轴分量，确定基波电压。
在一种可能的实现方式中，处理模块，具体用于计算正母线电压和负母线电压之和，并以该和的目标值和实时值之间的误差，进行PI计算，得到基波电压的D轴分量的目标值；计算正母线电压和负母线电压之差，并以该差的目标值和实时值之间的误差，进行PI计算，得到基波电压的零轴分量的目标值。
在一种可能的实现方式中，CVPI控制器的传递函数为：
；
其中， 为CVPI控制器的传递函数的函数值， 为CVPI控制器的比例增益系数， 为CVPI控制器的积分增益系数， 为基波电压的角频率， 为并联APF与电网之间的等效电感， 为电网供电侧的等效电感， 为电网供电侧的等效电感和并联APF与电网之间的等效电感之和， 为并联APF与电网之间的等效电阻， 为CVPI控制器的传递函数的输入量， 为虚数单位。
在一种可能的实现方式中，处理模块，具体用于基于负荷侧的实时电流的D轴分量、并联APF的交流侧的实时电流的D轴分量，以及多谐波控制器，确定谐波电压的D轴分量；基于负荷侧的实时电流的Q轴分量、并联APF的交流侧的实时电流的Q轴分量，以及多谐波控制器，确定谐波电压的Q轴分量；基于负荷侧的实时电流的零轴分量、并联APF的交流侧的实时电流的零轴分量，以及多谐波控制器，确定谐波电压的零轴分量；基于谐波电压的D轴分量、Q轴分量和零轴分量，确定谐波电压。
在一种可能的实现方式中，多谐波控制器的传递函数为：
；
其中， 为多谐波控制器的传递函数的函数值， 为谐波次数， 为第h次谐波频率下多谐振控制器的增益， 为谐振控制器的开环截止频率， ， 为基波电压的周期， 为基波电压的角频率， 为多谐波控制器的传递函数的输入量。
第三方面，本发明实施例提供了一种电子设备，其特征在于，电子设备包括存储器和处理器，该存储器存储有计算机程序，处理器用于调用并运行存储器中存储的计算机程序执行如上述第一方面以及第一方面中任一种可能的实现方式方法的步骤。
第四方面，本发明实施例提供了一种计算机可读存储介质，计算机可读存储介质存储有计算机程序，其特征在于，计算机程序被处理器执行时实现如上述第一方面以及第一方面中任一种可能的实现方式方法的步骤。
上述第二方面至第四方面中任一种实现方式所带来的技术效果可以参见第一方面对应实现方式所带来的技术效果，此处不再赘述。
 附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1是本发明实施例提供的一种三相四线制三电平并联有源电力滤波器结构的示意图；
图2是本发明实施例提供的一种并联APF的控制方法的控制逻辑图；
图3是本发明实施例提供的一种并联APF的控制方法的流程示意图；
图4是本发明实施例提供的一种基于复矢量的基波电流环路控制框图；
图5是本发明实施例提供的一种电流开环传递函数对应的波特图；
图6是本发明实施例提供的一种基于CVPI控制器的电流闭环传递函数对应的波特图；
图7是本发明实施例提供的另一种基于CVPI控制器的电流闭环传递函数对应的波特图；
图8是本发明实施例提供的一种基于CVPI与多谐振控制的复合电流控制框图；
图9是本发明实施例提供的一种不同增益系数的CVPI+18次谐振频率的谐振控制器下电流开环传递函数奈奎斯特图；
图10是本发明实施例提供的一种谐振控制器添加相位补偿环节前后CVPI+18次谐振频率的谐振控制器电流开环传递函数波特图；
图11是本发明实施例提供的一种基于CVPI+多谐波频率下谐振控制电流开环系统波特图；
图12是本发明实施例提供的一种CVPI+多谐振控制时电流波形及电网电流频谱图；
图13是本发明实施例提供的一种突加负载时的负载和并联APF的补偿电流波形图；
图14是本发明实施例提供的一种并联APF的控制装置的结构示意图；
图15是本发明实施例提供的一种电子设备的结构示意图。
 实施方式
以下描述中，为了说明而不是为了限定，提出了诸如特定系统结构、技术之类的具体细节，以便透彻理解本发明实施例。然而，本领域的技术人员应当清楚，在没有这些具体细节的其它实施例中也可以实现本发明。在其它情况中，省略对众所周知的系统、装置、电路以及方法的详细说明，以免不必要的细节妨碍本发明的描述。
在本发明的描述中，除非另有说明，“/”表示“或”的意思，例如，A/B可以表示A或B。本文中的“和/或”仅仅是一种描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。此外，“至少一个”“多个”是指两个或两个以上。“第一”、“第二”等字样并不对数量和执行次序进行限定，并且“第一”、“第二”等字样也并不限定一定不同。
在本申请实施例中，“示例性的”或者“例如”等词用于表示作例子、例证或说明。本申请实施例中被描述为“示例性的”或者“例如”的任何实施例或设计方案不应被解释为比其它实施例或设计方案更优选或更具优势。确切而言，使用“示例性的”或者“例如”等词旨在以具体方式呈现相关概念，便于理解。
此外，本申请的描述中所提到的术语“包括”和“具有”以及它们的任何变形，意图在于覆盖不排他的包含。例如包含了一系列步骤或模块的过程、方法、系统、产品或设备没有限定于已列出的步骤或模块，而是可选的还包括其他没有列出的步骤或模块，或可选的还包括对于这些过程、方法、产品或设备固有的其它步骤或模块。
为使本发明的目的、技术方案和优点更加清楚，下面将结合本发明的附图通过具体实施例来进行说明。
如背景技术，目前存在并联APF对各种频率电流谐波进行补偿时误差较大，补偿精度较低的技术问题。
为解决该技术问题，本发明实施例提供了一种并联APF的控制方法，应用于并联有源电力滤波器结构。图1为本发明实施例提供的一种三相四线制三电平并联有源电力滤波器结构的示意图。三相电网的非线性负荷为三相四线制二极管整流桥；三电平电压源型变换器通过输出滤波器连接到电网，构成并联型有源滤波器。如图1所示： ，  和  分别为电网供电侧的三相电压， ， 和 分别为电网供电侧的三相电流，  为中性线电流， 为电网供电侧的等效电感， 为并联APF与电网之间的等效电感，  为并联APF与电网之间的等效电阻，  为并联APF的直流侧的正母线电压，  为并联APF的直流侧的负母线电压，C 为并联APF的直流侧的正负母线电容， 、 、  和 为并联APF输出的补偿电流， 、 、 和 为电网负荷侧的负载电流。
图2为本发明实施例提供的一种并联APF的控制方法的控制逻辑图。本发明实施例提供的并联APF的控制方法的控制逻辑包括直流电压控制和交流电流控制两大部分。考虑到直流母线电压的均衡问题，在总压控制的基础上，设置了均压控制，其反馈信号为直流侧正负母线电压差U dc=U P－U N。电流控制部分由基波电流环路和谐波电流环路构成，基波d轴电流分量控制环路的指令为总压环的输出，实现对母线电压稳定控制，q轴电流分量控制环路的指令为0，实现基波电流和电压同相位，d、q轴电流环均采用CVPI控制器，零序电流环路指令为均压控制环路输出，通过对零序电流的调整，确保正负母线均压，环路采用PI控制器；谐波电流控制环路引入多谐振控制器，实现对负载侧各次谐波的高精度补偿，谐振控制器可灵活针对任意谐波进行设计。
基于图1和图2，图3为本发明实施例提供的一种并联APF的控制方法的流程示意图。该方法的执行主体为并联APF的控制装置。该方法包括步骤S101-S103。
S101、获取电网的负荷侧和并联APF的交流侧的实时电流，以及并联APF的直流侧的正母线电压和负母线电压。
S102、基于正母线电压和负母线电压，以及并联APF的交流侧的实时电流进行PI计算，得到基波电压。
本申请实施例中，基波电压与电网的供电侧的电压相位相同。
作为一种可能的实现方式，控制装置可以基于步骤S1021-S1025，确定基波电压。
S1021、基于正母线电压和负母线电压，进行总压控制和均压控制，得到基波电压的D轴分量的目标值和零轴分量的目标值；
作为一种可能的实现方式，控制装置可以基于步骤A1-A2，确定基波电压的D轴分量的目标值和零轴分量的目标值。
A1、计算正母线电压和负母线电压之和，并以该和的目标值和实时值之间的误差，进行PI计算，得到基波电压的D轴分量的目标值。
A2、计算正母线电压和负母线电压之差，并以该差的目标值和实时值之间的误差，进行PI计算，得到基波电压的零轴分量的目标值。
S1022、基于基波电压的D轴分量的目标值和并联APF的交流侧的实时电流的D轴分量之间的误差，以及CVPI控制器，进行PI计算，得到基波电压的D轴分量。
S1023、基于零和并联APF的交流侧的实时电流的Q轴分量之间的误差，以及CVPI控制器，进行PI计算，得到基波电压的Q轴分量。
S1024、基于基波电压的零轴分量的目标值和并联APF的交流侧的实时电流的零轴分量之间的误差，以及CVPI控制器，进行PI计算，得到基波电压的零轴分量；
S1025、基于基波电压的D轴分量、Q轴分量和零轴分量，确定基波电压。
在一些实施例中，CVPI控制器的传递函数为：
；
其中， 为CVPI控制器的传递函数的函数值， 为CVPI控制器的比例增益系数， 为CVPI控制器的积分增益系数， 为基波电压的角频率， 为并联APF与电网之间的等效电感， 为电网供电侧的等效电感， 为电网供电侧的等效电感和并联APF与电网之间的等效电感之和， 为并联APF与电网之间的等效电阻， 为CVPI控制器的传递函数的输入量， 为虚数单位。
可选的，在步骤S102之前，控制装置可以分别对电网的负荷侧和并联APF的交流侧的实时电流，进行DQ转换，得到电网的负荷侧的实时电流的D轴分量、Q轴分量和零轴分量，以及并联APF的交流侧的实时电流的D轴分量、Q轴分量和零轴分量。
需要说明的是，由三电平变换器dq0坐标系的数学模型可知，交流侧电流dq分量存在耦合。本发明实施例将PI控制器改进为CVPI控制器，实现电流解耦，并将CVPI控制器的零点设置为dq0坐标系下复矢量模型的极点，进行电流控制环路的设计。将dq复平面的复矢量表示为 ，由图2的控制逻辑图可得，基于复矢量的基波电流环路控制框图如图4所示。电流控制环路的CVPI控制器传递函数 为：
     ；
其中， 为所述CVPI控制器的比例增益系数， 为所述CVPI控制器的积分增益系数， 为所述基波电压的角频率。
需要说明的是，对于大功率APF装置，电流控制环路带宽远小于开关频率fs，可忽略SPWM调制的影响，对应的传递函数近似为1。所以引入CVPI控制器的电流开环传递函数 可以表示为：
   ；
令 ，可得电流闭环传递函数 为：
；
由上述公式可知，采用CVPI控制器，并根据零极点对消的原则设计，电流环路可实现解耦，并降为一阶系统。控制器 由电流控制环路带宽决定，示例性的，以20kVA三电平APF装置为例，对应的参数为Lg=0.05mH，Li=0.9mH，电阻r=0.5Ω，变换器的开关频率fs=10kHz，取电流控制环路带宽为1500Hz，可算得 =9.2， =4869。电流开环传递函数对应的波特图如图5所示，电流环路相位裕度为90°，控制系统稳定。其中，图5中的（a）为幅频特性曲线，图5中的（b）为相频特性曲线。
实际应用中，由于负载经常变化，且随着工作环境温度的不同，变换器和电网的电感元件参数会发生改变，在控制系统设计时，必须考虑控制环路的鲁棒性，由上述公式，根据拉氏变换的位移定理，可得静止坐标系下电流闭环传递函数 为：
；
令 为电网供电侧的等效电感和并联APF与电网之间的等效电感之和，可以得到一般带电流解耦的PI控制器下电流控制环路静止坐标系下闭环传递函数为：
；
假设随着环境的不同，实际电感值为理论值的m倍，图6和图7分别为m=0.5，1.0和1.5时，带电流解耦的PI控制器和基于CVPI控制器的电流闭环传递函数对应的波特图。由图6和图7可得，如果参数估计准确，两种控制方法都能实现dq电流分量解耦，基波频率信号无差控制，且具有良好的稳态性能。如果参数估计存在偏差，采用电流解耦的PI控制策略时，电流闭环特性增益随电感值变化较明显，而基于CVPI控制器的电流闭环增益在基波频率附近一直为1，说明基于CVPI控制方法的电流控制环路鲁棒性更好。
对于零轴电流控制环路，和dq电流控制环路独立，因此可以单独设计，由被控对象的模型可知，对应环路为1阶环节，本文采用PI控制器，设定零轴电流环路的带宽1500Hz，为了确保PI控制器对带宽频率处的相位不造成影响，将其转折频率设置为20Hz，得到零轴电流控制环路PI控制器比例增益k0p=1.6，积分增益k0i=200。
S103、基于负荷侧和并联APF的交流侧的实时电流进行谐波分析，得到谐波电压。
本申请实施例中，谐波电压用于表征负荷侧的谐波情况。
作为一种可能的实现方式，控制装置可以基于步骤S1031-S1034，确定谐波电压。
S1031、基于负荷侧的实时电流的D轴分量、并联APF的交流侧的实时电流的D轴分量，以及多谐波控制器，确定谐波电压的D轴分量。
S1032、基于负荷侧的实时电流的Q轴分量、并联APF的交流侧的实时电流的Q轴分量，以及多谐波控制器，确定谐波电压的Q轴分量。
S1033、基于负荷侧的实时电流的零轴分量、并联APF的交流侧的实时电流的零轴分量，以及多谐波控制器，确定谐波电压的零轴分量。
S1034、基于谐波电压的D轴分量、Q轴分量和零轴分量，确定谐波电压。
在一些实施例中，多谐波控制器的传递函数为：
；
其中， 为多谐波控制器的传递函数的函数值， 为谐波次数， 为第h次谐波频率下多谐振控制器的增益， 为谐振控制器的开环截止频率， ， 为基波电压的周期， 为基波电压的角频率， 为多谐波控制器的传递函数的输入量。
需要说明的是，对于三相对称供电系统，负载电流 的谐波频率主要以负序的5、11、17次，正序7、13、19次和零序6、9次为主。正负序电流分别变为 6、 12和 18次(正序谐波次数为正，负序谐波次数为负)，由于谐振控制器是余弦信号的内模，余弦函数为偶函数，谐振控制器可以实现正、负角频率下开环高增益控制。由上述分析，设计6、12和18次谐波频率的谐振控制器，实现对谐波电流的高精度控制。令多谐振控制器的传递函数GR(s)为：
；
其中：h为谐波次数，khr为第h次谐波频率下谐振控制器的增益，为了提升谐振控制器的频率适应性，设置了谐振控制器的开环截止频率ωc,从而构成准谐振控制器。
谐振控制器会在谐振频率右侧造成90°相位滞后，根据图3基于CVPI控制器的电流开环传递函数的相位曲线可以看出，在被补偿谐波频率处相位为-90°，引入式（6）的谐振控制器，必然影响控制系统的稳定性。因此，需要针对谐振控制器设计相位补偿环节，改进的谐振控制器GR1(s)可表示为：
；
其中：φh=hω0Ts。
图8为基于CVPI与多谐振控制的复合电流控制框图。由于各谐振控制器和CVPI控制器是并联连接，可以结合带CVPI控制器的电流控制环路分析某一谐振控制器的参数设计方法，其他谐振控制器参数设计可以按此类推。对于高次谐波控制，需要考虑SPWM环节和数字延时的影响，对应的延时时间为1.5Ts，Ts为变换器的开关周期，可将该延时环节等效为一阶惯性环节，对应的传递函数Gd(s)为：
；
CVPI+h次谐振频率的谐振控制器下电流开环传递函数 为：
；
考虑到谐振控制器的频率选择范围和谐振点频率增益的矛盾，一般ωc取3~5之间，根据 在谐振频率的相位裕度(PM)大于零的条件，确定增益系数khr，PM表达式为：
 ；
图9为不同增益系数的CVPI+18次谐振频率的谐振控制器下电流开环传递函数奈奎斯特图。图9为ωc=3，不同增益系数k18r，CVPI+18次谐振频率下谐振控制器的电流开环传递函数对应的奈奎斯特图，k18r从300到600变化，可以发现，随着k18r的增大，控制环路的相位裕度逐渐下降，当k18r=600时，系统相位裕度为25°。
图10为谐振控制器添加相位补偿环节前后CVPI+18次谐振频率的谐振控制器电流开环传递函数波特图。图10中（a）为幅频特性曲线，图10中（b）为相频特性曲线。由图10可得，引入相位补偿后，电流控制环路在谐振频率处的相位裕量得到明显改善。
同理，取ωc=3，根据6次和12次谐波频率处的电流控制环路相位裕度为正，确定对应谐振控制器的增益系数，得到k6r=1200，k12r=900。图8所示的基于CVPI+多谐振频率的谐振控制器电流开环传递函数 为：
；
在前述控制器参数设计的基础上，可以得到所提控制方法的电流开环传递函数对应的波特图如图11所示。图11为基于CVPI+多谐波频率下谐振控制电流开环系统波特图。与图4所示的CVPI控制相比可知，引入相位补偿的多谐振控制后，电流控制环路的带宽并未受到影响，但由于考虑了SPWM环节和数字实现的延时，电流控制环路的相位裕度降为45°，但控制系统依有一定的稳定裕度。零轴电流以三次谐波为主，可叠加三倍基波频率的谐振控制器，类似的方法，根据谐振频率处的相位裕度为正设计谐振控制器的参数，可取ωc=3，谐振控制器的增益系数k3r=950。
S104、基于基波电压和谐波电压，确定并联APF的交流侧的目标电压，并基于目标电压，确定并联APF中各开关管的占空比，以调整并联APF的交流侧的实时电压至目标电压。
本发明提供一种并联APF的控制方法，通过正母线电压和负母线电压，以及并联APF的交流侧的实时电流进行PI计算，得到基波电压，基于负荷侧和并联APF的交流侧的实时电流进行谐波分析，得到谐波电压，基于基波电压和谐波电压，确定并联APF的交流侧的目标电压，并基于目标电压，确定并联APF中各开关管的占空比，以调整并联APF的交流侧的实时电压至目标电压。由于基波电压与电网的供电侧的电压相位相同，可以表征供电侧的基波情况；谐波电压用于表征负荷侧的谐波情况，也即表征了负荷侧的电网元件参数的实时变化情况，如此确定的并联APF的交流侧的目标电压，既考量了供电侧的基波情况，又考量了负荷侧的电网元件参数的实时变化情况，使得最终负荷侧的谐波补偿与电网元件参数的变化相适应，减小了并联APF对电流谐波进行补偿时的误差，提高并联APF对电流谐波的补偿精度。
示例性的，以三相四线三电平并联型APF进行实例说明，系统的硬件电路和控制器参数如表1所示。控制系统用TMS320F2812构成。
表1
系统参数 数值大小
电网相电压有效值 220V
电网频率 50Hz
变流器侧电感Li 0.9mH
电网侧电感Lg 0.05mH
等效电阻r 0.5Ω
母线电压Udc 750V
母线电容 4700μF
APF额定容量 20kVA
CVPI控制器 kcp=9.2，kci=4869
零轴电流PI控制器 k0p=1.6，k0i=200
各谐振控制器 ωc=3，k3r=950，k6r=1200，k12r=900， k18r=600，
图12为本发明实施例提供的并联APF的控制方法的CVPI+多谐振控制时电流波形及电网电流频谱图。其中，图12中的（a）为电流波形图，图12中的（b）为电网电流频谱图。负载为15kW时，a相相关电流波形和电网电流谐波分布，其中 、 和 分别是a相的负载电流、电网电流和补偿电流，从电网电流的频谱分布可以看出，负载的特征次谐波电流得到明显补偿，电网电流质量较好，总谐波失真THD为3.5%。
图13为突加负载时的负载和并联APF的补偿电流波形，可以看出，控制系统的动态调节时间在一个工频周期以内，电流控制系统具有较快的跟踪性能。
应理解，上述实施例中各步骤的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本发明实施例的实施过程构成任何限定。
以下为本发明的装置实施例，对于其中未详尽描述的细节，可以参考上述对应的方法实施例。
图14示出了本发明实施例提供的一种并联APF的控制装置的结构示意图，该确定装置200包括：通信模块201和处理模块202。
通信模块201，用于获取电网的负荷侧和并联APF的交流侧的实时电流，以及并联APF的直流侧的正母线电压和负母线电压。
处理模块202，用于基于正母线电压和负母线电压，以及并联APF的交流侧的实时电流进行PI计算，得到基波电压，基波电压与电网的供电侧的电压相位相同。
处理模块202，还用于基于负荷侧和并联APF的交流侧的实时电流进行谐波分析，得到谐波电压，谐波电压用于表征负荷侧的谐波情况；
处理模块202，还用于基于基波电压和谐波电压，确定并联APF的交流侧的目标电压，并基于目标电压，确定并联APF中各开关管的占空比，以调整并联APF的交流侧的实时电压至目标电压。
在一种可能的实现方式中，处理模块202，还用于分别对电网的负荷侧和并联APF的交流侧的实时电流，进行DQ转换，得到电网的负荷侧的实时电流的D轴分量、Q轴分量和零轴分量，以及并联APF的交流侧的实时电流的D轴分量、Q轴分量和零轴分量。
在一种可能的实现方式中，处理模块202，具体用于基于正母线电压和负母线电压，进行总压控制和均压控制，得到基波电压的D轴分量的目标值和零轴分量的目标值；基于基波电压的D轴分量的目标值和并联APF的交流侧的实时电流的D轴分量之间的误差，以及CVPI控制器，进行PI计算，得到基波电压的D轴分量；基于零和并联APF的交流侧的实时电流的Q轴分量之间的误差，以及CVPI控制器，进行PI计算，得到基波电压的Q轴分量；基于基波电压的零轴分量的目标值和并联APF的交流侧的实时电流的零轴分量之间的误差，以及CVPI控制器，进行PI计算，得到基波电压的零轴分量；基于基波电压的D轴分量、Q轴分量和零轴分量，确定基波电压。
在一种可能的实现方式中，处理模块202，具体用于计算正母线电压和负母线电压之和，并以该和的目标值和实时值之间的误差，进行PI计算，得到基波电压的D轴分量的目标值；计算正母线电压和负母线电压之差，并以该差的目标值和实时值之间的误差，进行PI计算，得到基波电压的零轴分量的目标值。
在一种可能的实现方式中，CVPI控制器的传递函数为：
；
其中， 为CVPI控制器的传递函数的函数值， 为CVPI控制器的比例增益系数， 为CVPI控制器的积分增益系数， 为基波电压的角频率， 为并联APF与电网之间的等效电感， 为电网供电侧的等效电感， 为电网供电侧的等效电感和并联APF与电网之间的等效电感之和， 为并联APF与电网之间的等效电阻， 为CVPI控制器的传递函数的输入量， 为虚数单位。
在一种可能的实现方式中，处理模块202，具体用于基于负荷侧的实时电流的D轴分量、并联APF的交流侧的实时电流的D轴分量，以及多谐波控制器，确定谐波电压的D轴分量；基于负荷侧的实时电流的Q轴分量、并联APF的交流侧的实时电流的Q轴分量，以及多谐波控制器，确定谐波电压的Q轴分量；基于负荷侧的实时电流的零轴分量、并联APF的交流侧的实时电流的零轴分量，以及多谐波控制器，确定谐波电压的零轴分量；基于谐波电压的D轴分量、Q轴分量和零轴分量，确定谐波电压。
在一种可能的实现方式中，多谐波控制器的传递函数为：
；
其中， 为多谐波控制器的传递函数的函数值， 为谐波次数， 为第h次谐波频率下多谐振控制器的增益， 为谐振控制器的开环截止频率， ， 为基波电压的周期， 为基波电压的角频率， 为多谐波控制器的传递函数的输入量。
图15是本发明实施例提供的一种电子设备的结构示意图。如图15所示，该实施例的电子设备300包括：处理器301、存储器302以及存储在所述存储器302中并可在所述处理器301上运行的计算机程序303。所述处理器301执行所述计算机程序303时实现上述各方法实施例中的步骤，例如图3所示的步骤101至步骤104。或者，所述处理器301执行所述计算机程序303时实现上述各装置实施例中各模块/单元的功能，例如，图14所示通信模块201和处理模块202的功能。
示例性的，所述计算机程序303可以被分割成一个或多个模块/单元，所述一个或者多个模块/单元被存储在所述存储器302中，并由所述处理器301执行，以完成本发明。所述一个或多个模块/单元可以是能够完成特定功能的一系列计算机程序指令段，该指令段用于描述所述计算机程序303在所述电子设备300中的执行过程。例如，所述计算机程序303可以被分割成图14所示通信模块201和处理模块202。
所称处理器301可以是中央处理单元(Central Processing Unit，CPU)，还可以是其他通用处理器、数字信号处理器 (Digital Signal Processor，DSP)、专用集成电路 (Application Specific Integrated Circuit，ASIC)、现场可编程门阵列 (Field-Programmable Gate Array，FPGA) 或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件等。通用处理器可以是微处理器或者该处理器也可以是任何常规的处理器等。
所述存储器302可以是所述电子设备300的内部存储单元，例如电子设备300的硬盘或内存。所述存储器302也可以是所述电子设备300的外部存储设备，例如所述电子设备300上配备的插接式硬盘，智能存储卡（Smart Media Card，SMC），安全数字（Secure Digital，SD）卡，闪存卡（Flash Card）等。进一步地，所述存储器302还可以既包括所述电子设备300的内部存储单元也包括外部存储设备。所述存储器302用于存储所述计算机程序以及所述终端所需的其他程序和数据。所述存储器302还可以用于暂时地存储已经输出或者将要输出的数据。
所属领域的技术人员可以清楚地了解到，为了描述的方便和简洁，仅以上述各功能单元、模块的划分进行举例说明，实际应用中，可以根据需要而将上述功能分配由不同的功能单元、模块完成，即将所述装置的内部结构划分成不同的功能单元或模块，以完成以上描述的全部或者部分功能。实施例中的各功能单元、模块可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中，上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。另外，各功能单元、模块的具体名称也只是为了便于相互区分，并不用于限制本申请的保护范围。上述系统中单元、模块的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述或记载的部分，可以参见其它实施例的相关描述。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本发明的范围。
在本发明所提供的实施例中，应该理解到，所揭露的装置/终端和方法，可以通过其它的方式实现。例如，以上所描述的装置/终端实施例仅仅是示意性的，例如，所述模块或单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通讯连接可以是通过一些接口，装置或单元的间接耦合或通讯连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本发明各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。
所述集成的模块/单元如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本发明实现上述实施例方法中的全部或部分流程，也可以通过计算机程序来指令相关的硬件来完成，所述的计算机程序可存储于一计算机可读存储介质中，该计算机程序在被处理器执行时，可实现上述各个方法实施例的步骤。其中，所述计算机程序包括计算机程序代码，所述计算机程序代码可以为源代码形式、对象代码形式、可执行文件或某些中间形式等。所述计算机可读介质可以包括：能够携带所述计算机程序代码的任何实体或装置、记录介质、U盘、移动硬盘、磁碟、光盘、计算机存储器、只读存储器（Read-Only Memory，ROM）、随机存取存储器（Random Access Memory，RAM）、电载波信号、电信信号以及软件分发介质等。需要说明的是，所述计算机可读介质包含的内容可以根据司法管辖区内立法和专利实践的要求进行适当的增减，例如在某些司法管辖区，根据立法和专利实践，计算机可读介质不包括是电载波信号和电信信号。
以上所述实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的精神和范围，均应包含在本发明的保护范围之内。

Claims (10)

  1. 一种并联APF的控制方法，其特征在于，包括：
    获取电网的负荷侧和并联APF的交流侧的实时电流，以及所述并联APF的直流侧的正母线电压和负母线电压；
    基于所述正母线电压和负母线电压，以及并联APF的交流侧的实时电流进行PI计算，得到基波电压，所述基波电压与所述电网的供电侧的电压相位相同；
    基于所述负荷侧和并联APF的交流侧的实时电流进行谐波分析，得到谐波电压，所述谐波电压用于表征所述负荷侧的谐波情况；
    基于所述基波电压和所述谐波电压，确定所述并联APF的交流侧的目标电压，并基于所述目标电压，确定所述并联APF中各开关管的占空比，以调整所述并联APF的交流侧的实时电压至所述目标电压。
  2. 根据权利要求1所述的并联APF的控制方法，其特征在于，所述基于所述正母线电压和负母线电压，以及并联APF的交流侧的实时电流进行PI计算，得到基波电压，之前还包括：
    分别对所述电网的负荷侧和并联APF的交流侧的实时电流，进行DQ转换，得到电网的负荷侧的实时电流的D轴分量、Q轴分量和零轴分量，以及并联APF的交流侧的实时电流的D轴分量、Q轴分量和零轴分量。
  3. 根据权利要求2所述的并联APF的控制方法，其特征在于，所述基于所述正母线电压和负母线电压，以及并联APF的交流侧的实时电流进行PI计算，得到基波电压，包括：
    基于所述正母线电压和负母线电压，进行总压控制和均压控制，得到所述基波电压的D轴分量的目标值和零轴分量的目标值；
    基于所述基波电压的D轴分量的目标值和所述并联APF的交流侧的实时电流的D轴分量之间的误差，以及CVPI控制器，进行PI计算，得到所述基波电压的D轴分量；
    基于零和所述并联APF的交流侧的实时电流的Q轴分量之间的误差，以及CVPI控制器，进行PI计算，得到所述基波电压的Q轴分量；
    基于所述基波电压的零轴分量的目标值和所述并联APF的交流侧的实时电流的零轴分量之间的误差，以及CVPI控制器，进行PI计算，得到所述基波电压的零轴分量；
    基于所述基波电压的D轴分量、Q轴分量和零轴分量，确定所述基波电压。
  4. 根据权利要求3所述的并联APF的控制方法，其特征在于，所述基于所述正母线电压和负母线电压，进行总压控制和均压控制，得到所述基波电压的D轴分量的目标值和零轴分量的目标值，包括：
    计算所述正母线电压和负母线电压之和，并以该和的目标值和实时值之间的误差，进行PI计算，得到所述基波电压的D轴分量的目标值；
    计算所述正母线电压和负母线电压之差，并以该差的目标值和实时值之间的误差，进行PI计算，得到所述基波电压的零轴分量的目标值。
  5. 根据权利要求3所述的并联APF的控制方法，其特征在于，所述CVPI控制器的传递函数为：
    ；
    其中， 为所述CVPI控制器的传递函数的函数值， 为所述CVPI控制器的比例增益系数， 为所述CVPI控制器的积分增益系数， 为所述基波电压的角频率， 为所述并联APF与电网之间的等效电感， 为所述电网供电侧的等效电感， 为所述电网供电侧的等效电感和所述并联APF与电网之间的等效电感之和， 为所述并联APF与电网之间的等效电阻， 为所述CVPI控制器的传递函数的输入量， 为虚数单位。
  6. 根据权利要求1所述的并联APF的控制方法，其特征在于，所述基于所述负荷侧和并联APF的交流侧的实时电流进行谐波分析，得到谐波电压，包括：
    基于所述负荷侧的实时电流的D轴分量、并联APF的交流侧的实时电流的D轴分量，以及多谐波控制器，确定所述谐波电压的D轴分量；
    基于所述负荷侧的实时电流的Q轴分量、并联APF的交流侧的实时电流的Q轴分量，以及多谐波控制器，确定所述谐波电压的Q轴分量；
    基于所述负荷侧的实时电流的零轴分量、并联APF的交流侧的实时电流的零轴分量，以及多谐波控制器，确定所述谐波电压的零轴分量；
    基于所述谐波电压的D轴分量、Q轴分量和零轴分量，确定所述谐波电压。
  7. 根据权利要求6所述的并联APF的控制方法，其特征在于，所述多谐波控制器的传递函数为：
    ；
    其中， 为所述多谐波控制器的传递函数的函数值， 为谐波次数， 为第h次谐波频率下所述多谐振控制器的增益， 为所述谐振控制器的开环截止频率， ， 为所述基波电压的周期， 为所述基波电压的角频率， 为所述多谐波控制器的传递函数的输入量。
  8. 一种并联APF的控制装置，其特征在于，包括：
    通信模块，用于获取电网的负荷侧和并联APF的交流侧的实时电流，以及所述并联APF的直流侧的正母线电压和负母线电压；
    处理模块，用于基于所述正母线电压和负母线电压，以及并联APF的交流侧的实时电流进行PI计算，得到基波电压，所述基波电压与所述电网的供电侧的电压相位相同；
    所述处理模块，还用于基于所述负荷侧和并联APF的交流侧的实时电流进行谐波分析，得到谐波电压，所述谐波电压用于表征所述负荷侧的谐波情况；
    所述处理模块，还用于基于所述基波电压和所述谐波电压，确定所述并联APF的交流侧的目标电压，并基于所述目标电压，确定所述并联APF中各开关管的占空比，以调整所述并联APF的交流侧的实时电压至所述目标电压。
  9. 一种电子设备，其特征在于，所述电子设备包括存储器和处理器，该存储器存储有计算机程序，所述处理器用于调用并运行所述存储器中存储的计算机程序执行如权利要求1至7中任一项所述的方法。
  10. 一种计算机可读存储介质，所述计算机可读存储介质存储有计算机程序，其特征在于，所述计算机程序被处理器执行时实现如上的权利要求1至7中任一项所述方法的步骤。
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102638043A (zh) * 2012-04-12 2012-08-15 浙江大学 一种apf并联系统及其控制方法
CN106786647A (zh) * 2016-12-27 2017-05-31 三峡大学 一种三相四线制并联apf双闭环非线性复合控制方法
CN107732915A (zh) * 2017-10-24 2018-02-23 江苏大学 一种并联型有源电力滤波器的简化控制方法
US20210391719A1 (en) * 2019-04-17 2021-12-16 Shandong University Hybrid cascaded apf topology and control method therefor
CN115036929A (zh) * 2022-06-09 2022-09-09 国网河北省电力有限公司电力科学研究院 一种并联apf的控制方法及装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102638043A (zh) * 2012-04-12 2012-08-15 浙江大学 一种apf并联系统及其控制方法
CN106786647A (zh) * 2016-12-27 2017-05-31 三峡大学 一种三相四线制并联apf双闭环非线性复合控制方法
CN107732915A (zh) * 2017-10-24 2018-02-23 江苏大学 一种并联型有源电力滤波器的简化控制方法
US20210391719A1 (en) * 2019-04-17 2021-12-16 Shandong University Hybrid cascaded apf topology and control method therefor
CN115036929A (zh) * 2022-06-09 2022-09-09 国网河北省电力有限公司电力科学研究院 一种并联apf的控制方法及装置

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