WO2023236502A1 - 像素驱动电路、像素驱动方法及显示面板 - Google Patents

像素驱动电路、像素驱动方法及显示面板 Download PDF

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Publication number
WO2023236502A1
WO2023236502A1 PCT/CN2022/140911 CN2022140911W WO2023236502A1 WO 2023236502 A1 WO2023236502 A1 WO 2023236502A1 CN 2022140911 W CN2022140911 W CN 2022140911W WO 2023236502 A1 WO2023236502 A1 WO 2023236502A1
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Prior art keywords
transistor
terminal
capacitor
scan line
pixel
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English (en)
French (fr)
Inventor
周仁杰
袁海江
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HKC Co Ltd
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HKC Co Ltd
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
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    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
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    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
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    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
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    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
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    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
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    • G—PHYSICS
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving

Definitions

  • the present disclosure belongs to the field of display technology, and specifically relates to a pixel driving circuit, a pixel driving method and a display panel.
  • OLED Organic Light Emitting Diode, organic light emitting diode
  • OLED Organic Light Emitting Diode, organic light emitting diode
  • the present disclosure provides a pixel driving circuit, a pixel driving method and a display panel, which can reduce power consumption and achieve power saving.
  • a first aspect of the present disclosure provides a pixel driving circuit, including:
  • the first pixel circuit includes a first transistor, a first driving transistor, a first capacitor and a first light-emitting element.
  • the control end of the first transistor is connected to the first scan line, and the first end of the first transistor is connected to the first scan line.
  • a data line is connected.
  • the second terminal of the first transistor, the control terminal of the first driving transistor and the first terminal of the first capacitor are connected to the first node A.
  • the first terminal of the first driving transistor is connected to a data line.
  • the terminal is connected to the first power signal terminal, the second terminal of the first driving transistor is connected to the first terminal of the first light-emitting element, and the second terminals of the first light-emitting element and the first capacitor are both connected to The second power signal terminal is connected;
  • the second pixel circuit includes a second transistor, a second drive transistor, a second capacitor and a second light-emitting element, the control terminal of the second transistor is connected to the second scan line, the second The first end of the transistor is connected to the second data line, the second end of the second transistor, the control end of the second driving transistor and the first end of the second capacitor are connected to the second node B, the The first terminal of the second driving transistor is connected to the first power signal terminal, the second terminal of the second driving transistor is connected to the first terminal of the second light-emitting element, the second light-emitting element and the first The second ends of the capacitors are connected to the third power signal end, and the second data line and the first data line have opposite polarities; a charge sharing switch,
  • a second aspect of the present disclosure provides a pixel driving method for driving a pixel circuit.
  • the pixel driving method includes: a charging stage, using the scanning signal of the first scanning line to turn on the first transistor, using the The scan signal of the second scan line turns on the second transistor, and at the same time, the scan signal of the third scan line is used to close the charge sharing switch; in the light-emitting phase, the scan signal of the first scan line is used to close the third transistor.
  • a transistor using the scan signal of the second scan line to turn off the second transistor, and at the same time, using the scan signal of the third scan line to turn off the charge sharing switch; in the data polarity switching stage, using the third scan line
  • the scan signal of the scan line turns on the charge sharing switch, and at the same time, the scan signal of the first scan line is used to turn off the first transistor, and the scan signal of the second scan line is used to turn off the second transistor.
  • a third aspect of the present disclosure provides a display panel, including a pixel unit and the pixel driving circuit described in any one of the above, and the pixel driving circuit corresponds to the pixel unit one-to-one.
  • the disclosed pixel driving circuit, pixel driving method and display panel can be used to save power.
  • the pixel driving circuit includes a first pixel circuit and a second pixel circuit respectively connected to a first data line and a second data line of opposite polarity, and a charge sharing switch provided in the first pixel circuit and the second pixel circuit;
  • the charge sharing switch neutralizes the voltages of the first data line and the second data line, so that the voltages of the first data line and the second data line return to the intermediate value.
  • the first data line and The starting point of the voltage of the second data line becomes the intermediate value, making it easier to reach the target voltage and thus achieve the purpose of saving power.
  • FIG. 1 shows a schematic diagram of the pixel driving circuit provided by Embodiment 1 of the present disclosure.
  • FIG. 2 shows a schematic structural diagram of the first pixel circuit and the second pixel circuit provided with an inverter according to Embodiment 1 of the present disclosure.
  • FIG. 3 shows the process of changing the data voltage in the data line polarity provided by Embodiment 1 of the present disclosure.
  • Figure 4 shows the polarity changes of the data lines under different frame numbers provided by Embodiment 1 of the present disclosure.
  • FIG. 5 shows a schematic flowchart of a pixel driving method provided by Embodiment 2 of the present disclosure.
  • FIG. 6 shows a schematic flowchart of a pixel driving method for adding an inverter provided by Embodiment 2 of the present disclosure.
  • FIG. 7 shows the potential conditions of each scan line at different timings provided by Embodiment 2 of the present disclosure.
  • FIG. 8 shows a schematic structural diagram of the charging stage provided by Embodiment 2 of the present disclosure.
  • FIG. 9 shows a schematic structural diagram of the light-emitting stage provided by Embodiment 2 of the present disclosure.
  • Figure 10 shows a schematic structural diagram of the data polarity switching stage provided by Embodiment 2 of the present disclosure.
  • FIG. 11 shows a schematic structural diagram of a pixel circuit with an inverter in the charging stage according to Embodiment 2 of the present disclosure.
  • FIG. 12 shows a schematic structural diagram of a pixel circuit with an inverter in the light-emitting stage according to Embodiment 2 of the present disclosure.
  • FIG. 13 shows a schematic structural diagram of a pixel circuit with an inverter in the data polarity switching stage provided by Embodiment 2 of the present disclosure.
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments may, however, be embodied in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concepts of the example embodiments. To those skilled in the art.
  • first and second are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, features defined as “first” and “second” may explicitly or implicitly include one or more of these features.
  • “plurality” means two or more than two, unless otherwise expressly and specifically limited.
  • connection in this disclosure, unless otherwise clearly stated and limited, the terms “assembly”, “connection” and other terms should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral body; it can be a mechanical connection. A connection can also be an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be an internal connection between two elements or an interaction between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in this disclosure can be understood according to specific circumstances.
  • an embodiment of the present disclosure provides a pixel driving circuit, which includes a first pixel circuit 1 , a second pixel circuit 2 and a charge sharing switch T7 .
  • the first pixel circuit 1 includes a first transistor T1 , a first driving transistor T2 , a first capacitor C1 and a first light-emitting element L1 .
  • the control end of the first transistor T1 is connected to the first scan line 11 connection, the first end of the first transistor T1 is connected to the first data line 12 , the first transistor T1 is used to receive the scanning signal of the first scanning line 11 (ie: the first scanning signal Scan1), so as to connect the first data line 12
  • the first data signal DATA1 is input to the first capacitor C1; the second end of the first transistor T1, the control end of the first driving transistor T2 and the first end of the first capacitor C1 are connected to the first node A, that is, the first The voltage value corresponding to the data signal DATA1 is transmitted to the first node A; the first terminal of the first driving transistor T2 is connected to the first power signal terminal VDD, and the second terminal of the first driving transistor T2 is connected to the third terminal of the first light-emitting
  • the second pixel circuit 2 includes a second transistor T3, a second driving transistor T4, a second capacitor C2 and a second light-emitting element L2.
  • the control end of the second transistor T3 is connected to the second scan line 21.
  • the first end of the second transistor T3 is connected to the second data line 22 .
  • the second transistor T3 is used to receive the scan signal of the second scan line 21 (ie, the second scan signal Scan2 ), so as to convert the second scan signal of the second data line 22 to the second transistor T3 .
  • the second data signal DATA2 is input to the second capacitor C2; the second terminal of the second transistor T3, the control terminal of the second driving transistor T4 and the first terminal of the second capacitor C2 are connected to the second node B, that is, the second data signal
  • the voltage value corresponding to DATA2 is transmitted to the second node B.
  • the first terminal of the second driving transistor T4 is connected to the first power signal terminal VDD.
  • the second terminal of the second driving transistor T4 is connected to the first terminal of the second light-emitting element L2.
  • the second light-emitting element L2 and the second terminal of the second capacitor C2 are connected to the third power signal terminal VSS2, and the second data line 22 and the first data line 12 have opposite polarities.
  • the control terminal of the charge sharing switch T7 is connected to the third scan line 3
  • the first terminal of the charge sharing switch T7 is connected to the first node A
  • the second terminal of the charge sharing switch T7 is connected to the second node B.
  • the control end of the charge sharing switch T7 can respond to the scan signal of the third scan line 3 (ie, the third scan signal Scan3), so that the first node A and the second node B are connected.
  • the opposite polarity of the first data line 12 and the second data line 22 refers to the voltage value corresponding to the first data signal DATA1 provided by the first data line 12 and the second data provided by the second data line 22 .
  • the voltage values corresponding to the signal DATA2 are positive and negative to each other; for example, the voltage value corresponding to the first data signal DATA1 is positive, and the voltage value corresponding to the second data signal DATA2 is negative; the voltage value corresponding to the first data signal DATA1 is negative value, the voltage value corresponding to the second data signal DATA2 is a positive value.
  • the control end of the charge sharing switch T7 is used to receive the third scan signal Scan3 sent by the third scan line 3, turn on the charge sharing switch T7, and connect the first node A and the second node B, so that The voltage value at the first node A and the voltage value at the second node B become the average value V average between them; when it is necessary to reverse the polarity of the first data line 12 and the second data line 22
  • the average value V is changed, so that it is easier to reach the target voltage V target of the first data line 12 and the second data line 22 without changing from the current voltage V current to the target voltage V target , saving the reversal. voltage, thereby achieving the purpose of saving power.
  • the voltage value corresponding to the first data signal DATA1 is a positive value
  • the voltage value corresponding to the second data signal DATA2 is a negative value
  • the charge passes through
  • the shared switch T7 connects the first node A and the second node B, so that the voltage value V1 at the first node A and the voltage value at the second node B become the average value V average between them;
  • the voltage value corresponding to the first data signal DATA1 changes from the average value V to a negative value on average
  • the voltage value corresponding to the second data signal DATA2 changes from the average value V to a positive voltage value on average.
  • N is an integer greater than 1; compared to the voltage value corresponding to the first data signal DATA1 changes from a positive value to a negative value, and the voltage value corresponding to the second data signal DATA2 changes from a negative value When the value becomes a positive value, less reverse voltage is consumed, thereby saving power.
  • the first pixel circuit also includes a third transistor T5 , a third capacitor C3 and a first inverter 13 .
  • the control end of the third transistor T5 is connected to the first scan line 11 .
  • the third transistor T5 The first end of is connected to the first power signal terminal VDD, the second end of the third transistor T5, the first end of the first driving transistor T2 and the first end of the third capacitor C3 are connected to the third node C, and the third capacitor
  • the second end of C3 is connected to the fourth power signal end VSS3; the input end of the first inverter 13 is connected to one end of the first scan line 11, and the output end of the first inverter 13 is connected to the third transistor T5.
  • the control terminal is connected.
  • the second pixel circuit 2 also includes a fourth transistor T6, a fourth capacitor C4 and a second inverter 23.
  • the control end of the fourth transistor T6 is connected to the second scan line 21, and the first end of the fourth transistor T6 is connected to the first scan line 21.
  • the power signal terminal VDD is connected, the second terminal of the fourth transistor T6, the first terminal of the second driving transistor T4 and the first terminal of the fourth capacitor C4 are connected to the fourth node D, and the second terminal of the fourth capacitor C4 is connected to the fourth node D.
  • the fifth power signal terminal VSS4 is connected, the input terminal of the second inverter 23 is connected to one end of the second scan line 21, and the output terminal of the second inverter 23 is connected to the control terminal of the fourth transistor T6.
  • the first inverter 13 and the second inverter 23 can adjust the scan signals input by the first scan line 11 and the second scan line 21, that is, the first scan signal Scan1 and the second scan signal Scan2 can be adjusted.
  • the level of , after passing through the first inverter 13, the first scan signal Scan1 is converted to low level. That is, the first scan signal Scan1 controls the third transistor T5 to be turned on through the first inverter 13; the second scan signal Scan2 controls the fourth transistor T6 to be turned on through the second inverter 23.
  • the third transistor T5 and the fourth transistor T6 respectively receive the input of the first scan signal Scan1 and the second scan signal Scan2 and are turned on, and input the first power signal to
  • the third capacitor C3 and the fourth capacitor C4 store electricity; while switching the data polarity, the first power signal terminal VDD is disconnected, and the third transistor T5 and the fourth transistor T6 receive the first scan signal Scan1 and the second scan signal respectively.
  • the signal Scan2 is used to control the third transistor T5 and the fourth transistor T6 to turn off, and the third capacitor C3 and the fourth capacitor discharge to the third node C and the fourth node D respectively to supplement the third transistor T5 and the fourth transistor T6.
  • the first inverter 13, the second inverter 23, the third capacitor C3 and the fourth capacitor C4 can achieve the second power saving effect, and can also reduce the power consumption of the first power signal terminal VDD and reduce the use cost. ; In addition, the first light-emitting element L1 and the second light-emitting element L2 can also be protected to a certain extent.
  • first transistor T1, the second transistor T3, the third transistor T5, the fourth transistor T6, and the charge sharing switch T7 are the same as the first driving transistor T2 and the second driving transistor T4, and all have a first terminal, a first terminal, and a first terminal. Two terminals and control terminal. The control terminal of each transistor corresponds to the gate of the transistor, one of the first terminal and the second terminal corresponds to the source of the transistor, and the other corresponds to the drain of the transistor.
  • the first driving transistor T2, the second driving transistor T4, the first transistor T1, the second transistor T3, the third transistor T5, the fourth transistor T6 and the charge sharing switch T7 of the embodiment of the present disclosure may all be oxide films.
  • Transistors that is, the material of the active layer of each transistor can be an oxide.
  • metal oxide materials such as IGZO (Indium Gallium Zinc Oxide) can be used, or a-Si (amorphous silicon) can be used.
  • Thin film transistors can be specifically designed according to different implementation methods.
  • each transistor can be a bottom-gate type, that is, the gate electrode of the transistor is located below the active layer (close to the side of the glass substrate), so that the product can be appropriately thinned.
  • each transistor can also be a bottom-gate type.
  • Top grid type depending on the specific situation.
  • each transistor may be an enhancement mode or a depletion mode transistor, which is not specifically limited in the embodiments of the present disclosure.
  • all transistors in the pixel driving circuit may be N-type thin film transistors, namely: the first driving transistor T2, the second driving transistor T4, the first transistor T1, the second transistor T3, the third transistor T5, the fourth transistor T6 and
  • the charge sharing switches T7 can all be N-type thin film transistors, and the driving voltage of each transistor corresponds to a high-level voltage; the first power signal input by the aforementioned first power signal terminal VDD can be a DC high-level signal, and the second power supply
  • the second power signal of the signal terminal VSS1, the third power signal of the third power signal terminal VSS2, the fourth power signal of the fourth power signal terminal VSS3 and the fifth power signal of the fifth power signal terminal VSS4 may be a DC low level. Signal.
  • the transistors in the pixel driving circuit are not limited to the aforementioned N-type thin film transistors, and may also be all P-type thin film transistors, or some may be N-type thin film transistors and some may be P-type thin film transistors.
  • the transistor is a P-type thin film transistor, its driving voltage may correspond to a low-level voltage.
  • the first light-emitting element L1 can be a current-driven light-emitting element L, which is controlled to emit light by the current flowing through the first driving transistor T2;
  • the second light-emitting element L2 can be a current-driven light-emitting element, which can be controlled by the current flowing through the second driving transistor T2.
  • the current of the driving transistor T4 controls it to emit light;
  • the first light-emitting element L1 and the second light-emitting element L2 can be organic light-emitting diodes (OLED), that is to say, this pixel driving circuit can be applied to an OLED display device.
  • OLED organic light-emitting diodes
  • the first end of the first light-emitting element L1 is the anode of the OLED, and the second end of the first light-emitting element L1 is the cathode of the OLED; the first end of the second light-emitting element L2 is the anode of the OLED, and the second end of the second light-emitting element L2 is the anode of the OLED.
  • the terminal is the cathode of the OLED; that is, the anode of the organic light-emitting diode in the first pixel circuit 1 is connected to the second terminal of the first driving transistor T2, and the cathode of the organic light-emitting diode in the first pixel circuit 1 is connected to the second power signal terminal.
  • VSS1 is connected; the anode of the organic light-emitting diode in the second pixel circuit 2 is connected to the second terminal of the second driving transistor T4, and the cathode of the organic light-emitting diode in the second pixel circuit 2 is connected to the third power signal terminal VSS2.
  • first pixel circuit 1 and the second pixel circuit 2 can adopt a 2T1C structure, or can also adopt a 4T1C or 4T2C structure, and can be specifically designed according to different display panels.
  • first pixel circuit 1 and the second pixel circuit 2 can be located in the same column or in the same row. They can be designed according to different display panels and are not specifically limited here.
  • charge sharing is not performed between adjacent pixel driving circuits, that is, the two pixel circuits form a group of pixel driving circuits and perform charge sharing.
  • the first data line 12 and the second data line 22 may be located on the same side of the first pixel circuit 1 and the second pixel circuit 2, or They may be located on opposite sides of the first pixel circuit 1 and the second pixel circuit 2 .
  • the display panel includes a display area and a non-display area, in which the charge sharing switch T7 is disposed in the non-display area to prevent the charge sharing switch T7 from affecting the display effect of the display panel.
  • the scanning direction of the pixel driving circuit can be from the first row to the last row; for example, the first scanning signal Scan1 is provided by the Nth row scanning signal line, and the second scanning signal Scan2 is provided by the N+1th row scanning signal line.
  • the third scanning signal Scan3 is provided by the N+2th row scanning signal line.
  • N is a positive integer greater than or equal to 1.
  • the first transistor T1 When charging the first capacitor C1 and the second capacitor C2, the first transistor T1 receives the first scan signal Scan1 of the first scan line 11 and is turned on, and the second transistor T3 receives the second scan signal Scan1 of the second scan line 21.
  • the scan signal Scan2 is turned on, so that the first data signal DATA1 of the first data line 12 and the second data signal DATA2 of the second data line 22 are respectively input to the first node A and the second node B, and the first capacitor C1 and the second data signal DATA2 are respectively input to the first node A and the second node B.
  • the second capacitor C2 is charged, and the first capacitor C1 and the second capacitor C2 are charged to the voltage value corresponding to the first data signal DATA1 and the second data signal DATA2, and at this time, it flows through the first driving transistor T2 and the second driving transistor T2.
  • the voltage value of the transistor T4 is less than the threshold voltage, therefore, the first light-emitting element L1 and the second light-emitting element L2 do not emit light; during the light-emitting phase, the first transistor T1 and the second transistor T3 receive the first scanning signal Scan1 and the second scanning signal Scan2 respectively.
  • the charge sharing switch T7 receives the third scanning signal Scan3 of the third scanning line 3 and is turned on, connecting the first node A and the second node B, so that the first capacitor C1 stores The charge is shared with the charge stored in the second capacitor C2, thereby neutralizing the voltage, so that the voltage values at the first node A and the second node B are at the average value V average , so that less voltage is required when reversing. , thereby achieving the purpose of power saving; in addition, by neutralizing the voltages on the first data line 12 and the second data line 22, the power consumption of the source line can also be reduced, making it more durable.
  • the blanking area is a period of time during which each picture is blank and is not actually displayed.
  • the pixel driving circuit of the embodiment of the present disclosure adopts a charge sharing switch T7 added between two adjacent pixel circuits, which can neutralize the voltage on the data line with opposite polarity and reduce the startup during polarity deflection. voltage, thereby achieving the effect of power saving; in addition, adding an inverter and capacitor in each pixel circuit can better protect the light-emitting elements, and can also achieve the purpose of second power saving and reduce the first power supply. signal power consumption.
  • Embodiment 2 provides a pixel driving method for driving the pixel circuit of Embodiment 1.
  • the pixel driving method includes:
  • Step S100 charging stage t1, use the scan signal of the first scan line 11 to turn on the first transistor T1, use the scan signal of the second scan line 21 to turn on the second transistor T3, and at the same time, use the scan signal of the third scan line 3 to turn off the charge. Shared switch T7.
  • Step S200 light emitting stage t2, use the scan signal of the first scan line 11 to turn off the first transistor T1, use the scan signal of the second scan line 21 to turn off the second transistor T3, and at the same time, use the scan signal of the third scan line 3 to turn off the charge. Shared switch T7.
  • Step S300a data polarity switching stage t3, use the scan signal of the third scan line 3 to turn on the charge sharing switch T7, at the same time, use the scan signal of the first scan line 11 to turn off the first transistor T1, use the scan of the second scan line 21 The signal turns off the second transistor T3.
  • the pixel driving method (that is, the working process) corresponding to the pixel driving circuit shown in FIG. 1 or 2 will be described in detail below with reference to the working timing diagram of the pixel driving circuit shown in FIG. 7 .
  • the first scan signal Scan1 is high level, the second scan signal Scan2 is high level, and the third scan signal Scan3 is low level; so that the first The transistor T1 and the second transistor T3 are turned on, and the charge sharing switch T7 is turned off; in other embodiments, when the first transistor T1, the second transistor T3 and the charge sharing switch T7 are P-type thin film transistors, the first scanning signal Scan1 and the second scanning signal Scan1 are turned on.
  • the second scanning signal Scan2 is at low level, and the third scanning signal Scan3 is at high level.
  • the first scan signal Scan1 is at a high level
  • the second scan signal Scan2 is at a high level
  • the third scan signal Scan3 is at a low level, that is, the first transistor T1 and the second transistor T3 are turned on.
  • the first data signal DATA1 in the first data line 12 is transmitted to the first terminal of the first capacitor C1
  • the second data signal DATA2 in the second data line 22 is transmitted to the first terminal of the second capacitor C2 to transmit the data to the first terminal of the first capacitor C1.
  • a capacitor C1 and a second capacitor C2 are charged to Vdata; and at this time, the voltages of the first driving transistor T2 and the second driving transistor T4 are less than the threshold voltage, and the light-emitting element L does not emit light.
  • charge sharing switch T7 is not turned on, charge sharing is not performed.
  • the first scan signal Scan1 is low level, the second scan signal Scan2 is low level, and the third scan signal Scan3 is low level; so that the first scan signal Scan1 is low level, the second scan signal Scan2 is low level, and the third scan signal Scan3 is low level;
  • the transistor T1, the second transistor T3 and the charge sharing switch T7 are turned off; in other embodiments, when the first transistor T1, the second transistor T3 and the charge sharing switch T7 are P-type thin film transistors, the first scanning signal Scan1 and the second The scanning signal Scan2 and the third scanning signal Scan3 are high level.
  • the first scan signal Scan1, the second scan signal Scan2 and the third scan signal Scan3 are all low level, that is, the first transistor T1, the second transistor T3 and the charge sharing switch T7 are all turned off, the first The capacitor C1 and the second capacitor C2 are discharged to drive the first driving transistor T2 and the second driving transistor T4 to turn on, so that the first light-emitting element L1 and the second light-emitting element L2 emit light.
  • the first scan signal Scan1 is low level
  • the second scan signal Scan2 is low level
  • the third scan signal Scan3 is high level
  • the first transistor T1 and the second transistor T3 are turned off, and the charge sharing switch T7 is turned on; in other embodiments, when the first transistor T1, the second transistor T3, and the charge sharing switch T7 are P-type thin film transistors, the first scan signal Scan1 and the second scan signal Scan2 are at high level, and the third scan signal Scan3 is at low level.
  • the charge sharing switch T7 receives the third scan signal Scan3 of the third scan line 3 and is turned on, connecting the first node A and the second node B, so that the charge stored in the first capacitor C1 and the second capacitor C2 are stored.
  • the charge is shared, and then the voltage is neutralized, so that the voltage values at the first node A and the second node B are at the average value V average , so that less voltage is required when reversing, thereby achieving the purpose of saving power.
  • the power consumption of the source line can also be reduced, making it more durable.
  • the first pixel circuit also includes a third transistor T5, a third capacitor C3 and a first inverter 13.
  • the control end of the third transistor T5 is connected to the first scan line. 11 is connected, the first terminal of the third transistor T5 is connected to the first power signal terminal VDD, the second terminal of the third transistor T5, the first terminal of the first driving transistor T2 and the first terminal of the third capacitor C3 are connected to the first terminal of the third transistor T5.
  • the second end of the third capacitor C3 is connected to the fourth power signal terminal VSS3; one end of the first inverter 13 is connected to one end of the first scan line 11, and the output end of the second inverter is connected to The control end of the third transistor T5 is connected; the second pixel circuit 2 also includes a fourth transistor T6, a fourth capacitor C4 and a second inverter 23.
  • the control end of the fourth transistor T6 is connected to the second scan line 21.
  • the first terminal of T6 is connected to the first power signal terminal VDD, the second terminal of the fourth transistor T6, the first terminal of the second driving transistor T4 and the first terminal of the fourth capacitor C4 are connected to the fourth node D.
  • the second end of the capacitor C4 is connected to the fifth power signal terminal VSS4, one end of the second inverter 23 is connected to one end of the second scan line 21, and the output end of the second inverter is connected to the control of the fourth transistor T6. end connected.
  • the data polarity switching stage also includes: turning off the third transistor T5 and the fourth transistor T6 by disconnecting the first power signal terminal VDD. That is, step S300b: data polarity switching stage t3, use the scan signal of the third scan line 3 to turn on the charge sharing switch T7, at the same time, use the scan signal of the first scan line 11 to turn off the first transistor T1, use the second scan line
  • the scan signal of 21 turns off the second transistor T3; by disconnecting the first power signal terminal VDD, the third transistor T5 and the fourth transistor T6 are turned off.
  • the third transistor T5 and the fourth transistor T6 are respectively turned on by the input of the first scan signal Scan1 and the second scan signal Scan2, and input the first power signal. to store electricity in the third capacitor C3 and the fourth capacitor C4; as shown in Figure 13, the first power signal terminal VDD is disconnected while switching the data polarity to control the third transistor T5 and the fourth transistor T6 to turn off.
  • the third capacitor C3 and the fourth capacitor C4 discharge to the third node C and the fourth node D respectively to supplement the voltages at the second ends of the third transistor T5 and the fourth transistor T6 to drive the first driving transistor T2 and the second driving transistor.
  • T4 is turned on, causing the first light-emitting element L1 and the second light-emitting element L2 to emit light.
  • the first inverter 13, the second inverter 23, the third capacitor C3 and the fourth capacitor C4 can achieve the second power saving effect, and can also reduce the power consumption of the first power signal terminal VDD and reduce the use cost. ;
  • the first light-emitting element L1 and the second light-emitting element L2 can also be protected to a certain extent.
  • the third embodiment provides a display panel, which includes a pixel unit and the pixel driving circuit mentioned in the first embodiment, and the pixel driving circuit corresponds to the pixel unit one-to-one.
  • the display panel can be an organic light-emitting diode (OLED) display panel, electronic paper, mobile phone, tablet computer, television, monitor, notebook computer, digital photo frame, navigator, or any other product or component with a display function.
  • OLED organic light-emitting diode
  • the pixel unit includes a display area and a non-display area.
  • the charge sharing switch T7 is located in the non-display area.

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Abstract

本公开涉及一种像素驱动电路、像素驱动方法及显示面板，像素驱动电路包括第一像素电路和第二像素电路，第一像素电路和第二像素电路分别连接于第一扫描线和第二扫描线以及极性相反的第一数据线和第二数据线；像素驱动电路还包括：电荷共享开关，电荷共享开关的控制端连接于第二扫描线，电荷共享开关的第一端连接于第一像素电路，电荷共享开关的第二端连接于第二像素电路。

Description

像素驱动电路、像素驱动方法及显示面板
本申请要求于2022年6月8日提交中国专利局，申请号为CN 202210638239.6，申请名称为“像素驱动电路、像素驱动方法及显示面板”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开属于显示技术领域，具体涉及一种像素驱动电路、像素驱动方法及显示面板。
背景技术
OLED(Organic Light Emitting Diode，有机发光二极管)显示面板具有高亮度、宽视角、响应速度快、低功耗等优点，目前已被广泛地应用于高性能显示领域中。
但在不断反转数据线极性的过程中，电源会被不断的消耗掉，造成资源的浪费。
申请内容
本公开提供一种像素驱动电路、像素驱动方法及显示面板，能够降低功耗，并达到省电的作用。
本公开第一方面提供了一种像素驱动电路，包括：
第一像素电路，包括第一晶体管、第一驱动晶体管、第一电容和第一发光元件，所述第一晶体管的控制端与第一扫描线连接，所述第一晶体管的第一端与第一数据线连接，所述第一晶体管的第二端、所述第一驱动晶体管的控制端和所述第一电容的第一端连接于第一节点A，所述第一驱动晶体管的第一端与第一电源信号端连接，所述第一驱动晶体管的第二端与所述第一发光元件的第一端连接，所述第一发光元件和所述第一电容的第二端均与第二电源信号端连接；第二像素电路，包括第二晶体管、第二驱动晶体管、第二电容和第二发光元件，所述第二晶体管的控制端与第二扫描线连接，所述第二晶体管的第一端与第二数据线连接，所述第二晶体管的第二端、所述第二驱动晶体管的控制端和所述第二电容的第一端连接于第二节点B，所述第二驱动晶体管的第一端与第一电源信号端连接，所述第二驱动晶体管的第二端与所述第二发光元件的第一端连接，所述第二发光元件和所述第一电容的第二端均与第三电源信号端连接，且所述第二数据线与所述第一数据线极性相反；电荷共享开关，所述电荷共享开关的控制端连接于第三扫描线，所述电荷共享开关的第一端连接于所述第一节点A，所述电荷共享开关的第二端连接于所述第二节点B，所述电荷共享开关的控制端能够响应第三扫描线的扫描信号，以使得第一节点A与所述第二节 点B连接。
本公开第二方面提供了一种像素驱动方法，用于驱动如像素电路，所述像素驱动方法包括：充电阶段，利用所述第一扫描线的扫描信号打开所述第一晶体管，利用所述第二扫描线的扫描信号打开所述第二晶体管，同时，利用所述第三扫描线的扫描信号关闭所述电荷共享开关；发光阶段，利用所述第一扫描线的扫描信号关闭所述第一晶体管，利用所述第二扫描线的扫描信号关闭所述第二晶体管，同时，利用所述第三扫描线的扫描信号关闭所述电荷共享开关；数据极性切换阶段，利用所述第三扫描线的扫描信号打开所述电荷共享开关，同时，利用所述第一扫描线的扫描信号关闭所述第一晶体管，利用所述第二扫描线的扫描信号关闭所述第二晶体管。
本公开第三方面提供了一种显示面板，包括像素单元和上述任一项所述的像素驱动电路，所述像素驱动电路与所述像素单元一一对应。
本公开像素驱动电路、像素驱动方法及显示面板，可用于省电。该像素驱动电路包括分别与极性相反的第一数据线和第二数据线连接的第一像素电路和第二像素电路，以及设于第一像素电路和第二像素电路中的电荷共享开关；通过该电荷共享开关对第一数据线和第二数据线的电压进行中和，进而使得第一数据线和第二数据线的电压回复到中间值，等到电压反转时，第一数据线和第二数据线的电压起点就变成了该中间值，从而更加容易达到目标电压，进而达到省电的目的。
本公开的其他特性和优点将通过下面的详细描述变得显然，或部分地通过本公开的实践而习得。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本申请的实施例，并于说明书一起用于解释本申请的原理。
为了使本公开的内容更容易被清楚的理解，下面根据本公开的具体实施例并结合附图，对本公开作进一步详细的说明，其中：
图1示出了本公开实施例一提供的所述像素驱动电路的示意图。
图2示出了本公开实施例一提供的所述第一像素电路和第二像素电路设有反向器的结构示意图。
图3示出了本公开实施例一提供的数据线极性中数据电压变化的过程。
图4示出了本公开实施例一提供的不同帧数下数据线的极性变化。
图5示出了本公开实施例二提供的像素驱动方法流程示意图。
图6示出了本公开实施例二提供的增设反向器的像素驱动方法流程示意图。
图7示出了本公开实施例二提供的各扫描线在不同时序的电位情况。
图8示出了本公开实施例二提供的充电阶段的结构示意图。
图9示出了本公开实施例二提供的发光阶段的结构示意图。
图10示出了本公开实施例二提供的数据极性切换阶段的结构示意图。
图11示出了本公开实施例二提供地增设有反向器像素电路在充电阶段的结构示意图。
图12示出了本公开实施例二提供地增设有反向器像素电路在发光阶段的结构示意图。
图13示出了本公开实施例二提供地增设有反向器像素电路在数据极性切换阶段的结构示意图。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的范例；相反，提供这些实施方式使得本公开将更加全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。
在本公开中，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
在本公开中，除非另有明确的规定和限定，术语“装配”、“连接”等术语应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或成一体；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通或两个元件的相互作用关系。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本公开中的具体含义。
此外，所描述的特征、结构或特性可以以任何合适的方式结合在一个或更多实施例中。在下面的描述中，提供许多具体细节从而给出对本公开的实施例的充分理解。 然而，本领域技术人员将意识到，可以实践本公开的技术方案而没有特定细节中的一个或更多，或者可以采用其它的方法、组元、装置、步骤等。在其它情况下，不详细示出或描述公知方法、装置、实现或者操作以避免模糊本公开的各方面。
实施例一
参见图1所示，本公开实施例提供了一种像素驱动电路，其包括第一像素电路1、第二像素电路2和电荷共享开关T7。
其中，参见图1所示，该第一像素电路1包括第一晶体管T1、第一驱动晶体管T2、第一电容C1和第一发光元件L1，第一晶体管T1的控制端与第一扫描线11连接，第一晶体管T1的第一端与第一数据线12连接，第一晶体管T1用于接收第一扫描线11的扫描信号(即：第一扫描信号Scan1)，以将第一数据线12的第一数据信号DATA1输入至第一电容C1；第一晶体管T1的第二端、第一驱动晶体管T2的控制端和第一电容C1的第一端连接于第一节点A，也即将第一数据信号DATA1对应的电压值传输至第一节点A处；第一驱动晶体管T2的第一端与第一电源信号端VDD连接，第一驱动晶体管T2的第二端与第一发光元件L1的第一端连接，第一发光元件L1和第一电容C1的第二端与第二电源信号端VSS1连接。
参见图1所示，第二像素电路2，包括第二晶体管T3、第二驱动晶体管T4、第二电容C2和第二发光元件L2，第二晶体管T3的控制端与第二扫描线21连接，第二晶体管T3的第一端与第二数据线22连接，第二晶体管T3用于接收第二扫描线21的扫描信号(即：第二扫描信号Scan2)，以将第二数据线22的第二数据信号DATA2输入至第二电容C2；第二晶体管T3的第二端、第二驱动晶体管T4的控制端和第二电容C2的第一端连接于第二节点B，也即将第二数据信号DATA2对应的电压值传输至第二节点B处，第二驱动晶体管T4的第一端与第一电源信号端VDD连接，第二驱动晶体管T4的第二端与第二发光元件L2的第一端连接，第二发光元件L2和第二电容C2的第二端与第三电源信号端VSS2连接，且第二数据线22与第一数据线12极性相反。
参见图1所示，电荷共享开关T7的控制端连接于第三扫描线3，电荷共享开关T7的第一端连接于第一节点A，电荷共享开关T7的第二端连接于第二节点B，电荷共享开关T7的控制端能够响应第三扫描线3的扫描信号(即：第三扫描信号Scan3)，以使得第一节点A与第二节点B连接。
需要说明的是，第一数据线12与第二数据线22的极性相反指的是第一数据线 12提供的第一数据信号DATA1对应的电压值与第二数据线22提供的第二数据信号DATA2对应的电压值互为正负值；例如，第一数据信号DATA1对应的电压值为正值，第二数据信号DATA2对应的电压值为负值；第一数据信号DATA1对应的电压值为负值，第二数据信号DATA2对应的电压值为正值。
具体说明，电荷共享开关T7的控制端用于接收第三扫描线3所发出的第三扫描信号Scan3，将电荷共享开关T7进行导通，将第一节点A和第二节点B连接，以使其第一节点A处的电压值和第二节点B处的电压值变为其两者之间的平均值V 平均；当需要对第一数据线12和第二数据线22进行极性反转时，即从平均值V 平均进行变化，从而更加容易达到第一数据线12和第二数据线22的目标电压V 目标，而无需从当前电压V 当前变为目标电压V 目标，节省了反转电压，进而达到省电的目的。
举例而言，参见图1、图3和图4所示，在N帧时，第一数据信号DATA1对应的电压值为正值，第二数据信号DATA2对应的电压值为负值时，通过电荷共享开关T7对第一节点A和第二节点B进行连通，以使其第一节点A处的电压值V1和第二节点B处的电压值变为其两者之间的平均值V 平均；在空白区域进行极性反转时，第一数据信号DATA1对应的电压值从该平均值V 平均变为负值，第二数据信号DATA2对应的电压值从该平均值V 平均变为正压值，然后进入第N+1帧；其中，N为大于1的整数；相较于第一数据信号DATA1对应的电压值从正值变为负值，以及第二数据信号DATA2对应的电压值从负值变为正值所消耗的反转电压更少，进而达到省电的目的。
此外，参见图2所示，第一像素电路还包括第三晶体管T5、第三电容C3和第一反向器13，第三晶体管T5的控制端与第一扫描线11连接，第三晶体管T5的第一端与第一电源信号端VDD连接，第三晶体管T5的第二端、第一驱动晶体管T2的第一端和第三电容C3的第一端连接于第三节点C，第三电容C3的第二端与第四电源信号端VSS3连接；第一反向器13的输入端与第一扫描线11的一端相连，所述第一反向器13的输出端与第三晶体管T5的控制端相连。
第二像素电路2还包括第四晶体管T6、第四电容C4和第二反向器23，第四晶体管T6的控制端与第二扫描线21连接，第四晶体管T6的第一端与第一电源信号端VDD连接，第四晶体管T6的第二端、第二驱动晶体管T4的第一端和第四电容C4的第一端连接于第四节点D，第四电容C4的第二端与第五电源信号端VSS4连接，第二反向器23的输入端与第二扫描线21的一端相连，所述第二反向器23的输出端 与第四晶体管T6的控制端相连。
其中，第一反向器13和第二反向器23可以调整第一扫描线11和第二扫描线21所输入的扫描信号，也即，可以调整第一扫描信号Scan1和第二扫描信号Scan2的电平高低；举例而言，当第一扫描信号Scan1为低电平，经过第一反向器13之后将第一扫描信号Scan1转换为高电平；当第一扫描信号Scan1为高电平，经过第一反向器13之后将第一扫描信号Scan1转换为低电平。也即第一扫描信号Scan1经第一反向器13控制第三晶体管T5导通；第二扫描信号Scan2经第二反向器23控制第四晶体管T6导通。
需要说明的是，在未进行数据极性切换时，第三晶体管T5和第四晶体管T6分别接收第一扫描信号Scan1和第二扫描信号Scan2的输入而导通，并将第一电源信号输入至第三电容C3和第四电容C4中储电；在进行数据极性切换的同时断开第一电源信号端VDD，第三晶体管T5和第四晶体管T6分别接收第一扫描信号Scan1和第二扫描信号Scan2，以控制第三晶体管T5和第四晶体管T6关闭，第三电容C3和第四电容分别向第三节点C和第四节点D放电，以补充第三晶体管T5和第四晶体管T6第二端的电压，以驱使第一驱动晶体管T2和第二驱动晶体管T4导通，使得第一发光元件L1和第二发光元件L2发光。通过第一反向器13、第二反向器23、第三电容C3和第四电容C4可达到第二次省电的作用，还可以降低第一电源信号端VDD的功耗，降低使用成本；此外还可对第一发光元件L1和第二发光元件L2进行一定的保护。
应当理解的是，第一晶体管T1、第二晶体管T3、第三晶体管T5、第四晶体管T6、电荷共享开关T7与第一驱动晶体管T2和第二驱动晶体管T4相同，均具有第一端、第二端和控制端。各晶体管的控制端对应为晶体管的栅极，第一端和第二端中的一者对应为晶体管的源极，另一者对应为晶体管的漏极。
示例地，本公开实施例的第一驱动晶体管T2、第二驱动晶体管T4、第一晶体管T1、第二晶体管T3、第三晶体管T5、第四晶体管T6和电荷共享开关T7可均为氧化物薄膜晶体管，即：各晶体管的有源层的材料可为氧化物，例如，可采用IGZO(Indium Gallium Zinc Oxide，铟锌氧化物)等金属氧化物材料，也可以采用a-Si(非晶硅)薄膜晶体管，具体可根据不同的实施方式进行设计。
举例而言，各晶体管可为底栅型，即：晶体管的栅极位于有源层的下方(靠近玻璃基板的一侧)，以能够适当减薄产品，但不限于此，各晶体管也可为顶栅型，视具 体情况而定。
此外，各晶体管可为增强型或耗尽型晶体管，本公开实施例对此不做具体限定。
示例地，像素驱动电路中所有晶体管可为N型薄膜晶体管，即：第一驱动晶体管T2、第二驱动晶体管T4、第一晶体管T1、第二晶体管T3、第三晶体管T5、第四晶体管T6和电荷共享开关T7可均为N型薄膜晶体管，则各个晶体管的驱动电压对应为高电平电压；前述第一电源信号端VDD所输入的第一电源信号可为直流高电平信号，第二电源信号端VSS1的第二电源信号、第三电源信号端VSS2的第三电源信号、第四电源信号端VSS3的第四电源信号和第五电源信号端VSS4的第五电源信号可为直流低电平信号。
应当理解的是，像素驱动电路中各晶体管不限于前述提到的N型薄膜晶体管，也可以均为P型薄膜晶体管，或者部分为N型薄膜晶体管，部分为P型薄膜晶体管。在晶体管为P型薄膜晶体管时，其驱动电压可对应为低电平电压。
示例地，第一发光元件L1可为电流驱动型发光元件L，由流经第一驱动晶体管T2的电流控制其进行发光；第二发光元件L2可为电流驱动型发光元件，由流经第二驱动晶体管T4的电流控制其进行发光；例如：第一发光元件L1和第二发光元件L2可为有机发光二极管(OLED)，也就是说，此像素驱动电路可应用于OLED显示装置。第一发光元件L1的第一端为OLED的阳极，第一发光元件L1的第二端为OLED的阴极；第二发光元件L2的第一端为OLED的阳极，第二发光元件L2的第二端为OLED的阴极；也即第一像素电路1中的有机发光二极管的阳极与第一驱动晶体管T2的第二端连接，第一像素电路1中的有机发光二极管的阴极与第二电源信号端VSS1连接；第二像素电路2中的有机发光二极管的阳极与第二驱动晶体管T4的第二端连接，第二像素电路2中的有机发光二极管的阴极与第三电源信号端VSS2连接。
需要说明的是，该第一像素电路1和第二像素电路2可以采用2T1C的结构，也可以采用4T1C或4T2C等结构，具体可根据不同的显示面板进行设计。
此外，该第一像素电路1和第二像素电路2可以位于同一列，也可位于同一行，其可根据不同的显示面板进行设计，在此不做具体限定。此外，相邻的像素驱动电路之间不进行电荷共享，也即两个像素电路为一组像素驱动电路进行电荷共享。
示例地，当第一像素电路1和第二像素电路2位于同一列时，该第一数据线12和第二数据线22可以位于第一像素电路1和第二像素电路2的同一侧，也可位于第一像素电路1和第二像素电路2的相对侧。
需要说明的是，显示面板包括显示区和非显示区，其中，电荷共享开关T7设于非显示区处，以避免电荷共享开关T7影响显示面板的显示效果。
进一步地，像素驱动电路的扫描方向可以从第1行至最后一行；举例而言，第一扫描信号Scan1由第N行扫描信号线提供，第二扫描信号Scan2由第N+1行扫描信号线提供；第三扫描信号Scan3由第N+2行扫描信号线提供。其中，应当理解的是，N为大于或等于1的正整数。通过利用三个相邻的扫描信号线分别对应提供第一至第三扫描信号Scan3，可简化电路结构设计，减少扫描信号的布线数量，从而可增加像素开口率。
工作原理：向第一电容C1和第二电容C2进行充电时，第一晶体管T1接收第一扫描线11的第一扫描信号Scan1而导通，第二晶体管T3接收第二扫描线21的第二扫描信号Scan2而导通，以将第一数据线12的第一数据信号DATA1和第二数据线22的第二数据信号DATA2分别输入第一节点A和第二节点B，对第一电容C1和第二电容C2进行充电，并使第一电容C1和第二电容C2充电至第一数据信号DATA1和第二数据信号DATA2对应的电压值，且此时流经第一驱动晶体管T2和第二驱动晶体管T4的电压值小于阈值电压，因此，第一发光元件L1和第二发光元件L2不发光；发光阶段，第一晶体管T1和第二晶体管T3分别接收第一扫描信号Scan1和第二扫描信号Scan2而关闭，第一电容C1和第二电容C2开始放电，以驱使第一发光元件L1和第二发光元件L2进行发光。数据极性切换空白(blanking)区域时，电荷共享开关T7接收第三扫描线3的第三扫描信号Scan3而导通，将第一节点A和第二节点B连通，使得第一电容C1存储的电荷和第二电容C2存储的电荷进行分享，进而将电压进行中和，使得第一节点A和第二节点B处的电压值处于平均值V 平均，使其反转时所需要的电压更少，进而达到省电的目的；此外，通过对第一数据线12和第二数据线22上的电压进行中和，还可以降低源极(source)线的功耗，更耐用。
应当理解的是，空白(blanking)区域是每个画面在显示过程中，会有一段空白而未实际显示的画面的时间。
基于此，本公开实施例的像素驱动电路采用在两个相邻的像素电路之间增设电荷共享开关T7，可以对极性相反的数据线上的电压进行中和，降低极性偏转时的启动电压，进而达到省电的作用；此外，在每个像素电路中增设反向器和电容，可以对发光元件进行更好地保护，而且还可以达到第二次省电的目的以及降低第一电源信号的功耗。
实施例二：
参见图5所示，本实施例二提供了一种像素驱动方法，用于驱动如实施例一的像素电路，像素驱动方法包括：
步骤S100、充电阶段t1，利用第一扫描线11的扫描信号打开第一晶体管T1，利用第二扫描线21的扫描信号打开第二晶体管T3，同时，利用第三扫描线3的扫描信号关闭电荷共享开关T7。
步骤S200、发光阶段t2，利用第一扫描线11的扫描信号关闭第一晶体管T1，利用第二扫描线21的扫描信号关闭第二晶体管T3，同时，利用第三扫描线3的扫描信号关闭电荷共享开关T7。
步骤S300a、数据极性切换阶段t3，利用第三扫描线3的扫描信号打开电荷共享开关T7，同时，利用第一扫描线11的扫描信号关闭第一晶体管T1，利用第二扫描线21的扫描信号关闭第二晶体管T3。
下面结合图7所示的像素驱动电路的工作时序图对图1或图2所示的像素驱动电路对应的像素驱动方法(即：工作过程)进行详细说明。
参见图7、图8和图11所示，在充电阶段t1：第一扫描信号Scan1为高电平，第二扫描信号Scan2为高电平，第三扫描信号Scan3为低电平；使得第一晶体管T1、第二晶体管T3打开，电荷共享开关T7关闭；在另一些实施例中，第一晶体管T1、第二晶体管T3和电荷共享开关T7为P型薄膜晶体管时，第一扫描信号Scan1和第二扫描信号Scan2为低电平，第三扫描信号Scan3为高电平。
在此阶段，由于第一扫描信号Scan1为高电平，第二扫描信号Scan2为高电平，第三扫描信号Scan3为低电平，也即该第一晶体管T1、第二晶体管T3打开，以将第一数据线12中的第一数据信号DATA1传输至第一电容C1的第一端和第二数据线22中的第二数据信号DATA2传输至第二电容C2的第一端，以向第一电容C1和第二电容C2充电至Vdata；且此时第一驱动晶体管T2和第二驱动晶体管T4的电压小于阈值电压，发光元件L不发光。并且，电荷共享开关T7未打开不进行电荷共享。
参见图7、图9和图12所示，在发光阶段t2，第一扫描信号Scan1为低电平，第二扫描信号Scan2为低电平，第三扫描信号Scan3为低电平；使得第一晶体管T1、第二晶体管T3和电荷共享开关T7关闭；在另一些实施例中，第一晶体管T1、第二晶体管T3和电荷共享开关T7为P型薄膜晶体管时，第一扫描信号Scan1和第二扫 描信号Scan2和第三扫描信号Scan3为高电平。
在此阶段，由于第一扫描信号Scan1、第二扫描信号Scan2和第三扫描信号Scan3均为低电平，也即该第一晶体管T1、第二晶体管T3和电荷共享开关T7均关闭，第一电容C1和第二电容C2放电，以驱动第一驱动晶体管T2和第二驱动晶体管T4导通，以使第一发光元件L1和第二发光元件L2发光。
参见图7、图10和图13所示，在数据极性切换阶段t3，第一扫描信号Scan1为低电平，第二扫描信号Scan2为低电平，第三扫描信号Scan3为高电平；使得第一晶体管T1和第二晶体管T3关闭，电荷共享开关T7打开；在另一些实施例中，第一晶体管T1、第二晶体管T3和电荷共享开关T7为P型薄膜晶体管时，第一扫描信号Scan1和第二扫描信号Scan2为高电平，第三扫描信号Scan3为低电平。
在此阶段，电荷共享开关T7接收第三扫描线3的第三扫描信号Scan3而导通，将第一节点A和第二节点B连通，使得第一电容C1存储的电荷和第二电容C2存储的电荷进行分享，进而将电压进行中和，使得第一节点A和第二节点B处的电压值处于平均值V 平均，使其反转时所需要的电压更少，进而达到省电的目的；此外，通过对第一数据线12和第二数据线22上的电压进行中和，还可以降低源极(source)线的功耗，更耐用。
此外，参见图11、图12和图13所示，该第一像素电路还包括第三晶体管T5、第三电容C3和第一反向器13，第三晶体管T5的控制端与第一扫描线11连接，第三晶体管T5的第一端与第一电源信号端VDD连接，第三晶体管T5的第二端、第一驱动晶体管T2的第一端和第三电容C3的第一端连接于第三节点C，第三电容C3的第二端与第四电源信号端VSS3连接；第一反向器13的一端与第一扫描线11的一端相连，所述第二反向器的输出端与第三晶体管T5的控制端相连；第二像素电路2还包括第四晶体管T6、第四电容C4第二反向器23，第四晶体管T6的控制端与第二扫描线21连接，第四晶体管T6的第一端与第一电源信号端VDD连接，第四晶体管T6的第二端、第二驱动晶体管T4的第一端和第四电容C4的第一端连接于第四节点D，第四电容C4的第二端与第五电源信号端VSS4连接，第二反向器23的一端与第二扫描线21的一端相连，所述第二反向器的输出端与第四晶体管T6的控制端相连。
其中，参见图6所示，在数据极性切换阶段还包括：通过断开第一电源信号端VDD，关闭第三晶体管T5和第四晶体管T6。也即，步骤S300b：数据极性切换阶段t3，利用第三扫描线3的扫描信号打开电荷共享开关T7，同时，利用第一扫描线11 的扫描信号关闭第一晶体管T1，利用第二扫描线21的扫描信号关闭第二晶体管T3；通过断开第一电源信号端VDD，关闭第三晶体管T5和第四晶体管T6。
参见图12所示，在未进行数据极性切换时，第三晶体管T5和第四晶体管T6分别受第一扫描信号Scan1和第二扫描信号Scan2的输入而导通，并将第一电源信号输入至第三电容C3和第四电容C4中储电；参见图13所示，在进行数据极性切换的同时断开第一电源信号端VDD，以控制第三晶体管T5和第四晶体管T6关闭，第三电容C3和第四电容C4分别向第三节点C和第四节点D放电，以补充第三晶体管T5和第四晶体管T6第二端的电压，以驱使第一驱动晶体管T2和第二驱动晶体管T4导通，使得第一发光元件L1和第二发光元件L2发光。通过第一反向器13、第二反向器23、第三电容C3和第四电容C4可达到第二次省电的作用，还可以降低第一电源信号端VDD的功耗，降低使用成本；此外还可对第一发光元件L1和第二发光元件L2进行一定的保护。
实施例三：
本实施例三提供了一种显示面板，其包括像素单元和实施例一中所提及的像素驱动电路，该像素驱动电路和像素单元一一对应。
具体地，该显示面板可为有机发光二极管(OLED)显示面板、电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
此外，该像素单元包括显示区和非显示区，为了保证显示面板的显示效果，该电荷共享开关T7位于非显示区。
在本说明书的描述中，参考术语“一些实施例”、“示例地”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特点包含于本公开的至少一个实施例或示例中。在本说明书中，对上述术语的示意性表述不必须针对的是相同的实施例或示例。而且，描述的具体特征、结构、材料或者特点可以在任一个或多个实施例或示例中以合适的方式结合。此外，在不相互矛盾的情况下，本领域的技术人员可以将本说明书中描述的不同实施例或示例以及不同实施例或示例的特征进行结合和组合。
尽管上面已经示出和描述了本公开的实施例，可以理解的是，上述实施例是示例性的，不能理解为对本公开的限制，本领域的普通技术人员在本公开的范围内可以对上述实施例进行变化、修改、替换和变型，故但凡依本公开的权利要求和说明书所做 的变化或修饰，皆应属于本公开专利涵盖的范围之内。
尽管上面已经示出和描述了本申请的实施例，可以理解的是，上述实施例是示例性的，不能理解为对本申请的限制，本领域的普通技术人员在本申请的范围内可以对上述实施例进行变化、修改、替换和变型，故但凡依本申请的权利要求和说明书所做的变化或修饰，皆应属于本申请专利涵盖的范围之内。

Claims (20)

  1. 一种像素驱动电路，包括：
    第一像素电路，包括第一晶体管、第一驱动晶体管、第一电容和第一发光元件，所述第一晶体管的控制端与第一扫描线连接，所述第一晶体管的第一端与第一数据线连接，所述第一晶体管的第二端、所述第一驱动晶体管的控制端和所述第一电容的第一端连接于第一节点A，所述第一驱动晶体管的第一端与第一电源信号端连接，所述第一驱动晶体管的第二端与所述第一发光元件的第一端连接，所述第一发光元件和所述第一电容的第二端均与第二电源信号端连接；
    第二像素电路，包括第二晶体管、第二驱动晶体管、第二电容和第二发光元件，所述第二晶体管的控制端与第二扫描线连接，所述第二晶体管的第一端与第二数据线连接，所述第二晶体管的第二端、所述第二驱动晶体管的控制端和所述第二电容的第一端连接于第二节点B，所述第二驱动晶体管的第一端与第一电源信号端连接，所述第二驱动晶体管的第二端与所述第二发光元件的第一端连接，所述第二发光元件和所述第二电容的第二端均与第三电源信号端连接，且所述第二数据线与所述第一数据线极性相反；
    电荷共享开关，所述电荷共享开关的控制端连接于第三扫描线，所述电荷共享开关的第一端连接于所述第一节点A，所述电荷共享开关的第二端连接于所述第二节点B，所述电荷共享开关的控制端能够响应第三扫描线的扫描信号，以使得第一节点A与所述第二节点B连接。
  2. 根据权利要求1所述的像素驱动电路，其中，
    所述第一像素电路还包括第三晶体管、第三电容和第一反向器，所述第三晶体管的控制端与所述第一扫描线连接，所述第三晶体管的第一端与所述第一电源信号端连接，所述第三晶体管的第二端、所述第一驱动晶体管的第一端和所述第三电容的第一端连接于第三节点C，所述第三电容的第二端与第四电源信号端连接；所述第一反向器的输入端与所述第一扫描线的一端相连，所述第一反向器的输出端与所述第三晶体管的控制端相连；
    所述第二像素电路还包括第四晶体管、第四电容和第二反向器，所述第四晶体管的控制端与所述第二扫描线连接，所述第四晶体管的第一端与所述第一电源信号端连接，所述第四晶体管的第二端、所述第二驱动晶体管的第一端和所述第四电容的第一端连接于第四节点D，所述第四电容的第二端与第五电源信号端连接，所述第二反向器的输入端与所述第二扫描线的一端相连，所述第二反向器的输出端与所述第四晶体管的控制端相连。
  3. 根据权利要求1所述的像素驱动电路，其中，所述像素驱动电路的扫描方向为从第一行至最后一行；其中，
    第一扫描信号由第N行扫描线提供，第二扫描信号由第N+1行扫描线提供，第 三扫描信号由第N+2行扫描线提供，其中，N为大于或等于1的正整数。
  4. 根据权利要求1所述的像素驱动电路，其中，
    所述第一发光元件和所述第二发光元件均为有机发光二极管，所述第一像素电路中的有机发光二极管的阳极与第一驱动晶体管的第二端连接，所述第一像素电路中的有机发光二极管的阴极与第二电源信号端连接；
    所述第二像素电路中的有机发光二极管的阳极与第四驱动晶体管的第二端连接，所述第二像素电路中的有机发光二极管的阴极与第三电源信号端连接。
  5. 根据权利要求1所述的像素驱动电路，其中，
    所述第一像素电路和所述第二像素电路在列方向依次设置。
  6. 根据权利要求1所述的像素驱动电路，其中，所述第一像素电路和所述第二像素电路位于同一列，或位于同一行。
  7. 根据权利要求6所述的像素驱动电路，其中，当所述第一像素电路和所述第二像素电路位于同一列时，所述第一数据线和所述第二数据线位于所述第一像素电路和所述第二像素电路的同一侧，或位于所述第一像素电路和所述第二像素电路的相对侧。
  8. 根据权利要求1所述的像素驱动电路，其中，各所述晶体管可为底栅型。
  9. 一种像素驱动方法，用于像素驱动电路，其中，所述像素驱动方法包括：
    充电阶段，利用第一扫描线的扫描信号打开第一晶体管，利用第二扫描线的扫描信号打开第二晶体管，同时，利用第三扫描线的扫描信号关闭电荷共享开关；
    发光阶段，利用所述第一扫描线的扫描信号关闭所述第一晶体管，利用所述第二扫描线的扫描信号关闭所述第二晶体管，同时，利用所述第三扫描线的扫描信号关闭所述电荷共享开关；
    数据极性切换阶段，利用所述第三扫描线的扫描信号打开所述电荷共享开关，同时，利用所述第一扫描线的扫描信号关闭所述第一晶体管，利用所述第二扫描线的扫描信号关闭所述第二晶体管。
  10. 根据权利要求9所述的像素驱动方法，其中，所述像素驱动电路包括：
    第一像素电路，包括第一驱动晶体管、第一电容、第一发光元件和所述第一晶体管，所述第一晶体管的控制端与所述第一扫描线连接，所述第一晶体管的第一端与第一数据线连接，所述第一晶体管的第二端、所述第一驱动晶体管的控制端和所述第一电容的第一端连接于第一节点A，所述第一驱动晶体管的第一端与第一电源信号端连接，所述第一驱动晶体管的第二端与所述第一发光元件的第一端连接，所述第一发光元件和所述第一电容的第二端均与第二电源信号端连接；
    第二像素电路，包括第二驱动晶体管、第二电容、第二发光元件和所述第二晶体管，所述第二晶体管的控制端与所述第二扫描线连接，所述第二晶体管的第一端与第 二数据线连接，所述第二晶体管的第二端、所述第二驱动晶体管的控制端和所述第二电容的第一端连接于第二节点B，所述第二驱动晶体管的第一端与第一电源信号端连接，所述第二驱动晶体管的第二端与所述第二发光元件的第一端连接，所述第二发光元件和所述第二电容的第二端均与第三电源信号端连接，且所述第二数据线与所述第一数据线极性相反；
    所述电荷共享开关，所述电荷共享开关的控制端连接于第三扫描线，所述电荷共享开关的第一端连接于所述第一节点A，所述电荷共享开关的第二端连接于所述第二节点B，所述电荷共享开关的控制端能够响应第三扫描线的扫描信号，以使得第一节点A与所述第二节点B连接。
  11. 根据权利要求10所述的像素驱动方法，其中，
    所述第一像素电路还包括第三晶体管、第三电容和第一反向器，所述第三晶体管的控制端与所述第一扫描线连接，所述第三晶体管的第一端与所述第一电源信号端连接，所述第三晶体管的第二端、所述第一驱动晶体管的第一端和所述第三电容的第一端连接于第三节点C，所述第三电容的第二端与第四电源信号端连接；所述第一反向器的一端与所述第一扫描线的一端相连，所述第一反向器的输出端与所述第三晶体管的控制端相连；
    所述第二像素电路还包括第四晶体管、第四电容和第二反向器，所述第四晶体管的控制端与所述第二扫描线连接，所述第四晶体管的第一端与所述第一电源信号端连接，所述第四晶体管的第二端、所述第二驱动晶体管的第一端和所述第四电容的第一端连接于第四节点D，所述第四电容的第二端与第五电源信号端连接，所述第二反向器的输入端与所述第二扫描线的一端相连，所述第二反向器的输出端与所述第四晶体管的控制端相连；其中，在所述数据极性切换阶段还包括：
    通过断开第一电源信号端，关闭所述第三晶体管和所述第四晶体管。
  12. 根据权利要求10所述的像素驱动方法，其中，
    充电阶段，所述第一扫描线的扫描信号和所述第二扫描线的扫描信号为高电平，所述第三扫描线的扫描信号为低电平；
    发光阶段，所述第一扫描线的扫描信号和所述第二扫描线的扫描信号为低电平，所述第三扫描线的扫描信号为低电平；
    数据极性切换阶段，所述第一扫描线的扫描信号和所述第二扫描线的扫描信号为低电平，所述第三扫描线的扫描信号为高电平。
  13. 一种显示面板，包括像素单元和像素驱动电路，所述像素驱动电路与所述像素单元一一对应，所述像素驱动电路包括：
    第一像素电路，包括第一晶体管、第一驱动晶体管、第一电容和第一发光元件，所述第一晶体管的控制端与第一扫描线连接，所述第一晶体管的第一端与第一数据线 连接，所述第一晶体管的第二端、所述第一驱动晶体管的控制端和所述第一电容的第一端连接于第一节点A，所述第一驱动晶体管的第一端与第一电源信号端连接，所述第一驱动晶体管的第二端与所述第一发光元件的第一端连接，所述第一发光元件和所述第一电容的第二端均与第二电源信号端连接；
    第二像素电路，包括第二晶体管、第二驱动晶体管、第二电容和第二发光元件，所述第二晶体管的控制端与第二扫描线连接，所述第二晶体管的第一端与第二数据线连接，所述第二晶体管的第二端、所述第二驱动晶体管的控制端和所述第二电容的第一端连接于第二节点B，所述第二驱动晶体管的第一端与第一电源信号端连接，所述第二驱动晶体管的第二端与所述第二发光元件的第一端连接，所述第二发光元件和所述第二电容的第二端均与第三电源信号端连接，且所述第二数据线与所述第一数据线极性相反；
    电荷共享开关，所述电荷共享开关的控制端连接于第三扫描线，所述电荷共享开关的第一端连接于所述第一节点A，所述电荷共享开关的第二端连接于所述第二节点B，所述电荷共享开关的控制端能够响应第三扫描线的扫描信号，以使得第一节点A与所述第二节点B连接。
  14. 根据权利要求13所述的显示面板，其中，
    所述像素单元包括显示区和非显示区，所述电荷共享开关设于所述非显示区。
  15. 根据权利要求13所述的显示面板，其中，
    所述第一像素电路还包括第三晶体管、第三电容和第一反向器，所述第三晶体管的控制端与所述第一扫描线连接，所述第三晶体管的第一端与所述第一电源信号端连接，所述第三晶体管的第二端、所述第一驱动晶体管的第一端和所述第三电容的第一端连接于第三节点C，所述第三电容的第二端与第四电源信号端连接；所述第一反向器的输入端与所述第一扫描线的一端相连，所述第一反向器的输出端与所述第三晶体管的控制端相连；
    所述第二像素电路还包括第四晶体管、第四电容和第二反向器，所述第四晶体管的控制端与所述第二扫描线连接，所述第四晶体管的第一端与所述第一电源信号端连接，所述第四晶体管的第二端、所述第二驱动晶体管的第一端和所述第四电容的第一端连接于第四节点D，所述第四电容的第二端与第五电源信号端连接，所述第二反向器的输入端与所述第二扫描线的一端相连，所述第二反向器的输出端与所述第四晶体管的控制端相连。
  16. 根据权利要求13所述的显示面板，其中，所述像素驱动电路的扫描方向为从第一行至最后一行；其中，
    第一扫描信号由第N行扫描线提供，第二扫描信号由第N+1行扫描线提供，第三扫描信号由第N+2行扫描线提供，其中，N为大于或等于1的正整数。
  17. 根据权利要求13所述的显示面板，其中，
    所述第一发光元件和所述第二发光元件均为有机发光二极管，所述第一像素电路中的有机发光二极管的阳极与第一驱动晶体管的第二端连接，所述第一像素电路中的有机发光二极管的阴极与第二电源信号端连接；
    所述第二像素电路中的有机发光二极管的阳极与第四驱动晶体管的第二端连接，所述第二像素电路中的有机发光二极管的阴极与第三电源信号端连接。
  18. 根据权利要求13所述的显示面板，其中，
    所述第一像素电路和所述第二像素电路在列方向依次设置。
  19. 根据权利要求13所述的显示面板，其中，所述第一像素电路和所述第二像素电路位于同一列，或位于同一行。
  20. 根据权利要求19所述的显示面板，其中，当所述第一像素电路和所述第二像素电路位于同一列时，所述第一数据线和所述第二数据线位于所述第一像素电路和所述第二像素电路的同一侧，或位于所述第一像素电路和所述第二像素电路的相对侧。
PCT/CN2022/140911 2022-06-08 2022-12-22 像素驱动电路、像素驱动方法及显示面板 Ceased WO2023236502A1 (zh)

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