WO2023230873A1 - 显示基板及显示装置 - Google Patents

显示基板及显示装置 Download PDF

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Publication number
WO2023230873A1
WO2023230873A1 PCT/CN2022/096339 CN2022096339W WO2023230873A1 WO 2023230873 A1 WO2023230873 A1 WO 2023230873A1 CN 2022096339 W CN2022096339 W CN 2022096339W WO 2023230873 A1 WO2023230873 A1 WO 2023230873A1
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WO
WIPO (PCT)
Prior art keywords
power supply
sub
pixel
electrode
main body
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PCT/CN2022/096339
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English (en)
French (fr)
Inventor
黄耀
王彬艳
李孟
承天一
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2022/096339 priority Critical patent/WO2023230873A1/zh
Priority to CN202280001612.5A priority patent/CN117501343A/zh
Publication of WO2023230873A1 publication Critical patent/WO2023230873A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]

Definitions

  • At least one embodiment of the present disclosure relates to a display substrate and a display device.
  • the light-emitting element is at least partially located in the light-emitting area, the first electrode of the light-emitting element includes a body electrode overlapping with the light-emitting area; a plurality of power signal lines, at least part of the plurality of power signal lines extend along the first direction and along the second direction.
  • the maximum size, the maximum size of the first main body part in the first power supply part is greater than the maximum size of the second main body part, and the main body electrode of the first sub-pixel is farthest in the second direction.
  • the connection between the two endpoints is an endpoint connection, and in the third direction, the endpoint connection overlaps with the first main body part.
  • the plurality of power signal lines include a first power signal line and a second power signal line, and the first power signal line and the second power signal line are in the second direction.
  • the maximum dimensions on are respectively a first dimension and a second dimension, and the second dimension is smaller than the first dimension.
  • the extension direction of the symmetrical center line of the part of the first type power supply part except the first protruding part is consistent with the second symmetrical center of the body electrode of the first type sub-pixel.
  • the lines extend in directions that intersect.
  • the plurality of first sub-pixels further includes at least one second-type sub-pixel
  • the first power supply portion overlapping with the body electrode of the second-type sub-pixel is a second type power supply part
  • the second type power supply part includes a third symmetry center line extending along the first direction
  • the body electrode of the second type sub-pixel includes a fourth symmetry center line extending along the first direction. center line, the third symmetrical center line of the second type power supply part in the same column of the power supply signal line and the fourth symmetry center line of the second type sub-pixel overlapping with the second type power supply part.
  • the center line of symmetry lies in the same plane perpendicular to the base substrate.
  • the first body portion of the second type power supply portion includes a second protruding portion and a third protruding portion, and the second protruding portion and the third protruding portion are opposite to each other.
  • the main body electrode of the second type sub-pixel includes an opposite first corner and a second corner, and an opposite third corner and a fourth corner
  • the second The orthographic projection of the protruding portion on the base substrate at least partially overlaps the orthographic projection of one of the first corner portion and the second corner portion on the base substrate
  • the third protrusion An orthographic projection of the first corner portion on the base substrate at least partially overlaps an orthographic projection of the other of the first corner portion and the second corner portion on the base substrate.
  • the maximum size of the first main body part of the second type power supply part is larger than the maximum size of the first main body part of the first type power supply part, so
  • the ratio of the maximum size of the second main body part of the first type power supply part to the maximum size of the second main body part of the second type power supply part is 0.9 ⁇ 1.1.
  • the maximum dimension of the first main body portion of the second type power supply portion in the second direction is 1.1-2 times the maximum size.
  • each of the plurality of adjacent power signal lines includes a plurality of power supply parts arranged along the first direction, and a power supply part is disposed between two adjacent power supply parts.
  • the first connecting portion is electrically connected to two adjacent power supply portions.
  • the plurality of power supply portions include the first power supply portion.
  • the maximum size of the power supply portion in the second direction is equal to the first power supply portion.
  • the ratio of the maximum dimensions of the connecting portion in the second direction is 1.5-5.
  • the at least part of the sub-pixels further includes a plurality of second sub-pixels, and along the third direction, the at least one power supply signal line includes at least one connection with the plurality of second sub-pixels.
  • the sixth symmetrical center line extending in the direction, the fifth symmetrical center line of the second power supply part in the same column of the power supply signal line and all the second sub-pixels overlapping with the second power supply part
  • the sixth center line of symmetry is located in the same plane perpendicular to the base substrate.
  • the maximum size of the second power supply part is smaller than the maximum size of the first main body part of the first power supply part, and the second power supply part
  • the ratio of the maximum size of the first power supply section to the maximum size of the second main body section of the first power supply section is 0.9 to 1.1.
  • the display substrate further includes: a plurality of second connection parts, which are arranged on the same layer as at least part of the plurality of power signal lines, and each second connection part includes a first connection piece and a second connection part.
  • the plurality of second connection portions are arranged in an array along the first direction and the second direction to form a plurality of second connection portion rows and a plurality of second connection portion columns, and the power signal line includes a plurality of second connection portions along the first direction and the second direction.
  • a first connection portion electrically connected to the two adjacent power supply units is provided between two adjacent power supply units, and all the power supply signal lines included in the plurality of power supply units are
  • the power supply parts are arranged in an array along the first direction and the second direction to form a plurality of power supply part rows and a plurality of power supply part columns, and the plurality of second connection part rows and the plurality of power supply part rows are They are arranged alternately in the first direction, and two adjacent second connection portions in the same row of second connection portions are distributed on both sides of the data line.
  • the first connection member is electrically connected to the connection electrode of the first sub-pixel or the connection electrode of the second sub-pixel, and the second connection member is electrically connected to the third sub-pixel.
  • the connection electrodes of the pixels are electrically connected.
  • the first connecting part includes at least one digging part, and the area of the digging part is 1/4-1/3 of the area of the first connecting part.
  • An embodiment of the present disclosure provides a display device, including any of the above display substrates.
  • FIG. 1B is a schematic diagram of a partial cross-sectional structure of another display substrate.
  • FIG. 2A is a schematic diagram showing the relationship between pixel arrangement and conductive layer overlap in a display substrate.
  • FIG. 2B is a schematic diagram illustrating the relationship between pixel arrangement and conductive layer overlap in another display substrate.
  • FIG. 3 is a schematic diagram of a pixel arrangement structure in a display substrate according to an embodiment of the present disclosure.
  • Figure 4 is a partial cross-sectional structural diagram taken along line AA' shown in Figure 3.
  • FIG. 5 is a schematic diagram of a stacked structure of a second conductive layer and a first electrode of a light-emitting element in a display substrate according to an embodiment of the present disclosure.
  • FIG. 6 is a schematic diagram of a partial structure of a second conductive layer in a display substrate according to an embodiment of the present disclosure.
  • FIG. 7 is a partial structural diagram of a first electrode of a light-emitting element in a display substrate according to an embodiment of the present disclosure.
  • FIG. 8 is an equivalent diagram of a pixel circuit provided according to an embodiment of the present disclosure.
  • FIG. 9 is a schematic diagram of the stacked structure of the light shielding layer, the active semiconductor pattern, and the first connection layer in the pixel circuit according to an embodiment of the present disclosure.
  • FIG. 10 is a schematic diagram of a stacked structure of a light shielding layer, an active semiconductor pattern, a first connection layer, a second connection layer, a semiconductor layer and a third connection layer in a pixel circuit according to an embodiment of the present disclosure.
  • FIG. 11 is a partial structural diagram of a first conductive layer according to an embodiment of the present disclosure.
  • FIG. 12 is a schematic diagram of a stacked structure of a light shielding layer, an active semiconductor pattern, a first connection layer, a second connection layer, a semiconductor layer, a third connection layer and a first conductive layer in a pixel circuit according to an embodiment of the present disclosure.
  • FIG. 13 is a schematic diagram of a stacked structure of a first conductive layer and a second conductive layer according to an embodiment of the present disclosure.
  • Characteristics such as “perpendicular”, “parallel” and “identical” used in the embodiments of the present disclosure include strictly “perpendicular”, “parallel”, “identical” and other characteristics, as well as “approximately perpendicular”, “approximately parallel”, “Substantially the same,” etc., including certain errors, means what is acceptable for a particular value as determined by one of ordinary skill in the art, taking into account the errors in the measurement and associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). within the deviation range.
  • "Center” in embodiments of the present disclosure may include a location located strictly at the geometric center as well as a location located approximately at the center within a small area around the geometric center. For example, "approximately” can mean within one or more standard deviations, or within 10% or 5% of the stated value.
  • the performance specifications of organic light-emitting diode display products can include power consumption, brightness, color shift, etc.
  • Factors affecting color shift caused by the backplane included in organic light-emitting diode display products may include the flatness of the anode. Optimizing the flatness of the anode in the light-emitting element can prevent the light emitted from the light-emitting element from deflecting, thereby reducing color shift and other phenomena in display products.
  • FIG. 1A is a schematic diagram of a partial cross-sectional structure of a display substrate.
  • the display substrate includes a film layer 91 , which includes a base substrate, an active semiconductor layer located on the base substrate, and at least one connection layer located on the side of the active semiconductor layer away from the base substrate.
  • the display substrate also includes a conductive layer 11 located on the film layer 91.
  • the conductive layer 11 may include data lines, power signal lines, and other wiring lines.
  • the display substrate also includes a flat layer 12 located on the side of the conductive layer 11 away from the film layer 91, an anode 13 located on the side of the flat layer 12 away from the conductive layer 11, and a pixel defining layer 14 located on the side of the anode 13 away from the flat layer 12.
  • the pixel defining layer 14 includes a plurality of openings 15 - 17 for defining light emitting areas of sub-pixels. A plurality of openings 15-17 expose part of the anode 13. When a subsequent organic light-emitting layer is formed in the openings 15-17 of the pixel defining layer 14, the organic light-emitting layer contacts the anode 13, so that this part can drive the organic light-emitting layer to emit light. .
  • the arrangement of the conductive layer 11 may have a great impact on the light extraction effect of the light-emitting element. For example, it may destroy the flatness of the anode in the light-emitting element, thereby causing color shift of the light-emitting element.
  • the thickness of the conductive layer 11 is relatively large, for example, the thickness may be 0.6-0.9 ⁇ m, which will cause the surface of the flat layer 12 located on the conductive layer 11 facing the anode 13 to be uneven.
  • the thickness may be 0.6-0.9 ⁇ m, which will cause the surface of the flat layer 12 located on the conductive layer 11 facing the anode 13 to be uneven.
  • the distance is h1
  • the distance between the surface of the flat layer 12 away from the film layer 91 directly above the area where the conductive layer 11 is not provided and the surface of the film layer 91 away from the flat layer 12 is h2, h1>h2.
  • a conductive layer 11 is provided directly below part of the flat layer 12 , and no conductive layer 11 is provided directly below another part. Therefore, the flat layer 12 in the opening 16 faces the anode 13 The surface is uneven, causing the surface of the anode 13 located on the flat layer 12 to be uneven as well.
  • the distance between the surface of the anode 13 located directly above the conductive layer 11 away from the film layer 91 and the surface of the film layer 91 away from the anode 13 is h3, and the position of the conductive layer 11 is not set.
  • the distance between the surface of the anode 13 away from the film layer 91 and the surface of the film layer 91 away from the anode 13 is h4, h3>h4.
  • the anode 13 in the opening 16 is "tilted".
  • the anode 13 in the opening 15 will also be “tilted”, and according to the difference in the position of the conductive layer 11, the "tilt direction" of the anode 13 in the opening 15 is different from the "tilt direction” of the anode 13 in the opening 16. , resulting in inconsistent intensities of the sub-pixels corresponding to the openings 15 and 16 emitting light in different directions.
  • the light intensity emitted by the sub-pixel light-emitting area defined by the opening 15 and the opening 16 to the left and right sides is inconsistent.
  • the sub-pixel light-emitting area defined by the opening 17 emits light in different directions with the same intensity. .
  • the anode 13 in the opening 15 is “tilted” to the left
  • the anode 13 in the opening 16 is “tilted” to the right
  • the anode 13 in the opening 17 is “tilted” to the right.
  • the anode 13 is not tilted. Therefore, the "tilt" directions of the anode 13 of sub-pixels of different colors are different, resulting in a mismatch in the intensity of light emitted by the light-emitting areas of the three sub-pixels to the left and right sides.
  • a display device using such a display substrate will suffer from a large visual angle deviation. When viewed by the human eye, a color deviation phenomenon will appear, such that one side becomes red and the other side becomes cyan.
  • FIG. 1B is a schematic diagram of a partial cross-sectional structure of another display substrate.
  • the display substrate shown in FIG. 1B includes the film layer 91 shown in FIG. 1A , the conductive layer 11 , the flat layer 12 , the anode 13 and the pixel defining layer 14 .
  • the flat layer 12 in the display substrate includes a via hole 18 so that the anode 13 can be electrically connected to the conductive layer 11 .
  • the pixel defining layer 14 includes an opening 19 to expose a portion of the anode 13. When a subsequent organic light-emitting layer is formed in the opening 19, the organic light-emitting layer contacts the anode 13 to form a light-emitting area.
  • the via hole 18 is located outside the light-emitting area. Since the anode 13 located around the via hole 18 is tilted, a certain distance should be set between the light-emitting area and the via hole 18 to ensure the flatness of the anode 13 in the light-emitting area. This prevents color shift on the display substrate.
  • the positional relationship between the conductive layer 11 and the anode 13 and the positional relationship between the via hole 18 and the anode 13 provided in the flat layer 12 will affect the flatness of the anode 13 in the light-emitting area, resulting in the display substrate being prone to discoloration. partial phenomenon.
  • Figure 2A is a schematic diagram of the overlapping relationship between pixel arrangement and conductive layer in a display substrate
  • Figure 2B is a schematic diagram of the overlapping relationship between pixel arrangement and conductive layer in another display substrate
  • Figure 2C is a schematic diagram of the overlapping relationship between pixel arrangement and conductive layer in a display substrate
  • FIG. 2A and FIG. 2B show the matching relationship between the anode of the light-emitting element in the pixel circuit and the conductive layer connected thereto.
  • the conductive layer includes a plurality of conductive components, and in a direction perpendicular to the base substrate of the display substrate, the anode of the light-emitting element at least partially overlaps the conductive components in the conductive layer.
  • the display substrate includes a plurality of sub-pixels, such as a blue sub-pixel 01 configured to emit blue light, a red sub-pixel 02 configured to emit red light, and a green sub-pixel 03 configured to emit green light, wherein
  • the green sub-pixel 03 that emits green light includes a first green sub-pixel 031 and a second green sub-pixel 032.
  • the light-emitting element of each sub-pixel includes a light-emitting area.
  • the light-emitting area may be defined according to a plurality of openings in the pixel defining layer.
  • the light-emitting area corresponding to each sub-pixel may refer to the range shown by the dotted line.
  • its light-emitting area includes an overlapping area 0110 and a non-overlapping area 0111, and the area of the non-overlapping area 0111 is larger than the area of the overlapping area 0110.
  • the distance between the surface of the film layer (not shown in the figure) of the anode located directly above the conductive layer in the overlapping area 0110 away from the base substrate and the surface of the base substrate away from the anode corresponds to h3, not In the overlapping area 0111, the distance between the surface of the film layer of the anode located directly above the conductive layer away from the substrate and the surface of the substrate film layer away from the anode corresponds to h4, h3>h4.
  • the anode 13 in the light-emitting area of the blue sub-pixel 01 will be "tilted".
  • the distribution of the non-overlapping area 0111 has no symmetry relative to the overlapping area 0110.
  • the anode in the light-emitting area when the non-overlapping areas in the light-emitting area are symmetrically distributed relative to the overlapping area, the anode in the light-emitting area will be "symmetrically tilted", that is, in the light-emitting area, due to the non-overlapping area, The resulting light tilt directions are symmetrical in the overlapping and non-overlapping areas.
  • the non-overlapping area is symmetrically distributed relative to the overlapping area.
  • the color shift of pixels will be weakened to a certain extent.
  • the display substrate includes a plurality of sub-pixels, such as a blue sub-pixel 04 configured to emit blue light, a red sub-pixel 05 configured to emit red light, and a green sub-pixel configured to emit green light. 06, wherein the green sub-pixel 06 configured to emit green light includes a first green sub-pixel 0061 and a second green sub-pixel 0062.
  • the conductive layer overlapping the anode in the light-emitting area of sub-pixel 04 and sub-pixel 05 in FIG. 2B needs to have better flatness.
  • the non-overlapping area between the anode and the conductive layer in the light-emitting area of sub-pixel 0062 or sub-pixel 0061 has a certain symmetry relative to the overlapping area. Therefore, the color shift of the display substrate in FIG. 2B is relatively weak.
  • the conductive layer overlapping the anode in the light-emitting area of the sub-pixel's light-emitting element needs to ensure a certain flatness to prevent the anode in the light-emitting area of the sub-pixel from "tilting".
  • the symmetry state of the distribution of the non-overlapping areas relative to the overlapping areas will also have an impact on the luminous effect.
  • Embodiments of the present disclosure provide a display substrate and a display device.
  • the display substrate includes a substrate substrate, multiple sub-pixels and multiple power signal lines.
  • a plurality of sub-pixels are located on the base substrate, at least some of the sub-pixels include light-emitting elements and pixel circuits, the light-emitting elements include a light-emitting functional layer and first electrodes and second electrodes located on both sides of the light-emitting functional layer in a direction perpendicular to the base substrate,
  • the first electrode is located between the light-emitting functional layer and the substrate.
  • the light-emitting element is at least partially located in the light-emitting area.
  • the first electrode of the light-emitting element includes a body electrode that overlaps with the light-emitting area; at least part of the plurality of power signal lines are along the first direction. Extended and arranged along the second direction, the plurality of power signal lines are located between the base substrate and the first electrode of the light-emitting element, the first direction intersects the second direction, wherein at least some of the sub-pixels include a plurality of first sub-pixels,
  • at least one power supply signal line includes a first power supply portion overlapping a body electrode of at least one of the plurality of first sub-pixels, and each first power supply portion includes a first body portion and The second main body part; in the second direction, the maximum size of the main body electrode of the first sub-pixel is not less than the maximum size of its corresponding first power supply part, and the maximum size of the first main body part in the first power supply part is larger than the second main body part.
  • connection line between the two farthest endpoints of the main body electrode of the first sub-pixel in the second direction is the endpoint connection line, and in the third direction, the endpoint connection line overlaps with the first main body part.
  • Embodiments of the present disclosure design the matching form of the pixel circuit and the light-emitting element, which is beneficial to improving the flatness of the conductive layer overlapping the light-emitting element and reducing the probability of color shift and other phenomena occurring in the display product.
  • Figure 3 is a schematic diagram of a pixel arrangement structure in a display substrate provided by an embodiment of the present disclosure
  • Figure 4 is a schematic diagram of a partial cross-sectional structure taken along line AA' shown in Figure 3
  • Figure 5 is a schematic diagram of the pixel arrangement structure provided by an embodiment of the present disclosure.
  • Figure 6 is a partial structural schematic diagram of the second conductive layer in a display substrate provided by an embodiment of the present disclosure
  • Figure 7 is An embodiment of the present disclosure provides a partial structural diagram of a first electrode of a light-emitting element in a display substrate.
  • the display substrate includes a base substrate 001 and a plurality of sub-pixels 10 .
  • the plurality of sub-pixels 10 are located on the base substrate 001 .
  • At least some of the sub-pixels 10 include light-emitting elements 100 and pixel circuits 200 (see FIG. 13 ).
  • the pixel circuit 200 is configured to drive the light emitting element 100 to emit light.
  • the light-emitting element 100 includes a light-emitting functional layer 101 and a first electrode 102 and a second electrode 1022 located on both sides of the light-emitting functional layer 101 in a direction Z perpendicular to the base substrate 001.
  • the first electrode 102 is located between the light-emitting functional layer 101 and the base substrate. between 001.
  • a structural layer 1004 is provided on the side of the first electrode 102 of the light-emitting element 100 away from the second electrode 1022 .
  • the structural layer 1004 may include, for example, a base substrate, a layer where the active semiconductor pattern is located, and a film where the gate lines are located. layer, the film layer where the data line is located, and multiple insulation layers.
  • the display substrate also includes a pixel defining pattern 150.
  • the pixel defining pattern 150 is located on a side of the first electrode 102 of the light emitting element 100 away from the substrate substrate 001, and the pixel defining pattern 150 includes a plurality of openings 160 and a defining portion surrounding the plurality of openings 160. 170, the plurality of light-emitting elements 100 are at least partially located in the plurality of openings 160.
  • the defining portion 170 may define the size of the opening 160 .
  • the material of the defining portion 170 may include polyimide, acrylic, polyethylene terephthalate, or the like.
  • the pixel circuit 200 includes a light emission control transistor T6 (see FIG. 8 ), and the first electrode 102 of the light emitting element 100 is electrically connected to the light emission control transistor T6.
  • the light-emitting element 100 is at least partially located in the light-emitting area 103, and the first electrode 102 of the light-emitting element 100 includes a body electrode 104 overlapping the light-emitting area 103.
  • the portion of the light-emitting element 100 located in the opening 160 is the light-emitting area 103, and the orthographic projection area of the light-emitting area 103 on the base substrate 001 is surrounded by the orthographic projection of the body electrode 104 on the base substrate.
  • the body electrode 104 may be a portion of the first electrode 102 excluding the connection electrode (see description below).
  • the electrode portion of the first electrode 102 excluding the connection electrode and the main electrode also includes a protruding electrode (not shown in the figure), for example, the protruding electrode is opposite to the main electrode of the first electrode 102 bulge.
  • the protruding electrode may be configured to block part of the structure in the pixel circuit 200 .
  • the protruding electrodes may also be configured to form capacitances with some conductive structures in the pixel circuit 200 .
  • the shape of the body electrode 104 may be the same as the shape of the opening 160 of the pixel defining pattern 150; for example, the shape of the body electrode 104 may also be different from the shape of the opening 160 of the pixel defining pattern 150, which is not the case in the embodiments of the present disclosure. limit.
  • the body electrode 104 may be polygonal.
  • the vertex corners in the polygonal body electrode 104 may be chamfered.
  • the boundary of the body electrode 104 may be formed by connecting the edges of the protruding electrodes in the body electrode 104 through smooth transitions from both ends of the protruding electrodes.
  • the body electrode 104 may include a plurality of protruding electrodes.
  • the opening 160 of the pixel defining pattern 150 is configured to define the light emitting area 103 of the light emitting element 100 .
  • the light-emitting elements 100 of multiple sub-pixels 10 may be arranged in one-to-one correspondence with the multiple openings 160 .
  • the light emitting element 100 may include a portion located in the opening 160 and a portion overlapping the defining portion 170 in a direction perpendicular to the base substrate 001 .
  • the orthographic projection area of the light emitting element 100 on the base substrate 001 may be larger than the orthographic projection area of the opening area of the opening 160 on the base substrate 001 .
  • the opening 160 of the pixel defining pattern 150 is configured to expose the first electrode 102 of the light-emitting element 100, and the exposed first electrode 102 is at least partially in contact with the light-emitting functional layer 101 in the light-emitting element 100.
  • at least part of the first electrode 102 is located between the defining portion 170 and the base substrate 001 .
  • the first electrode 102 and the second electrode 1022 located on both sides of the light-emitting functional layer 101 can drive the light-emitting functional layer 101 in the opening 160 of the pixel defining pattern 150. Make a glow.
  • the first electrode 102 may be an anode
  • the second electrode 1022 may be a cathode
  • the cathode may be formed from a material with high conductivity and low work function.
  • the cathode may be made of a metallic material.
  • the anode may be formed from a conductive material with a high work function.
  • the above-mentioned light-emitting area 103 may refer to an effective light-emitting area of the light-emitting element 100, and the shape of the light-emitting area 103 refers to a two-dimensional shape.
  • the shape of the light-emitting area 103 may be the same as the shape of the opening 160 of the pixel defining pattern 150.
  • the opening 160 of the pixel defining pattern 150 may have a shape with a small size on a side close to the base substrate 001 and a large size on a side away from the base substrate 001 .
  • the shape of the light emitting area 103 may be substantially the same as the size and shape of the opening 160 of the pixel defining pattern 150 close to the base substrate 001 side.
  • the display substrate further includes a plurality of power signal lines 300 . At least part of the plurality of power signal lines 300 extends along the first direction N and is arranged along the second direction Y.
  • the plurality of power signal lines 300 Located between the base substrate 001 and the first electrode 102 of the light emitting element 100, the first direction N and the second direction Y intersect.
  • the first direction N may be perpendicular to the second direction Y.
  • the pixel circuit 200 further includes a light emission control transistor T5 (as shown in FIG. 8 ), and the light emission control transistor T5 is electrically connected to the power signal line 300 .
  • the light emission control transistor T5 is electrically connected to the power signal line 300 .
  • multiple power signal lines 300 may be disposed in the same conductive layer and configured to provide power signals to the pixel circuit.
  • At least part of the sub-pixels 10 includes a plurality of first sub-pixels 010 .
  • at least one power signal line 300 includes a connection with the plurality of first sub-pixels 010 .
  • At least one body electrode 1040 overlaps the first power supply portion 301 .
  • the first sub-pixel 010 may be a blue sub-pixel configured to emit blue light.
  • the first sub-pixel 010 may include different types of first sub-pixels, and the various types of first sub-pixels 010 shown in FIG. 3 include four different arrangement methods. In some embodiments of the present disclosure, multiple arrangements may be adopted according to actual layout design requirements, and the embodiments of the present disclosure do not limit this.
  • the body electrode 1040 in the first sub-pixel 010 is disposed on a side of the first power supply part 301 away from the base substrate 001 , and corresponding to each body electrode 1040 , the first power supply part 301 and The body electrodes 1040 at least partially overlap.
  • each first power supply part 301 includes a first body part 31 and a second body part 32 .
  • the maximum size M1 of the body electrode 1040 of the first sub-pixel 010 is not less than its
  • the maximum size L11 of the first main body part 31 in the first power supply unit 301 is larger than the maximum size L12 of the second main body part 32 .
  • the corresponding first power supply portion 301 of the body electrode 1040 of the first sub-pixel 010 refers to the first power supply portion 301 overlapping the body electrode 1040 of the first sub-pixel 010 .
  • connection line between the two farthest endpoints A1 and A2 of the main body electrode 1040 of the first sub-pixel 010 in the second direction Y is the endpoint connection line L2.
  • the endpoint connection line is L2.
  • the line L2 overlaps the first body portion 31 .
  • the first main body part 31 and the second main body part 32 are respectively two adjacent parts of the first power supply part 301 , and in the second direction Y, the main body of the first power supply part 301
  • the maximum size L11 of the first main body part 31 in the electrode 1040 is larger than the maximum size L12 of the second main body part 32
  • the orthogonal projected area of the first main body part 31 on the base substrate 001 is larger than that of the second main body part 32 on the base substrate 001
  • the extending direction of the endpoint connection line L2 on the body electrode 1040 may be determined according to the arrangement direction of the body electrode 1040 .
  • the endpoint connection line L2 may extend along the first direction N; for example, the endpoint connection line L2 may also extend along the second direction Y, and embodiments of the present disclosure do not limit this.
  • first main body part 31 and the second main body part 32 have an integrated structure.
  • the maximum size L1 of the first power supply part 301 in this embodiment is equal to the maximum size L11 of the first body part 31.
  • the maximum size M1 of the body electrode 1040 of the first sub-pixel 010 is not less than
  • the maximum size of the first power supply part 301 is L1
  • the orthographic projection of the main body electrode 1040 of the first sub-pixel 010 on the base substrate 001 can cover the orthographic projection of the first power supply part 301 on the base substrate 001 as much as possible, thereby The flatness corresponding to the light emitting area 103 in the body electrode 1040 can be enhanced.
  • the first power supply part 301 may also include parts other than the first main body part 31 and the second main body part 32, which are not limited in the embodiments of the present disclosure.
  • the embodiments of the present disclosure are beneficial to improving the flatness of the first electrode in the light-emitting element and reducing the probability of color shift and other phenomena occurring in the display product.
  • the plurality of power signal lines 300 include a first power signal line 300-1 and a second power signal line 300-2.
  • the maximum dimensions of 2 in the second direction Y are the first dimension Lm and the second dimension Ln respectively, and the second dimension Ln is smaller than the first dimension Lm.
  • the maximum sizes of the multiple power signal lines provided by the embodiment of the present disclosure in the second direction Y are not exactly the same, and can be set according to the shape and arrangement of the first electrode 102 of the first sub-pixel 010 to improve the efficiency of the first sub-pixel. Flatness of first electrode 102 in 010.
  • the shape and arrangement of the first power part 301 can be selected according to the type of the first sub-pixel 010 .
  • the display substrate may include first power supply parts 301 having different sizes in the second direction, for example, including first power supply parts 301 having different maximum sizes in the second direction, to respectively correspond to the first power supply parts 301 having different sizes in the second direction.
  • a smaller size or a smaller size of the first sub-pixel 010 of the main body electrode 1040 can be used to adapt to the actual patterning needs.
  • the main body electrode 1040 of the first sub-pixel 010 can have good flatness and reduce the color of the display substrate. Risk of bias.
  • the first power supply portion 301 with different sizes in the second direction Y is not limited to two types, and can be set according to actual design requirements, without limitation.
  • the plurality of first sub-pixels 010 in the display substrate may include at least one first-type sub-pixel 111 , a first-type sub-pixel 010 overlapping with the body electrode 1041 of the first-type sub-pixel 111 .
  • the power supply unit 301 is a first type power supply unit 3010.
  • the overlapping area of the body electrode 1041 of the first type sub-pixel 111 and the first body part 311 of the first type power supply part 3010 may be an asymmetric area.
  • the first main body portion 311 of the first type power supply portion 3010 has an asymmetric structure.
  • the area in the first type power supply part 3010 that overlaps the body electrode 1041 of the first type sub-pixel 111 is an asymmetric area.
  • “Asymmetrical” in the embodiments of the present disclosure may mean that the structure or region is not symmetrically arranged in any direction parallel to the base substrate.
  • the body electrode 1041 of the first type sub-pixel 111 and the first type power supply part 3010 have a large overlapping area, and the overlapping area is asymmetric as a whole.
  • the orthographic projection area of the overlapping area on the base substrate 001 can be 60% to 95% of the orthographic projection area of the main electrode 1041 on the base substrate 001, and the light-emitting area 103 of the first sub-pixel 111 is on the base substrate.
  • the orthographic projection on is located inside the orthographic projection of the body electrode 1041 on the base substrate.
  • the overlapping area and the light-emitting area 103 almost overlap, that is, the part of the body electrode 1041 that overlaps the light-emitting area 103 is uniform and Arranged flatly, the uniformity of the luminous intensity of the first type sub-pixel 111 can be improved and the probability of color shift can be reduced.
  • the orthographic projection area of the overlapping area on the base substrate 001 may be 65% to 90%, or 70% to 85%, or 75% to 80% of the orthographic projection area of the body electrode 1041 on the base substrate 001 wait.
  • the first main body part 311 of the first type power supply part 3010 in the display substrate may include a first protruding part 313 located along the first direction of the second main body part 312 N extends to one side of the first symmetry center line L3.
  • the extension direction of the symmetrical center line L4 of the portion of the first type power supply portion 3010 in the display substrate except the first protruding portion 313 is consistent with the second direction of the body electrode 1041 of the first type sub-pixel 111 .
  • the extending directions of the symmetry center lines L5 intersect.
  • first symmetry center line L3 and the symmetry center line L4 may coincide.
  • the embodiments of the present disclosure are not limited to this, and the two can also be distributed at intervals.
  • the second main body portion 312 of the first type power supply portion 3010 is symmetrically distributed with respect to the first symmetrical center line L3.
  • the maximum size of the first main body portion 311 in the second direction is the same as that of the second main body portion 312 , and the first type power supply portion 3010 is also relative to the first center line of symmetry L3 Symmetrical distribution.
  • the first protrusion 313 may be disposed only on one side of the first body part 311 relative to the first symmetry center line L3, so that the first protrusion
  • the arrangement of the portion 313 can increase the overlap area between the body electrode 1041 and the first type power supply portion 3010, and can better make the body electrode 1041 covering the body electrode 1041 flat, thereby increasing the flatness of the body electrode 1041.
  • the arrangement form of the body electrode 1041 in the first type power supply unit 3010 may be diverse.
  • the body electrodes 1041 are substantially symmetrically distributed with respect to the second symmetry center line L5.
  • the symmetry center line L4 and the second symmetry center line L5 are arranged vertically, which can maximize the overlapping area of the first type power supply unit 3010 and the main body electrode 1041, and can also make the main body electrode 1041 convex.
  • the protruding corner portion covers the first protruding portion 313 of the first type power supply portion 3010, thereby improving the flatness of the body electrode 1041.
  • the angle between the extension direction of the symmetry center line L4 and the second symmetry center line L5 may be 20 to 90 degrees, such as 30 to 80 degrees, such as 45 to 60 degrees, etc.
  • the plurality of first sub-pixels 010 in the display substrate further include at least one second-type sub-pixel 112.
  • the first sub-pixel 010 overlaps with the body electrode 1042 of the second-type sub-pixel 112.
  • the power supply unit 301 is a second type power supply unit 3011.
  • the second type power supply part 3011 includes a third symmetry center line L6 extending along the first direction N
  • the body electrode 1042 of the second type sub-pixel 112 includes a third symmetry center line L6 extending along the second direction N.
  • the center line L7 is located in the same plane perpendicular to the base substrate 001.
  • the orthographic projection of the third symmetry center line L6 on the base substrate coincides with the orthographic projection of the fourth symmetry center line L7 on the base substrate.
  • the second type sub-pixel 112 is disposed on a side of the second type power supply part 3011 away from the substrate, and the second type power supply part 3011 is symmetrical with respect to the second symmetry center line. distributed.
  • the body electrode 1042 of the second-type sub-pixel 112 can be considered to be a certain rotation of the body electrode 1041 of the first-type sub-pixel 111 clockwise or counterclockwise. obtained by angle.
  • the rotation angle in this embodiment is 90°.
  • the fourth symmetry center line L7 of the body electrode 1042 of the second type sub-pixel 112 also rotates clockwise or counterclockwise relative to the body electrode 1041 of the first type sub-pixel 111.
  • the body electrode 1042 of the second type sub-pixel 112 is disposed on the side of the second type power supply part 3011 away from the base substrate. Therefore, the third symmetry center line L6 of the second type power supply part 3011 and the second type power supply part 3011
  • the fourth symmetry center lines L7 of the overlapping second type sub-pixels 112 are parallel and located in the same plane perpendicular to the base substrate 001 .
  • the plurality of third symmetrical center lines L6 and the plurality of second-type power supply portions 3011 in the same column of power signal lines 300 are related to the plurality of second-type sub-pixels 112 in the same column.
  • the plurality of fourth symmetrical center lines L7 of the plurality of second-type sub-pixels 112 overlapping the second-type power supply portions 3011 are all located in the same plane perpendicular to the base substrate 001 .
  • the body electrode 1040 of the first sub-pixel 010 includes opposite first and second corners 141 and 142 , and opposite third and fourth corners 143 and 142 .
  • portion 144, the orthographic projection of at least one of the first corner portion 141 and the second corner portion 142 on the base substrate 001 at least partially overlaps with the orthographic projection of the first symmetry center line L3 on the base substrate 001, and the fourth corner
  • the orthographic projection of the portion 144 on the base substrate 001 at least partially overlaps with the orthographic projection of the first protruding portion 313 on the base substrate 001 .
  • the arrangement is such that the orthographic projection of the second protruding portion 317 on the base substrate 001 overlaps the first corner portion 141 , and the orthographic projection of the third protruding portion 318 on the base substrate 001 overlaps the second corner portion 142
  • the orthographic projection on the base substrate 001 overlaps; or the orthographic projection of the second protrusion 317 on the base substrate 001 overlaps with the second corner portion 142 and the third protrusion 318 is on the base substrate 001
  • the orthographic projection of the first corner portion 141 overlaps with the orthographic projection of the first corner portion 141 on the base substrate 001 .
  • the maximum size L14 of the second main body part 315 of the second type power supply part 3011 in the second direction Y is also smaller than the maximum size L13 of the first main body part 314 in the second direction Y. of.
  • the maximum dimension L13 of the first main body part 314 of the second type power supply part 3011 in the second direction Y may be 1.1 times the maximum dimension L14 of the second main body part 315 of the second type power supply part 3011 in the second direction Y. -2 times.
  • the maximum dimension L13 of the first main body part 314 may be 1.2 to 1.9 times the maximum dimension L14 of the second main body part.
  • the maximum dimension L13 of the first main body part 314 may be 1.3 to 1.8 times the maximum dimension L14 of the second main body part.
  • the maximum dimension L13 of the first main body part 314 may be 1.4 to 1.7 times the maximum dimension L14 of the second main body part.
  • the maximum dimension L13 of the first main body part 314 may be 1.5 to 1.6 times the maximum dimension L14 of the second main body part.
  • the maximum dimension L13 of the first main body part 314 of the second type power supply part 3011 in the second direction Y is set as large as possible.
  • the first main body part 314 is in the second direction Y.
  • the maximum dimension L13 in the direction Y may be 1.5 times the maximum dimension L14 of the second main body part 315 in the second direction Y, so that the first corner part 141 and the second part in the main body electrode 1042 of the second type sub-pixel 112
  • the corner portion 142 just covers the first protruding portion 317 and the second protruding portion 318 of the first main body portion 314, meeting the requirement for flatness of the body electrode 1042 of the second type sub-pixel 112, while also enabling the maximum size
  • the ratio between L13 and the largest size L14 is as uniform as possible to simplify layout design and manufacturing.
  • each of the plurality of adjacent power signal lines 300 in the display substrate includes a plurality of power supply portions 300 - 3 arranged along the first direction N. Two adjacent power supply portions 300 - 3 are arranged in the first direction N. A first connection portion 330 electrically connected to two adjacent power supply portions 300-3 is provided between the power supply portions 300-3.
  • the plurality of power supply portions 300-3 include the above-mentioned first power supply portion 301, and each power supply portion has a second The ratio of the maximum dimension in the direction Y to the maximum dimension L30 of the first connecting portion 330 in the second direction Y is 1.5-5.
  • the display substrate includes a plurality of power signal lines 300 extending along the first direction N, and at least one power supply portion 300 - 3 is provided in each power signal line 300 .
  • the power supply unit 300-3 may be the first power supply unit 301 or the second power supply unit 302.
  • the first power supply part 301 corresponds to the first sub-pixel 010
  • the second power supply part 302 corresponds to the second sub-pixel.
  • the first power supply part 301 may also include a first type power supply part 3010 corresponding to the first type sub-pixel 111, and a second type power supply part 3011 corresponding to the second type sub-pixel 112.
  • the orthographic projection of the power supply unit 300-3 on the base substrate 001 at least partially overlaps with the orthographic projection of its corresponding body electrode on the base substrate 001.
  • the overlapping area of the orthographic projection of each power supply unit 300 - 3 on the base substrate 001 and the orthographic projection of the corresponding body electrode on the base substrate 001 should be as large as possible.
  • the overlapping area may be the power supply unit 300 -3 corresponds to at least 90% of the orthogonal projected area of the body electrode on the base substrate 001, so that the body electrode corresponding to the power supply part 300-3 has a high flatness.
  • two adjacent power supply units 300 - 3 are electrically connected through the first connection part 330 , that is, all power supply units 300 - 3 on the same power supply signal line 300 are electrically connected.
  • the ratio of the maximum dimension L30 of each power supply unit 300-3 in the second direction Y to the maximum dimension L30 of the first connection part 330 in the second direction Y may be 1.5-5, for example, it may be 4, 2, 3, etc. .
  • the maximum dimension L30 in the second direction Y of the first connection part 330 can be designed to be smaller, which can make the layout space more relaxed and have Conducive to layout layout.
  • the first type power supply part 3010 includes a first sub-type power supply part 3016 and a second sub-type power supply part 3017 , and the second main body part 312 of the first type power supply part 3010 is included in the second direction Y.
  • the first protruding portion 3131 in the first sub-type power supply part 3016 is disposed on the first side K1 of the second main body part 312, and the first protruding part 3131 in the second sub-type power supply part 3017 is The protruding portion 3132 is provided on the second side K2 of the second main body portion 312 .
  • the direction indicated by the arrow in the Y direction is to the right
  • the first protruding portion 3131 provided in the first sub-type power supply unit 3016 is located on the left side of the second main body portion 312
  • the second sub-type The first protruding portion 3132 provided on the power supply portion 3017 is located on the right side of the second main body portion 312 .
  • first sub-type power supply portion 3016 and the second sub-type power supply portion 3017 arranged along the Y direction and adjacent to each other are symmetrically distributed with respect to a straight line extending along the N direction.
  • first sub-type power supply unit 3016 and the second sub-type power supply unit 3017 that are adjacent to each other may mean that no other first sub-type power supply unit 3016 and second sub-type power supply unit 3017 are provided between these two power supply units. , but other types of power supply units can be set.
  • the multiple power supply portions on each power supply signal line 300 may be different.
  • the maximum size of different power supply portions in the second direction Y may be different, so that they can be flexibly adapted to different body electrodes.
  • the arrangement form meets the flatness requirements of different body electrodes.
  • the orthographic projection of the fourth corner portion 144 of the body electrode 1041 of the first type sub-pixel 111 on the base substrate 001 can cover the third A protruding portion 3131 or a second protruding portion 3132 is formed on the orthographic projection of the base substrate 001 to ensure the flatness of the body electrode 1041 at the fourth corner 144 .
  • the body electrode 1040 of the first sub-pixel 010 includes a first corner 141 , a second corner 142 , a third corner 143 and a fourth corner 144 , and each side of the body electrode 1040 or
  • the extension lines are connected in sequence to form a polygon H10, and the multiple vertex corners of the polygon H10 have areas that do not overlap with the multiple corners of the corresponding body electrodes.
  • the third corner 143 does not overlap with the corresponding vertex corners of the polygon H10.
  • the overlapping region area A10 is larger than the area of the region in which each corner of at least some of the other corners does not overlap with the vertex corner of the polygon corresponding to the corner.
  • the four extension lines H1, H2, H3 and H4 of the body electrode 1040 constitute the polygon H10.
  • the polygon H10 includes a non-overlapping area A10 at the vertex corner; corresponding to the second corner 142, the polygon H10 includes a non-overlapping area A11 at the vertex corner; corresponding to the third corner 143 , the polygon H10 includes a non-overlapping area A12 at the vertex corner; corresponding to the fourth corner 144 , the polygon H10 includes a non-overlapping area A13 at the vertex corner.
  • the four corners of the body electrode 1040 may respectively include chamfers of different sizes.
  • the chamfers at the third corner 143 are larger than the chamfers at other corners, thereby making the third corner
  • the area A12 of the area where the portion 143 and the vertex of the corresponding polygon H10 do not overlap is larger than the area of the area where each of the other corner portions does not overlap with the vertex of the polygon H10 corresponding to the corner.
  • the chamfer size of each corner of the body electrode 1040 can be designed according to the size requirements of each light-emitting area.
  • the shapes of each body electrode provided in the embodiments of the present disclosure are only exemplary. Non-restrictive. This ensures flexibility in the shape design of the body electrode.
  • the above-mentioned chamfer may refer to the vertex angle formed by a curve, which may be an arc or an irregular curve, such as a curve intercepted from an ellipse, a wavy line, etc.
  • the embodiment of the present disclosure schematically shows that the curve has a shape that is convex outward relative to the center of the sub-pixel, but is not limited thereto.
  • the curve may also have a shape that is concave relative to the center of the sub-pixel.
  • the central angle of the arc can range from 10° to 150°.
  • the central angle of the arc may range from 60° to 120°.
  • the range of the central angle of the arc may be 90°.
  • the curve length of the rounded chamfer included in the third corner portion 143 may be 10 to 60 microns.
  • the radius of curvature of the chamfer at the third corner 143 is larger than the radius of curvature of the chamfers at other corners.
  • the first protruding part 313 includes an inclined edge connected to the straight edge of the second main body part 312 , and the angle between the inclined edge and the first direction N may be 10 to 90 degrees.
  • the angle between the inclined side and the side connecting the fourth corner 144 and the first corner 141 can be 0 to 30 degrees, such as 2 to 25 degrees, such as 5 to 20 degrees, such as 7 to 15 degrees, such as 8 to 20 degrees. 10 degrees.
  • one of the second protruding portion 317 and the third protruding portion 318 has the same shape and size as the first protruding portion 313 , and the second protruding portion 317 and the third protruding portion 318 have the same shape and size.
  • the outlet portion 318 is symmetrically distributed with respect to the third symmetry center line L6 extending along the first direction N of the second type power supply portion 3011 .
  • the same column power signal line 300 The fifth symmetry center line L32 of the second power supply part 302 and the sixth symmetry center line L33 of the second sub-pixel overlapping the second power supply part 302 are located in the same plane perpendicular to the base substrate 001 .
  • the orthographic projection of the main body electrode 1050 of the second sub-pixel 020 on the base substrate 001 is smaller than the orthographic projection area of the main body electrode 1040 of the first sub-pixel 010 on the base substrate 001
  • the third The maximum size of the main body electrode 1050 of the second sub-pixel 020 in the first direction N is smaller than the maximum size of the main body electrode 1040 of the first sub-pixel 010 in the first direction N
  • the maximum size of the main body electrode 1050 of the second sub-pixel 020 in the second direction Y is The maximum size is smaller than the maximum size of the main body electrode 1040 of the first sub-pixel 010 in the second direction Y.
  • the main body electrode 1050 of the second sub-pixel 020 is symmetrically distributed with respect to the sixth symmetry center line L33 extending along the first direction N, and the second power supply portion 302 is symmetrically distributed with respect to the fifth symmetry center line L32 extending along the first direction N. And the body electrode 1050 is disposed on the side of the second power supply part 302 away from the base substrate 001. Therefore, for the same second sub-pixel 020, the fifth symmetry center line L32 of the second power supply part 302 and the second power supply part 302 are The sixth symmetry center line L33 of the overlapping second sub-pixel 302 is located in the same plane perpendicular to the base substrate 001 .
  • the fifth symmetry center line L32 and the sixth symmetry center line L33 are parallel, and both are located in the same plane perpendicular to the base substrate 001 .
  • the fifth symmetry center line L32 and the sixth symmetry center line L33 of the same column of power signal lines 300 are located on the same axis perpendicular to the base substrate 001 within the plane.
  • the orthographic projection of the body electrode 1050 on the base substrate 001 is relatively small, and when the overlapping area AS1 is When the body electrode 1050 of the second sub-pixel 020 accounts for more than 90% of the orthographic projection area AS on the base substrate 001, the body electrode 1050 in the light-emitting area 1033 of the second sub-pixel 020 is almost completely flat, which can effectively Prevent color casts from occurring.
  • the second power supply unit 302 and the first power supply unit 301 have different shapes.
  • the area of the second power supply unit 302 is smaller than the area of the first power supply unit 301 .
  • the ratio of the maximum size of the second power supply part 302 in the second direction Y to the maximum size of the second main body part 32 of the first power supply part 301 in the second direction Y may be 0.9 ⁇ 1.1.
  • the first type power supply part 3010 may have the same shape as the second power supply part 302 except for the first protruding part 313, and the areas thereof may be the same.
  • the second type power supply part 3011 may have the same shape as the second power supply part 302 except for the second protruding part 317 and the third protruding part 318, and the areas thereof may be the same.
  • each second power supply unit 302 may have the same shape and area.
  • different portions of the power signal line 300 overlapping the first electrodes 102 of different second sub-pixels 020 may have the same shape and area.
  • the display substrate further includes a plurality of data lines 400 extending along the first direction N and arranged along the second direction Y.
  • the plurality of data lines 400 and the plurality of power signal lines 300 The data lines 400 arranged between two adjacent power signal lines 300 include a first data line 401 and a second data line 402 arranged along the second direction Y.
  • the first data line 401 and the second data line 402 are arranged on the same layer.
  • the lines 402 are symmetrically distributed with respect to the seventh symmetry center line L40 between the first data line 401 and the second data line 402 .
  • each data line also includes a connection block 450 to achieve connection with the transistor in the pixel circuit 200 .
  • the connection block is adjacent to and spaced apart from each power supply unit.
  • the minimum distance between the connection block and each power supply unit is approximately 1/3-2 of the size of the first connection portion 330 in the second direction Y. /3, which can help to relax the layout space and prevent signal interference between various signal lines.
  • the above-mentioned maximum dimension V may include the line width of the first data line 401 and the second data line 402 and the distance between them.
  • the orthographic projection area of the body electrode 1060 of the third sub-pixel 030 on the base substrate 001 is smaller than the orthographic projection area of the body electrode 1050 of the second sub-pixel 020 on the base substrate 001
  • the maximum size of the main body electrode 1060 of the third sub-pixel 030 in the first direction N is smaller than the maximum size of the main body electrode 1050 of the second sub-pixel 020 in the first direction N.
  • the main body electrode 1060 of the third sub-pixel 030 is in the second direction.
  • the maximum size in Y is smaller than the maximum size in the second direction Y of the body electrode 1050 of the second sub-pixel 020 .
  • the third sub-pixel 030 may have two different arrangement modes, and the third sub-pixel 030 in two different arrangement modes are arranged symmetrically with respect to the fourth symmetry center line L7.
  • the overlapping area AS2 of the body electrode 1060 of the third sub-pixel 030 and the data line 400 includes two parts, and the overlapping area AS2 is substantially symmetrical with respect to the seventh symmetry center line L40. Therefore, by symmetrically distributing the overlapping area AS2 with respect to the seventh symmetry center line L40, the flatness of the main body electrode 1060 of the third sub-pixel 030 can be increased to reduce the occurrence of color shift and other phenomena in the third sub-pixel 030.
  • the body electrode 1060 of the third sub-pixel 030 overlaps the portion of the data line 300 except the connection block 450 .
  • the display substrate further includes a plurality of second connection portions 500 .
  • the plurality of second connection portions 500 are arranged on the same layer as at least part of the plurality of power signal lines 300 .
  • Each second connection portion 500 includes a third A connecting piece 501 and a second connecting piece 502.
  • the plurality of second connection portions 500 are arranged in an array along the first direction N and the second direction Y to form a plurality of second connection portion rows 503 and a plurality of second connection portion columns 504 .
  • the power signal line 300 includes a plurality of power supply units arranged along the first direction N, such as a first power supply unit 301 and a second power supply unit 302. There is a power supply unit between two adjacent power supply units that is electrically connected to the two adjacent power supply units.
  • the power supply parts included in the plurality of power supply signal lines 300 are arranged in an array along the first direction N and the second direction Y to form a plurality of power supply part rows 308 and a plurality of power supply part columns 309 .
  • a plurality of second connection portion rows 503 and a plurality of power supply portion rows 308 are alternately arranged in the first direction N, and two adjacent second connection portions 500 in the same second connection portion row 503 are distributed on both sides of the data line 400 .
  • the plurality of second connecting parts 500 include a plurality of first connecting members 501 and a plurality of second connecting members 502 .
  • the plurality of first connecting members 501 include a plurality of first connecting members 501 arranged along the second direction Y.
  • a connector row, the plurality of second connectors 502 includes a plurality of second connector rows arranged along the second direction Y, the plurality of first connector rows and the plurality of second connector rows are alternately arranged along the second direction Y .
  • first connecting member 501 and the second connecting member 502 may be the same or different.
  • two adjacent second connection parts 500 in the same second connection part row 503 are symmetrically distributed with respect to the seventh symmetry center line L40.
  • the first connection part 501 or the second connection part 502 is connected to the data line.
  • the minimum distance 400 is basically consistent with the minimum distance between the first connecting member 501 or the second connecting member 502 and the first connecting part 300, thereby making the layout space distribution even and loose.
  • the first electrode 102 of the light-emitting element 100 also includes a connection electrode 105 electrically connected to the body electrode 104 .
  • the connection electrode 105 does not overlap with the light-emitting area 103 of the light-emitting element 100 , and the connection electrode 105 passes through
  • the second connection part 500 is electrically connected to the light emission control transistor T6.
  • connection electrode 105 of the body electrode 104 in each pixel circuit is disposed on one side of the body electrode 104.
  • the connection electrode 105 can They are all arranged on the left side of the center line extending along the first direction N of the body electrode 104 .
  • the area of the orthographic projection of the connection electrode 105 on the base substrate 001 is smaller than the area of the orthogonal projection of the body electrode 104 on the base substrate 001 .
  • connection electrode 105 on the base substrate 001 does not overlap with the orthographic projection of the data line 400 on the base substrate 001, and does not overlap with the orthographic projection of the light-emitting area 103 on the base substrate 001. Therefore, The connection electrode 105 can be prevented from interfering with the signals in the data line and the light-emitting area 103, thereby ensuring the performance of the pixel circuit 200.
  • connection electrode 105 of the light-emitting element 100 does not overlap with the first connection portion 300 , and in the first direction N, the maximum size L975 of the body electrode 1040 of the first sub-pixel 010 is not smaller than its The corresponding maximum size of the first main body part 31 in the first power supply part 301 is L985.
  • the maximum size L975 of the body electrode 1040 of the first sub-pixel 010 may be larger than the maximum size L985 of the first body part 31 .
  • the maximum size L985 of the first body part 31 may be 1/4-1/2 of the maximum size L975 of the body electrode 1040 of the first sub-pixel 010 .
  • the maximum size L985 of the first body part 31 may be 1/3-2/3 of the maximum size L975 of the body electrode 1040 of the first sub-pixel 010 .
  • the first connection part 300 is provided between the first connection part 501 and the second connection part 502 of the same second connection part 500, and the first connection part of the same second connection part 500
  • the member 501 and the second connecting member 502 are spaced apart relative to the first connecting portion 300 therebetween.
  • connection electrode 105 of the light-emitting element 100 is electrically connected to the first connection member 501 and the second connection member 502, and the first connection member 501 and the second connection member 502 in each second connection part 500 are connected to the adjacent first connection member 501 and the second connection member 502.
  • the portions 300 are spaced apart, thereby reducing interference between the signal of the connection electrode 105 when connected to the second connection portion 500 and the signal on the first connection portion 300 .
  • the orthographic projection of the body electrode 104 of the light-emitting element 100 on the base substrate and the orthographic projection of the second connection portion 500 on the base substrate are spaced as far as possible to prevent the second connection portion 500 from affecting the flatness of the body electrode 104.
  • arranging the first connecting part 501 and the second connecting part 502 of the same second connecting part 500 symmetrically with respect to the first connecting part 300 therebetween further facilitates layout arrangement.
  • the maximum dimension L51 of the first connecting member 501 or the second connecting member 502 in the first direction N is smaller than the maximum dimension L52 of the first connecting part 300 in the first direction N.
  • the first connection member 501 is electrically connected to the connection electrode 1051 of the first sub-pixel 010 or the connection electrode 1051 of the second sub-pixel 020 , and the second connection member 502 is connected to the third sub-pixel 030 Electrode 1061 is electrically connected.
  • connection electrodes 1051 of the adjacent first sub-pixel 010 , the connection electrodes 1051 of the second sub-pixel 020 and the connection electrodes 1051 of the third sub-pixel 030 are arranged at intervals in sequence. cloth, and the connection electrode 1051 of the first sub-pixel 010 and the connection electrode 1051 of the third sub-pixel 030 are both disposed on the side of the second connection part 500 close to the first connecting member 501, and the connection electrode 1051 of the second sub-pixel 020 is disposed On the side of the second connecting part 500 close to the second connecting piece 502, the second connecting part 500 is also spaced apart in the second direction. This can facilitate the utilization and design of layout space.
  • the plurality of sub-pixels 10 include a plurality of first sub-pixels 010 , a plurality of second sub-pixels 020 and a plurality of third sub-pixels 030 .
  • one of the first sub-pixel 010 and the second sub-pixel 020 is a blue sub-pixel that emits blue light
  • the other one of the first sub-pixel 010 and the second sub-pixel 020 is a red sub-pixel that emits red light
  • the third sub-pixel Pixel 030 is a green sub-pixel that emits green light.
  • the first sub-pixel 010 is a blue sub-pixel
  • the second sub-pixel 020 is a red sub-pixel
  • the area of the light-emitting area of the blue sub-pixel is larger than the area of the light-emitting area of the red sub-pixel.
  • the area of the light-emitting area of the blue sub-pixel is larger than the area of the light-emitting area of the green sub-pixel.
  • the embodiments of the present disclosure are not limited to this.
  • the names of the first sub-pixel, the second sub-pixel and the third sub-pixel can be interchanged.
  • the first sub-pixel can be a green sub-pixel
  • the second sub-pixel can be a blue sub-pixel
  • the third sub-pixel may be a red sub-pixel; or the first sub-pixel may be a blue sub-pixel, the second sub-pixel may be a red sub-pixel, the third sub-pixel may be a green sub-pixel, etc.
  • a plurality of first sub-pixels 010 and a plurality of second sub-pixels 020 are alternately arranged along the first direction N and the second direction Y to form a plurality of first pixel rows 061 and a plurality of first pixels.
  • a plurality of third sub-pixels 030 are arranged in an array along the first direction N and the second direction Y to form a plurality of second pixel rows 071 and a plurality of second pixel columns 072 .
  • the centers of the light-emitting areas of the adjacent first sub-pixel 010 and the second sub-pixel 020 are the four vertices of the virtual quadrilateral, and the center of the light-emitting area of the third sub-pixel 030 is provided within the virtual quadrilateral.
  • a second pixel row 071 includes a plurality of third sub-pixel pairs 035 arranged along the second direction Y, and two third sub-pixels 030 in a third sub-pixel pair 035 are respectively One pixel block 0301 and a second pixel block 0302, and the first pixel block 0301 and the second pixel block 0302 are alternately arranged along the second direction Y.
  • the first pixel blocks 0301 and the second pixel blocks 0302 in a second pixel column 072 are alternately arranged along the first direction N.
  • multiple sub-pixels 10 include multiple minimal repeating units 700 , and one minimal repeating unit 700 includes a first sub-pixel 010 , a first pixel block 0301 , a second pixel block 0302 and a second Subpixel 020.
  • at least two minimum repeating units 700 include a first sub-pixel 010, a first pixel block 0301, a second pixel block 0302 and a second sub-pixel 020.
  • each minimum repeating unit 700 includes a first sub-pixel 010, a first pixel block 0301, a second pixel block 0302 and a second sub-pixel 020.
  • each minimal repeating unit 700 includes two rows and four columns of sub-pixels 10 .
  • the first pixel block 0301 and the first sub-pixel 010 constitute the first pixel unit 701
  • the second pixel block 0302 and the second sub-pixel 020 constitute the second pixel unit 702. .
  • the first pixel block 0301 and the first sub-pixel 010 constitute the first pixel unit 701
  • the second pixel block 0302 and the second sub-pixel 020 constitute the second pixel unit 702.
  • the above-mentioned first pixel unit and second pixel unit are not pixels in the strict sense, that is, a pixel defined by a complete first sub-pixel 010, a second sub-pixel 020, and a third sub-pixel 030.
  • the minimum repeating unit 700 here refers to the minimum repeating unit in which the pixel arrangement structure may include multiple repeating arrangements.
  • the first sub-pixel 010 and the second sub-pixel 020 are common sub-pixels, and through the virtual algorithm, the four sub-pixels can realize the display of two virtual pixel units.
  • connection electrodes 1061 of the plurality of third sub-pixels 030 are electrically connected to the corresponding second connection portions 500 through the plurality of second connection holes D1, and the plurality of second connection holes D1 are located on the plurality of second connection lines X2.
  • a connection line X1 and a second connection line X2 both extend along the second direction Y and are spaced apart.
  • the first connection line X1 and the second connection line X2 are spaced apart in the first direction N, thereby also allowing a plurality of first sub-pixels 010 , a plurality of second sub-pixels 020 and a plurality of third sub-pixels 030 In the first direction N, there are intervals to make the layout space more uniform.
  • the plurality of first connection holes D0 may also have a certain deviation relative to the first connection line X1, that is, the plurality of first connection holes D0 may not be completely distributed on the first connection line X1. superior.
  • at least one first connection hole D0 has a deviation of 1-2 microns relative to the first connection line X1.
  • at least one first connection hole D0 has a deviation of 2-3 microns relative to the first connection line X1.
  • the plurality of second connection holes D1 may also have a certain deviation relative to the second connection line X2.
  • at least one second connection hole D1 has a deviation of 1-2 microns relative to the second connection line X2.
  • at least one second connection hole D1 has a deviation of 2-3 microns relative to the second connection line X21.
  • the first connection hole D0 corresponding to the first sub-pixel 010, the first connection hole D0 corresponding to the second sub-pixel 020, and the first pixel block 0301 correspond to
  • the second connection hole D1 of 0302 is located on the same first connection line X1, and the second connection hole D1 corresponding to the second pixel block 0302 is located on the second connection line X2.
  • the first connection hole D0 corresponding to the first sub-pixel 010 is located on the first connection line X1
  • the first connection hole D0 corresponding to the second sub-pixel 020 and the first pixel block 0301 correspond to
  • the second connection hole D1 of the second pixel block 0302 and the second connection hole D1 corresponding to the second pixel block 0302 are located on the second connection line X2, and the embodiment of the present disclosure does not limit this.
  • connection holes D1 can be arranged at equal intervals.
  • the connection holes D1 can be arranged at equal intervals.
  • the second connection holes D1 corresponding to the pixel block 0302 may also be arranged at unequal intervals, and embodiments of the present disclosure do not limit this.
  • the digging portion 380 on the first connecting portion 330 may be a through hole or opening penetrating the first connecting portion 330 in a direction perpendicular to the base substrate, such as the digging portion 380
  • the structure of the pixel circuit 200 on the side of the first connection portion 330 close to the base substrate 001 can be exposed, for example, the first connection portion 330 has a hollow pattern.
  • the digging portion 380 on the first connection 330 has substantially no overlap with the first electrode 102 .
  • the display product can enhance its transmittance by providing the perforated portion 380 .
  • providing the digging portion 380 on the first connecting portion 330 can improve the light transmittance of the display substrate and improve the display effect.
  • the number of the digging portions 380 on the first connecting portion 380 can be determined according to actual layout design requirements, and embodiments of the present disclosure do not limit this.
  • the digging portion 380 can be designed to have a regular shape.
  • the digging portion 380 can be designed to be a polygon, an ellipse, a regular polygon, a circle, etc.
  • the digging portion 380 may also be designed in an irregular shape.
  • the shapes of the plurality of digging portions 380 may be the same.
  • the shapes of the plurality of digging portions 380 may also be designed to be different. Embodiments of the present disclosure do not limit the shape of the hole-digging portion 380 .
  • the digging portions 380 on the same first connecting portion 330 may be symmetrically distributed with respect to a central symmetry line of the first connecting portion 330 .
  • the position of the hole-digging portion 380 in the first connecting portion 330 can also be determined according to the design needs of the actual layout, and embodiments of the present disclosure do not limit this.
  • the distance between the boundary of the digging part 380 and the boundary of the first connection part 330 is not less than 1 micron to prevent the first connection part 330 from being disconnected.
  • FIG. 8 is an equivalent diagram of a pixel circuit provided according to an embodiment of the present disclosure.
  • the light emission control transistor T6 in the pixel circuit 200 may be a first light emission control transistor T6.
  • the pixel circuit 200 also includes a second reset transistor T1, a threshold compensation transistor T2, a driving transistor T3, and a data writing transistor. T4, the second light emission control transistor T5, the first reset control transistor T7 and the storage capacitor C.
  • the first pole of the threshold compensation transistor T2 is electrically connected to the first pole of the driving transistor T3, the second pole of the threshold compensation transistor T2 is electrically connected to the gate of the driving transistor T3; the first pole of the first reset control transistor T7 is electrically connected to The reset power supply signal line is electrically connected to receive the reset signal Vinit.
  • the second electrode of the first reset control transistor T7 is electrically connected to the first electrode of the light-emitting element 100 (i.e., the N4 node); the first electrode of the data writing transistor T4 is connected to the driving transistor.
  • the second electrode of T3 is electrically connected, the second electrode of the data writing transistor T4 is electrically connected with the data line to receive the data signal Data, the gate electrode of the data writing transistor T4 is electrically connected with the scanning signal line to receive the scanning signal Gate; storage capacitor The first electrode of C is electrically connected to the power signal line, the second electrode of the storage capacitor C is electrically connected to the gate of the driving transistor T3; the gate of the threshold compensation transistor T2 is electrically connected to the scanning signal line to receive the compensation control signal; first The gate of the reset transistor T7 is electrically connected to the reset control signal line to receive the reset control signal Reset(N+1); the first electrode of the second reset transistor T1 is electrically connected to the reset power signal line to receive the reset signal Vinit.
  • the second reset The second electrode of the transistor T1 is electrically connected to the gate of the driving transistor T3, the gate of the second reset transistor T1 is electrically connected to the reset control signal line to receive the reset control signal Reset(N); the gate of the first light emitting control transistor T6
  • the light-emitting control signal line is electrically connected to receive the light-emitting control signal EM; the first pole of the first light-emitting control transistor T6 is electrically connected to the first pole of the driving transistor T3, and the second pole of the first light-emitting control transistor T6 is electrically connected to the light-emitting element 100.
  • the first electrode is electrically connected; the first electrode of the second light-emitting control transistor T5 is electrically connected to the power signal line to receive the first power signal VDD, and the second electrode of the second light-emitting control transistor T5 is electrically connected to the second electrode of the driving transistor T3 , the gate electrode of the second light-emitting control transistor T5 is electrically connected to the light-emitting control signal line to receive the light-emitting control signal EM, and the second electrode of the light-emitting element 100 is connected to the voltage terminal VSS.
  • the above-mentioned power signal line refers to a signal line that outputs the voltage signal VDD, and can be connected to a voltage source to output a constant voltage signal, such as a positive voltage signal.
  • the scan signal and the compensation control signal may be the same, that is, the gate of the data writing transistor T3 and the gate of the threshold compensation transistor T2 may be electrically connected to the same signal line to receive the same signal, reducing the number of signal lines.
  • the gate of the data writing transistor T3 and the gate of the threshold compensation transistor T2 may also be electrically connected to different signal lines respectively, that is, the gate of the data writing transistor T3 is electrically connected to the first scanning signal line, and the gate of the threshold compensation transistor T2 is electrically connected to the first scanning signal line.
  • the gate of T2 is electrically connected to the second scanning signal line, and the signals transmitted by the first scanning signal line and the second scanning signal line may be the same or different, so that the data is written into the gate of the transistor T3 and the threshold compensation transistor T2 They can be controlled separately, increasing the flexibility of controlling the pixel circuit 200 .
  • the light emission control signals input to the first light emission control transistor T6 and the second light emission control transistor T5 may be the same, that is, the gate electrode of the first light emission control transistor T6 and the gate electrode of the second light emission control transistor T5 may be electrically connected to the same terminal.
  • One signal line to receive the same signal reducing the number of signal lines.
  • the gate of the first light-emitting control transistor T6 and the gate of the second light-emitting control transistor T5 can also be electrically connected to different light-emitting control signal lines respectively, and the signals transmitted by the different light-emitting control signal lines can be the same or different. .
  • the reset control signal input to the first reset transistor T7 and the second reset transistor T1 may be the same, that is, the gate electrode of the first reset transistor T7 and the gate electrode of the second reset transistor T1 may be electrically connected to the same signal line. Receive the same signal and reduce the number of signal lines.
  • the gate of the first reset transistor T7 and the gate of the second reset transistor T1 may also be electrically connected to different reset control signal lines respectively. In this case, the signals on the different reset control signal lines may be the same or different.
  • the second reset transistor T1 when the display substrate is working, in the first stage of screen display, the second reset transistor T1 is turned on to initialize the voltage of the N1 node; in the second stage of screen display, data data is written through the data transistor T4, the driving transistor T3 and the threshold compensation transistor T2 are stored at the N1 node; in the third light-emitting stage, the second light-emitting control transistor T5, the driving transistor T3 and the first light-emitting control transistor T6 are all turned on, and the light-emitting element 100 is forward-conducted and emits light.
  • each pixel circuit in addition to the 7T1C (ie, seven transistors and one capacitor) structure shown in FIG. 8 , each pixel circuit can also be a structure including other numbers of transistors, such as 7T2C. structure, 6T1C structure, 6T2C structure or 9T2C structure, the embodiments of the present disclosure are not limited to this.
  • the equivalent diagram of the pixel circuit in the display substrate shown in the above embodiment may be the same as the equivalent diagram of the pixel circuit 200 shown in FIG. 8 .
  • FIG. 9 is a schematic diagram of the stacked structure of the light shielding layer, the active semiconductor pattern, and the first connection layer in the pixel circuit according to an embodiment of the present disclosure.
  • 10 is a schematic diagram of a stacked structure of a light shielding layer, an active semiconductor pattern, a first connection layer, a second connection layer, a semiconductor layer and a third connection layer in a pixel circuit according to an embodiment of the present disclosure.
  • the active semiconductor pattern LY1 is provided on the light-shielding layer LY0 , and the active semiconductor pattern LY1 can be formed by patterning a semiconductor material.
  • the active semiconductor pattern LY0 and the first connection layer LY2 can be used to make the active layer of the above-mentioned driving transistor T3, data writing transistor T4, second light emission control transistor T5, first light emission control transistor T6 and first reset control transistor T7 used to form the channel region of the above-mentioned transistor.
  • the active semiconductor pattern LY0 includes the active layer pattern (channel region) and doping region pattern (source and drain region) of the above-mentioned transistor of each sub-pixel, and the active layer pattern and doping region of the above-mentioned transistor in the same pixel circuit Pattern integrated setting.
  • the active semiconductor pattern LY1 can be made of amorphous silicon, polysilicon, oxide semiconductor materials, etc. It should be noted that the above-mentioned source region and drain region may be regions doped with n-type impurities or p-type impurities.
  • a metal layer such as a gate metal layer, is provided on the side of the active semiconductor pattern LY1 away from the base substrate.
  • the metal layer includes the above-mentioned scanning signal line, reset control signal line, light emission control signal line, driving transistor T3, data write The gate electrode of the input transistor T4, the second light emission control transistor T5, the first light emission control transistor T6 and the first reset control transistor T7.
  • Each dotted rectangular frame in Figure 9 shows each part where the above-mentioned metal layer overlaps with the active semiconductor pattern LY1 as the channel region of each transistor.
  • the active semiconductor pattern LY1 on both sides of each channel region is doped by ions.
  • the conductorization process is used as the first electrode and the second electrode of each transistor (ie, the above-mentioned source and drain regions).
  • the source and drain of a transistor can be symmetrical in structure, so there can be no difference in physical structure between the source and drain.
  • the third electrode of all or part of the transistors is The first and second poles are interchangeable as needed.
  • the semiconductor layer LY4 forming the channel region of the second reset transistor T1 and the threshold compensation transistor T2 in the pixel circuit may be located on a side of the active semiconductor pattern LY1 away from the base substrate, and the semiconductor layer LY4 may include an oxide semiconductor material.
  • the pixel circuit provided in FIG. 10 includes a light-shielding layer LY0 laid layer by layer, an active semiconductor pattern LY1, a first connection layer LY2, a second connection layer LY3, a semiconductor layer LY4 and a third connection layer.
  • the dotted rectangular frame shows the channel region of the second reset transistor T1 and the threshold compensation transistor T2 .
  • the second connection layer LY3 can provide a bottom gate structure for the second reset transistor T1 and the threshold compensation transistor T2.
  • the semiconductor layer LY4 is overlapped with the second connection layer LY3, and a third connection layer is laid on its side away from the base substrate.
  • the connection layer LY5 serves as the top gate layer structure of the second reset transistor T1 and the threshold compensation transistor T2.
  • the transistor using the oxide semiconductor has the characteristics of good hysteresis characteristics, low leakage current, and high mobility. (Mobility) is low, so oxide semiconductor transistors can be used to replace the low-temperature polysilicon material in the transistors to form a low-temperature polysilicon-oxide (LTPO) pixel circuit to achieve low leakage and help improve the stability of the gate voltage of the transistor.
  • LTPO low-temperature polysilicon-oxide
  • the embodiments of the present disclosure are not limited to the active semiconductor pattern of the pixel circuit being the active semiconductor pattern LY1 shown in FIG. 9A.
  • the semiconductor layer in the channel region of the second reset transistor T1 and the threshold compensation transistor T2 can also be combined with other transistors.
  • the semiconductor layer of the channel region is located on the same layer, that is, the active semiconductor pattern may include a second reset transistor T1, a threshold compensation transistor T2, a driving transistor T3, a data writing transistor T4, a second light emission control transistor T5, and a first light emission control transistor. T6 and the channel region of the first reset control transistor T7.
  • FIG. 11 is a schematic diagram of a partial structure of the first conductive layer according to an embodiment of the present disclosure
  • FIG. 12 is a light-shielding layer, an active semiconductor pattern, a first connection layer, and a second connection layer in a pixel circuit according to an embodiment of the present disclosure.
  • Figure 13A is a schematic diagram of the stacked structure of the first conductive layer and the second conductive layer according to an embodiment of the present disclosure
  • Figure 13B is a schematic diagram of the stacked structure of the first conductive layer and the second conductive layer according to an embodiment of the present disclosure
  • a schematic diagram of the stacked structure of the first conductive layer, the second conductive layer and the light-emitting element is provided in the disclosed embodiment.
  • the display substrate includes a first conductive layer LY6 (eg, SD1 layer) between the first electrode of the light-emitting element and the third connection layer LY5.
  • the first conductive layer LY6 includes a reset power signal line 801 , the reset power signal line 801 is electrically connected to the first pole of the first reset transistor T7 to provide a reset signal.
  • the above-mentioned reset power supply signal line 801 may be a first reset power supply signal line electrically connected to the first pole of the first reset transistor T7.
  • the display substrate further includes a second reset power supply signal line, and a first part of the second reset power supply signal line. It is located between the first conductive layer LY6 and the film layer where the gate electrode of the first reset transistor T7 is located, and is configured to be electrically connected to the first electrode of the second reset transistor T1 to provide a reset signal.
  • the first conductive layer LY6 further includes a connection structure 802
  • the second conductive layer LY7 further includes a connection block 450
  • the second pole of the data writing transistor T4 is connected to the connection through the connection structure 802.
  • Block 450 is in turn electrically connected to the data line 400 to receive the data signal.
  • the first conductive layer LY6 further includes a connection structure 803 through which the second reset transistor T1 is electrically connected to the second reset signal line.
  • the first conductive layer LY6 further includes a connection structure 804 through which the first pole of the first light emission control transistor T6 and the second pole of the first reset transistor T7 pass.
  • the connection structure 804 and the second connection portion 500 in the second conductive layer LY7 are electrically connected to the connection electrode 105 in the light-emitting element LY8, and the connection structure 804 is electrically connected to the connection electrode 105.
  • the first conductive layer LY6 also includes a connection structure 805.
  • the connection structure 805 includes a first connection structure 805A and a second connection structure 805B.
  • One pole is electrically connected to the first connection structure 805A
  • the second connection structure 805B is electrically connected to the first connection portion 330 in the second conductive layer LY7, so that the first pole of the second light emission control transistor T5 is connected to the power signal line 300 Electrical connection.
  • the first conductive layer LY6 further includes a connection structure 806 through which the first electrode of the threshold compensation transistor T2 is connected to the first electrode of the driving transistor T3 and the second electrode of the first light emitting control transistor T6 . pole to achieve electrical connection.
  • the first conductive layer LY6 further includes a connection structure 807 to realize a connection between the second electrode of the second reset transistor T1 , the second electrode of the threshold compensation transistor T2 and the gate electrode of the driving transistor T3 . Electrical connection.
  • connection structure 804 on the base substrate 001 substantially coincides with the orthographic projection of the connection block 450 on the base substrate 001, and the connection structure 804 has no overlap with the orthographic projection of the light-emitting element 100 on the base substrate 001, which is beneficial to layout design and reduces signal interference between the light-emitting elements 100.
  • connection structure 805 also includes a third connection structure 805C.
  • the first connection structure 805A and the second connection structure 805B are spaced apart in the first direction N, and are electrically connected through the third connection structure 805C. This allows the first electrode of the second light emission control transistor T5 to be electrically connected to the power signal line 300.
  • This connection method can be flexibly adapted to the current layout arrangement and minimizes wiring congestion with other transistors.
  • the orthographic projection of the first sub-pixel 010 on the base substrate 001, the orthographic projection of the reset power signal line 801 on the base substrate 001, and the orthographic projection of the connection structure 807 on the base substrate 001 are all the same. Overlap, and the overlapping area is substantially symmetrically distributed with respect to the symmetrical center line W1 of the body electrode 1040 of the first sub-pixel 010, which is beneficial to the flatness of the body electrode 1040 to reduce color shift.
  • the orthographic projection of the second pixel 02 on the base substrate 001 also overlaps with the orthographic projection of the reset power signal line 801 on the base substrate 001 and the orthographic projection of the connection structure 807 on the base substrate 001, and
  • the overlapping area is symmetrically distributed with respect to the symmetrical center line W2 of the main body electrode 1050 of the second sub-pixel 020, so that the main body electrode 1050 has good flatness.
  • the orthographic projection of the first connection structure 805A on the base substrate 001 falls into the overlapping area AS2 of the body electrode 1060 of the third sub-pixel 030 and the data line 400, and It is basically symmetrical with respect to the seventh symmetry center line L40, thus ensuring good flatness of the third sub-pixel 030 to reduce the degree of color shift.
  • Another embodiment of the present disclosure provides a display device, including any of the above display substrates.
  • the display device provided by the embodiment of the present disclosure designs the pixel circuit and the matching form of the pixel circuit and the light-emitting element, which is beneficial to enhancing the flatness of the connection electrode of the light-emitting element and reducing color shift and other phenomena in the display product.
  • the display device provided by the embodiment of the present disclosure may be an organic light-emitting diode display device.
  • the display device may further include a cover located on the display side of the display substrate.
  • the display device can be any product or component with a display function such as a mobile phone with an under-screen camera, a tablet computer, a notebook computer, a navigator, etc. This embodiment is not limited thereto.

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Abstract

提供了一种显示基板以及显示装置。显示基板包括位于衬底基板（001）上的多个子像素（10），多条电源信号线（300）沿第一方向延伸且沿第二方向排列；至少部分子像素（10）包括多个第一子像素（010），沿垂直于衬底基板（001）的第三方向，至少一条电源信号线（300）包括第一电源部（301），第一电源部（301）包括第一主体部（31）和第二主体部（32）；在第二方向上，第一子像素（010）的主体电极（1040）的最大尺寸不小于第一电源部（301）的最大尺寸，第一主体部（31）的最大尺寸大于第二主体部（32）的最大尺寸，第一子像素（010）的主体电极（1040）在第二方向上距离最远的两个端点的连线为端点连线，在第三方向上，端点连线与第一主体部（31）交叠。有利于增加发光元件中连接电极的平坦性，减小显示产品发生色偏等现象。

Description

显示基板及显示装置 技术领域
本公开至少一个实施例涉及一种显示基板以及显示装置。
背景技术
目前，有源矩阵有机发光二极管(AMOLED)柔性屏技术日趋成熟，其具有的可弯曲，对比度高，功耗低等特点，由此具有较高的发展前景。随着显示技术的不断发展，优化显示效果已成为必然趋势，为了提高显示器件的性能，一些显示产品通过优化像素中导电结构与发光元件之间的排布形式来减小色偏。
发明内容
本公开至少一个实施例提供一种显示基板以及显示装置。
本公开实施例提供一种显示基板，包括：衬底基板；多个子像素，位于所述衬底基板上，至少部分子像素包括发光元件和像素电路，所述发光元件包括发光功能层以及沿垂直于所述衬底基板的方向位于所述发光功能层两侧的第一电极和第二电极，所述第一电极位于所述发光功能层与所述衬底基板之间，所述发光元件至少部分位于发光区，所述发光元件的第一电极包括与所述发光区交叠的主体电极；多条电源信号线，所述多条电源信号线的至少部分沿第一方向延伸且沿第二方向排列，所述多条电源信号线位于所述衬底基板与所述发光元件的第一电极之间，所述第一方向与所述第二方向相交，其中，所述至少部分子像素包括多个第一子像素，沿垂直于所述衬底基板的第三方向，至少一条电源信号线包括与多个所述第一子像素的至少一个的主体电极交叠的第一电源部，每个所述第一电源部包括第一主体部和第二主体部；在所述第二方向上，所述第一子像素的主体电极的最大尺寸不小于其对应的所述第一电源部的最大尺寸，该第一电源部中的所述第一主体部的最大尺寸大于所述第二主体部的最大尺寸，所述第一子像素的主体电极在所述第二方向上距离最远的两个端点的连线为端点连线，在所述第三方向上，所述端点连线与所述第一主体部交叠。
例如，根据本公开的实施例，所述多条电源信号线包括第一电源信号线和第二电源信号线，所述第一电源信号线和所述第二电源信号线在所述第二 方向上的最大尺寸分别为第一尺寸和第二尺寸，且所述第二尺寸小于所述第一尺寸。
例如，根据本公开的实施例，多个所述第一子像素包括至少一个第一类型子像素，与所述第一类型子像素的主体电极交叠的所述第一电源部为第一类型电源部，所述第一类型电源部的所述第一主体部为非对称结构。
例如，根据本公开的实施例，所述第一类型电源部的所述第一主体部包括第一凸出部，所述第一凸出部位于所述第二主体部的沿所述第一方向延伸的第一对称中心线的一侧。
例如，根据本公开的实施例，所述第一类型电源部除所述第一凸出部以外的部分的对称中心线的延伸方向与所述第一类型子像素的主体电极的第二对称中心线的延伸方向相交。
例如，根据本公开的实施例，多个所述第一子像素还包括至少一个第二类型子像素，与所述第二类型子像素的主体电极交叠的所述第一电源部为第二类型电源部，所述第二类型电源部包括沿所述第一方向延伸的第三对称中心线，所述第二类型子像素的所述主体电极包括沿所述第一方向延伸的第四对称中心线，同一列所述电源信号线中的所述第二类型电源部的所述第三对称中心线和与该第二类型电源部交叠的所述第二类型子像素的所述第四对称中心线位于垂直于所述衬底基板的同一平面内。
例如，根据本公开的实施例，所述第一子像素的主体电极包括相对的第一角部和第二角部，以及相对的第三角部和第四角部，所述第一角部和所述第二角部至少之一在所述衬底基板上的正投影与所述第一对称中心线在所述衬底基板上的正投影至少部分交叠，所述第四角部在所述衬底基板上的正投影与所述第一凸出部在所述衬底基板上的正投影至少部分交叠。
例如，根据本公开的实施例，所述第二类型电源部的第一主体部包括第二凸出部和第三凸出部，所述第二凸出部和所述第三凸出部相对于所述第三对称中心线对称分布，所述第二类型子像素的主体电极包括相对的第一角部和第二角部，以及相对的第三角部和第四角部，所述第二凸出部在所述衬底基板上的正投影与所述第一角部和所述第二角部之一在所述衬底基板上的正投影至少部分交叠，所述第三凸出部在所述衬底基板上的正投影与所述第一角部和所述第二角部另一者在所述衬底基板上的正投影至少部分交叠。
例如，根据本公开的实施例，沿所述第三方向，所述第二类型子像素的 发光区与所述第二凸出部和所述第三凸出部的至少之一交叠。
例如，根据本公开的实施例，在所述第二方向上，所述第二类型电源部的第一主体部的最大尺寸大于所述第一类型电源部的第一主体部的最大尺寸，所述第一类型电源部的第二主体部的最大尺寸与所述第二类型电源部的第二主体部的最大尺寸之比为0.9～1.1。
例如，根据本公开的实施例，所述第二类型电源部的第一主体部在所述第二方向上的最大尺寸是所述第二类型电源部的第二主体部在所述第二方向上的最大尺寸的1.1-2倍。
例如，根据本公开的实施例，相邻的多条电源信号线中的每条电源信号线均包括沿所述第一方向排列的多个电源部，相邻两个电源部之间设置有与所述相邻两个电源部均电连接的第一连接部，多个所述电源部包括所述第一电源部，所述电源部在所述第二方向上的最大尺寸与所述第一连接部在所述第二方向上的最大尺寸之比为1.5-5。
例如，根据本公开的实施例，所述第一类型电源部包括第一子类型电源部和所述第二子类型电源部，所述第一类型电源部的所述第二主体部包括在所述第二方向上相对的第一侧和第二侧，所述第一子类型电源部中所述第一凸出部设置在所述第二主体部的第一侧，所述第二子类型电源部中所述第一凸出部设置在所述第二主体部的第二侧。
例如，根据本公开的实施例，所述第一子像素的主体电极包括多个角部，多个所述角部包括所述第一角部、所述第二角部、所述第三角部和所述第四角部，所述主体电极的每条边或其延长线依次连接形成多边形，且所述多边形的多个顶角存在与对应的主体电极的多个角部不交叠的区域；所述第三角部和与其对应的所述多边形的顶角不交叠的区域面积大于至少部分其他角部中各角部和与该角部对应的多边形的顶角不交叠的区域面积。
例如，根据本公开的实施例，所述至少部分子像素还包括多个第二子像素，沿所述第三方向，所述至少一条电源信号线包括与多个所述第二子像素的至少一个的主体电极交叠的第二电源部，所述第二电源部包括沿所述第一方向延伸的第五对称中心线，所述第二子像素的所述主体电极包括沿所述第一方向延伸的第六对称中心线，同一列所述电源信号线中的所述第二电源部的所述第五对称中心线和与该第二电源部交叠的所述第二子像素的所述第六对称中心线位于垂直于所述衬底基板的同一平面内。
例如，根据本公开的实施例，所述第二子像素的主体电极在所述衬底基板上的正投影与所述第二电源部在所述衬底基板上的正投影交叠，并且交叠面积至少为所述第二子像素的主体电极在所述衬底基板上的正投影面积的90％。
例如，根据本公开的实施例，在所述第二方向上，所述第二电源部的最大尺寸小于所述第一电源部的所述第一主体部的最大尺寸，且所述第二电源部的最大尺寸与所述第一电源部的所述第二主体部的最大尺寸之比为0.9～1.1。
例如，根据本公开的实施例，显示基板还包括：多条数据线，沿所述第一方向延伸且沿所述第二方向排列，所述多条数据线与所述多条电源信号线同层设置，其中，相邻两条电源信号线之间设置的所述数据线包括沿所述第二方向排列的第一数据线和第二数据线，所述第一数据线和第二数据线相对于所述第一数据线和第二数据线之间的第七对称中心线对称分布；所述至少部分子像素还包括多个第三子像素，多个所述第三子像素至少一个的发光元件的主体电极与所述数据线至少部分交叠，且所述第三子像素的主体电极与所述数据线的交叠区相对于所述第七对称中心线基本对称。
例如，根据本公开的实施例，显示基板还包括：多个第二连接部，与至少部分所述多条电源信号线同层设置，每个第二连接部包括第一连接件和第二连接件，多个所述第二连接部沿所述第一方向和所述第二方向阵列排布以形成多个第二连接部行和多个第二连接部列，所述电源信号线包括沿所述第一方向排列的多个电源部，相邻两个电源部之间设置有与所述相邻两个电源部均电连接的第一连接部，所述多条电源信号线包括的所述电源部沿所述第一方向和所述第二方向阵列排布以形成多个电源部行和多个电源部列，多个所述第二连接部行和多个所述电源部行在所述第一方向上交替排布，同一第二连接部行中相邻两个第二连接部分布在所述数据线两侧。
例如，根据本公开的实施例，所述发光元件的所述连接电极与所述第一连接部基本无交叠；在所述第一方向上，所述第一子像素的主体电极的最大尺寸不小于其对应的所述第一电源部中所述第一主体部的最大尺寸。
例如，根据本公开的实施例，所述第一连接件与所述第一子像素的连接电极或所述第二子像素的连接电极电连接，所述第二连接件与所述第三子像素的连接电极电连接。
例如，根据本公开的实施例，所述第一连接部包括至少一个挖孔部，所述挖孔部的面积为所述第一连接部的面积的1/4-1/3。
本公开实施例提供一种显示装置，包括上述任一显示基板。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1A为一种显示基板的局部截面结构示意图。
图1B为另一种显示基板的局部截面结构示意图。
图2A为一种显示基板中像素排布与导电层交叠关系的示意图。
图2B为另一种显示基板中像素排布与导电层交叠关系的示意图。
图3为本公开一实施例提供的一种显示基板中像素排布结构的示意图。
图4为沿图3所示AA’线所截的局部截面结构示意图。
图5为本公开一实施例提供的一种显示基板中第二导电层和发光元件的第一电极的叠层结构示意图。
图6为本公开一实施例提供的一种显示基板中第二导电层的局部结构示意图。
图7为本公开一实施例提供的一种显示基板中发光元件的第一电极的局部结构示意图。
图8为根据本公开实施例提供的像素电路的等效图。
图9为根据本公开实施例提供的像素电路中的遮光层、有源半导体图案、第一连接层的叠层结构示意图。
图10为根据本公开实施例提供的像素电路中的遮光层、有源半导体图案、第一连接层、第二连接层、半导体层以及第三连接层的叠层结构示意图。
图11为根据本公开实施例提供的第一导电层的局部结构示意图。
图12为根据本公开实施例提供的像素电路中的遮光层、有源半导体图案、第一连接层、第二连接层、半导体层、第三连接层以及第一导电层的叠层结构示意图。
图13为根据本公开实施例提供的第一导电层和第二导电层的叠层结构示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其它实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。
本公开实施例中使用的“垂直”、“平行”以及“相同”等特征均包括严格意义的“垂直”、“平行”、“相同”等特征，以及“大致垂直”、“大致平行”、“大致相同”等包含一定误差的情况，考虑到测量和与特定量的测量相关的误差(也就是，测量系统的限制)，表示在本领域的普通技术人员所确定的对于特定值的可接受的偏差范围内。本公开实施例中的“中心”可以包括严格的位于几何中心的位置以及位于几何中心周围一小区域内的大致中心的位置。例如，“大致”能够表示在一个或多个标准偏差内，或者在所述值的10％或者5％内。
有机发光二极管显示产品的性能规格可以包括功耗、亮度、色偏等。有机发光二极管显示产品包括的背板对色偏的影响因素可以包括阳极的平坦度。针对发光元件中阳极的平坦性进行优化设计，可以防止发光元件出射光线的偏移，进而减小显示产品发生色偏等现象。
图1A为一种显示基板的局部截面结构示意图。如图1A所示，显示基板包括膜层91，膜层91包括衬底基板、位于衬底基板上的有源半导体层、位于有源半导体层远离衬底基板一侧的至少一层连接层。显示基板还包括位于膜层91上的导电层11，例如导电层11可以包括数据线、电源信号线等走线。显示基板还包括位于导电层11远离膜层91一侧的平坦层12、位于平坦层12远离导电层11的一侧的阳极13以及位于阳极13远离平坦层12一侧的像素 限定层14。像素限定层14包括用于限定子像素的发光区的多个开口15-17。多个开口15-17暴露部分阳极13，当后续的有机发光层形成在上述像素限定层14的开口15-17中时，有机发光层与阳极13接触，从而这部分能够驱动有机发光层进行发光。
例如，在显示基板中，导电层11的设置可能会对发光元件的出光效果产生较大影响，例如可能破坏发光元件中的阳极平坦性，进而致使发光元件的产生色偏。
如图1A所示，导电层11的厚度较大，例如厚度可以为0.6-0.9um，会导致位于导电层11上的平坦层12的面向阳极13的表面不平坦。例如，位于导电层11(例如数据线、电源信号线及与其同层同材料的图案)正上方的平坦层12的远离膜层91的表面与膜层91的远离平坦层12的表面之间的距离为h1，未设置导电层11的区域正上方位置处的平坦层12的远离膜层91的表面与膜层91的远离平坦层12的表面之间的距离为h2，h1>h2。
如图1A所示，在开口16内，平坦层12中的一部分的正下方设置有导电层11，另一部分的正下方未设置导电层11，由此开口16内的平坦层12面向阳极13的表面是不平坦的，导致位于平坦层12上的阳极13的表面也不平坦。例如，对于位于开口16内的阳极13，位于导电层11正上方的阳极13的远离膜层91的表面与膜层91的远离阳极13的表面之间的距离为h3，未设置导电层11位置处的阳极13的远离膜层91的表面与膜层91的远离阳极13的表面之间的距离为h4，h3>h4。由此，开口16内的阳极13发生了“倾斜”。同理，开口15内的阳极13也会发生“倾斜”，且根据导电层11的位置的区别，开口15内的阳极13的“倾斜方向”与开口16内的阳极13的“倾斜方向”不同，从而导致开口15和开口16对应的子像素向不同方向发光的强度不一致。例如，以X方向的箭头所指的方向为右，则开口15和开口16限定的子像素发光区向左右两侧发出的光强度不一致。位于开口17内的阳极13正下方未设置导电层11，因此开口17内的阳极13的表面是基本平坦的，没有发生“倾斜”，开口17限定的子像素发光区向不同方向发光的强度一致。对于开口15-17限定的相邻三个不同颜色的子像素的发光区，开口15内的阳极13向左侧“倾斜”，开口16内的阳极13向右侧“倾斜”，开口17内的阳极13不倾斜，由此，不同颜色子像素的阳极13的“倾斜”方向不同，导致三个子像素的发光区向左右两侧发出的光强度不匹配。采用这样的显示基板的显示装置会发生 大视角色偏，人眼观看时，出现类似一侧发红，另一侧发青的色偏现象。
图1B为另一种显示基板的局部截面结构示意图。图1B所示的显示基板包括图1A所示的膜层91、导电层11、平坦层12、阳极13以及像素限定层14。如图1B所示，显示基板中的平坦层12包括过孔18以使阳极13可以与导电层11实现电连接。像素限定层14包括开口19以暴露部分阳极13，当后续的有机发光层形成在开口19中时，有机发光层与阳极13接触以形成发光区。
如图1B所示，过孔18位于发光区以外，由于位于过孔18周边的阳极13发生倾斜，发光区与过孔18之间应设置一定距离以保证发光区内的阳极13的平坦性，从而避免显示基板发生色偏现象。
参考图1A-图1B，导电层11与阳极13的位置关系、平坦层12中设置的过孔18与阳极13的位置关系都会影响发光区内阳极13的平坦性，从而导致显示基板容易发生色偏现象。
图2A是一种显示基板中像素排布与导电层交叠关系的示意图；图2B是另一种显示基板中像素排布与导电层交叠关系的示意图；图2C是一种显示基板中的一种子像素与导电层交叠关系的示意图。
为了图示清晰，图2A和图2B示出了像素电路中发光元件的阳极以及与之进行连接的导电层之间的匹配关系。参考图2A和图2B，导电层中包括多个导电部件，沿垂直于显示基板的衬底基板的方向，发光元件的阳极与导电层中的导电部件至少部分交叠。显示基板中包括多个子像素，如被配置为发出蓝光的蓝色子像素01，被配置为发出红光的红色子像素02、以及被配置为发出绿光的绿色子像素03，其中被配置为发出绿光的绿色子像素03包括第一绿色子像素031和第二绿色子像素032。每个子像素的发光元件包括发光区，例如，发光区可以根据像素限定层中的多个开口进行限定。
如图2A所示，对应于每个子像素的发光区可以参考虚线所示出的范围。对于被配置为发出蓝光的蓝色子像素01，其发光区包括交叠区0110和非交叠区0111，且非交叠区0111的面积大于交叠区0110的面积，结合图1A中的显示基板可知，交叠区0110中位于导电层正上方的阳极的远离衬底基板的膜层(图中未示出)的表面与衬底基板的远离阳极的表面之间的距离对应于h3，非交叠区0111中，位于导电层正上方的阳极的远离基板的膜层的表面与基板膜层的远离阳极的表面之间的距离对应于h4，h3>h4。由此，蓝色子像素01 的发光区内的阳极13将发生“倾斜”。同时，非交叠区0111相对于交叠区0110的分布无对称性。
例如，在本公开的一些实施例中，当发光区内的非交叠区相对于交叠区对称分布时，发光区内的阳极将发生“对称倾斜”，即在发光区内，由于非交叠区和非交叠区的所导致的光线倾斜方向对称。此时，相对于图2A中由于非交叠区0111与交叠区0110的非对称性排布而导致的仅朝向一侧的“倾斜”，非交叠区相对于交叠区对称分布时子像素的色偏程度将得到一定弱化。
如图2B所示，显示基板中包括多个子像素，如被配置为发出蓝光的蓝色子像素04，被配置为发出红光的红色子像素05、以及被配置为发出绿光的绿色子像素06，其中被配置为发出绿光的绿色子像素06包括第一绿色子像素0061和第二绿色子像素0062。相比于图2A，与如图2B中的子像素04和子像素05的发光区域内的阳极交叠的导电层需具有较好的平坦性。子像素0062或子像素0061中的发光区域内的阳极与导电层的非交叠区相对于交叠区具有一定的对称性。因此，图2B中的显示基板的色偏程度相对较弱。
由此，在像素电路中，与子像素的发光元件的发光区域内的阳极交叠的导电层需保证一定的平坦性，以防止子像素的发光区内的阳极发生“倾斜”。同时，当由于实际构图需求而导致非交叠区产生时，非交叠区相对于交叠区分布时的对称性状态也将对发光效果产生影响。
本公开实施例提供一种显示基板以及显示装置。显示基板包括衬底基板、多个子像素以及多条电源信号线。多个子像素位于衬底基板上，至少部分子像素包括发光元件和像素电路，发光元件包括发光功能层以及沿垂直于衬底基板的方向位于发光功能层两侧的第一电极和第二电极，第一电极位于发光功能层与衬底基板之间，发光元件至少部分位于发光区，发光元件的第一电极包括与发光区交叠的主体电极；多条电源信号线的至少部分沿第一方向延伸且沿第二方向排列，多条电源信号线位于衬底基板与发光元件的第一电极之间，第一方向与第二方向相交，其中，至少部分子像素包括多个第一子像素，沿垂直于衬底基板的第三方向，至少一条电源信号线包括与多个第一子像素的至少一个的主体电极交叠的第一电源部，每个第一电源部包括第一主体部和第二主体部；在第二方向上，第一子像素的主体电极的最大尺寸不小于其对应的第一电源部的最大尺寸，该第一电源部中的第一主体部的最大尺寸大于第二主体部的最大尺寸，第一子像素的主体电极在第二方向上距离最 远的两个端点的连线为端点连线，在第三方向上，端点连线与第一主体部交叠。本公开实施例对像素电路与发光元件的匹配形式进行设计，有利于提高与发光元件交叠的导电层的部分的平坦性，降低显示产品发生色偏等现象的概率。
下面结合附图对本公开实施例提供的显示基板以及显示装置进行描述。
图3是本公开一实施例提供的一种显示基板中像素排布结构的示意图；图4是沿图3所示AA’线所截的局部截面结构示意图；图5是本公开一实施例提供的一种显示基板中第二导电层和发光元件的第一电极的叠层结构示意图；图6是本公开一实施例提供的一种显示基板中第二导电层的局部结构示意图；图7是本公开一实施例提供的一种显示基板中发光元件的第一电极的局部结构示意图。
参考图3和图4，显示基板包括衬底基板001和多个子像素10，多个子像素10位于衬底基板001上，至少部分子像素10包括发光元件100和像素电路200(参见图13)。例如，像素电路200被配置为驱动发光元件100发光。发光元件100包括发光功能层101以及沿垂直于衬底基板001的方向Z位于发光功能层101两侧的第一电极102和第二电极1022，第一电极102位于发光功能层101与衬底基板001之间。
参考图3和图4，发光元件100的第一电极102远离第二电极1022的一侧设置有结构层1004，结构层1004例如可以包括衬底基板、有源半导体图案所在层、栅线所在膜层、数据线所在膜层以及多个绝缘层等膜层。显示基板还包括像素限定图案150，像素限定图案150位于发光元件100的第一电极102远离衬底基板001的一侧，且像素限定图案150包括多个开口160以及围绕多个开口160的限定部170，多个发光元件100至少部分位于多个开口160中。
例如，限定部170可以限定开口160的大小。例如，限定部170的材料可以包括聚酰亚胺、亚克力或聚对苯二甲酸乙二醇酯等。
参考图3和图4，像素电路200包括发光控制晶体管T6(参见图8)，发光元件100的第一电极102与发光控制晶体管T6电连接。
例如，发光元件100至少部分位于发光区103，发光元件100的第一电极102包括与发光区103交叠的主体电极104。发光元件100的位于开口160中的部分为发光区103，发光区103在衬底基板001上的正投影面积被主体电极 104在衬底基板上的正投影包围。例如，主体电极104可以为第一电极102中除去连接电极(参见下文描述)的部分。在本公开的一些实施例中，第一电极102中除去连接电极以及主体电极的电极部分还包括凸出电极(图中未示出)，例如，凸出电极相对于第一电极102的主体电极凸出。例如，凸出电极可以被配置为对像素电路200中的部分结构进行遮挡。例如，凸出电极也可以被配置为与像素电路200中的一些导电结构形成电容。
例如，主体电极104的形状可以与像素限定图案150的开口160的形状相同；例如，主体电极104的形状也可以与像素限定图案150的开口160的形状不相同，本公开的实施例对此不作限制。例如，主体电极104的可以为多边形。例如，多边形的主体电极104中的顶角可以是倒角。例如，主体电极104的边界可以是由主体电极104中的凸出电极的边线从凸出电极的两端经过平滑过渡而连接形成。例如，主体电极104中可以包括多个凸出电极。
例如，像素限定图案150的开口160被配置为限定发光元件100的发光区103。例如，多个子像素10的发光元件100可以与多个开口160一一对应设置。例如，发光元件100可以包括位于开口160中的部分，以及在垂直于衬底基板001的方向与限定部170交叠的部分。例如，发光元件100在衬底基板001上的正投影面积可以大于开口160的开口区域在衬底基板001上的正投影面积。
例如，像素限定图案150的开口160被配置为暴露发光元件100的第一电极102，暴露的第一电极102至少部分与发光元件100中的发光功能层101接触。例如，第一电极102的至少部分位于限定部170与衬底基板001之间。例如，当发光功能层101位于像素限定图案150的开口160中时，位于发光功能层101两侧的第一电极102和第二电极1022能够驱动像素限定图案150的开口160中的发光功能层101进行发光。
例如，第一电极102可以为阳极，第二电极1022可以为阴极。例如，阴极可由高导电性和低功函数的材料形成，例如，阴极可采用金属材料制成。例如，阳极可由具有高功函数的导电材料形成。
例如，上述发光区103可以指发光元件100的有效发光的区域，发光区103的形状指二维形状，例如发光区103的形状可以与像素限定图案150的开口160的形状相同。例如，像素限定图案150的开口160可以为靠近衬底基板001一侧尺寸小，远离衬底基板001一侧尺寸大的形状。例如，发光区103 的形状可以与像素限定图案150的开口160靠近衬底基板001一侧的大小和形状大致相同。
参考图3、图4和图6，显示基板还包括多条电源信号线300，多条电源信号线300的至少部分沿第一方向N延伸且沿第二方向Y排列，多条电源信号线300位于衬底基板001与发光元件100的第一电极102之间，第一方向N与第二方向Y相交。例如，第一方向N可以与第二方向Y垂直。
例如，像素电路200还包括发光控制晶体管T5(如图8所示)，发光控制晶体管T5与电源信号线300电连接。例如，多条电源信号线300可以设置在同一导电层中，被配置为向像素电路提供电源信号。
参考图3-图6，至少部分子像素10包括多个第一子像素010，沿垂直于衬底基板001的第三方向Z，至少一条电源信号线300包括与多个第一子像素010的至少一个的主体电极1040交叠的第一电源部301。
例如，如图3所示，第一子像素010可以是配置为发出蓝光的蓝色子像素。第一子像素010可以包括不同类型的第一子像素，图3中示出的各类第一子像素010包括了4中不同的设置方式。在本公开的一些实施例中，也可以根据实际版图的设计需求采用多种排布方式，本公开的实施例对此不作限制。
例如，参考图3-图5，第一子像素010中的主体电极1040设置在第一电源部301远离衬底基板001的一侧，且对应于每个主体电极1040，第一电源部301与主体电极1040至少部分交叠。
参考图3-图5，每个第一电源部301包括第一主体部31和第二主体部32，在第二方向Y上，第一子像素010的主体电极1040的最大尺寸M1不小于其对应的第一电源部301的最大尺寸L1，该第一电源部301中的第一主体部31的最大尺寸L11大于第二主体部32的最大尺寸L12。例如，第一子像素010的主体电极1040的对应的第一电源部301是指与第一子像素010的主体电极1040交叠的第一电源部301。
参考图3-图5，第一子像素010的主体电极1040在第二方向Y上距离最远的两个端点A1、A2的连线为端点连线L2，在第三方向Z上，端点连线L2与第一主体部31交叠。
例如，参考图3-图5，第一主体部31和第二主体部32分别为第一电源部301上相邻的两部分，并且在第二方向Y上，该第一电源部301的主体电极 1040中的第一主体部31的最大尺寸L11大于第二主体部32的最大尺寸L12，第一主体部31在衬底基板001上的正投影面积大于第二主体部32在衬底基板001上的正投影面积。通过将主体电极1040的端点连线L2与第一主体部31交叠，可以使得主体电极1040中面积较大的部分与第一主体部31交叠，进而保证了主体电极1040与第一电源部301的具有较大的交叠面积。例如，主体电极1040上的端点连线L2的延伸方向可以根据主体电极1040的排布方向而定。例如，端点连线L2可以沿第一方向N延伸；例如，端点连线L2也可以是沿第二方向Y延伸的，本公开的实施例对此不作限制。
例如，第一主体部31和第二主体部32为一体化的结构。
例如，在第二方向Y上，本实施例中第一电源部301的最大尺寸L1与第一主体部31的最大尺寸L11相等，当第一子像素010的主体电极1040的最大尺寸M1不小于第一电源部301的最大尺寸L1时，可以使第一子像素010的主体电极1040在衬底基板001上的正投影尽量覆盖第一电源部301在衬底基板001上的正投影，由此可增强主体电极1040中对应于发光区103的平坦度。
例如，第一电源部301上还可以包括除第一主体部31和第二主体部32之外的部分，本公开的实施例对此不作限定。
本公开实施例通过对像素电路与发光元件的匹配形式进行设计，有利于提高发光元件中第一电极的平坦性，降低显示产品发生色偏等现象的概率。
例如，参考图4-图6，多条电源信号线300包括第一电源信号线300-1和第二电源信号线300-2，第一电源信号线300-1和第二电源信号线300-2在所述第二方向Y上的最大尺寸分别为第一尺寸Lm和第二尺寸Ln，且第二尺寸Ln小于第一尺寸Lm。本公开实施例提供的多条电源信号线在第二方向Y上的最大尺寸不完全相同，可以根据第一子像素010的第一电极102的形状以及排布进行设置，以提高第一子像素010中第一电极102的平坦性。
例如，在本公开的实施例提供的多条电源信号线中，第一电源部301的形状和排布可以根据第一子像素010的类型进行选取。例如，显示基板可以包括在第二方向上具有不同尺寸的第一电源部301，例如，包括在第二方向上具有最大尺寸不同的第一电源部301，以分别对应于在第二方向上具有较小尺寸或较小尺寸的主体电极1040的第一子像素010，以适应实际构图的需要，同时也可以使得第一子像素010的主体电极1040具有良好的平坦性，减小显 示基板发生色偏的风险。
例如，在本公开的实施例中，在第二方向Y上具有不同尺寸的第一电源部301不限于两种，可以根据实际的设计需求进行设定，对此不作限定。
例如，参考图3、图5和图6，显示基板中的多个第一子像素010可以包括至少一个第一类型子像素111，与第一类型子像素111的主体电极1041交叠的第一电源部301为第一类型电源部3010。例如，第一类型子像素111的主体电极1041与第一类型电源部3010的第一主体部311的交叠区可以是非对称区。
例如，第一类型电源部3010的第一主体部311为非对称结构。例如，第一类型电源部3010中与第一类型子像素111的主体电极1041交叠的区域为非对称区域。本公开实施例中的“非对称”可以指该结构或者区域在平行于衬底基板的任意方向上均不是对称设置的。
例如，参考图3和图5，第一类型子像素111的主体电极1041与第一类型电源部3010具有较大的交叠区，并且交叠区整体上是非对称的。例如，交叠区在衬底基板001上的正投影面积可以为主体电极1041在衬底基板001上的正投影面积的60％～95％，第一子像素111的发光区103在衬底基板上的正投影位于主体电极1041在衬底基板上的正投影的内部，此时，交叠区与发光区103几乎是重合的，也即与发光区103交叠的部分主体电极1041是均匀而平坦地设置的，由此可以提高该第一类型子像素111的发光强度的均匀性，减小色偏的发生概率。例如，交叠区在衬底基板001上的正投影面积可以为主体电极1041在衬底基板001上的正投影面积的65％～90％，或者70％～85％，或者75％～80％等。
例如，如图6所示，显示基板中的第一类型电源部3010的第一主体部311可以包括第一凸出部313，第一凸出部313位于第二主体部312的沿第一方向N延伸的第一对称中心线L3的一侧。
例如，参考图5和图6，显示基板中第一类型电源部3010除第一凸出部313以外的部分的对称中心线L4的延伸方向与第一类型子像素111的主体电极1041的第二对称中心线L5的延伸方向相交。
例如，第一对称中心线L3与对称中心线L4可以重合。当然，本公开的实施例不限于此，两者也可以间隔分布。
例如，参考图3-图6，第一类型电源部3010的第二主体部312相对于第 一对称中心线L3对称分布。当不设置第一凸出部313时，第一主体部311在第二方向上的最大尺寸与第二主体部312是相同的，并且第一类型电源部3010也相对于第一对称中心线L3对称分布。为尽量匹配第一类型子像素111的主体电极1041的设置形态，第一凸出部313可以仅设置在第一主体部311的相对于第一对称中心线L3的一侧，这样第一凸出部313的设置可以增加主体电极1041与第一类型电源部3010的交叠区，可以更好地使覆盖其上的主体电极1041趋于平坦，由此可以增加主体电极1041的平坦度。
例如，第一类型电源部3010中的主体电极1041的设置形态可具有多样性。例如，参考图3和图5，主体电极1041相对于第二对称中心线L5基本为对称分布。例如，本实施例中将对称中心线L4与第二对称中心线L5垂直设置，可以使得第一类型电源部3010与主体电极1041的交叠面积尽量最大化，同时也可以使得主体电极1041上凸出的角部覆盖在第一类型电源部3010的第一凸出部313上，由此主体电极1041的平坦性程度得到了提升。
例如，对称中心线L4与第二对称中心线L5的延伸方向的夹角可以为20～90度，如30～80度，如45～60度等。
例如，参考图3、图5和图6，显示基板中的多个第一子像素010还包括至少一个第二类型子像素112，与第二类型子像素112的主体电极1042交叠的第一电源部301为第二类型电源部3011。
例如，参考图3、图5和图6，第二类型电源部3011包括沿第一方向N延伸的第三对称中心线L6，第二类型子像素112的主体电极1042包括沿第二方向N延伸的第四对称中心线L7，同一列电源信号线中的第二类型电源部3011的第三对称中心线L6和与该第二类型电源部3011交叠的第二类型子像素112的第四对称中心线L7位于垂直于衬底基板001的同一平面内。例如，第三对称中心线L6在衬底基板上的正投影与第四对称中心线L7在衬底基板上的正投影重合。
例如，参考图3、图5和图6，第二类型子像素112设置在第二类型电源部3011远离衬底基板的一侧，并且第二类型电源部3011相对于第二对称中心线呈对称分布。例如，根据第一子像素010在显示基板中的设置形态的不同，第二类型子像素112的主体电极1042可以认为是在将第一类型子像素111的主体电极1041顺时针或者逆时针旋转一定角度而得到。本实施例中的旋转角度为90°，因此，第二类型子像素112的主体电极1042的第四对称中心线 L7也相对于第一类型子像素111的主体电极1041顺时针或者逆时针旋转。第二类型子像素112的主体电极1042设置在第二类型电源部3011远离衬底基板的一侧，因此，第二类型电源部3011的第三对称中心线L6和与该第二类型电源部3011交叠的第二类型子像素112的第四对称中心线L7是平行的，并且均位于垂直于衬底基板001的同一平面内。例如，当同一列电源信号线300中对应于多个第二类型子像素112时，同一列电源信号线300中的多个第二类型电源部3011的多条第三对称中心线L6和与多个第二类型电源部3011交叠的多个第二类型子像素112的多条第四对称中心线L7均位于垂直于衬底基板001的同一平面内。
例如，参考图3、图5、图6和图7，第一子像素010的主体电极1040包括相对的第一角部141和第二角部142，以及相对的第三角部143和第四角部144，第一角部141和第二角部142至少之一在衬底基板001上的正投影与第一对称中心线L3在衬底基板001上的正投影至少部分交叠，第四角部144在衬底基板001上的正投影与第一凸出部313在衬底基板001上的正投影至少部分交叠。
例如，参考图3、图5、图6和图7，构成第一角部141、第二角部142、第三角部143和第四角部144的延长线使得主体电极1040近似呈四边形。对于第一类型子像素111的主体电极1041，第一角部141和第二角部142相对设置，并且第一角部141的顶点指向第二角部142的顶点的指向方向与第二对称中心线L5的延伸方向相交，例如，在本实施例中为垂直关系。
例如，第一角部141、第二角部142、第三角部143和第四角部144中的至少之一可以是由角部顶点的两侧的延长线延伸1～5微米而形成，例如，由角部顶点的两侧延长线的延伸长度可以是主体电极1040中相邻两个角部之间的边线长度的1/10。例如，当第一角部141、第二角部142、第三角部143和第四角部144中的至少之一的顶角为圆角时，则对应的角部可以由圆角的顶角两侧的弧线延伸1～5微米后形成。例如，第一角部141、第二角部142、第三角部143和第四角部144中的至少之一的角度的范围可以为70°～150°；例如第一角部141、第二角部142、第三角部143和第四角部144中的至少之一的角度的范围可以为80°～120°；第一角部141、第二角部142、第三角部143和第四角部144中的至少之一的角度的范围可以为90°～100°。
例如，将第一类型子像素111的主体电极1041设置于第一类型电源部 3010远离衬底基板001的一侧时，第一角部141的顶点指向第二角部142的顶点的指向方向与第一类型电源部3010的对称中心线L4的延伸方向是相同的，第三角部143的顶点指向第四角部144的顶点的指向方向与第二对称中心线L5基本重合。此时，如图5所示，第一凸出部313在衬底基板001上的正投影落入第四角部144在衬底基板001上的正投影中，使得第一类型电源部3010与主体电极1041的交叠面积最大化，提高了主体电极1041的平坦度。
例如，参考图3、图5、图6和图7，第二类型电源部3011的第一主体部314包括第二凸出部317和第三凸出部318，且第二凸出部317和第三凸出部318相对于第三对称中心线L6对称分布。
例如，参考图3、图5、图6和图7，第二类型子像素112的主体电极1042包括相对的第一角部141和第二角部142，以及相对的第三角部143和第四角部144，第二凸出部317在衬底基板001上的正投影与第一角部141和第二角部142之一在衬底基板001上的正投影至少部分交叠，第三凸出部318在衬底基板001上的正投影与第一角部141和第二角部142另一者在衬底基板001上的正投影至少部分交叠。
例如，参考图3、图5、图6和图7，第二类型子像素112的设置形态与第一类型子像素111不同，第二类型子像素112的主体电极1042相对于第一类型子像素111的主体电极1041逆时针旋转了90°。例如，第三角部143的顶点指向第四角部144的顶点的指向方向与第三对称中心线L6基本是重合的，因此，第二类型子像素112基于第二类型电源部3011可以包括两种设置形式，如使得第二凸出部317在衬底基板001上的正投影与第一角部141交叠，第三凸出部318在衬底基板001上的正投影与第二角部142在衬底基板001上的正投影交叠；或使得第二凸出部317在衬底基板001上的正投影与第二角部142交叠，第三凸出部318在衬底基板001上的正投影与第一角部141在衬底基板001上的正投影交叠。按照上述两种设置方式，相邻的两个第二类型子像素112中第三角部143的顶点指向第四角部144的顶点的指向方向是相反的，此时，第二类型电源部3011中的第二凸出部317和第三凸出部318在衬底基板001上的正投影落入主体电极1042在衬底基板001上的正投影，由此提高了主体电极1042的平坦性程度。上述“相邻的两个第二类型子像素”可以指在平行于衬底基板的一个方向上，这两个第二类型子像素之间没有设置其他第二类型子像素，但可以设置其他类型子像素。
例如，参考图3、图5和图6，以图5所示N方向的箭头所指的方向为向下，第二类型子像素112可以包括第三角部143位于第四角部144上方的第一种子像素和第三角部143位于第四角部144下方的第二种子像素，第一种子像素中的第三角部143的至少部分与第二类型电源部3011的第一主体部314交叠，第二种子像素中的第三角部143的至少部分与第二类型电源部3011的第二主体部315交叠。例如，各子像素的第一电极102还包括与像素电路200电连接的连接电极(参见下文描述)，第一种子像素中的第三角部143比第四角部144更靠近连接电极，第二种子像素中的第四角部144比第三角部143更靠近连接电极。
例如，在本公开的实施例中，参考图3-图6，沿第三方向Z，第二类型子像素112的发光区1032与第二凸出部317和第三凸出部318的至少之一交叠。发光区1032限定了第二类型子像素112的出光范围，当第二类型子像素112基于第二类型电源部3011按照上述两种设置形式设置时，第二凸出部317和第三凸出部318在衬底基板001上的正投影落入或与主体电极1042的发光区1032在衬底基板001上的正投影部分交叠，此时保证可以增强对应于发光区1032的主体电极1042的平坦性，从而可防止色偏。
例如，参考图3和图6，根据第一子像素111的设置形式的不同，第一类型电源部3010与第二类型子像素3011的形状设计也是相应不同的。
例如，在第二方向Y上，第二类型电源部3011的第一主体部314的最大尺寸L13是大于第一类型电源部3010的第一主体部311的最大尺寸L11的，且第一类型电源部3010的第二主体部312的最大尺寸L12与第二类型电源部3011的第二主体部315的最大尺寸L13之比为0.9～1.1。例如，第一类型电源部3010的第二主体部312的最大尺寸L12与第二类型电源部3011的第二主体部315的最大尺寸L13相等。
例如，参考图5和图6，第二类型子像素112的主体电极1042相对于第一类型子像素111的主体电极1041按照顺时针或逆时针旋转了90°，第一子像素010的主体电极1042具有对称结构，例如，第二类型子像素112的主体电极1042相对于第四对称中心线L7对称分布，并且第二类型电源部3011的相对于第二对称中心点L6对称分布，第三对称中心线L6与第四对称中心线L7是平行的，并且均位于垂直于衬底基板001的同一平面内。
例如，第一角部141的顶点与第二角部142的顶点之间的连线距离小于 第三角部143的顶点与第四角部144的顶点之间的连线距离。第一角部141和第二角部142分布在主体电极1042的第四对称中心线L7两侧，并且在第二类型电源部3011的远离衬底基板001的一侧，第一角部141和第二角部142分别对应于第二凸出部317和第三凸出部318。在第一类型电源部3010的远离衬底基板001的一侧，第四角部144对应于第一类型电源部3010的第一凸出部313。因此，第二类型电源部3011的第一主体部314的最大尺寸L13大于第一类型电源部3010的第一主体部311的最大尺寸L11。
例如，如图5所示，第一类型子像素111的主体电极1041包括位于端点连线L2两侧的两个部分，且在这两个部分的至少之一中，沿平行于第一方向N且逐渐远离该端点连线L2的方向，主体电极1041在第二方向Y上的最大尺寸逐渐减小。
例如，第一类型电源部3010的第二主体部312对应于主体电极1041的最大尺寸逐渐减小的部分，因此，第二主体部312上无需增加其他凸出结构来提高对应于该部分的主体电极1041的平坦性，第二主体部312在第二方向Y上的最大尺寸小于第一主体部311在第二方向Y上的最大尺寸。
同理，对于第二类型子像素112，第二类型电源部3011的第二主体部315在第二方向Y上的最大尺寸L14也是小于第一主体部314在第二方向Y上的最大尺寸L13的。
在本公开的一些实施例中，第一类型子像素111的主体电极1041在第二方向Y上的最大尺寸与第二类型子像素112的主体电极1042在第二方向Y上的最大尺寸相差不是特别大，因此，主体电极1041在第一方向N的尺寸减小趋势与主体电极1042在第一方向N的尺寸减小趋势也相差不大，第一类型电源部3010的第二主体部312与第二类型电源部3011的第二主体部315在第二方向Y上的最大尺寸也可以是相近的。例如，可以使得第一类型电源部3010的第二主体部312的最大尺寸L12与第二类型电源部3011的第二主体部315的最大尺寸L13之比为0.9～1.1，例如为1，即L12与L13相等，可以在满足主体电极1041或主体电极1042的平坦性的同时，有利于产品的制造，降低制造成本。
例如，第二类型电源部3011的第一主体部314在第二方向Y上的最大尺寸L13可以是第二类型电源部3011的第二主体部315在第二方向Y上的最大尺寸L14的1.1-2倍。例如，第二类型电源部3011中，第一主体部314的最 大尺寸L13可以为第二主体部的最大尺寸L14的1.2～1.9倍。例如，第二类型电源部3011中，第一主体部314的最大尺寸L13可以为第二主体部的最大尺寸L14的1.3～1.8倍。例如，第二类型电源部3011中，第一主体部314的最大尺寸L13可以为第二主体部的最大尺寸L14的1.4～1.7倍。例如，第二类型电源部3011中，第一主体部314的最大尺寸L13可以为第二主体部的最大尺寸L14的1.5～1.6倍。
例如，第一类型电源部中，第一主体部在第二方向上的最大尺寸可以为第二主体部在第二方向上的最大尺寸的1.1～1.8倍，如1.2～1.7倍，如1.3～1.6倍，如1.4～1.5倍等。
例如，将第二类型电源部3011的第一主体部314在第二方向Y上的最大尺寸L13设置的尽量大一些，例如，在本公开的一些实施例中，第一主体部314在第二方向Y上的最大尺寸L13可以是第二主体部315在第二方向Y上的最大尺寸L14的1.5倍，可以使得第二类型子像素112的主体电极1042中的第一角部141和第二角部142刚好将第一主体部314的第一凸出部317和第二凸出部318覆盖，满足第二类型子像素112的主体电极1042的平坦性设置的需求，同时还可以使得最大尺寸L13与最大尺寸L14之间的比例尽量统一，以利于简化版图设计和制造。
例如，参考图5和图6，显示基板中相邻的多条电源信号线300中的每条电源信号线300均包括沿第一方向N排列的多个电源部300-3，相邻两个电源部300-3之间设置有与相邻两个电源部300-3均电连接的第一连接部330，多个电源部300-3包括上述的第一电源部301，各电源部第二方向Y上的最大尺寸与第一连接部330在第二方向Y上的最大尺寸L30之比为1.5-5。
例如，各电源部300-3第二方向Y上的最大尺寸与第一连接部330在第二方向Y上的最大尺寸L30之比为2-4.5，如2.5-4，如3-3.5等。
例如，参考图3-图6，显示基板中包括多条沿第一方向N延伸的电源信号线300，且在每条电源信号线300中均设置至少一个电源部300-3。电源部300-3可以是第一电源部301，也可以是第二电源部302。其中第一电源部301对应于第一子像素010，第二电源部302对应于第二子像素。第一电源部301中还可以包括对应于第一类型子像素111的第一类型电源部3010，以及对应于第二类型子像素112的第二类型电源部3011。对于每个电源部300-3，该电源部300-3在衬底基板001上的正投影与其对应的主体电极在衬底基板001 上的正投影至少部分交叠。例如，每个电源部300-3在衬底基板001上的正投影与其对应的主体电极在衬底基板001上的正投影的交叠面积尽量大一些，例如该交叠面积可以是电源部300-3对应的主体电极在衬底基板001上的正投影面积的至少90％，以使得电源部300-3对应的主体电极具有较高的平坦度。
参考图5和图6，相邻两个电源部300-3通过第一连接部330实现电连接，也即同一条电源信号线300上的所有电源部300-3均是电连接的。各电源部300-3在第二方向Y上的最大尺寸与第一连接部330在第二方向Y上的最大尺寸L30之比可以是1.5-5，例如可以是4，或者2，或者3等。相对于各个电源部300-3，第一连接部330在实现了电连接功能的前提下，在第二方向Y上的最大尺寸L30可以设计的偏小一些，这样可以使得版图空间更宽松，有利于版图排布。
例如，参考图5和图6，第一类型电源部3010包括第一子类型电源部3016和第二子类型电源部3017，第一类型电源部3010的第二主体部312包括在第二方向Y上相对的第一侧K1和第二侧K2，第一子类型电源部3016中第一凸出部3131设置在第二主体部312的第一侧K1，第二子类型电源部3017中第一凸出部3132设置在第二主体部312的第二侧K2。
例如，如图6所示，以Y方向的箭头所指的方向为向右，第一子类型电源部3016设置的第一凸出部3131位于第二主体部312的左侧，第二子类型电源部3017设置的第一凸出部3132位于第二主体部312的右侧。
例如，沿Y方向排列的彼此相邻的第一子类型电源部3016和第二子类型电源部3017相对于沿N方向延伸的直线对称分布。这里的“彼此相邻的第一子类型电源部3016和第二子类型电源部3017”可以指这两个电源部之间没有设置其他第一子类型电源部3016和第二子类型电源部3017，但是可以设置其他类型电源部。
例如，每条电源信号线300上的多个电源部可以是不相同的，例如，不同的电源部在第二方向Y上的最大尺寸可以是不同的，从而可以灵活适应于不同的主体电极的排布形式，满足不同的主体电极的平坦性要求。
例如，参考图5和图6，第一类型子像素111可以包括两种设置方式。例如，如图5和图6所示，第一类型子像素111可以包括第三角部143位于第四角部144左侧的第三种子像素和第三角部143位于第四角部144右侧的第四种子像素，第三种子像素中的第四角部144与第一子类型电源部3016的第 一凸出部313交叠，第四种子像素中的第四角部144与第二子类型电源部3017的第一凸出部313交叠。
例如，如图5所示，第一类型子像素111的主体电极1041相对于平面P1对称分布。对应地，将第一子类型电源部3016中第一凸出部3131和第二子类型电源部3017中第一凸出部3132设置在相对的两侧。由此，可以满足第一类型子像素111在上述两种设置方式下，第一类型子像素111的主体电极1041中的第四角部144在衬底基板001上的正投影均能够覆盖在第一凸出部3131或第二凸出部3132在衬底基板001上的正投影上，以保证主体电极1041在第四角部144处的平坦性。
例如，参考图5和图6，第一子像素010的主体电极1040包括第一角部141、第二角部142、第三角部143和第四角部144，主体电极1040的每条边或其延长线依次连接成多边形H10，且多边形H10的多个顶角存在与对应的主体电极的多个角部不交叠的区域，其中，第三角部143和与其对应的多边形H10的顶角不交叠的区域面积A10大于至少部分其他角部中各角部和与该角部对应的多边形的顶角不交叠的区域面积。
例如，参考图5和图6，主体电极1040的四条延长线H1、H2、H3和H4，构成了多边形H10。对应于第一角部141，多边形H10在顶角处包括不交叠的区域A10；对应于第二角部142，多边形H10在顶角处包括不交叠的区域A11；对应于第三角部143，多边形H10在顶角处包括不交叠的区域A12；对应于第四角部144，多边形H10在顶角处包括不交叠的区域A13。
例如，主体电极1040的四个角部可以分别包括不同大小的倒角，例如，在本实施例中，第三角部143处的倒角均大于其他角部处的倒角，由此使得第三角部143和与其对应的多边形H10的顶角不交叠的区域面积A12大于其他角部中各角部和与该角部对应的多边形H10的顶角不交叠的区域面积。当然，在一些实施例中，主体电极1040的各个角部的倒角大小可以根据各发光区的大小要求进行设计，本公开的实施例中提供的各主体电极的形状仅是示例性的，而非限制。由此，可以保证主体电极的形状设计具有灵活性。
例如，上述倒角可以指一段曲线形成的顶角，该曲线可以为圆弧，也可以为非规则的曲线，例如椭圆形中截取的曲线、波浪线等。本公开实施例示意性的示出该曲线具有相对于子像素的中心向外凸的形状，但不限于此，也可以为该曲线具有相对于子像素的中心向内凹的形状。例如，曲线为圆弧时， 该圆弧的圆心角的范围可以为10°～150°。例如，该圆弧的圆心角的范围可以为60°～120°。例如，该圆弧的圆心角的范围可以为90°。例如，第三角部143包括的圆倒角的曲线长度可以为10～60微米。例如，第三角部143处的倒角的曲率半径均大于其他角部处的倒角的曲率半径。
例如，如图5和图6所示，第一类型电源部3010和第二类型电源部3011的第二主体部32包括沿第一方向N延伸的两条直边。例如，第一类型电源部3010的第一主体部311中与第一凸出部313相对的边可以为沿第一方向N延伸的直边，且该直边与第二主体部312的一条直边位于同一直线上。
例如，如图5和图6所示，第一凸出部313包括与第二主体部312的直边连接的倾斜边，该倾斜边与第一方向N的夹角可以为10～90度，如20～80度，如30～70度，如40～60度，如45度。例如该倾斜边与连接第四角部144和第一角部141的边的夹角可以为0～30度，如2～25度，如5～20度，如7～15度，如8～10度。例如，第一凸出部313远离第二主体部312一侧的边可以平行于第二方向Y，连接该边远离第二主体部312的沿第一方向N延伸的中心线的一端与倾斜边远离该中心线的一端的连接线可以包括折线或曲线。
例如，如图5和图6所示，第二凸出部317和第三凸出部318之一与第一凸出部313具有相同的形状和尺寸，第二凸出部317和第三凸出部318相对于第二类型电源部3011的沿第一方向N延伸的第三对称中心线L6对称分布。
例如，如图5和图6所示，第一类型电源部3010和第二类型电源部3011中的第二主体部32的形状和尺寸可以均相同，第一类型电源部3010的第一主体部311除第一凸出部313以外部分与第二类型电源部3011的第一主体部314除第二凸出部317和第三凸出部318以外部分的形状和尺寸可以均相同。
例如，如图5和图6所示，第一子像素为发出一种颜色光的子像素，如发出蓝光的子像素，电源信号线中与发出同一种颜色光的不同子像素的第一电极交叠的部分的形状可以不同，交叠区域的面积可以不同。
例如，具有上述四个角部的第一子像素111可以均匀分布在显示基板的显示区中，但不限于此，显示基板可以包括第一显示区和第二显示区，具有上述四个角部的第一子像素111可以仅分布在第一显示区。例如，第一显示区可以为设置屏下摄像头的区域，第二显示区可以为正常显示区，通过在设置屏下摄像头的区域设置具有上述四个角部的第一子像素111，有利于提高第 二显示区的透光率。
例如，参考图3-图6，至少部分子像素还包括多个第二子像素020，沿第三方向Z，至少一条电源信号线300包括与多个第二子像素020的至少一个的主体电极1050交叠的第二电源部302。第二电源部302包括沿第一方向N延伸的第五对称中心线L32，第二子像素020的主体电极1050包括沿第一方向N延伸的第六对称中心线L33，同一列电源信号线300中的第二电源部302的第五对称中心线L32和与该第二电源部302交叠的第二子像素的第六对称中心线L33位于垂直于衬底基板001的同一平面内。
例如，参考图3-图6，第二子像素020的主体电极1050在衬底基板001上的正投影小于第一子像素010的主体电极1040在衬底基板001上的正投影面积，且第二子像素020主体电极1050在第一方向N上的最大尺寸小于第一子像素010主体电极1040在第一方向N上的最大尺寸，第二子像素020主体电极1050在第二方向Y上的最大尺寸小于第一子像素010主体电极1040在第二方向Y上的最大尺寸。第二子像素020的主体电极1050相对于沿第一方向N延伸的第六对称中心线L33对称分布，第二电源部302相对于沿第一方向N延伸的第五对称中心线L32对称分布，并且主体电极1050设置在第二电源部302远离衬底基板001的一侧，因此，对于同一个第二子像素020，第二电源部302的第五对称中心线L32和与该第二电源部302交叠的第二子像素的第六对称中心线L33位于垂直于衬底基板001的同一平面内。第五对称中心线L32与第六对称中心线L33是平行的，并且均位于垂直于衬底基板001的同一平面内。当同一列电源信号线300对应于多个第二子像素020时，则同一列电源信号线300中的第五对称中心线L32与第六对称中心线L33均位于垂直于衬底基板001的同一平面内。
因此，主体电极1050在衬底基板001上的正投影可尽量将第二电源部302在衬底基板001上的正投影覆盖，从而使得主体电极1050趋于平坦。
例如，参考图3-图6，第二子像素020的主体电极1050在衬底基板001上的正投影与第二电源部302在衬底基板001上的正投影交叠，并且交叠面积AS1至少为第二子像素020的主体电极1050在衬底基板001上的正投影面积AS的90％。例如，交叠面积AS1至少为第二子像素020的主体电极1050在衬底基板001上的正投影面积AS的92％，或者95％，或者98％。
例如，参考图3-图6，相比于第二电源部302在衬底基板001上的正投影， 主体电极1050在衬底基板001上的正投影相对较小，并且当交叠面积AS1为第二子像素020的主体电极1050在衬底基板001上的正投影面积AS的90％以上时，第二子像素020的发光区1033内的主体电极1050几乎全部是平坦的，由此可以有效防止色偏的产生。
例如，如图3-图6所示，第二电源部302与第一电源部301的形状不同。例如，第二电源部302的面积小于第一电源部301的面积。例如，第二电源部302在第二方向Y上的最大尺寸与第一电源部301的第二主体部32在第二方向Y上的最大尺寸之比可以为0.9～1.1。例如，第一类型电源部3010除第一凸出部313以外的部分可以与第二电源部302的形状相同，且两者的面积相同。例如，第二类型电源部3011除第二凸出部317和第三凸出部318以外的部分可以与第二电源部302的形状相同，且两者的面积相同。
例如，如图5和图6所示，电源信号线300包括的沿第一方向N排列的多个电源部300-3可以包括交替排列的第一电源部301和第二电源部302，同一条电源线号线300上至少包括形状不同的两种电源部300-3。
例如，如图5和图6所示，各第二电源部302可以具有相同的形状以及面积。例如，电源信号线300与不同的第二子像素020的第一电极102交叠的不同部分可以具有相同的形状以及面积。
当然，本公开实施例不限于此，在第二子像素020的形状设置为包括与第一子像素010相似的四个角部时，与不同第二子像素020交叠的第二电源部302的形状可以不同，此时，第二电源部302的形状可以根据第二子像素020的第一电极102的形状而定。
例如，参考图5和图6，显示基板还包括多条数据线400，多条数据线400沿第一方向N延伸且沿第二方向Y排列，多条数据线400与多条电源信号线300同层设置，其中，相邻两条电源信号线300之间设置的数据线400包括沿第二方向Y排列的第一数据线401和第二数据线402，第一数据线401和第二数据线402相对于第一数据线401和第二数据线402之间的第七对称中心线L40对称分布。
例如，如图6所示，相邻两条电源信号线300之间的第一数据线401和第二数据线402在第二方向Y上的最大尺寸V小于电源信号线300在第二方向Y上的最大尺寸L13，每条数据线还包括了连接块450，以实现与像素电路200中的晶体管连接。对于同一条电源信号线300，连接块与各个电源部相邻 且间隔设置，连接块与各个电源部的最小距离约为第一连接部330在第二方向Y上的尺寸的1/3-2/3，由此可有利于实现版图空间的宽松，并防止各条信号线之间的信号干扰。上述最大尺寸V可以包括第一数据线401和第二数据线402的线宽以及两者之间的距离。
例如，如图6所示，第一类型电源部3010的第一主体部311与位于其两侧且与其紧邻的数据线(除连接块以外的部分)之间的距离不同。例如，第一类型电源部3010的第二主体部312与位于其两侧与其紧邻的数据线(除连接块以外的部分)之间的距离相同。例如，第二类型电源部3011的第一主体部314与位于其两侧且与其紧邻的数据线(除连接块以外的部分)之间的距离相同。例如，第一类型电源部3010的第二主体部312与位于其两侧与其紧邻的数据线(除连接块以外的部分)之间的距离相同。例如，第二电源部302与位于其两侧与其紧邻的数据线(除连接块以外的部分)之间的距离相同。
例如，参考图5和图6，至少部分子像素10还包括多个第三子像素030，多个第三子像素030中至少一个的发光元件100的主体电极1060与数据线400至少部分交叠，且第三子像素030的主体电极1060与数据线400的交叠区AS2相对于第七对称中心线L40基本对称。
例如，参考图5和图6，第三子像素030的主体电极1060在衬底基板001上的正投影面积小于第二子像素020的主体电极1050在衬底基板001上的正投影面积，且第三子像素030的主体电极1060在第一方向N上的最大尺寸小于第二子像素020的主体电极1050在第一方向N上的最大尺寸，第三子像素030主体电极1060在第二方向Y上的最大尺寸小于第二子像素020的主体电极1050在第二方向Y上的最大尺寸。例如，第三子像素030可以具有两种不同的设置方式，两个不同设置方式的第三子像素030相对于第四对称中心线L7对称设置。如图5所示，第三子像素030的主体电极1060与数据线400的交叠区AS2包括两部分，且交叠区AS2相对于第七对称中心线L40基本对称。由此，通过将交叠区AS2相对于第七对称中心线L40对称分布，可以增加第三子像素030的主体电极1060的平坦度，以减小第三子像素030产生色偏等现象。
例如，如图5所示，第三子像素030的主体电极1060与数据线300的除连接块450以外的部分交叠。
例如，参考图5和图6，显示基板还包括多个第二连接部500，多个第二 连接部500与至少部分多条电源信号线300同层设置，每个第二连接部500包括第一连接件501和第二连接件502。多个第二连接部500沿第一方向N和第二方向Y阵列排布以形成多个第二连接部行503和多个第二连接部列504。
电源信号线300包括沿第一方向N排列的多个电源部，例如第一电源部301和第二电源部302，相邻两个电源部之间设置有与相邻两个电源部均电连接的第一连接部300，多条电源信号线300包括的电源部沿第一方向N和第二方向Y阵列排布以形成多个电源部行308和多个电源部列309。
多个第二连接部行503和多个电源部行308在第一方向N上交替排布，同一第二连接部行503中相邻两个第二连接部500分布在数据线400两侧。
例如，如图6所示，多个第二连接部500包括多个第一连接件501和多个第二连接件502，多个第一连接件501包括沿第二方向Y排列的多个第一连接件列，多个第二连接件502包括沿第二方向Y排列的多个第二连接件列，多个第一连接件列和多个第二连接件列沿第二方向Y交替排列。
例如，第一连接件501与第二连接件502的形状可以相同，也可以不同。
例如，同一第二连接部行503中相邻两个第二连接部500相对于第七对称中心线L40对称分布，在第二方向上，第一连接件501或第二连接件502与数据线400的最小距离和第一连接件501或第二连接件502与第一连接部300的最小距离基本一致，由此可以使得版图空间分布均匀且宽松。
例如，在本公开的一些实施例中，多条电源信号线可以设置在不同层，并通过并联的形式进行电连接，因此，多个第二连接部500也可以分布在不同层上，本公开的实施例对此不作限制。例如，同一第二连接部行503中相邻两个第二连接部500也可以不是对称分布的，可以根据实际的版图需要进行设计。
例如，参考图5和图6，发光元件100的第一电极102还包括与主体电极104电连接的连接电极105，连接电极105与发光元件100的发光区103没有交叠，并且连接电极105通过第二连接部500与发光控制晶体管T6电连接。
例如，参考图5和图6，每个像素电路中主体电极104的连接电极105均设置在主体电极104的一侧，例如，以图7中的箭头Y的指向方向为右，连接电极105可以均设置在主体电极104的沿着第一方向N延伸的中心线的左侧。连接电极105在衬底基板001上的正投影的面积均小于主体电极104 在衬底基板001上的正投影的面积。例如，连接电极105在衬底基板001上的正投影与数据线400在衬底基板001上的正投影无交叠，与发光区103在衬底基板001上的正投影没有交叠，由此可以避免连接电极105对数据线和发光区103的中的信号产生干扰，保证像素电路200的性能。
例如，参考图5和图6，发光元件100的连接电极105与第一连接部300无交叠，且在第一方向N上，第一子像素010的主体电极1040的最大尺寸L975不小于其对应的第一电源部301中第一主体部31的最大尺寸L985。
例如，发光元件100的连接电极105在衬底基板001上的正投影与其相近的第一连接部300在衬底基板001上的正投影的交叠面积几乎无交叠。例如，该交叠面积不大于连接电极105在衬底基板001上的正投影面积的1/15，以减少信号线之间可能产生的串扰现象。
例如，参考图5和图6，第一子像素010的主体电极1040的最大尺寸L975可以大于第一主体部31的最大尺寸L985。在一些实施例中，第一主体部31的最大尺寸L985可以为第一子像素010的主体电极1040的最大尺寸L975的1/4-1/2。例如，第一主体部31的最大尺寸L985可以为第一子像素010的主体电极1040的最大尺寸L975的1/3-2/3。例如，第一子像素010的主体电极1040的最大尺寸L975不小于其对应的第一电源部301中第一主体部31的最大尺寸L985，有利于增强主体电极1040的平坦性。
例如，在第二方向Y上，同一个第二连接部500的第一连接件501和第二连接件502之间设置有第一连接部300，且同一个第二连接部500的第一连接件501和第二连接件502相对于二者之间的第一连接部300间隔分布。
例如，参考图5和图6，多个第二连接部行503和多个电源部行308在第一方向N上交替排布，也即，相邻两个电源部行308之间设置有一个第二连接部行503，在同一第二连接部行503中，每个第二连接部500的第一连接件501和第二连接件502之间设置有一个第一连接部300，并且该第一连接部300与其最近的第一连接件501和第二连接件502间隔设置。发光元件100的连接电极105与第一连接件501和第二连接件502电连接，且每个第二连接部500中的第一连接件501和第二连接件502与相邻的第一连接部300间隔设置，由此可减小连接电极105在与第二连接部500连接时的信号与第一连接部300上的信号发生干扰。
例如，发光元件100的主体电极104在衬底基板上的正投影与第二连接 部500在衬底基板上的正投影尽量间隔设置，可以避免第二连接部500影响主体电极104的平坦度。例如，将同一个第二连接部500的第一连接件501和第二连接件502相对于二者之间的第一连接部300对称设置，进一步有利于版图的排布。
例如，参考图5和图6，第一连接件501或第二连接件502在第一方向N上的最大尺寸L51小于第一连接部300在第一方向N上的最大尺寸L52。
例如，参考图5和图6，同一个第二连接部500的第一连接件501和第二连接件502之间设置有第一连接部300，且当该第一连接部300在第一方向N上的最大尺寸L52较大，且大于与其邻近的第一连接件501或第二连接件502在第一方向N上的最大尺寸L51时，有利于使连接在该第一连接部300在第一方向N上的两端的两个电源部与第一连接件501和第二连接件502之间具有一定间距，进而是使得设置在该两个电源部上的主体电极104也可以与第一连接件501和第二连接件502之间具有一定间距，由此可防止信号之间的干扰。
例如，参考图5和图6，第一连接件501与第一子像素010的连接电极1051或第二子像素020的连接电极1051电连接，第二连接件502与第三子像素030的连接电极1061电连接。
例如，参考图5和图6，在第一方向上，相邻的第一子像素010的连接电极1051、第二子像素020的连接电极1051和第三子像素030的连接电极1051依次间隔排布，且第一子像素010的连接电极1051和第三子像素030的连接电极1051均设置在第二连接部500靠近第一连接件501的一侧，第二子像素020的连接电极1051设置在第二连接部500靠近第二连接件502的一侧，从而在第二方向上也间隔设置。由此，可有利于版图空间的利用和设计。
当然，在一些实施例中，第二连接部500中的连接件的数量和位置也可以根据实际构图的不同而相应变化，本公开的实施例对此不作限制。
例如，如图7所示，多个子像素10包括多个第一子像素010、多个第二子像素020以及多个第三子像素030。例如，第一子像素010和第二子像素020之一为发出蓝光的蓝色子像素，第一子像素010和第二子像素020的另一个为发出红光的红色子像素，第三子像素030为发出绿光的绿色子像素。例如，第一子像素010为蓝色子像素，第二子像素020为红色子像素，蓝色子像素的发光区的面积大于红色子像素的发光区的面积。例如，蓝色子像素的 发光区的面积大于绿色子像素的发光区的面积。当然，本公开实施例不限于此，第一子像素、第二子像素以及第三子像素的名称可以互换，如第一子像素可以为绿色子像素，第二子像素可以为蓝色子像素，第三子像素可以为红色子像素；或者，第一子像素可以为蓝色子像素，第二子像素可以为红色子像素，第三子像素可以为绿色子像素等。
例如，如图7所示，多个第一子像素010和多个第二子像素020沿第一方向N和第二方向Y交替设置以形成多个第一像素行061和多个第一像素列062，多个第三子像素030沿第一方向N和第二方向Y阵列排布以形成多个第二像素行071和多个第二像素列072。
多个第一像素行061和多个第二像素行071沿第一方向N交替设置且在第二方向Y上彼此错开，多个第一像素列062和多个第二像素列072沿第二方向Y交替设置且在第一方向N上彼此错开。
第一方向和第二方向相交。例如，第一方向与第二方向可以垂直。例如，第一方向和第二方向可以互换。
例如，以第一像素行061中相邻的第一子像素010和第二子像素020的发光区的中心，以及沿列方向与该相邻的第一子像素010和第二子像素020分别相邻的第一子像素010和第二子像素020的发光区的中心为虚拟四边形的四个顶点，虚拟四边形内设置有一个第三子像素030的发光区的中心。
例如，如图7所示，一个第二像素行071包括沿第二方向Y排列的多个第三子像素对035，一个第三子像素对035中的两个第三子像素030分别为第一像素块0301和第二像素块0302，且第一像素块0301和第二像素块0302沿第二方向Y交替设置。例如，一个第二像素列072中的第一像素块0301和第二像素块0302沿第一方向N交替设置。
例如，至少两个第二像素行071包括沿第一方向排列的多个第三子像素对035，至少两个第三子像素对035中的两个第三子像素030分别为第一像素块0301和第二像素块0302，且第一像素块0301和第二像素块0302沿第二方向Y交替设置。例如，至少两个第二像素列072中的第一像素块0301和第二像素块0302沿第一方向N交替设置。
例如，如图7所示，多个子像素10包括多个最小重复单元700，一个最小重复单元700包括一个第一子像素010，一个第一像素块0301、一个第二像素块0302以及一个第二子像素020。例如，至少两个最小重复单元700包 括一个第一子像素010，一个第一像素块0301、一个第二像素块0302以及一个第二子像素020。例如，每个最小重复单元700包括一个第一子像素010，一个第一像素块0301、一个第二像素块0302以及一个第二子像素020。例如，每个最小重复单元700包括两行四列子像素10。
例如，如图7所示，一个最小重复单元700中，第一像素块0301与第一子像素010构成第一像素单元701，第二像素块0302与第二子像素020构成第二像素单元702。
例如，至少两个最小重复单元700中，第一像素块0301与第一子像素010构成第一像素单元701，第二像素块0302与第二子像素020构成第二像素单元702。
上述第一像素单元和第二像素单元不是严格意义上的像素，即由完整的一个第一子像素010、一个第二子像素020以及一个第三子像素030定义的一个像素。这里的最小重复单元700是指像素排列结构可以包括多个重复排列的该最小重复单元。
例如，第一子像素010和第二子像素020为共用子像素，通过虚拟算法，可以使得四个子像素实现两个虚拟像素单元的显示。
需要说明的是，本公开的实施例中提供的像素排布形式仅是示例性的，而非限制。在本公开的一些实施例中，根据实际的版图设计需要，像素排布形式可以随之灵活改变。
参考图3和图5，多个第一子像素010的连接电极1051和多个第二子像素020的连接电极1051分别通过多个第一连接孔D0与相应的第二连接部500电连接，且多个第一连接孔D0位于多条第一连接线X1上。
多个第三子像素030的连接电极1061分别通过多个第二连接孔D1与相应的第二连接部500电连接，且多个第二连接孔D1位于多条第二连接线X2上，第一连接线X1与第二连接线X2均沿第二方向Y延伸且间隔设置。
例如，如图3所示，多个第一子像素010的连接电极1051和多个第二子像素020的连接电极1051均分布在第一连接件的边缘的一侧，第一连接线X1沿第二方向Y延伸。多个第三子像素030的连接电极1061均分布在第一连接件的靠近中部的位置，第二连接线X2也沿第二方向Y延伸。第一连接线X1与第二连接线X2在第一方向N上是间隔设置的，由此也可以使得多个第一子像素010、多个第二子像素020和多个第三子像素030在第一方向N 上是间隔设置，以使得版图空间更加均匀。
例如，在本开的一些实施例中，多个第一连接孔D0相对于第一连接线X1也可以具有一定的偏差，即多个第一连接孔D0可以不完全分布在第一连接线X1上。例如，至少一个第一连接孔D0相对于第一连接线X1具有1-2微米的偏差。例如，至少一个第一连接孔D0相对于第一连接线X1具有2-3微米的偏差。同理，多个第二连接孔D1相对于第二连接线X2也可以具有一定的偏差。例如，至少一个第二连接孔D1相对于第二连接线X2具有1-2微米的偏差。例如，至少一个第二连接孔D1相对于第二连接线X21具有2-3微米的偏差。
例如，参考图3-图6，在本公开的一些实施例中，在同一个最小重复单元700中，第一子像素010与第二子像素020分别对应的第一连接孔D0位于同一条第一连接线X1上，第一像素块0301和第二像素块0302分别对应的第二连接孔D1位于同一条第二连接线X2上。在本公开的一些实施例中，在同一个最小重复单元700中，第一子像素010对应的第一连接孔D0、第二子像素020对应的第一连接孔D0以及第一像素块0301对应的第二连接孔D1位于同一条第一连接线X1上，第二像素块0302对应的第二连接孔D1位于第二连接线X2上。例如，在同一个最小重复单元700中，第一子像素010对应的第一连接孔D0位于第一连接线X1上，第二子像素020对应的第一连接孔D0、第一像素块0301对应的第二连接孔D1以及第二像素块0302对应的第二连接孔D1位于第二连接线X2上，本公开的实施例对此不作限制。
例如，第一子像素010对应的第一连接孔D0、第二子像素020对应的第一连接孔D0、第一像素块0301对应的第二连接孔D1以及第二像素块0302对应的第二连接孔D1可以等间距排布。例如，根据实际的版图设计需要，第一子像素010对应的第一连接孔D0、第二子像素020对应的第一连接孔D0、第一像素块0301对应的第二连接孔D1以及第二像素块0302对应的第二连接孔D1也可以是不等间距排布，本公开的实施例对此不作限制。
如图6所示，第一连接部330包括至少一个挖孔部380，并且挖孔部380的面积为第一连接部330的面积的1/4-1/3。
例如，在本公开的一些实施例中，第一连接部330上的挖孔部380可以是在垂直于衬底基板的方向上贯通第一连接部330的通孔或者开口，如挖孔部380可以暴露第一连接部330靠近衬底基板001一侧的像素电路200的结 构，如第一连接部330具有镂空图案。例如，第一连接330上的挖孔部380与第一电极102基本无交叠。例如，显示产品可以通过设置挖孔部380以增强其透过率。例如，在第一连接部330上设置挖孔部380，可有利于显示基板的透光性，使得显示效果优良。例如，第一连接部380上的挖孔部380的数量可以根据实际版图设计需求而定，本公开的实施例对此不作限制。例如，挖孔部380可以设计为具有规则的形状，例如，挖孔部380可以设计为多边形，椭圆形，正多边形以及圆形等。例如，挖孔部380也可以设计为不规则的形状。例如，多个挖孔部380的形状可以是相同的。例如，多个挖孔部380的形状也可以设计为不同的。本公开的实施例对于挖孔部380的形状不作限制。
例如，同一个第一连接部330上的挖孔部380可以是相对于该第一连接部330的一条中心对称线对称分布。例如，第一连接部330中挖孔部380的位置也可以根据实际版图的设计需要而定，本公开的实施例对此不作限制。
例如，在同一个第一连接部330中，挖孔部380的边界与第一连接部330的边界之间的距离不小于1微米，以防止第一连接部330发生断路。
图8为根据本公开实施例提供的像素电路的等效图。
例如，如图8所示，像素电路200中的发光控制晶体管T6可以为第一发光控制晶体管T6，像素电路200还包括第二复位晶体管T1、阈值补偿晶体管T2、驱动晶体管T3、数据写入晶体管T4、第二发光控制晶体管T5、第一复位控制晶体管T7以及存储电容C。
例如，显示基板还包括复位电源信号线、扫描信号线、电源信号线、复位控制信号线、发光控制信号线以及数据线。
例如，阈值补偿晶体管T2的第一极与驱动晶体管T3的第一极电连接，阈值补偿晶体管T2的第二极与驱动晶体管T3的栅极电连接；第一复位控制晶体管T7的第一极与复位电源信号线电连接以接收复位信号Vinit，第一复位控制晶体管T7的第二极与发光元件100的第一电极电连接(即N4节点)；数据写入晶体管T4的第一极与驱动晶体管T3的第二极电连接，数据写入晶体管T4的第二极与数据线电连接以接收数据信号Data，数据写入晶体管T4的栅极与扫描信号线电连接以接收扫描信号Gate；存储电容C的第一极与电源信号线电连接，存储电容C的第二极与驱动晶体管T3的栅极电连接；阈值补偿晶体管T2的栅极与扫描信号线电连接以接收补偿控制信号；第一复位晶体 管T7的栅极与复位控制信号线电连接以接收复位控制信号Reset(N+1)；第二复位晶体管T1的第一极与复位电源信号线电连接以接收复位信号Vinit，第二复位晶体管T1的第二极与驱动晶体管T3的栅极电连接，第二复位晶体管T1的栅极与复位控制信号线电连接以接收复位控制信号Reset(N)；第一发光控制晶体管T6的栅极与发光控制信号线电连接以接收发光控制信号EM；第一发光控制晶体管T6的第一极与驱动晶体管T3的第一极电连接，第一发光控制晶体管T6的第二极与发光元件100的第一电极电连接；第二发光控制晶体管T5的第一极与电源信号线电连接以接收第一电源信号VDD，第二发光控制晶体管T5的第二极与驱动晶体管T3的第二极电连接，第二发光控制晶体管T5的栅极与发光控制信号线电连接以接收发光控制信号EM，发光元件100的第二电极与电压端VSS连接。上述电源信号线指输出电压信号VDD的信号线，可以与电压源连接以输出恒定的电压信号，例如正电压信号。
例如，扫描信号和补偿控制信号可以相同，即，数据写入晶体管T3的栅极和阈值补偿晶体管T2的栅极可以电连接到同一条信号线以接收相同的信号，减少信号线的数量。例如，数据写入晶体管T3的栅极和阈值补偿晶体管T2的栅极也可以分别电连接至不同的信号线，即数据写入晶体管T3的栅极电连接到第一扫描信号线，阈值补偿晶体管T2的栅极电连接到第二扫描信号线，而第一扫描信号线和第二扫描信号线传输的信号可以相同，也可以不同，从而使得数据写入晶体管T3的栅极和阈值补偿晶体管T2可以被分开单独控制，增加控制像素电路200的灵活性。
例如，第一发光控制晶体管T6和第二发光控制晶体管T5被输入的发光控制信号可以相同，即，第一发光控制晶体管T6的栅极和第二发光控制晶体管T5的栅极可以电连接到同一条信号线以接收相同的信号，减少信号线的数量。例如，第一发光控制晶体管T6的栅极和第二发光控制晶体管T5的栅极也可以分别电连接至不同的发光控制信号线，而不同的发光控制信号线传输的信号可以相同，也可以不同。
例如，第一复位晶体管T7和第二复位晶体管T1被输入的复位控制信号可以相同，即，第一复位晶体管T7的栅极和第二复位晶体管T1的栅极可以电连接到同一条信号线以接收相同的信号，减少信号线的数量。例如，第一复位晶体管T7的栅极和第二复位晶体管T1的栅极也可以分别电连接至不同的复位控制信号线，此时，不同复位控制信号线上的信号可以相同也可以不 相同。
例如，如图8所示，显示基板工作时，在画面显示的第一阶段，第二复位晶体管T1打开，使N1节点的电压初始化；在画面显示的第二阶段，data数据通过数据写入晶体管T4、驱动晶体管T3以及阈值补偿晶体管T2存储在N1节点；在第三发光阶段，第二发光控制晶体管T5、驱动晶体管T3以及第一发光控制晶体管T6均打开，发光元件100正向导通发光。
需要说明的是，在本公开实施例中，各像素电路除了可以为图8所示的7T1C(即七个晶体管和一个电容)结构之外，还可以为包括其他数量的晶体管的结构，如7T2C结构、6T1C结构、6T2C结构或者9T2C结构，本公开实施例对此不作限定。上述实施例中所示的显示基板中像素电路的等效图可以与图8所示像素电路200的等效图相同。
图9为根据本公开实施例提供的像素电路中的遮光层、有源半导体图案、第一连接层的叠层结构示意图。图10为根据本公开实施例提供的像素电路中的遮光层、有源半导体图案、第一连接层、第二连接层、半导体层以及第三连接层的叠层结构示意图。
如图9所示，有源半导体图案LY1设置在遮光层LY0上，有源半导体图案LY1可采用半导体材料图案化形成。有源半导体图案LY0和第一连接层LY2可用于制作上述的驱动晶体管T3、数据写入晶体管T4、第二发光控制晶体管T5、第一发光控制晶体管T6和第一复位控制晶体管T7的有源层以用于形成上述晶体管的沟道区。有源半导体图案LY0包括各子像素的上述晶体管的有源层图案(沟道区)和掺杂区图案(源漏区)，且同一像素电路中的上述晶体管的有源层图案和掺杂区图案一体设置。
例如，有源半导体图案LY1可采用非晶硅、多晶硅、氧化物半导体材料等制作。需要说明的是，上述的源极区域和漏极区域可为掺杂有n型杂质或p型杂质的区域。
例如，有源半导体图案LY1远离衬底基板的一侧设置有金属层，如栅极金属层，该金属层包括上述扫描信号线、复位控制信号线、发光控制信号线以及驱动晶体管T3、数据写入晶体管T4、第二发光控制晶体管T5、第一发光控制晶体管T6和第一复位控制晶体管T7的栅极。图9中各虚线矩形框示出了上述金属层与有源半导体图案LY1交叠的各个部分以作为各个晶体管的沟道区，在每个沟道区两侧的有源半导体图案LY1通过离子掺杂等工艺导体 化作为各个晶体管的第一极和第二极(即上述源漏区)。晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在物理结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管，除作为控制极的栅极，直接描述了其中一极为第一极，另一极为第二极，所以本公开的实施例中全部或部分晶体管的第一极和第二极根据需要是可以互换的。
例如，形成像素电路中的第二复位晶体管T1和阈值补偿晶体管T2的沟道区的半导体层LY4可以位于有源半导体图案LY1远离衬底基板的一侧，半导体层LY4可以包括氧化物半导体材料。
例如，在图10为根据本公开实施例提供的像素电路中包括逐层铺设的遮光层LY0，有源半导体图案LY1、第一连接层LY2、第二连接层LY3、半导体层LY4以及第三连接层LY5。
如图10所示，虚线矩形框示出了第二复位晶体管T1和阈值补偿晶体管T2的沟道区。例如，第二连接层LY3可为第二复位晶体管T1和阈值补偿晶体管T2提供底栅结构，半导体层LY4与第二连接层LY3交叠设置，并在其远离衬底基板的一侧铺设第三连接层LY5以作为第二复位晶体管T1和阈值补偿晶体管T2顶栅层结构。
例如，像素电路的第二复位晶体管T1和阈值补偿晶体管T2中的有源层采用氧化物半导体的情况下，因用氧化物半导体的晶体管具备磁滞特性好，漏电流低的特点，同时迁移率(Mobility)较低，故可以采用氧化物半导体的晶体管代替晶体管中的低温多晶硅材料，形成低温多晶硅-氧化物的(LTPO)像素电路，实现低漏电，利于提高晶体管的栅极电压的稳定性。
当然，本公开实施例不限于像素电路的有源半导体图案为图9A所示的有源半导体图案LY1，第二复位晶体管T1和阈值补偿晶体管T2的沟道区的半导体层也可以与其他晶体管的沟道区的半导体层位于同一层，即有源半导体图案可以包括第二复位晶体管T1、阈值补偿晶体管T2、驱动晶体管T3、数据写入晶体管T4、第二发光控制晶体管T5、第一发光控制晶体管T6和第一复位控制晶体管T7的沟道区。
图11为根据本公开实施例提供的第一导电层的局部结构示意图；图12为根据本公开实施例提供的像素电路中的遮光层、有源半导体图案、第一连接层、第二连接层、半导体层、第三连接层以及第一导电层的叠层结构示意图；图13A为根据本公开实施例提供的第一导电层和第二导电层的叠层结构示意 图；图13B为为根据本公开实施例提供的第一导电层、第二导电层以及发光元件的叠层结构示意图。
例如，参考图11A、图12，显示基板包括位于发光元件的第一电极与第三连接层LY5之间的第一导电层LY6(如SD1层)，第一导电层LY6包括复位电源信号线801，该复位电源信号线801与第一复位晶体管T7的第一极电连接以提供复位信号。例如，上述复位电源信号线801可以为与第一复位晶体管T7的第一极电连接的第一复位电源信号线，显示基板还包括第二复位电源信号线，第二复位电源信号线的第一部分位于第一导电层LY6与第一复位晶体管T7的栅极所在膜层之间，被配置为与第二复位晶体管T1的第一极电连接以提供复位信号。
例如，参考图6、图11和图12，第一导电层LY6还包括连接结构802，第二导电层LY7还包括连接块450，数据写入晶体管T4的第二极通过连接结构802连接至连接块450，进而与数据线400电连接以接收数据信号。
例如，参考图6、图11和图12，第一导电层LY6还包括连接结构803，第二复位晶体管T1通过连接结构803与第二复位信号线电连接。
例如，参考图6、图7、图11、图12和图13，第一导电层LY6还包括连接结构804，第一发光控制晶体管T6的第一极以及第一复位晶体管T7的第二极通过连接结构804和第二导电层LY7中的第二连接部500电连接至发光元件LY8中的连接电极105，连接结构804与连接电极105电连接。
例如，参考图6、图11、图12和图13，第一导电层LY6还包括连接结构805，连接结构805包括第一连接结构805A和第二连接结构805B，第二发光控制晶体管T5的第一极与第一连接结构805A电连接，第二连接结构805B与第二导电层LY7中的第一连接部330电连接，由此使得第二发光控制晶体管T5的第一极与电源信号线300电连接。
例如，参考图6和图12，第一导电层LY6还包括连接结构806，阈值补偿晶体管T2的第一极通过连接结构806与驱动晶体管T3的第一极以及第一发光控制晶体管T6的第二极实现电连接。
例如，参考图6和图12，第一导电层LY6还包括连接结构807，以实现第二复位晶体管T1的第二极、阈值补偿晶体管T2的第二极以及驱动晶体管T3的栅极之间的电连接。
参考图3、图6、图7、图11、图12和图13，连接结构804在衬底基板 001上的正投影与连接块450在衬底基板001上的正投影基本重合，并且连接结构804与发光元件100在衬底基板001上的正投影无交叠，有利于版图的设计，并减小于发光元件100之间的信号干扰。
参考图12和图13，连接结构805还包括第三连接结构805C，第一连接结构805A和第二连接结构805B在第一方向N上间隔设置，并通过第三连接结构805C实现电连接，由此使得第二发光控制晶体管T5的第一极电连接至电源信号线300，该连接方式可以灵活地适应于当前的版图排布，并尽量减少了与其他晶体管之间的布线拥挤。
参考图3和图13，第一子像素010在衬底基板001上的正投影与复位电源信号线801在衬底基板001上的正投影、连接结构807在衬底基板001上的正投影均交叠，并且交叠区域相对于第一子像素010的主体电极1040的对称中心线W1基本呈对称分布，由此，有利于主体电极1040的平坦性，以减小色偏。类似地，第二像素02在衬底基板001上的正投影也与复位电源信号线801在衬底基板001上的正投影、连接结构807在衬底基板001上的正投影均交叠，并且交叠区域相对于第二子像素020的主体电极1050的对称中心线W2本呈对称分布，使得主体电极1050的平坦性良好。
参考图3、图5、图6和图13，第一连接结构805A在衬底基板001上的正投影落入第三子像素030的主体电极1060与数据线400的交叠区AS2中，且相对于第七对称中心线L40基本对称，由此，可以保证第三子像素030的平坦性良好，以减小色偏程度。
本公开另一实施例提供一种显示装置，包括上述任一种显示基板。本公开实施例提供的显示装置通过对像素电路进行设计，对像素电路与发光元件的匹配形式进行设计，有利于增强发光元件的连接电极的平坦性，减少显示产品发生色偏等现象。
例如，本公开实施例提供的显示装置可以为有机发光二极管显示装置。
例如，显示装置还可以包括位于显示基板的显示侧的盖板。
例如，该显示装置可以为具有屏下摄像头的手机、平板电脑、笔记本电脑、导航仪等任何具有显示功能的产品或者部件，本实施例不限于此。
有以下几点需要说明：
(1)本公开的实施例附图中，只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)在不冲突的情况下，本公开的同一实施例及不同实施例中的特征可以相互组合。
以上所述仅是本公开的示范性实施方式，而非用于限制本公开的保护范围，本公开的保护范围由所附的权利要求确定。

Claims (23)

  1. 一种显示基板，包括:
    衬底基板；
    多个子像素，位于所述衬底基板上，至少部分子像素包括发光元件和像素电路，所述发光元件包括发光功能层以及沿垂直于所述衬底基板的方向位于所述发光功能层两侧的第一电极和第二电极，所述第一电极位于所述发光功能层与所述衬底基板之间，所述发光元件至少部分位于发光区，所述发光元件的第一电极包括与所述发光区交叠的主体电极；
    多条电源信号线，所述多条电源信号线的至少部分沿第一方向延伸且沿第二方向排列，所述多条电源信号线位于所述衬底基板与所述发光元件的第一电极之间，所述第一方向与所述第二方向相交，
    其中，所述至少部分子像素包括多个第一子像素，沿垂直于所述衬底基板的第三方向，至少一条电源信号线包括与多个所述第一子像素的至少一个的主体电极交叠的第一电源部，每个所述第一电源部包括第一主体部和第二主体部；
    在所述第二方向上，所述第一子像素的主体电极的最大尺寸不小于其对应的所述第一电源部的最大尺寸，该第一电源部中的所述第一主体部的最大尺寸大于所述第二主体部的最大尺寸，所述第一子像素的主体电极在所述第二方向上距离最远的两个端点的连线为端点连线，在所述第三方向上，所述端点连线与所述第一主体部交叠。
  2. 根据权利要求1所述的显示基板，其中，所述多条电源信号线包括第一电源信号线和第二电源信号线，所述第一电源信号线和所述第二电源信号线在所述第二方向上的最大尺寸分别为第一尺寸和第二尺寸，且所述第二尺寸小于所述第一尺寸。
  3. 根据权利要求1所述的显示基板，其中，多个所述第一子像素包括至少一个第一类型子像素，与所述第一类型子像素的主体电极交叠的所述第一电源部为第一类型电源部，所述第一类型电源部的所述第一主体部为非对称结构。
  4. 根据权利要求3所述的显示基板，其中，所述第一类型电源部的所述第一主体部包括第一凸出部，所述第一凸出部位于所述第二主体部的沿所述第一方向延伸的第一对称中心线的一侧。
  5. 根据权利要求4所述的显示基板，其中，所述第一类型电源部除所述第一凸出部以外的部分的对称中心线的延伸方向与所述第一类型子像素的主体电极的第二对称中心线的延伸方向相交。
  6. 根据权利要求4-5任一项所述的显示基板，其中，多个所述第一子像素还包括至少一个第二类型子像素，与所述第二类型子像素的主体电极交叠的所述第一电源部为第二类型电源部，
    所述第二类型电源部包括沿所述第一方向延伸的第三对称中心线，所述第二类型子像素的所述主体电极包括沿所述第一方向延伸的第四对称中心线，同一列所述电源信号线中的所述第二类型电源部的所述第三对称中心线和与该第二类型电源部交叠的所述第二类型子像素的所述第四对称中心线位于垂直于所述衬底基板的同一平面内。
  7. 根据权利要求4-5任一项所述的显示基板，其中，所述第一子像素的主体电极包括相对的第一角部和第二角部，以及相对的第三角部和第四角部，
    所述第一角部和所述第二角部至少之一在所述衬底基板上的正投影与所述第一对称中心线在所述衬底基板上的正投影至少部分交叠，所述第四角部在所述衬底基板上的正投影与所述第一凸出部在所述衬底基板上的正投影至少部分交叠。
  8. 根据权利要求6所述的显示基板，其中，所述第二类型电源部的第一主体部包括第二凸出部和第三凸出部，所述第二凸出部和所述第三凸出部相对于所述第三对称中心线对称分布，
    所述第二类型子像素的主体电极包括相对的第一角部和第二角部，以及相对的第三角部和第四角部，
    所述第二凸出部在所述衬底基板上的正投影与所述第一角部和所述第二角部之一在所述衬底基板上的正投影至少部分交叠，所述第三凸出部在所述衬底基板上的正投影与所述第一角部和所述第二角部中另一者在所述衬底基板上的正投影至少部分交叠。
  9. 根据权利要求8所述的显示基板，其中，沿所述第三方向，所述第二类型子像素的发光区与所述第二凸出部和所述第三凸出部的至少之一交叠。
  10. 根据权利要求6或8所述的显示基板，其中，在所述第二方向上，所述第二类型电源部的第一主体部的最大尺寸大于所述第一类型电源部的第一主体部的最大尺寸，所述第一类型电源部的第二主体部的最大尺寸与所述 第二类型电源部的第二主体部的最大尺寸之比为0.9～1.1。
  11. 根据权利要求6以及8至10任一项所述的显示基板，其中，所述第二类型电源部的第一主体部在所述第二方向上的最大尺寸是所述第二类型电源部的第二主体部在所述第二方向上的最大尺寸的1.1-2倍。
  12. 根据权利要求1-11任一项所述的显示基板，其中，相邻的多条电源信号线中的每条电源信号线均包括沿所述第一方向排列的多个电源部，相邻两个电源部之间设置有与所述相邻两个电源部均电连接的第一连接部，多个所述电源部包括所述第一电源部，
    所述电源部在所述第二方向上的最大尺寸与所述第一连接部在所述第二方向上的最大尺寸之比为1.5-5。
  13. 根据权利要求7所述的显示基板，其中，所述第一类型电源部包括第一子类型电源部和所述第二子类型电源部，所述第一类型电源部的所述第二主体部包括在所述第二方向上相对的第一侧和第二侧，所述第一子类型电源部中所述第一凸出部设置在所述第二主体部的第一侧，所述第二子类型电源部中所述第一凸出部设置在所述第二主体部的第二侧。
  14. 根据权利要求7或8所述的显示基板，其中，所述第一子像素的主体电极包括多个角部，多个所述角部包括所述第一角部、所述第二角部、所述第三角部和所述第四角部，所述主体电极的每条边或其延长线依次连接形成多边形，且所述多边形的多个顶角存在与对应的主体电极的多个角部不交叠的区域；
    所述第三角部和与其对应的所述多边形的顶角不交叠的区域面积大于至少部分其他角部中各角部和与该角部对应的多边形的顶角不交叠的区域面积。
  15. 根据权利要求1-11任一项所述的显示基板，其中，所述至少部分子像素还包括多个第二子像素，
    沿所述第三方向，所述至少一条电源信号线包括与多个所述第二子像素的至少一个的主体电极交叠的第二电源部，
    所述第二电源部包括沿所述第一方向延伸的第五对称中心线，所述第二子像素的所述主体电极包括沿所述第一方向延伸的第六对称中心线，同一列所述电源信号线对应的所述第二电源部的所述第五对称中心线和与该第二电源部交叠的所述第二子像素的所述第六对称中心线位于垂直于所述衬底基板 的同一平面内。
  16. 根据权利要求15所述的显示基板，其中，所述第二子像素的主体电极在所述衬底基板上的正投影与所述第二电源部在所述衬底基板上的正投影交叠，并且交叠面积至少为所述第二子像素的主体电极在所述衬底基板上的正投影面积的90％。
  17. 根据权利要求15或16所述的显示基板，其中，在所述第二方向上，所述第二电源部的最大尺寸小于所述第一电源部的所述第一主体部的最大尺寸，且所述第二电源部的最大尺寸与所述第一电源部的所述第二主体部的最大尺寸之比为0.9～1.1。
  18. 根据权利要求15-17任一项所述的显示基板，还包括：
    多条数据线，沿所述第一方向延伸且沿所述第二方向排列，所述多条数据线与所述多条电源信号线同层设置，
    其中，相邻两条电源信号线之间设置的所述数据线包括沿所述第二方向排列的第一数据线和第二数据线，所述第一数据线和第二数据线相对于所述第一数据线和第二数据线之间的第七对称中心线对称分布；
    所述至少部分子像素还包括多个第三子像素，多个所述第三子像素至少一个的发光元件的主体电极与所述数据线至少部分交叠，且所述第三子像素的主体电极与所述数据线的交叠区相对于所述第七对称中心线基本对称。
  19. 根据权利要求18所述的显示基板，还包括：
    多个第二连接部，与至少部分所述多条电源信号线同层设置，每个第二连接部包括第一连接件和第二连接件，
    多个所述第二连接部沿所述第一方向和所述第二方向阵列排布以形成多个第二连接部行和多个第二连接部列，
    所述电源信号线包括沿所述第一方向排列的多个电源部，相邻两个电源部之间设置有与所述相邻两个电源部均电连接的第一连接部，所述多条电源信号线包括的所述电源部沿所述第一方向和所述第二方向阵列排布以形成多个电源部行和多个电源部列，
    多个所述第二连接部行和多个所述电源部行在所述第一方向上交替排布，同一第二连接部行中相邻两个第二连接部分布在所述数据线两侧。
  20. 根据权利要求19所述的显示基板，其中，所述发光元件的所述连接电极与所述第一连接部基本无交叠；
    在所述第一方向上，所述第一子像素的主体电极的最大尺寸不小于其对应的所述第一电源部中所述第一主体部的最大尺寸。
  21. 根据权利要求19-20任一项所述的显示基板，其中，所述第一连接件与所述第一子像素的连接电极或所述第二子像素的连接电极电连接，所述第二连接件与所述第三子像素的连接电极电连接。
  22. 根据权利要求12以及18-21任一项所述的显示基板，其中，所述第一连接部包括至少一个挖孔部，所述挖孔部的面积为所述第一连接部的面积的1/4-1/3。
  23. 一种显示装置，包括权利要求1-22任一项所述的显示基板。
PCT/CN2022/096339 2022-05-31 2022-05-31 显示基板及显示装置 WO2023230873A1 (zh)

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