WO2023230865A1

WO2023230865A1 - Substrate and preparation method therefor, chip package structure, and electronic device

Info

Publication number: WO2023230865A1
Application number: PCT/CN2022/096316
Authority: WO
Inventors: 杨方旭; 石林; 杨健
Original assignee: 华为技术有限公司
Priority date: 2022-05-31
Filing date: 2022-05-31
Publication date: 2023-12-07

Abstract

The embodiments of the present application relate to the technical field of semiconductors. Provided are a substrate and a preparation method therefor, a chip package structure, and an electronic device, which reduce crosstalk between differential pair of signals in an electronic device. The substrate comprises a first differential pair of vias and a second differential pair of vias, which are located in the substrate, wherein the first differential pair of vias include a first positive differential via and a first negative differential via; the second differential pair of vias include a second positive differential via and a second negative differential via; and the first positive differential via, the first negative differential via, the the second positive differential via and the second negative differential via are in a T-shaped arrangement, and the second positive differential via and the second negative differential via are respectively arranged on two sides of an extension line of a first virtual line segment, for example, the second positive differential via and the second negative differential via are symmetrically arranged on two sides of the extension line of the first virtual line segment. The first virtual line segment is a virtual line segment that connects a projection of the first positive differential via with a projection of the first negative differential via on the surface of the substrate.

Description

Substrate and preparation method thereof, chip packaging structure, electronic equipment

Technical field

The present application relates to the field of semiconductor technology, and in particular to a substrate and its preparation method, a chip packaging structure, and electronic equipment.

Background technique

Differential signals have good anti-noise and anti-interference capabilities, and are increasingly used as an internal signal transmission method in electronic equipment. The so-called differential signal refers to a signal transmitted using two signal lines. The two signals on the two signal lines have the same amplitude and opposite phase. Differential signals can be either analog or digital.

In order to realize the transmission of differential signals, a differential pair including two differential signal terminals is usually used for differential signal transmission. However, crosstalk usually occurs between adjacent differential pairs, thereby affecting the integrity of the differential signals transmitted by each differential pair.

In the field of high-speed differential signals (such as serializers, deserializers, digital-to-analog converters, analog-to-digital converters, clocks, etc.), crosstalk between differential pairs has become a key factor limiting further improvement in device performance.

Contents of the invention

Embodiments of the present application provide a substrate and a preparation method thereof, a chip packaging structure, and electronic equipment, which are used to reduce crosstalk between differential pairs of signals in electronic equipment.

In order to achieve the above purpose, this application adopts the following technical solutions:

A first aspect of the embodiment of the present application provides a substrate. The substrate may be a PCB, a download board, or a packaging substrate. The substrate includes a first differential pair via hole and a second differential pair via hole located within the substrate. The first differential pair of vias includes a first positive differential via and a first negative differential via; the second differential pair of vias includes a second positive differential via and a second negative differential via. The via holes of the first differential pair and the via holes of the second differential pair are arranged in a staggered manner. The connection line of the via holes of the first differential pair and the connection line of the via holes of the second differential pair do not intersect. The via holes of the first differential pair and the via holes of the second differential pair do not intersect. The via holes are arranged in a T shape. That is to say, the second positive differential via and the second negative differential via are respectively provided on both sides (for example, the upper and lower sides) of the extension line of the first virtual line segment; and the second positive differential via and the second negative differential via The holes are located at the same end (such as the left end or the right end) of the first virtual line segment. The first virtual line segment is a virtual line segment that connects the projection of the first positive differential via hole on the surface of the substrate and the projection of the first negative differential via hole on the surface of the substrate.

In the substrate provided by the embodiment of the present application, by arranging the second positive differential via and the second negative differential via on both sides of the extension line of the first virtual line segment, the second positive differential via and the second negative differential via are simultaneously Interferenced by the first positive differential via (or the first negative differential via). According to the characteristics of the differential signal, the signals of the second positive differential via and the second negative differential via are different, and the interferences received by the second positive differential via and the second negative differential via cancel each other out, so the crosstalk can be reduced. . In the case where the second positive differential via and the second negative differential via are symmetrically arranged on both sides of the extension line of the first virtual line segment, the second positive differential via and the second negative differential via are affected by the first positive differential via. The interference of the holes (or the first negative differential via) is consistent, so crosstalk can be eliminated. For example, the interference of the second positive differential via by the first positive differential via is 5mV, the interference of the second negative differential via by the first positive differential via is also 5mV, the second positive differential via and the second negative differential via The signals through the vias are different, and the interference can cancel each other out.

On the contrary, because the signals transmitted by the second positive differential via and the second negative differential via are signals with opposite polarities. Therefore, according to the opposite polarity characteristics, the interference of the second positive differential via and the second negative differential via on the first positive differential via (or the first negative differential via) also cancel each other, thereby achieving the reduction of crosstalk. Small. In the case where the second positive differential via and the second negative differential via are symmetrically arranged on both sides of the extension line of the first virtual line segment, the first positive differential via (or the first negative differential via) is affected by the second positive differential via. The interference of the differential via and the second negative differential via is consistent, so crosstalk can be eliminated. For example, the interference from the first positive differential via to the second positive differential via is 5mV, and the interference from the first positive differential via to the second negative differential via is -5mV. The interferences of 5mV and -5mV can cancel each other out.

In a possible implementation, the substrate further includes a first differential pair signal line and a second differential pair signal line; the first differential pair signal line is coupled to the first differential pair via hole, and the second differential pair signal line is coupled to the first differential pair signal line. Two differential pairs are coupled via vias; the first differential pair signal line and the second differential pair signal line are located in the substrate and are arranged on the same layer.

In this application, since along the direction parallel to the first virtual line segment, the second positive differential via hole and the second negative differential via hole are disposed on the same side of the first differential pair via hole. In this case, the second differential pair signal line may be located on the same side of the first differential pair signal line, that is, the second positive differential signal line and the second negative differential signal line are located on the same side of the first differential pair signal line. It is possible to achieve no intersection between the first differential pair signal line and the second differential pair signal line. Then, the first differential pair signal line and the second differential pair signal line can be arranged on the same layer to reduce the number of layers of signal lines in the substrate, thereby reducing the thickness of the substrate and reducing the cost of the substrate. In the related art, since the second positive differential via and the second negative differential via are located between the first positive differential via and the first negative differential via, if the first positive differential signal line and the first negative differential signal are to be lines are adjacent, and the second positive differential signal line and the second negative differential signal line are adjacent, it is inevitable that the first differential pair signal line and the second differential pair signal line will cross. Therefore, the first differential pair signal line and The second differential pair signal lines can only be arranged in different layers, resulting in an increase in substrate thickness.

In a possible implementation, the substrate further includes a first differential pair pad. The first differential pair pad includes a first positive differential pad and a first negative differential pad; the first positive differential pad is coupled to the first positive differential via, and the first negative differential pad is coupled to the first negative differential via. coupling; the second differential pair pad includes a second positive differential pad and a second negative differential pad; the second positive differential pad is coupled to the second positive differential via, and the second negative differential pad is coupled to the second Negative differential via coupling; a plurality of reference ground pads, a first positive differential pad, a first negative differential pad, a second positive differential pad, a second negative differential pad and a plurality of reference ground pad array rows spread on the surface of the substrate.

Since the solder balls of the current mainstream chip packaging structure are arranged in an array on the packaging substrate, the substrate provided by the embodiment of the present application has a first positive differential pad, a first negative differential pad, a second positive differential pad, The second negative differential pad and multiple reference ground pad arrays are arranged on the same surface of the substrate. This eliminates the need to change the solder ball arrangement of the chip package structure to be bonded to the substrate, and is compatible with existing checkerboard-shaped solder balls. The chip packaging structure of the arrangement scheme has a wide range of applications.

In a possible implementation, the first differential pair via holes and the second differential pair via holes are arranged along a first direction, the first positive differential pads and the first negative differential pads are arranged along the second direction, and the first differential pair via holes are arranged along a first direction. One direction intersects the second direction; the first positive differential via is offset from the first positive differential pad, the first negative differential via is offset from the first negative differential pad; the second positive differential via is offset from the second positive differential via. The differential pads are aligned and arranged, and the second negative differential via is aligned with the second negative differential pad. This is a simple implementation.

In a possible implementation, the substrate further includes a first differential pair pad on the surface of the substrate. The first differential pair pad includes a first positive differential pad and a first negative differential pad; the first positive differential via is aligned with the first positive differential pad and coupled to the first positive differential pad; The negative differential via is aligned with the first negative differential pad and coupled to the first negative differential pad; the second differential pair pad is located on the surface of the substrate, and the second differential pair pad includes a second positive differential pad and the second negative differential pad; the second positive differential via is aligned with the second positive differential pad and coupled to the second positive differential pad; the second negative differential via is aligned with the second negative differential pad , and coupled to the second negative differential pad. The first negative differential via is aligned with the first negative differential pad, and the second positive differential via is aligned with the second positive differential pad, thereby reducing crosstalk between the first differential pair via and the second differential pair via. Or on the basis of elimination, the first differential via hole and the second differential via hole can be easily prepared, and the layout of the first differential via hole and the second differential via hole is simple.

In a possible implementation, the substrate further includes a reference ground pad located on the surface of the substrate; the first differential pair via hole and the second differential pair via hole are arranged along the first direction, and the first positive differential pad and the first differential pair via hole are arranged in the first direction. The negative differential pads are arranged along the first direction; along the second direction, a reference ground pad is provided on at least one side of the second differential pair pad, and the second differential pair pad and the reference ground pad are located on the same straight line; wherein , the first direction intersects with the second direction. The second differential pair pad and the reference ground pad are located on the same straight line. Then the second positive differential pad and the second negative differential pad are arranged in the reference ground pad array. Only the first positive differential pad and the second differential pad need to be changed. The arrangement pattern of negative differential pads is enough, and the changes to the substrate structure are small.

In a possible implementation, the substrate further includes a reference ground pad located on the surface of the substrate; a reference ground pad is provided between adjacent first differential pair via holes and second differential pair via holes. A reference ground pad is provided between the first differential pair via hole and the second differential pair via hole. The reference ground pad is coupled to the reference ground via hole. The reference ground pad can connect the first differential pair via hole and the second differential pair via hole. Isolate the vias to reduce crosstalk between the first differential pair vias and the second differential pair vias.

In a possible implementation, the second positive differential via and the second negative differential via are symmetrically arranged on both sides of the extension line of the first virtual line segment. The second positive differential via and the second negative differential via are symmetrically arranged on both sides of the extension line of the first virtual line segment. The second positive differential via and the second negative differential via are affected by the first positive differential via (or the second negative differential via). The interference of the first positive differential via (or the first negative differential via) by the second positive differential via and the second negative differential via is consistent, so it can be achieved Elimination of crosstalk.

In a possible implementation, the substrate includes a plurality of first differential pair via holes and a plurality of second differential pair via holes, and the plurality of first differential pair via holes and the plurality of second differential pair via holes are arranged in a plurality of There are multiple rows and columns; the first differential pair via holes and the second differential pair via holes in each row parallel to the first direction are alternately arranged. In this way, crosstalk can be reduced or eliminated for both the first differential pair via holes and the second differential pair via holes adjacent along the first direction.

In a possible implementation, the substrate includes a plurality of first differential pair via holes and a plurality of second differential pair via holes, and the plurality of first differential pair via holes and the plurality of second differential pair via holes are arranged in a plurality of There are multiple rows and columns; the first differential pair via holes and the second differential pair via holes in each column parallel to the second direction are alternately arranged. In this way, crosstalk can be reduced or eliminated for both the first differential pair via holes and the second differential pair via holes adjacent along the second direction.

In a possible implementation, the substrate includes a plurality of first differential pair via holes and a plurality of second differential pair via holes, and the plurality of first differential pair via holes and the plurality of second differential pair via holes are arranged in a plurality of Rows and columns; the first differential pair via holes and the second differential pair via holes in each row parallel to the first direction are alternately arranged, and the first differential pair via holes and the second differential pair via holes in each column parallel to the second direction Arrange alternately. In this way, crosstalk can be reduced or eliminated for the first differential pair via holes and the second differential pair via holes adjacent along the first direction and the second direction, and the crosstalk elimination effect is good.

In a possible implementation, the substrate further includes a plurality of first reference ground vias, and the first reference ground vias are located in the substrate; along the first direction, aligned with the reference ground pad immediately adjacent to the first differential pair pad. A first reference ground via is provided. This arrangement pattern, on the one hand, can obtain the impedance continuity of high-frequency and high-speed signals. On the other hand, it can facilitate the layout of differential pair signal lines.

In a possible implementation, the substrate further includes a plurality of first reference ground vias, and the first reference ground vias are located in the substrate; along the first direction, the first differential pair pads and the first differential pair are connected to each other. A first reference ground via hole is provided between adjacent reference ground pads. This arrangement pattern, on the one hand, can obtain the impedance continuity of high-frequency and high-speed signals. On the other hand, it can facilitate the layout of differential pair signal lines.

In a possible implementation, the substrate further includes a plurality of second reference ground vias, and the second reference ground vias are located in the substrate; along the first direction, the second differential pair pads and the second differential pair are connected to each other. A second reference ground via hole is provided between the reference ground pads on the side immediately adjacent to the bonding pads; along the second direction, a second reference ground via hole is provided in alignment with the reference ground pads immediately adjacent to the second differential pair pad. This arrangement pattern, on the one hand, can obtain the impedance continuity of high-frequency and high-speed signals. On the other hand, it can facilitate the layout of differential pair signal lines.

In a possible implementation, the substrate further includes a plurality of second reference ground vias, and the second reference ground vias are located in the substrate; the second reference ground pads immediately adjacent to the second differential pair pads are aligned with the second reference ground vias. Ground vias. This arrangement pattern, on the one hand, can obtain the impedance continuity of high-frequency and high-speed signals. On the other hand, it can facilitate the layout of differential pair signal lines.

In a possible implementation, the substrate includes a plurality of first differential pair via holes and a plurality of second differential pair via holes, and the plurality of first differential pair via holes and the plurality of second differential pair via holes are arranged in a plurality of rows and columns; the substrate also includes a first signal line layer, the first signal line layer is provided with a first differential pair signal line and a second differential pair signal line; the first differential pair signal line and the first differential pair in the first row Via coupling, the second differential pair signal line is coupled to the second differential pair via hole in the first row; the first differential pair signal line extends between the first differential pair via hole and the second differential pair via hole to the outlet side of the substrate; the second differential pair signal line extends between the second positive differential via hole and the second negative differential via hole to the outlet side of the substrate. This arrangement of differential signal lines has relatively small requirements on line width and has a wide range of applications.

In a possible implementation, the substrate further includes a second signal line layer, and the second signal line layer is provided with a first differential pair signal line and a second differential pair signal line; the first differential pair signal line in the second signal line layer The line is coupled to the first differential pair via hole in the second row, the second differential pair signal line is coupled to the second differential pair via hole in the second row; the first differential pair signal line and the second differential pair signal line Through between the first differential pair via hole and the second differential pair via hole in the first row, extend to the outlet edge of the substrate. This arrangement of differential signal lines has relatively small requirements on line width and has a wide range of applications.

In a possible implementation, the substrate includes a stacked dielectric layer and a core layer, and the first differential pair via hole and the second differential pair via hole penetrate the core layer; the substrate is a packaging substrate; the material of the dielectric layer includes Ajinomoto stack membrane. This is a possible application scenario.

In a possible implementation, the substrate includes a dielectric layer, the first differential pair of via holes and the second differential pair of via holes penetrate the dielectric layer; the substrate is a printed circuit board or a download board, and the material of the dielectric layer includes a prepreg. This is a possible application scenario.

A second aspect of the embodiment of the present application provides a chip packaging structure, including a chip, a packaging substrate and a download board; the packaging substrate is the substrate of any one of the first aspects; the download board is the substrate of any one of the first aspects; the chip It includes a first-stage first differential pair pin and a first-stage second differential pair pin. The first-stage first differential pair pin is coupled to the first differential pair via hole in the packaging substrate. The first-stage second differential pair The pins are coupled to the second differential pair via holes in the packaging substrate; the chip packaging structure also includes a second-level first differential pair pin and a second-level second differential pair pin located on the side of the packaging substrate away from the chip; The first differential pair pins of the second stage are respectively coupled to the first differential pair via holes in the packaging substrate and the first differential pair via holes in the download board. The second differential pair pins of the second stage are coupled to the second differential pair via holes in the packaging substrate. are respectively coupled to the second differential pair via holes in the download board.

A third aspect of the embodiment of the present application provides a chip packaging structure, including a chip and a packaging substrate; the packaging substrate is the substrate of any one of the first aspects; the chip includes a first-level first differential pair pin and a first-level first differential pair pin. Two differential pair pins, the first differential pair pin of the first stage is coupled to the first differential pair via hole, and the second differential pair pin of the first stage is coupled to the second differential pair via hole.

A fourth aspect of the embodiment of the present application provides a chip packaging structure, including a chip, an adapter board and a packaging substrate that are stacked in sequence; the adapter board includes a third differential via and a fourth differential via located in the adapter plate. hole. The third differential pair via hole includes the third positive differential via hole and the third negative differential via hole; the fourth differential pair via hole is located in the adapter board, and the fourth differential pair via hole includes the fourth positive differential via hole and the fourth negative differential via hole. Differential vias; the third differential pair vias and the fourth differential pair vias are arranged in a T shape, or it can be understood that the fourth positive differential vias and the fourth negative differential vias are respectively arranged at the extension of the third virtual line segment On both sides of the line; the fourth positive differential via and the fourth negative differential via are located at the same end of the third virtual line segment. Among them, the third virtual line segment is a virtual line segment connecting the third positive differential via hole and the third negative differential via hole on the surface of the adapter board; the chip includes a first-level first differential pair pin and a first-level second differential pair The first differential pair pin of the first stage is coupled to the third differential pair via hole, and the second differential pair pin of the first stage is coupled to the fourth differential pair via hole.

In the chip packaging structure provided by the embodiment of the present application, by arranging the fourth positive differential via and the fourth negative differential via in the adapter board on both sides of the extension line of the third virtual line segment, the fourth positive differential via and the fourth negative differential via are The four negative differential vias are simultaneously interfered by the third positive differential via (or the third negative differential via). According to the characteristics of the differential signal, the signals of the fourth positive differential via and the fourth negative differential via are different, and the interferences received by the fourth positive differential via and the fourth negative differential via cancel each other out, so the crosstalk can be reduced. . In the case where the fourth positive differential via and the fourth negative differential via are symmetrically arranged on both sides of the extension line of the third virtual line segment, the fourth positive differential via and the fourth negative differential via are affected by the third positive differential via. The interference of the holes (or the third negative differential via) is consistent, so crosstalk can be eliminated.

In a possible implementation, the fourth positive differential via and the fourth negative differential via are symmetrically arranged on both sides of the extension line of the third virtual line segment. The fourth positive differential via and the fourth negative differential via are symmetrically arranged on both sides of the extension line of the third virtual line segment, and the fourth positive differential via and the fourth negative differential via are protected by the third positive differential via (or the fourth negative differential via). The interference of the three negative differential vias) is consistent, and the interference of the third positive differential via (or the third negative differential via) by the fourth positive differential via and the fourth negative differential via is consistent, so it can be achieved Elimination of crosstalk.

In a possible implementation, the chip packaging structure further includes a first rewiring layer, which is provided on the side of the adapter board facing the chip; the first differential pair pins of the first level pass through the first rewiring layer Coupled with the third differential pair via hole, the second differential pair pin of the first stage is coupled with the fourth differential pair via hole through the first redistribution layer. This is one possible structure.

In a possible implementation, the chip packaging structure further includes a second rewiring layer, the second rewiring layer is provided on the side of the transfer board facing the packaging substrate; the third differential pair via hole and the fourth differential pair via hole pass through The second redistribution layer is coupled to the packaging substrate. This is one possible structure.

In a possible implementation, the material of the adapter plate includes silicon, glass or ceramics. This is one possible structure.

A fifth aspect of the embodiment of the present application provides an electronic device, including a chip packaging structure and a printed circuit board; the chip packaging structure is provided on the printed circuit board; the chip packaging structure is the second aspect, the third aspect, or the fourth aspect. In any one of the chip packaging structures, the printed circuit board is the substrate in any one of the first aspects.

In a possible implementation, the electronic device further includes a connector, and the connector is located between the chip packaging structure and the printed circuit board.

A sixth aspect of the embodiment of the present application provides a substrate. The substrate may be a PCB, a download board, or a packaging substrate. The substrate includes: a first differential pair pad, located on the surface of the substrate; the first differential pair pad includes a first positive differential pad and a first negative differential pad; a second differential pair pad, located on the surface of the substrate, the second differential pair The bonding pads include a second positive differential bonding pad and a second negative differential bonding pad; the second positive differential bonding pad and the second negative differential bonding pad are respectively disposed on both sides of the extension line of the fourth virtual line segment; and the second positive differential bonding pad The pad and the second negative differential pad are located at the same end of the fourth virtual line segment; wherein the fourth virtual line segment is a virtual line segment connecting the first positive differential pad and the first negative differential pad on the surface of the substrate.

In the substrate provided by the embodiment of the present application, by arranging the second positive differential pad and the second negative differential pad on both sides of the extension line of the first virtual line segment, the second positive differential pad and the second negative differential pad are simultaneously Interference from the first positive differential pad (or the first negative differential pad). According to the characteristics of the differential signal, the signals of the second positive differential pad and the second negative differential pad are different, and the interferences received by the second positive differential pad and the second negative differential pad cancel each other out, so the crosstalk can be reduced. . In the case where the second positive differential pad and the second negative differential pad are symmetrically arranged on both sides of the extension line of the first virtual line segment, the second positive differential pad and the second negative differential pad are affected by the first positive differential pad. The interference of the pad (or the first negative differential pad) is consistent, so crosstalk can be eliminated. For example, the interference of the second positive differential pad by the first positive differential pad is 5mV, the interference of the second negative differential pad by the first positive differential pad is also 5mV, the second positive differential pad and the second negative differential pad The signals on the pads are different, and the interference can cancel each other out. On the contrary, mutual cancellation of interference can also be achieved.

In a possible implementation, the substrate further includes a first differential pair signal line and a second differential pair signal line; the first differential pair signal line is coupled to the first differential pair pad, and the second differential pair signal line is coupled to the first differential pair pad. Two differential pairs of pads are coupled; the first differential pair signal line and the second differential pair signal line are located in the substrate and are arranged on the same layer. In this case, the second differential pair signal line may be located on the same side of the first differential pair signal line, that is, the second positive differential signal line and the second negative differential signal line are located on the same side of the first differential pair signal line. It is possible to achieve no intersection between the first differential pair signal line and the second differential pair signal line. Then, the first differential pair signal line and the second differential pair signal line can be arranged on the same layer to reduce the number of layers of signal lines in the substrate, thereby reducing the thickness of the substrate and reducing the cost of the substrate.

In a possible implementation, the substrate further includes a reference ground pad located on the surface of the substrate; the first differential pair pad and the second differential pair pad are arranged along the first direction; along the second direction, the second differential pair A reference ground pad is provided on at least one side of the pad, and the second differential pair pad and the reference ground pad are located on the same straight line; wherein the first direction intersects with the second direction. The second differential pair pad and the reference ground pad are located on the same straight line. Then the second positive differential pad and the second negative differential pad are arranged in the reference ground pad array. Only the first positive differential pad and the second differential pad need to be changed. The arrangement pattern of negative differential pads is enough, and the changes to the substrate structure are small.

In a possible implementation, the substrate further includes: a first differential pair of vias, located in the substrate; the first differential pair of vias includes a first positive differential via and a first negative differential via; the first positive differential via The hole is aligned with the first positive differential pad and coupled to the first positive differential pad; the first negative differential via is aligned with the first negative differential pad and coupled to the first negative differential pad; Two differential pairs of vias are located in the substrate. The second differential pair of vias includes a second positive differential via and a second negative differential via. The second positive differential via is aligned with the second positive differential pad and is aligned with the second positive differential via. The two positive differential pads are coupled; the second negative differential via is aligned with the second negative differential pad and coupled to the second negative differential pad. The first negative differential via is aligned with the first negative differential pad, and the second positive differential via is aligned with the second positive differential pad, thereby reducing crosstalk between the first differential pair via and the second differential pair via. Or on the basis of elimination, the first differential via hole and the second differential via hole can be easily prepared, and the layout of the first differential via hole and the second differential via hole is simple.

In a possible implementation, the substrate further includes a reference ground pad located on the surface of the substrate; a reference ground pad is provided between adjacent first differential pair pads and second differential pair pads. A reference ground pad is provided between the first differential pair pad and the second differential pair pad. The reference ground pad is coupled to the reference ground pad. The reference ground pad can connect the first differential pair pad and the second differential pair pad. Isolate the pads to reduce crosstalk between the first differential pair pads and the second differential pair pads.

In a possible implementation, the second positive differential pad and the second negative differential pad are symmetrically arranged on both sides of the extension line of the fourth virtual line segment. The second positive differential pad and the second negative differential pad are symmetrically arranged on both sides of the extension line of the first virtual line segment. The second positive differential pad and the second negative differential pad are affected by the first positive differential pad (or the second negative differential pad). The interference from the first positive differential pad (or the first negative differential pad) to the second positive differential pad and the second negative differential pad is consistent, so it can be achieved Elimination of crosstalk.

In a possible implementation, the substrate includes a plurality of first differential pair pads and a plurality of second differential pair pads, and the plurality of first differential pair pads and the plurality of second differential pair pads are arranged in a plurality of There are multiple rows and columns; the first differential pair pads and the second differential pair pads of each row parallel to the first direction are alternately arranged. In this way, crosstalk between the first differential pair pads and the second differential pair pads adjacent along the first direction can be reduced or eliminated.

In a possible implementation, the substrate includes a plurality of first differential pair pads and a plurality of second differential pair pads, and the plurality of first differential pair pads and the plurality of second differential pair pads are arranged in a plurality of There are multiple rows and columns; the first differential pair pads and the second differential pair pads in each column parallel to the second direction are alternately arranged. In this way, the crosstalk between the first differential pair pads and the second differential pair pads adjacent along the second direction can be reduced or eliminated.

In a possible implementation, the substrate includes a stacked dielectric layer and a core layer, and the first differential pair pad and the second differential pair pad are located on the surface of the dielectric layer; the substrate is a packaging substrate; the material of the dielectric layer includes a element accumulation film. This is a possible application scenario.

In a possible implementation, the substrate includes stacked multi-layer dielectric layers, and the first differential pair pad and the second differential pair pad are located on the surface of the multi-layer dielectric layer; the substrate is a printed circuit board or a download board, and the dielectric layer Materials include prepreg. This is a possible application scenario.

A seventh aspect of the embodiments of the present application provides a method for preparing a substrate, which is used to prepare the substrate of any one of the first aspect or the sixth aspect.

An eighth aspect of the embodiments of the present application provides a method for preparing a chip packaging structure, which is used to prepare the chip packaging structure of any one of the second aspect, the third aspect, or the fourth aspect.

Description of the drawings

Figure 1A is a schematic framework diagram of an electronic device provided by an embodiment of the present application;

Figure 1B is a stacked diagram of a chip packaging structure and a PCB illustrating an embodiment of the present application;

Figure 1C is a stacked diagram of another chip packaging structure and PCB illustrating an embodiment of the present application;

Figure 1D is a stacked diagram of another chip packaging structure and PCB illustrating an embodiment of the present application;

Figure 2A is a schematic diagram illustrating the positional relationship between a differential pair via hole and a differential pair pad according to an embodiment of the present application;

Figure 2B is a schematic diagram illustrating the arrangement of another differential pair via hole and differential pair pad according to an embodiment of the present application;

Figure 2C is a schematic diagram of the arrangement pattern of vias illustrating an embodiment of the present application;

Figure 2D is a schematic diagram of the arrangement of solder balls and vias according to an embodiment of the present application;

Figure 3A is a cross-sectional view of a substrate provided by an embodiment of the present application;

Figure 3B is a schematic diagram of the positional relationship between a first differential pair via hole and a second differential pair via hole provided by an embodiment of the present application;

Figure 3C is a schematic diagram of the positional relationship between another first differential pair via hole and a second differential pair via hole provided by an embodiment of the present application;

Figure 3D is a schematic diagram of the positional relationship between another first differential pair via hole and a second differential pair via hole provided by an embodiment of the present application;

Figure 3E is a schematic diagram of the positional relationship between another first differential pair via hole and a second differential pair via hole provided by an embodiment of the present application;

Figure 3F is a schematic diagram of the positional relationship between another first differential pair via hole and a second differential pair via hole provided by an embodiment of the present application;

Figure 4A is a schematic diagram of the positional relationship between differential pair vias and differential pair pads in a substrate provided by an embodiment of the present application;

Figure 4B is a schematic diagram of the positional relationship between differential pair vias and differential pair pads in another substrate provided by an embodiment of the present application;

Figure 4C is a three-dimensional schematic diagram of the positional relationship between differential pair via holes and differential pair pads in a substrate provided by an embodiment of the present application;

Figure 4D is a schematic diagram of the positional relationship between differential pair vias and differential pair pads in yet another substrate provided by an embodiment of the present application;

Figure 4E is a schematic diagram of the positional relationship between differential pair vias and differential pair pads in yet another substrate provided by an embodiment of the present application;

Figure 5 is a schematic diagram of a fan-out route of a differential signal line provided by an embodiment of the present application;

Figure 6A is a schematic diagram of an arrangement of multiple differential pair vias in a row provided by an embodiment of the present application;

Figure 6B is a schematic diagram of another arrangement of multiple differential pair vias in a row provided by an embodiment of the present application;

Figure 6C is a schematic diagram of another arrangement of multiple differential pair vias in a row provided by an embodiment of the present application;

Figure 6D is a schematic diagram of another arrangement of multiple differential pair vias in a row provided by an embodiment of the present application;

Figure 7A is a schematic diagram of another arrangement of multiple differential pair vias in multiple rows and multiple columns provided by an embodiment of the present application;

Figure 7B is a schematic diagram of another arrangement of multiple differential pair vias in multiple rows and multiple columns provided by an embodiment of the present application;

FIG. 7C is a schematic diagram of another arrangement of multiple differential pair vias in a row provided by an embodiment of the present application;

Figure 8A is a schematic diagram of an arrangement of reference ground vias provided by an embodiment of the present application;

Figure 8B is a schematic diagram of another arrangement of reference ground vias provided by an embodiment of the present application;

Figure 8C is a schematic diagram of another arrangement of reference ground vias provided by an embodiment of the present application;

Figure 8D is a schematic diagram of another arrangement of reference ground vias provided by an embodiment of the present application;

Figure 9 is a schematic diagram of a basic arrangement of vias and pads provided by an embodiment of the present application;

Figure 10A is a schematic diagram of a fan-out route of a differential signal line provided by an embodiment of the present application;

Figure 10B is a schematic diagram of the fan-out route of another differential signal line provided by an embodiment of the present application;

Figure 11A is a schematic diagram of a simulation effect of near-end crosstalk provided by an embodiment of the present application;

Figure 11B is a schematic diagram of another near-end crosstalk simulation effect provided by an embodiment of the present application;

Figure 11C is a schematic diagram of a simulation effect of far-end crosstalk provided by an embodiment of the present application;

Figure 11D is a schematic diagram of another far-end crosstalk simulation effect provided by an embodiment of the present application;

Figures 12A-12E are schematic diagrams of the positional relationship between another differential pair pad and a differential pair via provided for embodiments of the present application;

Figure 13A is a stacked diagram of another chip packaging structure and PCB provided by an embodiment of the present application;

Figure 13B is a schematic diagram of the arrangement of the first-level differential pair pins in a chip provided by an embodiment of the present application;

Figure 13C is a schematic diagram of the arrangement of the first-level differential pair pins in another chip provided by an embodiment of the present application;

Figure 13D is a schematic diagram of the arrangement of the second-stage differential pair pins in a packaging substrate provided by an embodiment of the present application;

Figure 13E is a schematic diagram of the arrangement of the second-stage differential pair pins in another packaging substrate provided by an embodiment of the present application;

Figure 14A is a stacked diagram of another chip packaging structure and PCB provided by an embodiment of the present application;

Figure 14B is a schematic diagram of the arrangement of the third-stage differential pair pins in a download board provided by an embodiment of the present application;

Figure 14C is a schematic diagram of the arrangement of the third-stage differential pair pins in another download board provided by the embodiment of the present application;

Figure 15A is a stacked diagram of another chip packaging structure and PCB provided by an embodiment of the present application;

Figure 15B is a schematic diagram of the arrangement of vias in an adapter board provided by an embodiment of the present application;

FIG. 15C is another stacked pattern of a chip packaging structure and a PCB provided by an embodiment of the present application.

Detailed ways

The technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all of the embodiments.

In the following, in the embodiments of the present application, the terms "first", "second", etc. are only used for convenience of description and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, features defined by "first," "second," etc. may explicitly or implicitly include one or more of such features. In the description of this application, unless otherwise stated, "plurality" means two or more.

In the embodiments of the present application, "upper", "lower", "left" and "right" are not limited to the orientations schematically placed relative to the components in the drawings. It should be understood that these directional terms may be relative concepts. , they are used for relative description and clarification, which may change accordingly according to changes in the orientation of the components in the drawings.

In the embodiments of this application, unless the context requires otherwise, throughout the description and claims, the term "comprise" is interpreted as having an open and inclusive meaning, that is, "including, but not limited to." In the description of the specification, the terms "one embodiment," "some embodiments," "exemplary embodiments," "exemplarily," or "some examples" and the like are intended to indicate specific features associated with the embodiment or example. , structures, materials or characteristics are included in at least one embodiment or example of the present disclosure. The schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials or characteristics described may be included in any suitable manner in any one or more embodiments or examples.

When describing some embodiments, the expression "coupled" and its derivatives may be used. For example, some embodiments may be described using the term "coupled" to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited by the content herein.

In the embodiment of this application, "and/or" is just an association relationship describing associated objects, indicating that there can be three relationships, for example, A and/or B, which can mean: A alone exists, and A and A exist simultaneously. B, there are three situations of B alone. In addition, the character "/" in this article generally indicates that the related objects are an "or" relationship.

Exemplary embodiments are described in the embodiments of the present application with reference to cross-sectional views and/or plan views and/or equivalent circuit diagrams that are idealized exemplary drawings. In the drawings, the thickness of layers and regions are exaggerated for clarity. Accordingly, variations from the shapes in the drawings due, for example, to manufacturing techniques and/or tolerances are contemplated. Thus, example embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result from, for example, manufacturing. For example, an etched area shown as a rectangle will typically have curved features. Accordingly, the regions shown in the figures are schematic in nature and their shapes are not intended to illustrate the actual shapes of regions of the device and are not intended to limit the scope of the exemplary embodiments.

An embodiment of the present application provides an electronic device. The electronic equipment is, for example, consumer electronic products, household electronic products, vehicle-mounted electronic products, financial terminal products, and communication electronic products. Among them, consumer electronic products include mobile phones, tablets, laptops, e-readers, personal computers (PC), personal digital assistants (PDA), desktop monitors, Smart wearable products (such as smart watches, smart bracelets), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, drones, etc. Home electronic products include smart door locks, TVs, remote controls, refrigerators, rechargeable small household appliances (such as soymilk machines, sweeping robots), etc. Vehicle-mounted electronic products such as car navigation systems, vehicle-mounted high-density digital video discs (digital video discs, DVDs), etc. Financial terminal products include automated teller machines (ATMs), self-service terminals, etc. Communication electronic products include communication equipment such as servers, memories, and base stations.

The embodiments of this application do not place any special restrictions on the specific form of the above-mentioned terminal equipment. For convenience of explanation, the following description takes the electronic device as a mobile phone as an example.

The embodiments of the present application do not place special restrictions on the specific forms of the above-mentioned electronic devices. For convenience of explanation, the following embodiments take the electronic device as a mobile phone as an example.

In this case, as shown in FIG. 1A , the electronic device 1 mainly includes a display module 2 , a middle frame 3 , a case (also called a battery cover or a back case) 4 and a cover 5 .

The display module 2 has a light-emitting side from which the display screen can be seen and a backside opposite to the light-emitting side. The backside of the display module 2 is close to the middle frame 3 , and the cover 5 is disposed on the light-emitting side of the display module 2 .

The above-mentioned display module 2 includes a display panel (DP). In a possible embodiment of the present application, the display screen is a liquid crystal display (LCD). Or, in another possible embodiment of the present application, the display screen is an organic light-emitting diode (organic lightemitting diode, OLED) display screen.

The cover plate 5 is located on the side of the display module 2 away from the middle frame 3. The cover plate 5 can be, for example, cover glass (CG), and the cover glass can have a certain degree of toughness.

The middle frame 3 is located between the display module 2 and the housing 4. The surface of the middle frame 3 away from the display module 2 is used to install internal components such as batteries, printed circuit boards (PCB), cameras, and antennas. . After the casing 4 and the middle frame 3 are closed, the above-mentioned internal components are located between the casing 4 and the middle frame 3 .

As shown in Figure 1B, the above-mentioned electronic device 1 also includes a chip disposed on the PCB. The chip may include a processor (center processing unit, CPU) chip, a radio frequency chip, a radio frequency power amplifier (power amplifier, PA) chip, or a system-level chip. (system on a chip, SOC), power management integrated circuits (PMIC), memory chips (such as high bandwidth memory (HBM)), audio processor chips, touch screen control chips, NAND flash (flash memory) ), image sensor chips, charging protection chips and other chips. The PCB is used to carry the above-mentioned chips and complete signal interaction with the above-mentioned chips.

In some embodiments, as shown in FIG. 1B , the chip is disposed on the packaging substrate. After being bonded to the packaging substrate to form a chip packaging structure, the packaging substrate is bonded to the PCB.

In other embodiments, as shown in FIG. 1C , the chip is disposed on the packaging substrate, the packaging substrate is bonded to the download board to form a chip packaging structure, and the download board is bonded to the PCB. This chip packaging structure may be called a dual substrate packaging structure, for example.

In some embodiments, as shown in FIG. 1D , the chip is bonded to the adapter board, and after the adapter board and the packaging substrate are bonded to form the chip packaging structure, the packaging substrate is bonded to the PCB. This chip packaging structure may be called a 2.5D packaging structure, for example.

Of course, the chip can also be directly bonded to the PCB, which is not limited in the embodiments of the present application.

Because differential signals have good anti-noise and anti-interference capabilities, they are increasingly used as an internal signal transmission method in electronic equipment. When the signal interaction is completed through differential signals between the chip and the PCB, the crosstalk between the differential signals will seriously affect the signal quality, thereby affecting product performance.

In order to reduce differential crosstalk, in some technologies, the chip is packaged and more reference ground solder balls are added to the packaging substrate. Correspondingly, a reference ground pad and a reference ground via are added to the PCB to isolate the differential signals.

For example, as shown in Figure 2A, a differential pair pad D and a reference ground pad G are provided on the surface of the PCB. The differential pair pad D includes a positive differential pad P and a negative differential pad N. An array of positive differential pads P, negative differential pads N and reference ground pads G is arranged on the same surface of the PCB.

A differential pair via H and a reference ground via g are provided inside the PCB. The differential pair via H includes a positive differential via p and a negative differential via n. The positive differential via p is coupled to the positive differential pad P, and the negative via The differential via n is coupled to the negative differential pad N, and the reference ground via g is coupled to the reference ground pad G.

Please continue to refer to Figure 2A. For example, taking the positive differential pad P and the positive differential via p as an example, the smaller circle with a black edge on the edge represents the positive differential via p, and the larger one with no black edge on the edge represents the positive differential via p. Differential pad P. The positive differential pad P and the positive differential via p are arranged in a staggered manner and coupled through fan-out traces, forming a shape similar to a "dog bone". In the same way, the negative differential pad N and the negative differential via n are arranged in a staggered manner and coupled through fan-out traces, forming a shape similar to a "dog bone".

Regarding the positional relationship between the reference ground via g and the reference ground pad G, the reference ground via g is aligned with the reference ground pad G, and the reference ground via g is located below the reference ground pad G, or it can be understood as a matter of skill in the art. People often refer to the via-in-pad structure. Of course, the reference ground via g and the reference ground pad G may also be disposed in a staggered manner, or it may be understood that the reference ground via g and the reference ground pad G are coupled through fan-out wiring.

Based on the structure shown in Figure 2A, although more reference ground solder balls are added through the package, correspondingly, the reference ground pad G and the reference ground via g are set on the PCB to isolate the differential signals. However, on the one hand, this will increase the chip package size and PCB layout space, resulting in a decrease in the competitiveness of chips and systems. On the other hand, due to the limitations of via size and distance between vias, at most one reference ground via g is added between the positive differential via p and the negative differential via n, which makes it difficult to improve the system competitiveness (such as increasing the signal rate, cost reduction) requirements.

In other technologies, as shown in FIG. 2B , a first differential pair pad D1, a second differential pair pad D2 and a reference ground pad G are provided on the surface of the PCB. The first differential pair pad D1 includes a first positive differential pad P1 and a first negative differential pad N1, and the second differential pair pad D2 includes a second positive differential pad P2 and a second negative differential pad N2.

A first differential pair via hole H1, a second differential pair via hole H2 and a reference ground via hole g are provided inside the PCB. The first differential pair via H1 includes a first positive differential via p1 and a first negative differential via n1. The first positive differential via p1 is located below the first positive differential pad P1 and is coupled to the first positive differential pad P1. The first negative differential via n1 is located below the first negative differential pad N1 and is coupled to the first negative differential pad N1. The second differential pair via H2 includes a second positive differential via p2 and a second negative differential via n2. The second positive differential via p2 is located below the second positive differential pad P2 and is coupled to the second positive differential pad P2. The second negative differential via n2 is located below the second negative differential pad N2 and coupled to the second negative differential pad N2. The reference ground via g is located below the reference ground pad G and is coupled to the reference ground pad G.

As shown in FIG. 2B , the first differential pair pad D1 and the second differential pair pad D2 are arranged orthogonally, and the first differential pair via hole H1 and the second differential pair via hole H2 are arranged orthogonally. Or it can be understood that the first positive differential pad P1 and the first negative differential pad N1 are orthogonally arranged with the second positive differential pad P2 and the second negative differential pad N2, and the first positive differential via p1 and the first negative differential via p1 are arranged orthogonally. The negative differential via n1 is arranged orthogonally with the second positive differential via p2 and the second negative differential via n2.

As shown in Figure 2C, based on the symmetry design between the first differential pair via H1 and the second differential pair via H2, the first positive differential via p1 and the first negative differential via n1 are connected to the second positive differential via The hole p2 and the second negative differential via n2 are vertically orthogonal. The first positive differential via p1 and the first negative differential via n1 are interfered by the second positive differential via p2 (or the second negative differential via n2). Consistently, according to the characteristics of the differential signal, the signal difference between the first positive differential via p1 and the first negative differential via n1 on the receiving side is affected by the difference between the first positive differential via p1 and the first negative differential via n1. When the interference is consistent, crosstalk can be reduced or eliminated after subtraction.

Since the first differential pair via hole H1 and the second differential pair via hole H2 are arranged orthogonally, in order to avoid trace intersection, the fan-out of the first differential pair pad D1 and the second differential pair pad D2 requires routing on different layers. , thus leading to an increase in the number of signal line layers in the PCB and packaging substrate, significantly increasing the cost of the PCB and packaging substrate. In addition, the first differential pair pad D1 and the second differential pair pad D2 are arranged orthogonally, which requires redesigning the package substrate structure and the basic solder ball arrangement array of the package, and is incompatible with the existing package structure. For chip packaging structures with conventional checkerboard solder ball arrangement, crosstalk cannot be effectively reduced.

In some technologies, as shown in FIG. 2D , a first differential pair pin M1 , a second differential pair pin M2 and a reference ground pin n3 are provided on the surface of the chip packaging structure. The first differential pair pin M1 includes a first positive differential pin m1 and a first negative differential pin n1, and the second differential pair pin M2 includes a second positive differential pin m2 and a second negative differential pin n2.

As shown in FIG. 2D , the first differential pair pin M1 and the second differential pair pin M2 are arranged orthogonally. Or it can be understood that the first positive differential pin m1 and the first negative differential pin n1 are orthogonally arranged with the second positive differential pin m2 and the second negative differential pin n2.

Based on the symmetrical design between the first differential pair pin M1 and the second differential pair pin M2, the first positive differential pin m1 and the first negative differential pin n1 are connected with the second positive differential pin m2 and the second negative differential pin M2. The differential pin n2 is vertically orthogonal. The first positive differential pin m1 and the first negative differential pin n1 are interfered by the second positive differential pin m2 (or the second negative differential pin n2) in the same way. According to the differential signal Characteristics of the signal difference between the first positive differential pin m1 and the first negative differential pin n1 on the receiving side, when the interference received by the first positive differential pin m1 and the first negative differential pin n1 is the same , crosstalk can be reduced or eliminated after subtraction.

Since the first differential pair pin M1 and the second differential pair pin M2 are arranged orthogonally, there is a second differential pair pin M2 between the first positive differential pin m1 and the first negative differential pin n1. There is a first differential pair pin M1 between the differential pin m2 and the second negative differential pin n2. Because other signal lines cannot be set between differential pairs of signals. Therefore, in order to avoid wiring interference and intersection, the fan-out of the first differential pair pin M1 and the second differential pair pin M2 needs to be routed on different layers, resulting in an increase in the number of signal line layers in the PCB and packaging substrate, significantly increasing the PCB and Package substrate cost. In addition, the first differential pair pin M1 and the second differential pair pin M2 are arranged orthogonally, which requires redesigning the package substrate structure and the basic solder ball arrangement array of the package, and is incompatible with the existing package structure. For chip packaging structures with conventional solder ball arrangement schemes, crosstalk cannot be effectively reduced.

Based on this, embodiments of the present application provide a substrate to improve the above problems.

Below, several examples are used to schematically illustrate the structure of the substrate provided by the embodiments of the present application.

Example 1

As shown in FIG. 3A , the substrate includes a stacked dielectric layer and a signal line layer disposed between adjacent dielectric layers. Among them, Figure 3A takes the substrate as a PCB or a download board as an example for illustration. The substrate provided by the embodiment of the present application may also be a packaging substrate.

The substrate also includes a first differential pair via hole H1 and a second differential pair via hole H2. The first differential pair via hole H1 and the second differential pair via hole H2 are both located in the substrate.

Wherein, the first differential pair via hole H1 and the second differential pair via hole H2 both extend along the thickness direction of the substrate. The first differential pair via hole H1 and the second differential pair via hole H2 can be the through holes shown in Figure 3A. The first differential pair via hole H1 and the second differential pair via hole H2 may also be blind holes. Alternatively, the first differential pair via hole H1 and the second differential pair via hole H2 may extend to the surface of the substrate, and the first differential pair via hole H1 and the second differential pair via hole H2 may not extend to the surface of the substrate. The embodiments of the present application do not limit this. The following examples take the first differential pair via hole H1 and the second differential pair via hole H2 as through holes as examples.

It should be emphasized that the via holes proposed in the embodiments of this application refer to conductive holes with a conductive function. For example, the via hole can be a plated through hole (PTH), and a plated hole can also be called a metallized hole, which is a conductive structure formed after the entire hole wall is plated with metal. Or, for example, the via can also be a through silicon via (TSV) or a through glass via (TGV).

In some embodiments, the substrate is a through-hole plate, that is, the first differential pair via hole H1 and the second differential pair via hole H2 penetrate the substrate, that is, the first differential pair via hole H1 and the second differential pair via hole H2 Via H2 penetrates each dielectric layer in the substrate. For example, in the field of information and communications technology (ICT), through-hole boards are often used.

As shown in FIG. 3B , the first differential pair via H1 includes a first positive differential via p1 and a first negative differential via n1. The second differential pair via H2 includes a second positive differential via p2 and a second negative differential via n2.

Along the direction intersecting the first virtual line segment O1-O1, the second positive differential via p2 and the second negative differential via n2 are respectively disposed on both sides of the extension line O1-O1' of the first virtual line segment. And along the direction parallel to the first virtual line segment O1-O1, the second positive differential via p2 and the second negative differential via n2 are located at the same end of the first virtual line segment O1-O1. Or it can be understood that the second differential pair via hole H2 is located on the side of the first differential pair via hole H1.

The first virtual line segment O1-O1 is a virtual line segment connecting the first positive differential via p1 and the first negative differential via n1 on the surface of the substrate. It can be understood that one end of the first virtual line segment O1-O1 is located at the center of the first positive differential via p1, and the other end of the first virtual line segment O1-O1 is located at the center of the first negative differential via n1.

Then, along the direction parallel to the first virtual line segment O1-O1, the second positive differential via p2 and the second negative differential via n2 are located at the same end of the first virtual line segment O1-O1. The second positive differential via p2 and the second negative differential via n2 may be located on the side of the end of the first virtual line segment O1-O1 where the first positive differential via p1 is located, or the second positive differential via p2 and the second negative differential via p2 may be located on the side of the first virtual line segment O1-O1. The two negative differential vias n2 are located on the side of the end of the first virtual line segment O1-O1 where the first negative differential via n1 is located. The embodiments of the present application do not limit this.

Or it can be understood that the second positive differential via p2 and the second negative differential via n2 are both arranged on the side of the first positive differential via p1 away from the first negative differential via n1, or the second positive differential via p2 and The second negative differential vias n2 are all arranged on the side of the first negative differential vias n1 away from the first positive differential vias p1.

In addition, the second positive differential via p2 and the second negative differential via n2 are respectively disposed on both sides of the extension line O1-O1′ of the first virtual line segment. It can be understood that the second positive differential via p2 and the second negative differential via The differential via n2 is not located on both sides of the first virtual line segment O1-O1. That is to say, the second positive differential via p2 and the second negative differential via are not provided on both sides of the first differential pair via H1 perpendicular to the first virtual line segment O1-O1 (for example, the dotted rectangular frame area in Figure 3B) n2, the second positive differential via p2 and the second negative differential via n2 are located on one side of the first differential pair via H1, and the second positive differential via p2 and the second negative differential via n2 pass through the first differential pair Holes H1 belong to the positional relationship of adjacent arrangement.

In addition, the second positive differential via p2 and the second negative differential via n2 are respectively disposed on both sides of the extension line O1-O1′ of the first virtual line segment. Then, the second positive differential via p2 and the second negative differential via The second virtual line segment O2-O2 formed by connecting the holes n2 intersects with the extension line O1-O1' of the first virtual line segment, and the second virtual line segment O2-O2 does not intersect with the first virtual line segment O1-O1.

In some embodiments, as shown in FIG. 3B , the second virtual line segment O2-O2 is perpendicular to the extension line O1-O1' of the first virtual line segment.

In other embodiments, as shown in FIG. 3C , the second virtual line segment O2-O2 and the extension line O1-O1' of the first virtual line segment may not be perpendicular, which is not limited in the embodiment of the present application.

In some embodiments, as shown in FIG. 3B and FIG. 3C , the second positive differential via p2 and the second negative differential via n2 are non-mirroringly disposed on both sides of the extension line O1-O1′ of the first virtual line segment.

For example, as shown in Figure 3B, the distance S1 from the second positive differential via p2 to the extension line O1-O1' of the first virtual line segment is the same as the distance S1 from the second negative differential via n2 to the extension line O1-O1 of the first virtual line segment. The distance S2 of ′ is not equal. The distance S1 from the second positive differential via p2 to the extension line O1-O1' of the first virtual line segment can be understood as the distance from the center of the second positive differential via p2 to the extension line O1-O1' of the first virtual line segment. . In the same way, the distance S2 from the second negative differential via n2 to the extension line O1-O1' of the first virtual line segment can be understood as the distance S2 from the center of the second negative differential via n2 to the extension line O1-O1 of the first virtual line segment. 'distance.

It can also be understood that the distance between the second positive differential via p2 and the extension line O1-O1' of the first virtual line segment, and the distance between the second negative differential via n2 and the extension line O1-O1' of the first virtual line segment are not equal. .

In other embodiments, as shown in FIG. 3D , the second positive differential via p2 and the second negative differential via n2 are mirror-image-disposed on both sides of the extension line O1-O1′ of the first virtual line segment.

For example, as shown in Figure 3D, the distance S1 from the second positive differential via p2 to the extension line O1-O1' of the first virtual line segment is the same as the distance S1 from the second negative differential via n2 to the extension line O1-O1 of the first virtual line segment. ′ is equal to the distance S2. It can also be understood that the distance between the second positive differential via p2 and the extension line O1-O1' of the first virtual line segment, and the distance between the second negative differential via n2 and the extension line O1-O1' of the first virtual line segment are equal.

It can be understood from the above description that the extension line O1-O1' of the first virtual line segment intersects the second virtual line segment O2-O2. The first positive differential via p1 and the first negative differential via n1 are arranged in a direction parallel to the extension line O1-O1′ of the first virtual line segment, and the second positive differential via p2 and the second negative differential via n2 are arranged along Arranged parallel to the direction of the second virtual line segment O2-O2. Then, the arrangement direction of the first positive differential via p1 and the first negative differential via n1 intersects with the arrangement direction of the second positive differential via p2 and the second negative differential via n2.

Then, the first differential pair via hole H1 can be understood as including the adjacently arranged first positive differential via hole p1 and the first negative differential via hole n1.

In some embodiments, as shown in FIG. 3D , the first positive differential via p1 and the first negative differential via n1 are arranged immediately adjacent to each other, and no other vias are arranged between the first positive differential via p1 and the first negative differential via n1 via hole structure.

In other embodiments, as shown in FIG. 3E , other vias (such as reference ground vias) are provided between the first positive differential via p1 and the first negative differential via n1 .

In the same way, the second differential pair via hole H2 can be understood as including an adjacent second positive differential via hole p2 and a second negative differential via hole n2.

In some embodiments, as shown in FIG. 3D , the second positive differential via p2 and the second negative differential via n2 are arranged immediately adjacent to each other, and no other positive differential via p2 and the second negative differential via n2 are arranged between them. via hole structure.

In other embodiments, other vias (such as reference ground vias) are provided between the second positive differential via p2 and the second negative differential via n2.

In addition, the embodiment of the present application does not limit the extension direction of the first virtual line segment O1-O1 and the second virtual line segment O2-O2. Along the direction parallel to the first virtual line segment O1-O1, the second differential pair via H2 is located The first differential pair can be on the same side of via H1. The second differential pair via H2 is located on the side of the first differential pair via H1. It can be understood that the first positive differential via p1 and the first negative differential via n1 are located on the second positive differential via p2 and the second negative differential via. On the same side of hole n2, the second positive differential via p2 and the second negative differential via n2 are located on the same side of the first positive differential via p1 and the first negative differential via n1.

In this embodiment of the present application, the horizontal direction in the perspective of Figure 3D is defined as the first direction X, and the vertical direction in the perspective of Figure 3D is defined as the second direction Y. The first direction X and the second direction Y intersect (for example, are perpendicular), and both the first direction X and the second direction Y are perpendicular to the thickness direction of the substrate.

In some embodiments, as shown in Figure 3D, the first virtual line segment O1-O1 extends along the first direction X. Then, the first positive differential via p1 and the first negative differential via n1 are arranged along the first direction X. The second virtual line segment O2-O2 extends along the second direction Y. Then, the second positive differential via p2 and the second negative differential via n2 are arranged along the second direction Y.

Or it can be understood that the first differential pair via hole H1 and the second differential pair via hole H2 are arranged adjacent to each other along the first direction X.

It should be noted that the embodiment of the present application does not limit which of the first positive differential via p1 and the first negative differential via n1 is closer to the second differential pair via H2. As shown in FIG. 3B , the first positive differential via p1 is disposed between the first negative differential via n1 and the second differential pair via H2. Alternatively, as shown in FIG. 3D , the first negative differential via n1 is provided between the first positive differential via p1 and the second differential pair via H2.

Similarly, taking the perspective of Figure 3B as an example, the embodiment of the present application determines which of the second positive differential via p2 and the second negative differential via n2 in the second differential pair via H2 is located on the extension line O1 of the first virtual line segment The upper side of -O1′ and the lower side of the extension line O1-O1′ of the first virtual line segment are not limited. As shown in Figure 3B, the second positive differential via p2 is disposed above the extension line O1-O1' of the first virtual line segment, and the second negative differential via n2 is disposed on the extension line O1-O1' of the first virtual line segment. lower side. Alternatively, as shown in Figure 3D, the second negative differential via n2 is disposed above the extension line O1-O1' of the first virtual line segment, and the second positive differential via p2 is disposed on the extension line O1-O1 of the first virtual line segment. ′ Lower side.

In other embodiments, as shown in FIG. 3F , the first virtual line segment O1-O1 extends along the second direction Y. Then, the first positive differential via p1 and the first negative differential via n1 are arranged along the second direction Y. The second virtual line segment O2-O2 extends along the first direction X. Then, the second positive differential via p2 and the second negative differential via n2 are arranged along the first direction X.

Or it can be understood that the first differential pair via hole H1 and the second differential pair via hole H2 are arranged adjacent to each other along the second direction Y.

It should be noted that the embodiment of the present application does not limit which of the first positive differential via p1 and the first negative differential via n1 is closer to the second differential pair via H2. As shown in FIG. 3F , the first negative differential via n1 is disposed between the first positive differential via p1 and the second differential pair via H2. The first positive differential via p1 may also be provided between the first negative differential via n1 and the second differential pair via H2.

Similarly, taking the perspective of Figure 3F as an example, the embodiment of the present application determines which of the second positive differential via p2 and the second negative differential via n2 of the second differential pair via H2 is located on the extension line O1 of the first virtual line segment The left side of -O1′ and the right side of the extension line O1-O1′ of the first virtual line segment are not limited. As shown in Figure 3F, the second negative differential via n2 is disposed on the left side of the extension line O1-O1' of the first virtual line segment, and the second positive differential via p2 is disposed on the extension line O1-O1' of the first virtual line segment. Right. Alternatively, the second positive differential via p2 is disposed on the left side of the extension line O1-O1' of the first virtual line segment, and the second negative differential via n2 is disposed on the right side of the extension line O1-O1' of the first virtual line segment.

In the substrate provided by the embodiment of the present application, by arranging the second positive differential via p2 and the second negative differential via n2 on both sides of the extension line O1-O1′ of the first virtual line segment, the second positive differential via p2 and The second negative differential via n2 is simultaneously interfered by the first positive differential via p1 (or the first negative differential via n1). According to the characteristics of the differential signal, the signals of the second positive differential via p2 and the second negative differential via n2 are different, and the interferences received by the second positive differential via p2 and the second negative differential via n2 cancel each other out, so it can be achieved Reduction of crosstalk. In the case where the second positive differential via p2 and the second negative differential via n2 are symmetrically arranged on both sides of the extension line O1-O1′ of the first virtual line segment, the second positive differential via p2 and the second negative differential via Hole n2 is uniformly interfered by the first positive differential via p1 (or the first negative differential via n1), so crosstalk can be eliminated. For example, the interference of the second positive differential via p2 by the first positive differential via p1 is 5mV, the interference of the second negative differential via n2 by the first positive differential via p1 is also 5mV, and the interference of the second positive differential via p2 is also 5mV. By making a difference with the signal of the second negative differential via n2, the interference can cancel each other out.

On the contrary, the signals transmitted by the second positive differential via p2 and the second negative differential via n2 are signals with opposite polarities. Therefore, according to the opposite polarity characteristics, the interference of the second positive differential via p2 and the second negative differential via n2 on the first positive differential via p1 (or the first negative differential via n1) also cancels each other, so that Achieve crosstalk reduction. In the case where the second positive differential via p2 and the second negative differential via n2 are symmetrically arranged on both sides of the extension line O1-O1′ of the first virtual line segment, the first positive differential via p1 (or the first negative differential via The interference of the via n1) by the second positive differential via p2 and the second negative differential via n2 is consistent, so crosstalk can be eliminated. For example, the interference of the first positive differential via p1 by the second positive differential via p2 is 5mV, and the interference of the first positive differential via p1 by the second negative differential via n2 is -5mV. The interference of 5mV and -5mV can be Cancel each other out.

In addition, since the first differential pair via H1 and the second differential pair via H2 are arranged adjacently, the fan-out traces of the first differential pair via H1 and the fan-out traces of the second differential pair via H2 will not intersect. , can be set up on the same layer, without increasing the number of layers of signal lines in the substrate, which can reduce the thickness of the substrate and reduce the cost of the substrate.

On this basis, as shown in FIG. 4A , the substrate also includes a first differential pair pad D1, a second differential pair pad D2, and a reference ground pad G.

The first differential pair pad D1 includes a first positive differential pad P1 and a first negative differential pad N1. The first positive differential pad P1 is coupled to the first positive differential via p1. The first negative differential pad N1 is coupled to the first positive differential via p1. The first negative differential via n1 is coupled.

In some embodiments, as shown in FIG. 4A , the first positive differential pad P1 and the first negative differential pad N1 are arranged adjacently along the first direction X.

In other embodiments, as shown in FIG. 4B , the first positive differential pad P1 and the first negative differential pad N1 are arranged adjacently along the second direction Y.

Of course, no matter which direction the first positive differential pad P1 and the first negative differential pad N1 are adjacently arranged, a reference ground pad G may be provided between the first positive differential pad P1 and the first negative differential pad N1 , the reference ground pad G may not be provided between the first positive differential pad P1 and the first negative differential pad N1. Figures 4A and 4B are only illustrations without any limitation.

The embodiments of the present application do not limit the positional relationship and coupling method between the first differential pair pad D1 and the first differential pair via hole H1. In some embodiments, as shown in Figure 4B, the first positive differential pad P1 Arranged in a staggered manner with the first positive differential via p1, the first positive differential pad P1 and the first positive differential via p1 are coupled through wires. The first negative differential pad N1 and the first negative differential via n1 are arranged in a staggered manner, and the first negative differential pad N1 and the first negative differential via n1 are coupled through wires.

As shown in Figure 4C, the first positive differential pad P1 and the first positive differential via p1 are arranged in a staggered manner. It can be understood that along the thickness direction of the substrate, the first positive differential via p1 is not disposed on the first positive differential via p1. Directly below disk P1. The first negative differential pad N1 and the first negative differential via n1 are arranged in a staggered manner. It can be understood that along the thickness direction of the substrate, the first negative differential via n1 is not disposed directly below the first negative differential pad N1.

The embodiment of the present application does not limit the specific position of the first positive differential via p1. For example, as shown in FIG. 4B, four pads are provided at the four top corners of the first positive differential via p1. The distance from the differential via p1 to the four pads is equal. Four soldering pads are provided at four top corners of the first negative differential via n1, and the first negative differential via n1 is equidistant from the four soldering pads.

Similarly, as shown in Figure 4B, the second differential pair pad D2 includes a second positive differential pad P2 and a second negative differential pad N2, and the second positive differential pad P2 is coupled to the second positive differential via p2. , the second negative differential pad N2 is coupled to the second negative differential via n2.

In some embodiments, the second positive differential pad P2 and the second negative differential pad N2 are adjacently disposed along the first direction X.

In other embodiments, as shown in FIG. 4B , the second positive differential pad P2 and the second negative differential pad N2 are arranged adjacently along the second direction Y.

Of course, no matter in which direction the second positive differential pad P2 and the second negative differential pad N2 are adjacently arranged, a reference ground pad G may be provided between the second positive differential pad P2 and the second negative differential pad N2 , the reference ground pad G may not be provided between the second positive differential pad P2 and the second negative differential pad N2.

The embodiments of the present application do not limit the positional relationship and coupling method between the second differential pair pad D2 and the second differential pair via hole H2. In some embodiments, as shown in Figure 4B and Figure 4C, the second positive differential pair The via p2 is aligned with the second positive differential pad P2, and the second negative differential via n2 is aligned with the second negative differential pad N2. Or it can be understood that along the thickness direction of the substrate, the second positive differential via p2 is located below the second positive differential pad P2, and the second negative differential via n2 is located below the second negative differential pad N2.

Or it can be understood that the orthographic projection of the second positive differential via p2 on the substrate surface is located within the orthographic projection of the second positive differential pad P2 on the substrate surface. The cross-sectional area of the second positive differential pad P2 may be larger than the cross-sectional area of the second positive differential via p2, and the cross-sectional area of the second positive differential pad P2 may also be equal to the cross-sectional area of the second positive differential via p2. .

The orthographic projection of the second negative differential via n2 on the substrate surface is located within the orthographic projection of the second negative differential pad N2 on the substrate surface. The cross-sectional area of the second negative differential pad N2 may be greater than the cross-sectional area of the second negative differential via n2, and the cross-sectional area of the second negative differential pad N2 may also be equal to the cross-sectional area of the second negative differential via n2 .

In other embodiments, as shown in FIG. 4D , the second positive differential pad P2 and the second positive differential via p2 are arranged in a staggered manner, and the second positive differential pad P2 and the second positive differential via p2 are coupled through wires. catch. The second negative differential pad N2 and the second negative differential via n2 are arranged in a staggered manner, and the second negative differential pad N2 and the second negative differential via n2 are coupled through wires.

It should be noted that FIG. 4A to FIG. 4D are illustrated by taking the second positive differential pad P2 and the second negative differential pad N2 symmetrically disposed on both sides of the extension line O1-O1′ of the first virtual line segment as an example. , but the embodiment of the present application is not limited to this, and the positions of the first differential pair via hole H1 and the second differential pair via hole H2 can be reasonably adjusted.

As shown in FIG. 4D , the first positive differential pad P1, the first negative differential pad N1, the second positive differential pad P2, the second negative differential pad N2 and a plurality of reference ground pads G array are arranged on the substrate. s surface.

The first positive differential pad P1, the first negative differential pad N1, the second positive differential pad P2, the second negative differential pad N2 and the plurality of reference ground pad G arrays are arranged on the same surface of the substrate. It can be understood that That is, along the first direction X, the distance between adjacent pads (for example, between the reference ground pad G and the first positive differential pad P1) is equal. Along the second direction Y, the distance between adjacent pads (eg, between adjacent reference ground pads G) is equal.

Since the solder balls of the current mainstream chip packaging structure are arranged in an array on the packaging substrate, the substrate provided by the embodiment of the present application has the first positive differential pad P1, the first negative differential pad N1, the second positive differential pad The pad P2, the second negative differential pad N2 and the multiple reference ground pad G arrays are arranged on the same surface of the substrate. There is no need to change the solder ball arrangement of the chip package structure to be bonded to the substrate, and it is compatible with existing The chip packaging structure of the checkerboard solder ball arrangement scheme has a wide range of applications.

In some embodiments, as shown in FIG. 4D , the first differential pair via hole H1 and the second differential pair via hole H2 are disposed immediately adjacent to each other, and no reference ground pad G is disposed between them.

In other embodiments, as shown in FIG. 4E , a reference ground pad G is provided between the first differential pair via hole H1 and the second differential pair via hole H2.

It can be understood that a reference ground pad G is provided between the first differential pair via hole H1 and the second differential pair via hole H2. It can be understood that the projection of the reference ground pad G on the substrate surface is located between the projections of the first differential pair via hole H1 and the second differential pair via hole H2 on the substrate surface.

According to needs, one or more rows of reference ground pads G may be provided between the first differential pair via hole H1 and the second differential pair via hole H2. FIG. 4E is only an illustration without any limitation.

A reference ground pad G is provided between the first differential pair via hole H1 and the second differential pair via hole H2. The reference ground pad G is coupled to the reference ground via hole. The reference ground pad G can connect the first differential pair via hole H1 to the second differential pair via hole H2. The hole H1 and the second differential pair via hole H2 are isolated to reduce crosstalk between the first differential pair via hole H1 and the second differential pair via hole H2.

Among them, the embodiment of the present application does not make a limit on whether the reference ground pad G and the reference ground via holes are arranged in a staggered manner, or whether the reference ground pad G and the reference ground via holes are arranged in alignment. Just set it up. An example of the arrangement of the reference ground vias will be given later.

In some embodiments, as shown in FIG. 5 , the substrate further includes a first differential pair signal line L1 and a second differential pair signal line L2.

The first differential pair signal line L1 includes a first positive differential signal line Lp1 and a first negative differential signal line Ln1. The first positive differential signal line Lp1 and the first negative differential signal line Ln1 are immediately disposed on the same signal line layer, and are on the same signal line layer. No other signal lines are provided between the first positive differential signal line Lp1 and the first negative differential signal line Ln1 in the signal line layer. In the same way, the second differential pair signal line L2 includes a second positive differential signal line Lp2 and a second negative differential signal line Ln2. The second positive differential signal line Lp2 and the second negative differential signal line Ln2 are immediately arranged on the same signal line layer. And no other signal lines are provided between the second positive differential signal line Lp2 and the second negative differential signal line Ln2 in the signal line layer.

The first differential pair signal line L1 is coupled to the first differential pair via hole H1, and the second differential pair signal line L2 is coupled to the second differential pair via hole H2. That is to say, the first positive differential signal line Lp1 is coupled to the first positive differential via p1, and the first negative differential signal line Ln1 is coupled to the first negative differential via n1. The second positive differential signal line Lp2 is coupled to the second positive differential via p2, and the second negative differential signal line Ln2 is coupled to the second negative differential via n2.

Among them, the first differential pair signal line L1 and the second differential pair signal line L2 are located in the substrate and are arranged on the same layer.

That is to say, the first differential pair signal line L1 and the second differential pair signal line L2 are located on the same dielectric layer. The first positive differential signal line Lp1, the first negative differential signal line Ln1, the second positive differential signal line Lp2 and the second negative differential signal line Ln2 are arranged on the same layer. The first positive differential signal line Lp1 and the first negative differential signal line Ln1 They are arranged closely together without the second positive differential signal line Lp2 or the second negative differential signal line Ln2 between them. The second positive differential signal line Lp2 and the second negative differential signal line Ln2 are arranged immediately adjacent to each other, without the first positive differential signal line Lp1 or the first negative differential signal line Ln1 between them.

It should be noted that the arrangement of the first differential pair signal line L1 and the second differential pair signal line L2 illustrated in FIG. 5 is only an illustration without any limitation.

In the embodiment of the present application, along the direction parallel to the first virtual line segment O1-O1, the second positive differential via p2 and the second negative differential via n2 are disposed on the same side of the first differential pair via H1. Therefore, the first virtual line segment O1-O1 does not intersect the second virtual line segment O2-O2. In this case, by reasonably setting the arrangement of the first differential pair signal line L1 and the second differential pair signal line L2, it is possible to achieve no intersection between the first differential pair signal line L1 and the second differential pair signal line L2. Then, the first differential pair signal line L1 and the second differential pair signal line L2 can be placed on the same layer to reduce the number of layers of signal lines in the substrate and thin the substrate.

In some embodiments, as shown in FIG. 6A , the substrate includes a plurality of first differential pair vias H1 and a plurality of second differential pair vias H2 , a plurality of first differential pair vias H1 and a plurality of second differential pairs. The via holes H2 are arranged along the first direction X.

The embodiments of the present application do not limit the number of first differential vias and second differential vias. In FIG. 6A , the number of first differential vias and the number of second differential vias are equal is taken as an example for illustration. The numbers of the first differential vias and the second differential vias may also be unequal.

The embodiment of the present application does not limit the manner in which the plurality of first differential pair vias H1 and the plurality of second differential pair vias H2 are arranged along the first direction H1 and the second differential pair via H2 are enough.

In a possible implementation, as shown in FIG. 6A , a plurality of first differential pair via holes H1 and a plurality of second differential pair via holes H2 are arranged in a line. The row direction is a direction parallel to the first direction X.

In some embodiments, as shown in FIG. 6A , along the first direction X, a plurality of first differential pair via holes H1 and a plurality of second differential pair via holes H2 are at least partially arranged in an alternating pattern.

Among them, a plurality of first differential pair vias H1 and a plurality of second differential pair vias H2 are alternately arranged along the first direction X, which means that along the first direction X, there is one first differential via and one second differential via. The vias are arranged alternately. The two first differential pair via holes H1 will not be adjacent, nor will the two second differential pair via holes H2 be adjacent.

For example, as shown in FIG. 6A , along the first direction cloth.

Or, for example, along the first direction Arranged in the manner of H1.

Or, for example, along the first direction Arranged in the manner of H2.

By alternately arranging a plurality of first differential pair vias H1 and a plurality of second differential pair vias H2 along the first direction X, crosstalk can be achieved between any two adjacent differential vias along the first direction X. Reduce to meet system requirements for crosstalk.

In other embodiments, as shown in FIG. 6B , along the first direction The second differential pair via hole H2, the second differential pair via hole H2, and the first differential pair via hole H1 are regularly arranged.

In some embodiments, as shown in FIG. 6C , along the first direction The first differential pair via hole H1 and the second differential pair via hole H2 that are arranged adjacently are sufficient.

The arrangement of the plurality of first differential pair vias H1 and the plurality of second differential pair vias H2 illustrated in FIGS. 6A to 6C is only a schematic and is not subject to any limitation. It can be set appropriately as needed.

In addition, regardless of the regular arrangement of the first differential pair via hole H1 and the second differential pair via hole H2, in some embodiments, as shown in FIGS. 6A to 6C , at least some of the adjacent first differential pair via holes are The reference ground pad G may not be disposed between H1 and the second differential pair via hole H2, and the first differential via hole and the second differential via hole are disposed closely adjacent to each other.

In other embodiments, as shown in FIG. 6D , a reference ground pad G may be provided between at least part of the adjacent first differential pair via hole H1 and the second differential pair via hole H2.

In another possible implementation, as shown in FIG. 7A , a plurality of first differential pair via holes H1 and a plurality of second differential pair via holes H2 are arranged in multiple rows.

The embodiment of the present application does not limit the arrangement of the first differential pair via hole H1 and the second differential pair via hole H2 in each row. You may refer to the above description of the multiple first differential pair via holes H1 and the multiple second differential pair via holes H1. Schematic diagram of the arrangement of the first differential pair via H1 and the second differential pair via H2 when the vias H2 are arranged in a row.

The arrangement rules of the first differential pair via hole H1 and the second differential pair via hole H2 in each row may be the same or different, and the embodiment of the present application does not limit this.

In some embodiments, as shown in FIG. 7A , the arrangement rules of the first differential pair via hole H1 and the second differential pair via hole H2 in each row are the same.

For example, as shown in FIG. 7A , along the column direction, that is, along the second direction Y, the first differential pair via hole H1 and the second differential pair via hole H2 are not adjacently arranged.

Or, as an example, as shown in FIG. 7B , along the column direction, that is, along the second direction Y, the substrate also includes adjacently arranged first differential pair via holes H1 and second differential pair via holes H2.

Among them, along the second direction Y, the substrate includes a first differential pair via hole H1 and a second differential pair via hole H2 that are adjacently arranged. Here, it is necessary to perform the first differential pair via hole H1 and the second differential pair via hole H2. Give special instructions.

As shown in FIG. 7C , the first differential pair via hole H1 and the second differential pair via hole H2 are arranged along the second direction Y, and the first positive differential via hole p1 and the first negative differential via hole n1 are arranged along the second direction Y. cloth, the second positive differential via p2 and the second negative differential via n2 are arranged along the first direction X.

The first positive differential via p1 is coupled to the first positive differential pad P1, and the first negative differential via n1 is coupled to the first negative differential pad N1. The second positive differential via p2 is coupled to the second positive differential pad P2, and the second negative differential via n2 is coupled to the second negative differential pad N2. Of course, the embodiment of the present application does not include the relative positional relationship between the first positive differential via p1 and the first positive differential pad P1, the relative positional relationship between the first negative differential via n1 and the first negative differential pad N1, the second positive differential via The relative positional relationship between the differential via p2 and the second positive differential pad P2 and the relative positional relationship between the second negative differential via n2 and the second negative differential pad N2 are not limited, and are only an illustration in FIG. 7C .

Comparing Figure 7B and Figure 7C, it can be seen that from the second direction Y, the first differential pair via hole H1 in Figure 7B can be equivalent to the second differential pair via hole H2 in Figure 7C. The second differential pair via hole H2 in Figure 7B The pair of vias H2 may be equivalent to the first differential pair of vias H1 in FIG. 7C , except that the names are different.

Therefore, as shown in FIG. 7B , when a plurality of first differential pair via holes H1 and a plurality of second differential pair via holes H2 are arranged in multiple rows and multiple columns in the substrate, the arrangement along the first direction For the structures of the first differential pair via hole H1 and the second differential pair via hole H2, please refer to the above-mentioned descriptions of FIGS. 6A to 6D. The structure of each column of the first differential pair via hole H1 and the second differential pair via hole H2 arranged along the second direction Y. The first differential pair via hole H1 illustrated in Figure 7B can be understood as the structure of the first differential pair via hole H1 shown in Figure 6A-Figure 6D The second differential pair via hole H2 shown in FIG. 7B can be understood as the first differential pair via hole H1 in FIG. 6A to FIG. 6D .

For example, as shown in FIG. 7B , in the first direction X, the first differential pair via hole H1 and the second differential pair via hole H2 are alternately arranged in each row. Along the second direction Y, the first differential pair via holes H1 and the second differential pair via holes H2 are alternately arranged in each column.

In this way, along the first direction X, crosstalk between any adjacent first differential pair via hole H1 and second differential pair via hole H2 can be reduced or eliminated. Along the second direction Y, crosstalk between any closely adjacent first differential pair via hole H1 and second differential pair via hole H2 can be reduced or eliminated. The crosstalk elimination effect in the entire substrate is good, which can meet the requirements of products with high crosstalk elimination requirements.

The above describes the first differential pair via H1 and the first differential pair pad D1, and the second differential pair via H2 and the second differential pair pad D2. Next, the positional relationship between the reference ground via hole and the reference ground pad G in the substrate is described. The relative positional relationship between the reference ground via hole and the reference ground pad G can be reasonably set as needed, and the embodiments of the present application are not limited to this.

In some embodiments, as shown in FIG. 8A , the substrate further includes a plurality of first reference ground vias g1 , and the first reference ground vias g1 are coupled to the reference ground pad G.

Among them, the first reference ground via hole g1, the first differential pair via hole H1 and the second differential pair via hole H2 are all located in the substrate. The first reference ground via hole g1 may be a through hole or a blind hole.

For example, as shown in Figure 8A, the first differential pair via H1 and the first differential pair pad D1 are arranged in a staggered manner. Along the first direction X, the reference ground pad G is immediately adjacent to the first differential pair pad D1. A first reference ground via g1 is aligned below.

That is to say, the first reference ground via g1 is aligned below the reference ground pad G located immediately adjacent to the first positive differential pad P1 and located on the left side of the first positive differential pad P1. Immediately adjacent to the first positive differential pad P1, a first reference ground via g1 is aligned below the reference ground pad G located on the right side of the first positive differential pad P1.

Immediately adjacent to the first negative differential pad N1, a first reference ground via g1 is aligned below the reference ground pad G located on the left side of the first negative differential pad N1. Immediately adjacent to the first negative differential pad N1, a first reference ground via g1 is aligned below the reference ground pad G located on the right side of the first negative differential pad N1.

Then, four adjacent first reference ground vias g1 are provided around the first differential pair via hole H1.

Wherein, the first reference ground via hole g1 is aligned with the reference ground pad G, and the reference ground pad G only needs to cover the first reference ground via hole g1.

Or, for example, as shown in FIG. 8B , the first differential pair via H1 and the first differential pair pad D1 are arranged in a staggered manner. Along the first direction A first reference ground via g1 is provided between the reference ground pads G immediately adjacent to the pad D1.

That is to say, the first reference ground via g1 is provided between the reference ground pad G located on the left side of the first positive differential pad P1 and the first positive differential pad P1 immediately adjacent to the first positive differential pad P1. . A first reference ground via g1 is provided between the reference ground pad G located on the right side of the first positive differential pad P1 and the first positive differential pad P1 immediately adjacent to the first positive differential pad P1.

A first reference ground via g1 is provided between the reference ground pad G located on the left side of the first negative differential pad N1 and the first negative differential pad N1 immediately adjacent to the first negative differential pad N1. A first reference ground via g1 is provided between the reference ground pad G located on the right side of the first negative differential pad N1 and the first negative differential pad N1 immediately adjacent to the first negative differential pad N1.

Wherein, a first reference ground via g1 is provided between the first positive differential pad P1 and the reference ground pad G. The first reference ground via g1 may be located between the first positive differential pad P1 and the reference ground pad G. On the connection line, the first reference ground via g1 can also be located on both sides of the connection line between the first positive differential pad P1 and the reference ground pad G. The embodiment of the present application does not limit this, and it can be arranged reasonably as needed. .

Similarly, a first reference ground via g1 is provided between the first negative differential pad N1 and the reference ground pad G. The first reference ground via g1 may be located between the first negative differential pad N1 and the reference ground pad G. On the connection line, the first reference ground via g1 can also be located on both sides of the connection line between the first negative differential pad N1 and the reference ground pad G. The embodiment of the present application does not limit this, and the layout can be reasonably arranged as needed. Can.

However, it should be understood that, as shown in FIG. 8B , the first reference ground via g1 and the first positive differential via p1 and the first negative differential via n1 should be spaced apart to avoid short circuits.

The above-mentioned arrangement of the first reference ground via g1, the reference ground pad G, and the first differential pair pad D1 provided by the embodiment of the present application can, on the one hand, obtain impedance continuity of high-frequency and high-speed signals. On the other hand, it can facilitate the layout of differential pair signal lines. Regarding the layout of the differential pair signal lines, the following is a detailed illustration.

Of course, when the second positive differential via p2 is misaligned with the second positive pad, and the second negative differential via n2 is misaligned with the second negative pad, the third differential via hole H2 on the periphery of the second differential pair is misaligned. The arrangement of the two reference ground vias can also refer to the above description about the first reference ground via g1.

In other embodiments, as shown in Figure 8C, the substrate further includes a plurality of second reference ground vias g2, and the second reference ground vias g2 are coupled to the reference ground pad G.

The second reference ground via hole g2 is located in the substrate, and the second reference ground via hole g2 may be a through hole or a blind hole.

For example, as shown in FIG. 8C , the second positive differential via p2 is aligned with the second positive differential pad P2, and the second negative differential via n2 is aligned with the second negative differential pad N2. Along the first direction X, a second reference ground via g2 is provided between the second differential pair pad D2 and the reference ground pad G on one side immediately adjacent to the second differential pair pad D2.

That is to say, along the first direction X, a second reference ground via g2 is provided between the second differential pair pad D2 and the left reference ground pad G immediately adjacent to the second differential pair pad D2. That is, along the first direction X, a second reference ground via g2 is provided between the second positive differential pad P2 and the reference ground pad G on the left side of the second positive differential pad P2. A second reference ground via g2 is provided between the second negative differential pad N2 and the reference ground pad G on the left side of the second negative differential pad N2.

Alternatively, along the first direction X, a second reference ground via g2 is provided between the second differential pair pad D2 and the right reference ground pad G adjacent to the second differential pair pad D2. That is, along the first direction X, a second reference ground via g2 is provided between the second positive differential pad P2 and the reference ground pad G on the right side of the second positive differential pad P2. A second reference ground via g2 is provided between the second negative differential pad N2 and the reference ground pad G on the right side of the second negative differential pad N2.

Wherein, a second reference ground via g2 is provided between the second positive differential pad P2 and the reference ground pad G. The second reference ground via g2 may be located between the second positive differential pad P2 and the reference ground pad G. On the connection line, the second reference ground via g2 can also be located on both sides of the connection line between the second positive differential pad P2 and the reference ground pad G. The embodiment of the present application does not limit this, and it can be arranged appropriately according to needs. .

In the same way, a second reference ground via g2 is provided between the second negative differential pad N2 and the reference ground pad G. The second reference ground via g2 may be located between the second negative differential pad N2 and the reference ground pad G. On the connection line, the second reference ground via g2 can also be located on both sides of the connection line between the second negative differential pad N2 and the reference ground pad G. The embodiment of the present application does not limit this, and the layout can be reasonably arranged as needed. Can.

On this basis, along the second direction Y, a second reference ground via g2 is aligned below the reference ground pad G immediately adjacent to the second differential pair pad D2.

That is to say, along the second direction Y, the second reference ground via hole g2 is aligned below the reference ground pad G located on the side (upper side) of the second positive differential pad P2 away from the second negative differential pad N2. , a second reference ground via g2 is aligned below the reference ground pad G located on the side (lower side) of the second negative differential pad N2 away from the second positive differential pad P2.

This is equivalent to saying that there are four second reference ground vias g2 around the second differential pair via hole H2. Of course, if there is no reference ground pad G on the lower side of the second negative differential via n2, the second reference ground via g2 may not be provided on the lower side of the second negative differential via n2.

Or, for example, as shown in FIG. 8D , the second positive differential via p2 is aligned with the second positive differential pad P2, and the second negative differential via n2 is aligned with the second negative differential pad N2. A second reference ground via g2 is provided in alignment with the lower side of the reference ground pad G which is immediately adjacent to the second differential pair pad D2.

That is to say, along the first direction X, the second reference ground via g2 is aligned below the reference ground pad G that is immediately adjacent to the second differential pair pad D2. Along the second direction Y, a second reference ground via g2 is also aligned below the reference ground pad G that is adjacent to the second differential pair pad D2.

That is, along the first direction X, a second reference ground via g2 is provided between the second differential pair pad D2 and the left reference ground pad G immediately adjacent to the second differential pair pad D2. That is, along the first direction X, a second reference ground via g2 is provided between the second positive differential pad P2 and the reference ground pad G on the left side of the second positive differential pad P2. A second reference ground via g2 is provided between the second negative differential pad N2 and the reference ground pad G on the left side of the second negative differential pad N2.

Moreover, along the first direction X, a second reference ground via g2 is provided between the second differential pair pad D2 and the right reference ground pad G adjacent to the second differential pair pad D2. That is, along the first direction X, a second reference ground via g2 is provided between the second positive differential pad P2 and the reference ground pad G on the right side of the second positive differential pad P2. A second reference ground via g2 is provided between the second negative differential pad N2 and the reference ground pad G on the right side of the second negative differential pad N2.

Moreover, along the second direction Y, a second reference ground via g2 is aligned below the reference ground pad G located on the side (upper side) of the second positive differential pad P2 away from the second negative differential pad N2, and is located at A second reference ground via g2 is aligned below the reference ground pad G on the side (lower side) of the second negative differential pad N2 away from the second positive differential pad P2.

Then, six adjacent second reference ground vias g2 are provided around the second differential pair via hole H2.

Of course, when the first positive differential via p1 is aligned with the first positive pad, and the first negative differential via n1 is aligned with the first negative pad, the first reference on the periphery of the first differential pair via H1 The arrangement of the ground via hole g1 may also refer to the above description about the second reference ground via hole g2.

The arrangement of the second reference ground via g2, the reference ground pad G, and the second differential pair pad D2 provided by the embodiment of the present application can, on the one hand, improve the impedance continuity in the reference ground pad G. On the other hand, it can facilitate the layout of differential pair signal lines. Regarding the layout of the differential pair signal lines, the following is a detailed illustration.

As shown in Figure 9, when multiple first differential pair via holes H1 and multiple second differential pair via holes H2 are arranged in multiple rows and multiple columns, the first differential pair pad D1 and the second differential pair pad D1 in the substrate Pad D2 is also arranged in multiple rows and columns.

The arrangement of the first reference ground via g1 on the periphery of the first differential pair pad D1 in each row can be as shown in Figure 8A or Figure 8B , and the second reference ground on the periphery of the second differential pair pad D2 in each row. The arrangement of vias g2 can be as shown in Figure 8C or Figure 8D.

The arrangement of the first reference ground vias g1 on the periphery of the first differential pair pad D1 in the same row may be the same or different. The arrangement of the first reference ground vias g1 on the periphery of the first differential pair pad D1 in different rows may be the same or different.

Similarly, the arrangement of the second reference ground vias g2 on the periphery of the second differential pair pad D2 in the same row may be the same or different. The arrangement of the second reference ground vias g2 on the periphery of the second differential pair pad D2 in different rows may be the same or different.

Among them, as shown in Figure 9, when only one row of reference ground pads G is provided between the first differential pair pad D1 and the second differential pair pad D2, the first differential pair pad D1 and the second differential pair pad D2 The first reference ground via g1 and the second reference ground via g2 between the differential pair pads D2 may overlap.

In some embodiments, as shown in FIG. 9 , a plurality of first differential pair via holes H1 and a plurality of second differential pair via holes H2 are arranged in two rows and multiple columns.

The arrangement of the first reference ground via g1 on the periphery of the first differential pair pad D1 in the up row can be referred to as shown in Figure 8A, and the second reference ground via g1 on the periphery of the second differential pair pad D2 and the second reference on the periphery of the pad G. The arrangement of the ground via g2 can be referred to as shown in Figure 8D.

The arrangement of the first reference ground via g1 on the periphery of the first differential pair pad D1 in the downstream direction can be referred to as shown in Figure 8B, and the second reference ground via g1 on the periphery of the second differential pair pad D2 and the second reference on the periphery of the pad G. The arrangement of the ground via g2 can be referred to as shown in Figure 8C.

This facilitates the arrangement of differential signal lines. Below, an example is given to illustrate the arrangement of differential signal lines.

In some embodiments, as shown in FIG. 10A , the substrate further includes a first signal line layer provided with a first differential pair signal line L1 and a second differential pair signal line L2.

The first differential pair signal line L1 is coupled to the first differential pair via hole H1 in the first row, and the second differential pair signal line L2 is coupled to the second differential pair via hole H2 in the first row. The first differential pair via hole H1 and the second differential pair via hole H2 in the first row are adjacent to the outlet edge of the substrate.

The first differential pair signal line L1 includes a first positive differential signal line Lp1 and a first negative differential signal line Ln1, and the second differential pair signal line L2 includes a second positive differential signal line Lp2 and a second negative differential signal line Ln2. Then, the first differential pair signal line L1 is coupled to the first differential pair via H1 in the first row. It can be understood that the first positive differential signal line Lp1 is coupled to the first positive differential via p1 in the first row. , the first negative differential signal line Ln1 is coupled to the first negative differential via n1 in the first row. The second differential pair signal line L2 is coupled to the second differential pair via H2 in the first row. It can be understood that the second positive differential signal line Lp2 is coupled to the second positive differential via p2 in the first row. The two negative differential signal lines Ln2 are coupled to the second negative differential via n2 in the first row.

As shown in Figure 10A, the first differential pair signal line L1 extends between the first differential pair via hole H1 and the second differential pair via hole H2 to the outlet edge of the substrate, and the second differential pair signal line L2 passes through the second positive pair. Between the differential via p2 and the second negative differential via n2, it extends to the outlet edge of the substrate.

Of course, since the first reference ground via hole g1 and the second reference ground via hole g2 are located inside the substrate, the first differential pair via hole H1 and the second differential pair via hole H2 are located inside the substrate. Therefore, as shown in Figure 10A, the first differential pair signal line L1 and the second differential pair signal line L2 in the first signal line layer and the first reference ground via hole g1 and the second reference ground via hole g2 should be arranged in a staggered manner. , the first differential pair signal line L1 and the second differential pair signal line L2 are not coupled to the first reference ground via hole g1 and the second reference ground via hole g2.

As shown in FIG. 10B , the substrate further includes a second signal line layer, and the second signal line layer is also provided with a first differential pair signal line L1 and a second differential pair signal line L2.

The first signal line layer and the second signal line layer may be the same signal line layer, and the first signal line layer and the second signal line layer may be different signal line layers.

Please continue to refer to Figure 10B. The first differential pair signal line L1 in the second signal line layer is coupled to the first differential pair via hole H1 in the second row. The second differential pair signal line L2 is coupled to the second differential pair signal line L2 in the second row. Differential pair via H2 is coupled. The first differential pair via hole H1 and the second differential pair via hole H2 in the second row are provided on the side of the first row of the first differential pair via hole H1 and the second differential pair via hole H2 away from the outlet edge of the substrate.

The first differential pair signal line L1 includes a first positive differential signal line Lp1 and a first negative differential signal line Ln1, and the second differential pair signal line L2 includes a second positive differential signal line Lp2 and a second negative differential signal line Ln2. Then, the first differential pair signal line L1 is coupled to the first differential pair via H1 in the second row. It can be understood that the first positive differential signal line Lp1 is coupled to the first positive differential via p1 in the second row. , the first negative differential signal line Ln1 is coupled to the first negative differential via n1 in the second row. The second differential pair signal line L2 is coupled to the second differential pair via H2 in the second row. It can be understood that the second positive differential signal line Lp2 is coupled to the second positive differential via p2 in the second row. The two negative differential signal lines Ln2 are coupled to the second negative differential via n2 in the second row.

As shown in Figure 10B, the first differential pair signal line L1 and the second differential pair signal line L2 extend between the first differential pair via hole H1 and the second differential pair via hole H2 in the first row to the outgoing line of the substrate. side.

The first differential pair signal line L1 and the second differential pair signal line L2 can extend to the outlet edge of the substrate through the same pair of first differential pair via holes H1 and second differential pair via holes H2 in the first row. As shown in FIG. 10B , the first differential pair signal line L1 and the second differential pair signal line L2 may also extend between different pairs of first differential pair via holes H1 and second differential pair via holes H2 in the first row. The outlet side of the substrate.

Of course, since the first reference ground via hole g1 and the second reference ground via hole g2 are located inside the substrate, the first differential pair via hole H1 and the second differential pair via hole H2 are located inside the substrate. Therefore, as shown in FIG. 10B , the first and second differential pair signal lines L1 and L2 in the second signal line layer are misaligned with the first and second reference ground vias g1 and g2 .

It should be emphasized that due to the limitations of the gap size between adjacent via holes and the width of the signal lines, the arrangement of the first differential pair signal line L1 and the second differential pair signal line L2 shown in Figure 10A and Figure 10B has a simple process. Easy to implement.

Of course, according to the different line widths of the first differential pair signal line L1 and the second differential pair signal line L2, the first differential pair signal line L1 and the second differential pair signal line L2 can be arranged in different ways. The first reference ground The via g1 and the second reference ground via g2 can also be arranged in different ways. The embodiment of this application illustrates the arrangement of the first reference ground via g1 and the second reference ground via g2, and the first differential The arrangement of the signal line L1 and the second differential pair signal line L2 is only an illustration without any limitation.

After simulation, it is found that comparing the substrate boards in Figure 9 and Figure 2, along the first direction X, the near-end crosstalk (NEXT) of the first differential pair via H1 and the second differential pair via H2 is as shown in the figure As shown in 11A, the near-end crosstalk of the first differential pair via hole H1 and the second differential pair via hole H2 in the substrate provided by the embodiment of the present application is significantly reduced. Among them, the abscissa in Figure 11A is frequency, and the ordinate is near-end crosstalk.

Along the second direction Y, the near-end crosstalk of the first differential pair via hole H1 and the second differential pair via hole H2 is as shown in Figure 11B. The first differential pair via hole H1 and the second differential pair via hole H1 in the substrate provided by the embodiment of the present application The near-end crosstalk on via H2 is significantly reduced.

Along the first direction The near-end crosstalk on via H1 and the second differential pair via H2 is significantly reduced. Among them, the abscissa in Figure 11C is frequency, and the ordinate is far-end crosstalk.

Along the second direction Y, the far-end crosstalk of the first differential pair via hole H1 and the second differential pair via hole H2 is as shown in Figure 11D. The first differential pair via hole H1 and the second differential pair via hole H1 in the substrate provided by the embodiment of the present application The near-end crosstalk on via H2 is significantly reduced.

Therefore, in the substrate provided by the embodiment of the present application, without changing the pad array arrangement on the surface of the substrate, by reasonably setting the arrangement of the first differential pair via hole H1 and the second differential pair via hole H2 in the substrate, it can be realized The first differential pair via H1 and the second differential pair via H2 reduce or eliminate near-end crosstalk and far-end crosstalk. On this basis, by rationally setting the fan-out method of the first differential pair via hole H1 and the second differential pair via hole H2, the number of layers of signal lines in the substrate can be reduced.

Embodiments of the present application also provide a method for preparing a substrate, which is used to prepare the above-mentioned substrate. The embodiment of the present application does not limit the formation method of the first differential pair via hole H1, the second differential pair via hole H2, the first differential pair bonding pad D1, and the second differential pair bonding pad D2 in the substrate. It is sufficient that the first differential pair via H1, the second differential pair via H2, the first differential pair pad D1, and the second differential pair pad D2 satisfy the above schematic positional relationship.

Example 2

The main difference between this example and Example 1 is that in this example, the first differential pair pad D1 and the first differential pair via hole H1 are under-disk hole structures, and the second differential pair pad D2 and the second differential pair via hole are H2 is the subplate hole structure.

An embodiment of the present application also provides a substrate. As shown in FIG. 12A , the substrate includes a first differential pair via hole H1 and a second differential pair via hole H2.

The first differential pair via H1 includes a first positive differential via p1 and a first negative differential via n1. The second differential pair via H2 includes a second positive differential via p2 and a second negative differential via n2. Along the direction intersecting the first virtual line segment O1-O1, the second positive differential via p2 and the second negative differential via n2 are respectively disposed on both sides of the extension line O1-O1' of the first virtual line segment. And along the direction parallel to the first virtual line segment O1-O1, the second positive differential via p2 and the second negative differential via n2 are located at the same end of the first virtual line segment O1-O1. Or it can be understood that the second differential pair via hole H2 is located on the side of the first differential pair via hole H1.

The structure and positional relationship between the first differential pair via hole H1 and the second differential pair via hole H2 are the same as Example 1. Please refer to the relevant description in Example 1.

On this basis, please continue to refer to FIG. 12A , the substrate also includes a first differential pair pad D1 and a second differential pair pad D2.

The first differential pair pad D1 is located on the surface of the substrate. The first differential pair pad D1 includes a first positive differential pad P1 and a first negative differential pad N1; the first positive differential via p1 and the first positive differential pad P1 is aligned and coupled to the first positive differential pad P1. The first negative differential via n1 is aligned with the first negative differential pad N1 and coupled to the first negative differential pad N1.

The second differential pair pad D2 is located on the surface of the substrate. The second differential pair pad D2 includes a second positive differential pad P2 and a second negative differential pad N2; the second positive differential via p2 and the second positive differential pad P2 is aligned and coupled to the second positive differential pad P2. The second negative differential via n2 is aligned with the second negative differential pad N2 and coupled to the second negative differential pad N2.

That is to say, in this example, the first positive differential pad P1 and the first positive differential via p1 have an under-disk hole structure, and the first negative differential pad N1 and the first negative differential via n1 have an under-disk hole structure. The second positive differential pad P2 and the second positive differential via p2 have an under-disk hole structure, and the second negative differential pad N2 and the second negative differential via n2 have an under-disk hole structure.

That is, the arrangement rules of the first differential pair pad D1 and the first differential pair via hole H1 are the same, and the arrangement rules of the second differential pair pad D2 and the second differential pair via hole H2 are the same.

In this way, on the basis of reducing or eliminating the crosstalk between the first differential pair via H1 and the second differential pair via H2, the first differential via and the second differential via can be easily prepared, and the first differential via hole and second differential via layout is simple.

In some embodiments, as shown in FIG. 12A , the first differential pair pad D1 and the second differential pair pad D2 are disposed in close proximity.

In some embodiments, as shown in FIG. 12B , the substrate also includes a reference ground pad G located on the surface of the substrate; a reference ground pad is provided between the adjacent first differential pair pad D1 and the second differential pair pad D2 G.

In some embodiments, as shown in FIG. 12B , the first differential pair via hole H1 and the second differential pair via hole H2 are arranged along the first direction X, and the first positive differential pad P1 and the first negative differential pad N1 arranged along the first direction X. Along the second direction Y, a reference ground pad G is provided on at least one side of the second differential pair pad D2, and the second differential pair pad D2 and the reference ground pad G are located on the same straight line.

Wherein, the second differential pair pad D2 and the reference ground pad G are located on the same straight line. It can be understood that both the second positive differential pad P2 and the second negative differential pad N2 are located on the same straight line as the reference ground pad G.

The second differential pair pad D2 and the reference ground pad G are located on the same straight line. Then the second positive differential pad P2 and the second negative differential pad N2 are arranged in an array with the reference ground pad G. Only the first positive differential pad needs to be changed. The arrangement of the differential pad P1 and the first negative differential pad N1 is sufficient, and the changes to the substrate structure are small.

In other embodiments, as shown in FIG. 12C , the first differential pair via hole H1 and the second differential pair via hole H2 are arranged along the first direction X, and the first positive differential pad P1 and the first negative differential pad N1 is arranged along the first direction X. Along the first direction X, a reference ground pad G is provided on at least one side of the first positive differential pair pad, and the first positive differential pair pad and the reference ground pad G are located on the same straight line.

Wherein, the first differential pair pad D1 and the reference ground pad G are located on the same straight line. It can be understood that both the first positive differential pad P1 and the first negative differential pad N1 are located on the same straight line as the reference ground pad G.

In the same way, the first differential pair pad D1 and the reference ground pad G are located on the same straight line, then the array arrangement of the first positive differential pad P1 and the first negative differential pad N1 and the reference ground pad G only needs to be changed. The arrangement of the second positive differential pad P2 and the second negative differential pad N2 is sufficient, and the changes to the substrate structure are small.

Of course, as shown in Figure 12D, the first differential pair via hole H1 and the second differential pair via hole H2 can also be arranged along the second direction Y. The structure of the first differential pair via hole H1 and the second differential pair via hole H2 For the relationship, reference can be made to the structural relationship between the first differential pair via hole H1 and the second differential pair via hole H2 when they are arranged along the first direction X, which will not be described again here.

In some embodiments, as shown in FIG. 12E , a plurality of first differential pair via holes H1 and a plurality of second differential pair via holes H2 are arranged in multiple rows and multiple columns in the substrate.

Comparing Figure 12D and Figure 12E, it can be seen that from the second direction Y, the first differential pair via hole H1 in Figure 12E can be equivalent to the second differential pair via hole H2 in Figure 12D, and the second differential pair via hole H2 in Figure 12E The pair of vias H2 may be equivalent to the first differential pair of vias H1 in FIG. 12D , except that the names are different.

Therefore, as shown in FIG. 12E , when a plurality of first differential pair via holes H1 and a plurality of second differential pair via holes H2 are arranged in multiple rows and multiple columns in the substrate, the arrangement along the first direction For the structures of the first differential pair via hole H1 and the second differential pair via hole H2, please refer to the above-mentioned descriptions of FIGS. 12A to 12C. The structure of each column of the first differential pair via hole H1 and the second differential pair via hole H2 arranged along the second direction Y. The first differential pair via hole H1 illustrated in Figure 12E can be understood as the structure of the first differential pair via hole H1 shown in Figure 12A-Figure 12C The second differential pair via hole H2 shown in FIG. 12E can be understood as the first differential pair via hole H1 in FIG. 12A to FIG. 12C .

For example, as shown in FIG. 12E , in the first direction X, the first differential pair via hole H1 and the second differential pair via hole H2 are alternately arranged in each row. Along the second direction Y, the first differential pair via holes H1 and the second differential pair via holes H2 are alternately arranged in each column.

In this way, along the first direction X, crosstalk between any adjacent first differential pair via hole H1 and second differential pair via hole H2 can be reduced or eliminated. Along the second direction Y, crosstalk between any closely adjacent first differential pair via hole H1 and second differential pair via hole H2 can be reduced or eliminated. The crosstalk elimination effect in the entire substrate is good, which can meet the requirements of products with higher crosstalk elimination requirements.

Taking FIG. 12E as an example, in some embodiments, the second differential pair via hole H2 and the reference ground pad G are located on the same straight line, and the first differential pair via hole H1 and the reference ground pad G are not located on the same straight line. The first positive differential via p1 and the two reference ground pads G on its left side form an isosceles triangle, and the first negative differential via n1 and the two reference ground pads G on its right side form an isosceles triangle.

Therefore, the substrate provided by the embodiment of the present application can realize the first differential by changing the arrangement pattern of the pads on the surface of the substrate and by reasonably setting the arrangement of the first differential pair via hole H1 and the second differential pair via hole H2 in the substrate. Reduce or eliminate near-end crosstalk and far-end crosstalk on via H1 and the second differential pair via H2. On this basis, both the first differential pair via hole H1 and the second differential pair via hole H2 adopt an under-disk hole structure, which can simplify the process.

Embodiments of the present application also provide a method for preparing a substrate, which is used to prepare the above-mentioned substrate. The embodiment of the present application does not limit the formation method of the first differential pair via hole H1, the second differential pair via hole H2, the first differential pair bonding pad D1, and the second differential pair bonding pad D2 in the substrate. It is sufficient that the first differential pair via H1, the second differential pair via H2, the first differential pair pad D1, and the second differential pair pad D2 satisfy the above schematic positional relationship. Example three

An embodiment of the present application also provides a substrate, which may be a packaging substrate, a PCB or a download board. Please continue to refer to FIG. 12A. The substrate includes a first differential pair pad D1 and a second differential pair pad D2 located on the surface of the substrate.

The first differential pair pad D1 includes a first positive differential pad P1 and a first negative differential pad N1, and the second differential pair pad D2 includes a second positive differential pad P2 and a second negative differential pad N2. The second positive differential pad P2 and the second negative differential pad N2 are respectively disposed on both sides of the extension line of the fourth virtual line segment; and the second positive differential pad P2 and the second negative differential pad N2 are located on the fourth virtual line segment. of the same end. The fourth virtual line segment is a virtual line segment connecting the first positive differential pad P1 and the first negative differential pad N1 on the surface of the substrate.

For a description of the positional relationship between the first differential pair pad D1 and the second differential pair pad D2, please refer to the correlation between the first differential pair via hole H1 and the second differential pair via hole H2 in Example 1 and Example 2. describe.

In some embodiments, the first differential pair pad D1 and the second differential pair pad D2 may refer to the related description of the first differential pair pad D1 and the second differential pair pad D2 in Example 2.

In some embodiments, the substrate further includes a first differential pair via H1 and a second differential pair via H2.

The embodiment of the present application does not limit the relative positional relationship between the first differential pair via H1 and the first differential pair pad D1 and the relative positional relationship between the second differential pair via H2 and the second differential pair pad D2.

In some embodiments, the relative positional relationship between the first differential pair via H1 and the first differential pair pad D1 and the relative positional relationship between the second differential pair via H2 and the second differential pair pad D2 can be referred to Example 2. The relevant descriptions will not be repeated here.

In some embodiments, the substrate further includes a first differential pair signal line and a second differential pair signal line.

The first differential pair signal line is coupled to the first differential pair pad D1, and the second differential pair signal line is coupled to the second differential pair pad D2. The first differential pair signal line and the second differential pair signal line are located in the substrate and are arranged on the same layer.

Of course, the first differential pair signal line and the second differential pair signal line may also be located in the substrate and arranged in different layers.

Please continue to refer to FIG. 12A. In some embodiments, the substrate further includes a reference ground pad G.

For the positional relationship between the reference ground pad G and the first differential pair pad D1 and the second differential pair pad D2, please refer to the relevant description in Example 2.

Example 4

An embodiment of the present application also provides an electronic device. The electronic device includes any of the substrates illustrated in Examples 1 and 2.

Embodiments of the present application provide an electronic device. The electronic device includes a chip packaging structure and a PCB. The chip packaging structure is disposed on the PCB, and the chip packaging structure is electrically connected to the PCB.

In some embodiments, as shown in FIG. 13A , the chip packaging structure provided by embodiments of the present application includes a chip and a packaging substrate.

Wherein, the packaging substrate is any of the substrates shown in Example 1 and Example 2. The substrate includes a stacked dielectric layer and a core layer (core). The first differential pair via hole H1 and the second differential pair via hole H2 penetrate the core layer. The first differential pair via hole H1 and the second differential pair via hole H2 pass through the dielectric layer. The blind and buried holes in the chip lead out the signal. The material of the dielectric layer includes Ajinomoto build-up film (ABF), and the material of the core layer includes prepreg. In this case, the first differential pair via hole H1 and the second differential pair via hole H2 may be buried vias.

The chip includes a first-level first differential pair pin A1 and a first-level second differential pair pin A2. The first-level first differential pair pin A1 is coupled to the first differential pair via H1. The first-level second differential pair pin A1 is coupled to the first differential pair via H1. The differential pair pin A2 is coupled to the second differential pair via hole H2 to achieve electrical connection between the chip and the packaging substrate.

The chip packaging structure also includes a second-level first differential pair pin B1 and a second-level second differential pair pin B2 located on the side of the packaging substrate away from the chip. The second-level first differential pair pin B1 is connected to the second-level first differential pair pin B1 in the packaging substrate. The first differential pair via hole H1 is coupled, and the second stage second differential pair pin B2 is coupled to the second differential pair via hole H2 in the packaging substrate.

It can be understood that the first differential pair pin A1 of the first stage is coupled to the first differential pair via hole H1 in the packaging substrate. For example, the first differential pair pin A1 of the first stage can be coupled to the first differential pair pin A1 of the packaging substrate. The differential pair pad D1 is bonded to realize coupling of the first differential pair pin A1 of the first stage and the first differential pair via hole H1 in the packaging substrate.

Among them, the first-stage first differential pair pin A1 includes the first-stage first positive differential pin ap1 and the first-stage first negative differential pin an1. The first-level first positive differential pin ap1 is bonded to the first positive differential pad P1 in the packaging substrate, so as to realize the coupling of the first-level first positive differential pin ap1 with the first positive differential via p1. The first negative differential pin an1 of the first stage is bonded to the first negative differential pad N1 in the packaging substrate, so as to realize the coupling of the first negative differential pin an1 of the first stage and the first negative differential via n1.

Similarly, the first-stage second differential pair pin A2 is coupled to the second differential pair via hole H2 in the packaging substrate. For example, the first-stage second differential pair pin A2 is coupled to the second differential pair in the packaging substrate. Pad D2 is bonded to achieve coupling between the first-stage second differential pair pin A2 and the second differential pair via hole H2 in the package substrate.

The first-stage second differential pair pin A2 includes a first-stage second positive differential pin ap2 and a first-stage second negative differential pin an2. The second positive differential pin ap2 of the first level is bonded to the second positive differential pad P2 in the packaging substrate, so as to realize the coupling of the second positive differential pin ap2 of the first level and the second positive differential via p2. The second negative differential pin an2 of the first stage is bonded to the second negative differential pad N2 in the packaging substrate, so as to realize the coupling of the second negative differential pin an2 of the first stage and the second negative differential via n2.

In some embodiments, the first differential pair pin A1 of the first stage is provided correspondingly to the first differential pair pad D1 in the packaging substrate, and their arrangement rules are the same. The second differential pair pin A2 of the first stage is arranged correspondingly to the second differential pair pad D2 in the packaging substrate, and their arrangement rules are the same.

In some embodiments, the chip also includes a first-level reference ground pin G1, a first-level first positive differential pin ap1, a first-level first negative differential pin an1, The arrangement pattern of the second positive differential pin ap2 of the first level and the second negative differential pin an2 of the first level is consistent with the reference ground pin, the first positive differential pad P1, the first negative differential pad N1, The arrangement rules of the second positive differential pad P2 and the second negative differential pad N2 are the same. Please refer to the relevant descriptions in Example 1 and Example 2, which will not be described again here.

For example, as shown in Figure 13B, the first level reference ground pin G1, the first level first positive differential pin ap1, the first level first negative differential pin an1, the first level second positive differential pin ap2 And the array arrangement of the first-stage and second negative differential pin an2.

Or, for example, as shown in Figure 13C, the first-stage second positive differential pin ap2 and the first-stage second negative differential pin an2 are located in the same row as the first-stage reference ground pin G1, and the first-stage first The positive differential pin ap1 and the first negative differential pin an1 of the first stage are not located in the same row as the first stage reference ground pin G1.

Or, for example, the first positive differential pin ap1 of the first stage and the first negative differential pin an1 of the first stage are located in the same row as the reference ground pin G1 of the first stage, and the second positive differential pin ap2 of the first stage and The first-stage second negative differential pin an2 and the first-stage reference ground pin G1 are not located in the same row.

In some embodiments, the PCB is any of the substrates illustrated in Example 1 and Example 2. The material of the dielectric layer in the PCB includes prepreg, and the material of each dielectric layer may be the same, for example.

In addition, the first differential pair pin B1 of the second stage is coupled to the first differential pair via hole H1 in the PCB and the first differential pair via hole H1 in the packaging substrate respectively, and the second differential pair pin B2 of the second stage is coupled to the first differential pair via hole H1 in the PCB. The second differential pair via hole H2 and the second differential pair via hole H2 in the packaging substrate are respectively coupled to achieve electrical connection between the chip packaging structure and the PCB.

It can be understood that the first differential pair pin B1 of the second stage is coupled to the first differential pair via hole H1 in the PCB, for example, it can be the first differential pair pin B1 of the second stage and the first differential butt welding in the PCB. The pad D1 is bonded to realize the coupling of the second-stage first differential pair pin B1 and the first differential pair via H1.

The second-stage first differential pair pin B1 includes a second-stage first positive differential pin bp1 and a second-stage first negative differential pin bn1. The second-stage first positive differential pin bp1 is bonded to the first positive differential pad P1 in the PCB to achieve coupling of the second-stage first positive differential pin bp1 with the first positive differential via p1. The second-stage first negative differential pin bn1 is bonded to the first negative differential pad N1 in the PCB to achieve coupling of the second-stage first negative differential pin bn1 with the first negative differential via n1.

In the same way, the second differential pair pin B2 of the second stage is coupled to the second differential pair via H2. For example, the second differential pair pin B2 of the second stage can be bonded to the second differential pair pad D2 in the PCB. , to realize the coupling between the second differential pair pin B2 of the second stage and the second differential pair via H2.

The second differential pair pin B2 of the second stage includes a second positive differential pin bp2 of the second stage and a second negative differential pin bn2 of the second stage. The second positive differential pin bp2 of the second stage is bonded to the second positive differential pad P2 in the PCB to realize the coupling of the second positive differential pin bp2 of the second stage with the second positive differential via p2. The second negative differential pin bn2 of the second stage is bonded to the second negative differential pad N2 in the PCB to achieve coupling of the second negative differential pin bn2 of the second stage with the second negative differential via n2.

In some embodiments, the first differential pair pin B1 of the second stage is arranged correspondingly to the first differential pair pad D1 in the PCB, and their arrangement rules are the same. The second differential pair pin B2 of the second stage is set correspondingly to the second differential pair pad D2 in the PCB, and their arrangement rules are the same.

In some embodiments, the chip also includes a second-level reference ground pin, a second-level first positive differential pin bp1, a second-level first negative differential pin bn1, a second-level first reference ground pin, The arrangement pattern of the second positive differential pin bp2 and the second negative differential pin bn2 of the second stage is consistent with the reference ground pin G, the first positive differential pad P1, the first negative differential pad N1, and the second The arrangement rules of the positive differential pad P2 and the second negative differential pad N2 are the same. You can refer to the relevant descriptions in Example 1 and Example 2 and will not repeat them here.

For example, as shown in Figure 13D, the second level reference ground pin G2, the second level first positive differential pin bp1, the second level first negative differential pin bn1, the second level second positive differential pin bp2 And the second stage second negative differential pin bn2 array arrangement.

Or, for example, as shown in Figure 13E, the second positive differential pin bp2 of the second stage and the second negative differential pin bn2 of the second stage are located in the same row as the reference ground pin G2 of the second stage, and the first The positive differential pin bp1 and the second-stage first negative differential pin bn1 are not located in the same row as the second-stage reference ground pin G2.

Or, as an example, the first positive differential pin bp1 of the second stage and the first negative differential pin bn1 of the second stage are located in the same row as the reference ground pin G2 of the second stage, and the second positive differential pins bp2 and The second negative differential pin bn2 of the second stage and the reference ground pin G2 of the second stage are not located in the same row.

In some embodiments, as shown in Figure 14A, the chip packaging structure further includes a download board.

The download board is any of the substrates shown in Example 1 and Example 2. The material of the dielectric layer in the download board includes prepreg. For example, the material of each dielectric layer may be the same. The first differential pair via hole H1 and the second differential pair via hole H2 penetrate at least one dielectric layer.

The download board is disposed between the packaging substrate and the PCB, and is coupled to the packaging substrate and the PCB respectively to achieve coupling between the packaging substrate and the PCB. In this case, the second-stage first differential pair pin B1 and the second-stage second differential pair pin B2 are not directly coupled to the PCB.

Please continue to refer to Figure 14A. The chip is coupled to the packaging substrate through the first differential pair pin A1 of the first stage and the second differential pair pin A2 of the first stage. The packaging substrate is coupled to the packaging substrate through the first differential pair pin B1 of the second stage and the second differential pair pin A2 of the first stage. The secondary second differential pair pin B2 is coupled to the download board.

The chip packaging structure also includes a third-level first differential pair pin C1 and a third-level second differential pair pin C2 located on the side of the download board away from the packaging substrate. The third-level first differential pair pin C1 is connected to the download board. The first differential pair via H1 is coupled to the first differential pair via H1 in the PCB respectively, and the third stage second differential pair pin C2 is connected to the second differential pair via H2 in the download board and the second differential pair in the PCB. The holes H2 are respectively coupled to realize the electrical connection between the download board and the PCB.

It can be understood that the third-level first differential pair pin C1 is coupled to the first differential pair via hole H1 in the PCB, for example, the third-level first differential pair pin C1 is coupled to the first differential pair pad in the PCB. D1 bonding to achieve coupling between the third-level first differential pair pin C1 and the first differential pair via H1 in the PCB.

The third-stage first differential pair pin C1 includes a third-stage first positive differential pin cp1 and a third-stage first negative differential pin cn1. The third-level first positive differential pin cp1 is bonded to the first positive differential pad P1 in the PCB to achieve coupling of the third-level first positive differential pin cp1 with the first positive differential via p1. The third-level first negative differential pin cn1 is bonded to the first negative differential pad N1 in the PCB to achieve coupling between the third-level first negative differential pin cn1 and the first negative differential via n1.

In the same way, the third-level second differential pair pin C2 is coupled to the second differential pair via H2. For example, the third-level second differential pair pin C2 can be bonded to the second differential pair pad D2 in the PCB. , to achieve coupling between the third-stage second differential pair pin C2 and the second differential pair via H2.

The third-stage second differential pair pin C2 includes a third-stage second positive differential pin cp2 and a third-stage second negative differential pin cn2. The third-level second positive differential pin cp2 is bonded to the second positive differential pad P2 in the PCB to achieve coupling of the third-level second positive differential pin cp2 with the second positive differential via p2. The third-level second negative differential pin cn2 is bonded to the second negative differential pad N2 in the PCB to achieve coupling between the third-level second negative differential pin cn2 and the second negative differential via n2.

In some embodiments, the first differential pair pin C1 of the third stage is arranged correspondingly to the first differential pair pad D1 in the PCB, and their arrangement rules are the same. The second differential pair pin C2 of the third stage is set correspondingly to the second differential pair pad D2 in the PCB, and their arrangement rules are the same.

In some embodiments, the chip also includes a third-level reference ground pin G3, a third-level first positive differential pin cp1, a third-level first negative differential pin cn1, and a third-level first positive differential pin cn1. The arrangement pattern of the third-level second positive differential pin cp2 and the third-level second negative differential pin cn2 is consistent with the reference ground pin in the PCB, the first positive differential pad P1, the first negative differential pad N1, and the The two positive differential pads P2 and the second negative differential pad N2 are arranged in the same manner. Please refer to the relevant descriptions in Example 1 and Example 2, which will not be described again here.

For example, as shown in Figure 14B, the third-level reference ground pin G3, the third-level first positive differential pin cp1, the third-level first negative differential pin cn1, and the third-level second positive differential pin cp2 And the third-stage second negative differential pin cn2 array arrangement.

Or, for example, as shown in Figure 14C, the second positive differential pin cp2 of the third stage and the second negative differential pin cn2 of the third stage are located in the same row as the reference ground pin G3 of the third stage, and the first The positive differential pin cp1 and the third-stage first negative differential pin cn1 are not located in the same row as the third-stage reference ground pin G3.

Or, for example, the third-stage first positive differential pin cp1 and the third-stage first negative differential pin cn1 are in the same row as the third-stage reference ground pin G3, and the third-stage second positive differential pin cp2 and The second negative differential pin cn2 of the third stage and the reference ground pin G3 of the third stage are not located in the same row. In the embodiment of the present application, the above-mentioned first-stage first differential pair pin A1, first-stage second differential pair pin A2, second-stage differential first pair pin, and second-stage second differential pair pin B2, the third-level first differential pair pin C1 and the third-level second differential pair pin C2 can be solder bumps (solder bumps), solder balls (solder balls), or copper pillars (Cu pillars).

In some embodiments, as shown in FIG. 15A , the chip packaging structure further includes an interposer. The interposer is disposed between the chip and the packaging substrate. The interposer is coupled to the chip and the packaging substrate respectively.

For example, the material of the adapter board includes silicon, and the chip packaging structure can be understood as a through-silicon via interposer 2.5D packaging (chip-on-wafer-on-substrate, CoWoS) structure.

For example, the material of the adapter board includes glass, and the chip packaging structure can be understood as a glass through hole interposer 2.5D packaging (chip on glass-on-substrate, CoGoS) structure.

For example, the material of the adapter board includes ceramics, and the chip packaging structure can be understood as a ceramic through-hole interposer 2.5D packaging (chip on ceramics-on-substrate, CoCoS) structure.

As shown in Figure 15A, the adapter board also includes a third differential pair via hole H3 and a fourth differential pair via hole H4 located in the adapter board. The third differential pair via hole H3 and the fourth differential pair via hole H4 pass through the adapter board. Connect the board.

As shown in Figure 15B, the third differential pair via H3 includes a third positive differential via p3 and a third negative differential via n3, and the fourth differential pair via H4 includes a fourth positive differential via p4 and a fourth negative differential via. Via n4.

Along the direction intersecting the third virtual line segment O3-O3, the fourth positive differential via p4 and the fourth negative differential via n4 are respectively disposed on both sides of the extension line O3-O3′ of the third virtual line segment, along with the third virtual line segment O3-O3. In the parallel direction of the virtual line segment O3-O3, the fourth positive differential via p4 and the fourth negative differential via n4 are located at the same end of the third virtual line segment O3-O3.

The third virtual line segment is a virtual line segment O3-O3 connecting the third positive differential via p3 and the third negative differential via n3 on the surface of the adapter board.

In some embodiments, as shown in FIG. 15B , the fourth positive differential via p4 and the fourth negative differential via n4 are symmetrically disposed on both sides of the extension line O3-O3' of the third virtual line segment.

In some embodiments, as shown in FIG. 15B , the adapter board further includes a third reference ground via g3 , and the third reference ground via g3 is located in the adapter board.

For the structure and position of the third differential pair via hole H3 in the adapter board, please refer to the relevant description of the first differential pair via hole H1 in Example 1 and Example 2, which will not be described again here. For the structure and position of the fourth differential pair via H4, please refer to the relevant descriptions of the second differential pair via H2 in Example 1 and Example 2, which will not be described again here. For the structure and location of the third reference ground via g3, please refer to the relevant descriptions of the first reference ground via g1 and the second reference ground via g2 in Examples 1 and 2, which will not be described again here.

It should be noted that in some embodiments, the first differential pair pad D1 and the first differential pair via hole H1 in the package substrate are under-disk hole structures, and the second differential pair pad D2 and the second differential pair via hole H2 are It is also a subplate hole structure.

In this case, as shown in FIG. 15A , no rewiring layer may be provided between the chip and the adapter board, and no rewiring layer may be provided between the adapter board and the packaging substrate.

Of course, a rewiring layer can also be provided between the chip and the adapter board, and a rewiring layer can also be provided between the adapter board and the packaging substrate.

In other embodiments, in the package substrate, the first differential pair pad D1 and the first differential pair via hole H1 are arranged in a staggered manner, and the second differential pair pad D2 and the second differential pair via hole H2 are arranged in a staggered manner.

In this case, as shown in FIG. 15C , a first redistribution layer RDL1 is provided between the chip and the adapter board, and a second redistribution layer RDL2 is also provided between the adapter board and the packaging substrate.

The first redistribution layer RDL1 is coupled to the first-level first differential pair pin A1 and the first-level second differential pair pin A2 close to the chip side. The first redistribution layer RDL1 is close to the adapter board side and is coupled to the third The differential pair via H3 and the fourth differential pair via H4 are coupled.

The second redistribution layer RDL2 is coupled to the third differential pair via hole H3 and the fourth differential pair via hole H4 on the side close to the transfer board. The second redistribution layer RDL2 is connected to the first differential pair in the packaging substrate on the side close to the package substrate. Pad D1 (not shown in the figure) is coupled to a second differential pair pad D2 (not shown in the figure).

In some embodiments, the electronic device further includes a connector (socket) located between the chip packaging structure and the PCB.

For example, the connector is located between the packaging substrate and the PCB. The side of the connector close to the packaging substrate is provided with pins respectively coupled to the second-stage first differential pair pin B1 and the second-stage second differential pair pin B2. , the connector is provided with pins coupled to the first differential pair pad D1 and the second differential pair pad D2 on a side close to the PCB.

Or, as an example, the connector is located between the download board and the PCB, and the side of the connector close to the download board is provided with the first differential pair pin C1 of the third stage and the second differential pair pin C2 of the third stage respectively. Coupling pins, the side of the connector close to the PCB is provided with pins corresponding to and coupled to the first differential pair pad D1 and the second differential pair pad D2 respectively.

Embodiments of the present application also provide a method for preparing a chip packaging structure, which is used to prepare any of the above chip packaging structures. The embodiments of this application do not limit the formation method of the first differential pair via H1 and the second differential pair via H2, or the third differential pair via H3 and the fourth differential pair via H4 in the chip packaging structure. It is sufficient that the first differential pair via H1 and the second differential pair via H2, or the third differential pair via H3 and the fourth differential pair via H4 in the chip packaging structure satisfy the above schematic positional relationship.

Of course, when the electronic device includes the substrate shown in Example 3, the coupling relationship between each part of the chip packaging structure and the first differential pair pad D1 and the second differential pair pad D2 in the substrate of Example 3 can be as described above. The coupling relationship between various parts of the chip packaging structure is the same as that of the first differential pair via H1 and the second differential pair via H2 in the substrate of Example 1 or Example 2, and will not be described again here.

The above are only specific embodiments of the present application, but the protection scope of the present application is not limited thereto. Any person familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application. should be covered by the protection scope of this application. Therefore, the protection scope of this application should be subject to the protection scope of the claims.

Claims

A substrate, characterized in that it includes:

A first differential pair of vias is located in the substrate; the first differential pair of vias includes a first positive differential via and a first negative differential via;

A second differential pair via hole is located in the substrate, the second differential pair via hole includes a second positive differential via hole and a second negative differential via hole; the second positive differential via hole and the second negative differential via hole Differential vias are respectively provided on both sides of the extension line of the first virtual line segment; and the second positive differential via and the second negative differential via are located at the same end of the first virtual line segment; wherein, the The first virtual line segment is a virtual line segment that connects the projection of the first positive differential via hole and the projection of the first negative differential via hole on the surface of the substrate.
The substrate according to claim 1, wherein the substrate further includes a first differential pair signal line and a second differential pair signal line;

The first differential pair signal line is coupled to the first differential pair via hole, and the second differential pair signal line is coupled to the second differential pair via hole;

The first differential pair signal line and the second differential pair signal line are located in the substrate and are arranged on the same layer.
The substrate according to claim 1 or 2, characterized in that the substrate further includes:

A first differential pair pad includes a first positive differential pad and a first negative differential pad; the first positive differential pad is coupled to the first positive differential via, and the first negative differential pad coupled to the first negative differential via;

The second differential pair pad includes a second positive differential pad and a second negative differential pad; the second positive differential pad is coupled to the second positive differential via, and the second negative differential pad coupled to the second negative differential via;

A plurality of reference ground pads, the first positive differential pad, the first negative differential pad, the second positive differential pad, the second negative differential pad and the plurality of reference ground pads The disk array is arranged on the surface of the substrate.
The substrate according to claim 3, wherein the first differential pair via holes and the second differential pair via holes are arranged along a first direction, and the first positive differential pad and the first differential pair via hole are arranged in a first direction. The negative differential pads are arranged along a second direction, and the first direction intersects the second direction;

The first positive differential via is offset from the first positive differential pad, and the first negative differential via is offset from the first negative differential pad;

The second positive differential via is aligned with the second positive differential pad, and the second negative differential via is aligned with the second negative differential pad.
The substrate according to claim 1 or 2, characterized in that the substrate further includes:

A first differential pair pad is located on the surface of the substrate. The first differential pair pad includes a first positive differential pad and a first negative differential pad; the first positive differential via is connected to the first The positive differential pad is aligned and coupled to the first positive differential pad; the first negative differential via is aligned to the first negative differential pad and coupled to the first negative differential pad. coupling;

A second differential pair pad is located on the surface of the substrate. The second differential pair pad includes a second positive differential pad and a second negative differential pad; the second positive differential via is connected to the second The positive differential pad is aligned and coupled to the second positive differential pad; the second negative differential via is aligned to the second negative differential pad and coupled to the second negative differential pad. coupling.
The substrate according to claim 5, wherein the substrate further includes a reference ground pad located on the surface of the substrate;

The first differential pair via hole and the second differential pair via hole are arranged along the first direction, and the first positive differential pad and the first negative differential pad are arranged along the first direction;

Along the second direction, the reference ground pad is provided on at least one side of the second differential pair pad, and the second differential pair pad and the reference ground pad are located on the same straight line;

Wherein, the first direction intersects the second direction.
The substrate according to any one of claims 1 to 6, wherein the substrate further includes a reference ground pad located on the surface of the substrate;

The reference ground pad is disposed between the adjacent first differential pair via hole and the second differential pair via hole.
The substrate according to any one of claims 1 to 7, wherein the second positive differential via and the second negative differential via are symmetrically arranged on both sides of the extension line of the first virtual line segment. .
The substrate according to any one of claims 1 to 8, wherein the substrate includes a plurality of first differential pair via holes and a plurality of second differential pair via holes, and the plurality of first differential pair via holes and the plurality of second differential pair vias are arranged in multiple rows and multiple columns;

The first differential pair via holes and the second differential pair via holes in each row parallel to the first direction are alternately arranged;

and / or,

The first differential pair via holes and the second differential pair via holes in each column parallel to the second direction are alternately arranged.
The substrate according to claim 4, wherein the substrate further includes a plurality of first reference ground vias, and the first reference ground vias are located in the substrate;

Along the first direction, the first reference ground via hole is aligned with the reference ground pad immediately adjacent to the first differential pair pad.
The substrate according to claim 4, wherein the substrate further includes a plurality of first reference ground vias, and the first reference ground vias are located in the substrate;

Along the first direction, the first reference ground via hole is provided between the first differential pair pad and the reference ground pad immediately adjacent to the first differential pair pad.
The substrate according to claim 4, 10 or 11, characterized in that the substrate further includes a plurality of second reference ground via holes, the second reference ground via holes are located in the substrate;

Along the first direction, the second reference ground via is provided between the second differential pair pad and the reference ground pad on the side immediately adjacent to the second differential pair pad;

Along the second direction, the second reference ground via hole is provided in alignment with the reference ground pad immediately adjacent to the second differential pair pad.
The substrate according to claim 4, 10 or 11, characterized in that the substrate further includes a plurality of second reference ground via holes, the second reference ground via holes are located in the substrate;

The second reference ground via hole is provided in alignment with the reference ground pad immediately adjacent to the second differential pair pad.
The substrate according to claim 12 or 13, wherein the substrate includes a plurality of first differential pair via holes and a plurality of second differential pair via holes, the plurality of first differential pair via holes and the plurality of second differential pair via holes. A plurality of second differential pair vias are arranged in multiple rows and columns;

The substrate also includes a first signal line layer, the first signal line layer is provided with a first differential pair signal line and a second differential pair signal line; the first differential pair signal line is connected to the first differential pair signal line in the first row. A first differential pair via is coupled, and the second differential pair signal line is coupled with the second differential pair via in the first row;

The first differential pair signal line extends between the first differential pair via hole and the second differential pair via hole to the outlet edge of the substrate; the second differential pair signal line passes through the first differential pair via hole. Between the two positive differential vias and the second negative differential via, it extends to the outlet edge of the substrate.
The substrate according to claim 14, characterized in that:

The substrate further includes a second signal line layer, the second signal line layer is provided with the first differential pair signal line and the second differential pair signal line;

The first differential pair signal line in the second signal line layer is coupled to the first differential pair via hole in the second row, and the second differential pair signal line is coupled to the first differential pair signal line in the second row. Two differential pairs of vias are coupled; the first differential pair signal line and the second differential pair signal line pass between the first differential pair of vias and the second differential pair of vias in the first row , extending to the outlet edge of the substrate.
The substrate according to any one of claims 1 to 15, wherein the substrate includes a stacked dielectric layer and a core layer, and the first differential pair via hole and the second differential pair via hole penetrate the core layer;

The substrate is a packaging substrate; the material of the dielectric layer includes an Ajinomoto deposited film.
The substrate according to any one of claims 1 to 15, wherein the substrate includes a dielectric layer, and the first differential pair via hole and the second differential pair via hole penetrate the dielectric layer;

The substrate is a printed circuit board or a download board, and the material of the dielectric layer includes prepreg.
A chip packaging structure, characterized by including a chip, a packaging substrate and a download board;

The packaging substrate is the substrate according to any one of claims 1-16; the download board is the substrate according to any one of claims 1-15;

The chip includes a first-level first differential pair pin and a first-level second differential pair pin, and the first-level first differential pair pin is coupled to the first differential pair via hole in the packaging substrate, The second differential pair pins of the first stage are coupled to the second differential pair via holes in the packaging substrate;

The chip packaging structure also includes a second-level first differential pair of pins and a second-level second differential pair of pins located on the side of the packaging substrate away from the chip; the second-level first differential pair of pins Coupled respectively with the first differential pair via hole in the packaging substrate and the first differential pair via hole in the download board, the second stage second differential pair pin is connected to the second differential pair pin in the packaging substrate The pair of vias and the second differential pair of vias in the download board are respectively coupled.
A chip packaging structure, characterized by including a chip and a packaging substrate;

The packaging substrate is the substrate according to any one of claims 1-16;

The chip includes a first stage first differential pair pin and a first stage second differential pair pin. The first stage first differential pair pin is coupled to the first differential pair via hole. The first stage The second differential pair pin is coupled to the second differential pair via.
A chip packaging structure, which is characterized in that it includes a chip, an adapter board and a packaging substrate that are stacked in sequence;

The adapter board includes a third differential via hole and a fourth differential via hole; the third differential pair via hole is located in the adapter board; the third differential pair via hole includes a third positive differential via hole and a fourth differential via hole. a third negative differential via; the fourth differential pair via is located in the adapter board, and the fourth differential pair includes a fourth positive differential via and a fourth negative differential via;

The fourth positive differential via and the fourth negative differential via are respectively disposed on both sides of the extension line of the third virtual line segment; the fourth positive differential via and the fourth negative differential via are located at The same end of the third virtual line segment; wherein the third virtual line segment is a virtual line segment connecting the third positive differential via and the third negative differential via on the surface of the adapter board;

The chip includes a first-level first differential pair pin and a first-level second differential pair pin. The first-level first differential pair pin is coupled to the third differential pair via hole. A first-level second differential pair pin is coupled to the fourth differential pair via hole.
The chip packaging structure according to claim 20, wherein the fourth positive differential via and the fourth negative differential via are symmetrically arranged on both sides of the extension line of the third virtual line segment.
The chip packaging structure according to claim 20 or 21, characterized in that the chip packaging structure further includes a first rewiring layer, and the first rewiring layer is provided on the side of the adapter plate facing the chip. ;

The first differential pair pins of the first stage are coupled to the third differential pair vias through the first redistribution layer, and the second differential pair pins of the first stage are coupled to the third differential pair pins through the first redistribution layer. The fourth differential pair is coupled via vias.
The chip packaging structure according to any one of claims 20 to 22, characterized in that the chip packaging structure further includes a second rewiring layer, the second rewiring layer is disposed on the adapter plate facing the One side of the package substrate;

The third differential pair via hole and the fourth differential pair via hole are coupled to the packaging substrate through the second redistribution layer.
The chip packaging structure according to any one of claims 20 to 23, wherein the material of the adapter plate includes silicon, glass or ceramics.
An electronic device, characterized in that it includes a chip packaging structure and a printed circuit board; the chip packaging structure is provided on the printed circuit board;

The chip packaging structure is the chip packaging structure according to any one of claims 18 to 24, and the printed circuit board is the substrate according to any one of claims 1 to 15.
The electronic device of claim 25, further comprising a connector located between the chip packaging structure and the printed circuit board.
A substrate, characterized in that it includes:

A first differential pair pad is located on the surface of the substrate; the first differential pair pad includes a first positive differential pad and a first negative differential pad;

A second differential pair pad is located on the surface of the substrate, the second differential pair pad includes a second positive differential pad and a second negative differential pad; the second positive differential pad and the second negative The differential pads are respectively disposed on both sides of the extension line of the fourth virtual line segment; and the second positive differential pad and the second negative differential pad are located at the same end of the fourth virtual line segment; wherein, the The fourth virtual line segment is a virtual line segment connecting the first positive differential pad and the first negative differential pad on the surface of the substrate.
The substrate according to claim 27, wherein the substrate further includes a first differential pair signal line and a second differential pair signal line;

The first differential pair signal line is coupled to the first differential pair pad, and the second differential pair signal line is coupled to the second differential pair pad;

The first differential pair signal line and the second differential pair signal line are located in the substrate and are arranged on the same layer.
The substrate according to claim 27 or 28, wherein the substrate further includes a reference ground pad located on the surface of the substrate;

The first differential pair pad and the second differential pair pad are arranged along a first direction; along the second direction, the reference ground pad is provided on at least one side of the second differential pair pad, The second differential pair pad and the reference ground pad are located on the same straight line;

Wherein, the first direction intersects the second direction.
The substrate according to any one of claims 27-29, characterized in that the substrate further includes:

A first differential pair of vias is located in the substrate; the first differential pair of vias includes a first positive differential via and a first negative differential via; the first positive differential via is connected to the first positive differential via. The differential pads are aligned and coupled to the first positive differential pad; the first negative differential via is aligned to the first negative differential pad and coupled to the first negative differential pad. catch;

A second differential pair of vias is located in the substrate. The second differential pair of vias includes a second positive differential via and a second negative differential via. The second positive differential via is connected to the second positive differential via. The differential pads are aligned and coupled to the second positive differential pad; the second negative differential via is aligned to the second negative differential pad and coupled to the second negative differential pad. catch.
The substrate according to any one of claims 27 to 30, wherein the substrate further includes a reference ground pad located on the surface of the substrate;

The reference ground pad is disposed between the adjacent first differential pair pad and the second differential pair pad.
The substrate according to any one of claims 27 to 31, characterized in that the second positive differential pad and the second negative differential pad are symmetrically arranged on both sides of the extension line of the fourth virtual line segment. .
The substrate according to any one of claims 27 to 32, wherein the substrate includes a plurality of first differential pair pads and a plurality of second differential pair pads, the plurality of first differential pair pads and the plurality of second differential pair pads are arranged in multiple rows and multiple columns;

The first differential pair pads and the second differential pair pads are alternately arranged in each row parallel to the first direction;

and / or,

The first differential pair pads and the second differential pair pads are alternately arranged in each column parallel to the second direction.
The substrate according to any one of claims 27-33, wherein the substrate includes a stacked dielectric layer and a core layer, and the first differential pair pad and the second differential pair pad are located on the The surface of the dielectric layer;

The substrate is a packaging substrate; the material of the dielectric layer includes an Ajinomoto deposited film.
The substrate according to any one of claims 27 to 33, wherein the substrate includes a stack of multiple dielectric layers, and the first differential pair pad and the second differential pair pad are located on the plurality of dielectric layers. The surface of the layer dielectric layer;

The substrate is a printed circuit board or a download board, and the material of the dielectric layer includes prepreg.
A method for preparing a substrate, characterized in that it is used to prepare the substrate according to any one of claims 1-17 or 27-35.