WO2023229566A1

WO2023229566A1 - Current ratio equalizer circuit

Info

Publication number: WO2023229566A1
Application number: PCT/TR2023/050477
Authority: WO
Inventors: Tufan Coşkun KARALAR; Ömer Lütfi NUZUMLALI
Original assignee: Aselsan Elektroni̇k Sanayi̇ Ve Ti̇caret Anoni̇m Şi̇rketi̇; İstanbul Tekni̇k Üni̇versi̇tesi̇
Priority date: 2022-05-26
Filing date: 2023-05-25
Publication date: 2023-11-30

Abstract

The present invention relates to a current ratio equalizer circuit that equalizes the current ratios by decreasing or increasing the currents of current sources by the control circuit (3) according to the result of the comparison, until the integral results are equal, by integrating a plurality of currents at different times over the same capacitor and comparing the results of these integrals with a comparator (2).

Description

Current Ratio Equalizer Circuit

Technical Field

The invention relates to a current ratio equalizer circuit used in all applications that use two or more current sources and control the ratio of these currents to each other.

The invention relates to a current ratio equalizer circuit that equalizes the current ratios by decreasing or increasing the currents of current sources by the control circuit according to the result of the comparison, until the integral results are equal, by integrating a plurality of currents at different times over the same capacitor and comparing the results of these integrals with a comparator circuit.

Prior Art

Current mirroring is the most common method used to adjust current ratios, especially in electronic chip circuits. In this method, the desired current ratios are made by adjusting the lengths of the transistors in the circuit. In this circuit, for example, an 11 current is multiplied by 100 and an I2 current is obtained using M1 , M2, M3 and M4 transistors. If the current 11 is passed through the transistor M1 of size W/L, a voltage VG is formed at the gate of the transistor according to the equation in the saturation region of the transistor. If this gate voltage is supplied to transistor M2, which is 100 times larger than transistor M1 , again according to the equation of the transistor in the saturation region, it is ensured that the current 11 passes 100 times through the M2 transistor. Herein, the channel length modulation effect of transistors is neglected. M3 and M4 cascode transistors are added to the circuit so as to reduce the channel length modulation effect and to ensure that the current ratio is not affected by the load voltage (VL). The ratio of the currents may differ from the desired value due to the differences caused by the nonuniformity in the CMOS fabrication. For this reason, the channel width and length of the transistors used in current mirroring circuits are kept too large so as to achieve a precise ratio. However, although the channel width and length of the transistors are kept large, it is difficult to obtain huge ratio precisely such as 100-200 due to mismatches in the fabrication. In particular, it can be much more difficult to achieve the desired ratio in a small area in circuits where small currents are used to obtain low power consumption (approximately 1-100 nA).

As a result of the research on the subject, the application numbered US4268820 and titled “Integrating Type Analog-to-Digital Converter” was encountered. An integral type analog-to-digital converter with a short conversion period and a small amplitude of the integral output is disclosed in the application. Here, a method has been revealed to improve the conversion accuracy of the ADC topology known as "Dual slope integrating analog to digital converter". In said method, the integrals of different currents are taken and these integrals are compared. However, the process of changing the current value fed from the variable current source until the integrals taken by the integrator are sampled over the capacitances and the voltages measured across these capacitances are equal to each other, is not mentioned herein.

As a result of the research on the subject, the application numbered US20100231290 and titled “Measurement Device, Electronic System, and Control Method Utilizing the Same” was encountered. A circuit for correcting the manufacturing-induced errors in the p parameter of BJT transistors in a circuit used to measure the temperature of chips (IC) is described in said application. This circuit is designed to make the ratio of the collector current of the PNP transistor 16 between the two phases. In this circuit, since the collector current goes directly to the GND point, the ratio of IC currents in two phases is tried to be made 16 by using the formula IC=IE-IB. Therefore, IB1 and IE1 currents in the first phase are converted to voltage with a current mirroring element and resistor and kept in the memory of the calculation unit. In the second phase, after the same operations are performed for IB2 and IE2 currents, the results found in the second phase are compared with the results found in the first phase in the calculation unit. According to this result, the (IE2-IB2)/(IE1 -IB1 ) ratio is tried to be equalized to 16 by adjusting the IE2 current. Here, the value of at least one current supplied from current sources is adjusted so as to maintain a predetermined current ratio as a result of comparing the voltages obtained from the currents from different current sources with each other. The process of changing the current value fed from the variable current source until the integrals taken by the integrator are sampled over the capacitances and the voltages measured across these capacitances are equal to each other but not to a fixed value, is not mentioned in said application. As a result of the research on the subject, the application numbered WO96/10297 and titled “System for Calibrating Analog-to-Digital Converter” was encountered. In said application, a novelty has been revealed so as to solve the low resolution problem in the ADC technique known as "Dual slope integrating analog to digital converter". Herein, the charge accumulated on the capacitor is discharged using two separate current sources called IL and IS. The input current of the ADC can be converted into a high resolution digital data by switching these currents on and off at certain times by a controller. However, the ratio of IL and IS currents must be at the desired level so as to avoid linearity errors in this ADC structure. Here, this value is set as 32. A ratio higher or lower than this value may cause monotonicity and missing code errors. Therefore, in such a case, the currents need to be calibrated so that the ratio of their currents is 32 in order for the circuit to work properly. In said application, instead of calibrating the ratio of currents to a specific number, first of all the ratio between currents are founded. Then to calculate the final value of ADC this founded ratio is used. The method described below is used to find the ratio of the currents in this application. First of all, the capacitance is filled with a current whose value is known. Then, the current II discharges the capacitance during the time i . Following this, the Is current discharges the capacitance during the time tsi ■ This process is repeated using the times tL2 and ts2. At the end of these periods, the ratio of the currents is calculated according to the following formula:

As a result of this ratio, the value of can be, for example, .i . This value is then used in the calculator to create the numerical value of the input current. However, this extra process increases the complexity of the circuit. In addition to this, the process of changing the current value fed from the variable current source until the integrals taken by the integrator are sampled over the capacitances and the voltages measured across these capacitances are equal to each other, is not mentioned in this invention.

As a result, due to the abovementioned disadvantages and the insufficiency of the current solutions regarding the subject matter, a development is required to be made in the relevant technical field.

Aim of the Invention The invention aims to solve the abovementioned disadvantages by being inspired from the current conditions.

The main aim of the invention is to equalize the current ratios by decreasing or increasing the currents of current sources by the current ratio equalizer circuit according to the result of the comparison, until the integral results are equal, by integrating a plurality of currents at different times over the same capacitor and comparing the results of these integrals with a comparator circuit.

Another aim of the invention is to control the ratios of currents to each other and to fix these ratios in applications where two or more current sources are used in general, in particular two current sources that discharge the sampling capacity dual ramp single slope analog-to-digital converters.

Another aim of the invention is to provide a more accurate current ratio at small currents.

The structural and characteristic features of the present invention will be understood clearly by the following drawings and the detailed description made with reference to these drawings and therefore the evaluation shall be made by taking these figures and the detailed description into consideration.

Figures to Help Understanding of the Invention

Figure 1 is the schematic view of the mirroring method used in prior art

Figure 2 is a simplified schematic view of the current equalizer circuit which is the subject of the invention.

Figure 3 is the time display of the current equalizer circuit which is the subject of the invention.

Figure 4 is the detailed schematic view of the alternative version of the current equalizer circuit which is the subject of the invention.

Figure 5 is a representative schematic view of the OTA (Operational Trasnconductance Amplifier) load current problem.

Reference List 1. OTA (Operational T ransconductance Amplifier)

2. Comparator

3. Control circuit

T1 . Reset time

T2. 11 current integration time

T3. Reset time

T4. I2 current integration time

Symbols and abbreviations used in the figures and description

I: Current

M: Transistor

V: Voltage

C: Capacitor t: Time

<D: Switch

S: Another switch

Detailed Description of the Invention

In this detailed description, the preferred embodiments of the inventive current equalizer circuit are described by means of examples only for clarifying the subject matter.

For example, it is aimed that an l₂ current is A times as much as an current in the example application seen in the simplified scheme of the inventive current equalizer circuit, given in Figure 2. The current equalizer circuit integrates the and l₂ currents respectively and compares the result of these integrals with a comparator (2), and changes the value of the l₂ current to be A multiple of the current so as to adjust the ratio of the currents. The value of l₂ current can be increased or decreased by controlling the DAC (Digital to Analog Converter) control circuit (3).

The present invention can be adapted to control and fix the ratios of currents produced by current sources to each other in applications where two or more current sources are used in general, in particular two current sources that discharge sampling capacitor in dual ramp single slope analog-to-digital converters. Accordingly, the present invention mainly comprises of the following;

• at least one constant current source producing constant current and at least one variable current producing variable current source,

• at least one integrator that integrates the constant current supplied by the constant current source and the variable current supplied by the variable current source,

• a sampler that samples the constant current integral over a first capacitance and the variable current integral over a second capacitance taken by the integrator;

• at least one comparator (2) at the output of the sampler that compares the voltage across the first capacitance with the voltage across the second capacitance in each cycle, and

• at least one digital-analog converter control circuit (3) that enables the variable current value to be increased or decreased in each cycle until the voltages on the first capacitance and the second capacitance are equal according to the comparison result coming from the comparator (2).

In the present invention, the integration time determines the ratio of the currents. The output voltage of the integrator OTA is shown in Equation 1.

Equation 1 :

Here t_x time denotes the time to start the integral. Before time t_x as seen in Figure 3, since the Ont capacitor is reset, the v_Cint(tx) voltage (loaded voltage across the capacitor before starting the integral) becomes zero. Here, V_ref is the voltage connected to the positive input of the OTA shown in Figure 2. Also, since the integrated currents are time-invariant DC currents, Equation 1 can be simplified as in Equation2.

Equation 2:

If the h current is integrated during tinti, the resulting VOUTI output voltage becomes as in Equation 3.

Equation 3:

Likewise, if the l₂ current is integrated during , the resulting VOUT2 output voltage becomes as in Equation 4. Equation 4:

If VOUTI and VOUT2 can be equated with a circuit to be used, the ratio of currents is equal to the ratio of integration time. Equation 5: tint₂

I₂ tint!

In the inventive current equalizer circuit, VOUTI and VOUT2 voltages are compared with each other through the comparator (2) during each cycle and as a result of this, the value of l₂ current is changed with a digital-analog converter in each cycle, thus VOUTI and VOUT2 voltages are equalized to each other.

The timing signals of the switches used in the inventive current equalizer circuit and the voltages of the signals in the circuit are given in Figure 3. The operating structure of the circuit can be understood more easily with the help of Figure 3:

• First of all, the integration capacitance Cint is reset by the reset switch. Then, the reset switch is opened and the 01 switch is closed, and the current is integrated during tinti ■ The resulting integral voltage is sampled by opening the switch <t>i at the capacitance Ci.

• Then the Cint capacitance is reset again for the second integration. After this step, the ₂ switch is closed and the l₂ current is integrated in time. The resulting integral voltage is sampled by opening the switch 0₂ at the capacitance C₂.

• After the second integration is finished, the comparator (2) compares the voltages across capacitances Ci and C₂ and the control circuit (3); o increases l₂ current through the digital analog converter if the voltage across capacitance C₂ is less than the voltage across capacitance Ci. o reduces l₂ current through the digital analog converter if the voltage across capacitance C₂ is greater than the voltage across capacitance Ci.

• Then, the Cint capacitance is reset again and the same operations are applied, and the circuit operates until the voltages on the capacitances Ci and C₂ are equal to each other. When the voltages across capacitances Ci and C₂ are equal, the condition specified in Equation 5 is fulfilled and the value of l₂ current becomes equal to A times the value of current.

In an alternative embodiment of the present invention, the circuit shown in Figure 4 is presented so as to achieve the requested A ratio with higher accuracy:

I. In an exemplary embodiment, the first value of the integral voltage should be 2.65V and the final value should be 1.65V in order for the current equalizer circuit to operate better. In addition to the reset switch shown in Figure 2, the S₂ and S₃ switches shown in Figure 4 have been added so as to achieve this.

II. Cciamp capacitor and S₄ switch are added to the circuit so as to prevent settling errors during transitions between the reset phase and the current integrating, and to get rid of the reset noise simultaneously. Switch S₄ is kept closed for a while after the integration of and l₂ currents begins. Thus, while the voltage on the left side of the Cciamp capacitor starts to decrease due to the integration process, the voltage on the right side remains constant at VREF2 (2.65V). Then, when the switch S₄ is turned on, the voltage value on the right side of the Cciamp capacitor starts from the VREF2 voltage and follows the voltage on the left side of the capacitor with the same slope. The effect of the OTA's reset noise is not seen in the voltage across the right branch of the capacitor since the initial voltage of this circuit does not start from the output voltage of the OTA at the time of reset, it always starts from the VREF2 voltage. At the same time, the voltage changes that appear on the left side of the capacitor are not visible on the right side of the capacitor during the opening and closing of other switches in the circuit, since switch S₄ remains closed for a while after the integrating process has started. If switch S₄ opens after the voltages on the left side of the capacitor have fully settled, settling errors that may occur due to opening and closing of other switches on the right side of the capacitor are prevented.

III. Also, the load on the C_Sh_isb and C_Sh_msb capacitances changes since the output voltage changes while integrating the large and small currents. Currents Id and Ic2 that change this load are provided by OTA. Ici and Ic2 currents are formed as in the equations below. Equation 6 and Equation 7:

However, the slope of the output voltage is different by a multiple of A when integrating the current h and l₂. For this reason, there is a difference of a multiple of A between the currents provided by the OTA, as seen in Equation 8, during the phases where the and l₂ currents are integrated.

Equation 8:

When different current is provided by the OTA, the feedback voltage at the negative input voltage of the OTA differs for both phases. This difference causes the final voltage on the C_Sh_isb and C_Sh_msb capacitors to change and desired ratio to be different from A. Switches S₅ and S₆ are added to the circuit, and these switches are turned on for a very short time in the last step of the integration process, and the OTA output voltage is sampled on the C_Sh_isb and Csh_msb capacities so as to solve this problem. Thus, it is prevented from driving current over the C_Sh_isb and C_Sh_msb capacities while integrating the and l₂ currents of the OTA, so that the feedback voltage remains the same in both phases of the integrating process.

IV. Offset and other errors of OTA in the current equalizer circuit do not affect the operating performance of the circuit.. But the effect of comparator (2) is not like this. The performance of the comparator (2), in particular the offset voltage, directly affects the performance of the current equalizer circuit. Therefore, autozero switches 89,10,11,12 and auto-zero comparator (2) have been added to the current equalizer circuit. The auto-zero comparator (2) operates in two phases. The first phase is the auto-zero phase. In this phase, switches Sn and Si₂ are kept closed, and switches S₉ and S10 are kept open. In this way, the same voltage is applied to the plus and minus ends of the comparator (2), and the offset of the circuit is recorded on a capacitance in the comparator (2). Then, when the comparator (2) is in phase, switches Sn and S12 are opened and switches S₉ and S10 are closed, the comparator (2) works with zero offset by adding the offset value recorded in the previous phase to the difference between the input voltages.

Claims

CLAIMS A current equalizer which controls and equalizes the ratios of currents produced by current sources in applications where two or more current sources are used, characterized by comprising;

• at least one digital-analog converter control circuit (3) that enables the variable current value to be increased or decreased in each cycle until the voltages on the first capacitance and the second capacitance are equal according to the comparison result coming from the comparator (2). The current equalizer according to claim 1 , characterized by comprising at least one Cciamp capacitor that prevents settling errors and reset noise in the phase transitions where reset phase and current are integrated. The current equalizer according to claim 1 , characterized by comprising at least one switch that prevents settling errors and reset noise in the phase transitions where reset phase and current are integrated. The current equalizer according to claim 1 , characterized by comprising autozero switches and auto-zero comparator (2) so as to prevent errors occurring in the circuit in all phases.