WO2023227211A1 - Agencement optoélectronique et son procédé de traitement - Google Patents

Agencement optoélectronique et son procédé de traitement Download PDF

Info

Publication number
WO2023227211A1
WO2023227211A1 PCT/EP2022/064191 EP2022064191W WO2023227211A1 WO 2023227211 A1 WO2023227211 A1 WO 2023227211A1 EP 2022064191 W EP2022064191 W EP 2022064191W WO 2023227211 A1 WO2023227211 A1 WO 2023227211A1
Authority
WO
WIPO (PCT)
Prior art keywords
contact
layer
recess
reflective
optoelectronic
Prior art date
Application number
PCT/EP2022/064191
Other languages
English (en)
Inventor
Siegfried Herrmann
Original Assignee
Ams-Osram International Gmbh
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ams-Osram International Gmbh filed Critical Ams-Osram International Gmbh
Priority to PCT/EP2022/064191 priority Critical patent/WO2023227211A1/fr
Publication of WO2023227211A1 publication Critical patent/WO2023227211A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages
    • H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/58—Optical field-shaping elements
    • H01L33/60—Reflective elements

Definitions

  • the present invention concerns an optoelectronic arrangement and a method for processing the same .
  • BACKGROUND pLEDs are suited for a variety of applications including but not limited to displays , headlight and the like .
  • One suitable technique is to monolithically integrate the individual pLEDs onto a wafer, that also forms directly a part of the display .
  • An alternative which allows for more flexibility proposes the processing of such pLEDs on a growth substrate on wafer level and subsequently utilize mass transfer to transfer the pLEDs to a PCB or nay other suitable carrier .
  • the carrier in this regard may include power supply and control circuitry .
  • the pLED is placed at a certain contact location and the soldered onto the carrier .
  • an optoelectronic arrangement comprises a contacting layer on a carrier , said contacting layer having at contact lead .
  • the contact lead may be connected to some circuitry in the carrier .
  • This circuitry may include in some instances current and voltage supply circuitry for the optoelectronic device .
  • a reflective layer stack is arranged at least partially on said contacting layer .
  • the reflective layer stack comprises a recess in a top surface , said recess being in electric contact with said contact lead .
  • the recess can be a through hole through the recess layer stack or portions thereof .
  • the bottom opening of the through hole may be arranged over the contact lead .
  • the bottom of the recess or the layer stack material may be a conductive material .
  • the proposed optoelectronic arrangement further comprises an optoelectronic device having a first contact area on a surface facing the recess . It may also contain a second contact area . A cross section of the first contact area is smaller than a cross section of the surface of the optoelectronic device . In other words , the first contact area is smaller than the top surface of the optoelectronic device .
  • a solder material is now arranged in the recess and extends above the top surface . The solder material contacts the first contact area of the optoelectronic device thus holding the device mechanically in place and also contacting it electrically .
  • the recess can act as a soldering reservoir thus defining the overall amount of solder material .
  • the recess defines a contact area for the optoelectronic device having a dedicated geometry and defined roughness . Consequently, the geometry for the recess can include a square , a rectangle , a hexagon a circular or ovular shape and the like .
  • the reflective layer stack comprises a reflective layer on said contacting layer .
  • the reflective layer may comprise aluminum, silver, gold, or any other suitable reflective material and is in electrical contact with the contact lead .
  • the reflective conductive layer may be surrounded by an isolating material . This will limit the conductivity to a certain area reducing the probability of short cuts .
  • a structured layer is applied on top of the reflective layer .
  • the structured layer comprises the recess .
  • the recess is a through hole , such that the "bottom of the recess" is formed by the reflective layer .
  • the structured layer may include a transparent insulator , like for example Si02 .
  • the structured layer may a transparent conductive material like ITO , which can optionally be surrounded by an insulating material .
  • the reflective layer or the structured layer may span several such recesses and ultimately several optoelectronic devices . In such case , the reflective layer is used as a common contact .
  • the structured layer comprises the reflective material .
  • the reflective layer may be a topmost layer of the layer stack .
  • the material of the structured layer stack may comprise ITS or a conductive metal .
  • the overall surface of the recess formed therein is conductive , which simplifies the soldering process .
  • the reflective layer stack may comprise an insulating material , in particular a transparent insulating material , in which the recess is formed .
  • portions of the surface of the recess comprise an insulating material .
  • a conductive material may be deposit on the surface of the recess .
  • Such material may include a thin layer of gold, palladium or platin .
  • a contact well may be arranged in the recess that extents above the top surface . A portion of the contact well can rest on the top surface surrounding the cavity . The contact well builds the reservoir for the soldering material in some instances and allows positioning the optoelectronic device .
  • the contact well or the soldering material extends above the top surface .
  • the surface of the optoelectronic device facing the recess is distanced apart from the top surface .
  • the optoelectronic device may rest on the well with a small airgap outside the actual contact area .
  • a distance between the surface of the optoelectronic device facing the recess and the top surface is substantially equal to a height of the contact well extending above the surface .
  • the portion of the contact well above the surface may comprise one or more openings such that excess solder material can spoil though those openings to ensure the optoelectronic device rest smooth and flat .
  • the solder material should fill the recess to ensure proper electrical and mechanical connection to the optoelectronic device .
  • the surface of the optoelectronic device comprises approximately the same size as the top surface . However, the surface of the optoelectronic device can also be smaller than the respective top surface . If the optoelectronic arrangement according to the proposed principle includes more than one contact lead, electrically contacting a top surface , the top surfaces ( and the electric contact leads ) can be arranged in rows and columns . Two adj acent top surfaces may be spaced apart from each other and they can be separated by an insulating material .
  • the reflective layer stack may comprise an insulating layer with recesses and contact wells formed therein . In such case the contact wells can be spaced apart and separated by the insulating material of the layer stack .
  • the optoelectronic arrangement comprises an encapsulating material arranged on the reflective layer stack and surrounding the optoelectronic device .
  • the encapsulating material is also arranged on the top surface of the reflective layer stack .
  • the encapsulating material is transparent and may comprise an insulating plastic component , for example epoxy, silicon, and the like .
  • the optoelectronic device also comprises a second contact area .
  • the second contact area may be located on a surface of the optoelectronic device facing away from the carrier and the recess , respectively .
  • Such types of optoelectronic devices are referred to as vertical pLEDs .
  • optoelectronic devices having the respective first and second contact areas on the same side are referred to as horizontal pLEDs .
  • the optoelectronic arrangement comprises a pair of recesses and/or contact wells , which are spaced apart . The distance between the two recesses and/or contact wells correspond to a distance between the first and second contact areas , respectively on the same surface side of the optoelectronic device . Solder material in both contact wells is used to fix and contact the optoelectronic device to the contact layer mechanically and electrically .
  • the optoelectronic arrangement may comprise a contact wiring, electrically contacting the second contact area on a surface of the optoelectronic device facing away from the recess and/or the contact well .
  • the contact wiring is led out , for example to an edge of the arrangement .
  • a carrier with a contacting layer is provided, whereas the contacting layer includes at least one contact lead .
  • the carrier may comprise circuitry like voltage and power supply and may also comprise one or more rewiring layers .
  • a reflective layer stack is provided on said contact layer .
  • the reflective layer stack comprises a contact well in a top surface of the layer stack .
  • the contact well now electrically contacts a respective lead or plug in the contacting layer .
  • a solder material is deposited in the contact well .
  • an optoelectronic device having a first contact area on a surface facing the contact well is provided .
  • the optoelectronic device may also comprise a second contact area, which is either on the same side as the first contact area or facing away therefrom.
  • the optoelectronic device is soldered to the contact well using the deposited solder material , such that the optoelectronic component is mechanically and electrically fixed at the contact well .
  • a second contact may also be applied to the second contact area .
  • the proposed method proposes a defined contact area with a specified surface geometry .
  • the device When providing the optoelectronic device , the device can be placed using adhesive forces exerted by atomic van der Waals forces . Those are sufficiently large giving the surface geometry and the size of the optoelectronic devices .
  • the solder material is suitable for a low temperature bond process in the range of about 200 ° C thus reducing the risk of heat damages during the solder process .
  • the step of providing a reflective layer stack on said contact layer comprises patterning a reflective material on the contact layer .
  • the reflective material is in electrical contact with the contact lead .
  • a material layer is deposited onto the reflective layer .
  • the material layer or the reflective layer is structured to form a recess in the respective top surface (that is the top surface of the material layer or the reflective layer ) such that a portion of the reflective layer is exposed and optionally above the contact lead .
  • the structuring can be conducted by forming a patterned photoresist followed by a subsequent etching process .
  • a contact well is formed in the recess , wherein the contact well comprises a conductive layer .
  • the conductive layer is formed by sputtering, plating , and other deposition method can extend above the top surface of the conductive layer .
  • the contact well and more particular the portion extending above the surface is shaped in some instance to form a supporting surface , on which the optoelectronic device can be placed upon .
  • the material of the conductive layer may comprise Gold, Palladium, Platin, Aluminum, Silver, and the like . It may be useful in some instances to use a conductive material .
  • the reflective layer stack on said contact layer can be formed by depositing a conductive and reflective material directly on the contact layer and subsequently patterning the reflective material to form a recess in the top surface of the reflective material , the recess does neither need to be a through hole nor be arranged in direct vicinity of the contact lead .
  • a structured sacrificial layer is arranged on the top layer of the top surface and around the respective recesses and/or contact wells . The solder material may be sputtered or otherwise deposited inside the contact well .
  • the sacrificial layer is removed after the sputtering process thus also removing any residual solder material not within the recesses and/or wells .
  • the solder material can then be annealed .
  • the annealing temperature may be set to approximately 170 ° C to 240 ° C .
  • the solder material may liquify .
  • the solder material may form a bump or a similar shape . In this regard it is possible to shape the solder material by exerting a pressure thereupon . Such shaping may also have the benefit of removing or at least breaking any oxidised surface of the solder material .
  • the optoelectronic device is encapsulated with a with a transparent insulating material , for example SI02 .
  • the insulating material can be applied in particular by spin coating .
  • Figure 1 shows an embodiment of an optoelectronic arrangement in accordance with some aspects of the proposed principle
  • Figures 2A to 2E illustrate various steps for processing a carrier suitable to receive one or more optoelectronic device accordance with some aspects of the proposed principle ;
  • Figures 3A to 3D show further process steps for processing an optoelectronic arrangement having a plurality of optoelectronic devices in accordance with some aspects of the proposed principle ;
  • Figure 4 illustrates another embodiment of a carrier suitable to receive an optoelectronic device accordance with some aspects of the proposed principle ;
  • Figure 5 shows another embodiment of an optoelectronic arrangement in accordance with some aspects of the proposed principle .
  • Figure 1 illustrates an optoelectronic arrangement 1 in accordance with the proposed principle .
  • the optoelectronic arrangement comprises a carrier 20 including one or more circuit devices embedded therein but not illustrated in the Figure .
  • the circuit devices in the carrier are adapted to provide current and supply voltage to an optoelectronic device la being part of the arrangement .
  • the carrier 20 further includes wiring layer 21 that comprises one or more contact leads 21a .
  • the contact leads 21a are connected to the circuitry of carrier 20 .
  • Wiring layer 21 can form an integral portion of carrier 20 or deposited on carrier 20 in a subsequent process step . The latter may allow using the same circuitry within the carrier 20 for different application and particular different geometry that are set by the additional wiring layer .
  • the optoelectronic arrangement can therefore comprise a plurality of optoelectronic devices connected to the carrier as presented herein and arranged in columns and rows , respectively .
  • a reflective layer stack is deposited on the wiring layer 21 .
  • the reflective layer stack comprises a conductive reflective layer 22 as well as a structured layer 23 .
  • the reflective layer 22 includes silver , gold, aluminum, palladium or any other suitable reflective material .
  • the reflective layer is in electrical contact with the contact leads 21a .
  • Structured layer 23 comprises a recess , which is formed in the present example directly above contact layer 20a .
  • the recess is formed as a through hole and extends form the top surface through structured layer 23 , such that reflective layer 23 forms a bottom of the recess . Due to the conductive nature of reflective layer 23 , one may shift recess in structured layer 23 , such that it is not directly arranged above contact lead 23 . It needs however to be ensured that reflective layer 23 connects contact lead and the recess .
  • the recess is filled with contact 1224 . More particularly, the bottom of the recesses 22 a is covered by a gold layer which extends on the sidewall of the recess and above the main surface of the structured layer 23 . The contact will therefore extend above the top surface and forms the side wall adj acent to the recess on the top surface of layer 23 .
  • the structured layer 23 is formed by an insulating transparent material , hence the recess must have access to the reflective material layer 23 .
  • the structured layer 22 can be formed of a conductive material and even a reflective conductive material . In the latter case , it is required that layer 23 contacts contact lead 21a , but the recess within layer 23 can be positioned spaced apart from contact lead .
  • the bottom of the recess and the sidewalls are covered by a reflective and conductive material forming a so-called contact well 24 .
  • the contact well 24 is made of gold . Alternative materials would be palladium or platin for example .
  • Contact well 24 comprises a thickness of a few nm on the bottom and sidewalls . The material does however extend above the surface of the structured layer 23 forming a substantially flat area surrounding the recess . The gold material of contact well 24 is therefore also deposited on portions of the top surface of structured layer 23 surrounding the recess .
  • solder material 25 is deposited in the contact well 24 and connects a first contact area 15 of an optoelectronic device mechanically as well as electrically .
  • optoelectronic device is fixed with its first contact area to the top of the contact well and the solder material .
  • First contact area 15 has at least the same size as the cross section of the solder material but may also comprise a large cross-section .
  • the contact provides a mechanical and electrical stable connection between the carrier 20 including the reflective the structured layer as well as the optoelectronic device .
  • the optoelectronic device rests with its first contact area 15 on the contact well 24 and the solder material 25 .
  • the optoelectronic device comprises a small distance to the top surface of structured layer 23 .
  • Contact well 24 and solder material 25 are forming an inter metallic phase connecting the optoelectronic device to the carrier .
  • the optoelectronic device la comprises two differently doped regions 11 and 12 with an active layer 13 formed in-between .
  • a 11 second contact area 14 is provided on the top surface of doped region .
  • First contact area 15 is arranged in a recess of the top passivation layer 60 .
  • the passivation also extends onto and along the sidewall of the device as a side wall passivation layer 60 up to the top surface of optoelectronic device la .
  • the optoelectronic device in accordance with the present embodiment is implemented as a so-called vertical device with its respective first and second contact areas 15 and 14 on to opposite surface is .
  • an alternative implementation to a vertical device is a horizontal device as illustrated in Figure 15 .
  • the optoelectronic device la comprises both contact areas 15 and 14 on the same surface side facing the carrier 20 .
  • the device comprises an insulated through hole 12a that reaches through region 11 and active layer 13 into doped region 12 . Both contact areas are spaced apart and are contacted by solder material 25 to the carrier 20 .
  • Carrier 20 in turn comprises two contacting or wiring layer 21a that are in contact with two contact wells 24 , respectively . Each of the two wiring layers 21a is connected to a respective contact well 24 .
  • the material 25 of the contact wells is soldered to the respective contact areas .
  • An insulating layer 23a separates both contacting wiring layers 21a and the reflective layers 22 .
  • FIG. 2A to 2D illustrate various steps of processing the carrier in accordance with the proposed principle .
  • carrier substrate 20 is provided in a first step depicted in Figure 2A .
  • the carrier substrate may comprise various circuitry based on CMOS technology any other suitable circuitry and logic .
  • carrier 20 may include voltage and current supply circuitry, control circuitry for activating or deactivating the optoelectronic devices , various sensors for measuring temperature or other parameters and the like .
  • the carrier 20 can be processed in the previous step and particularly adapted to suit the optoelectronic arrangement in subsequent processes .
  • a contacting structure with a rewiring layer 21 having several contacts leads 21a is deposited on the top surface of the carrier 20 in the first process step shown in Figure 2B .
  • the rewiring structure 21 with its contact layer 21a can be formed also as an integral part of the carrier 20 .
  • a rewiring layer may be suitable in cases , in which the sizes and locations of the various circuitry within carrier 20 do not match the respective desired locations of the optoelectronic device in the optoelectronic arrangement .
  • a reflective layer stack is deposited on top of the rewiring structure 21 .
  • the reflective layer stack comprises a reflective layer 22 , which consists of silver . Other materials like aluminum or gold are also suitable .
  • the reflective layer 22 is surrounded by an insulating material (not shown here ) to prevent short circuit between adj acent contact leads in the rewiring structure 21 .
  • a structured layer 23 is arranged on top of reflective layer 22 .
  • the structured layer is transparent non-conductive material , like an epoxy or Si02 , but can also comprise a conductive material like ITO .
  • an insulating barrier (not shown) separates layer 23 from an adj acent portion .
  • a recess 25b is arranged within the structured layer 23 , whereas the bottom of recess is formed by a portion of the top surface the reflective layer 22 .
  • structured layer 23 comprises a through hole in the vicinity of contact lead 21a , such that is arranged in this particular embodiment above the contact .
  • the conductive and reflective layer 22 provides an electrical connection between of the contact and the bottom of the recess .
  • the bottom of the recess as well as the sidewalls are covered by a gold material forming a so- called contact well 24 .
  • the sidewalls of the contact well 24 extend above the top surface of structured layer 23 , with material for the contact well resting on portions of the top surface of the structured layer 23 adj acent to the recess .
  • the material of contact well 24 is also a reflective material and can be formed by a so-called under bump metallization or UBM .
  • the height of the contact well 24 extends above the top surface of structured layer 23 .
  • a spacer is formed by contact well defining a distance between the optoelectronic device later arranged on contact well 24 and the top surface of structured layer 23 . Said distance may be in the range of a few nm or few 10 nm to 100 nm.
  • Figure 2D illustrates the next step of the proposed process , in which a solder material is sputtered into the contact well 24 .
  • a photoresist (not shown here ) is applied to the surface and structured to prevent solder material to be deposited outside the contact well 24 .
  • the spattering process leads to solder material 25 being arranged inside the recess as well as on the top surface of the contact well 24 .
  • Material adj acent to the contact well and for example deposited on the structured photoresist (not shown here ) or any other sacrificial layer is removed during lift of process , leaving the illustrated structure in Figure 2D behind .
  • FIG. 2E illustrates the result of subsequent annealing process , in which the solder material in the side the contact well is heated to a temperature of about 170 ° to 240 ° depending on the material for the contact well 24 as well as the geometry of the recess and the corresponding geometry of contact well .
  • the solder material forms a certain shape , -in this case- , a bump due to the surface tension of the solder material .
  • the annealing process illustrated in figure 3E will therefore provide a well-defined structure and geometry, which can be used for subsequent process steps during the processing and particularly the deposition of the optoelectronic devices on the contact well . Further to the annealing process illustrated herein several steps for removing the oxide layer on top of the solder material can be performed .
  • an optional mechanical structuring can be performed on the solder material during or after the annealing process .
  • the solder material can be pressed into the contact well , thereby filling the contact well 24 completely .
  • the older material may extend slightly over the top surface of the contact well depending on the amount and volume of the solder material .
  • Figures 3A to 3D illustrate the next process steps after the carrier 20 has been processed with a plurality of contact wells in accordance with the proposed principle .
  • stamp 3 comprises an adhesive surface , to which a plurality of optoelectronic device is attached to .
  • Figure 3A illustrates an example , in which stamp 3 is used to transferring a plurality of optoelectronic devices to the respective contact wells .
  • the solder material 25 as well as a contact well 24 are chosen such that adhesive forces like Van-der-Waals forces will provide sufficient adhesion during the transfer process when the stamp 20 transfers and arranges a plurality of optoelectronic devices on the respective contact bringing them in contact with the solder material and the contact wells .
  • This process is figuratively illustrated in Figure 3A.
  • the adhesive forces are large enough that the first contact areas of the respective optoelectronic devices stack on the solder material within the contact wells .
  • solder process shown in figure 3B is conducted .
  • the solder process will mechanically and electrically fix the respective optoelectronic devices with their respective first contact areas 15 to the contact well 24 .
  • the optoelectronic device is in electrical contact with the contact well 24 and the contact lead 21 .
  • spin on glass technology is used to spin a transparent material encapsulating the respective optoelectronic devices as well as the contact wells 24 . Such process will support fixing the optoelectronic devices and protect them form damages .
  • any other suitable deposition process of transparent insulating material can be used . The deposited material is either mechanically grinded or otherwise reduced such that the top surface of the optoelectronic devices 11 are exposed .
  • the second area contacts 14 on the tip surface of the respective optoelectronic devices are connected to a transparent conductive material 36 like ITO .
  • the transparent conductive material is deposited as a thin layer forming a common contact for all devices .

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Led Device Packages (AREA)

Abstract

L'invention concerne un agencement optoélectronique comprenant une couche de contact sur un support, ladite couche de contact ayant un fil de contact, et un empilement de couches réfléchissantes disposées au moins partiellement sur ladite couche de contact. La couche réfléchissante comprend une cavité dans une surface supérieure, ladite cavité étant en contact électrique avec ledit fil de contact. L'agencement optoélectronique comprend en outre un dispositif optoélectronique ayant une première zone de contact sur une surface faisant face à la cavité et une seconde zone de contact, dans laquelle une section transversale de la première zone de contact est inférieure à une section transversale de la surface. Un matériau de brasure est disposé à l'intérieur de la cavité et s'étend au-dessus de la surface supérieure, le matériau de brasure entrant en contact mécaniquement et électriquement avec la première zone de contact.
PCT/EP2022/064191 2022-05-25 2022-05-25 Agencement optoélectronique et son procédé de traitement WO2023227211A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/EP2022/064191 WO2023227211A1 (fr) 2022-05-25 2022-05-25 Agencement optoélectronique et son procédé de traitement

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/EP2022/064191 WO2023227211A1 (fr) 2022-05-25 2022-05-25 Agencement optoélectronique et son procédé de traitement

Publications (1)

Publication Number Publication Date
WO2023227211A1 true WO2023227211A1 (fr) 2023-11-30

Family

ID=82196701

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2022/064191 WO2023227211A1 (fr) 2022-05-25 2022-05-25 Agencement optoélectronique et son procédé de traitement

Country Status (1)

Country Link
WO (1) WO2023227211A1 (fr)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130056776A1 (en) * 2011-09-06 2013-03-07 Genesis Photonics Inc. Plate
US20170338390A1 (en) * 2014-10-31 2017-11-23 Seoul Viosys Co., Ltd. High efficiency light emitting device
US20190097084A1 (en) * 2017-09-25 2019-03-28 Primax Electronics Ltd. Light source module
JP2021092646A (ja) * 2019-12-10 2021-06-17 株式会社ジャパンディスプレイ 表示装置、および表示装置の製造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130056776A1 (en) * 2011-09-06 2013-03-07 Genesis Photonics Inc. Plate
US20170338390A1 (en) * 2014-10-31 2017-11-23 Seoul Viosys Co., Ltd. High efficiency light emitting device
US20190097084A1 (en) * 2017-09-25 2019-03-28 Primax Electronics Ltd. Light source module
JP2021092646A (ja) * 2019-12-10 2021-06-17 株式会社ジャパンディスプレイ 表示装置、および表示装置の製造方法

Similar Documents

Publication Publication Date Title
TWI502705B (zh) 晶片封裝體及其製造方法
TWI473223B (zh) 晶片封裝體及其製造方法
KR101630138B1 (ko) 마이크로 소자들을 안정화하기 위한 구조체
US6888209B2 (en) Semiconductor package and method of fabricating the same
CN100576554C (zh) 影像感测元件封装体及其制作方法
KR101641993B1 (ko) 드라이버 ic용 금속 범프 구조체 및 그의 제조 방법
US20100258950A1 (en) Package with semiconductor device and integrated circuit mounted therein and method for manufacturing such package
TW200910584A (en) Electronic device wafer level scale packages and fabrication methods thereof
SG133571A1 (en) Semiconductor device, method of manufacturing the same, and camera module
CN110832635A (zh) 用于制造基于led的发射显示装置的方法
US20220238751A1 (en) Method of manufacturing a hybrid device
CN110943067B (zh) 半导体装置及其制造方法
US10354971B2 (en) Method for producing a chip module
WO2023227211A1 (fr) Agencement optoélectronique et son procédé de traitement
WO2008033563A2 (fr) Support permettant le soudage face dessous d'une puce émettrice de lumière
CN102543782A (zh) 转接封装结构及其形成方法
JP2007518253A (ja) 薄膜化シリコンからなる電子チップの製造方法
KR101287308B1 (ko) 홈으로 분리된 접촉 패드들을 갖는 박형화된 이미지 센서
CN112436019A (zh) 半导体设备封装和其制造方法
JP2021501459A (ja) 半導体パッケージングのための構造及び方法
US20220399302A1 (en) Substrate bonding
KR101101432B1 (ko) 반도체 디바이스의 제조 방법 및 이를 이용한 반도체 디바이스
TW202412255A (zh) 用於製造光電裝置的方法及光電裝置
US20220013700A1 (en) Method for Producing Optoelectronic Semiconductor Devices and Optoelectronic Semiconductor Device
WO2023222240A1 (fr) Procédé de fabrication d'un dispositif optoélectronique et dispositif optoélectronique

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22733308

Country of ref document: EP

Kind code of ref document: A1