WO2023226581A1 - 基于谐波调控的j类分布式功率放大器及其优化方法 - Google Patents

基于谐波调控的j类分布式功率放大器及其优化方法 Download PDF

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WO2023226581A1
WO2023226581A1 PCT/CN2023/084167 CN2023084167W WO2023226581A1 WO 2023226581 A1 WO2023226581 A1 WO 2023226581A1 CN 2023084167 W CN2023084167 W CN 2023084167W WO 2023226581 A1 WO2023226581 A1 WO 2023226581A1
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harmonic
power amplifier
impedance
class
load impedance
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PCT/CN2023/084167
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English (en)
French (fr)
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王琮
魏宇琛
谭笑
宋文昊
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王琮
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/42—Modifications of amplifiers to extend the bandwidth
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/36—Circuit design at the analogue level
    • G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/56—Modifications of input or output impedances, not otherwise provided for
    • H03F1/565—Modifications of input or output impedances, not otherwise provided for using inductive elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
    • H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
    • H03F3/193—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only with field-effect devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H03F3/211—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only using a combination of several amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/36—Indexing scheme relating to amplifiers the amplifier comprising means for increasing the bandwidth
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/451—Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

Definitions

  • the present invention relates to an ultra-wideband power amplifier. Specifically, by establishing a J-class distributed power amplifier circuit architecture, a high-octave high-efficiency distributed amplifier based on artificial transmission line harmonic impedance optimization and a design method thereof are proposed.
  • Ultra-wideband technology has its high speed, high stealth, high penetration capability, and anti-interference ability.
  • low cost and other advantages occupy an important position in the field of communication and testing, and are widely used in electronic countermeasures, military communications, wireless communication test systems, electromagnetic compatibility (Electro Magnetic Compatibility, EMC) test systems, etc.
  • EMC Electro Magnetic Compatibility
  • the power amplifier at the transmitting end has always been one of the important devices that affects key indicators such as link efficiency, power, and gain.
  • applications such as electronic warfare, EMC test systems, and wireless communication test systems have put forward ultra-bandwidth, high efficiency, high power, and high integration requirements for power amplifiers.
  • gallium nitride As a third-generation semiconductor material, gallium nitride has become the first choice for producing ultra-wideband monolithic microwave integrated amplifiers due to its high power density, good heat dissipation performance, anti-interference ability, and excellent high-frequency characteristics.
  • FIG. 1 shows the circuit structure topology of a traditional asymmetric distributed power amplifier (Non-uniform Distributed Amplifier, NDA).
  • the purpose of the invention is to solve the problem of low amplifier output power, efficiency and gain in distributed amplifiers caused by the loss of reverse transmission of part of the output signal, the frequency variation characteristics of the optimal load impedance, the uneven driving state of transistors at different positions, etc. problem, and provide a high-octave high-efficiency distributed amplifier based on artificial transmission line harmonic impedance optimization and its optimization method.
  • the distributed power amplifier based on harmonic control of the present invention includes an input artificial uniform transmission line and an output artificial non-uniform transmission line.
  • Uniform transmission line and multiple gain units, the two ports of the output artificial non-uniform transmission line are connected to reactive terminals (L 1 and L 2 ), and an RC parallel resonant circuit is connected to the gate of the transistor in each gain unit.
  • This invention completes the extraction of parameters such as input and output capacitance and output impedance of each transistor based on the physically based accurate large-signal power tube model, and designs input and output artificial transmission lines and reactive terminal networks to achieve impedance matching of transistors and good port voltage stability.
  • the use of wave coefficient distributed architecture greatly expands the operating bandwidth of the power amplifier.
  • the power-synthesizing Class J distributed ultra-wideband power amplifier of the present invention includes two distributed power amplifiers based on harmonic control, a power distribution network, a power synthesis network and a Class J amplifier output matching network.
  • the two ports of the power distribution network are connected to the two ports respectively.
  • the inputs of two distributed power amplifiers based on harmonic control are coupled with artificial uniform transmission lines.
  • the outputs of two distributed power amplifiers based on harmonic control are artificially coupled with non-uniform transmission lines using a power synthesis network.
  • the power synthesis network is coupled with the output matching network of the class J amplifier. cascade.
  • the hybrid cascaded multi-octave class J distributed power amplifier of the present invention includes a driver stage power amplification unit, a (lumped) broadband matching network and a power synthesized class J distributed ultra-wideband power amplifier, which are successively staged along the signal transmission direction. It is a Class J distributed ultra-wideband power amplifier that connects a driver stage power amplification unit, a broadband matching network and power synthesis.
  • the driver stage power amplification unit is composed of a negative feedback network and a common source-cascode-cascode three-stage stacked structure in parallel.
  • the optimization method of the distributed power amplifier based on harmonic control of the present invention is implemented according to the following steps:
  • Step 1 Divide the working frequency band into ⁇ f 1 , ⁇ f 2 and ⁇ f 3 , set the fundamental frequency to f 1 (f 1 ⁇ ⁇ f 1 ), and use load pull to obtain the optimal fundamental wave load impedance Z 10 , and Z 10 will be used as ⁇ f
  • the second or third fixed harmonic load impedance at the frequency point in the 2 band, the second harmonic load impedance of class J mode f 1 is calculated by the following formula (1.1):
  • V DD is the power supply voltage
  • V K is the knee voltage of the transistor
  • I max is the maximum drain current of the transistor
  • -1 ⁇ 1 is a constant parameter
  • R optB 2(V DD -V K )/I max It is the optimal load impedance for the fundamental wave of Class B PA (radio frequency power amplifier);
  • Z 30 is affected by the second harmonic load impedance Z 32 and the third harmonic load impedance Z 33 ;
  • G CD(1) is the best characteristic conductance of the drain line of the first section
  • G OPT(1) is the best fundamental conductance of the first-stage transistor
  • G CD(n) is the drain line of the nth section.
  • the best characteristic conductance, G DL is the drain terminal resistance
  • G OPT( k) is the optimal fundamental conductance of the k-th transistor;
  • the initial value of the gate line impedance is determined by the following formula:
  • G CG(i) is the best characteristic conductance of the i-th gate line
  • G IN(k) is the input conductance of the k-th transistor
  • the present invention analyzes the parasitic parameters of broadband transistors based on a high-precision physical base model, and designs a high-octave, high-efficiency Class J non-uniform distributed power amplifier based on a comprehensive harmonic control method.
  • this Class J non-uniformly distributed power amplifier has the advantages of high efficiency, large power and wide bandwidth: first, the non-uniformly distributed amplifier can accurately control the impedance of each level and reduce artificial transmission line losses; second, Ultra-wideband power synthesis achieves high power output and ensures high power density of a single chip; thirdly, load-pull-based harmonic control comprehensive technology is applied to distributed amplifiers, and Class J is introduced for the first time on the basis of traditional distributed amplifiers.
  • the amplifier matching network effectively improves efficiency while maintaining ultra-wideband operation.
  • the present invention proposes an ultra-wideband J-class power amplifier harmonic impedance control method and a J-class distributed amplifier design method; adding a pure reactive terminal network to the NDA terminal open-circuit structure can not only improve The port characteristics improve system stability, and can integrate the terminal network structure into the matching network to improve circuit utilization; a high-performance driver stage is achieved through a three-level stacking structure and a parallel negative feedback network, and the input port is connected in series with a first-order equalizer matching network.
  • the finally realized power amplifier has the characteristics of high power, high efficiency, ultra-wideband, high gain and high integration.
  • This invention is based on the research foundation of the accurate ASM (Advanced Spice Model) physical model, and designs a multi-octave high-performance distributed amplifier, including an improved compact ultra-wideband high-balanced power synthesizer circuit under the NDA structure, and a Class J distribution under load pull Type amplifier circuit and hybrid cascade drive amplifier circuit, analyze the circuit principle from the basic theoretical structure and optimize the circuit design based on the circuit model.
  • ASM Advanced Spice Model
  • it includes: using an improved NDA with a purely reactive terminal network to improve input and output characteristics; conducting modeling by studying the coupled tap inductor structure to effectively realize the design of an ultra-miniaturized, ultra-wideband, and highly balanced power synthesizer; using harmonic load traction technology, effectively realize the harmonic impedance optimization of Class B biased power amplifiers, and construct a high-efficiency Class J distributed amplifier circuit; optimize the high-frequency characteristic impedance complex characteristics of artificial transmission lines to achieve harmonic control of Class J distributed amplifiers; optimize the output matching network to achieve A compromise between high-efficiency harmonic control and maximum output power; a negative feedback reactive broadband amplifier is designed as the driver stage, and an extremely high system gain index is obtained in a smaller size through a hybrid cascade method.
  • the invention makes it possible to use a single power amplifier chip to perform multi-band transmission, can reduce physical space and system complexity, expand the application scope of the chip, and is suitable for both military and civilian applications. Solving problems such as insufficient domestic production capacity has high social value. At the same time, the monolithic integrated ultra-wideband power amplifier chip can control the cost very well, which is much lower than the price of the same type of modules currently on the market, and has high economic value.
  • Figure 1 is a schematic diagram of the circuit structure topology of a traditional NDA
  • Figure 2 is a circuit architecture diagram of a distributed power amplifier based on harmonic regulation according to the first embodiment
  • Figure 3 is a circuit architecture diagram of the power-synthesized Class J distributed ultra-wideband power amplifier described in the second embodiment
  • Figure 4 is the circuit of the hybrid cascaded multi-octave Class J distributed power amplifier described in the third embodiment. Architecture diagram;
  • Figure 5 is a small signal test chart of a distributed power amplifier based on harmonic control in the embodiment, where a represents the return loss and b represents the gain;
  • Figure 6 is a large signal test chart of a distributed power amplifier based on harmonic control in the embodiment, where ⁇ represents output power, ⁇ represents gain, and - represents efficiency.
  • the distributed power amplifier based on harmonic control in this embodiment includes an input artificial uniform transmission line 1, an output artificial non-uniform transmission line 2 and a plurality of gain units 3.
  • the two ports of the output artificial non-uniform transmission line 2 are connected with a reactance type
  • the terminals 4 (L 1 and L 2 ) have an RC parallel resonant circuit connected to the gate of the transistor in each gain unit 3 .
  • Specific Embodiment 2 The difference between this embodiment and Specific Embodiment 1 is that the output end of the artificial non-uniform transmission line 2 is connected to a Class J (amplifier output) matching network.
  • Class J amplifier output
  • the power-synthesized Class J distributed ultra-wideband power amplifier includes two distributed power amplifiers based on harmonic control, a power distribution network 5, a power synthesis network 6 and a Class J amplifier output matching network 11.
  • the two ports of the power distribution network 5 are respectively coupled to the input artificial uniform transmission lines 1 of the two distributed power amplifiers based on harmonic control, and the output artificial non-uniform transmission lines 2 of the two distributed power amplifiers based on harmonic control adopt a power synthesis network. 6 coupling, the power synthesis network 6 is cascaded with the class J amplifier output matching network 11.
  • the present invention uses a lumped power divider and power combiner based on tapped coupling inductors to solve the problems of large area and narrow bandwidth in traditional power synthesis. It uses planar film inductive coupling technology to reduce the required inductance and obtain small-size passive devices. .
  • the hybrid cascaded multi-octave Class J distributed power amplifier includes a driver stage power amplification unit, a (lumped) broadband matching network 7 and a power-synthesized Class J distributed ultra-wideband power amplifier.
  • the driver stage power amplification unit, the broadband matching network 7 and the power synthesized class J distributed ultra-wideband power amplifier are sequentially cascaded, in which the driver stage power amplification unit is composed of a negative feedback network 8 and a common source-cascode-cascode
  • the three-level stacking structure is composed of 9 parallel connections.
  • This implementation uses a power-synthesized Class J distributed ultra-wideband power amplifier as the output stage, and simultaneously designs and integrates a miniaturized negative feedback reactive drive wideband power amplifier, using a hybrid cascade method to achieve high-power and high-gain output of the MMIC power amplifier.
  • the transistors adopt a common source-common gate-common gate three-stage stack structure to obtain higher and flatter gain and bandwidth, thereby obtaining a higher gain-bandwidth product; a parallel negative feedback network structure is used, and the network
  • the series resistance and series reactance in the amplifier improve the gain flatness and transistor stability under large bandwidth; a first-order equalizer is connected in series at the input port as a gain compensation network to obtain excellent broadband matching and gain consistency.
  • a lumped broadband matching network is applied to realize the hybrid cascade of reactive and distributed amplifiers to achieve high-gain MMIC power amplifiers under ultra-wideband.
  • Embodiment 5 The difference between this implementation and the fourth implementation is that a gain compensation network 10 is coupled between the signal input end and the drive stage power amplification unit.
  • Embodiment 6 The difference between this implementation and the fifth implementation is that the gain compensation network 10 is a first-order equalizer.
  • Step 1 Divide the working frequency band into ⁇ f 1 , ⁇ f 2 and ⁇ f 3 , set the fundamental frequency to f 1 (f 1 ⁇ f 1 ), and use load pulling The optimal fundamental load impedance Z 10 is obtained. At the same time, Z 10 will be used as the second or third fixed harmonic load impedance at the frequency point in the ⁇ f 2 frequency band.
  • the second harmonic load impedance of f 1 in Class J mode is given by the following formula (1.1 ) is calculated as:
  • V DD is the power supply voltage
  • V K is the knee voltage of the transistor
  • I max is the maximum drain current of the transistor
  • -1 ⁇ 1 is a constant parameter
  • R optB 2(V DD -V K )/I max It is the optimal load impedance for the fundamental wave of Class B PA (radio frequency power amplifier);
  • Z 30 is affected by the second harmonic load impedance Z 32 and the third harmonic load impedance Z 33 ;
  • G CD(1) is the best characteristic conductance of the drain line of the first section
  • G OPT(1) is the best fundamental conductance of the first-stage transistor
  • G CD(n) is the drain line of the nth section.
  • the best characteristic conductance, G DL is the drain terminal resistance
  • G OPT( k) is the optimal fundamental conductance of the k-th transistor;
  • the initial value of the gate line impedance is determined by the following formula:
  • G CG(i) is the best characteristic conductance of the i-th gate line
  • G IN(k) is the input conductance of the k-th transistor
  • This implementation can absorb the non-negligible imaginary component of the artificial transmission line at the high-frequency end into the output matching network of the Class J amplifier, thereby obtaining a harmonic-controlled Class J distributed amplifier with low loss, large bandwidth and high efficiency.
  • This implementation uses load pull technology to optimize high-order harmonics to obtain the impact of high-order harmonics on output power and efficiency; second, analyze the relationship between the impact of improved NDA high-frequency fundamental wave and low-frequency harmonic impedance on output efficiency and power; third 3. Analyze the impact of each harmonic impedance and fundamental impedance of the Class J ultra-wideband power amplifier on the output power and efficiency based on the harmonic fundamental impedance deployment model. Based on the analysis results, the key factors affecting the efficiency and power mathematical model of the Class J ultra-wideband power amplifier are obtained. Parameters, key parameters include fundamental wave impedance, harmonic impedance, termination load, working mode, etc.
  • Specific Embodiment 9 The difference between this implementation and Specific Embodiment 7 or 8 is that in step five, the gate line and the drain line are terminated with inductors L 1 and L 2 respectively.
  • Embodiment 1 The distributed power amplifier based on harmonic control in this embodiment includes an input artificial uniform transmission line, an output artificial non-uniform transmission line and multiple gain units.
  • the reverse port of the output artificial non-uniform transmission line is connected to a reactive terminal.
  • An RC parallel resonant circuit is connected to the gate of the transistor in each gain unit.
  • Embodiment 2 In this embodiment, the optimization method of distributed power amplifier based on harmonic control is implemented according to the following steps:
  • the impedance is calculated by the following formula (1.1):
  • V DD is the power supply voltage
  • V K is the knee voltage of the transistor
  • I max is the maximum drain current of the transistor
  • -1 ⁇ 1 is a constant parameter
  • R optB 2(V DD -V K )/I max It is the optimal load impedance for the fundamental wave of Class B PA (radio frequency power amplifier);
  • Z 30 is affected by the second harmonic load impedance Z 32 and the third harmonic load impedance Z 33 ;
  • G CD(1) is the best characteristic conductance of the drain line of the first section
  • G OPT(1) is the best fundamental conductance of the first-stage transistor
  • G CD(n) is the drain line of the nth section.
  • Conductance G OPT(k) is the optimal fundamental wave conductance of the k-th transistor;
  • the initial value of the gate line impedance is determined by the following formula:
  • G CG(i) is the best characteristic conductance of the i-th gate line
  • G IN(k) is the input conductance of the k-th transistor
  • the small-signal results in Figure 5 demonstrate that the power amplifier has a flat gain of over 18dB and a return loss of over -10dB in the 2-18GHz range.
  • the large-signal results in Figure 6 demonstrate a maximum saturated output power of over 43dBm (20W) and a power-added efficiency of greater than 30% from 2-18GHz, a result that far exceeds that of traditional distributed amplifiers.
  • the characteristics of ultra-wideband, high efficiency and high gain of the class J distributed amplifier proposed by the present invention are proved.

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Abstract

基于谐波调控的J类分布式功率放大器及其优化方法，本发明的目的是为了解决分布式放大器中不同位置晶体管的不均匀驱动状态等导致的放大器输出功率、效率与增益较低的问题。本发明基于谐波调控的分布式功率放大器包括输入人工均匀传输线、输出人工非均匀传输线和多个增益单元，输出人工非均匀传输线的两端口连接有电抗式终端，在每个增益单元中晶体管的栅极上连接有RC并联谐振电路。本发明基于负载牵引方法利用谐波调控技术，在NDA终端开路结构加入纯电抗式终端网络，既能改善端口特性提高系统稳定性，又能将终端网络结构融入匹配网络，提高电路利用率，使该功率放大器具有大功率、高效率、超宽带、高增益、高集成度等特点。

Description

基于谐波调控的J类分布式功率放大器及其优化方法 技术领域
本发明涉及一种超宽带功率放大器，具体通过建立J类分布式功放电路架构，提出一种基于人工传输线谐波阻抗优化的高倍频程高效率分布式放大器及其设计方法。
背景技术
随着世界通讯技术的快速发展革新以及军事作战系统覆盖领域的不断扩大，通信系统所处的电磁环境变得日益复杂，超宽带技术由于其高速率、高隐秘性、高穿透能力、抗干扰、低成本等优势在通信、测试领域占据重要地位，广泛应用于电子对抗、军事通信、无线通信测试系统、电磁兼容(Electro Magnetic Compatibility,EMC)测试系统等。根据香农定理，带宽的增加会带来通信容量的线性增加，而通过增加功率的方式来提高通信容量，需付出的代价将成指数倍增长。超宽带技术作为一种新型、高速、短距离无线技术，所使用的带宽可达数个倍频程，在频谱资源压力与日剧增的情况下，超宽带技术开辟出一条全新的频谱资源利用道路。
整个射频链路中，发射末端的功放一直是影响链路效率、功率、增益等关键指标的重要设备之一。近年来，电子战、EMC测试系统、无线通信测试系统等应用均对功放提出了超带宽、高效率、高功率、高集成化等要求。作为第三代半导体材料的氮化镓因其高功率密度，良好的散热性能与抗干扰能力，优良的高频特性，成为制作超宽带单片微波集成功放的首选。
如今，基于氮化镓工艺的单片微波集成电路(Monolithic Microwave Integrated Circuit,MMIC)正在被逐步引入到商用射频微波系统中。对于功放而言，通常其工作频率范围达到几个倍频程时被称为超宽带功放。超宽带功放应用于射频系统中时，需要在宽频带上获得适当且平坦的增益，因此分布式放大器(Distributed Amplifier，DA)应运而生。分布式放大器的栅极线电感和漏极线电感与功放器件的栅漏电容和漏源电容构成人工传输线，能够在极宽的频带上实现平坦增益，且非常适合单片集成，因此单片集成氮化镓超宽带分布式功放的建模、设计与工艺的研究均是当前热点，图1为传统非对称分布式功率放大器(Non-uniform Distributed Amplifier，NDA)的电路结构拓扑。然而，相比于窄带功放，如此宽频带的工作场合给电路和系统的设计带来了诸多挑战，尤其是功放的设计，其主要指标如输出功率(Pout)、增益(Gain)和功率附加效率(Power Added Efficiency，PAE)等一直难以提升。
发明内容
本发明的目的是为了解决分布式放大器中因部分输出信号反向传输的损耗、最佳负载阻抗的频变特性、不同位置晶体管的不均匀驱动状态等导致的放大器输出功率、效率与增益较低的问题，而提供一种基于人工传输线谐波阻抗优化的高倍频程高效率分布式放大器及其优化方法。
本发明基于谐波调控的分布式功率放大器包括输入人工均匀传输线、输出人工非 均匀传输线和多个增益单元，输出人工非均匀传输线的两端口连接有电抗式终端(L1和L2)，在每个增益单元中晶体管的栅极上连接有RC并联谐振电路。
本发明根据物理基精准大信号功率管模型，完成各晶体管输入输出电容以及输出阻抗等参量的提取，并设计出输入输出人工传输线和电抗式终端网络，实现晶体管的阻抗匹配以及良好的端口电压驻波系数分布式架构的使用大大拓展了功率放大器的工作带宽。
本发明功率合成的J类分布式超宽带功率放大器包括两个基于谐波调控的分布式功率放大器、功率分配网络、功率合成网络和J类放大器输出匹配网络，功率分配网络的两端口分别与两个基于谐波调控的分布式功率放大器的输入人工均匀传输线耦合，两个基于谐波调控的分布式功率放大器的输出人工非均匀传输线采用功率合成网络耦合，功率合成网络与J类放大器输出匹配网络级联。
本发明混合级联式多倍频程J类分布式功率放大器包括驱动级功率放大单元、(集总式)宽带匹配网络和功率合成的J类分布式超宽带功率放大器，沿信号传输方向依次级联驱动级功率放大单元、宽带匹配网络和功率合成的J类分布式超宽带功率放大器，其中驱动级功率放大单元由负反馈网络与共源-共栅-共栅三级堆叠结构并联组成。
本发明基于谐波调控的分布式功率放大器的优化方法按照以下步骤实现：
步骤一、将工作频段分为Δf1、Δf2和Δf3，设置基频为f1(f1∈Δf1)，采用负载牵引得到最佳基波负载阻抗Z10，同时Z10将作为Δf2频段内频点的二次或三次固定谐波负载阻抗，f1的J类模式二次谐波负载阻抗由下式(1.1)计算得到：
其中，VDD是电源电压，VK是晶体管的膝电压，Imax是晶体管的最大漏极电流，-1≤α≤1是常量参数，RoptB＝2(VDD-VK)/Imax是B类PA(射频功率放大器)的基波最佳负载阻抗；
步骤二、设置基波为f2(f2∈Δf2，f1＝2f2)，将Z10固定为二次谐波负载阻抗，即Z22＝Z10，进行负载牵引，得到最佳基波负载阻抗Z20，Z20受二次谐波负载阻抗Z22影响；
步骤三、设置基频为f3(f3∈Δf3，f1＝3f3)，将Z10固定为三次谐波负载阻抗，即Z33＝Z10，将Z20固定为二次谐波负载阻抗，即Z32＝Z20，进行负载牵引，得到最佳基波负载阻抗Z30，Z30受二次谐波负载阻抗Z32和三次谐波负载阻抗Z33影响；
步骤四、将最佳基波阻抗代入下式中计算漏极线阻抗初值：
GCD(1)＝GOPT(1)      (1.2)
其中，GCD(1)为第1节漏极线的最佳特征电导，GOPT(1)为第1级晶体管的最佳基波电导，GCD(n)为第n节漏极线的最佳特征电导，GDL为漏极端接电阻，GOPT(n)＝1/ROPT(n)＝re(Zopt(n))为第n级晶体管的最佳基波电导，GOPT(k)为第k级晶体管的最佳基波电导；
栅极线阻抗初值由下式确定：
其中，GCG(i)为第i节栅极线的最佳特征电导，GIN(k)为第k级晶体管的输入电导；
此外，栅极线电长度与漏极线电长度满足以下关系，式中θCG(i)为第i节栅极线的电长度，θCD(i)为第i节漏极线的电长度：
θCG(i)＝θCD(i)      (1.5)
步骤五：将Δf1频段的二次谐波阻抗端接至纯电抗部分，实现J类工作模式，调节栅极线和漏极线电长度，在满足θCG(i)＝θCD(i)的条件下引入电抗以抵消最佳基波阻抗的虚部分量，完成基于谐波调控的分布式功率放大器的优化。
本发明根据高精度物理基模型分析宽带晶体管寄生参量，设计基于谐波调控综合方法的高倍频程高效率J类非均匀分布式功放。该J类非均匀分布式功放与传统功放相比具有效率高、功率大、带宽大的优势：第一、非均匀分布式放大器能精准控制每一级阻抗，减小人工传输线损耗；第二、超宽带功率合成实现了大功率输出，保证了单片的高功率密度；第三、基于负载牵引的谐波调控综合技术应用于分布式放大器中，首次在传统分布式放大器的基础上引入J类放大器匹配网络，在保持超宽带工作的前提下有效提高了效率。
本发明基于负载牵引方法利用谐波调控技术，提出了一种超宽带J类功放谐波阻抗调控方法和J类分布式放大器设计方法；在NDA终端开路结构加入纯电抗式终端网络，既能改善端口特性提高系统稳定性，又能将终端网络结构融入匹配网络，提高电路利用率；通过三级堆叠结构和并联负反馈网络、输入端口串联一阶均衡器匹配网络实现高性能驱动级。最终实现的功率放大器具有大功率、高效率、超宽带、高增益、高集成度的特点。
本发明基于精准ASM(Advanced Spice Model)物理基模型研究基础，设计多倍频程高性能分布式放大器，包括改进NDA结构下紧凑型超宽带高平衡性功率合成器电路、负载牵引下J类分布式放大器电路以及混合级联驱动放大器电路，根据电路模型从基本理论架构分析电路原理并优化电路设计。具体包括：采用纯电抗终端网络改进型NDA提高输入、输出特性；通过研究耦合抽头电感结构实施建模，有效实现超小型化、超宽带、高平衡性功率合成器的设计；利用谐波负载牵引技术，有效实现B类偏置的功放谐波阻抗优化，构建高效率J类分布式放大器电路；优化人工传输线高频段特性阻抗复数特性实现J类分布式放大器的谐波调控；优化输出匹配网络实现高效率谐波调控与最大输出功率的折中处理；设计负反馈式电抗宽带放大器作为驱动级，通过混合式级联方法以较小的尺寸获得极高的系统增益指标。
本发明使得使用单个功放芯片执行多频带发射成为可能，可以减少物理空间和系统复杂性，拓展芯片应用范围，同时适用于军民两种应用场合。解决国内产能不足等问题，具有很高的社会价值。同时，单片集成的超宽带功率放大器芯片可以很好的控制成本，远低于目前市售同类型模块的价格，有较高的经济价值。
附图说明
图1是传统NDA的电路结构拓扑示意图；
图2是具体实施方式一所述的基于谐波调控的分布式功率放大器的电路架构图；
图3是具体实施方式二所述的功率合成的J类分布式超宽带功率放大器的电路架构图；
图4是具体实施方式三所述的混合级联式多倍频程J类分布式功率放大器的电路架构图；
图5是实施例中基于谐波调控的分布式功率放大器小信号测试图，其中a代表回波损耗，b代表增益；
图6是实施例中基于谐波调控的分布式功率放大器大信号测试图，其中■代表输出功率，▲代表增益，—代表效率。
具体实施方式
具体实施方式一：本实施方式基于谐波调控的分布式功率放大器包括输入人工均匀传输线1、输出人工非均匀传输线2和多个增益单元3，输出人工非均匀传输线2的两端口连接有电抗式终端4(L1和L2)，在每个增益单元3中晶体管的栅极上连接有RC并联谐振电路。
具体实施方式二：本实施方式与具体实施方式一不同的是输出人工非均匀传输线2的输出端连接有J类(放大器输出)匹配网络。
具体实施方式三：本实施方式功率合成的J类分布式超宽带功率放大器包括两个基于谐波调控的分布式功率放大器、功率分配网络5、功率合成网络6和J类放大器输出匹配网络11，功率分配网络5的两端口分别与两个基于谐波调控的分布式功率放大器的输入人工均匀传输线1耦合，两个基于谐波调控的分布式功率放大器的输出人工非均匀传输线2采用功率合成网络6耦合，功率合成网络6与J类放大器输出匹配网络11级联。
本实施方式将两路改进的NDA在输出端口进行宽频功率合成。本发明采用基于抽头耦合电感的集总式功率分配器与功率合成器解决传统功率合成中面积大、带宽窄等问题，采用平面薄膜电感耦合技术减小所需电感量，获得小尺寸无源器件。
具体实施方式四：本实施方式混合级联式多倍频程J类分布式功率放大器包括驱动级功率放大单元、(集总式)宽带匹配网络7和功率合成的J类分布式超宽带功率放大器，沿信号传输方向依次级联驱动级功率放大单元、宽带匹配网络7和功率合成的J类分布式超宽带功率放大器，其中驱动级功率放大单元由负反馈网络8与共源-共栅-共栅三级堆叠结构9并联组成。
本实施方式将功率合成的J类分布式超宽带功率放大器作为输出级，同时设计集成小型化负反馈电抗式驱动宽带功放，采用混合级联方法实现MMIC功放的高功率高增益输出。在驱动级功放中，晶体管采用共源-共栅-共栅三级堆叠结构获得了更高的更平坦的增益和带宽，从而得到更高的增益带宽积；采用并联式负反馈网络结构，网络中的串联电阻和串联电抗改善了大带宽下的增益平坦度和晶体管的稳定性；在输入端口串联一阶均衡器作为增益补偿网络，以获得优良的宽带匹配性和增益一致性。同时，应用集总式宽带匹配网络实现电抗式和分布式放大器的混合级联，实现超宽带下的高增益MMIC功放。
具体实施方式五：本实施方式与具体实施方式四不同的是在信号输入端和驱动级功率放大单元之间耦合有增益补偿网络10。
具体实施方式六：本实施方式与具体实施方式五不同的是增益补偿网络10为一阶均衡器。
具体实施方式七：本实施方式基于谐波调控的分布式功率放大器的优化方法按照以下步骤实施：
步骤一、将工作频段分为Δf1、Δf2和Δf3，设置基频为f1(f1∈Δf1)，采用负载牵 引得到最佳基波负载阻抗Z10，同时Z10将作为Δf2频段内频点的二次或三次固定谐波负载阻抗，f1的J类模式二次谐波负载阻抗由下式(1.1)计算得到：
其中，VDD是电源电压，VK是晶体管的膝电压，Imax是晶体管的最大漏极电流，-1≤α≤1是常量参数，RoptB＝2(VDD-VK)/Imax是B类PA(射频功率放大器)的基波最佳负载阻抗；
步骤二、设置基波为f2(f2∈Δf2，f1＝2f2)，将Z10固定为二次谐波负载阻抗，即Z22＝Z10，进行负载牵引，得到最佳基波负载阻抗Z20，Z20受二次谐波负载阻抗Z22影响；
步骤三、设置基频为f3(f3∈Δf3，f1＝3f3)，将Z10固定为三次谐波负载阻抗，即Z33＝Z10，将Z20固定为二次谐波负载阻抗，即Z32＝Z20，进行负载牵引，得到最佳基波负载阻抗Z30，Z30受二次谐波负载阻抗Z32和三次谐波负载阻抗Z33影响；
步骤四、将最佳基波阻抗代入下式中计算漏极线阻抗初值：
GCD(1)＝GOPT(1)   (1.2)
其中，GCD(1)为第1节漏极线的最佳特征电导，GOPT(1)为第1级晶体管的最佳基波电导，GCD(n)为第n节漏极线的最佳特征电导，GDL为漏极端接电阻，GOPT(n)＝1/ROPT(n)＝re(Zopt(n))为第n级晶体管的最佳基波电导，GOPT(k)为第k级晶体管的最佳基波电导；
栅极线阻抗初值由下式确定：
其中，GCG(i)为第i节栅极线的最佳特征电导，GIN(k)为第k级晶体管的输入电导；
此外，栅极线电长度与漏极线电长度满足以下关系，式中θCG(i)为第i节栅极线的电长度，θCD(i)为第i节漏极线的电长度：
θCG(i)＝θCD(i)      (1.5)
步骤五：将Δf1频段的二次谐波阻抗端接至纯电抗部分，实现J类工作模式，调节栅极线和漏极线电长度，在满足θCG(i)＝θCD(i)的条件下引入电抗以抵消最佳基波阻抗的虚部分量，完成基于谐波调控的分布式功率放大器的优化。
本实施方式可将人工传输线在高频端不可忽略的虚部分量吸收进J类放大器输出匹配网络，从而获得低损耗、大带宽和高效率的谐波调控J类分布式放大器。
本实施方式利用负载牵引技术对高次谐波优化得出高次谐波对输出功率和效率的影响；第二，分析改进NDA高频基波和低频谐波阻抗对输出效率和功率影响的关系；第三，根据谐波基波阻抗调配模型分析J类超宽频功放各谐波阻抗和基波阻抗对输出功率和效率的影响，根据分析结果得出影响J类超宽带功放效率与功率数学模型的关键参数，关键参数包括各级晶体管基波阻抗、谐波阻抗、端接负载、工作模式等；第四，根据上述关键参数设计J类分布式功放电路架构，将人工传输线在高频端不可忽略的虚部分量吸收进J类放大器输出匹配网络，从而获得低损耗、大带宽和高效率的谐波调控J类分布式放大器。
具体实施方式八：本实施方式与具体实施方式七不同的是步骤四中GDL＝0。
具体实施方式九：本实施方式与具体实施方式七或八不同的是步骤五中在栅极线和漏极线分别端接电感L1和L2。
实施例一：本实施例基于谐波调控的分布式功率放大器包括输入人工均匀传输线、输出人工非均匀传输线和多个增益单元，输出人工非均匀传输线的反向端口连接有电抗式终端，在每个增益单元中晶体管的栅极上连接有RC并联谐振电路。
实施例二：本实施例基于谐波调控的分布式功率放大器的优化方法按照以下步骤实施：
步骤一、将带内工作频段分为三部分：Δf1＝9～18GHz、Δf2＝6～9GHz和Δf3＝2～6GHz，Δf1的所有高次谐波均在工作频带外；Δf2的二次谐波落入工作频带内，但三次(或以上)谐波在工作频带外；Δf3的三次(或以上)谐波落入工作频带内；设置基频为f1(f1∈Δf1)，采用负载牵引得到最佳基波负载阻抗Z10，同时Z10将作为Δf2频段内频点的二次或三次固定谐波负载阻抗，f1的J类模式二次谐波负载阻抗由下式(1.1)计算得到：
其中，VDD是电源电压，VK是晶体管的膝电压，Imax是晶体管的最大漏极电流，-1≤α≤1是常量参数，RoptB＝2(VDD-VK)/Imax是B类PA(射频功率放大器)的基波最佳负载阻抗；
步骤二、设置基波为f2(f2∈Δf2，f1＝2f2)，将Z10固定为二次谐波负载阻抗，即Z22＝Z10，进行负载牵引，得到最佳基波负载阻抗Z20，Z20受二次谐波负载阻抗Z22影响；
步骤三、设置基频为f3(f3∈Δf3，f1＝3f3)，将Z10固定为三次谐波负载阻抗，即Z33＝Z10，将Z20固定为二次谐波负载阻抗，即Z32＝Z20，进行负载牵引，得到最佳基波负载阻抗Z30，Z30受二次谐波负载阻抗Z32和三次谐波负载阻抗Z33影响；
步骤四、将最佳基波阻抗代入下式中计算漏极线阻抗初值：
GCD(1)＝GOPT(1)   (1.2)
其中，GCD(1)为第1节漏极线的最佳特征电导，GOPT(1)为第1级晶体管的最佳基波电导，GCD(n)为第n节漏极线的最佳特征电导，GDL为漏极端接电阻，GDL＝0，GOPT(n)＝1/ROPT(n)＝re(Zopt(n))为第n级晶体管的最佳基波电导，GOPT(k)为第k级晶体管的最佳基波电导；
栅极线阻抗初值由下式确定：
其中，GCG(i)为第i节栅极线的最佳特征电导，GIN(k)为第k级晶体管的输入电导；
此外，栅极线电长度与漏极线电长度满足以下关系：
θCG(i)＝θCD(i)   (1.5)
步骤五：在栅极线和漏极线分别端接电感L1和L2，避免了反向回波的功耗，将Δf1频段的二次谐波阻抗端接至纯电抗部分，实现J类工作模式，调节栅极线和漏极线电长度，在满足θCG(i)＝θCD(i)的条件下引入电抗以抵消最佳基波阻抗的虚部分量，完成基于谐波调控的分布式功率放大器的优化。
图5的小信号结果展示了2-18GHz范围内功率放大器具有超过18dB的平坦增益和超过-10dB的回波损耗。图6的大信号结果展示了超过43dBm(20W)的最大饱和输出功率以及2-18GHz内大于30％的功率附加效率，该结果远超传统分布式放大器。证明了本发明提出的J类分布式放大器的超宽带、高效率和高增益的特点。

Claims (3)

  1. 基于谐波调控的分布式功率放大器的优化方法，该基于谐波调控的分布式功率放大器包括输入人工均匀传输线(1)、输出人工非均匀传输线(2)和多个增益单元(3)，输出人工非均匀传输线(2)的两端口连接有电抗式终端(4)，在每个增益单元(3)中晶体管的栅极上连接有RC并联谐振电路；其特征在于该优化方法按照以下步骤实现：
    步骤一、将工作频段分为Δf1、Δf2和Δf3，设置基频为f1，采用负载牵引得到最佳基波负载阻抗Z10，同时Z10将作为Δf2频段内频点的二次或三次固定谐波负载阻抗，f1的J类模式二次谐波负载阻抗由下式(1.1)计算得到：
    其中，VDD是电源电压，VK是晶体管的膝电压，Imax是晶体管的最大漏极电流，-1≤α≤1是常量参数，是B类PA的基波最佳负载阻抗；
    步骤二、设置基波为f2，将Z10固定为二次谐波负载阻抗，即Z22＝Z10，进行负载牵引，得到最佳基波负载阻抗Z20，Z20受二次谐波负载阻抗Z22影响；
    步骤三、设置基频为f3，将Z10固定为三次谐波负载阻抗，即Z33＝Z10，将Z20固定为二次谐波负载阻抗，即Z32＝Z20，进行负载牵引，得到最佳基波负载阻抗Z30，Z30受二次谐波负载阻抗Z32和三次谐波负载阻抗Z33影响；
    步骤四、将最佳基波阻抗代入下式中计算漏极线阻抗初值：
    GCD(1)＝GOPT(1)    (1.2)
    其中，GCD(1)为第1节漏极线的最佳特征电导，GOPT(1)为第1级晶体管的最佳基波电导，GCD(n)为第n节漏极线的最佳特征电导，GDL为漏极端接电阻，GOPT(n)＝1/ROPT(n)＝re(Zopt(n))为第n级晶体管的最佳基波电导，GOPT(k)为第k级晶体管的最佳基波电导；
    栅极线阻抗初值由下式确定：
    其中，GCG(i)为第i节栅极线的最佳特征电导，GIN(k)为第k级晶体管的输入电导；
    此外，栅极线电长度与漏极线电长度满足以下关系，式中θCG(i)为第i节栅极线的电长度，θCD(i)为第i节漏极线的电长度：
    θCG(i)＝θCD(i)     (1.5)
    步骤五：将Δf1频段的二次谐波阻抗端接至纯电抗部分，实现J类工作模式，调节栅极线和漏极线电长度，在满足θCG(i)＝θCD(i)的条件下引入电抗以抵消最佳基波阻抗的虚部分量，完成基于谐波调控的分布式功率放大器的优化。
  2. 根据权利要求1所述的基于谐波调控的分布式功率放大器的优化方法，其特征在于步骤四中GDL＝0。
  3. 根据权利要求1所述的基于谐波调控的分布式功率放大器的优化方法，其特征在于 步骤五中在栅极线和漏极线分别端接电感L1和L2。
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