WO2023226074A1 - 时序逻辑元件性能评估方法及设备 - Google Patents

时序逻辑元件性能评估方法及设备 Download PDF

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Publication number
WO2023226074A1
WO2023226074A1 PCT/CN2022/096858 CN2022096858W WO2023226074A1 WO 2023226074 A1 WO2023226074 A1 WO 2023226074A1 CN 2022096858 W CN2022096858 W CN 2022096858W WO 2023226074 A1 WO2023226074 A1 WO 2023226074A1
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logic element
sequential logic
value
time
target
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PCT/CN2022/096858
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English (en)
French (fr)
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吴增泉
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长鑫存储技术有限公司
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Priority to US17/872,479 priority Critical patent/US12019120B2/en
Publication of WO2023226074A1 publication Critical patent/WO2023226074A1/zh

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking

Definitions

  • Embodiments of the present disclosure relate to the field of semiconductor technology, and in particular, to a sequential logic element performance evaluation method and device.
  • sequential logic components may have different designs (including structure, MOS tube type, etc.). Therefore, how to evaluate the performance of sequential logic components is an urgent technical problem that needs to be solved.
  • Embodiments of the present disclosure provide a method and device for performance evaluation of sequential logic components, which can effectively evaluate the performance of sequential logic components.
  • the present disclosure provides a sequential logic element performance evaluation method, which method includes:
  • sampling value the establishment time is the time difference between the target edge of the clock signal and the target edge of the target sampling value in the data signal, and the first preset value is stably output by the sequential logic element to be tested
  • the setup time when the target sampling value is determined, and the second preset value is determined by the setup time when the sequential logic element to be tested stably outputs the reverse value of the target sampling value;
  • the evaluation parameters of the sequential logic element under test are determined, and based on the evaluation parameters, the performance of the sequential logic element under test is evaluated to evaluate.
  • the evaluation parameter includes an average output delay
  • the sequential logic element under test is determined according to the sample value output by the sequential logic element under test after each decrement of the setup time.
  • Component evaluation parameters including:
  • the sample value output by the sequential logic element under test after each decrement of the setup time, it is determined that the sample value output by the sequential logic element under test is inverted from the target sample value to the reverse direction of the target sample value. value, the first setup time value of the sequential logic element under test;
  • the target edge of the clock signal and the timing sequence under test are completed each time the decrease is completed.
  • the logic element outputs the first average value of the delay time between the target sample values;
  • the first average value is determined as the output delay average value.
  • the evaluation parameters also include a target setup time; and the sequential logic element under test is determined according to the sample value output by the sequential logic element under test after each decrement of the setup time.
  • the evaluation parameters include:
  • the establishment time corresponding to the sum of the mean value and the fixed delay offset is determined as the target establishment time.
  • the evaluation parameter further includes a metastable time; and the sequential logic element under test is determined according to the sampling value output by the sequential logic element under test after each decrement of the establishment time.
  • Component evaluation parameters including:
  • the difference between the establishment time corresponding to the peak value and the inflection point is obtained, and the difference is used as the metastable time.
  • the evaluation parameters also include target holding time; the method further includes:
  • the sample value output by the sequential logic element under test after each decrement of the holding time, it is determined that the sample value output by the sequential logic element under test is inverted from the target sample value to the reverse direction of the target sample value. value, the first holding time value of the sequential logic element under test;
  • the first holding time value is determined as the target holding time.
  • the data signal includes a first data signal and a second data signal with opposite phases
  • the clock signal includes a first clock signal and a second clock signal with opposite phases
  • the logic element includes a first sequential logic element to be tested and a second sequential logic element to be tested
  • the input of preset clock signals and data signals into the sequential logic element to be tested includes:
  • the evaluation parameters further include at least one of the following evaluation parameters:
  • the maximum setup time is the maximum value of the target setup time corresponding to the first sequential logic element to be tested and the target setup time corresponding to the second sequential logic element to be tested;
  • the maximum holding time is the maximum value of the target holding time corresponding to the first sequential logic element to be tested and the target holding time corresponding to the second sequential logic element to be tested;
  • the maximum metastable time is the maximum value of the metastable time corresponding to the first sequential logic element to be tested and the metastable time corresponding to the second sequential logic element to be tested;
  • the setup time deviation is the absolute value of the difference between the target setup time corresponding to the first sequential logic element under test and the target setup time corresponding to the second sequential logic element under test;
  • the hold time deviation is the absolute value of the difference between the target hold time corresponding to the first sequential logic element under test and the target hold time corresponding to the second sequential logic element under test.
  • the present disclosure provides a sequential logic element performance evaluation device, which includes:
  • the input module is used to input the preset clock signal and data signal into the sequential logic element to be tested, and the sequential logic element to be tested is used to sample the data signal according to the clock signal;
  • An adjustment module configured to decrease the establishment time of the sequential logic element to be tested from a first preset value to a second preset value according to a preset decrement step, and record the time of each decrement of the establishment time. Measure the sampling value output by the sequential logic element; the establishment time is the time difference between the target edge of the clock signal and the target edge of the target sampling value in the data signal, and the first preset value is determined by the target edge of the clock signal. The establishment time when the sequential logic element stably outputs the target sampling value is determined, and the second preset value is determined by the establishment time when the sequential logic element to be tested stably outputs the reverse value of the target sampling value;
  • An evaluation module configured to determine the evaluation parameters of the sequential logic element to be tested based on the sampled value output by the sequential logic element to be tested after each decrement of the establishment time, and to evaluate the sequence logic element to be tested based on the evaluation parameters. The performance of sequential logic components is evaluated.
  • the evaluation parameter includes an average output delay
  • the evaluation module is used to:
  • the sample value output by the sequential logic element under test after each decrement of the setup time, it is determined that the sample value output by the sequential logic element under test is inverted from the target sample value to the reverse direction of the target sample value. value, the first setup time value of the sequential logic element under test;
  • the target edge of the clock signal and the timing sequence under test are completed each time the decrease is completed.
  • the logic element outputs the first average value of the delay time between the target sample values;
  • the first average value is determined as the output delay average value.
  • the evaluation parameters also include target establishment time; the evaluation module is also used to:
  • the establishment time corresponding to the sum of the mean value and the fixed delay offset is determined as the target establishment time.
  • the evaluation parameters also include metastable time; the evaluation module is also used to:
  • the difference between the establishment time corresponding to the peak value and the inflection point is obtained, and the difference is used as the metastable time.
  • the evaluation parameters also include target holding time; the adjustment module is also used to:
  • the evaluation module is also used to:
  • the sample value output by the sequential logic element under test after each decrement of the holding time, it is determined that the sample value output by the sequential logic element under test is inverted from the target sample value to the reverse direction of the target sample value. value, the first holding time value of the sequential logic element under test;
  • the first holding time value is determined as the target holding time.
  • the data signal includes a first data signal and a second data signal with opposite phases
  • the clock signal includes a first clock signal and a second clock signal with opposite phases
  • the logic element includes a first sequential logic element to be tested and a second sequential logic element to be tested
  • the input module is used for:
  • the evaluation parameters further include at least one of the following evaluation parameters:
  • the maximum output delay is the maximum value of the output delay average value corresponding to the first sequential logic element to be tested and the output delay average value corresponding to the second sequential logic element to be tested;
  • the maximum setup time is the maximum value of the target setup time corresponding to the first sequential logic element to be tested and the target setup time corresponding to the second sequential logic element to be tested;
  • the maximum holding time is the maximum value of the target holding time corresponding to the first sequential logic element to be tested and the target holding time corresponding to the second sequential logic element to be tested;
  • An uncertain time interval which is the sum of the maximum setup time and the maximum hold time
  • the maximum metastable time is the maximum value of the metastable time corresponding to the first sequential logic element to be tested and the metastable time corresponding to the second sequential logic element to be tested;
  • the setup time deviation is the absolute value of the difference between the target setup time corresponding to the first sequential logic element under test and the target setup time corresponding to the second sequential logic element under test;
  • the hold time deviation is the absolute value of the difference between the target hold time corresponding to the first sequential logic element under test and the target hold time corresponding to the second sequential logic element under test.
  • the memory stores computer execution instructions
  • the at least one processor executes the computer execution instructions stored in the memory, so that the at least one processor executes the sequential logic element performance evaluation method provided in the first aspect.
  • the sequential logic element performance evaluation method and device can invert the output of the sequential logic element under test from the target sampling value to the reverse value of the target sampling value by gradually shortening the establishment time of the sequential logic element to be tested; By measuring or calculating some evaluation parameters of the sequential logic element under test when the output of the sequential logic element under test is inverted from the target sampled value to the reverse value of the target sampled value, and based on these evaluation parameters, the sequential logic element under test can be Effective evaluation of performance can help improve the performance of sequential logic components under test or design based on the performance of sequential logic components and improve the actual circuit or timing.
  • Figure 2 is a schematic flowchart of steps of a sequential logic element performance evaluation method provided in an embodiment of the present disclosure
  • Figure 3 is a schematic diagram of a timing logic provided in an embodiment of the present disclosure.
  • Figure 4 is a schematic diagram 1 of the relationship between delay duration and establishment time provided in an embodiment of the present disclosure
  • Figure 5 is a schematic diagram 2 of the relationship between delay duration and establishment time provided in an embodiment of the present disclosure
  • Figure 6 is a schematic circuit structure diagram of a sequential logic element to be tested provided in an embodiment of the present disclosure
  • Figure 7 is a second sequence logic diagram provided in an embodiment of the present disclosure.
  • Figure 8 is a schematic diagram of a program module of a sequential logic element performance evaluation device provided in an embodiment of the present disclosure
  • FIG. 9 is a schematic diagram of the hardware structure of an electronic device provided by an embodiment of the present disclosure.
  • module refers to any known or later developed hardware, software, firmware, artificial intelligence, fuzzy logic or combination of hardware or/and software code capable of performing the functions associated with that element .
  • PKI process design kits
  • the above-mentioned sequential logic elements can be latch (Latch), flip-flop (Flip Flop, referred to as FF), etc.
  • latches are memory cell circuits that are sensitive to pulse levels. They can change state under the action of a specific input pulse level. Latching is to temporarily store signals to maintain a certain level state. In digital circuits, binary digital signals "0" and "1" can be recorded.
  • a flip-flop also called a bistable gate, is a storage component with two stable states that can record binary digital signals "1" and "0". Its output is determined by the data input at the time specified by the input clock. .
  • the setup time (Setup Time) of the sequential logic element refers to the shortest time that the data input signal must remain stable before the valid edge of the clock; the hold time (Hold time) refers to the data input signal must remain stable after the valid edge of the clock. the shortest time.
  • the sequential logic element can correctly collect the data; and after the valid edge of the clock (or at the same time) At the same time), even if the data changes, it will not affect the output of the sequential logic element.
  • FIG. 1 is a schematic diagram of the setup time and hold time of the sequential logic elements in the embodiment of the present disclosure.
  • sequential logic components may have different designs (including structure, MOS tube type, etc.), making it more difficult to evaluate the performance of sequential logic components.
  • embodiments of the present disclosure provide a method for evaluating the performance of sequential logic elements.
  • the output of the sequential logic element under test can be reversed from the target sample value to the target sample.
  • the inverse value of the value when the output of the sequential logic element under test is inverted from the target sampling value to the inverse value of the target sampling value, some evaluation parameters of the sequential logic element under test can be calculated based on these evaluation parameters. Effectively evaluating the performance of the sequential logic components under test will help improve the performance of the sequential logic components under test.
  • FIG. 2 is a schematic flowchart of steps of a sequential logic element performance evaluation method provided in an embodiment of the present disclosure.
  • the above sequential logic element performance evaluation method includes:
  • a test platform can be established in advance, and software can be used in the test platform to simulate a sequential logic circuit, which includes a sequential logic element to be tested.
  • the above-mentioned sequential logic element to be tested can sample the above-mentioned data signal according to the clock signal.
  • the above sequential logic elements may include latches, flip-flops, etc.
  • a reasonable clock cycle can be selected in advance.
  • a clock signal CK with a clock cycle of 2.5 ns and a duty cycle of 50% can be used.
  • the pulse width of the data signal can also be preset.
  • a data signal D with a pulse width of 675 ps can be used.
  • the above-mentioned establishment time is the time difference between the target edge of the clock signal and the target edge of the target sample value in the above-mentioned data signal.
  • the above-mentioned first preset value is determined by the establishment time when the sequential logic element under test stably outputs the above-mentioned target sampling value
  • the above-mentioned second preset value is determined by the establishment time when the sequential logic element under test stably outputs the inverse value of the above-mentioned target sampling value.
  • the above-mentioned first preset value is greater than the universal setup time of the sequential logic element under test, thereby ensuring that the sequential logic element under test can be stable when the above-mentioned first preset value is used as the setup time.
  • the sequential logic element under test may output the inverse value of the above target sample value because it cannot collect the above target sample value, or Outputs the above target sample value with a higher delay.
  • a value that is much smaller than the universal setup time can be selected as the second preset value, thereby ensuring that the sequential logic element under test uses the second preset value as the setup time.
  • the timing logic element can stably output the inverse value of the above target sampling value.
  • the above-mentioned second preset value can be a negative value, that is, the target edge of the target sample value in the above-mentioned data signal can be located after the target edge of the clock signal, thereby ensuring that the sequential logic element under test cannot collect the target sample value.
  • Figure 3 is a schematic diagram of a sequence logic provided in the embodiment of the present disclosure.
  • the above-mentioned setup time is the time difference between the time corresponding to the rising edge of the clock signal CK and the time corresponding to the rising edge of the data signal D.
  • the establishment time is a positive number; when the rising edge of the data signal D is after the rising edge of the clock signal CK, the establishment time is Time is a negative number.
  • the above-mentioned first preset value can be selected to be a maximum of 650 ps.
  • the above second preset value can be selected as -420ps.
  • first preset value and the second preset value are only exemplary, and in other embodiments, other values may also be selected.
  • the establishment time t1 650ps
  • the establishment time t2 649ps
  • the establishment time t3 648ps; ...; and so on, until the establishment time of the last acquisition 1 is -420ps.
  • S203 Determine the evaluation parameters of the sequential logic element to be tested based on the sample value output by the sequential logic element to be tested after each decrement of the above-mentioned setup time, and evaluate the performance of the sequential logic element to be tested based on the evaluation parameters.
  • some evaluation parameters can be set in advance, such as the output delay, setup time, hold time, metastable time, etc. when the output of the sequential logic element under test inverts from 1 to 0.
  • the performance evaluation result of the sequential logic element can be obtained according to the above-mentioned evaluation parameter and the performance evaluation standard corresponding to the above-mentioned evaluation parameter.
  • the sequential logic element performance evaluation method can invert the output of the sequential logic element under test from the target sampled value to the reverse value of the target sampled value by gradually shortening the setup time of the sequential logic element to be tested; by measuring Or calculate some evaluation parameters of the sequential logic element under test when the output of the sequential logic element under test is reversed from the target sampling value to the reverse value of the target sampling value, and based on these evaluation parameters, the performance of the sequential logic element under test can be evaluated Effective evaluation, thereby helping to improve the performance of the sequential logic components under test.
  • the above evaluation parameters include the output delay average value.
  • Evaluation parameters of the sequential logic components under test include:
  • the third value of the sequential logic element under test is determined.
  • a setup time value in the process of calculating the setup time of the sequential logic element under test decreasing from the first preset value to the first setup time value, the target edge of the clock signal and the output target sample of the sequential logic element under test when each decrease is completed.
  • This waiting time is the clock-to-output delay of the sequential logic element, which is the above-mentioned
  • the delay length can also be understood as the sum of all delays within the sequential logic element from the start of the clock trigger to the output of valid data.
  • the delay time from the clock trigger to the output of valid data Q is tz.
  • the setup time of the sequential logic element when the setup time of the sequential logic element is sufficient, the data signal is relatively stable when the effective edge of the clock signal arrives, so the clock-to-output delay of the sequential logic element will be smaller and the size will be relatively stable. ;
  • the setup time of the sequential logic component When the setup time of the sequential logic component is not sufficient, the data signal may not be in a stable state when the valid edge of the clock signal arrives, so the clock-to-output delay of the sequential logic component will also increase, and the longer the setup time, sufficient, the greater the clock-to-output delay of the sequential logic element;
  • the setup time of the sequential logic element when the setup time of the sequential logic element is reduced to the point where the target sample value cannot be collected when the valid edge of the clock signal arrives, the sequential logic element will fail to output the target sample value. At this point, the clock-to-output delay of the sequential logic element is zero.
  • FIG. 4 is a schematic diagram 1 of the relationship between the delay duration and the setup time provided in the embodiment of the present disclosure.
  • t1 represents the above-mentioned first preset value
  • tn represents the above-mentioned second preset value
  • the abscissa represents the number of decrements of the establishment time
  • the ordinate represents time (unit is ps).
  • the establishment time of the sequential logic element under test decreases to tx, the above delay time suddenly becomes 0, it can be concluded that when the establishment time of the sequential logic element under test decreases to tx, the sequential logic element outputs the target sampling value fail. That is, it is determined that when the sampling value output by the sequential logic element under test is reversed from the target sampling value to the reverse value of the target sampling value, the first setup time value of the sequential logic element under test is tx.
  • the value of the above-mentioned delay time corresponding to each decrease is completed, and then the average value of all the recorded delay times can be calculated, and the value of the delay time can be calculated.
  • the average value is used as the average of the above output delays.
  • the sequential logic element performance evaluation method provided by the embodiments of the present disclosure can invert the output of the sequential logic element under test from the target sampled value to the reverse value of the target sampled value by gradually shortening the setup time of the sequential logic element to be tested; by measuring Or calculate the output delay average of the sequential logic element under test before the output of the sequential logic element under test reverses from the target sampling value to the reverse value of the target sampling value, which can effectively evaluate the delay performance of the sequential logic element under test. Evaluate.
  • the above-mentioned evaluation parameters also include the target setup time.
  • the evaluation parameters of the sequential logic element under test are determined according to the sample value output by the sequential logic element under test after each decrement of the setup time, and further include :
  • the value of the above-mentioned delay time corresponding to each decrease is completed, and then from all recorded Select the smallest delay durations (such as 100) among the delay durations.
  • the fixed delay offset of the sequential logic element under test refers to the inherent transmission delay of the sequential logic element under test to the data signal, or the first inherent transmission delay to the data signal and the second inherent transmission delay to the clock signal. The difference in inherent transmission delays.
  • the performance evaluation method of sequential logic elements selects the smallest delay durations from all recorded delay durations, and then calculates the average value of the selected delay durations, so that it can be determined that the sequential logic element is at its optimal state.
  • the target setup time corresponding to the sequential logic element can be evaluated based on the target setup time to determine whether the setup time of the sequential logic element to be tested is the optimal setup time.
  • the above-mentioned evaluation parameters also include metastable time.
  • the evaluation parameters of the sequential logic element under test are determined based on the sampled value output by the sequential logic element under test after each decrement of the setup time, and further include:
  • the difference between the establishment time corresponding to the peak value and the inflection point is obtained, and the difference is used as the metastable time.
  • FIG. 5 is a second schematic diagram of the relationship between the delay duration and the setup time provided in the embodiment of the present disclosure.
  • t1 represents the above-mentioned first preset value
  • tn represents the above-mentioned second preset value
  • the abscissa represents the number of decrements of the establishment time
  • the ordinate represents time (unit is ps)
  • the above-mentioned decrement step is 1 ps.
  • the inflection point of the curve of the delay duration changing with the number of decrements of the setup time is point K
  • the delay duration corresponding to the inflection point K is tk
  • the number of decrements is Lk
  • the setup time is t1-Lk
  • the peak value is tm
  • the number of decrements corresponding to the above peak value is Lm
  • the establishment time is t1-Lm.
  • the method for evaluating the performance of sequential logic elements measures or calculates the metastable state time of the sequential logic element under test when the output of the sequential logic element under test reverses from the target sampling value to the reverse value of the target sampling value. , the metastable time of the sequential logic element under test can be evaluated.
  • the above-mentioned evaluation parameters also include a target holding time.
  • the holding time of the sequential logic element under test can be reduced from the third preset value to the fourth preset value according to the preset decrement step.
  • the preset value is based on the sample value output by the sequential logic element under test after each decrement of the holding time. Determine the sequence value when the sample value output by the sequential logic element under test reverses from the target sample value to the reverse value of the target sample value.
  • the first holding time value of the logic element is determined as the target holding time.
  • the above-mentioned holding time is the time for the data signal to remain stable after the target edge of the clock signal.
  • the third preset value is determined by the holding time when the sequential logic element to be tested stably outputs the target sampling value.
  • the above-mentioned fourth preset value is determined by The holding time when the sequential logic element stably outputs the reverse value of the target sample value is determined.
  • the universal holding time of the sequential logic element to be tested can be determined first, and then the third preset value is determined based on the universal holding time of the sequential logic element to be tested.
  • the sequential logic element under test when the holding time of the sequential logic element under test is less than its corresponding universal holding time, the sequential logic element under test will output the inverse value of the target sampling value because it cannot collect the target sampling value.
  • a value that is much smaller than the universal holding time can be selected as the fourth preset value, thereby ensuring that the sequential logic element under test uses the fourth preset value as the holding time.
  • the timing logic element can stably output the inverse value of the above target sampling value.
  • the sequential logic element under test since the sequential logic element under test has an inherent transmission delay for the data signal, even if the hold time is a negative value before inputting the sequential logic element under test, that is, the falling edge of the data signal is before the rising edge of the clock signal. , in the actual sampling process, the holding time may be converted to a positive value, that is, the holding time + deviation value is a positive value. In other words, the final calculated target holding time may be a negative value.
  • the above-mentioned evaluation parameters may also include an average current, which is an average current during the entire simulation time period.
  • the performance evaluation method of sequential logic elements provided by the embodiments of the present disclosure can measure or calculate the holding time of the sequential logic element under test when the output of the sequential logic element under test reverses from the target sampling value to the reverse value of the target sampling value. Evaluate the hold time of the sequential logic element under test.
  • the above data signal includes a first data signal and a second data signal with opposite phases
  • the above clock signal includes a first clock signal and a second clock with opposite phases
  • the above-mentioned sequential logic element to be tested includes a first sequential logic element to be tested and a second sequential logic element to be tested.
  • the first clock signal and the first data signal are input to the first sequential logic element to be tested, so as to use the first clock signal to sample the first data signal; the second clock signal and the second data signal are input to the third Two sequential logic elements to be tested, for sampling the second data signal using the second clock signal.
  • FIG. 6 is a schematic circuit structure diagram of a sequential logic element to be tested in an embodiment of the present disclosure.
  • the sequential logic element to be tested includes flip-flop 1 and flip-flop 2.
  • the first clock signal CK and the first data signal Drise are input to the flip-flop 1, so that the rising edge of the first clock signal CK is used to sample the data "1" of the first data signal Drise, and the sampled data Qrise is output.
  • the first data signal Drise and the second data signal Dfall have opposite phases, and the first clock signal CK and the second clock signal CKn have opposite phases.
  • FIG. 7 is a second sequence logic diagram provided in the embodiment of the present disclosure.
  • the above-mentioned evaluation parameters also include at least one of the following evaluation parameters:
  • the maximum output delay is the maximum value of the average output delay corresponding to the first sequential logic element under test and the average output delay corresponding to the second sequential logic element under test.
  • the maximum setup time is the maximum value of the target setup time corresponding to the first sequential logic element under test and the target setup time corresponding to the second sequential logic element under test.
  • the maximum holding time is the maximum value of the target holding time corresponding to the first sequential logic element to be tested and the target holding time corresponding to the second sequential logic element to be tested.
  • the uncertain time interval is the sum of the above-mentioned maximum setup time and maximum hold time.
  • the maximum metastable time is the maximum value of the metastable time corresponding to the first sequential logic element to be tested and the metastable state time corresponding to the second sequential logic element to be tested.
  • the setup time deviation is the absolute value of the difference between the target setup time corresponding to the first sequential logic element under test and the target setup time corresponding to the second sequential logic element under test.
  • the hold time deviation is the absolute value of the difference between the target hold time corresponding to the first sequential logic element under test and the target hold time corresponding to the second sequential logic element under test.
  • the above-mentioned uncertain time interval may be greater than the holding time of the data signal, or may be shorter than the holding time of the data signal.
  • Embodiments of the present disclosure provide a method for evaluating the performance of a sequential logic element by measuring or calculating some evaluations of the sequential logic element under test when the output of the sequential logic element under test is inverted from the target sampling value to the reverse value of the target sampling value. parameters, and based on these evaluation parameters, the performance of the sequential logic element under test can be effectively evaluated more comprehensively and completely, which helps to improve the performance of the sequential logic element under test.
  • an embodiment of the present disclosure also provides a sequential logic element performance evaluation device.
  • Figure 8 is a schematic diagram of a program module of a sequential logic element performance evaluation device provided in an embodiment of the present disclosure.
  • the sequential logic element performance evaluation device includes:
  • the input module 801 is used to input preset clock signals and data signals into the sequential logic element to be tested, and the sequential logic element to be tested is used to sample the data signal according to the clock signal.
  • the adjustment module 802 is configured to decrease the setup time of the sequential logic element to be tested from a first preset value to a second preset value according to a preset decrement step, and record the steps after each decrement of the setup time.
  • the sampling value output by the sequential logic element to be tested; the establishment time is the time difference between the target edge of the clock signal and the target edge of the target sampling value in the data signal, and the first preset value is determined by the target edge of the clock signal.
  • the setup time when the sequential logic element under test stably outputs the target sample value is determined, and the second preset value is determined by the setup time when the sequential logic element to be tested stably outputs the reverse value of the target sample value.
  • the evaluation module 803 is configured to determine the evaluation parameters of the sequential logic element to be tested based on the sample value output by the sequential logic element to be tested after each decrement of the establishment time, and to evaluate the sequential logic element to be tested based on the evaluation parameters. Evaluate the performance of sequential logic components.
  • the evaluation parameters include output delay average
  • the evaluation module 803 is used to:
  • the sample value output by the sequential logic element under test after each decrement of the setup time, it is determined that the sample value output by the sequential logic element under test is inverted from the target sample value to the reverse direction of the target sample value. value, the first setup time value of the sequential logic element under test;
  • the target edge of the clock signal and the timing sequence under test are completed each time the decrease is completed.
  • the logic element outputs the first average value of the delay time between the target sample values;
  • the first average value is determined as the output delay average value.
  • the evaluation parameters also include the target establishment time; the evaluation module 803 is also used to:
  • the establishment time corresponding to the sum of the mean value and the fixed delay offset is determined as the target establishment time.
  • the evaluation parameters also include metastable time; the evaluation module 803 is also used to:
  • the difference between the establishment time corresponding to the peak value and the inflection point is obtained, and the difference is used as the metastable time.
  • the evaluation parameters also include the target holding time; the adjustment module 802 is also used to:
  • the holding time of the sequential logic element to be tested is decreased from a third preset value to a fourth preset value, and the sequential logic element to be tested is recorded after each decrement of the holding time.
  • the sampling value output by the component; the holding time is the time for the data signal to remain stable after the target edge of the clock signal, and the third preset value is stably output by the sequential logic component to be tested to the target sample.
  • the holding time when the value is determined, and the fourth preset value is determined by the holding time when the sequential logic element to be tested stably outputs the reverse value of the target sampling value;
  • Evaluation module 803 is also used to:
  • the sample value output by the sequential logic element under test after each decrement of the holding time, it is determined that the sample value output by the sequential logic element under test is inverted from the target sample value to the reverse direction of the target sample value. value, the first holding time value of the sequential logic element under test;
  • the first holding time value is determined as the target holding time.
  • the data signal includes a first data signal and a second data signal with opposite phases
  • the clock signal includes a first clock signal and a second clock signal with opposite phases
  • the logic element includes a first sequential logic element to be tested and a second sequential logic element to be tested
  • Input module 801 is used for:
  • the evaluation parameters further include at least one of the following evaluation parameters:
  • the maximum output delay is the maximum value of the output delay average value corresponding to the first sequential logic element to be tested and the output delay average value corresponding to the second sequential logic element to be tested;
  • the maximum setup time is the maximum value of the target setup time corresponding to the first sequential logic element to be tested and the target setup time corresponding to the second sequential logic element to be tested;
  • the maximum holding time is the maximum value of the target holding time corresponding to the first sequential logic element to be tested and the target holding time corresponding to the second sequential logic element to be tested;
  • An uncertain time interval which is the sum of the maximum setup time and the maximum hold time
  • the maximum metastable time is the maximum value of the metastable time corresponding to the first sequential logic element to be tested and the metastable time corresponding to the second sequential logic element to be tested;
  • the setup time deviation is the absolute value of the difference between the target setup time corresponding to the first sequential logic element to be tested and the target setup time corresponding to the second sequential logic element to be tested;
  • the hold time deviation is the absolute value of the difference between the target hold time corresponding to the first sequential logic element under test and the target hold time corresponding to the second sequential logic element under test.
  • embodiments of the present disclosure also provide an electronic device, which includes at least one processor and a memory; wherein the memory stores computer execution instructions; the at least one processor The computer execution instructions stored in the memory are executed to implement each step in the sequential logic element performance evaluation method as described in the above embodiment, which will not be described again in this embodiment.
  • FIG. 9 is a schematic diagram of the hardware structure of an electronic device provided by an embodiment of the present disclosure.
  • the electronic device 90 of this embodiment includes: a processor 901 and a memory 902; wherein:
  • Memory 902 used to store computer execution instructions
  • the processor 901 is configured to execute computer execution instructions stored in the memory to implement various steps in the sequential logic element performance evaluation method described in the above embodiments. For details, please refer to the relevant descriptions in the foregoing method embodiments.
  • the memory 902 can be independent or integrated with the processor 901 .
  • the device When the memory 902 is provided independently, the device also includes a bus 903 for connecting the memory 902 and the processor 901 .
  • the disclosed devices and methods can be implemented in other ways.
  • the device embodiments described above are only illustrative.
  • the division of modules is only a logical function division. In actual implementation, there may be other division methods, for example, multiple modules may be combined or integrated. to another system, or some features can be ignored, or not implemented.
  • the coupling or direct coupling or communication connection between each other shown or discussed may be through some interfaces, indirect coupling or communication connection of devices or modules, and may be in electrical, mechanical or other forms.
  • the aforementioned program can be stored in a computer-readable storage medium.
  • the steps including the above-mentioned method embodiments are executed; and the aforementioned storage media include: ROM, RAM, magnetic disks, optical disks and other media that can store program codes.

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Abstract

本公开实施例提供一种时序逻辑元件性能评估方法及设备，涉及半导体技术领域，包括：将预设的时钟信号与数据信号输入待测时序逻辑元件，根据预设递减步长，将待测时序逻辑元件的建立时间从第一预设值递减至第二预设值，其中，第一预设值由待测时序逻辑元件稳定输出目标采样值时的建立时间确定，第二预设值由待测时序逻辑元件稳定输出目标采样值的反向值时的建立时间确定；根据上述建立时间每次递减后待测时序逻辑元件输出的采样值，确定待测时序逻辑元件的评估参数，并根据该评估参数，对待测时序逻辑元件的性能进行评估。本公开实施例可以对时序逻辑元件的性能进行有效的评估。

Description

时序逻辑元件性能评估方法及设备
本公开要求于2022年05月26日提交中国专利局、申请号为202210582260.9、申请名称为“时序逻辑元件性能评估方法及设备”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开实施例涉及半导体技术领域，尤其涉及一种时序逻辑元件性能评估方法及设备。
背景技术
目前，在进行基于标准单元库的专用集成电路(Application Specific Integrated Circuit，简称ASIC)设计时，代工厂通常会提供工艺设计工具包(Process Design Kit，简称PDK)，其包含如触发器、锁存器等时序逻辑元件的设计和特性参数(如建立时间或保持时间等)。
其中，在全定制电路设计以及工艺开发阶段，时序逻辑元件可能有不同的设计(包括结构、MOS管类型等)。因此，如何对时序逻辑元件的性能进行评估，是目前亟需解决的技术问题。
发明内容
本公开实施例提供了一种时序逻辑元件性能评估方法及设备，可以对时序逻辑元件的性能进行有效的评估。
第一方面，本公开提供一种时序逻辑元件性能评估方法，该方法包括：
将预设的时钟信号与数据信号输入待测时序逻辑元件，所述待测时序逻辑元件用于根据所述时钟信号对所述数据信号进行采样；
根据预设递减步长，将所述待测时序逻辑元件的建立时间从第一预设值递减至第二预设值，并记录所述建立时间每次递减后所述待测时序逻辑元件输出的采样值；所述建立时间为所述时钟信号的目标沿与所述数据信号中目标采样值的目标沿之间的时间差，所述第一预设值由所述待测时序逻辑元件稳定输出所述目标采样值时的建立时间确定，所述第二预设值由所述待测时序逻辑元件稳定输出所述目标采样值的反向值时的建立时间确定；
根据所述建立时间每次递减后所述待测时序逻辑元件输出的采样值，确定所述待测时序逻辑元件的评估参数，并根据所述评估参数，对所述待测时序逻辑元件的性能 进行评估。
在一种可行的实施方式中，所述评估参数包括输出延时平均值，所述根据所述建立时间每次递减后所述待测时序逻辑元件输出的采样值，确定所述待测时序逻辑元件的评估参数，包括：
根据所述建立时间每次递减后所述待测时序逻辑元件输出的采样值，确定所述待测时序逻辑元件输出的采样值从所述目标采样值反转为所述目标采样值的反向值时，所述待测时序逻辑元件的第一建立时间值；
计算所述待测时序逻辑元件的建立时间从所述第一预设值递减至所述第一建立时间值的过程中，每次递减完成时所述时钟信号的目标沿与所述待测时序逻辑元件输出所述目标采样值之间的延迟时长的第一均值；
将所述第一均值确定为所述输出延时平均值。
在一种可行的实施方式中，所述评估参数还包括目标建立时间；所述根据所述建立时间每次递减后所述待测时序逻辑元件输出的采样值，确定所述待测时序逻辑元件的评估参数，包括：
选取最小的若干个所述延迟时长；
计算选取的若干个所述延迟时长的均值与所述待测时序逻辑元件的固定延时偏移量的和；
将所述均值与所述固定延时偏移量的和对应的建立时间确定为所述目标建立时间。
在一种可行的实施方式中，所述评估参数还包括亚稳态时间；所述根据所述建立时间每次递减后所述待测时序逻辑元件输出的采样值，确定所述待测时序逻辑元件的评估参数，包括：
绘制所述延迟时长随所述建立时间的递减次数变化的曲线，并确定所述曲线的拐点与峰值；
获取所述峰值与所述拐点对应的所述建立时间的差值，且将所述差值作为所述亚稳态时间。
在一种可行的实施方式中，所述评估参数还包括目标保持时间；所述方法还包括：
根据所述预设递减步长，将所述待测时序逻辑元件的保持时间从第三预设值递减至第四预设值，并记录所述保持时间每次递减后所述待测时序逻辑元件输出的采样值；所述保持时间为所述时钟信号的目标沿之后，所述数据信号保持稳定的时间，所述第三预设值由所述待测时序逻辑元件稳定输出所述目标采样值时的保持时间确定，所述第四预设值由所述待测时序逻辑元件稳定输出所述目标采样值的反向值时的保持时间确定；
根据所述保持时间每次递减后所述待测时序逻辑元件输出的采样值，确定所述待测时序逻辑元件输出的采样值从所述目标采样值反转为所述目标采样值的反向值时，所述待测时序逻辑元件的第一保持时间值；
将所述第一保持时间值确定为所述目标保持时间。
在一种可行的实施方式中，所述数据信号包括相位相反的第一数据信号与第二数据信号，所述时钟信号包括相位相反的第一时钟信号和第二时钟信号，所述待测时序逻辑元件包括第一待测时序逻辑元件与第二待测时序逻辑元件；
所述将预设的时钟信号与数据信号输入待测时序逻辑元件，包括：
将所述第一时钟信号与所述第一数据信号输入所述第一待测时序逻辑元件，以利用所述第一时钟信号对所述第一数据信号进行采样；将所述第二时钟信号与所述第二数据信号输入所述第二待测时序逻辑元件，以利用所述第二时钟信号对所述第二数据信号进行采样。
在一种可行的实施方式中，所述评估参数还包括以下评估参数中的至少一种：
最大输出延时，为所述第一待测时序逻辑元件对应的所述输出延时平均值与所述第二待测时序逻辑元件对应的所述输出延时平均值的最大值；
最大建立时间，为所述第一待测时序逻辑元件对应的所述目标建立时间与所述第二待测时序逻辑元件对应的所述目标建立时间的最大值；
最大保持时间，为所述第一待测时序逻辑元件对应的所述目标保持时间与所述第二待测时序逻辑元件对应的所述目标保持时间的最大值；
不确定时间区间，所述不确定时间区间为所述最大建立时间与所述最大保持时间的和；
最大亚稳态时间，为所述第一待测时序逻辑元件对应的所述亚稳态时间与所述第二待测时序逻辑元件对应的所述亚稳态时间的最大值；
建立时间偏差，为所述第一待测时序逻辑元件对应的所述目标建立时间与所述第二待测时序逻辑元件对应的所述目标建立时间之差的绝对值；
保持时间偏差，为所述第一待测时序逻辑元件对应的所述目标保持时间与所述第二待测时序逻辑元件对应的所述目标保持时间之差的绝对值。
第二方面，本公开提供一种时序逻辑元件性能评估装置，该装置包括：
输入模块，用于将预设的时钟信号与数据信号输入待测时序逻辑元件，所述待测时序逻辑元件用于根据所述时钟信号对所述数据信号进行采样；
调节模块，用于根据预设递减步长，将所述待测时序逻辑元件的建立时间从第一预设值递减至第二预设值，并记录所述建立时间每次递减后所述待测时序逻辑元件输出的采样值；所述建立时间为所述时钟信号的目标沿与所述数据信号中目标采样值的目标沿之间的时间差，所述第一预设值由所述待测时序逻辑元件稳定输出所述目标采样值时的建立时间确定，所述第二预设值由所述待测时序逻辑元件稳定输出所述目标采样值的反向值时的建立时间确定；
评估模块，用于根据所述建立时间每次递减后所述待测时序逻辑元件输出的采样值，确定所述待测时序逻辑元件的评估参数，并根据所述评估参数，对所述待测时序 逻辑元件的性能进行评估。
在一种可行的实施方式中，所述评估参数包括输出延时平均值，所述评估模块用于：
根据所述建立时间每次递减后所述待测时序逻辑元件输出的采样值，确定所述待测时序逻辑元件输出的采样值从所述目标采样值反转为所述目标采样值的反向值时，所述待测时序逻辑元件的第一建立时间值；
计算所述待测时序逻辑元件的建立时间从所述第一预设值递减至所述第一建立时间值的过程中，每次递减完成时所述时钟信号的目标沿与所述待测时序逻辑元件输出所述目标采样值之间的延迟时长的第一均值；
将所述第一均值确定为所述输出延时平均值。
在一种可行的实施方式中，所述评估参数还包括目标建立时间；所述评估模块还用于：
选取最小的若干个所述延迟时长；
计算选取的若干个所述延迟时长的均值与所述待测时序逻辑元件的固定延时偏移量的和；
将所述均值与所述固定延时偏移量的和对应的建立时间确定为所述目标建立时间。
在一种可行的实施方式中，所述评估参数还包括亚稳态时间；所述评估模块还用于：
绘制所述延迟时长随所述建立时间的递减次数变化的曲线，并确定所述曲线的拐点与峰值；
获取所述峰值与所述拐点对应的所述建立时间的差值，且将所述差值作为所述亚稳态时间。
在一种可行的实施方式中，所述评估参数还包括目标保持时间；所述调节模块还用于：
根据所述预设递减步长，将所述待测时序逻辑元件的保持时间从第三预设值递减至第四预设值，并记录所述保持时间每次递减后所述待测时序逻辑元件输出的采样值；所述保持时间为所述时钟信号的目标沿之后，所述数据信号保持稳定的时间，所述第三预设值由所述待测时序逻辑元件稳定输出所述目标采样值时的保持时间确定，所述第四预设值由所述待测时序逻辑元件稳定输出所述目标采样值的反向值时的保持时间确定；
所述评估模块还用于：
根据所述保持时间每次递减后所述待测时序逻辑元件输出的采样值，确定所述待测时序逻辑元件输出的采样值从所述目标采样值反转为所述目标采样值的反向值时，所述待测时序逻辑元件的第一保持时间值；
将所述第一保持时间值确定为所述目标保持时间。
在一种可行的实施方式中，所述数据信号包括相位相反的第一数据信号与第二数据信号，所述时钟信号包括相位相反的第一时钟信号和第二时钟信号，所述待测时序逻辑元件包括第一待测时序逻辑元件与第二待测时序逻辑元件；
所述输入模块用于：
将所述第一时钟信号与所述第一数据信号输入所述第一待测时序逻辑元件，以利用所述第一时钟信号对所述第一数据信号进行采样；将所述第二时钟信号与所述第二数据信号输入所述第二待测时序逻辑元件，以利用所述第二时钟信号对所述第二数据信号进行采样。
在一种可行的实施方式中，所述评估参数还包括以下评估参数中的至少一种：
最大输出延时，为所述第一待测时序逻辑元件对应的所述输出延时平均值与所述第二待测时序逻辑元件对应的所述输出延时平均值的最大值；
最大建立时间，为所述第一待测时序逻辑元件对应的所述目标建立时间与所述第二待测时序逻辑元件对应的所述目标建立时间的最大值；
最大保持时间，为所述第一待测时序逻辑元件对应的所述目标保持时间与所述第二待测时序逻辑元件对应的所述目标保持时间的最大值；
不确定时间区间，所述不确定时间区间为所述最大建立时间与所述最大保持时间的和；
最大亚稳态时间，为所述第一待测时序逻辑元件对应的所述亚稳态时间与所述第二待测时序逻辑元件对应的所述亚稳态时间的最大值；
建立时间偏差，为所述第一待测时序逻辑元件对应的所述目标建立时间与所述第二待测时序逻辑元件对应的所述目标建立时间之差的绝对值；
保持时间偏差，为所述第一待测时序逻辑元件对应的所述目标保持时间与所述第二待测时序逻辑元件对应的所述目标保持时间之差的绝对值。
第三方面，本公开提供一种电子设备，包括：至少一个处理器和存储器；
所述存储器存储计算机执行指令；
所述至少一个处理器执行所述存储器存储的计算机执行指令，使得所述至少一个处理器执行如第一方面提供的时序逻辑元件性能评估方法。
本公开实施例提供的时序逻辑元件性能评估方法及设备，通过逐步缩短待测时序逻辑元件的建立时间，可以使待测时序逻辑元件输出从目标采样值反转为目标采样值的反向值；通过测量或计算待测时序逻辑元件的输出从目标采样值反转为目标采样值的反向值时，待测时序逻辑元件的一些评估参数，并根据这些评估参数，可以对待测时序逻辑元件的性能进行有效的评估，从而有助于提升待测时序逻辑元件的性能或者基于时序逻辑元件的性能设计并改良实际电路或时序。
附图说明
图1为本公开实施例中时序逻辑元件的建立时间与保持时间示意图；
图2为本公开实施例中提供的一种时序逻辑元件性能评估方法的步骤流程示意图；
图3为本公开实施例中提供的一种时序逻辑示意图一；
图4为本公开实施例中提供的一种延迟时长与建立时间的关系示意图一；
图5为本公开实施例中提供的一种延迟时长与建立时间的关系示意图二；
图6为本公开实施例中提供的一种待测时序逻辑元件的电路结构示意图；
图7为本公开实施例中提供的一种时序逻辑示意图二；
图8为本公开实施例中提供的一种时序逻辑元件性能评估装置的程序模块示意图；
图9为本公开实施例提供的一种电子设备的硬件结构示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。此外，虽然本公开中公开内容按照示范性一个或几个实例来介绍，但应理解，可以就这些公开内容的各个方面也可以单独构成一个完整实施方式。
需要说明的是，本公开中对于术语的简要说明，仅是为了方便理解接下来描述的实施方式，而不是意图限定本公开的实施方式。除非另有说明，这些术语应当按照其普通和通常的含义理解。
本公开中说明书和权利要求书及上述附图中的术语“第一”、“第二”等是用于区别类似或同类的对象或实体，而不必然意味着限定特定的顺序或先后次序，除非另外注明。应该理解这样使用的用语在适当情况下可以互换，例如能够根据本公开实施例图示或描述中给出那些以外的顺序实施。
此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖但不排他的包含，例如，包含了一系列组件的产品或设备不必限于清楚地列出的那些组件，而是可包括没有清楚地列出的或对于这些产品或设备固有的其它组件。
本公开实施例中使用的术语“模块”，是指任何已知或后来开发的硬件、软件、固件、人工智能、模糊逻辑或硬件或/和软件代码的组合，能够执行与该元件相关的功能。
在半导体技术领域中，在进行基于标准单元库的ASIC设计流程中，芯片设计者采用硬件描述语言设计芯片，即对芯片功能进行建模，然后运用自动化设计软件将设计代码综合成标准单元电路，进而通过物理后端设计将标准单元电路转换成对应制程工艺下可制造的图形数据流文件(Graphic Data Stream，简称GDS)版图，最后由代工厂生产芯片。
其中，在进行基于标准单元库的ASIC设计时，代工厂通常会预先提供工艺设计 工具包(Process Design Kit，简称PDK)，其会包含一些时序逻辑元件的设计和特性参数(如建立时间或保持时间等)。
可选的，上述时序逻辑元件可以为锁存器(Latch)、触发器(Flip Flop，简称FF)等。
其中，锁存器是一种对脉冲电平敏感的存储单元电路，它们可以在特定输入脉冲电平作用下改变状态。锁存，就是把信号暂存以维持某种电平状态，在数字电路中则可以记录二进制数字信号“0”和“1”。
触发器也叫双稳态门，是一种具有两种稳态的用于储存的组件，可记录二进制数字信号“1”和“0”，其输出由输入时钟所规定的时刻的数据输入确定。
时序逻辑元件的建立时间(Setup Time)是指在时钟有效沿之前，数据输入端信号必须保持稳定的最短时间；保持时间(Hold time)是指在时钟有效沿之后，数据输入端信号必须保持稳定的最短时间。
可以理解的是，在理想情况下，只要在时钟有效沿来临时，有效数据也来临(时钟有效沿之前或同时)，则时序逻辑元件便能够正确采集到数据；而在时钟有效沿之后(或同时)，即使数据发生变化，也不会影响时序逻辑元件的输出了。
然而在实际情况中，时钟沿打开开关需要时间，逻辑门的状态改变(电容充放电等)也都需要时间，因此数据的采集是需要一定时间的，在这个时间内数据不能发生变化，即在时钟有效沿来临之前，数据必须提前一个最小时间量“预先准备好”，这个最小时间量就是上述建立时间。另外，时钟沿关闭开关也需要时间，如果在这个时间段内数据有变化的话，那么新数据就有可能被传递到下一级，进而发生错误，所以数据必须保持一定时间不变，即在时钟有效沿来临之后，数据必须保持一个最小时间量“不能变化”，这个最小时间量就是上述保持时间。
为了更好的理解本公开实施例，参照图1，图1为本公开实施例中时序逻辑元件的建立时间与保持时间示意图。
在图1中，在时钟信号CK的上升沿来之前，数据信号D须提前一个最小时间量“预先准备好”，且不能变化，这个最小时间量就是建立时间；另外，在时钟信号CK的上升沿来之后，数据D仍旧须保持一个最小时间量不能变化，这个最小时间量就是保持时间。
目前，在全定制电路设计以及工艺开发阶段，时序逻辑元件可能有不同的设计(包括结构、MOS管类型等)，导致对时序逻辑元件的性能评估难度增大。
面对上述技术问题，本公开实施例提供了一种时序逻辑元件性能评估方法，通过逐步缩短待测时序逻辑元件的建立时间，可以使待测时序逻辑元件输出从目标采样值反转为目标采样值的反向值；通过测量或计算待测时序逻辑元件的输出从目标采样值反转为目标采样值的反向值时，待测时序逻辑元件的一些评估参数，并根据这些评估参数，可以对待测时序逻辑元件的性能进行有效的评估，有助于提升待测时序逻辑元 件的性能。具体实施方式请参见以下实施例中的内容。
参照图2，图2为本公开实施例中提供的一种时序逻辑元件性能评估方法的步骤流程示意图。在本公开一些实施例中，上述时序逻辑元件性能评估方法包括：
S201、将预设的时钟信号与数据信号输入待测时序逻辑元件。
在一些实施方式中，可以预先建立测试平台，并在该测试平台中采用软件模拟出时序逻辑电路，该时序逻辑电路中包括待测时序逻辑元件。
其中，上述待测时序逻辑元件可以根据时钟信号对上述数据信号进行采样。
可选的，上述时序逻辑元件可以包括锁存器、触发器等。
在一些实施方式中，可以预先选取合理的时钟周期，如本公开一些实施例中可以采用时钟周期为2.5ns、占空比为50％的时钟信号CK。
在一些实施方式中，还可以预先设置数据信号的脉冲宽度，如本公开一些实施例中可以采用脉冲宽度为675ps的数据信号D。
S202、根据预设递减步长，将待测时序逻辑元件的建立时间从第一预设值递减至第二预设值，并记录建立时间每次递减后待测时序逻辑元件输出的采样值。
其中，上述建立时间为时钟信号的目标沿与上述数据信号中目标采样值的目标沿之间的时间差。上述第一预设值由待测时序逻辑元件稳定输出上述目标采样值时的建立时间确定，上述第二预设值由待测时序逻辑元件稳定输出上述目标采样值的反向值时的建立时间确定。
在一种可行的实施方式中，可以先确定待测时序逻辑元件的通用建立时间，然后根据待测时序逻辑元件的通用建立时间确定第一预设值。
可选的，上述第一预设值大于待测时序逻辑元件的通用建立时间，由此可以保证待测时序逻辑元件在采用上述第一预设值作为建立时间时，待测时序逻辑元件能够稳定输出上述目标采样值。
可以理解的是，当待测时序逻辑元件的建立时间小于其对应的通用建立时间时，待测时序逻辑元件可能会因为无法采集到上述目标采样值而输出上述目标采样值的反向值，或者以较高的延迟输出上述目标采样值。在本公开一些实施例中，可以选择一个远小于上述通用建立时间的值作为上述第二预设值，由此可以保证待测时序逻辑元件在采用上述第二预设值作为建立时间时，待测时序逻辑元件能够稳定输出上述目标采样值的反向值。
其中，当上述目标采样值为“1”时，上述目标采样值的反向值为“0”；相反，当上述目标采样值为“0”时，上述目标采样值的反向值为“1”。
可选的，上述第二预设值可以为负值，即上述数据信号中目标采样值的目标沿可以位于时钟信号的目标沿之后，由此可以保证待测时序逻辑元件无法采集到目标采样值。
为了更好的理解本公开实施例，参照图3，图3为本公开实施例中提供的一种时 序逻辑示意图一。
在图3中，假设数据信号D的脉冲宽度p等于675ps，上述建立时间为时钟信号CK的上升沿对应的时刻与上述数据信号D的上升沿对应的时刻之间的时间差。
可以理解的是，当上述数据信号D的上升沿位于时钟信号CK的上升沿之前时，上述建立时间为正数；当上述数据信号D的上升沿位于时钟信号CK的上升沿之后时，上述建立时间则为负数。
在一种可行的实施方式中，假设待测时序逻辑元件的最小保持时间为25ps，则上述第一预设值最大可以选用650ps。
可选的，上述第二预设值可以选用-420ps。
需要说明的是，上述第一预设值与第二预设值的取值仅仅只是示例性的，在其它一些实施例中，也可以选用其它的值。
在仿真过程中，对于待测时序逻辑元件的每一次采样，按照预设递减步长，将待测时序逻辑元件的建立时间进行递减，并记录待测时序逻辑元件每次采样输出的采样值。
示例性的，如图3所示，假设上述递减步长为1ps，则在第一次采集目标采样值1时，建立时间t1＝650ps；第二次采集1时，建立时间t2＝649ps；第三次采集1时，建立时间t3＝648ps；……；依次类推，直至到最后一次采集1的建立时间为-420ps为止。
S203、根据上述建立时间每次递减后待测时序逻辑元件输出的采样值，确定待测时序逻辑元件的评估参数，并根据该评估参数，对待测时序逻辑元件的性能进行评估。
可以理解的是，当待测时序逻辑元件的建立时间在递减到某一个值后，待测时序逻辑元件就会因为无法采集到上述目标采样值1，而输出上述目标采样值的反向值0。因此，在本公开一些实施例中，可以预先设置一些评估参数，如待测时序逻辑元件的输出从1反转为0时的输出延时、建立时间、保持时间及亚稳态时间等。在仿真完成后，根据上述建立时间每次递减后待测时序逻辑元件输出的采样值，确定出待测时序逻辑元件的输出从1反转为0时的临界点，然后检测或计算出上述评估参数在该临界点的值。
在检测或计算出上述评估参数在上述临界点的值之后，可以根据上述评估参数以及上述评估参数对应的性能评估标准，来得到时序逻辑元件的性能评估结果。
本公开实施例提供的时序逻辑元件性能评估方法，通过逐步缩短待测时序逻辑元件的建立时间，可以使待测时序逻辑元件输出从目标采样值反转为目标采样值的反向值；通过测量或计算待测时序逻辑元件的输出从目标采样值反转为目标采样值的反向值时，待测时序逻辑元件的一些评估参数，并根据这些评估参数，可以对待测时序逻辑元件的性能进行有效的评估，从而有助于提升待测时序逻辑元件的性能。
基于上述实施例中所描述的内容，在本公开一些实施例中，上述评估参数包括输出延时平均值，上述步骤S203中根据建立时间每次递减后待测时序逻辑元件输出的采 样值，确定待测时序逻辑元件的评估参数，包括：
根据建立时间每次递减后待测时序逻辑元件输出的采样值，确定待测时序逻辑元件输出的采样值从目标采样值反转为目标采样值的反向值时，待测时序逻辑元件的第一建立时间值；计算待测时序逻辑元件的建立时间从第一预设值递减至第一建立时间值的过程中，每次递减完成时时钟信号的目标沿与待测时序逻辑元件输出目标采样值之间的延迟时长的第一均值；将该第一均值确定为上述输出延时平均值。
可以理解的是，在时钟信号的有效沿到达后，数据信号的目标采样值并不能立即传到时序逻辑元件的输出端，这段等待的时间为时序逻辑元件的时钟到输出延时，即上述延迟时长，也可以理解为是从时钟触发开始到有效数据输出，时序逻辑元件内部所有延时的总和。
如图3所示，从时钟触发开始到有效数据Q输出的延迟时长为tz。
可以理解的是，当时序逻辑元件的建立时间较充足时，在时钟信号的有效沿到达时，数据信号也比较稳定，因此时序逻辑元件的时钟到输出延时也会比较小，且大小比较稳定；当时序逻辑元件的建立时间不够充足时，在时钟信号的有效沿到达时，数据信号可能并不处于稳定状态，因此时序逻辑元件的时钟到输出延时也会增大，且建立时间越不充足，时序逻辑元件的时钟到输出延时越大；当时序逻辑元件的建立时间减小到无法在时钟信号的有效沿到达时采集到目标采样值，则时序逻辑元件会输出目标采样值失败，此时，时序逻辑元件的时钟到输出延时为零。
为了更好的理解本公开实施例，参照图4，图4为本公开实施例中提供的一种延迟时长与建立时间的关系示意图一。
在图4中，t1表示上述第一预设值，tn表示上述第二预设值，横坐标表示建立时间的递减次数，纵坐标表示时间(单位为ps)。
从图4中可以看出，当待测时序逻辑元件的建立时间从t1递减至ty的过程中，上述延迟时长比较小，且比较稳定；当待测时序逻辑元件的建立时间从ty递减至tx的过程中，上述延迟时长会逐渐增大，然后突然变为0；之后，待测时序逻辑元件的建立时间从tx递减至tn的过程中，上述延迟时长会一直保持为0。
其中，由于待测时序逻辑元件的建立时间递减至tx时，上述延迟时长突然变为0，由此可以得出，待测时序逻辑元件的建立时间递减至tx时，时序逻辑元件输出目标采样值失败。即可以确定出待测时序逻辑元件输出的采样值从目标采样值反转为目标采样值的反向值时，待测时序逻辑元件的第一建立时间值为tx。
在一些实施例中，可以记录待测时序逻辑元件的建立时间从t1递减至tx的过程中，每次递减完成时对应的上述延迟时长的值，然后计算记录的所有延迟时长的均值，将该均值作为上述输出延时平均值。
本公开实施例提供的时序逻辑元件性能评估方法，通过逐步缩短待测时序逻辑元件的建立时间，可以使待测时序逻辑元件输出从目标采样值反转为目标采样值的反向 值；通过测量或计算待测时序逻辑元件的输出从目标采样值反转为目标采样值的反向值之前，待测时序逻辑元件的输出延时平均值，可以对待测时序逻辑元件的时延性能进行有效的评估。
在本公开一些实施例中，上述评估参数还包括目标建立时间，上述步骤S203中根据建立时间每次递减后待测时序逻辑元件输出的采样值，确定待测时序逻辑元件的评估参数，还包括：
选取最小的若干个上述延迟时长；计算选取的若干个延迟时长的均值与待测时序逻辑元件的固定延时偏移量的和，将上述均值与固定延时偏移量的和对应的建立时间确定为上述目标建立时间。
仍旧参照图4，在本公开一些实施例中，可以记录待测时序逻辑元件的建立时间从t1递减至tx的过程中，每次递减完成时对应的上述延迟时长的值，然后从记录的所有延迟时长中选择最小的若干个(如100个)延迟时长。
计算已选择的若干个延迟时长的均值与待测时序逻辑元件的固定延时偏移量的和，记为tc；从图4中查找出待测时序逻辑元件对应的延迟时长为tc时，待测时序逻辑元件对应的建立时间，并将该建立时间确定为上述目标建立时间。可以理解的是，待测时序逻辑元件的固定延迟偏移量指的是待测时序元件对数据信号的固有传输延迟，或者说是对数据信号的第一固有传输延迟和对时钟信号的第二固有传输延迟的差值。
本公开实施例提供的时序逻辑元件性能评估方法，通过从记录的所有延迟时长中选择最小的若干个延迟时长，然后计算已选择的若干个延迟时长的均值，可以确定出时序逻辑元件在处于最优输出状态时，时序逻辑元件对应的目标建立时间，基于该目标建立时间可以对待测时序逻辑元件的建立时间是否为最优建立时间进行评估。
在本公开一些实施例中，上述评估参数还包括亚稳态时间，上述步骤S203中根据建立时间每次递减后待测时序逻辑元件输出的采样值，确定待测时序逻辑元件的评估参数，还包括：
绘制所述延迟时长随所述建立时间的递减次数变化的曲线，并确定所述曲线的拐点与峰值；
获取所述峰值与所述拐点对应的所述建立时间的差值，且将所述差值作为所述亚稳态时间。
为了更好的理解本公开实施例，参照图5，图5为本公开实施例中提供的延迟时长与建立时间的关系示意图二。
在图5中，t1表示上述第一预设值，tn表示上述第二预设值，横坐标表示建立时间的递减次数，纵坐标表示时间(单位为ps)，上述递减步长为1ps。
在本公开一些实施例中，假设上述延迟时长随上述建立时间的递减次数变化的曲线的拐点为点K，拐点K对应的延迟时长为tk，递减次数为Lk，建立时间为t1-Lk；上述峰值为tm，且上述峰值对应的递减次数为Lm，建立时间为t1-Lm。则上述亚稳 态时间可以由以下方式计算：
亚稳态时间＝Lm-Lk
本公开实施例提供的时序逻辑元件性能评估方法，通过测量或计算待测时序逻辑元件的输出从目标采样值反转为目标采样值的反向值时，待测时序逻辑元件的亚稳态时间，可以对待测时序逻辑元件的亚稳态时间进行评估。
在本公开一些实施例中，上述评估参数还包括目标保持时间，在一些实施例中，可以根据预设递减步长，将待测时序逻辑元件的保持时间从第三预设值递减至第四预设值，根据保持时间每次递减后待测时序逻辑元件输出的采样值，确定待测时序逻辑元件输出的采样值从目标采样值反转为目标采样值的反向值时，待测时序逻辑元件的第一保持时间值，将该第一保持时间值确定为上述目标保持时间。
其中，上述保持时间为时钟信号的目标沿之后，数据信号保持稳定的时间，第三预设值由待测时序逻辑元件稳定输出目标采样值时的保持时间确定，上述第四预设值由待测时序逻辑元件稳定输出目标采样值的反向值时的保持时间确定。
在一种可行的实施方式中，可以先确定待测时序逻辑元件的通用保持时间，然后根据待测时序逻辑元件的通用保持时间确定出第三预设值。
可以理解的是，当待测时序逻辑元件的保持时间小于其对应的通用保持时间时，待测时序逻辑元件就会因为无法采集到上述目标采样值而输出上述目标采样值的反向值。在本公开一些实施例中，可以选择一个远小于上述通用保持时间的值作为上述第四预设值，由此可以保证待测时序逻辑元件在采用上述第四预设值作为保持时间时，待测时序逻辑元件能够稳定输出上述目标采样值的反向值。
在一些实施例中，由于待测时序逻辑元件对数据信号具有固有传输延迟，因此在输入待测时序逻辑元件之前，即便保持时间为负值，即数据信号的下降沿在时钟信号的上升沿之前，在实际采样过程中，保持时间可能转换为正值，即保持时间+偏差值为正值。也就是说，最后计算出来的目标保持时间可能是负值。
在一些实施例中，上述评估参数还可以包括平均电流，该平均电流为整个仿真时间段的平均电流。
本公开实施例提供的时序逻辑元件性能评估方法，通过测量或计算待测时序逻辑元件的输出从目标采样值反转为目标采样值的反向值时，待测时序逻辑元件的保持时间，可以对待测时序逻辑元件的保持时间进行评估。
基于上述实施例中所描述的内容，在本公开一些实施例中，上述数据信号包括相位相反的第一数据信号与第二数据信号，上述时钟信号包括相位相反的第一时钟信号和第二时钟信号，上述待测时序逻辑元件包括第一待测时序逻辑元件与第二待测时序逻辑元件。在进行仿真时，将第一时钟信号与第一数据信号输入第一待测时序逻辑元件，以利用第一时钟信号对第一数据信号进行采样；将第二时钟信号与第二数据信号输入第二待测时序逻辑元件，以利用第二时钟信号对第二数据信号进行采样。
为了更好的理解本公开实施例，参照图6，图6为本公开实施例中提供的一种待测时序逻辑元件的电路结构示意图。
在图6中，待测时序逻辑元件包括触发器1与触发器2。在进行仿真时，将第一时钟信号CK与第一数据信号Drise输入触发器1，以利用第一时钟信号CK的上升沿对第一数据信号Drise的数据“1”进行采样，输出采样数据Qrise；将第二时钟信号CKn与第二数据信号Dfall输入触发器2，以利用第二时钟信号CKn的下降沿对第二数据信号Dfall的数据“0”进行采样，输出采样数据Qfall。
其中，第一数据信号Drise与第二数据信号Dfall的相位相反，第一时钟信号CK与第二时钟信号CKn的相位相反。
为了更好的理解本公开实施例，参照图7，图7为本公开实施例中提供的一种时序逻辑示意图二。
可以理解的是，通过逐渐缩小触发器1的建立时间，可以检测出触发器1输出的采样数据Qrise从“1”反转为“0”时，触发器1的以下评估参数：输出延时平均值、目标建立时间、亚稳态时间及目标保持时间。
通过逐渐缩小触发器2的建立时间，可以检测出触发器2输出的采样数据Qfall从“0”反转为“1”时，触发器2的以下评估参数：输出延时平均值、目标建立时间、亚稳态时间及目标保持时间。
在本公开一些实施例中，上述评估参数还包括以下评估参数中的至少一种：
最大输出延时，为第一待测时序逻辑元件对应的输出延时平均值与第二待测时序逻辑元件对应的输出延时平均值的最大值。
最大建立时间，为第一待测时序逻辑元件对应的目标建立时间与第二待测时序逻辑元件对应的目标建立时间的最大值。
最大保持时间，为第一待测时序逻辑元件对应的目标保持时间与第二待测时序逻辑元件对应的目标保持时间的最大值。
不确定时间区间，为上述最大建立时间与最大保持时间的和。
最大亚稳态时间，为第一待测时序逻辑元件对应的亚稳态时间与第二待测时序逻辑元件对应的亚稳态时间的最大值。
建立时间偏差，为第一待测时序逻辑元件对应的目标建立时间与第二待测时序逻辑元件对应的目标建立时间之差的绝对值。
保持时间偏差，为第一待测时序逻辑元件对应的目标保持时间与第二待测时序逻辑元件对应的目标保持时间之差的绝对值。
在一些实施例中，上述不确定时间区间可能大于数据信号的保持时间，也有可能小于数据信号的保持时间。
本公开实施例提供了一种时序逻辑元件性能评估方法，通过测量或计算待测时序逻辑元件的输出从目标采样值反转为目标采样值的反向值时，待测时序逻辑元件的一 些评估参数，并根据这些评估参数，可以更加全面、完整的对待测时序逻辑元件的性能进行有效的评估，有助于提升待测时序逻辑元件的性能。
基于上述实施例中描述的内容，本公开实施例中还提供一种时序逻辑元件性能评估装置。参照图8，图8为本公开实施例中提供的一种时序逻辑元件性能评估装置的程序模块示意图，该时序逻辑元件性能评估装置包括：
输入模块801，用于将预设的时钟信号与数据信号输入待测时序逻辑元件，所述待测时序逻辑元件用于根据所述时钟信号对所述数据信号进行采样。
调节模块802，用于根据预设递减步长，将所述待测时序逻辑元件的建立时间从第一预设值递减至第二预设值，并记录所述建立时间每次递减后所述待测时序逻辑元件输出的采样值；所述建立时间为所述时钟信号的目标沿与所述数据信号中目标采样值的目标沿之间的时间差，所述第一预设值由所述待测时序逻辑元件稳定输出所述目标采样值时的建立时间确定，所述第二预设值由所述待测时序逻辑元件稳定输出所述目标采样值的反向值时的建立时间确定。
评估模块803，用于根据所述建立时间每次递减后所述待测时序逻辑元件输出的采样值，确定所述待测时序逻辑元件的评估参数，并根据所述评估参数，对所述待测时序逻辑元件的性能进行评估。
在一种可行的实施方式中，所述评估参数包括输出延时平均值，评估模块803用于：
根据所述建立时间每次递减后所述待测时序逻辑元件输出的采样值，确定所述待测时序逻辑元件输出的采样值从所述目标采样值反转为所述目标采样值的反向值时，所述待测时序逻辑元件的第一建立时间值；
计算所述待测时序逻辑元件的建立时间从所述第一预设值递减至所述第一建立时间值的过程中，每次递减完成时所述时钟信号的目标沿与所述待测时序逻辑元件输出所述目标采样值之间的延迟时长的第一均值；
将所述第一均值确定为所述输出延时平均值。
在一种可行的实施方式中，所述评估参数还包括目标建立时间；评估模块803还用于：
选取最小的若干个所述延迟时长；
计算选取的若干个所述延迟时长的均值与所述待测时序逻辑元件的固定延时偏移量的和；
将所述均值与所述固定延时偏移量的和对应的建立时间确定为所述目标建立时间。
在一种可行的实施方式中，所述评估参数还包括亚稳态时间；评估模块803还用于：
绘制所述延迟时长随所述建立时间的递减次数变化的曲线，并确定所述曲线的拐点与峰值；
获取所述峰值与所述拐点对应的所述建立时间的差值，且将所述差值作为所述亚稳态时间。
在一种可行的实施方式中，所述评估参数还包括目标保持时间；调节模块802还用于：
根据所述预设递减步长，将所述待测时序逻辑元件的保持时间从第三预设值递减至第四预设值，并记录所述保持时间每次递减后所述待测时序逻辑元件输出的采样值；所述保持时间为所述时钟信号的目标沿之后，所述数据信号保持稳定的时间，所述第三预设值由所述待测时序逻辑元件稳定输出所述目标采样值时的保持时间确定，所述第四预设值由所述待测时序逻辑元件稳定输出所述目标采样值的反向值时的保持时间确定；
评估模块803还用于：
根据所述保持时间每次递减后所述待测时序逻辑元件输出的采样值，确定所述待测时序逻辑元件输出的采样值从所述目标采样值反转为所述目标采样值的反向值时，所述待测时序逻辑元件的第一保持时间值；
将所述第一保持时间值确定为所述目标保持时间。
在一种可行的实施方式中，所述数据信号包括相位相反的第一数据信号与第二数据信号，所述时钟信号包括相位相反的第一时钟信号和第二时钟信号，所述待测时序逻辑元件包括第一待测时序逻辑元件与第二待测时序逻辑元件；
输入模块801用于：
将所述第一时钟信号与所述第一数据信号输入所述第一待测时序逻辑元件，以利用所述第一时钟信号对所述第一数据信号进行采样；将所述第二时钟信号与所述第二数据信号输入所述第二待测时序逻辑元件，以利用所述第二时钟信号对所述第二数据信号进行采样。
在一种可行的实施方式中，所述评估参数还包括以下评估参数中的至少一种：
最大输出延时，为所述第一待测时序逻辑元件对应的所述输出延时平均值与所述第二待测时序逻辑元件对应的所述输出延时平均值的最大值；
最大建立时间，为所述第一待测时序逻辑元件对应的所述目标建立时间与所述第二待测时序逻辑元件对应的所述目标建立时间的最大值；
最大保持时间，为所述第一待测时序逻辑元件对应的所述目标保持时间与所述第二待测时序逻辑元件对应的所述目标保持时间的最大值；
不确定时间区间，所述不确定时间区间为所述最大建立时间与所述最大保持时间的和；
最大亚稳态时间，为所述第一待测时序逻辑元件对应的所述亚稳态时间与所述第二待测时序逻辑元件对应的所述亚稳态时间的最大值；
建立时间偏差，为所述第一待测时序逻辑元件对应的所述目标建立时间与所述第 二待测时序逻辑元件对应的所述目标建立时间之差的绝对值；
保持时间偏差，为所述第一待测时序逻辑元件对应的所述目标保持时间与所述第二待测时序逻辑元件对应的所述目标保持时间之差的绝对值。
需要说明的是，本公开实施例中输入模块801、调节模块802及评估模块803具体执行的内容可以参阅图1至图7所示实施例中相关内容，此处不做赘述。
进一步的，基于上述实施例中所描述的内容，本公开实施例中还提供了一种电子设备，该电子设备包括至少一个处理器和存储器；其中，存储器存储计算机执行指令；上述至少一个处理器执行存储器存储的计算机执行指令，以实现如上述实施例中描述的时序逻辑元件性能评估方法中的各个步骤，本实施例此处不再赘述。
为了更好的理解本公开实施例，参照图9，图9为本公开实施例提供的一种电子设备的硬件结构示意图。
如图9所示，本实施例的电子设备90包括：处理器901以及存储器902；其中：
存储器902，用于存储计算机执行指令；
处理器901，用于执行存储器存储的计算机执行指令，以实现上述实施例中描述的时序逻辑元件性能评估方法中的各个步骤，具体可以参见前述方法实施例中的相关描述。
可选地，存储器902既可以是独立的，也可以跟处理器901集成在一起。
当存储器902独立设置时，该设备还包括总线903，用于连接所述存储器902和处理器901。
在本公开所提供的几个实施例中，应该理解到，所揭露的设备和方法，可以通过其它的方式实现。例如，以上所描述的设备实施例仅仅是示意性的，例如，所述模块的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个模块可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或模块的间接耦合或通信连接，可以是电性，机械或其它的形式。
本领域普通技术人员可以理解：实现上述各方法实施例的全部或部分步骤可以通过程序指令相关的硬件来完成。前述的程序可以存储于一计算机可读取存储介质中。该程序在执行时，执行包括上述各方法实施例的步骤；而前述的存储介质包括：ROM、RAM、磁碟或者光盘等各种可以存储程序代码的介质。
最后应说明的是：以上各实施例仅用以说明本公开的技术方案，而非对其限制；尽管参照前述各实施例对本公开进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本公开各实施例技术方案的范围。

Claims (15)

  1. 一种时序逻辑元件性能评估方法，所述方法包括：
    将预设的时钟信号与数据信号输入待测时序逻辑元件，所述待测时序逻辑元件用于根据所述时钟信号对所述数据信号进行采样；
    根据预设递减步长，将所述待测时序逻辑元件的建立时间从第一预设值递减至第二预设值，并记录所述建立时间每次递减后所述待测时序逻辑元件输出的采样值；所述建立时间为所述时钟信号的目标沿与所述数据信号中目标采样值的目标沿之间的时间差，所述第一预设值由所述待测时序逻辑元件稳定输出所述目标采样值时的建立时间确定，所述第二预设值由所述待测时序逻辑元件稳定输出所述目标采样值的反向值时的建立时间确定；
    根据所述建立时间每次递减后所述待测时序逻辑元件输出的采样值，确定所述待测时序逻辑元件的评估参数，并根据所述评估参数，对所述待测时序逻辑元件的性能进行评估。
  2. 根据权利要求1所述的方法，其中，所述评估参数包括输出延时平均值，所述根据所述建立时间每次递减后所述待测时序逻辑元件输出的采样值，确定所述待测时序逻辑元件的评估参数，包括：
    根据所述建立时间每次递减后所述待测时序逻辑元件输出的采样值，确定所述待测时序逻辑元件输出的采样值从所述目标采样值反转为所述目标采样值的反向值时，所述待测时序逻辑元件的第一建立时间值；
    计算所述待测时序逻辑元件的建立时间从所述第一预设值递减至所述第一建立时间值的过程中，每次递减完成时所述时钟信号的目标沿与所述待测时序逻辑元件输出所述目标采样值之间的延迟时长的第一均值；
    将所述第一均值确定为所述输出延时平均值。
  3. 根据权利要求2所述的方法，其中，所述评估参数还包括目标建立时间；所述根据所述建立时间每次递减后所述待测时序逻辑元件输出的采样值，确定所述待测时序逻辑元件的评估参数，包括：
    选取最小的若干个所述延迟时长；
    计算选取的若干个所述延迟时长的均值与所述待测时序逻辑元件的固定延时偏移量的和；
    将所述均值与所述固定延时偏移量的和对应的建立时间确定为所述目标建立时间。
  4. 根据权利要求3所述的方法，其中，所述评估参数还包括亚稳态时间；所述根据所述建立时间每次递减后所述待测时序逻辑元件输出的采样值，确定所述待测时序逻辑元件的评估参数，包括：
    绘制所述延迟时长随所述建立时间的递减次数变化的曲线，并确定所述曲线的拐 点与峰值；
    获取所述峰值与所述拐点对应的所述建立时间的差值，且将所述差值作为所述亚稳态时间。
  5. 根据权利要求4所述的方法，其中，所述评估参数还包括目标保持时间；所述方法还包括：
    根据所述预设递减步长，将所述待测时序逻辑元件的保持时间从第三预设值递减至第四预设值，并记录所述保持时间每次递减后所述待测时序逻辑元件输出的采样值；所述保持时间为所述时钟信号的目标沿之后，所述数据信号保持稳定的时间，所述第三预设值由所述待测时序逻辑元件稳定输出所述目标采样值时的保持时间确定，所述第四预设值由所述待测时序逻辑元件稳定输出所述目标采样值的反向值时的保持时间确定；
    根据所述保持时间每次递减后所述待测时序逻辑元件输出的采样值，确定所述待测时序逻辑元件输出的采样值从所述目标采样值反转为所述目标采样值的反向值时，所述待测时序逻辑元件的第一保持时间值；
    将所述第一保持时间值确定为所述目标保持时间。
  6. 根据权利要求5所述的方法，其中，所述数据信号包括相位相反的第一数据信号与第二数据信号，所述时钟信号包括相位相反的第一时钟信号和第二时钟信号，所述待测时序逻辑元件包括第一待测时序逻辑元件与第二待测时序逻辑元件；
    所述将预设的时钟信号与数据信号输入待测时序逻辑元件，包括：
    将所述第一时钟信号与所述第一数据信号输入所述第一待测时序逻辑元件，以利用所述第一时钟信号对所述第一数据信号进行采样；将所述第二时钟信号与所述第二数据信号输入所述第二待测时序逻辑元件，以利用所述第二时钟信号对所述第二数据信号进行采样。
  7. 根据权利要求6所述的方法，其中，所述评估参数还包括以下评估参数中的至少一种：
    最大输出延时，为所述第一待测时序逻辑元件对应的所述输出延时平均值与所述第二待测时序逻辑元件对应的所述输出延时平均值的最大值；
    最大建立时间，为所述第一待测时序逻辑元件对应的所述目标建立时间与所述第二待测时序逻辑元件对应的所述目标建立时间的最大值；
    最大保持时间，为所述第一待测时序逻辑元件对应的所述目标保持时间与所述第二待测时序逻辑元件对应的所述目标保持时间的最大值；
    不确定时间区间，所述不确定时间区间为所述最大建立时间与所述最大保持时间的和；
    最大亚稳态时间，为所述第一待测时序逻辑元件对应的所述亚稳态时间与所述第二待测时序逻辑元件对应的所述亚稳态时间的最大值；
    建立时间偏差，为所述第一待测时序逻辑元件对应的所述目标建立时间与所述第二待测时序逻辑元件对应的所述目标建立时间之差的绝对值；
    保持时间偏差，为所述第一待测时序逻辑元件对应的所述目标保持时间与所述第二待测时序逻辑元件对应的所述目标保持时间之差的绝对值。
  8. 一种时序逻辑元件性能评估装置，所述装置包括：
    输入模块，用于将预设的时钟信号与数据信号输入待测时序逻辑元件，所述待测时序逻辑元件用于根据所述时钟信号对所述数据信号进行采样；
    调节模块，用于根据预设递减步长，将所述待测时序逻辑元件的建立时间从第一预设值递减至第二预设值，并记录所述建立时间每次递减后所述待测时序逻辑元件输出的采样值；所述建立时间为所述时钟信号的目标沿与所述数据信号中目标采样值的目标沿之间的时间差，所述第一预设值由所述待测时序逻辑元件稳定输出所述目标采样值时的建立时间确定，所述第二预设值由所述待测时序逻辑元件稳定输出所述目标采样值的反向值时的建立时间确定；
    评估模块，用于根据所述建立时间每次递减后所述待测时序逻辑元件输出的采样值，确定所述待测时序逻辑元件的评估参数，并根据所述评估参数，对所述待测时序逻辑元件的性能进行评估。
  9. 根据权利要求8所述的装置，其中，所述评估参数包括输出延时平均值，所述评估模块用于：
    根据所述建立时间每次递减后所述待测时序逻辑元件输出的采样值，确定所述待测时序逻辑元件输出的采样值从所述目标采样值反转为所述目标采样值的反向值时，所述待测时序逻辑元件的第一建立时间值；
    计算所述待测时序逻辑元件的建立时间从所述第一预设值递减至所述第一建立时间值的过程中，每次递减完成时所述时钟信号的目标沿与所述待测时序逻辑元件输出所述目标采样值之间的延迟时长的第一均值；
    将所述第一均值确定为所述输出延时平均值。
  10. 根据权利要求9所述的装置，其中，所述评估参数还包括目标建立时间；所述评估模块还用于：
    选取最小的若干个所述延迟时长；
    计算选取的若干个所述延迟时长的均值与所述待测时序逻辑元件的固定延时偏移量的和；
    将所述均值与所述固定延时偏移量的和对应的建立时间确定为所述目标建立时间。
  11. 根据权利要求10所述的装置，其中，所述评估参数还包括亚稳态时间；所述评估模块还用于：
    绘制所述延迟时长随所述建立时间的递减次数变化的曲线，并确定所述曲线的拐点与峰值；
    获取所述峰值与所述拐点对应的所述建立时间的差值，且将所述差值作为所述亚稳态时间。
  12. 根据权利要求11所述的装置，其中，所述评估参数还包括目标保持时间；所述调节模块还用于：
    根据所述预设递减步长，将所述待测时序逻辑元件的保持时间从第三预设值递减至第四预设值，并记录所述保持时间每次递减后所述待测时序逻辑元件输出的采样值；所述保持时间为所述时钟信号的目标沿之后，所述数据信号保持稳定的时间，所述第三预设值由所述待测时序逻辑元件稳定输出所述目标采样值时的保持时间确定，所述第四预设值由所述待测时序逻辑元件稳定输出所述目标采样值的反向值时的保持时间确定；
    所述评估模块还用于：
    根据所述保持时间每次递减后所述待测时序逻辑元件输出的采样值，确定所述待测时序逻辑元件输出的采样值从所述目标采样值反转为所述目标采样值的反向值时，所述待测时序逻辑元件的第一保持时间值；
    将所述第一保持时间值确定为所述目标保持时间。
  13. 根据权利要求12所述的装置，其中，所述数据信号包括相位相反的第一数据信号与第二数据信号，所述时钟信号包括相位相反的第一时钟信号和第二时钟信号，所述待测时序逻辑元件包括第一待测时序逻辑元件与第二待测时序逻辑元件；
    所述输入模块用于：
    将所述第一时钟信号与所述第一数据信号输入所述第一待测时序逻辑元件，以利用所述第一时钟信号对所述第一数据信号进行采样；将所述第二时钟信号与所述第二数据信号输入所述第二待测时序逻辑元件，以利用所述第二时钟信号对所述第二数据信号进行采样。
  14. 根据权利要求13所述的装置，其中，所述评估参数还包括以下评估参数中的至少一种：
    最大输出延时，为所述第一待测时序逻辑元件对应的所述输出延时平均值与所述第二待测时序逻辑元件对应的所述输出延时平均值的最大值；
    最大建立时间，为所述第一待测时序逻辑元件对应的所述目标建立时间与所述第二待测时序逻辑元件对应的所述目标建立时间的最大值；
    最大保持时间，为所述第一待测时序逻辑元件对应的所述目标保持时间与所述第二待测时序逻辑元件对应的所述目标保持时间的最大值；
    不确定时间区间，所述不确定时间区间为所述最大建立时间与所述最大保持时间的和；
    最大亚稳态时间，为所述第一待测时序逻辑元件对应的所述亚稳态时间与所述第二待测时序逻辑元件对应的所述亚稳态时间的最大值；
    建立时间偏差，为所述第一待测时序逻辑元件对应的所述目标建立时间与所述第二待测时序逻辑元件对应的所述目标建立时间之差的绝对值；
    保持时间偏差，为所述第一待测时序逻辑元件对应的所述目标保持时间与所述第二待测时序逻辑元件对应的所述目标保持时间之差的绝对值。
  15. 一种电子设备，包括：至少一个处理器和存储器；
    所述存储器存储计算机执行指令；
    所述至少一个处理器执行所述存储器存储的计算机执行指令，使得所述至少一个处理器执行如权利要求1至7任一项所述的时序逻辑元件性能评估方法。
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US4924468A (en) * 1987-11-30 1990-05-08 Kontron Holding Ag Logic analyzer
CN105991111A (zh) * 2015-03-02 2016-10-05 华为技术有限公司 一种时序预测电路及方法
CN111243635A (zh) * 2018-11-28 2020-06-05 长鑫存储技术有限公司 写数据采样信号时序监测方法、监测电路和存储器
CN114397561A (zh) * 2022-03-24 2022-04-26 龙芯中科技术股份有限公司 时序错误检测电路、方法以及电子设备

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4924468A (en) * 1987-11-30 1990-05-08 Kontron Holding Ag Logic analyzer
CN105991111A (zh) * 2015-03-02 2016-10-05 华为技术有限公司 一种时序预测电路及方法
CN111243635A (zh) * 2018-11-28 2020-06-05 长鑫存储技术有限公司 写数据采样信号时序监测方法、监测电路和存储器
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