WO2023225550A2

WO2023225550A2 - Fabrication of multilayer semiconductor devices with high aspect ratio microneedles

Info

Publication number: WO2023225550A2
Application number: PCT/US2023/067112
Authority: WO
Inventors: Mark A. Webb; Marc S. CHOOLJIAN; David A. Steele; Lauren M. Otto; Charles V. NGUYEN
Original assignee: Mekonos Inc.
Priority date: 2022-05-18
Filing date: 2023-05-17
Publication date: 2023-11-23
Also published as: WO2023225550A3; WO2023225540A3; WO2023225540A2

Abstract

Aspects of the present disclosure provide systems, methods, and computer-readable storage devices that support fabrication of multilayer semiconductor devices containing microneedles having high aspect ratios. A method of fabricating such a device includes bonding a first substrate structure to a second substrate structure via a substrate bond. The first substrate structure includes a first substrate, an oxide layer on a first surface, a semiconductor material layer on the oxide layer, and a first hard mask layer on the semiconductor material layer. The second substrate structure includes a second substrate and a second hard mask layer on the second substrate. The method includes grinding a second surface of the first substrate that is opposite to the first surface. The method includes performing a combination of lithography and etching operations on the grinded second surface to form a trench within the first substrate structure and a substrate pillar within the trench.

Description

FABRICATION OF MULTILAYER SEMICONDUCTOR DEVICES WITH HIGH ASPECT RATIO MICRONEEDLES

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] The present application claims the benefit of U.S. Provisional Application No. 63/364,948, filed on May 18, 2022 and titled “FABRICATION METHODS OF PRECISE AUTOMATED TOOLS”, the contents of which are incorporated herein by reference in their entirety.

TECHNICAL FIELD

[0002] The present disclosure relates generally to systems, processes, and methods for manufacturing a multilayer semiconductor device that contains needles or other tools for medical or biomedical applications. Particular implementations leverage substrate bonding techniques and other fabrication processes to fabricate or manufacture the multilayer semiconductor device from multiple semiconductor substrates.

BACKGROUND

[0003] As technology advances, research and commercial interest in developing microscopic devices continues to grow. For example, in recent years materials and technologies traditionally associated with fabricating semiconductor devices for computers or other electronic devices have found useful applications in other fields, such as in biology and medicine. One such application is the use of microneedles and nanoneedles fabricated using semiconductor materials. Microneedles have attracted the attention of researchers because of their potential to provide a pain-free or reduced-pain alternative to syringes for injecting fluid into a patient or drawing blood from a patient for testing (e.g., blood glucose and/or insulin levels). Additionally, microneedles offer the potential for improved logistics (e.g., reducing the free volume of medication in any one place to reduce or eliminate the need for refrigerated transport) and increased patient selfadministration (e.g., reducing the need and resulting costs for a healthcare provider to be present to inject fluid or draw blood). Microneedles may be also useful for medical procedures requiring a high degree of precision, such as treatments precisely targeting cancer cells while avoiding non- cancerous cells. [0004] High aspect ratio nanoneedle/microneedle architectures and geometries are commercially difficult to manufacture at scale. For example, attempts at fabricating microneedles with high aspect ratios often result in microneedles that fail to achieve the desired aspect ratios or that are brittle and prone to breaking, which limits or prevents their usefulness in medical or biological applications. Even more difficult is achieving specific feature geometries for high efficacy cell and gene engineering workflows utilizing traditional semiconductor process tooling. High aspect ratio structures that are tightly packed are known to not survive processing in liquids. It is also difficult to manufacture high aspect ratio microneedles for multi-use devices, as opposed to a single-use devices that fail after use due to stress. Manufacturing microneedle structures at scale without breaking the structures or experiencing low yield is a key barrier to commercial viability.

[0005] Another related difficulty in manufacturing microneedles/nanoneedles in multilayer semiconductor devices (e.g., monolith devices) is the difficulty in fabricating such small, high aspect ratio tools within the other semiconductor layers and structures. In many cases it may be desirable to form microneedles onto microelectromechanical systems (MEMS) actuators so that the microneedles can be extended or retracted using electrostatic forces. Such a structure may be covered by a membrane which enables electrostatic activation of the MEMS actuator, and the membrane may include a pore through which the microneedle extends during activation. However, difficulties with forming such a membrane may result in damage to the microneedles, which decreases yield of fabricated microneedles and presents an economic barrier to an entity that seeks to fabricate microneedles in such MEMS systems. As an example, a membrane layer might be formed from material that is deposited onto the same substrate that includes as the actuator, but depositing the membrane material over a microneedle structure may break the microneedle structure or damage specialized tip geometries. One method to deal with this problem is to form microneedles through an already-formed pore in the membrane layer, however the narrow diameter of the pore makes formation of the microneedle difficult or impossible, and may result in damage to the microneedle or the tip geometry during formation in such a tight space. Increasing the size of the pore may not be an option, as increasing the pore’s diameter sacrifices surface area of the membrane needed for electrostatic actuation, thus requiring higher voltages to get the same actuation results. These higher voltages may not be safe or possible in the desired medical and biomedical applications. Another option is to form a membrane layer on a separate substrate and combine this substrate with the substrate on which the microneedle(s) are formed. However, because of the small size and aspect ratio of the microneedles, alignment of a preformed pore is difficult because even very small misalignments can lead to an unacceptably high likelihood that the microneedle will miss the pore during actuation and break or be damaged by colliding with the membrane layer. Forming the pore after the substrates are bonded also presents challenges, as the substrate holding the membrane layer can obscure the microneedle or any other means of determining a precise location of the microneedle, resulting in the same high likelihood of collisions. Additionally, forming the pore may include etching or other operations that may damage the microneedle.

SUMMARY

[0006] Aspects of the present disclosure provide systems, devices, methods, and computer-readable storage devices and media that support scalable fabrication of multilayer semiconductor devices that include microneedles or tools having high aspect ratios. The aspects described herein enable the fabrication or manufacture of such multilayer semiconductor devices using fabrication techniques that can be performed using semiconductor fabrication tools without requiring reprogramming or fundamental redesign of the tools. This is directly related to faster manufacturing time and scalability for multilayer semiconductor devices containing microneedle arrays, such as microelectromechanical system (MEMS) devices or nanoelectromechanical system (NEMS) devices.

[0007] In some aspects described herein, microneedle structures may be formed in a multilayer semiconductor substrate structure, using lithographic and etching processes. In some aspects, a plurality of multilayer substrate structures may be bonded together using bond processes, non-limiting examples of which include oxide bond processes (e.g., substrate bonds or substrate- to-substrate bonds), metallic bond processes, and thermocompression bond processes. In aspects described herein, the lithographic, etching, bonding, and other processes and operations are designed to maintain a very small total thickness variation (TTV) across critical dimensions of the substrates. Maintaining a small TTV across critical dimensions of the substrate prevents needle damage and improves yield of the fabrication process. Small TTV also enables the fabrication of microneedles on the surface of MEMS actuators. Techniques for precisely aligning pores or through-holes in a membrane for the microneedles are also described herein. [0008] In some aspects, the microneedle structures formed may include a pillar and a custom-shaped tip. A pillar may be formed from the substrate by etching surrounding material away from the pillar, such as through the use of reactive ion etching (RIE). Additionally, in some aspects a pillar may be tapered further, by performing chemical or oxidative thinning, to achieve a desired aspect ratio. Custom-shaped tips can be formed for the microneedle structures prior to and/or during the etching of the pillar structure, and may include as non-limiting examples, such shapes as cones, cone-shaped cavities, cavities having a substantially flat bottom, polygonal cavities, polygonal protrusions, pores, and/or pads. These custom-shaped tips are formed by applying custom patterns, such as annular cutout patterns and the like, to photoresist material during the lithographic processes and by designing the patterns and etching processes parameters such that etching the substrate using a custom pattern-shaped material as a mask results in formation of detailed shapes such as cones, inverted cones, polygonal structures, and the like, that dimensions and characteristics of the custom-shaped tips can be controlled by design of dimensions and characteristics of the custom patterns. In some implementations, a metal material may be deposited on the custom-shaped tip, such as on a protruding substrate structure or within an etched cavity.

[0009] References made in this disclosure to microneedles or microneedle structures are intended to refer also to nanoneedles and nanoneedle structures and vice versa. For the sake of clarity and conciseness, only one of the terms may be listed, but unless explicitly specified differently, a reference to one of these terms is intended to include the others. Likewise, references to MEMS devices are intended to include NEMS devices unless explicitly specified otherwise.

[0010] In a particular aspect, a method for fabricating multilayer semiconductor devices with microneedles having high aspect ratios includes bonding a first substrate structure to a second substrate structure via a substrate bond between a first hard mask layer of the first substrate structure and a second hard mask layer of the second substrate structure. The first substrate structure includes a first substrate, an oxide layer on a first surface of the first substrate that at least partially surrounds a dielectric structure, a semiconductor material layer on the oxide layer, and the first hard mask layer on the semiconductor material layer. The oxide layer is disposed between the first substrate and the semiconductor material layer. The semiconductor material is layer disposed between the oxide layer and the first hard mask layer. The second substrate structure includes a second substrate and the second hard mask layer on the second substrate. The method also includes grinding a second surface of the first substrate. The second surface is opposite to the first surface. The method further includes performing a combination of lithography operations and etching operations on the grinded second surface. The combination of lithography operations and etching operations form a trench within the first substrate structure and a substrate pillar within the trench. The substrate pillar is formed on the dielectric structure and has a custom-shaped feature at a tip of the substrate pillar.

[0011] In another particular aspect, a non-transitory computer-readable storage device stores instructions that, when executed by one or more processors, cause the one or more processors to perform operations for fabricating multilayer semiconductor devices with microneedles having high aspect ratios. The operations include initiating bonding of a first substrate structure to a second substrate structure via a substrate bond between a first hard mask layer of the first substrate structure and a second hard mask layer of the second substrate structure. The first substrate structure includes a first substrate, an oxide layer on a first surface of the first substrate that at least partially surrounds a dielectric structure, a semiconductor material layer on the oxide layer, and the first hard mask layer on the semiconductor material layer. The oxide layer is disposed between the first substrate and the semiconductor material layer. The semiconductor material layer is disposed between the oxide layer and the first hard mask layer. The second substrate structure includes a second substrate and the second hard mask layer on the second substrate. The operations also include initiating grinding of a second surface of the first substrate. The second surface is opposite to the first surface. The operations further include initiating performance of a combination of lithography operations and etching operations on the grinded second surface. The combination of lithography operations and etching operations form a trench within the first substrate structure and a substrate pillar within the trench. The substrate pillar is formed on the dielectric structure and has a custom-shaped feature at a tip of the substrate pillar.

[0012] In another particular aspect, a multilayer semiconductor device includes a first material layer stack including a first plurality of material layers. The first plurality of material layers includes a first substrate, an oxide layer in contact with a first surface of the first substrate and at least partially surrounding a cavity in the first material layer stack, and a semiconductor material layer in contact with the oxide layer. The cavity includes a substrate pillar disposed on a dielectric structure and has a custom-shaped feature at a tip of the substrate pillar. The oxide layer is disposed between the first substrate and the semiconductor material layer. A first hard mask layer is in contact with the semiconductor material layer. The semiconductor material layer is disposed between the oxide layer and the first hard mask layer. A first metal layer is in contact with a second surface of the first substrate that is opposite to the first surface. The multilayer semiconductor device also includes a second material layer stack including a second plurality of material layers. The second material layer stack is bonded to the first hard mask layer via a substrate bond. The multilayer semiconductor device further includes a third material layer stack including a third plurality of material layers. The third material layer stack is bonded to the first metal layer via a metallic bond.

[0013] The foregoing has outlined rather broadly the features and technical advantages of the present disclosure in order that the detailed description that follows may be better understood. Additional features and advantages will be described hereinafter which form the subject of the claims of the disclosure. It should be appreciated by those skilled in the art that the conception and specific aspects disclosed may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present disclosure. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the scope of the disclosure as set forth in the appended claims. The novel features which are disclosed herein, both as to organization and method of operation, together with further objects and advantages will be better understood from the following description when considered in connection with the accompanying figures. It is to be expressly understood, however, that each of the figures is provided for the purpose of illustration and description only and is not intended as a definition of the limits of the present disclosure.

BRIEF DESCRIPTION OF THE DRAWINGS

[0014] For a more complete understanding of the present disclosure, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:

[0015] FIG. 1 illustrates a first stage of an example of a process for fabricating a multilayer semiconductor device containing microneedles according to one or more aspects;

[0016] FIG. 2 illustrates a second stage of an example of the process shown in FIG. 1;

[0017] FIG. 3 illustrates a third stage of an example of the process shown in FIG. 1 ; [0018] FIG. 4 illustrates a fourth stage of an example of the process shown in FIG. 1;

[0019] FIG. 5 illustrates a fifth stage of an example of the process shown in FIG. 1;

[0020] FIG. 6 illustrates a sixth stage of an example of the process shown in FIG. 1;

[0021] FIG. 7 illustrates a seventh stage of an example of the process shown in FIG. 1;

[0022] FIG. 8 illustrates an eighth stage of an example of the process shown in FIG. 1;

[0023] FIG. 9 illustrates a ninth stage of an example of the process shown in FIG. 1;

[0024] FIG. 10 illustrates a tenth stage of an example of the process shown in FIG. 1;

[0025] FIG. 11 illustrates an eleventh stage of an example of the process shown in FIG. 1;

[0026] FIG. 12 illustrates a twelfth stage of an example of the process shown in FIG. 1;

[0027] FIG. 13 is a flow diagram illustrating an example of a method for fabricating a multilayer semiconductor device containing microneedles according to one or more aspects; and

[0028] FIG. 14 is a block diagram of an example of a computing device that is operable to support fabrication of a multilayer semiconductor device containing microneedles according to one or more aspects.

[0029] It should be understood that the drawings are not necessarily to scale and that the disclosed aspects are sometimes illustrated diagrammatically and in partial views. In certain instances, details which are not necessary for an understanding of the disclosed methods and apparatuses or which render other details difficult to perceive may have been omitted. It should be understood, of course, that this disclosure is not limited to the particular aspects illustrated herein.

DETAILED DESCRIPTION

[0030] Referring to FIGS. 1-12, stages of an example of a process for fabricating a multilayer semiconductor device containing microneedles according to one or more aspects of the present disclosure are shown. The process described with reference to FIGS. 1-12 may be performed to fabricate a multilayer semiconductor device, such as a microelectromechanical system (MEMS) device or a nanoelectromechanical system (NEMS) device that contains one or more tools, such as microneedles, nanoneedles, or other tools, for use in medical or biomedical procedures. In some implementations, the multilayer semiconductor device is formed by bonding together three semiconductor substrates: a first substrate (e.g., a device layer), a second substrate (e.g., a handle layer), and a third substrate (e.g., a membrane layer). The disclosed multilayer semiconductor devices have microneedles or tools that have high aspect ratios as compared to conventional microneedles or other tools. As used herein, an aspect ratio of a microneedle refers to a proportional relationship between a longitudinal dimension of the microneedle and a lateral dimension of the microneedle (or a portion thereof). As further described herein, the disclosed methods and processes for fabrication of such multilayer semiconductor devices are scalable and may be implemented in foundries or by other semiconductor manufacturers. Although described in the context of medical and biological applications, the multilayer semiconductor devices that are described herein are not so limited, and may be designed and used in other applications and contexts. As non-limiting examples, the manufacturing and/or fabrication processes disclosed herein may be used to fabricate multilayer semiconductor devices that include tools with high aspect ratios for brain implants, stealth metasurfaces, or other applications and use cases.

[0031] FIG. 1 illustrates a first stage of the multilayer semiconductor device fabrication process. The process may be initiated by providing a first substrate 100 (e.g., a substrate that is to become a device layer of the multilayer semiconductor device) and adding one or more additional layers to the first substrate 100 to form a first substrate structure 101 that is to be bonded with two additional substrate structures, as further described herein. The first substrate 100 (e.g., a wafer) may include undoped silicon (Si), doped Si (e.g., Si with an impurity of boron, phosphorus, arsenic, antimony, or the like), silicon dioxide (SiCh), silicon carbide (SiC), or any other substrate material suitable for the formation of microneedles or medical tools. In some particular implementations, the first substrate 100 is a P-type substrate having a thickness in a range between 100-200 millimeters (mm), and in some implementations approximately 150 mm. Additionally or alternatively, the first substrate 100 may be a silicon-on-insulator (SOI) wafer for which a majority of the wafer is Si, with one surface having an insulator layer, such as silicon oxide (SiO), disposed between the majority of the wafer and a small Si layer on one surface of the SOI wafer. A needle location 110 is shown using dashed lines in FIG. 1. The needle location 110 represents a location at which a microneedle, or other tool, having a high aspect ratio is to be formed during later stage(s) of the multilayer semiconductor device fabrication process.

[0032] The first substrate 100 may also include, or have formed thereon, an oxide layer 120 and a semiconductor material layer 130. The oxide layer 120 is disposed between the first substrate 100 and the semiconductor material layer 130. Stated another way, in the orientation shown in FIG. 1, the oxide layer 120 is disposed above (e.g., on) the first substrate 100, and the semiconductor material layer 130 is disposed above (e.g., on) the oxide layer 120. The oxide layer 120 may include SiO, SiCh, or any other oxide-containing material that is suitable for providing an etch mask during a silicon etch process. Although described as an “oxide” layer, in some other implementations, the oxide layer 120 may instead include (or be replaced with) a layer of another type of material suitable for providing an etch mask, such as SiC or silicon nitride (SiN), as nonlimiting examples. In some implementations, the oxide layer 120 may have a thickness in a range between 100 and 200 nanometers (nm). The semiconductor material layer 130 may include undoped Si, doped Si (e.g., Si with an impurity of boron, phosphorus, arsenic, antimony, or the like), SiCb, SiC, or any other semiconductor material suitable for the formation of microneedles or medical tools, similar to the first substrate 100. In implementations in which the first substrate 100 is an SOI wafer, the oxide layer 120 may be a buried oxide (BOx) layer and the semiconductor material layer 130 may include the same type of silicon a the first substrate 100. Although FIG. 1 shows the oxide layer 120 and the semiconductor material layer 130, these layers are optional and are not included in some implementations (such that the subsequent processes are performed directly on the first substrate 100).

[0033] At particular locations in the first substrate 100, one or more alignment marks may be etched or otherwise formed. The alignment marks may be disposed proximate to one or more side edges of the first substrate 100. In the example shown in FIG. 1, the first substrate 100 includes one or more first alignment marks (referred to herein as “first alignment marks 132”) and one or more second alignment marks (referred to herein as “second alignment marks 134”). The first alignment marks 132 and/or the second alignment marks 134 may be formed by etching the semiconductor material layer 130, the oxide layer 120, the first substrate 100, or through other techniques that form markings that can be perceived and used to determine location and alignment with respect to the first substrate 100 by one or more semiconductor fabrication tools. The first alignment marks 132 and the second alignment marks 134 may also be referred to as placement marks, bonding alignment marks, location marks, or the like. In some implementations, the first alignment marks 132 and the second alignment marks 134 are a same type of alignment mark, such as alignment marks used by the same type of tool or to indicate the same type of alignment information. In some other implementations, the first alignment marks 132 and the second alignment marks 134 are different types of alignment marks, such as alignment marks used by different types of tools or to indicate different types of alignment information. The particular alignment marks illustrated in FIG. 1 are illustrative and encompass any type of alignment markings rather than just the specific markings shown in FIG. 1.

[0034] During the first stage of the multilayer semiconductor device fabrication process, an additional oxide layer 140 may be formed on the semiconductor material layer 130 (or on the first substrate 100 in implementations in which the semiconductor material layer 130 and the oxide layer 120 are not included). For example, an oxide material may be deposited on the semiconductor material layer 130 (e.g., a first surface of the first substrate structure 101) to form the additional oxide layer 140. The additional oxide layer 140 (e.g., the additional oxide material) may be deposited using any suitable deposition technique, such as a chemical vapor deposition (CVD) technique, an electro-chemical vapor deposition (ECVD) technique, a plasma-enhanced chemical vapor deposition (PECVD) technique, a sputtering technique, an evaporation technique, an atomic layer deposition (ALD) technique, a spin coating technique, a pulsed laser deposition (PLD) technique, a molecular-beam epitaxial technique, an electroplating technique, or the like. Although described as being deposited, the deposition may include or be replaced by an oxide growth process, such as a wet oxide growth process or a dry oxide growth process, that grows the additional oxide material from the semiconductor material layer 130 (or the first substrate 100 in implementations in which the semiconductor material layer 130 is omitted) to form the additional oxide layer 140. The additional oxide layer 140 may include SiO, SiCh, or any other oxidecontaining material that is suitable for providing an etch mask during a silicon etch process. Although described as an “oxide” layer, in some other implementations, the additional oxide layer 140 may instead include (or be replaced with) a layer of another type of material suitable for providing an etch mask, such as SiC or SiN, as non-limiting examples.

[0035] FIG. 2 illustrates a second stage of the multilayer semiconductor device fabrication process. During the second stage, one or more etching operations (e.g., an etching process) may be performed to form a trench 150 in a portion of the additional oxide layer 140, the semiconductor material layer 130, the oxide layer 120, the first substrate 100, or a combination thereof. The etching process may include or correspond to a plasma etch, a wet etch, a chemical etch, a dry etch, or any other type of etching process that is capable of etching into a semiconductor substrate and/or oxide layers. The etching process may be performed to a target depth such that a bottom surface 152 of the trench 150 is at a desired location of a base of a microneedle or other tool to be performed in subsequent stages of the multilayer semiconductor device fabrication process. In some implementations, a photoresist material may be deposited over the area in which the trench 150 is to be formed, and one or more lithography operations may be performed to pattern the photoresist material into a mask to be used during the etching process. The photoresist material may be deposited on the additional oxide layer 140 using any suitable deposition technique, such as a CVD technique, an ECVD technique, a PECVD technique, a sputtering technique, an evaporation technique, an ALD technique, a spin coating technique, a PLD technique, a molecular- beam epitaxial technique, an electroplating technique, or the like.

[0036] FIG. 3 illustrates a third stage of the multilayer semiconductor device fabrication process. During the third stage, a dielectric material may be deposited on the additional oxide layer 140 and the trench 150. The dielectric material may include materials with dielectric properties, such as porcelain, ceramics, glass, mica, plastics, silica (e.g., SiCh), doped carbon, doped fluorine, silsesquioxanes, various metal-oxides, silica-based ceramics, hafnium silicate (HfSiCU), or zirconium silicate (ZrSiCU), as non-limiting examples. The dielectric material may be deposited on the additional oxide layer 140 and the trench 150 using any suitable deposition technique, such as a CVD technique, an ECVD technique, a PECVD technique, a sputtering technique, an evaporation technique, an ALD technique, a spin coating technique, a PLD technique, a molecular-beam epitaxial technique, an electroplating technique, or the like. Depositing the dielectric material may form a dielectric layer 160 on the additional oxide layer 140 and a dielectric structure 162 within a portion of the trench 150. After formation, the dielectric structure 162 may be at least partially surrounded by the oxide layer 120. The third stage may also include deposition, also referred to as back filling, of an additional semiconductor material on the dielectric layer 160 and the dielectric structure 162 (e.g., within the trench 150). The additional semiconductor material may include any of the materials described with reference to the semiconductor material layer 130 and the first substrate 100, and the deposition may include backfilling and/or any deposition technique described with reference to the semiconductor material layer 130 and the first substrate 100. Depositing the additional semiconductor material may form an additional semiconductor material layer 170 (e.g., a backfilled silicon layer) on the dielectric layer 160 and additional semiconductor material 172 (e.g., backfilled silicon) on the dielectric structure 162 within the trench 150.

[0037] FIG. 4 illustrates a fourth stage of the multilayer semiconductor device fabrication process. During the fourth stage, the additional semiconductor material layer 170, at least a portion of the additional semiconductor material 172, and the dielectric layer 160 may be grinded away or removed from the first substrate structure 101, and the semiconductor material layer 130 (which includes a remaining portion of the additional semiconductor material 172) may be planarized. For example, a chemical mechanical planarization (CMP) process, also known or referred to as a chemical mechanical polishing process, may be performed on a surface (e.g., the top surface in the orientation shown in FIG. 4) of the semiconductor material layer 130 to form a substantially smooth surface of the semiconductor material layer 130 that covers the trench 150 and the dielectric structure 162. For example, the substantially smooth surface resulting from the planarization may reduce total thickness variation (TTV) for the first substrate structure 101 to within target margins. In some implementations, one or more etches may be performed to create small openings in the semiconductor material layer 130 that will operate as “springs” for an actuator that includes the microneedles to be formed during subsequent stages. For example, an actuator structure 180 (e.g., a MEMS actuator, a NEMS actuator, or another type of electromechanical actuator) formed from the multilayer semiconductor device fabrication process described herein may include an actuator base 182 (e.g., a portion of the semiconductor material layer 130 which will support the dielectric structure 162 and a microneedle or tool formed thereon), and actuator springs 184 (e.g., openings in the semiconductor material layer 130 that will enable the actuator base to move and propel the microneedle, as further described herein).

[0038] After planarizing the surface of the semiconductor material layer 130, a hard mask material may be deposited on the semiconductor material layer 130 to form a hard mask layer 190 (e.g., a bond hard mask layer or bond oxide layer) on the semiconductor material layer 130. The hard mask material may include any of the materials, such as SiO, SiC, or SiN, described with reference to the oxide layer 120, and the deposition may include any deposition technique described with reference to the semiconductor material layer 130, the additional semiconductor material layer 170, and the first substrate 100. Additionally or alternatively, the hard mask layer 190 may include a metal hard mask material or a metal oxide hard mask material, such as aluminum oxide (AI2O3), tantalum oxide (Ta2O5), or the like. The hard mask material may be deposited to form the hard mask layer 190 having a desired thickness, such as within a range between 125-175 nanometers (nm), and in some implementations approximately 140 nm. Because the hard mask layer 190 is deposited on the substantially smooth surface of the semiconductor material layer 130, the hard mask layer 190 may also have a substantially smooth surface (e.g., a top surface in the orientation illustrated in FIG. 4). In some implementations, additional planarization, grinding, or other operations may be performed to smooth the surface of the hard mask layer 190. In some implementations, after the planarization or grinding, the hard mask layer 190 may have a thickness in a range between 400 and 600 nm, and in a particular implementation, a thickness of approximately 500 nm. After the fourth stage, the first substrate structure 101 shown FIG. 4 is prepared for bonding with another substrate structure. At this point in time, the oxide layer 120 is disposed between the first substrate 100 and the semiconductor material layer 130, and the semiconductor material layer 130 is disposed between the oxide layer 120 and the hard mask layer 190.

[0039] FIG. 5 illustrates a fifth stage of the multilayer semiconductor device fabrication process. During the fifth stage, the first substrate structure 101 may be bonded to a second substrate structure 201 via a substrate bond, as represented by the arrows in FIG. 5. A substrate bond refers to attaching two or more substrates to each other by means of various chemical and physical effects, as compared to using adhesive bonding, soldering, or the like. To illustrate, the second substrate structure 201 may include a second substrate 200 and a second hard mask layer 210 disposed on a surface (e.g., a top surface, in the orientation shown in FIG. 5) of the second substrate 200. The second substrate 200 (e.g., a wafer that is to become a handle layer, or an interposer layer, of the multilayer semiconductor device) may include undoped Si, doped Si (e.g., Si with an impurity of boron, phosphorus, arsenic, antimony, or the like), SiCh, SiC, or any other substrate material suitable for the formation of microneedles or medical tools, or for the formation of a handle or interposer in a MEMS device, a NEMS device, or another type of electromechanical device. In some implementations, the second substrate 200 may have a thickness in a range between 300 and 500 pm, and in a particular implementation, a thickness of approximately 400 pm. The second hard mask layer 210 (e.g., a second bond hard mask layer) may include any of the materials described above with reference to the hard mask layer 190, and the second hard mask layer 210 may be deposited or formed using any of the techniques described above for the hard mask layer 190. In some implementations, the second hard mask layer 210 may have a thickness in a range between 0.5 and 2 gm, and in a particular implementation, a thickness of approximately 1 pm. As shown in FIG. 5, the substrate bond may be between the hard mask layer 190 and the second hard mask layer 210 (e.g., at least a portion of the hard mask layer 190 may be placed into direct contact with the second hard mask layer 210). Bonding the first substrate structure 101 to the second substrate structure 201 may create a bonded monolith substrate 300 (e.g., a monolith substrate formed from the first substrate 100 and the second substrate 200), as shown in FIG. 6.

[0040] In some implementations, the second substrate structure 201 may optionally include a second oxide layer 230 and a second semiconductor material layer 220, such as in implementations in which the second substrate 200 is a SOI wafer. In such implementations, the second oxide layer 230 is disposed between the second substrate 200 and the second semiconductor material layer 220, and the second semiconductor material layer 220 may be disposed between the second oxide layer 230 and the second hard mask layer 210. In some other implementations, the second semiconductor material layer 220 and the second oxide layer 230 are omitted, such that the second hard mask layer 210 is in direct contact with the second substrate 200.

[0041] In some implementations, the second substrate structure 201 may include alignment marks at various locations. The alignment marks may be disposed proximate to one or more side edges of the second substrate 200. In the example shown in FIG. 5, the second substrate 200 includes one or more third alignment marks (referred to herein as “third alignment marks 232”) and one or more fourth alignment marks (referred to herein as “fourth alignment marks 234”). The third alignment marks 232 and/or the fourth alignment marks 234 may be formed by etching the second semiconductor material layer 220, the second oxide layer 230, the second substrate 200, or through other techniques that form markings that can be perceived and used to determine location and alignment with respect to the second substrate 200 by one or more semiconductor fabrication tools. For example, an alignment mark cutout 212 may be etched or otherwise formed in the second hard mask layer 210 to enable visibility of the fourth alignment marks 234. In some implementations, the third alignment marks 232 and the fourth alignment marks 234 are a same type of alignment mark, such as alignment marks used by the same type of tool or to indicate the same type of alignment information. In some other implementations, the third alignment marks 232 and the fourth alignment marks 234 are different types of alignment marks, such as alignment marks used by different types of tools or to indicate different types of alignment information. The particular alignment marks illustrated in FIG. 5 are illustrative and encompass any type of alignment markings rather than just the specific markings shown in FIG. 5. In some implementations, the first alignment marks 132 and the third alignment marks 232 may be the same type of alignment marks and may be used to align the first substrate structure 101 to the second substrate structure 201 during the bonding process. In some such implementations, a distance 236 between two alignment marks (e.g., of the first alignment marks 132) on one substrate structure may be substantially equal to the distance between two corresponding alignment marks (e.g., of the third alignment marks 232) on another substrate structure and/or the distance 236 may represent a tolerance for alignment of the two substrate structures during the bonding process. Additionally or alternatively, the second alignment marks 134 and the fourth alignment marks 234 may be the same type of alignment marks and may be used to align the first substrate structure 101 to the second substrate structure 201 during the bonding process.

[0042] FIG. 6 illustrates a sixth stage of the multilayer semiconductor device fabrication process. During the sixth stage, the bonding between the first substrate structure 101 and the second substrate structure 201 is complete, forming the bonded monolith substrate 300. For example, the hard mask layer 190 may be bonded to the second hard mask layer 210, forming a bonded hard mask layer 320 at a bond interface 322 that extends a width of the bonded monolith substrate 300. After the bonding process is complete, a second surface (e.g., the top surface in the orientation shown in FIG. 6) of the first substrate 100 that is opposite to the first surface (e.g., the bottom surface in the orientation shown in FIG. 6) may be grinded and/or otherwise reduced. For example, a process that includes grinding, lapping, CMP, or a combination thereof, may remove a portion of the first substrate 100 until a remaining portion has a remaining thickness 330. The remaining thickness 330 may be chosen to be substantially equal to the target height of a microneedle or other tool to be formed from the bonded monolith substrate 300, as further described herein. In some implementations, the remaining thickness 330 (e.g., of the first substrate 100) is within a range between 100 nm and 1 mm), such as within a range between 3 pm and 100 pm, and in some particular implementations is 25 pm. Additionally or alternatively, a distance between the grinded second surface (e.g., a top surface in the orientation shown in FIG. 6) of the first substrate 100 and the oxide layer 120 is within a range between 10 and 50 pm.

[0043] Because the first substrate structure 101 is bonded to the second substrate structure 201 using a substrate bond, the bonding may introduce more TTV at the bond interface 322 than other types of bond interfaces, such as thermal crystalline bond interfaces, due to the nature of the substrate bond. However, a significant portion of the bond interface 322 is inside of an area that is etched away in subsequent stage(s) of the multilayer substrate fabrication process, and as such, the increased TTV at the bond interface 322 is not impactful to device performance. To illustrate, the bond interface 322 is within a sacrificial layer for a later stage, and as a result, does not impact any physical device features because any discrepancy or mis-bond in that area is etched out in a later stage of the process. Additionally, to achieve a consistent across-wafer TTV after the grinding, it is desirable for the first substrate 100 and the second substrate 200 to have a very high quality TTV process during formation and for any thin film processing (e.g., oxide layers, hard mask layers, etc.) to be performed without any significant CVD. In this manner, the small TTV in the first substrate 100 and the second substrate 200 can be maintained throughout the bonding process and the grinding of the second surface of the first substrate 100. As such, the process described herein is a scalable convergent process that uses the least number of bonds, and in which the bond interfaces are the least impactful to the end device architecture. As a nonlimiting example, after the grinding described with reference to FIG. 6, a TTV across an eight inch wafer (e.g., the first substrate 100) may be 500 nm or less, even after grinding away 800 pm or more of the first substrate 100.

[0044] In some implementations, additional alignment marks may be formed on the first substrate 100. For example, one or more fifth alignment marks (referred to herein as “fifth alignment marks 332”) may be etched into the grinded second surface of the first substrate 100. The fifth alignment marks 332 may be any type of alignment marks described herein, and may be the same type (or different) than one or more of the first alignment marks 132, the second alignment marks 134, the third alignment marks 232, and the fourth alignment marks 234. Additionally or alternatively, an etched opening 334 may be cut into a portion of the grinded second surface of the first substrate 100 to expose the second alignment marks 134 and/or the fourth alignment marks 234. In some implementations, the second alignment marks 134, the fourth alignment marks 234, and/or the fifth alignment marks 332 may be used to align the first substrate structure 101 during a bonding process with an additional substrate structure, as further described herein.

[0045] After grinding the second surface of the first substrate 100, and optionally forming the fifth alignment marks 332 and/or forming the etched opening 334, a first metal layer 340 (e.g., a first thermocompression bond layer) may be formed on the grinded second surface of the first substrate 100. For example, the first metal layer 340 may be formed by performing a metallization liftoff process using a metal material on portions of the grinded second surface of the first substrate 100. Alternatively, the first metal layer 340 may be deposited via a vapor deposition process, an e-beam process, a sputtering process, an electrodeposition process, or any type of deposition process suitable for depositing metals or metallic materials. In either example, the metal material may include an inorganic metal, an organic metal, or a metal alloy, a mixture of metals and/or metal alloys, or a sinterable ceramic or composite material that can be thermally processed at elevated temperatures up to 1050 degrees Celsius. As illustrative examples, the metal material that forms the first metal layer 340 may include gold, silver, copper, or alloys thereof. The first metal layer 340 may recessed from and expose a region at which a trench is to be formed for the formation of microneedles or other tools. For example, the first metal layer 340 may be recessed from and expose a region of the first substrate 100 above the actuator springs 184 and the needle location 110 in the orientation shown in FIG. 6. Because the first metal layer 340 is recessed from where a cavity will be defined and etched for the microneedles (or other tools), the alignment between the first substrate structure 101 and the second substrate structure 201 during the substrate bond can be less precise than alignment of features in later stages, such that the substrate structures can be aligned at higher resolutions than the submicron resolution. To illustrate, a slight mismatch of an annulus of the surrounding first metal layer 340 and a location of a cavity for microneedles is permissible, due to the recession of the first metal layer 340, as compared to the more precise alignment of the microneedle tip and a through-hole (e.g., pore) formed in a later stage. After the first metal layer 340 is formed, an additional hard mask material may be deposited on the first metal layer 340 and the grinded second surface of the first substrate 100 to form an additional hard mask layer 350. The additional hard mask material may include any of the materials, such as oxides, SiO, SiC, or SiN, described with reference to the hard mask layer 190 or the second hard mask layer 210, and the deposition may include any deposition technique described with reference to the hard mask layer 190 or the second hard mask layer 210.

[0046] FIG. 7 illustrates a seventh stage of the multilayer semiconductor device fabrication process. During the seventh stage, a combination of lithography operations and etching operations may be performed on the grinded second surface of the first substrate 100 to form a needle trench 360 (which, when covered, will also be referred to as a needle cavity 360) within the first substrate 100 and one or more substrate pillars within the needle trench 360, including an illustrative substrate pillar 310. In some implementations, the substrate pillar 310 (e.g., a microneedle) may have a height in a range between 5 and 20 pm, and in a particular implementation, a height of approximately 10 pm. As shown in FIG. 7, the substrate pillar 310 may be formed on the dielectric structure 162. Because the oxide layer 120 acts as an etch stop for the etching operations, etching the needle trench 360 and forming the substrate pillar 310 does not damage the dielectric structure 162 unlike if the dielectric structure were formed in the needle trench 360 prior to formation of the substrate pillar 310. By preventing damage to the dielectric structure 162 in this manner, the multilayer semiconductor device fabrication process described herein results in the dielectric structure 162 acting as a pedestal for the substrate pillar 310 that is not likely to fall over due to damage from the etching process, thereby improving yield of the microneedles described herein as compared to other techniques for etching silicon microneedles. Additionally, the dielectric structure 162 electrically isolates the needle (e.g., the substrate pillar 310) from the actuator base 182, which may run at a higher voltage than the needle, such as up to 18 volts. The substrate pillar 310 may have a custom-shaped feature at a tip that is formed by the combination of lithography operations and etching operations, such as a conical tip, an inverted conical cavity, a polygonal tip, a polygonal cavity, a pad-shaped tip, a circular cavity, other custom shapes, or the like. In some implementations, a hard mask cover 312 may be formed on the tip of the substrate pillar 310 to protect the tip (e.g., the customer feature) from damage during subsequent etch operations or other operations. The hard mask cover 312 may include any of the materials described above with reference to the hard mask layer 190, the second hard mask layer 210, or the additional hard mask layer 350, and deposition of the hard mask material may include any deposition technique described with reference to the hard mask layer 190, the second hard mask layer 210, or the additional hard mask layer 350. Although shown as forming a single substrate pillar 310 in FIG. 7, this is for ease of illustration, and in other examples, the combination of lithography operations and etching operations pattern and form a plurality of substrate pillars (e.g., including the substrate pillar 310) on a plurality of dielectric structures (e.g., including the dielectric structure 162) within the needle trench 360, and each substrate pillar of the plurality of substrate pillars may have a respective custom-shaped feature at the tip.

[0047] To form the substrate pillar 310 and the custom shaped pillar, the one or more lithography operations may include depositing and exposing one or more photoresist layers on the additional hard mask layer 350 to create a custom pattern and using the custom pattern as a mask during the etching operations. The photoresist material may be deposited on the additional hard mask layer 350 using any suitable deposition technique, such as a CVD technique, an ECVD technique, a PECVD technique, a sputtering technique, an evaporation technique, an ALD technique, a spin coating technique, a PLD technique, a molecular-beam epitaxial technique, an electroplating technique, or the like. In some particular implementations, the photoresist layer(s) include dual -ultraviolet (DUV) photoresist that is capable of forming patterns in the 130-180 nm critical dimension (CD) range. The etching operations may include a Bosch etching process that is performed to cut away the first substrate 100, a plasma etching process, a wet etching process, a dry etching process, another type of etching process, or a combination thereof. In some implementations, the combination of lithography operations and etching operations are performed at a particular region of the grinded second surface of the first substrate 100 that is identified based on one or more substrate alignment marks included in the first substrate structure 101. For example, the particular region may be at a preprogrammed location with reference to the first substrate 100, and the location may be identified with a high degree of precision by aligning a semiconductor fabrication tool using alignment information represented by the second alignment marks 134, the fourth alignment marks 234, the fifth alignment marks 332, other alignment marks, or a combination thereof. In some implementations, the etching processes may be controlled such that the substrate pillar 310 is tapered from the dielectric structure 162 to the tip (e.g., where the hard mask cover 312 is located in FIG. 7).

[0048] FIG. 8 illustrates an eighth stage of the multilayer semiconductor device fabrication process. During the eighth stage, one or more oxidative thinning processes may be performed to further taper the substrate pillar 310. In some implementations, a single oxidative thinning process is performed. Alternatively, multiple stages of oxidative thinning may be performed. The one or more oxidative thinning processes may include causing oxide within the substrate pillar 310 to grow, as represented by oxide growth 314 in FIG. 8, in different amounts at different points along the substrate pillar 310. As the oxide growth 314 grows, the substrate pillar 310 beneath the oxide growth 314 thins, such that increasing the oxide growth 314 at one location increases the thinning at that location of the substrate pillar 310 as compared to a different location with less oxide growth 314. The oxide growth 314 may then be removed, resulting in an increased thinning and tapering of the substrate pillar 310. In some implementations that include a plasma etching process, the tapered etching process may include alternating of cycling at the plasma etch tool with the photoresist layer in place, alternating of chamber cleanliness steps at the plasma etch tool in between etching process runs with the photoresist layer in place, SiO growth resharpening in the oxidation tool after removal of the photoresist layer with subsequent SiO removal, other thinning or tapered etching techniques, or a combination thereof. To further illustrate, one or more oxidative thinning processes (e.g., a single-stage or multi-stage oxidative thinning process) may be performed to further decrease a dimension, such as a diameter, toward the tip of the substrate pillar 310 (e.g., an end that includes the custom-shaped feature) as compared to the opposite end of the substrate pillar 310 (e.g., a bottom end in FIG. 8 that extends from the dielectric structure 162). Alternatively, the thinning processes may include one or more chemical thinning processes.

[0049] FIG. 9 illustrates a ninth stage of the multilayer semiconductor device fabrication process. During the ninth stage, one or more vapor etching operations may be performed on the needle trench 360. The vapor etching operations may include hydrogen fluoride (HF) vapor etching operations or another type of vapor etching operations. The vapor etching operations may remove a portion of the oxide layer 120 between the needle trench 360 to extend the needle trench 360 to the semiconductor material layer 130 and to expose the dielectric structure 162. Due to the actuator springs 184 (e.g., openings in the semiconductor material layer 130), the vapor etching operations may also remove portions of the bonded hard mask layer 320 (e.g., the bonded combination of the hard mask layer 190 and the second hard mask layer 210) between the second substrate 200 and the needle trench 360 to form a cavity 362. The cavity 362 may be under the needle trench 360 (in the orientation shown in FIG. 9), and the etching of the cavity 362 may be precisely controlled by placement of the actuator springs 184 and selection of operating parameters for the vapor etching operations. To illustrate, the vapor etching may undercut the needle trench 360 a little during the formation of the cavity 362, but a lateral atrium may be well controlled by the position of the entry points that the vapor has access to the underlying structure. These underlying substructure vapor access locations may be two-dimensionally (2D) spatially located such that a mean free path of the vapor is controlled. For example, the access patterns can be placed in a 2D pattern that causes the vapor to etch out in a in a circular pattern, and a placement that achieves a desired undercut can be determined by solving a mean free path 2D problem. To illustrate, the vapor etching can be precisely simulated, and typically the vapor entry points are located such that when the cavity 362 is etched for a particular amount of time, the undercutting is simulated and thus the vapor entry point locations can be adjusted to achieve a target simulated undercutting. Alternatively, a cutout may be etched on the backside for the vapor entry point, such as by lithographically installing an etched cutout area up to the oxide etch stop, which becomes a sacrificial layer that gets removed in a later stage. In this alternate example, because the cutout area is a circular annular access point, the vapor etching process can similarly be characterized as a mean free path problem, thereby enabling control of the degree of undercutting. After performing the vapor etching operations, the hard mask cover 312 may be removed, exposing a substrate pillar tip 370 of the substrate pillar 310. As described above, the substrate pillar tip 370 may have a custom-feature shape, and may be a feature that extends from the substrate pillar 310 or a cavity within the substrate pillar 310.

[0050] FIG. 10 illustrates a tenth stage of the multilayer semiconductor device fabrication process. During the tenth stage, a third substrate structure 401 may be prepared for bonding with the bonded monolith substrate 300. The third substrate structure 401 may include a third substrate 400 (e.g., a membrane vehicle substrate), a third hard mask layer 420, a nitride membrane layer 430, and a second metal layer 440 (e.g., a second thermocompression bond layer). As shown in FIG. 10, the third hard mask layer 420 may be disposed between the third substrate 400 and the nitride membrane layer 430, and the nitride membrane layer 430 may be disposed between the third hard mask layer 420 and the second metal layer 440. The material layers 420 and 440 may include similar materials to, and may be deposited on the third substrate 400 using similar deposition processes, as described above for the hard mask layer 190 and the first metal layer 340, respectively. The third substrate 400 may include similar materials as described above with reference to the first substrate 100 or the second substrate 200. In some implementations, the third substrate 400 may have a thickness in a range between 300 and 500 pm, and in a particular implementation, a thickness of approximately 400 pm. The nitride membrane layer 430 may include nitride, such as low-stress nitride (LSN) or ultra low stress nitride (ULSN), that forms a membrane for use in isolating the needle cavity 360 from an exterior of the multilayer semiconductor device. For example, the nitride membrane layer 430 may separate the chemical environment of the needle cavity 360 from the exterior nodes at which the microneedles are being deployed. This may circumvent microfluidic, boundary layer fluid exclusion during actuation of the microneedles through respective through-holes (e.g., pores) formed through the nitride membrane layer 430 during a later stage of the process.. Additionally, isolating the chemical environment, the nitride membrane layer 430 (or a back side of the third substrate 400) may act as a substrate that cells can be captured on. For example, cells may be captured adjacent to an interfacing cavity, and inside such an interfacing cavity (e.g., the needle cavity 360), there may be a plurality of various MEMS structures, complex architectures, delivery manifolding, or the like, that can access the captured cells. Another benefit of isolating the needle cavity 360 is provided by electrical signal isolation. For example, unique electrical signal, as well as liquid chemical materials, can be applied inside the needle cavity 360 while being screened from the exterior by the nitride membrane layer 430. This supports applications that perform impedance sensing of the local chemical environment, as well as other applications. In some implementations, the nitride membrane layer 430 may have a thickness in a range between 100 and 300 pm, and in a particular implementation, a thickness of approximately 200 pm.

[0051] The third substrate structure 401 may also include one or more sixth alignment marks (referred to herein as “sixth alignment marks 432”) and one or more seventh alignment marks (referred to herein as “seventh alignment marks 434”). The sixth alignment marks 432 and the seventh alignment marks 434 may be the same or different types of alignment marks that the first alignment marks 132 and the second alignment marks 134, respectively, as described above. In some implementations, the second metal layer 440 may include a recessed opening 442 that is located with a region that corresponds to the location of the substrate pillar 310 in the bonded monolith substrate 300. The recessed opening 442 may be located at the region based on the sixth alignment marks 432 and/or the seventh alignment marks 434, although the recessed opening 442 may have a larger diameter and be located less precisely than a pore that is to be formed within the recessed opening 442, as further described herein.

[0052] FIG. 11 illustrates an eleventh stage of the multilayer semiconductor device fabrication process. During the eleventh stage, the first substrate structure 101 to the third substrate structure 401 via a metallic bond (also referred to as a metal -to-metal bond), as represented by the arrows in FIG. 11. A metallic bond refers to attaching two or more substrates to each other by means of metal films between the substrates, as compared to using adhesive bonding, soldering, or the like. In some implementations, the metallic bond is a thermocompression bond. As shown in FIG. 11, the metallic bond (e.g., the thermocompression bond) may be between the first metal layer 340 and the second metal layer 440 (e.g., at least a portion of the first metal layer 340 may be placed into direct contact with at least a portion of the second metal layer 440). Bonding the first substrate structure 101 to the third substrate structure 401 may create a multilayer semiconductor structure 500 (e.g., a monolith substrate formed from the first substrate 100, the second substrate 200, and the third substrate 400), as shown in FIG. 11. In some implementations, the first metal layer 340 and/or the second metal layer 440 may be grounded and may act as a counter pull up electrode that is part of an electrostatic parallel plate actuator (e.g., the actuator structure 180). As such, these conductive metal layer(s) are utilized not only as a thermal compressive eutectic glue to encapsulate the needle cavity 360, but also as the counter electrode for the actuator structure 180. Additionally, because the conductive metal layer(s) are grounded, they are also utilized as an impedance screen to screen out the chemical environment and electrostatic signal environment exterior to the multilayer semiconductor structure 500.

[0053] In some implementations, the first substrate structure 101 is aligned with the third substrate structure 401 during the bonding based on sets of placement marks (e.g., alignment marks) included in each of the substrate structures. For example, the fifth alignment marks 332 and the sixth alignment marks 432 may be the same type of alignment marks and may be used to align the first substrate structure 101 to the third substrate structure 401 during the bonding process. In some such implementations, a distance 536 between two alignment marks (e.g., of the sixth alignment marks 432) on one substrate structure may be substantially equal to the distance between two corresponding alignment marks (e.g., of the fifth alignment marks 332) on another substrate structure and/or the distance 536 may represent a tolerance for alignment of the two substrate structures during the bonding process. Additionally or alternatively, the second alignment marks 134 and the seventh alignment marks 434 may be the same type of alignment marks and may be used to align the first substrate structure 101 to the third substrate structure 401 during the bonding process.

[0054] FIG. 12 illustrates a twelfth stage of the multilayer semiconductor device fabrication process. During the twelfth stage, the bonding between the first substrate structure 101 and the third substrate structure 401 is complete, forming the multilayer semiconductor structure 500. For example, the first metal layer 340 may be bonded to the second metal layer 440, forming a bonded metal layer at a second bond interface 540 that extends a width of the multilayer semiconductor structure 500. After the bonding process is complete, a second surface (e.g., the top surface in the orientation shown in FIG. 12) of the third substrate 400 that is opposite to a first surface (e.g., the bottom surface in the orientation shown in FIG. 12) may be grinded and/or otherwise reduced. For example, a process that includes grinding, lapping, CMP, or a combination thereof, may remove a portion of the third substrate 400 until a remaining portion has a target thickness. Additionally or alternatively, an additional combination of lithography operations and etching operations may be performed on the second surface of the third substrate 400 to form a through-hole (e.g., a pore) through the third substrate 400, the third hard mask layer 420, and the nitride membrane layer 430 to the needle trench 360, now referred to as the needle cavity 360 as due to being enclosed by the third substrate structure 401. The through-hole may have a diameter that is within a range between 5 gm and 25 gm, such as 10 gm, 15 gm, or 20 gm, in particular implementations. The diameter of the through-hole may be chosen based on an amount of annular coverage needed for the electrostatics of the actuator structure 180. In some implementations, the third hard mask layer 420 and/or the nitride membrane layer 430 may act as a final etch stop when forming the through-hole. To illustrate, because a dry etch performed on the third substrate 400 may result in a thickness variation of up to 25 pm from the center of the etch to a side of the etch, the through-hole may be formed by first performing a dry etch that stops approximately 25-50 pm short of a target depth, and then a chemical etch process may be performed to finish etching the through-hole. The chemical etch may provide approximately 1000-to-l selectivity, such that negligible amounts are lost and a thickness variation is substantially zero.

[0055] The through-hole (not shown) may be aligned with the substrate pillar 310 such that the substrate pillar 310 is able to travel through the through-hole when the actuator structure 180 is actuated without coming into contact with the through-hole. As such, the through hole may be within the recessed opening 442 and may be more finely aligned with the substrate pillar 310 (e.g., a microneedle or other tool formed from the substrate pillar 310 and the substrate pillar tip 370) than the recessed opening 442. To achieve the more fine alignment, the additional combination of lithography operations and etching operations may be performed at a particular region of the second surface of the third substrate 400 that is identified based on one or more substrate alignment marks included in the third substrate structure 401, such as the sixth alignment marks 432 and/or the seventh alignment marks 434. Because the various substrate structures are bonded together using alignment marks, and because the bonding layers and layers that make up the actuator structure 180 are controlled to have little to no TTV across the multilayer semiconductor structure 500, the through-hole may have small dimensions and still be precisely aligned to fit the microneedle, even with its high aspect ratio, without sacrificing additional real estate on the third substrate 400, which would reduce yield of the fabrication process. In some implementations, the substrate structures of the multilayer semiconductor structure 500 (e.g., the first substrate 100 and the third substrate 400) are aligned such that an alignment tolerance (based on various alignment markings) is less than or equal to an allowable mismatch between the through-hole and the substrate pillar tip 370. [0056] In some particular implementations, the fabrication process described above with reference to FIGS. 1-12 results in fabrication of a multilayer semiconductor device (e.g., 500) that includes a first material layer stack (e.g., 101), a second material layer stack (e.g., 201), and a third material layer stack (e.g., 401). The first material stack includes a first plurality of material layers that includes a first substrate (e.g., 100), an oxide layer (e.g., 120) in contact with a first surface of the first substrate and at least partially surrounding a cavity (e.g., 360) in the first material layer stack, a semiconductor material layer (e.g., 130) in contact with the oxide layer, a first hard mask layer (e.g., 190) in contact with the semiconductor material layer, and a first metal layer (e.g., 350) in contact with a second surface of the first substrate that is opposite to the first surface. The cavity includes a substrate pillar (e.g., 310) disposed on a dielectric structure (e.g., 162) and having a custom-shaped feature at a tip (e.g., 370) of the substrate pillar. The oxide layer is disposed between the first substrate and the semiconductor material layer. The semiconductor material layer is disposed between the oxide layer and the first hard mask layer. The second material layer stack includes a second plurality of material layers. The second material layer stack is bonded to the first hard mask layer via a substrate bond (e.g., 322). The third material layer stack includes a third plurality of material layers. The third material layer stack is bonded to the first metal layer via a metallic bond (e.g., 540).

[0057] In some such particular implementations, the second plurality of material layers includes a second substrate (e.g., 200) and a second hard mask layer (e.g., 210) in contact with the second substrate. The substrate bond is between the first hard mask layer and the second hard mask layer. The second hard mask layer at least partially surrounds a second cavity (e.g., 362) within the second material layer stack. In some such implementations, the semiconductor material layer of the first material layer stack includes one or more openings (e.g., 184) that connect the cavity to the second cavity.

[0058] In some such particular implementations, the third plurality of material layers includes a third substrate (e.g., 400), a third hard mask layer (e.g., 420) in contact with the third substrate, a nitride membrane layer (e.g., 430) in contact with the third hard mask layer, and a second metal layer (e.g., 440) in contact with the nitride membrane layer. The third hard mask layer is disposed between the third substrate and the nitride membrane layer. The nitride membrane layer is disposed between the third hard mask layer and the second metal layer. The metallic bond (e.g., 540) is between the first metal layer and the second metal layer. In some such implementations, a through-hole through the third substrate, the third hard mask layer, and the nitride membrane layer connects the cavity to an exterior of the multilayer semiconductor device. The through-hole is aligned with the substrate pillar. In some such implementations, an opening (e.g., 442) in the second metal layer is aligned with and recessed from the through-hole.

[0059] As described above, the multilayer semiconductor device fabrication method described with reference to FIGS. 1-12 enables fabrication of a multilayer semiconductor device that includes microneedles, or other tools, having high aspect ratios in a scalable manner. For example, bonding the first substrate structure 101 to the second substrate structure 201 via a substrate bond reduces the number of bonds used to form the multilayer semiconductor structure 500 without experiencing significant thickness variation from the substrate bond because a significant portion of the bond interface 322 is etched away to form the needle cavity 360 and the cavity 362. Additionally, the metallic (e.g., thermocompression) bond between the first substrate structure 101 and the third substrate structure 401 provides electrical benefits as well as isolating the environment of the needle cavity 360 from an exterior of the multilayer semiconductor structure 500. Other benefits include maintaining a very low TTV across the length of the substrate structures, even after grinding and other operations, due to the use of controlled TTV substrates, the types of bonding used, and avoiding use of CVD for depositing many of the material layers. Maintaining a low TTV prevents different microneedles from being at different heights, which can cause the microneedles to tip over and break or be damaged by misalignment with respective through-holes, thereby reducing yield during fabrication. For example, other silicon microneedle device fabrication techniques may result in a yield of 50% or less of the yield realized by the disclosed processes and techniques. Additionally or alternatively, by the architecture described herein and the use of alignment marks during fabrication enables formation of through-holes through the nitride membrane layer 430 after enclosure of the needle cavity 360 in a manner that is precisely aligned and that does not damage the microneedles (e.g., the substrate pillar tip 370), thereby further improving yield of the disclosed fabrication process.

[0060] Referring to FIG. 13, a flow diagram of an example of a method for fabricating a multilayer semiconductor device containing microneedles according to one or more aspects is shown as a method 1300. In some implementations, the operations of the method 1300 may be stored as instructions that, when executed by one or more processors (e.g., the one or more processors of a computing device or a server), cause the one or more processors to perform the operations of the method 1300. In some implementations, these instructions may be stored on a non-transitory computer-readable storage device or a non-transitory computer-readable storage medium. In some implementations, the method 1300 may be performed by a computing device, such as a computing device described further herein with reference to FIG. 14.

[0061] The method 1300 includes bonding a first substrate structure to a second substrate structure via a substrate bond between a first hard mask layer of the first substrate structure and a second hard mask layer of the second substrate structure, at 1302. For example, the first substrate structure may include or correspond to the first substrate structure 101 of FIGS. 1-5, the second substrate structure may include or correspond to the second substrate structure 201 of FIG. 5, bonding the first substrate structure to the second substrate structure may include or correspond to the bonding process illustrated by the arrows in FIG. 5, and the substrate bond between a first hard mask layer of the first substrate structure and a second hard mask layer of the second substrate structure may include or correspond to the bonded hard mask layer 320 of FIGS. 6-12, including the bond interface 322 of FIGS. 6-12. The first substrate structure may include a first substrate, an oxide layer on a first surface of the first substrate that at least partially surrounds a dielectric structure, a semiconductor material layer on the oxide layer, and the first hard mask layer on the semiconductor material layer. The oxide layer may be disposed between the first substrate and the semiconductor material layer, and the semiconductor material layer may be disposed between the oxide layer and the first hard mask layer. For example, the first substrate may include or correspond to the first substrate 100 of FIGS. 1-12, the oxide layer on the first surface of the first substrate may include or correspond to oxide layer 120 of FIGS. 1-12, the dielectric structure may include or correspond to dielectric structure 162 of FIGS. 3-12, the semiconductor material layer on the oxide layer may include or correspond to the semiconductor material layer 130 of FIGS. 1-12, and the first hard mask layer may include or correspond to the hard mask layer 190 of FIGS. 4-5. The second substrate structure may include a second substrate and the second hard mask layer on the second substrate. For example, the second substrate structure may include or correspond to the second substrate structure 201 of FIG. 5, and the second hard mask layer of the second substrate structure may include or correspond to the second hard mask layer 210 of FIG. 5.

[0062] The method 1300 includes grinding a second surface of the first substrate, at

1304. The second surface may be opposite to the first surface. For example, a depth of the grinded second surface may include or correspond to the remaining thickness 330 of the first substrate 100 illustrated in FIGS 6-12. The depth may also include or correspond to the height of the needle location 110 of FIG. 6 and/or the height of the substrate pillar 310 in FIGS. 7-12. In some implementations, a distance between the grinded second surface of the first substrate and the oxide layer may be within a range between 10 and 50 micrometers.

[0063] The method 1300 includes performing a combination of lithography operations and etching operations on the grinded second surface, at 1306. The combination of lithography operations and etching operations may form a trench within the first substrate structure and a substrate pillar within the trench. The substrate pillar is formed on the dielectric structure and has a custom-shaped feature at a tip of the substrate pillar. For example, the trench may include or correspond to the needle trench 360 of FIGS. 7-9 (also referred to as the needle cavity 360), the substrate pillar may include or correspond to the substrate pillar 310 of FIGS. 7-12, and the customshaped feature at a tip of the substrate pillar may include or correspond to a custom-shaped feature at the substrate pillar tip 370 of FIG. 9.

[0064] In some implementations, the method 1300 may include performing one or more oxidative thinning processes to further taper the substrate pillar. For example, the one or more oxidative thinning processes may include or correspond to the oxide growth 314 illustrated in FIG. 8, which is subsequently removed or etched away, as shown in FIG. 9. As such, the substrate pillar is tapered from the dielectric structure to the tip. Additionally or alternatively, the combination of lithography operations and etching operations of the method 1300 may pattern and form a plurality of substrate pillars on a plurality of dielectric structures within the trench. The plurality of substrate pillars may include the substrate pillar, and each substrate pillar of the plurality of substrate pillars may have a respective custom-shaped feature at the tip.

[0065] In some implementations, the method 1300 may include performing one or more vapor etching operations on the trench. In such implementations, the one or more vapor etching operations may remove a portion of the oxide layer between the trench and the semiconductor material layer to extend the trench to the semiconductor material layer and expose the dielectric structure. For example, the needle trench 360 may be extended as shown in FIG. 9. Additionally or alternatively, the one or more vapor etching operations may remove portions of the first hard mask layer and the second hard mask layer between the second substrate and the trench to form a cavity. For example, the cavity may include or correspond to the cavity 362 of FIGS. 9-12.

[0066] In some implementations, the method 1300 may include, prior to bonding the first substrate structure to the second substrate structure, performing one or more first etching operations on the first substrate structure. In such implementations, the one or more first etching operations may form a second trench in a portion of the first substrate and a portion of the oxide layer. For example, the second trench may include or correspond to the trench 150 of FIG. 2. Notably in this example, trench 150 is depicted as including a bottom surface 152 which extends into the first substrate 100 at a location corresponding to the needle location 110. In such implementations, the method 1300 may include depositing a dielectric material on the oxide layer and the second trench. The dielectric material forms the dielectric structure within a portion of the second trench and a dielectric layer on the oxide layer. The method 1300 may also include depositing a semiconductor material on the dielectric layer and the dielectric structure. The semiconductor material forms the semiconductor material layer on the dielectric layer. For example, the dielectric layer may include or correspond to the dielectric layer 160 in FIG. 3, and the semiconductor material layer may include or correspond to the additional semiconductor material layer 170 in FIG. 3. In some such implementations, the method 1300 may further include, prior to bonding the first substrate structure to the second substrate structure, planarizing the semiconductor material layer. In some such implementations, the planarization may form a substantially smooth surface of the semiconductor material layer that covers the second trench and the dielectric structure. The method 1300 may also include depositing a hard mask material on the semiconductor material layer. In such implementations, the hard mask material may form the first hard mask layer on the semiconductor material layer. The first hard mask layer may also have a substantially smooth surface based on the substantially smooth surface of the semiconductor material layer. For example, the first hard mask layer may include or correspond to the hard mask layer 190 of FIG. 4.

[0067] In some implementations, the combination of lithography operations and etching operations the method 1300 may be performed at a particular region of the grinded second surface of the first substrate. The particular region of the grinded second surface may be identified based on one or more substrate alignment marks included in the first substrate structure. For example, the one or more substrate alignment marks may include or correspond to the first alignment marks 132 and/or the second alignment marks 134 of FIGS. 4-5. Additionally or alternatively, the first substrate structure may be aligned with the second substrate structure during the bonding based on a first set of alignment marks included in the first substrate structure and a second set of alignment marks included in the second substrate structure. For example, the first set of alignment marks included in the first substrate structure may include or correspond to the first alignment marks 132 and/or the second alignment marks 134, and the second set of alignment marks included in the second substrate structure may include or correspond to the third alignment marks 232 and/or fourth alignment marks 234.

[0068] In some implementations, the method 1300 may include, prior to performing the combination of lithography operations and etching operations, forming a first metal layer on a portion of the grinded second surface of the first substrate. The first metal layer may be recessed from and may expose a region at which the trench is to be formed. For example, the first metal layer may include or correspond to the first metal layer 340 of FIGS. 6-12. In some such implementations, forming the first metal layer includes performing a metallization liftoff process on the portion of the grinded second surface of the first substrate. Alternatively or additionally, the method 1300 may include bonding the first substrate structure to a third substrate structure via a metallic bond between the first metal layer of the first substrate structure and a second metal layer of the third substrate structure. For example, the third substrate structure may include or correspond to the third substrate structure 401 of FIGS. 10-11, the metallic bond may include or correspond to the second bond interface 540 of FIG. 12, and bonding the first substrate structure to a third substrate structure via a metallic bond may include or correspond to the bonding process illustrated in FIG. 11. The third substrate structure may include a third substrate, a third hard mask layer on a third surface of the third substrate, a nitride membrane layer on the third hard mask layer, and the second metal layer on the nitride membrane layer. For example, the third substrate may include or correspond to the third substrate 400 of FIGS. 10-12, the third hard mask layer may include or correspond to the third hard mask layer 420 of FIGS. 10-12, the nitride membrane layer may include or correspond to the nitride membrane layer 430 of FIGS. 10-12, and the second metal layer may include or correspond to the second metal layer 440 of FIGS. 10-12. The third hard mask layer may be disposed between the third substrate and the nitride membrane layer and the nitride membrane layer may be disposed between the third hard mask layer and the second metal layer, as shown in FIG. 10. In some such implementations, the metallic bond includes a thermocompression bond between the first metal layer and the second metal layer. [0069] In some implementations that include the bonding of the first substrate structure and the third substrate structure, the method 1300 may further include grinding a fourth surface of the third substrate. The fourth surface is opposite to the third surface. For example, the fourth surface of the third substrate may include or correspond to the top surface of the third substrate 400 in the orientation shown in FIG. 10. In some such implementations, the method 1300 may further include performing an additional combination of lithography operations and etching operations on the grinded fourth surface of the third substrate. The additional combination of lithography operations and etching operations form a through-hole through the third substrate, the third hard mask layer, and the nitride membrane layer to the trench, and the through-hole is aligned with the substrate pillar, as described with reference to FIG. 12. In some particular implementations, the additional combination of lithography operations and etching operations are performed at a particular region of the grinded fourth surface. The particular region of the grinded fourth surface may be identified based on one or more substrate alignment marks included in the third substrate structure. For example, the one or more substrate alignment marks may include or correspond to sixth alignment marks 432 and/or seventh alignment marks 434 of FIGS. 10-11. In some particular implementations, the first substrate structure may be aligned with the third substrate structure during the bonding based on a third set of placement marks included in the first substrate structure and a fourth set of placement marks included in the third substrate structure. For example, the third set of placement marks may include or correspond to fifth alignment marks 332 of FIG. 11.

[0070] Referring to FIG. 14, an example of a computing device that is operable to support fabrication of a multilayer semiconductor device containing microneedles according to one or more aspects of the present disclosure is shown as a computing environment 1400 that includes a computing device 1410. The computing device 1410 may be operable to initiate or control fabrication of one or more multilayer semiconductor devices that contain microneedles or other tools, including the stages of the process described with reference to FIGS. 1-12.

[0071] The computing device 1410 includes at least one processor 1420 and system memory 1430. Depending on the configuration and type of computing device, the system memory 1430 may be volatile (such as random access memory or “RAM”), non-volatile (such as read-only memory or “ROM,” flash memory, and similar memory devices that maintain stored data even when power is not provided) or some combination of the two. The system memory 1430 typically includes instructions 1432 and one or more applications. The at least one processor 1420 may be operable to execute the instructions 1432 to perform one or more operations described herein, including operations of the method 1300 of FIG. 13. Alternatively, the instructions 1432, the applications, or both, may be located at multiple computing devices, where the multiple computing devices are part of a distributed computing system. In this case, one or more of the multiple computing devices of the distributed system may comprise the representative computing device 1410.

[0072] The computing device 1410 may also have additional features or functionality. For example, the computing device 1410 may also include removable and/or non-removable data storage devices such as magnetic disks, optical disks, tape, and standard-sized or miniature flash memory cards. Such additional storage is illustrated in FIG. 14 by storage 1440. Computer storage media may include volatile and/or non-volatile storage and removable and/or non-removable media implemented in any method or technology for storage of information such as computer- readable instructions, data structures, program components or other data. The system memory 1430 and the storage 1440 are examples of computer storage media. The computer storage media includes, but is not limited to, RAM, ROM, electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disks (CD), digital versatile disks (DVD) or other optical storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store information and that can be accessed by computing device 1410. Any such computer storage media may be part of the computing device 1410. The computing device 1410 may also have input/output (VO) device(s) 1450, which may include input devices, such as a keyboard, mouse, pen, voice input device, touch input device, etc., output device(s), such as a display, speakers, a printer, etc., or a combination thereof.

[0073] The computing device 1410 also contains one or more communication interface(s) 1460 that allow the computing device 1410 to communicate with a fabrication system 1480 via a wired or a wireless network 1470. The fabrication system 1480 may include one or more semiconductor fabrication tools, one or more computing devices, other tools or devices, or a combination thereof. In an illustrative embodiment, the fabrication system 1480 may initiate or facilitate any of the stages of the process described with reference to FIGS. 1-12. [0074] The communication interface(s) 1460 are an example of communication media. By way of example, and not limitation, communication media may include wired media such as a wired network or direct-wired connection, and wireless media, such as acoustic, radio frequency (RF), infrared and other wireless media. It will be appreciated, however, that not all of the components or devices illustrated in FIG. 14 or otherwise described in the previous paragraphs are necessary to support embodiments as herein described. For example, the VO device(s) 1450 may be optional.

[0075] It is noted that other types of devices and functionality may be provided according to aspects of the present disclosure and discussion of specific devices and functionality herein have been provided for purposes of illustration, rather than by way of limitation. It is noted that the operations of the method 1300 of FIG. 13 may be performed in any order. It is also noted that the method 1300 of FIG. 13 may also include other functionality or operations consistent with the description of the operations of the stages of the process described with reference to FIGS. 1- 12. Additionally or alternatively, the computing device 1410 of FIG. 14 may be configured to perform operations of the method 1300 of FIG. 13 and/or operations of any of the stages of the process described with reference to FIGS. 1-12.

[0076] Those of skill in the art would understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0077] Components, the functional blocks, and the modules described herein with respect to FIGS. 1-14) include processors, electronics devices, hardware devices, electronics components, logical circuits, memories, software codes, firmware codes, among other examples, or any combination thereof. In addition, features discussed herein may be implemented via specialized processor circuitry, via executable instructions, or combinations thereof.

[0078] Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure. Skilled artisans will also readily recognize that the order or combination of components, methods, or interactions that are described herein are merely examples and that the components, methods, or interactions of the various aspects of the present disclosure may be combined or performed in ways other than those illustrated and described herein.

[0079] The various illustrative logics, logical blocks, modules, circuits, and algorithm processes described in connection with the implementations disclosed herein may be implemented as electronic hardware, computer software, or combinations of both. The interchangeability of hardware and software has been described generally, in terms of functionality, and illustrated in the various illustrative components, blocks, modules, circuits and processes described above. Whether such functionality is implemented in hardware or software depends upon the particular application and design constraints imposed on the overall system.

[0080] The hardware and data processing apparatus used to implement the various illustrative logics, logical blocks, modules, and circuits described in connection with the aspects disclosed herein may be implemented or performed with a general purpose single- or multi-chip processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, or any conventional processor, controller, microcontroller, or state machine. In some implementations, a processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration. In some implementations, particular processes and methods may be performed by circuitry that is specific to a given function.

[0081] In one or more aspects, the functions described may be implemented in hardware, digital electronic circuitry, computer software, firmware, including the structures disclosed in this specification and their structural equivalents thereof, or any combination thereof. Implementations of the subject matter described in this specification also may be implemented as one or more computer programs, that is one or more modules of computer program instructions, encoded on a computer storage media for execution by, or to control the operation of, data processing apparatus.

[0082] If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. The processes of a method or algorithm disclosed herein may be implemented in a processor-executable software module which may reside on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that may be enabled to transfer a computer program from one place to another. A storage media may be any available media that may be accessed by a computer. By way of example, and not limitation, such computer- readable media can include random-access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that may be used to store desired program code in the form of instructions or data structures and that may be accessed by a computer. Also, any connection may be properly termed a computer-readable medium. Disk and disc, as used herein, includes compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk, hard disk, solid state disk, and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media. Additionally, the operations of a method or algorithm may reside as one or any combination or set of codes and instructions on a machine readable medium and computer-readable medium, which may be incorporated into a computer program product.

[0083] Various modifications to the implementations described in this disclosure may be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to some other implementations without departing from the spirit or scope of this disclosure. Thus, the claims are not intended to be limited to the implementations shown herein, but are to be accorded the widest scope consistent with this disclosure, the principles and the novel features disclosed herein. [0084] Additionally, a person having ordinary skill in the art will readily appreciate, the terms “upper” and “lower” are sometimes used for ease of describing the figures, and indicate relative positions corresponding to the orientation of the figure on a properly oriented page, and may not reflect the proper orientation of any device as implemented.

[0085] Certain features that are described in this specification in the context of separate implementations also may be implemented in combination in a single implementation. Conversely, various features that are described in the context of a single implementation also may be implemented in multiple implementations separately or in any suitable subcombination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination may in some cases be excised from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination.

[0086] Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. Further, the drawings may schematically depict one more example processes in the form of a flow diagram. However, other operations that are not depicted may be incorporated in the example processes that are schematically illustrated. For example, one or more additional operations may be performed before, after, simultaneously, or between any of the illustrated operations. In certain circumstances, multitasking and parallel processing may be advantageous. Moreover, the separation of various system components in the implementations described above should not be understood as requiring such separation in all implementations, and it should be understood that the described program components and systems may generally be integrated together in a single software product or packaged into multiple software products. Additionally, some other implementations are within the scope of the following claims. In some cases, the actions recited in the claims may be performed in a different order and still achieve desirable results.

[0087] As used herein, including in the claims, various terminology is for the purpose of describing particular implementations only and is not intended to be limiting of implementations. For example, as used herein, an ordinal term (e.g., “first,” “second,” “third,” etc.) used to modify an element, such as a structure, a component, an operation, etc., does not by itself indicate any priority or order of the element with respect to another element, but rather merely distinguishes the element from another element having a same name (but for use of the ordinal term). The term “coupled” is defined as connected, although not necessarily directly, and not necessarily mechanically; two items that are “coupled” may be unitary with each other, the term “or,” when used in a list of two or more items, means that any one of the listed items may be employed by itself, or any combination of two or more of the listed items may be employed. For example, if a composition is described as containing components A, B, or C, the composition may contain A alone; B alone; C alone; A and B in combination; A and C in combination; B and C in combination; or A, B, and C in combination. Also, as used herein, including in the claims, “or” as used in a list of items prefaced by “at least one of’ indicates a disjunctive list such that, for example, a list of “at least one of A, B, or C” means A or B or C or AB or AC or BC or ABC (that is A and B and C) or any of these in any combination thereof. The term “substantially” is defined as largely but not necessarily wholly what is specified - and includes what is specified; e.g., substantially 90 degrees includes 90 degrees and substantially parallel includes parallel - as understood by a person of ordinary skill in the art. In any disclosed aspect, the term “substantially” may be substituted with “within [a percentage] of’ what is specified, where the percentage includes 0.1, 1, 5, and 10 percent; and the term “approximately” may be substituted with “within 10 percent of’ what is specified. The phrase “and/or” means and or.

[0088] Although the aspects of the present disclosure and their advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit of the disclosure as defined by the appended claims. Moreover, the scope of the present application is not intended to be limited to the particular implementations of the process, machine, manufacture, composition of matter, means, methods and processes described in the specification. As one of ordinary skill in the art will readily appreciate from the present disclosure, processes, machines, manufacture, compositions of matter, means, methods, or operations, presently existing or later to be developed that perform substantially the same function or achieve substantially the same result as the corresponding aspects described herein may be utilized according to the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or operations.

Claims

CLAIMS What is claimed is:

1. A method of fabricating multilayer semiconductor devices with microneedles having high aspect ratios, the method comprising: bonding a first substrate structure to a second substrate structure via a substrate bond between a first hard mask layer of the first substrate structure and a second hard mask layer of the second substrate structure, wherein the first substrate structure includes a first substrate, an oxide layer on a first surface of the first substrate that at least partially surrounds a dielectric structure, a semiconductor material layer on the oxide layer, and the first hard mask layer on the semiconductor material layer, the oxide layer disposed between the first substrate and the semiconductor material layer, the semiconductor material layer disposed between the oxide layer and the first hard mask layer, and wherein the second substrate structure includes a second substrate and the second hard mask layer on the second substrate; grinding a second surface of the first substrate, the second surface opposite to the first surface; and performing a combination of lithography operations and etching operations on the grinded second surface, the combination of lithography operations and etching operations forming a trench within the first substrate structure and a substrate pillar within the trench, the substrate pillar formed on the dielectric structure and having a custom-shaped feature at a tip of the substrate pillar.

2. The method of claim 1, further comprising: performing one or more oxidative thinning processes to further taper the substrate pillar, the substrate pillar tapered from the dielectric structure to the tip.

3. The method of any of claims 1 or 2, wherein the combination of lithography operations and etching operations pattern and form a plurality of substrate pillars on a plurality of dielectric structures within the trench, the plurality of substrate pillars including the substrate pillar, and wherein each substrate pillar of the plurality of substrate pillars has a respective custom-shaped feature at the tip.

4. The method of any of claims 1-3, further comprising: performing one or more vapor etching operations on the trench, wherein the one or more vapor etching operations remove a portion of the oxide layer between the trench and the semiconductor material layer to extend the trench to the semiconductor material layer and expose the dielectric structure, and wherein the one or more vapor etching operations remove portions of the first hard mask layer and the second hard mask layer between the second substrate and the trench to form a cavity.

5. The method of any of claims 1-4, further comprising, prior to bonding the first substrate structure to the second substrate structure: performing one or more first etching operations on the first substrate structure, the one or more first etching operations forming a second trench in a portion of the first substrate and a portion of the oxide layer; depositing a dielectric material on the oxide layer and the second trench, the dielectric material forming the dielectric structure within a portion of the second trench and a dielectric layer on the oxide layer; and depositing a semiconductor material on the dielectric layer and the dielectric structure, the semiconductor material forming the semiconductor material layer on the dielectric layer.

6. The method of claim 5, further comprising, prior to bonding the first substrate structure to the second substrate structure: planarizing the semiconductor material layer, the planarization forming a substantially smooth surface of the semiconductor material layer that covers the second trench and the dielectric structure; and depositing a hard mask material on the semiconductor material layer, wherein the hard mask material forms the first hard mask layer on the semiconductor material layer, the first hard mask layer having a substantially smooth surface based on the substantially smooth surface of the semiconductor material layer.

7. The method of any of claims 1-6, wherein the combination of lithography operations and etching operations are performed at a particular region of the grinded second surface of the first substrate, and wherein the particular region of the grinded second surface is identified based on one or more substrate alignment marks included in the first substrate structure.

8. The method of any of claims 1-7, wherein the first substrate structure is aligned with the second substrate structure during the bonding based on a first set of alignment marks included in the first substrate structure and a second set of alignment marks included in the second substrate structure.

9. The method of any of claims 1-8, wherein a distance between the grinded second surface of the first substrate and the oxide layer is within a range between 10 and 50 micrometers.

10. The method of any of claims 1-9, further comprising, prior to performing the combination of lithography operations and etching operations: forming a first metal layer on a portion of the grinded second surface of the first substrate, wherein the first metal layer is recessed from and exposes a region at which the trench is to be formed.

11. The method of claim 10, wherein forming the first metal layer comprises performing a metallization liftoff process on the portion of the grinded second surface of the first substrate.

12. The method of any of claims 10 or 11, further comprising: bonding the first substrate structure to a third substrate structure via a metallic bond between the first metal layer of the first substrate structure and a second metal layer of the third substrate structure, the third substrate structure including a third substrate, a third hard mask layer on a third surface of the third substrate, a nitride membrane layer on the third hard mask layer, and the second metal layer on the nitride membrane layer, wherein the third hard mask layer is disposed between the third substrate and the nitride membrane layer, and wherein the nitride membrane layer is disposed between the third hard mask layer and the second metal layer.

13. The method of claim 12, wherein the metallic bond comprises a thermocompression bond between the first metal layer and the second metal layer.

14. The method of any of claims 12 or 13, further comprising: grinding a fourth surface of the third substrate, the fourth surface opposite to the third surface.

15. The method of claim 14, further comprising: performing an additional combination of lithography operations and etching operations on the grinded fourth surface of the third substrate, the additional combination of lithography operations and etching operations forming a through-hole through the third substrate, the third hard mask layer, and the nitride membrane layer to the trench, wherein the through-hole is aligned with the substrate pillar.

16. The method of claim 15, wherein the additional combination of lithography operations and etching operations are performed at a particular region of the grinded fourth surface, and wherein the particular region of the grinded fourth surface is identified based on one or more substrate alignment marks included in the third substrate structure.

17. The method of claim 16, wherein the first substrate structure is aligned with the third substrate structure during the bonding based on a third set of alignment marks included in the first substrate structure and a fourth set of alignment marks included in the third substrate structure.

18. A non-transitory computer-readable storage device storing instructions that, when executed by one or more processors, cause the one or more processors to perform operations for fabricating multilayer semiconductor devices with microneedles having high aspect ratios, the operations comprising: initiating bonding of a first substrate structure to a second substrate structure via a substrate bond between a first hard mask layer of the first substrate structure and a second hard mask layer of the second substrate structure, wherein the first substrate structure includes a first substrate, an oxide layer on a first surface of the first substrate that at least partially surrounds a dielectric structure, a semiconductor material layer on the oxide layer, and the first hard mask layer on the semiconductor material layer, the oxide layer disposed between the first substrate and the semiconductor material layer, the semiconductor material layer disposed between the oxide layer and the first hard mask layer, and wherein the second substrate structure includes a second substrate and the second hard mask layer on the second substrate; initiating grinding of a second surface of the first substrate, the second surface opposite to the first surface; and initiating performance of a combination of lithography operations and etching operations on the grinded second surface, the combination of lithography operations and etching operations forming a trench within the first substrate structure and a substrate pillar within the trench, the substrate pillar formed on the dielectric structure and having a custom-shaped feature at a tip of the substrate pillar.

19. The non-transitory computer-readable storage device of claim 18, wherein the operations further comprise: initiating performance of one or more vapor etching operations on the trench, wherein the one or more vapor etching operations remove a portion of the oxide layer between the trench and the semiconductor material layer to extend the trench to the semiconductor material layer and expose the dielectric structure, and wherein the one or more vapor etching operations remove portions of the first hard mask layer and the second hard mask layer between the second substrate and the trench to form a cavity.

20. The non-transitory computer-readable storage device of any of claims 18 or 19, wherein the operations further comprise, prior to initiating performance of the combination of lithography operations and etching operations: initiating formation of a first metal layer on a portion of the grinded second surface of the first substrate, wherein the first metal layer is recessed from and exposes a region at which the trench is to be formed; and initiating bonding of the first substrate structure to a third substrate structure via a metallic bond between the first metal layer of the first substrate structure and a second metal layer of the third substrate structure, the third substrate structure including a third substrate, a third hard mask layer on a third surface of the third substrate, a nitride membrane layer on the third hard mask layer, and the second metal layer on the nitride membrane layer, wherein the third hard mask layer is disposed between the third substrate and the nitride membrane layer, and wherein the nitride membrane layer is disposed between the third hard mask layer and the second metal layer.

21. A multilayer semiconductor device comprising: a first material layer stack comprising a first plurality of material layers, wherein the first plurality of material layers includes: a first substrate; an oxide layer in contact with a first surface of the first substrate and at least partially surrounding a cavity in the first material layer stack, the cavity including a substrate pillar disposed on a dielectric structure and having a custom-shaped feature at a tip of the substrate pillar; a semiconductor material layer in contact with the oxide layer, wherein the oxide layer is disposed between the first substrate and the semiconductor material layer; a first hard mask layer in contact with the semiconductor material layer, wherein the semiconductor material layer is disposed between the oxide layer and the first hard mask layer; and a first metal layer in contact with a second surface of the first substrate that is opposite to the first surface; a second material layer stack comprising a second plurality of material layers, the second material layer stack bonded to the first hard mask layer via a substrate bond; and a third material layer stack comprising a third plurality of material layers, the third material layer stack bonded to the first metal layer via a metallic bond.

22. The multilayer semiconductor device of claim 21, wherein the second plurality of material layers includes: a second substrate; and a second hard mask layer in contact with the second substrate, wherein the substrate bond is between the first hard mask layer and the second hard mask layer, and wherein the second hard mask layer at least partially surrounds a second cavity within the second material layer stack.

23. The multilayer semiconductor device of claim 22, wherein the semiconductor material layer of the first material layer stack includes one or more openings that connect the cavity to the second cavity.

24. The multilayer semiconductor device of any of claims 21-23, wherein the substrate pillar is tapered from the dielectric structure to the tip.

25. The multilayer semiconductor device of any of claims 21-24, wherein the cavity includes a plurality of dielectric structures and a plurality of substrate pillars that include the substrate pillar, and wherein each substrate pillar of the plurality of substrate pillars is disposed on a respective dielectric structure of the plurality of dielectric structures and has a respective custom-shaped feature at the tip.

26. The multilayer semiconductor device of any of claims 21-25, wherein the third plurality of material layers includes: a third substrate; a third hard mask layer in contact with the third substrate; a nitride membrane layer in contact with the third hard mask layer, wherein the third hard mask layer is disposed between the third substrate and the nitride membrane layer; and a second metal layer in contact with the nitride membrane layer, wherein the nitride membrane layer is disposed between the third hard mask layer and the second metal layer, and wherein the metallic bond is between the first metal layer and the second metal layer.

27. The multilayer semiconductor device of claim 26, wherein a through-hole through the third substrate, the third hard mask layer, and the nitride membrane layer connects the cavity to an exterior of the multilayer semiconductor device, and wherein the through-hole is aligned with the substrate pillar.

28. The multilayer semiconductor device of claim 27, wherein an opening in the second metal layer is aligned with and recessed from the through-hole.