WO2023223589A1 - Puce semi-conductrice - Google Patents

Puce semi-conductrice Download PDF

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Publication number
WO2023223589A1
WO2023223589A1 PCT/JP2022/046592 JP2022046592W WO2023223589A1 WO 2023223589 A1 WO2023223589 A1 WO 2023223589A1 JP 2022046592 W JP2022046592 W JP 2022046592W WO 2023223589 A1 WO2023223589 A1 WO 2023223589A1
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WO
WIPO (PCT)
Prior art keywords
gate
region
wiring
gate wiring
semiconductor chip
Prior art date
Application number
PCT/JP2022/046592
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English (en)
Japanese (ja)
Inventor
健良 増田
Original Assignee
住友電気工業株式会社
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Publication of WO2023223589A1 publication Critical patent/WO2023223589A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the present disclosure relates to a semiconductor chip.
  • a semiconductor chip including a plurality of transistor cells arranged in parallel is known (for example, see Patent Document 1).
  • a semiconductor chip of the present disclosure includes a plurality of transistor cells arranged in a row along a first direction, and the transistor cell has a gate wiring extending along a second direction orthogonal to the first direction.
  • the gate wiring is arranged so that mutual inductance generated between the gate wiring of the adjacent transistor cell has a negative value.
  • FIG. 1 is a circuit diagram showing a semiconductor chip according to an embodiment.
  • FIG. 2 is a plan view showing the semiconductor chip according to the embodiment.
  • FIG. 3 is a cross-sectional view (part 1) showing the semiconductor chip according to the embodiment.
  • FIG. 4 is a cross-sectional view (part 2) showing the semiconductor chip according to the embodiment.
  • FIG. 5 is a cross-sectional view (part 3) showing the semiconductor chip according to the embodiment.
  • An object of the present disclosure is to provide a semiconductor chip that can reduce internal inductance.
  • a semiconductor chip includes a plurality of transistor cells arranged in a row along a first direction, and the transistor cells are arranged along a second direction orthogonal to the first direction.
  • the gate wiring has an extending gate wiring, and the gate wiring is arranged so that mutual inductance generated between the gate wiring of the adjacent transistor cell has a negative value.
  • the mutual inductance acts in a direction that reduces the self-inductance, so the internal inductance of the gate wiring can be reduced. Therefore, ringing of the gate voltage can be suppressed.
  • the gate wiring may be arranged so that the direction of current flowing along the second direction is opposite to the gate wiring of the adjacent transistor cell. In this case, mutual inductance tends to be a negative value.
  • a semiconductor substrate In [1] or [2], a semiconductor substrate, a gate pad disposed on the semiconductor substrate, a first connection wiring that electrically connects the gate wiring and the gate pad, and the a second connection wiring that electrically connects the gate wiring and the gate pad, the first connection wiring extending along the first direction, and the second connection wiring connecting the first connection wiring a first gate wiring that is electrically connected to the first connection wiring, and a first gate wiring that is electrically connected to the second connection wiring.
  • second gate wirings, and the first gate wirings and the second gate wirings may be arranged alternately along the first direction. In this case, currents in opposite directions tend to flow through adjacent gate wirings.
  • the first gate wiring and the second gate wiring may be parallel to each other. In this case, mutual inductance tends to act in a direction that reduces self-inductance.
  • the semiconductor substrate may be a silicon carbide substrate. In this case, it is easy to obtain an excellent withstand voltage.
  • the plurality of transistor cells may be electrically connected to a common source terminal and electrically connected to a common drain terminal.
  • a plurality of transistor cells can be mounted on one semiconductor chip.
  • the transistor cell may be a vertical transistor cell. In this case, it is easy to achieve both reduction in on-resistance and improvement in breakdown voltage.
  • a semiconductor chip 1 according to an embodiment will be explained.
  • FIG. 1 is a circuit diagram showing a semiconductor chip 1 according to an embodiment. As shown in FIG. 1, the semiconductor chip 1 according to the embodiment includes a plurality of transistor cells 100.
  • the plurality of transistor cells 100 are electrically connected in parallel.
  • the plurality of transistor cells 100 are electrically connected to a common gate terminal G, a common source terminal S, and a common drain terminal D.
  • a plurality of transistor cells 100 can be mounted on one semiconductor chip 1.
  • a body diode BD is generated between a source terminal S and a drain terminal D.
  • Each transistor cell 100 is connected to a gate terminal G by a gate wiring 22.
  • Each gate wiring 22 may have internal inductance.
  • the internal inductance includes the self-inductance of each gate wiring 22 and mutual inductance due to each gate wiring 22 and adjacent gate wirings 22.
  • Each gate wiring 22 is arranged so that the mutual inductance generated between the gate wiring 22 of the adjacent transistor cell 100 has a negative value.
  • the mutual inductance acts in a direction to reduce the self-inductance, so the internal inductance of the gate wiring 22 can be reduced. Therefore, ringing of the gate voltage can be suppressed.
  • each gate wiring 22 For example, if the absolute value of the self-inductance of each gate wiring 22 is L and the absolute value of mutual inductance is M, then the internal inductance of each gate wiring 22 is LM. Therefore, the internal inductance of each gate wiring 22 can be reduced.
  • each gate wiring 22 is arranged so that the mutual inductance generated between the gate wiring 22 of the adjacent transistor cell 100 has a positive value, the internal inductance of each gate wiring 22 becomes L+M. Therefore, the internal inductance of each gate wiring 22 increases.
  • FIG. 2 is a plan view showing the semiconductor chip 1 according to the embodiment. As shown in FIG. 2, the semiconductor chip 1 according to the embodiment includes a plurality of transistor cells 100.
  • the plurality of transistor cells 100 are arranged side by side along the Y-axis direction, with the X-axis direction being the longitudinal direction.
  • the Y-axis direction is an example of a first direction
  • the X-axis direction is an example of a second direction.
  • Each transistor cell 100 is, for example, a vertical transistor cell with a trench gate structure.
  • Each transistor cell 100 may be a vertical transistor cell with a planar gate structure. When each transistor cell 100 is a vertical transistor cell, it is easy to reduce on-resistance and improve breakdown voltage.
  • Each transistor cell 100 has a gate wiring 22 extending along the X-axis direction.
  • Each gate wiring 22 is arranged such that, for example, the direction of current flowing along the X-axis direction is opposite to that of the gate wiring 22 of an adjacent transistor cell 100. In this case, mutual inductance tends to be a negative value.
  • the plurality of gate wirings 22 include a first gate wiring 22a and a second gate wiring 22b.
  • the first gate wiring 22a is electrically connected to the gate runner 51 and not electrically connected to the gate runner 52.
  • the second gate wiring 22b is electrically connected to the gate runner 52 and not electrically connected to the gate runner 51.
  • the first gate wiring 22a and the second gate wiring 22b are arranged alternately along the Y-axis direction, for example. In this case, currents in opposite directions are likely to flow through adjacent gate wirings 22 .
  • the first gate wiring 22a, the second gate wiring 22b, and the gate runners 51 and 52 are arranged, for example, in a comb shape. Gate runners 51 and 52 are electrically connected to gate pad 60.
  • the plurality of gate wirings 22 are, for example, parallel to each other. In this case, mutual inductance tends to act in a direction that reduces self-inductance.
  • FIG. 3 to 5 are cross-sectional views showing the semiconductor chip 1 according to the embodiment.
  • FIG. 3 is a cross-sectional view taken along line AA in FIG.
  • FIG. 4 is a sectional view taken along line BB in FIG.
  • FIG. 5 is a sectional view taken along line CC in FIG. 2.
  • the semiconductor chip 1 mainly includes a silicon carbide substrate 10, a gate insulating film 21, a gate wiring 22, an interlayer insulating film 23, a source electrode 30, It has a drain electrode 40, gate runners 51 and 52, and a gate pad 60.
  • Silicon carbide substrate 10 is an example of a semiconductor substrate. When using silicon carbide substrate 10, it is easy to obtain excellent breakdown voltage. Silicon carbide substrate 10 includes a silicon carbide single crystal substrate 11 and a silicon carbide epitaxial layer 12 on silicon carbide single crystal substrate 11 . Silicon carbide substrate 10 has a first main surface 10A and a second main surface 10B opposite to the first main surface 10A. Silicon carbide epitaxial layer 12 constitutes first principal surface 10A, and silicon carbide single crystal substrate 11 constitutes second principal surface 10B. Silicon carbide single crystal substrate 11 and silicon carbide epitaxial layer 12 are made of, for example, hexagonal silicon carbide of polytype 4H. Silicon carbide single crystal substrate 11 contains an n-type impurity such as nitrogen (N), and has n-type conductivity type. A plurality of transistor cells 100 are formed on a silicon carbide substrate 10.
  • N nitrogen
  • Silicon carbide epitaxial layer 12 mainly includes a drift region 13 , a body region 14 , a source region 15 , a contact region 16 , an electric field relaxation region 17 , and a connection region 18 .
  • the drift region 13 contains an n-type impurity such as nitrogen or phosphorus (P), and has an n-type conductivity type.
  • the drift region 13 has a first region 13A, a second region 13B, and a third region 13C.
  • Body region 14 is provided above the drift region 13.
  • Body region 14 contains, for example, a p-type impurity such as aluminum (Al), and has p-type conductivity type.
  • Source region 15 is provided on the body region 14.
  • Source region 15 contains an n-type impurity such as nitrogen or phosphorus, and has n-type conductivity.
  • Source region 15 is separated from drift region 13 by body region 14 .
  • Source region 15 constitutes first main surface 10A.
  • Contact region 16 contains, for example, a p-type impurity such as aluminum, and has p-type conductivity type. Contact region 16 penetrates source region 15 and contacts body region 14 . Contact region 16 constitutes first main surface 10A.
  • the effective concentration of p-type impurities in the contact region 16 is, for example, 1 ⁇ 10 18 cm ⁇ 3 or more and 2 ⁇ 10 20 cm ⁇ 3 or less.
  • a gate trench 5 defined by a side surface 3 and a bottom surface 4 is provided on the first main surface 10A.
  • Side surface 3 penetrates source region 15 and body region 14 to reach drift region 13 .
  • the side surface 3 may be, for example, a surface inclined from the second main surface 10B, or a surface perpendicular to the second main surface 10B.
  • the bottom surface 4 is continuous with the side surface 3.
  • the bottom surface 4 is in the drift region 13.
  • the bottom surface 4 is, for example, a plane parallel to the second main surface 10B.
  • the gate trench 5 extends, for example, in a stripe shape along the X-axis direction.
  • the plurality of gate trenches 5 When viewed in plan from a direction perpendicular to the first main surface 10A, the plurality of gate trenches 5 are provided at regular intervals in the Y-axis direction.
  • the plurality of gate trenches 5 may be provided, for example, in an array.
  • the electric field relaxation region 17 contains a p-type impurity such as aluminum, and has a p-type conductivity type.
  • the electric field relaxation region 17 extends along the X-axis direction.
  • Electric field relaxation region 17 is located between body region 14 and second main surface 10B. When viewed in plan from a direction perpendicular to the first main surface 10A, the electric field relaxation region 17 includes a portion that overlaps with the gate trench 5.
  • the electric field relaxation region 17 relieves electric field concentration on the gate insulating film 21 in contact with the bottom surface 4 when a high voltage is applied.
  • the upper end surface of the electric field relaxation region 17 is separated from the bottom surface 4 in the direction perpendicular to the second main surface 10B.
  • the upper end surface of the electric field relaxation region 17 may include the bottom surface 4 of the gate trench 5. A portion of the upper end surface of electric field relaxation region 17 faces a portion of the lower end surface of body region 14 .
  • Electric field relaxation region 17 is electrically connected to source electrode 30 . In this case, the electric field relaxation region 17 becomes the source potential, and the parasitic capacitance between the gate wiring 22 and the drain electrode 40 can be reduced. Therefore, switching speed is improved.
  • the effective concentration of p-type impurities in the electric field relaxation region 17 is, for example, 5 ⁇ 10 17 cm ⁇ 3 or more and 5 ⁇ 10 18 cm ⁇ 3 or less.
  • connection region 18 contains, for example, a p-type impurity such as aluminum, and has a p-type conductivity type.
  • the connection region 18 penetrates the first region 13A and reaches the electric field relaxation region 17.
  • Connection region 18 electrically connects body region 14 and electric field relaxation region 17 .
  • Connection region 18 contacts body region 14 .
  • Connection region 18 may contact contact region 16 .
  • Connection region 18 may contact each of body region 14 and contact region 16 .
  • Connection region 18 is between contact region 16 and electric field relaxation region 17 .
  • Connection region 18 is closer to second main surface 10B than contact region 16 is.
  • the connection region 18 is located closer to the first main surface 10A than the electric field relaxation region 17 is.
  • a plurality of connection regions 18 are arranged at regular intervals along the X-axis direction, for example.
  • the effective concentration of p-type impurities in connection region 18 may be approximately the same as the effective concentration of p-type impurities in electric field relaxation region 17 .
  • the effective concentration of p-type impurities in the connection region 18 is, for example, 5 ⁇ 10 17 cm ⁇ 3 or more and 5 ⁇ 10 18 cm ⁇ 3 or less.
  • the first region 13A of the drift region 13 is located between the body region 14 and the electric field relaxation region 17.
  • the first region 13A is in contact with the body region 14 and the electric field relaxation region 17.
  • the first region 13A is closer to the first main surface 10A than the electric field relaxation region 17 is.
  • the second region 13B is closer to the second main surface 10B than the first region 13A.
  • the second region 13B is continuous with the first region 13A.
  • the second region 13B contacts the electric field relaxation region 17 in a direction parallel to the second main surface 10B.
  • the second region 13B and the electric field relaxation region 17 may be located on the same plane parallel to the second main surface 10B.
  • the effective concentration of n-type impurities in the second region 13B may be higher than the effective concentration of n-type impurities in the first region 13A.
  • the third region 13C is closer to the second main surface 10B than the second region 13B.
  • the third region 13C is continuous with the second region 13B.
  • the third region 13C contacts the electric field relaxation region 17.
  • the third region 13C is closer to the second main surface 10B than the electric field relaxation region 17 is.
  • Third region 13C may be between second region 13B and silicon carbide single crystal substrate 11.
  • Third region 13C may be continuous with silicon carbide single crystal substrate 11.
  • the effective concentration of n-type impurities in the third region 13C may be the same as the effective concentration of n-type impurities in the second region 13B.
  • the gate insulating film 21 is, for example, an oxide film.
  • the gate insulating film 21 is made of a material containing silicon dioxide, for example.
  • the gate insulating film 21 is in contact with the side surfaces 3 and the bottom surface 4.
  • the gate insulating film 21 contacts the first region 13A at the bottom surface 4.
  • the gate insulating film 21 contacts the source region 15, the body region 14, and the first region 13A at the side surface 3.
  • Gate insulating film 21 may be in contact with source region 15 on first main surface 10A.
  • the gate wiring 22 is provided on the gate insulating film 21.
  • the gate wiring 22 is made of, for example, polysilicon containing conductive impurities.
  • Gate wiring 22 is provided inside gate trench 5 . A portion of the gate wiring 22 may be provided on the first main surface 10A.
  • the interlayer insulating film 23 covers the gate wiring 22.
  • the interlayer insulating film 23 is in contact with the gate wiring 22 and the gate insulating film 21 .
  • the interlayer insulating film 23 is, for example, an oxide film.
  • the interlayer insulating film 23 is made of a material containing silicon dioxide, for example. Interlayer insulating film 23 electrically insulates gate wiring 22 and source electrode 30 from each other. A part of the interlayer insulating film 23 may be provided inside the gate trench 5.
  • a contact hole 24 is formed in the interlayer insulating film 23 and the gate insulating film 21.
  • Contact holes 24 are provided at regular intervals in the Y-axis direction. The contact holes 24 are provided so that the gate trench 5 is located between the contact holes 24 adjacent in the Y-axis direction when viewed in plan from a direction perpendicular to the first main surface 10A.
  • Contact hole 24 extends along the X-axis direction. Source region 15 and contact region 16 are exposed from interlayer insulating film 23 and gate insulating film 21 through contact hole 24 . The contact regions 16 do not need to be provided over the entire area in the X-axis direction, and may be provided periodically.
  • a barrier metal film may be formed to cover the upper surface and side surfaces of the interlayer insulating film 23 and the side surfaces of the gate insulating film 21.
  • the source electrode 30 is in contact with the first main surface 10A.
  • the source electrode 30 has a contact electrode 31 and a source wiring 32.
  • the contact electrode 31 contacts the source region 15 and the contact region 16 on the first main surface 10A.
  • the contact electrode 31 is made of a material containing, for example, nickel silicide (NiSi).
  • Contact electrode 31 may be made of a material containing titanium, aluminum, and silicon. Contact electrode 31 makes an ohmic contact with contact region 16 .
  • the source wiring 32 covers the upper surface and side surfaces of the interlayer insulating film 23 and the upper surface of the contact electrode 31.
  • the source wiring 32 is in contact with the contact electrode 31.
  • the source wiring 32 is made of a material containing aluminum, for example.
  • the drain electrode 40 is in contact with the second main surface 10B. Drain electrode 40 contacts silicon carbide single crystal substrate 11 at second main surface 10B. Drain electrode 40 is electrically connected to drift region 13 .
  • the drain electrode 40 is made of a material containing, for example, nickel silicide. Drain electrode 40 may be made of a material containing titanium, aluminum, and silicon. Drain electrode 40 makes an ohmic contact with silicon carbide single crystal substrate 11 .
  • the gate runner 51 is provided on the positive side of the X-axis relative to the plurality of gate wirings 22. Gate runner 51 extends along the Y-axis direction. The gate runner 51 electrically connects the first gate wiring 22a and the gate pad 60. The gate runner 51 is electrically connected to the end of the first gate wiring 22a on the positive side of the X-axis.
  • the charging current flows from the positive side of the X-axis toward the negative side of the X-axis, as shown by the arrows in FIGS. 2 and 4.
  • the discharge current flows from the negative side of the X-axis toward the positive side of the X-axis.
  • the gate runner 51 is made of a material with lower electrical resistivity than the gate wiring 22.
  • the gate runner 51 is made of a material containing aluminum or copper, for example.
  • Gate runner 51 may be made of a material containing aluminum and copper.
  • the gate runner 51 is an example of a first connection wiring.
  • the gate runner 52 is provided on the negative side of the X-axis relative to the plurality of gate wirings 22.
  • the gate runner 52 extends along the Y-axis direction.
  • the gate runner 52 is arranged with a plurality of gate wirings 22 interposed between it and the gate runner 51.
  • the gate runner 52 electrically connects the second gate wiring 22b and the gate pad 60.
  • the gate runner 52 is electrically connected to the end of the second gate wiring 22b on the negative side of the X-axis. In this case, the charging current flows from the negative side of the X-axis toward the positive side of the X-axis as shown by the arrows in FIGS. 2 and 5.
  • Gate runner 52 is made of the same material as gate runner 51.
  • the gate runner 52 is an example of the second connection wiring.
  • the gate pad 60 is provided on the positive side of the Y-axis relative to the plurality of gate wirings 22.
  • the gate pad 60 may be provided on the negative side of the Y-axis with respect to the plurality of gate wirings 22.
  • Gate pad 60 has, for example, a rectangular shape.
  • Gate pad 60 is made of a material containing aluminum or copper, for example.
  • Gate pad 60 may be constructed from a material including aluminum and copper.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

L'invention concerne une puce semi-conductrice (1) qui comprend une pluralité de cellules de transistor (100) disposées côte à côte le long d'une première direction (Y), les cellules de transistor comprenant des fils de grille (22a, 22b) s'étendant le long d'une seconde direction (X) orthogonale à la première direction, les fils de grille étant disposés de telle sorte qu'une inductance mutuelle générée entre les fils de grille des cellules de transistor adjacentes est une valeur négative.
PCT/JP2022/046592 2022-05-19 2022-12-19 Puce semi-conductrice WO2023223589A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2022082046 2022-05-19
JP2022-082046 2022-05-19

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Publication Number Publication Date
WO2023223589A1 true WO2023223589A1 (fr) 2023-11-23

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2016046900A1 (fr) * 2014-09-24 2016-03-31 新電元工業株式会社 Dispositif à semiconducteur de carbure de silicium, procédé de fabrication de dispositif à semiconducteur de carbure de silicium et procédé de conception de dispositif à semiconducteur de carbure de silicium
JP2017163136A (ja) * 2016-02-29 2017-09-14 インフィネオン テクノロジーズ オーストリア アクチエンゲゼルシャフト ダブルゲートトランジスタ素子及び動作方法
JP2019062737A (ja) * 2018-11-19 2019-04-18 株式会社デンソー 駆動装置
JP2019169597A (ja) * 2018-03-23 2019-10-03 株式会社東芝 半導体装置
JP2021002620A (ja) * 2019-06-24 2021-01-07 富士電機株式会社 半導体装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2016046900A1 (fr) * 2014-09-24 2016-03-31 新電元工業株式会社 Dispositif à semiconducteur de carbure de silicium, procédé de fabrication de dispositif à semiconducteur de carbure de silicium et procédé de conception de dispositif à semiconducteur de carbure de silicium
JP2017163136A (ja) * 2016-02-29 2017-09-14 インフィネオン テクノロジーズ オーストリア アクチエンゲゼルシャフト ダブルゲートトランジスタ素子及び動作方法
JP2019169597A (ja) * 2018-03-23 2019-10-03 株式会社東芝 半導体装置
JP2019062737A (ja) * 2018-11-19 2019-04-18 株式会社デンソー 駆動装置
JP2021002620A (ja) * 2019-06-24 2021-01-07 富士電機株式会社 半導体装置

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