WO2023223337A1 - Pmma gate dielectric based patterned bottom-gate bottom contact type organic thin film transistor - Google Patents

Pmma gate dielectric based patterned bottom-gate bottom contact type organic thin film transistor Download PDF

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WO2023223337A1
WO2023223337A1 PCT/IN2023/050394 IN2023050394W WO2023223337A1 WO 2023223337 A1 WO2023223337 A1 WO 2023223337A1 IN 2023050394 W IN2023050394 W IN 2023050394W WO 2023223337 A1 WO2023223337 A1 WO 2023223337A1
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layer
pmma
resist
thin film
film transistor
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PCT/IN2023/050394
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French (fr)
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Anuj RAJPOOT
Soumya Dutta
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INDIAN INSTITUTE OF TECHNOLOGY MADRAS (IIT Madras)
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Publication of WO2023223337A1 publication Critical patent/WO2023223337A1/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having a potential-jump barrier or a surface barrier
    • H10K10/40—Organic transistors
    • H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
    • H10K10/462—Insulated gate field-effect transistors [IGFETs]
    • H10K10/468—Insulated gate field-effect transistors [IGFETs] characterised by the gate dielectrics
    • H10K10/471—Insulated gate field-effect transistors [IGFETs] characterised by the gate dielectrics the gate dielectric comprising only organic materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having a potential-jump barrier or a surface barrier
    • H10K10/80—Constructional details
    • H10K10/82—Electrodes
    • H10K10/84—Ohmic electrodes, e.g. source or drain electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/621—Providing a shape to conductive layers, e.g. patterning or selective deposition
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K85/00—Organic materials used in the body or electrodes of devices covered by this subclass
    • H10K85/10—Organic polymers or oligomers
    • H10K85/111—Organic polymers or oligomers comprising aromatic, heteroaromatic, or aryl chains, e.g. polyaniline, polyphenylene or polyphenylene vinylene
    • H10K85/113—Heteroaromatic compounds comprising sulfur or selene, e.g. polythiophene

Definitions

  • the present invention generally relates to thin-film transistors (TFTs). More Particularly, it relates to organic TFTs or solution-processed organic TFTs (hereafter referred to as OTFTs), employing pristine poly-(methyl-methacrylate) (PMMA) and/or PMMA based hybrid/blended and multi-layer dielectric (hereafter referred to as PMMA layer) layer as a gate dielectric layer.
  • OTFTs organic TFTs or solution-processed organic TFTs
  • PMMA poly-(methyl-methacrylate)
  • PMMA layer multi-layer dielectric
  • the present invention also relates to the manufacturing method of PMMA-based OTFTs with sub- 10pm or sub-pm channel length and gate overlap (hereafter referred to as miniaturized OTFTs) using the bi-layer resist approach of photolithographic patterning (hereafter referred to as bi-layer lithography).
  • the OTFT technology offers significant advantages such as low-cost fabrication and flexibility over the conventional TFT technologies such as poly-crystalline or amorphous silicon (a-Si) TFT technology for attractive applications like flexible displays, low-cost back-plane, and logic circuits (see X. Guo et. Al., IEEE Transactions on Electron Devices, vol. 64, no. 5, pp. 1906-1921, 2017).
  • the low process temperature typically less than 200°C for solution-processed organic semiconductors and polymer gate dielectrics, facilitates the use of plastic substrates like PEN and PET substrates which are ideal for flexible and low-cost electronics.
  • Solution-processed organic semiconductors and polymer gate dielectrics are essential to avail full advantage of the low cost and low-temperature processing of OTFT technology.
  • a good quality polymer gate dielectric and an easily scalable device architecture are essential for facilitating photolithography to achieve device scaling.
  • channel length (L) and gate overlap (L ov ) scaling using photolithography can play a vital role in improving the performance of solution-processed OTFTs for faster logic and driver circuit applications (see A. a. Zakhidov et. Al., Applied Physics Letters, vol. 99, no. 18, p. 183308, 2011).
  • Photo-lithography is a process that enables micron-scale patterning of a thin film or the bulk of a substrate. It uses light to transfer a geometric pattern from a photomask to a light-sensitive chemical photoresist on the substrate.
  • PMMA poly-(methyl- methacrylate)
  • PMMA acts as a promising host matrix to realize composite and hybrid dielectrics with embedded inorganic components (see L. Shang et. Al. , IEEE Transactions on Electron Devices, vol. 56, no. 3, pp. 370-376, 2009).
  • the bottom-gate bottom-contact (BG-BC) OTFT structure is the most preferred device structure (see X. Guo et al., IEEE Transactions on Electron Devices, vol. 64, no. 5, pp. 1906-1921, 2017) among all the possible OTFT configurations described as top-gate top-contact (TG-TC), bottom-gate bottom-contact (BG-BC), top-gate bottomcontact (TG-BC), and bottom-gate top-contact (BG-TC). It offers the benefits of both bottom-gate and bottom-contact configurations for easy photolithography and low-cost process integration. [0008] In botom-gate configuration, the organic semiconductor layer deposition comes after the gate electrode and gate dielectric layer (see F. M. Li et. al.
  • the source and drain electrodes can be realized using photolithography over the already deposited gate dielectric layer.
  • the BG-BC configuration provides greater flexibility in selecting the paterning and deposition methods for various device layers (see Y. Wen et. Al., Chemical Reviews, 111 (5), pp. 3358-3406, 2011).
  • United States Patent 8829494 to Cambridge Display Technology titled “Organic thin film transistor” discloses an organic thin film transistor and a method of manufacturing the same.
  • the organic thin film transistor comprises source and drain electrodes, an organic semiconductor disposed in a channel region between the source and drain electrodes, a gate electrode, and a dielectric disposed between the source and drain electrodes and the gate electrode.
  • Korean Patent 102450399 to Samsung Electronics Co., Ltd. titled “Thin film transistor, method of manufacturing same, and electronic device including thin same” relates to a thin film transistor which includes a gate electrode, a semiconductor which overlaps the gate electrode, a gate insulator located between the gate electrode and the semiconductor, and a source electrode and a drain electrode electrically connected to the semiconductor, the gate insulator includes an inorganic insulation film located on the gate electrode and an organic insulation film located on the semiconductor.
  • I. Mejia (see I. Mejia et. Al., Microelectron. Reliab., vol. 48, no. 11-12, pp. 1795-1799, 2008) showed the possibility of fabricating photo-lithographically patterned TG-BC OTFTs by etching the already deposited metal layer on PMMM.
  • the process is compatible only with the TG-BC OTFTs because the deposited metal layer protects the gate dielectric during the photolithography. Meanwhile, the process may damage or contaminate the dielectric-semiconductor or metal-semiconductor interface in BG-BC, BG-TC, and TG- TC device configurations.
  • the primary objective of the present invention is to provide a manufacturable process to produce high-performance organic thin-fdm transistors (OTFTs) employing PMMA based dielectrics as a gate dielectric.
  • OTFTs organic thin-fdm transistors
  • Another objective of the present invention is to provide a manufacturable process to produce miniaturized solution-processed PMMA gate dielectric -based organic thin-fdm transistors in the BG-BC configuration.
  • Yet another objective of the present invention is to provide a more readily manufacturable process for higher performance organic thin-film transistors, comprising the PMMA gate dielectric layer and at least the bottom gate and bottom source and drain electrodes, with a thin film semiconductor layer more specifically but not limited to the organic semiconductor layer formed over the bottom source and drain electrodes.
  • Still another objective of the present invention is to provide a more readily manufacturable process for thin-film transistors employing the PMMA layer as an insulating gate layer that can cater to large-area circuits.
  • Yet another objective of the present invention is to provide a method to perform photolithography to realize the patterned sub- 10pm and sub-pm size features over PMMA gate dielectric as a conductive source and drain electrodes when not employing any chemical modification like cross-linking, photo-cross-linking, chemical wet etching or using capping layer.
  • Yet another objective of the present invention is to provide optimized photolithography process steps, which result in no physical or electrical degradation of PMMA gate dielectric during the fabrication of thin-film transistors.
  • Yet another objective of the present invention is to provide an optimized low- temperature process to produce thin-film transistors using bi-layer lithography over the PMMA gate dielectric layer to facilitate flexible substrates in various applications.
  • isopropyl alcohol is used as a resist stripper during the lift-off process.
  • TMAH tetramethyl ammonium hydroxide
  • the present invention discloses an organic thin fdm transistor and a method for manufacturing the same using conventional UV/deep-UV lithography using a bi-layer resist stack.
  • an organic thin film transistor comprising: a rigid or flexible substrate having a first side and a second side, wherein the substrate is selected from glass, Si/SiCE, flexible metal sheet preferably stainless steel, aluminum or flexible plastic substrate specifically a PET or, a PEN substrate; an electrically conducting gate electrode, being positioned in the bottom gate configuration over the substrate wherein the bottom of the gate electrode facing the first side of the substrate; a pristine poly-(methyl- methacrylate) (PMMA) or PMMA based dielectric as gate dielectric layer, being positioned over the top of the electrically conducting gate electrode, wherein the bottom of the gate dielectric layer facing the first side of the substrate; a photolithographically patterned electrically conducting source and drain electrodes, being positioned over the top of the gate dielectric layer in the bottom-contact configuration over the substrate, wherein the bottom of the electrically conducting source and drain electrodes facing the first side of the substrate; and a semiconducting layer, being positioned over the top of the source and drain electrode
  • a method for manufacturing the thin film transistor by performing conventional UV/deep-UV lithography using a bi-layer resist stack comprising the steps of: a. forming a photo-lithographically patterned electrically conducting gate electrode; b. forming pristine PMMA or PMMA based dielectric layer on top of electrically conducting gate electrode; c. forming a bi-layer resist stack over the pristine PMMA or PMMA based dielectric layer prepared in step (b), wherein the bi-layer resist stack comprising:
  • a thin upper resist layer deposited on top of the bottom-resist layer by spin coating d. exposing the bi-layer resist stack to the suitable UV or deep-UV radiation through a photomask; e. developing the exposed bi-layer resist stack using a compatible developer to form photolithographically patterned source and drain electrode structures; f. depositing an electrically conducting layer for source and drain electrodes over the patterned structures; g. performing lift-off of the electrically conducting source and drain electrode layer and top-resist layer using a suitable photoresist stripper to realize photolithographically patterned electrically conducting source and drain electrodes; h. removing the bottom-resist layer using the compatible developer followed by DI water cleaning; i. preferably performing surface treatment of patterned source and drain electrodes; and j. forming the semiconducting layer, being positioned over the top of the photolithographically patterned electrically conducting source and drain electrodes.
  • FIG. 1 represents a schematic of atypical traditional miniaturized BG-BC type OTFT
  • FIG. 2 illustrates the schematic of a miniaturized BG-BC type OTFT with PMMA gate dielectric layer according to present invention
  • FIG. 3 A represents a schematic of formation of the photolithographically patterned gate electrode 22
  • FIG. 3B represents a schematic of deposition of PMMA gate dielectric layer 23 on the substrate 21;
  • FIG. 3C represents a schematic of formation of methacrylic-polymer based resist especially polyglutarimide or poly-(dimethylglutarimide) based bottom resist layer 31 over PMMA gate dielectric 23;
  • FIG. 3D represents a schematic of formation of the top resist layer MICROPOSIT S1800 series photo-resist 32 over the bottom resist layer 31;
  • FIG. 3E represents a schematic of exposing the formed bi-layer resist stack using suitable radiation such as UV/ deep-UV radiation through a photomask;
  • FIG. 3F represents a schematic of pattern formation after developing the exposed bi-layer resist-stack of layer 31 and 32 employing tetra methyl ammonium hydroxide based developer;
  • FIG. 3G represents a schematic of patterned bi-layer resist-stack of layer 31 and 32 with deposited metal layer 33 over it;
  • FIG. 3H represents a schematic of formation of photolithographically patterned metal features achieved by lift-off of the deposited metal 33 and top-resist layer 32 using isopropyl -alcohol, leaving bottom -resist layer 31;
  • FIG. 31 illustrate patterned laterally spaced source and drain electrodes 24 and 25 and other desired metal patterns over PMMA Layer 23 after removal of the bottom -resist layer 31 ;
  • FIG. 3J illustrates a schematic of formation of the thin film of the preferred semiconductor layer 26 over photo-lithographically patterned source and drain electrodes 24 and 25;
  • the present invention discloses an organic thin-fdm transistor with a PMMA gate dielectric layer and provides process steps to realize three-dimensional sub- 10pm or sub-pm features as a conductive source and drain electrodes over the above-specified gate dielectric layer.
  • a thin film transistor comprising: a rigid or flexible substrate having a first side and a second side, wherein the substrate is selected from glass, Si/SiO2, flexible metal sheet preferably stainless steel, aluminum or flexible plastic substrate specifically a PET or, a PEN substrate; an electrically conducting gate electrode, being positioned in the bottom gate configuration over the substrate wherein the bottom of the gate electrode facing the first side of the substrate; a pristine poly-(methyl -methacrylate) (PMMA) or PMMA based dielectric as gate dielectric layer, being positioned over the top of the electrically conducting gate electrode, wherein the bottom of the gate dielectric layer facing the first side of the substrate; a photolithographically patterned electrically conducting source and drain electrodes, being positioned over the top of the gate dielectric layer in the bottom-contact configuration over the substrate, wherein the bottom of the electrically conducting source and drain electrodes facing the first side of the substrate; and a semiconducting layer, being positioned over the top of the source and drain
  • the electrically conducting gate electrode, electrically conducting source and drain electrodes are photo-lithographically patterned and comprises a conducting polymer selected from the group comprising PEDOTPSS, a stable metal such as gold, but not limited to it, a metal alloy, or a conducting oxide such as indium tin oxide, preferably a stable metal but not limited to it.
  • a conducting polymer selected from the group comprising PEDOTPSS, a stable metal such as gold, but not limited to it, a metal alloy, or a conducting oxide such as indium tin oxide, preferably a stable metal but not limited to it.
  • the PMMA layer as gate dielectric layer being deposited by methods such as spin coating, chemical vapour deposition, plasma polymerization, thermal deposition, RF sputtering and DC sputtering for a large area.
  • the electrically conducting source and drain electrodes are photolithographically patterned using the bi-layer lithography, as disclosed in the Indian Patent No. 384333 entitled “Bi-layer resist approach of photolithographic patterning over PMMA based polymer dielectrics” which deals with the bi-layer stack of a methacrylic- polymer based resist and a typical g-line, i-line, broadband, deep UV, and 193nm (positive or negative tone) photoresist.
  • the bi-layer lithography includes a bi-layer resist stack for performing conventional UV/Deep-UV lithography over pristine PMMA or PMMA based dielectric layer, comprising: a) a thick bottom-resist layer deposited directly over pristine PMMA or PMMA based dielectric layer, and b) a thin upper resist layer deposited on top of the bottom-resist layer.
  • the thick bottom-resist layer in the bi-layer resist stack is chemically compatible with the pristine PMMA or PMMA-based dielectric layer.
  • the thick bottom-resist layer is a methacrylic-polymer based resist, preferably polyglutarimide or poly-(dimethylglutarimide) based resist obtained through imidization of PMMA.
  • the thick bottom -resist layer is a polymethylglutarimide
  • the upper resist layer is a g-line, i-line, broadband, deep UV, or 193nm (positive or negative tone) photoresist, preferably MICROPOSIT 's SI 800 series photoresist.
  • the semiconducting layer is made of an inorganic semiconductor material such as amorphous-silicon, an organic semiconductor material such as DPP-DTT (Poly[[2,3,5,6-tetrahydro-2,5-bis(2-octyldodecyl)-3,6- dioxopyrrolo[3,4-c]pyrrole-l,4-diyl]-2,5-thiophenediylthieno[3,2 b]thiophene-2,5-diyl- 2,5-thiophenediyl]), or an oxide semiconductor material such as IGZO (Indium gallium zinc oxide), more preferably an organic polymer semiconductor such as P3HT (Poly(3- hexylthiophene-2, 5 -diyl)) .
  • DPP-DTT Poly[[2,3,5,6-tetrahydro-2,5-bis(2-octyldodecyl)-3,6- dioxopyrrolo[
  • a method for manufacturing the thin film transistor by performing conventional UV/deep-UV lithography using a bi -layer resist stack comprising the steps of: a. forming a photo-lithographically patterned electrically conducting gate electrode; b. forming pristine PMMA or PMMA based dielectric layer on top of electrically conducting gate electrode; c. forming a bi-layer resist stack over the pristine PMMA or PMMA based dielectric layer prepared in step (b), wherein the bi-layer resist stack comprising:
  • a thin upper resist layer deposited on top of the bottom-resist layer by spin coating d. exposing the bi-layer resist stack to the suitable UV or deep-UV radiation through a photomask; e. developing the exposed bi-layer resist stack using a compatible developer to form photolithographically patterned source and drain electrode structures; f. depositing an electrically conducting layer for source and drain electrodes over the patterned structures; g. performing lift-off of the electrically conducting source and drain electrode layer and top-resist layer using a suitable photoresist stripper to realize photolithographically patterned electrically conducting source and drain electrodes; h. removing the bottom-resist layer using the compatible developer followed by DI water cleaning; i. preferably performing surface treatment of patterned source and drain electrodes; and j. forming the semiconducting layer, being positioned over the top of the photolithographically patterned electrically conducting source and drain electrodes.
  • the thick bottom-resist layer is annealed more preferably at 115°C temperature.
  • the developer is based on tetra methyl ammonium hydroxide (TMAH), preferably MICROPOSIT MF-319 or MF-321.
  • TMAH tetra methyl ammonium hydroxide
  • the photoresist stripper used is isopropyl alcohol and it is maintained at a temperature during the metal lift-off, more preferably in the temperature range of 35 °C to 55 °C.
  • the surface treatment of patterened source and drain electrodes improves the carrier transport at the interface between the source and drain electrodes and the semiconductor layer.
  • the present invention is a method with optimized process steps to fabricate/ manufacture high-performance miniaturized OTFTs with PMMA gate dielectric layer with patterned source and drain electrodes, which are realized using the novel bi-layer lithography in the BG-BC configuration.
  • the novel bi-layer lithography enables conventional photolithography employing conventional resists, organic developers, and stripper solvents directly over the PMMA layer. It involves the process steps which result in no physical and electronic degradation of the PMMA layer during the entire process and facilitates easy implementation of widely used photolithography over PMMA.
  • bi-layer lithography reduces the complexity of scaling OTFTs with PMMA gate dielectric. It delivers cost-effectiveness in manufacturing high-performance miniaturized OTFTs with PMMA gate dielectric because of their low-temperature process steps and the use of conventional photoresists/developers during photolithography.
  • a typical traditional miniaturized BG-BC type OTFT includes a lithographically patterned gate electrode 12 over a chosen substrate 11, a gate insulator 13 composed of a dielectric medium facilitating photolithography atop of it, an organic semiconductor fdm, more specifically a solution-processed organic semiconductor film 13 selected from either an organic polymeric semiconductor material or an organic molecular semiconductor material, and two laterally spaced photolithographically patterned conductive strips 14 and 15 made of stable metal, a metal alloy, or a transparent conductor such as indium-tin-oxide, as a source and a drain electrode.
  • Organic polymer gate dielectrics are essential for low-cost and flexible organic electronic applications offering key advantages such as solution processability, mechanical flexibility, and low-temperature processing.
  • Conventional miniaturized BG-BC type OTFTs (e.g., TFT 10) generally include a gate dielectric 13 such as SiO x , SiN x , A1O X , or organic polymeric dielectric medium, preferably cross-linked PVP, cytop, or parylene-c enabling the paterning of the source and drain electrodes using conventional photolithography on top of these gate insulator 13.
  • FIG. 2 illustrates a miniaturized OTFT configuration according to the present invention.
  • the TFT 20 comprises a substrate 21 in contact with the paterned gate electrode 22, comprising a PMMA gate dielectric 23, two lithographically paterned laterally spaced source and drain electrodes 24 and 25 made of stable metal, a metal alloy, or a transparent conductor such as indium-tin-oxide fabricated using bi-layer lithography, and a semiconductor film, more specifically a solution-processed organic semiconductor film 26 selected from either an organic polymeric semiconductor material or an organic molecular semiconductor material.
  • the bi-layer lithography involves the formation of a bi-layer resist stack of methacrylic polymers based resists, especially polyglutarimide or poly- (dimethylglutarimide) based resists such as MicroChem' s PMGI as a botom-resist layer (the first layer of bi-layer resist stack) coated directly over PMMA dielectric layer followed by the formation of the top-resist layer (the second layer of bi-layer resist stack) of a typical g-line, i-line, broadband, deep UV, and 193nm (positive or negative tone) photoresist by spin coating method.
  • the method is a low-temperature process and facilitates the easy liftoff of deposited metal layers.
  • the poly-(dimethylglutarimide) based botom-resist layers such as PMGI or LOR, are compatible with conventional g-line, i-line, broadband, deep UV, 193nm, and e- beam photoresists, for example, MICROPOSIT S 1813 positive photoresist and PMMA (e- beam photoresist).
  • the poly-(dimethylglutarimide) based resists are resistant to general solvents and less susceptible to intermixing with other polymers or resists when stacked.
  • the photolithographically patterned gate electrode 22 made of stable metal, a metal alloy, or a transparent conductor such as indium-tin-oxide on a rigid/flexible substrate 21 made of a material such as glass, Si/SiO2, aluminum foil, or a plastic substrate (PET, PEN substrates), as shown in FIG. 3A.
  • PMMA gate dielectric layer 23 over the patterned gate electrode 22 by a suitable method such as plasma polymerization, thermal deposition, RF sputtering, DC sputtering, etc., more specifically by spin coating covering the entire active circuit region, as shown in FIG. 3B.
  • a suitable method such as plasma polymerization, thermal deposition, RF sputtering, DC sputtering, etc., more specifically by spin coating covering the entire active circuit region, as shown in FIG. 3B.
  • bi-layer resists stack over the deposited PMMA gate dielectric layer by spin coating the first layer of bi-layer resist stack 31 as a relatively thick methacrylic- polymer based resist, especially polyglutarimide or poly-(dimethylglutarimide), more specifically MicroChem's PMGI, followed by annealing of the formed film 31 at a temperature in the range of 70°C to 150°C, more specifically, annealing MicroChem's PMGI bottom-resist layer 31 at 115°C temperature, as shown in FIG. 3C. 4.
  • methacrylic- polymer based resist especially polyglutarimide or poly-(dimethylglutarimide)
  • MicroChem's PMGI more specifically MicroChem's PMGI
  • top-resist layer 32 by spin coating (also the second layer of bi-layer resist stack) over the deposited and annealed bottom-resist layer 31 as a conventional g-line, i-line, broadband, deep UV, 193nm (positive or negative tone) photoresist, more specifically MICROPOSIT SI 800 series photoresist such as MICROPOSIT S 1813 coated on top of the bottom -resist layer prepared in the earlier step, as shown in FIG. 3D.
  • spin coating also the second layer of bi-layer resist stack
  • MICROPOSIT SI 800 series photoresist such as MICROPOSIT S 1813 coated on top of the bottom -resist layer prepared in the earlier step, as shown in FIG. 3D.
  • tetramethylammonium hydroxide based developers such as MICROPOSIT MF-319, as shown in FIG. 3F.
  • the tetramethylammonium hydroxide (TMAH) based developers such as MICROPOSIT MF319 can be used without causing any physical or electrical degradation of the PMMA gate dielectric layer 23.
  • the developer is used for developing both the top and bottom-resist layers.
  • metal layer 33 preferably but not limited to, of stable metal, a metal alloy, or a transparent conductor such as indium-tin-oxide over the patterned bi-layer resist stack to realize two lithographically patterned laterally spaced source and drain electrodes 24 and 25, as shown in FIG. 3G.
  • Lift-off of the deposited metal layer 33 is done by employing isopropyl alcohol as a top photoresist layer stripper to achieve the patterned laterally spaced source and drain electrodes 24 and 25, as shown in FIG. 3H.
  • PMMA layer 23 is susceptible to most organic solvents, including acetone, making stripping a developed photoresist difficult.
  • isopropyl alcohol does not interact with the bottom-resist layer 31.
  • Isopropyl alcohol is a very weak solvent for the low molecular weight PMMA and is known as a non-solvent for high molecular weight PMMA such as 950K or 495K PMMA.
  • the bottom-resist layer 31 acts as a barrier between the PMMA layer 23 and isopropyl alcohol.
  • the temperature of isopropyl alcohol is maintained at sufficient temperature, more preferably at a temperature in the range of 35 °C to 55°C, to enhance the reactivity of isopropyl alcohol in order to enable the stripping of the top photoresist layer.
  • the exposed bottom-resist layer 31 in the remaining channel region and other active regions is removed by using the tetramethylammonium hydroxide (TMAH) based developer solutions such as MICROPOSIT MF319, leaving only the patterned laterally spaced source and drain electrodes 24 and 25 and other desired metal patterns over PMMA Layer 23 without dissolving or damaging the PMMA layer 23, as shown in FIG. 31.
  • TMAH tetramethylammonium hydroxide
  • HMDS hexamethyldisilazane
  • thiol compounds such as 1 -octadecane.
  • the deposition of preferred semiconductor layer can be performed by using a suitable method such as plasma polymerization, thermal deposition, RF sputtering and DC sputteringmore specifically by spin coating covering the entire active circuit region.
  • 10pm channel lengths and constant channel width-to-length ration (W/L) of 500 in the BG- BC configuration were fabricated according to the invention with a configuration illustrated in FIG. 2.
  • the OTFTs with the channel length of 2pm and 4pm are demonstrated in the example work by performing photolithography on pristine PMMA according to the invention.
  • FIG. 3A A blanket layer of 450nm pristine PMMA solution in anisole (60mg/ml) was spin- coated, followed by annealing at 120°C, as illustrated in FIG. 3B.
  • FIG. 3D on top of the PMGI layer to form the top-resist layer
  • prebake the bi-layer is exposed to UV (FIG. 3E) through the mask plate using the Karl- Suss mask aligner.
  • An exposed bi-layer resist-stake was developed (FIG. 3F) using MICROPOSIT MF319 (tetramethylammonium -hydroxide based developer) without experiencing any physical or chemical degradation of the PMMA layer.
  • FIG. 3G and FIG. 3H the evaporation of the source and drain metal electrodes for which we have deposited Cr/Au by thermal evaporation followed by lift-off is illustrated in FIG. 3G and FIG. 3H, respectively.
  • IPA is used as a photoresist stripper during lift-off (FIG. 3H).
  • One of the key advantages of employing the bi-layer resist structure is that it facilitates the easy lift-off using IPA.
  • the bottom-resist layer was removed by MF319 exposure for 20 seconds, followed by DI water cleaning, as illustrated in FIG. 31.
  • RR-P3HT Sigma Aldrich
  • thin films were prepared by spin-coating from dichlorobenzene (DCB) solution (5 mg/ml) on top of already patterned source and drain metal electrodes, as illustrated in FIG. 3J.
  • the characterization of the fabricated OTFT based on P3HT and PMMA gate dielectric shows the apparent p-type enhancement-mode behavior.
  • the output characteristics of the 2pm and 4pm channel length device with a W/L ratio of 500 are shown in FIG. 4 and FIG. 5.
  • the saturation mobility of 3.8x 10 cm 2 /V -s and the on/off ratio of 10 3 has been calculated from the saturation transfer characteristics of the device shown in FIG. 6.
  • the device showed a threshold voltage of 0 V and a sub-threshold swing (SS) of 1.65 V/decade.
  • SS sub-threshold swing
  • FIG. 7 shows the continuously measured transfer characteristics of the 2pm channel length OTFTs with continuous VGS sweeps up to 20 cycles in the saturation region.
  • No shift of transfer curves was observed in the saturation region with the IDS at the 10 th and 20 th VGS sweep cycles which are attributed to the fact that there is no change in the switchon voltage (VON).
  • NO shift in switch-on voltage (VON) corresponding to the 10th and 20th sweep implies no event of charge injection or generation within the bulk of the gate dielectric.
  • no variation of SS between the successive sweeps rules out the formation of any additional trap states at the P3HT/PMMA interface due to gate-bias stress demonstrating the undamaged and good quality of pristine PMMA gate dielectric layer delivering excellent OTFT operational stability.
  • the present invention provides performing photolithography over PMMA and/or PMMA based hybrid/blended and bi -layer dielectric systems which facilitate the easy realization of miniaturized micron and sub-micron organic electronics devices such as PMMA gate dielectric based organic field effect transistors. Since the process does not involve any kind of pre-processing or post-processing step to treat chemically or physically the PMMA, it facilitates the solution for true low cost, easy processing and large area manufacturing of organic electronic devices using PMMA and/or PMMA based hybrid/blended and bi-layer dielectric systems.

Abstract

Disclosed are an improved PMMA gate dielectric based and miniaturized bottom-gate bottom-contact type (BG-BC) organic thin film transistor as shown in FIG. 2 and a method of manufacturing the same. The present invention comprises a pristine poly-(methyl-methacrylate) (PMMA) or PMMA based hybrid/blended and multi-layered polymer gate dielectric and photolithographically patterned source and drain electrodes over gate dielectric layer employing bi-layer lithography. The present invention provides cost effective and low temperature process steps to manufacture high performance, photo-lithographically patterned PMMA gate dielectric based bottom-gate bottom-contact type organic thin film transistor.

Description

PMMA GATE DIELECTRIC BASED PATTERNED BOTTOM-GATE BOTTOM CONTACT TYPE ORGANIC THIN FILM TRANSISTOR
FIELD OF THE INVENTION:
[0001] The present invention generally relates to thin-film transistors (TFTs). More Particularly, it relates to organic TFTs or solution-processed organic TFTs (hereafter referred to as OTFTs), employing pristine poly-(methyl-methacrylate) (PMMA) and/or PMMA based hybrid/blended and multi-layer dielectric (hereafter referred to as PMMA layer) layer as a gate dielectric layer. The present invention also relates to the manufacturing method of PMMA-based OTFTs with sub- 10pm or sub-pm channel length and gate overlap (hereafter referred to as miniaturized OTFTs) using the bi-layer resist approach of photolithographic patterning (hereafter referred to as bi-layer lithography).
BACKGROUND:
[0002] The OTFT technology offers significant advantages such as low-cost fabrication and flexibility over the conventional TFT technologies such as poly-crystalline or amorphous silicon (a-Si) TFT technology for attractive applications like flexible displays, low-cost back-plane, and logic circuits (see X. Guo et. Al., IEEE Transactions on Electron Devices, vol. 64, no. 5, pp. 1906-1921, 2017). The low process temperature, typically less than 200°C for solution-processed organic semiconductors and polymer gate dielectrics, facilitates the use of plastic substrates like PEN and PET substrates which are ideal for flexible and low-cost electronics.
[0003] Solution-processed organic semiconductors and polymer gate dielectrics are essential to avail full advantage of the low cost and low-temperature processing of OTFT technology. A good quality polymer gate dielectric and an easily scalable device architecture are essential for facilitating photolithography to achieve device scaling. [0004] Apart from material innovations, channel length (L) and gate overlap (Lov) scaling using photolithography can play a vital role in improving the performance of solution-processed OTFTs for faster logic and driver circuit applications (see A. a. Zakhidov et. Al., Applied Physics Letters, vol. 99, no. 18, p. 183308, 2011). Photo-lithography is a process that enables micron-scale patterning of a thin film or the bulk of a substrate. It uses light to transfer a geometric pattern from a photomask to a light-sensitive chemical photoresist on the substrate.
[0005] In general, photoresist processing causes severe damage to the organic polymer dielectrics resulting in poor device performance. The photolithography over polymer gate dielectrics or semiconductors has been a challenge in realizing high-performance solution- processed OTFTs due to their low resistance towards organic solvents and resists.
[0006] Among the handful of the solution-processed polymer dielectrics, poly-(methyl- methacrylate) (PMMA), owning a smooth, hydrophobic, and hydroxyl group-free surface provides reduced trap density with an excellent dielectric-semiconductor interface (see F. De Angelis et. Al., Applied Physics Letters, vol. 86, no. 20, pp. 1-3, 2005). PMMA is a low dielectric constant polymer that also has been used as a buffer layer with high-k and other polymer dielectrics such as PVA and PVP, resulting in reduced hysteresis (see Huang et al., AIP Advances 3, 052122, 2013). Due to its excellent chemo-physical and thermal properties, PMMA acts as a promising host matrix to realize composite and hybrid dielectrics with embedded inorganic components (see L. Shang et. Al. , IEEE Transactions on Electron Devices, vol. 56, no. 3, pp. 370-376, 2009).
[0007] Meanwhile, the bottom-gate bottom-contact (BG-BC) OTFT structure is the most preferred device structure (see X. Guo et al., IEEE Transactions on Electron Devices, vol. 64, no. 5, pp. 1906-1921, 2017) among all the possible OTFT configurations described as top-gate top-contact (TG-TC), bottom-gate bottom-contact (BG-BC), top-gate bottomcontact (TG-BC), and bottom-gate top-contact (BG-TC). It offers the benefits of both bottom-gate and bottom-contact configurations for easy photolithography and low-cost process integration. [0008] In botom-gate configuration, the organic semiconductor layer deposition comes after the gate electrode and gate dielectric layer (see F. M. Li et. al. , Organic Thin Film Transistor Integration: A Hybrid Approach, 2011) expending the choice of preferred semiconductor layer. Contrary to the top-contact configuration, in botom contact OTFTs, the source and drain electrodes can be realized using photolithography over the already deposited gate dielectric layer. In combination, the BG-BC configuration provides greater flexibility in selecting the paterning and deposition methods for various device layers (see Y. Wen et. Al., Chemical Reviews, 111 (5), pp. 3358-3406, 2011).
[0009] There has not been much progress in realizing miniaturized PMMA gate dielectric -based OTFTs in BG-BC configuration by employing photolithography over PMMA. Despite being an excellent polymer gate dielectric and offering several advantages over other polymer gate dielectrics, the adoption of PMMA as a gate dielectric for realizing solution-processed miniaturized OTFTs for circuit applications has been a challenge.
[0010] The incompatibility of pristine PMMA with photolithography and the lack of suitable cross-linker or chemical methods are significant limitations for advancement of BG-BC OTFT technology incorporating PMMA as a gate dielectric (Reference: T. G. Kim et. Al., Synthetic Metals, vol. 159, no. 7-8, pp. 749-753, 2009). Some of the reported methods for PMMA cross-linking pose the limitation of a controlled process environment (Reference: Noh et. Al., Org. Electron. Physics, Mater. Appl., vol. 10, no. 1, pp. 174-180, 2009), where the cross-linking requires the presence of moisture, limiting the use of organic semiconductors as most of the organic semiconductors degrade in the presence of moisture. At the same time, the other reported methods are limited to labs and require rigorous chemical processing and understanding to do the same.
[0011] However, few prior art disclose photo-lithographically paterned organic thin film transistor where PMMA can be used as dielectric/insulating material.
[0012] For example, United States Patent 8829494 to Cambridge Display Technology titled “Organic thin film transistor” discloses an organic thin film transistor and a method of manufacturing the same. The organic thin film transistor comprises source and drain electrodes, an organic semiconductor disposed in a channel region between the source and drain electrodes, a gate electrode, and a dielectric disposed between the source and drain electrodes and the gate electrode.
[0013] Korean Patent 102450399 to Samsung Electronics Co., Ltd. titled “Thin film transistor, method of manufacturing same, and electronic device including thin same” relates to a thin film transistor which includes a gate electrode, a semiconductor which overlaps the gate electrode, a gate insulator located between the gate electrode and the semiconductor, and a source electrode and a drain electrode electrically connected to the semiconductor, the gate insulator includes an inorganic insulation film located on the gate electrode and an organic insulation film located on the semiconductor.
[0014] Further, I. Mejia (see I. Mejia et. Al., Microelectron. Reliab., vol. 48, no. 11-12, pp. 1795-1799, 2008) showed the possibility of fabricating photo-lithographically patterned TG-BC OTFTs by etching the already deposited metal layer on PMMM. The process is compatible only with the TG-BC OTFTs because the deposited metal layer protects the gate dielectric during the photolithography. Meanwhile, the process may damage or contaminate the dielectric-semiconductor or metal-semiconductor interface in BG-BC, BG-TC, and TG- TC device configurations.
[0015] However, none of the prior art discloses an optimized low-temperature manufacturing process of miniaturized organic thin-film transistors (OTFTs) in most preferred BG-BC configuration by directly employing a PMMA layer.
[0016] In view of potential significance of solution processed OTFTs, it would be desirable to have a novel method to produce miniaturized BG-BC type OTFTs with PMMA based gate dielectrics with improved characteristics and operational stability. The present invention discloses such devices, and a method of making the devices employing the bi - layer lithography method. OBJECTIVES OF THE INVENTION:
[0017] The primary objective of the present invention is to provide a manufacturable process to produce high-performance organic thin-fdm transistors (OTFTs) employing PMMA based dielectrics as a gate dielectric.
[0018] Another objective of the present invention is to provide a manufacturable process to produce miniaturized solution-processed PMMA gate dielectric -based organic thin-fdm transistors in the BG-BC configuration.
[0019] Yet another objective of the present invention is to provide a more readily manufacturable process for higher performance organic thin-film transistors, comprising the PMMA gate dielectric layer and at least the bottom gate and bottom source and drain electrodes, with a thin film semiconductor layer more specifically but not limited to the organic semiconductor layer formed over the bottom source and drain electrodes.
[0020] Still another objective of the present invention is to provide a more readily manufacturable process for thin-film transistors employing the PMMA layer as an insulating gate layer that can cater to large-area circuits.
[0021] Yet another objective of the present invention is to provide a method to perform photolithography to realize the patterned sub- 10pm and sub-pm size features over PMMA gate dielectric as a conductive source and drain electrodes when not employing any chemical modification like cross-linking, photo-cross-linking, chemical wet etching or using capping layer.
[0022] Yet another objective of the present invention is to provide optimized photolithography process steps, which result in no physical or electrical degradation of PMMA gate dielectric during the fabrication of thin-film transistors. [0023] Yet another objective of the present invention is to provide an optimized low- temperature process to produce thin-film transistors using bi-layer lithography over the PMMA gate dielectric layer to facilitate flexible substrates in various applications. Also, in the present invention, isopropyl alcohol is used as a resist stripper during the lift-off process. To develop the exposed bi-layer resist-stack mentioned above, tetramethyl ammonium hydroxide (TMAH) based developers such as MICROPOSIT MF319 are used without any physical or electrical degradation of PMMA gate dielectric.
SUMMARY OF THE INVENTION:
[0024] In order to achieve the aforementioned objectives, the present invention discloses an organic thin fdm transistor and a method for manufacturing the same using conventional UV/deep-UV lithography using a bi-layer resist stack.
[0025] According to the present invention, an organic thin film transistor, comprising: a rigid or flexible substrate having a first side and a second side, wherein the substrate is selected from glass, Si/SiCE, flexible metal sheet preferably stainless steel, aluminum or flexible plastic substrate specifically a PET or, a PEN substrate; an electrically conducting gate electrode, being positioned in the bottom gate configuration over the substrate wherein the bottom of the gate electrode facing the first side of the substrate; a pristine poly-(methyl- methacrylate) (PMMA) or PMMA based dielectric as gate dielectric layer, being positioned over the top of the electrically conducting gate electrode, wherein the bottom of the gate dielectric layer facing the first side of the substrate; a photolithographically patterned electrically conducting source and drain electrodes, being positioned over the top of the gate dielectric layer in the bottom-contact configuration over the substrate, wherein the bottom of the electrically conducting source and drain electrodes facing the first side of the substrate; and a semiconducting layer, being positioned over the top of the source and drain electrodes, wherein the bottom of the semiconducting layer facing the first side of the substrate. [0026] In accordance with the present invention, a method for manufacturing the thin film transistor by performing conventional UV/deep-UV lithography using a bi-layer resist stack, comprising the steps of: a. forming a photo-lithographically patterned electrically conducting gate electrode; b. forming pristine PMMA or PMMA based dielectric layer on top of electrically conducting gate electrode; c. forming a bi-layer resist stack over the pristine PMMA or PMMA based dielectric layer prepared in step (b), wherein the bi-layer resist stack comprising:
(i) a thick bottom-resist layer deposited directly over the pristine PMMA or PMMA based dielectric layer by spin coating followed by annealing of the formed layer at a temperature in the range of 70°C to 150°C and
(ii) a thin upper resist layer deposited on top of the bottom-resist layer by spin coating; d. exposing the bi-layer resist stack to the suitable UV or deep-UV radiation through a photomask; e. developing the exposed bi-layer resist stack using a compatible developer to form photolithographically patterned source and drain electrode structures; f. depositing an electrically conducting layer for source and drain electrodes over the patterned structures; g. performing lift-off of the electrically conducting source and drain electrode layer and top-resist layer using a suitable photoresist stripper to realize photolithographically patterned electrically conducting source and drain electrodes; h. removing the bottom-resist layer using the compatible developer followed by DI water cleaning; i. preferably performing surface treatment of patterned source and drain electrodes; and j. forming the semiconducting layer, being positioned over the top of the photolithographically patterned electrically conducting source and drain electrodes.
BRIEF DESCRIPTION OF THE DRAWINGS
[0027] The objective of the present invention will now be described in more detail concerning the accompanying drawings, in which:
[0028] FIG. 1 represents a schematic of atypical traditional miniaturized BG-BC type OTFT;
[0029] FIG. 2 illustrates the schematic of a miniaturized BG-BC type OTFT with PMMA gate dielectric layer according to present invention;
[0030] FIG. 3 A represents a schematic of formation of the photolithographically patterned gate electrode 22;
[0031] FIG. 3B represents a schematic of deposition of PMMA gate dielectric layer 23 on the substrate 21;
[0032] FIG. 3C represents a schematic of formation of methacrylic-polymer based resist especially polyglutarimide or poly-(dimethylglutarimide) based bottom resist layer 31 over PMMA gate dielectric 23; [0033] FIG. 3D represents a schematic of formation of the top resist layer MICROPOSIT S1800 series photo-resist 32 over the bottom resist layer 31;
[0034] FIG. 3E represents a schematic of exposing the formed bi-layer resist stack using suitable radiation such as UV/ deep-UV radiation through a photomask;
[0035] FIG. 3F represents a schematic of pattern formation after developing the exposed bi-layer resist-stack of layer 31 and 32 employing tetra methyl ammonium hydroxide based developer;
[0036] FIG. 3G represents a schematic of patterned bi-layer resist-stack of layer 31 and 32 with deposited metal layer 33 over it;
[0037] FIG. 3H represents a schematic of formation of photolithographically patterned metal features achieved by lift-off of the deposited metal 33 and top-resist layer 32 using isopropyl -alcohol, leaving bottom -resist layer 31;
[0038] FIG. 31 illustrate patterned laterally spaced source and drain electrodes 24 and 25 and other desired metal patterns over PMMA Layer 23 after removal of the bottom -resist layer 31 ;
[0039] FIG. 3J illustrates a schematic of formation of the thin film of the preferred semiconductor layer 26 over photo-lithographically patterned source and drain electrodes 24 and 25;
[0040] FIG. 4 illustrates the output characteristics of the 2pm channel length PMMA gate dielectric based BG-BC type OTFT device with a W/L = 500;
[0041] FIG. 5 illustrates the output characteristics of the 4pm channel length PMMA gate dielectric based BG-BC type OTFT device with a W/L = 500; [0042] FIG. 6 illustrates the transfer characteristics of the 2pm channel length PMMA gate dielectric based BG-BC type OTFT device with a W/L = 500 in saturation region at VDS = 40V; and
[0043] FIG. 7 illustrates the continuously measured transfer characteristics of the 2pm channel length and W/L = 500, PMMA gate dielectric based BG-BC type OTFT device with continuous VGS sweeps up to 20 cycles in the saturation region.
DETAILED DESCRIPTION OF THE INVENTION:
[0044] The present invention discloses an organic thin-fdm transistor with a PMMA gate dielectric layer and provides process steps to realize three-dimensional sub- 10pm or sub-pm features as a conductive source and drain electrodes over the above-specified gate dielectric layer.
[0045] According to the present invention, a thin film transistor, comprising: a rigid or flexible substrate having a first side and a second side, wherein the substrate is selected from glass, Si/SiO2, flexible metal sheet preferably stainless steel, aluminum or flexible plastic substrate specifically a PET or, a PEN substrate; an electrically conducting gate electrode, being positioned in the bottom gate configuration over the substrate wherein the bottom of the gate electrode facing the first side of the substrate; a pristine poly-(methyl -methacrylate) (PMMA) or PMMA based dielectric as gate dielectric layer, being positioned over the top of the electrically conducting gate electrode, wherein the bottom of the gate dielectric layer facing the first side of the substrate; a photolithographically patterned electrically conducting source and drain electrodes, being positioned over the top of the gate dielectric layer in the bottom-contact configuration over the substrate, wherein the bottom of the electrically conducting source and drain electrodes facing the first side of the substrate; and a semiconducting layer, being positioned over the top of the source and drain electrodes, wherein the bottom of the semiconducting layer facing the first side of the substrate.
[0046] In one embodiment, the electrically conducting gate electrode, electrically conducting source and drain electrodes are photo-lithographically patterned and comprises a conducting polymer selected from the group comprising PEDOTPSS, a stable metal such as gold, but not limited to it, a metal alloy, or a conducting oxide such as indium tin oxide, preferably a stable metal but not limited to it.
[0047] In accordance with the present invention, the PMMA layer as gate dielectric layer, being deposited by methods such as spin coating, chemical vapour deposition, plasma polymerization, thermal deposition, RF sputtering and DC sputtering for a large area.
[0048] In the present invention, the electrically conducting source and drain electrodes are photolithographically patterned using the bi-layer lithography, as disclosed in the Indian Patent No. 384333 entitled “Bi-layer resist approach of photolithographic patterning over PMMA based polymer dielectrics” which deals with the bi-layer stack of a methacrylic- polymer based resist and a typical g-line, i-line, broadband, deep UV, and 193nm (positive or negative tone) photoresist.
[0049] The bi-layer lithography includes a bi-layer resist stack for performing conventional UV/Deep-UV lithography over pristine PMMA or PMMA based dielectric layer, comprising: a) a thick bottom-resist layer deposited directly over pristine PMMA or PMMA based dielectric layer, and b) a thin upper resist layer deposited on top of the bottom-resist layer.
[0050] Furthermore, the thick bottom-resist layer in the bi-layer resist stack is chemically compatible with the pristine PMMA or PMMA-based dielectric layer.
[0051] In one embodiment, the thick bottom-resist layer is a methacrylic-polymer based resist, preferably polyglutarimide or poly-(dimethylglutarimide) based resist obtained through imidization of PMMA.
[0052] In another embodiment, the thick bottom -resist layer is a polymethylglutarimide
(PMGI) resist layer, preferably PMGI or LOR resist layer. [0053] In an embodiment, the upper resist layer is a g-line, i-line, broadband, deep UV, or 193nm (positive or negative tone) photoresist, preferably MICROPOSIT 's SI 800 series photoresist.
[0054] In accordance with the present invention, the semiconducting layer is made of an inorganic semiconductor material such as amorphous-silicon, an organic semiconductor material such as DPP-DTT (Poly[[2,3,5,6-tetrahydro-2,5-bis(2-octyldodecyl)-3,6- dioxopyrrolo[3,4-c]pyrrole-l,4-diyl]-2,5-thiophenediylthieno[3,2 b]thiophene-2,5-diyl- 2,5-thiophenediyl]), or an oxide semiconductor material such as IGZO (Indium gallium zinc oxide), more preferably an organic polymer semiconductor such as P3HT (Poly(3- hexylthiophene-2, 5 -diyl)) .
[0055] According to the present inention, a method for manufacturing the thin film transistor by performing conventional UV/deep-UV lithography using a bi -layer resist stack, comprising the steps of: a. forming a photo-lithographically patterned electrically conducting gate electrode; b. forming pristine PMMA or PMMA based dielectric layer on top of electrically conducting gate electrode; c. forming a bi-layer resist stack over the pristine PMMA or PMMA based dielectric layer prepared in step (b), wherein the bi-layer resist stack comprising:
(iii) a thick bottom-resist layer deposited directly over the pristine PMMA or PMMA based dielectric layer by spin coating followed by annealing of the formed layer at a temperature in the range of 70°C to 150°C and
(iv) a thin upper resist layer deposited on top of the bottom-resist layer by spin coating; d. exposing the bi-layer resist stack to the suitable UV or deep-UV radiation through a photomask; e. developing the exposed bi-layer resist stack using a compatible developer to form photolithographically patterned source and drain electrode structures; f. depositing an electrically conducting layer for source and drain electrodes over the patterned structures; g. performing lift-off of the electrically conducting source and drain electrode layer and top-resist layer using a suitable photoresist stripper to realize photolithographically patterned electrically conducting source and drain electrodes; h. removing the bottom-resist layer using the compatible developer followed by DI water cleaning; i. preferably performing surface treatment of patterned source and drain electrodes; and j. forming the semiconducting layer, being positioned over the top of the photolithographically patterned electrically conducting source and drain electrodes.
[0056] In accordance with the method of present invention, the thick bottom-resist layer is annealed more preferably at 115°C temperature. The developer is based on tetra methyl ammonium hydroxide (TMAH), preferably MICROPOSIT MF-319 or MF-321.
[0057] According to present invention, the photoresist stripper used is isopropyl alcohol and it is maintained at a temperature during the metal lift-off, more preferably in the temperature range of 35 °C to 55 °C.
[0058] In the present invention, the surface treatment of patterened source and drain electrodes improves the carrier transport at the interface between the source and drain electrodes and the semiconductor layer. [0059] In one aspect, the present invention is a method with optimized process steps to fabricate/ manufacture high-performance miniaturized OTFTs with PMMA gate dielectric layer with patterned source and drain electrodes, which are realized using the novel bi-layer lithography in the BG-BC configuration.
[0060] The novel bi-layer lithography enables conventional photolithography employing conventional resists, organic developers, and stripper solvents directly over the PMMA layer. It involves the process steps which result in no physical and electronic degradation of the PMMA layer during the entire process and facilitates easy implementation of widely used photolithography over PMMA.
[0061] According to the present invention, bi-layer lithography reduces the complexity of scaling OTFTs with PMMA gate dielectric. It delivers cost-effectiveness in manufacturing high-performance miniaturized OTFTs with PMMA gate dielectric because of their low-temperature process steps and the use of conventional photoresists/developers during photolithography.
[0062] As illustrated in FIG. 1, a typical traditional miniaturized BG-BC type OTFT includes a lithographically patterned gate electrode 12 over a chosen substrate 11, a gate insulator 13 composed of a dielectric medium facilitating photolithography atop of it, an organic semiconductor fdm, more specifically a solution-processed organic semiconductor film 13 selected from either an organic polymeric semiconductor material or an organic molecular semiconductor material, and two laterally spaced photolithographically patterned conductive strips 14 and 15 made of stable metal, a metal alloy, or a transparent conductor such as indium-tin-oxide, as a source and a drain electrode.
[0063] Organic polymer gate dielectrics are essential for low-cost and flexible organic electronic applications offering key advantages such as solution processability, mechanical flexibility, and low-temperature processing. Conventional miniaturized BG-BC type OTFTs (e.g., TFT 10) generally include a gate dielectric 13 such as SiOx, SiNx, A1OX, or organic polymeric dielectric medium, preferably cross-linked PVP, cytop, or parylene-c enabling the paterning of the source and drain electrodes using conventional photolithography on top of these gate insulator 13.
[0064] These dielectrics are not suitable for low cost and flexible organic electronic applications due to various reasons such as non-flexibility, costly or complex deposition techniques, and most importantly, the poor organic semiconductor-dielectric interface offered by them. Meanwhile, no prior art demonstrates the fabrication of miniaturized BOES C type OTFTs with PMMA gate dielectric (13) because of the incompatibility of the PMMA with the conventional photolithography process.
[0065] FIG. 2 illustrates a miniaturized OTFT configuration according to the present invention. The TFT 20 comprises a substrate 21 in contact with the paterned gate electrode 22, comprising a PMMA gate dielectric 23, two lithographically paterned laterally spaced source and drain electrodes 24 and 25 made of stable metal, a metal alloy, or a transparent conductor such as indium-tin-oxide fabricated using bi-layer lithography, and a semiconductor film, more specifically a solution-processed organic semiconductor film 26 selected from either an organic polymeric semiconductor material or an organic molecular semiconductor material.
[0066] The bi-layer lithography involves the formation of a bi-layer resist stack of methacrylic polymers based resists, especially polyglutarimide or poly- (dimethylglutarimide) based resists such as MicroChem' s PMGI as a botom-resist layer (the first layer of bi-layer resist stack) coated directly over PMMA dielectric layer followed by the formation of the top-resist layer (the second layer of bi-layer resist stack) of a typical g-line, i-line, broadband, deep UV, and 193nm (positive or negative tone) photoresist by spin coating method. The method is a low-temperature process and facilitates the easy liftoff of deposited metal layers.
[0067] The poly-(dimethylglutarimide) based botom-resist layers such as PMGI or LOR, are compatible with conventional g-line, i-line, broadband, deep UV, 193nm, and e- beam photoresists, for example, MICROPOSIT S 1813 positive photoresist and PMMA (e- beam photoresist). The poly-(dimethylglutarimide) based resists are resistant to general solvents and less susceptible to intermixing with other polymers or resists when stacked.
[0068] These resists are also sensitive to deep-UV (240-290nm) exposure which facilitates the possibility of realizing sub-pm scale patterns over PMMA gate dielectric using bi-layer lithography. In bi-layer lithography, PMGI acts as a capping layer during the entire process while protecting the PMMA gate dielectric from unwanted exposure to conventional photoresists, developer, and stripper solvents involved in conventional photolithography.
[0069] The optimized process steps (1) to (10) for the method of manufacturing the miniaturized BG-BC type OTFTs with PMMA gate dielectric according to the present invention are as follows:
1. Formation of the photolithographically patterned gate electrode 22 made of stable metal, a metal alloy, or a transparent conductor such as indium-tin-oxide on a rigid/flexible substrate 21 made of a material such as glass, Si/SiO2, aluminum foil, or a plastic substrate (PET, PEN substrates), as shown in FIG. 3A.
2. Deposition of PMMA gate dielectric layer 23 over the patterned gate electrode 22 by a suitable method such as plasma polymerization, thermal deposition, RF sputtering, DC sputtering, etc., more specifically by spin coating covering the entire active circuit region, as shown in FIG. 3B.
3. Formation of a bi-layer resists stack over the deposited PMMA gate dielectric layer by spin coating the first layer of bi-layer resist stack 31 as a relatively thick methacrylic- polymer based resist, especially polyglutarimide or poly-(dimethylglutarimide), more specifically MicroChem's PMGI, followed by annealing of the formed film 31 at a temperature in the range of 70°C to 150°C, more specifically, annealing MicroChem's PMGI bottom-resist layer 31 at 115°C temperature, as shown in FIG. 3C. 4. Formation of a relatively thin top-resist layer 32 by spin coating (also the second layer of bi-layer resist stack) over the deposited and annealed bottom-resist layer 31 as a conventional g-line, i-line, broadband, deep UV, 193nm (positive or negative tone) photoresist, more specifically MICROPOSIT SI 800 series photoresist such as MICROPOSIT S 1813 coated on top of the bottom -resist layer prepared in the earlier step, as shown in FIG. 3D.
5. Exposure of the bi-layer resist stack to the activating radiation, more specifically to UV/deep-UV radiation such as i-line UV suitable for the top-resist layer, as shown in FIG. 3E.
6. Developing the already exposed bi-layer resist-stack of layers 31 and 32 using tetramethylammonium hydroxide based developers such as MICROPOSIT MF-319, as shown in FIG. 3F. The tetramethylammonium hydroxide (TMAH) based developers such as MICROPOSIT MF319 can be used without causing any physical or electrical degradation of the PMMA gate dielectric layer 23. The developer is used for developing both the top and bottom-resist layers.
7. Deposition of metal layer 33, preferably but not limited to, of stable metal, a metal alloy, or a transparent conductor such as indium-tin-oxide over the patterned bi-layer resist stack to realize two lithographically patterned laterally spaced source and drain electrodes 24 and 25, as shown in FIG. 3G.
8. Lift-off of the deposited metal layer 33 is done by employing isopropyl alcohol as a top photoresist layer stripper to achieve the patterned laterally spaced source and drain electrodes 24 and 25, as shown in FIG. 3H. PMMA layer 23 is susceptible to most organic solvents, including acetone, making stripping a developed photoresist difficult. During the lift-off of metal layer 33, isopropyl alcohol does not interact with the bottom-resist layer 31. Isopropyl alcohol is a very weak solvent for the low molecular weight PMMA and is known as a non-solvent for high molecular weight PMMA such as 950K or 495K PMMA.
Also, the bottom-resist layer 31 acts as a barrier between the PMMA layer 23 and isopropyl alcohol. In the process of metal lift-off using isopropyl alcohol, the temperature of isopropyl alcohol is maintained at sufficient temperature, more preferably at a temperature in the range of 35 °C to 55°C, to enhance the reactivity of isopropyl alcohol in order to enable the stripping of the top photoresist layer.
9. After lift-off of metal layer 33, the exposed bottom-resist layer 31 in the remaining channel region and other active regions is removed by using the tetramethylammonium hydroxide (TMAH) based developer solutions such as MICROPOSIT MF319, leaving only the patterned laterally spaced source and drain electrodes 24 and 25 and other desired metal patterns over PMMA Layer 23 without dissolving or damaging the PMMA layer 23, as shown in FIG. 31.
10. Formation of the thin film of the preferred semiconductor layer 26 over photo- lithographically patterned source and drain electrodes 24 and 25, with or without surface treatment by using a suitable self-assemboled monolayer of hexamethyldisilazane (HMDS) or thiol compounds such as 1 -octadecane. The deposition of preferred semiconductor layer can be performed by using a suitable method such as plasma polymerization, thermal deposition, RF sputtering and DC sputteringmore specifically by spin coating covering the entire active circuit region.
[0070] A better understanding of the embodiments of the invention may be obtained in light of the following example, which is set forth to illustrate but is not to be construed to limit the above-described embodiments. [0071] Example 1:
[0072] Organic thin-film transistors with pristine PMMA gate dielectric of varying sub-
10pm channel lengths and constant channel width-to-length ration (W/L) of 500 in the BG- BC configuration were fabricated according to the invention with a configuration illustrated in FIG. 2. The OTFTs with the channel length of 2pm and 4pm are demonstrated in the example work by performing photolithography on pristine PMMA according to the invention.
[0073] To fabricate the OTFTs, photo-lithographically defined aluminum (Al) gate electrodes on the pre-cleaned glass substrate are realized in the first step, as illustrated in FIG. 3A. A blanket layer of 450nm pristine PMMA solution in anisole (60mg/ml) was spin- coated, followed by annealing at 120°C, as illustrated in FIG. 3B.
[0074] For patterning bottom source and drain electrodes over PMMA, the formation of a bi-layer resist-stack of PMGI resist as a bottom-resist coated directly over PMMA layer at the spin rate of 3000 rpm followed by low-temperature annealing at 115 °C for 10 min on a hot plate (FIG. 3C).
[0075] Further, MICROPOSIT S 1813 positive photoresist was spin-coated at 4000 rpm
(FIG. 3D) on top of the PMGI layer to form the top-resist layer, followed by prebake. After the prebake, the bi-layer is exposed to UV (FIG. 3E) through the mask plate using the Karl- Suss mask aligner. An exposed bi-layer resist-stake was developed (FIG. 3F) using MICROPOSIT MF319 (tetramethylammonium -hydroxide based developer) without experiencing any physical or chemical degradation of the PMMA layer.
[0076] Further, the evaporation of the source and drain metal electrodes for which we have deposited Cr/Au by thermal evaporation followed by lift-off is illustrated in FIG. 3G and FIG. 3H, respectively. IPA is used as a photoresist stripper during lift-off (FIG. 3H). One of the key advantages of employing the bi-layer resist structure is that it facilitates the easy lift-off using IPA. After the metal lift-off, the bottom-resist layer was removed by MF319 exposure for 20 seconds, followed by DI water cleaning, as illustrated in FIG. 31. RR-P3HT (Sigma Aldrich) thin films were prepared by spin-coating from dichlorobenzene (DCB) solution (5 mg/ml) on top of already patterned source and drain metal electrodes, as illustrated in FIG. 3J.
[0077] The characterization of the fabricated OTFT based on P3HT and PMMA gate dielectric shows the apparent p-type enhancement-mode behavior. The output characteristics of the 2pm and 4pm channel length device with a W/L ratio of 500 are shown in FIG. 4 and FIG. 5. The saturation mobility of 3.8x 10 cm2/V -s and the on/off ratio of 103 has been calculated from the saturation transfer characteristics of the device shown in FIG. 6. The device showed a threshold voltage of 0 V and a sub-threshold swing (SS) of 1.65 V/decade. The device showed excellent performance in terms of the device parameters compared with the earlier reported results.
[0078] FIG. 7 shows the continuously measured transfer characteristics of the 2pm channel length OTFTs with continuous VGS sweeps up to 20 cycles in the saturation region. No shift of transfer curves was observed in the saturation region with the IDS at the 10th and 20th VGS sweep cycles which are attributed to the fact that there is no change in the switchon voltage (VON). NO shift in switch-on voltage (VON) corresponding to the 10th and 20th sweep implies no event of charge injection or generation within the bulk of the gate dielectric. Furthermore, no variation of SS between the successive sweeps rules out the formation of any additional trap states at the P3HT/PMMA interface due to gate-bias stress demonstrating the undamaged and good quality of pristine PMMA gate dielectric layer delivering excellent OTFT operational stability.
[0079] Thus, the present invention provides performing photolithography over PMMA and/or PMMA based hybrid/blended and bi -layer dielectric systems which facilitate the easy realization of miniaturized micron and sub-micron organic electronics devices such as PMMA gate dielectric based organic field effect transistors. Since the process does not involve any kind of pre-processing or post-processing step to treat chemically or physically the PMMA, it facilitates the solution for true low cost, easy processing and large area manufacturing of organic electronic devices using PMMA and/or PMMA based hybrid/blended and bi-layer dielectric systems. [0080] While the preceding written description of the invention enables one of ordinary skill to make and use what is considered presently to be the best mode thereof those of ordinary skill will understand and appreciate the existence of variations, combinations, and equivalents of the specific embodiment, method, and examples herein. The invention should, therefore, not be limited by the above-described embodiment, method, and examples but by all embodiments and methods within the scope of the invention as claimed.

Claims

I/We Claim:
1. A thin film transistor (20), comprising: a. a rigid or flexible substrate (21) having a first side and a second side; b. an electrically conducting gate electrode (22), being positioned in the bottom gate configuration over the substrate wherein the bottom of the gate electrode facing the first side of the substrate; c. a pristine poly-(methyl-methacrylate) (PMMA) or PMMA based dielectric as gate dielectric layer, being positioned over the top of the electrically conducting gate electrode, wherein the bottom of the gate dielectric layer facing the first side of the substrate; d. a photolithographically patterned electrically conducting source and drain electrodes (24, 25), being positioned over the top of the gate dielectric layer in the bottom -contact configuration over the substrate, wherein the bottom of the electrically conducting source and drain electrodes facing the first side of the substrate ;and e. a semiconducting layer, being positioned over the top of the source and drain electrodes, wherein the bottom of the semiconducting layer facing the first side of the substrate.
2. The thin film transistor as claimed in claim 1, wherein the substrate is selected from the group comprising glass, Si/SiC , flexible metal sheet and flexible plastic substrate.
3. The thin film transistor as claimed in claim 1, wherein the electrically conducting gate electrode is photo-lithographically patterned and comprises a conducting polymer selected from the group comprising PEDOT:PSS, a stable metal, a metal alloy, or a conducting oxide.
4. The thin film transistor as claimed in claim 1, wherein the PMMA layer as gate dielectric layer, being deposited by methods selected from the group comp spin coating, chemical vapour deposition, plasma polymerization, thermal deposition, RF sputtering and DC sputteringfor a large area.
5. The thin film transistor as claimed in claim 1, wherein the electrically conducting source and drain electrodes includes a conducting polymer selected from the group comprising PEDOT:PSS, a stable metal, a metal alloy, or a conducting oxide.
6. The thin film transistor as claimed in claim 1, wherein the electrically conducting source and drain electrodes are photolithographically patterned using the bi-layer lithography.
7. The thin film transistor as claimed in claim 6, wherein the bi-layer lithography includes a bi-layer resist stack for performing conventional UV/Deep-UV lithography over pristine PMMA or PMMA based dielectric layer, comprising: a) a thick bottom-resist layer deposited directly over pristine PMMA or PMMA based dielectric layer, and b) a thin upper resist layer deposited on top of the bottom-resist layer.
8. The thin film transistor as claimed in claim 7, wherein the thick bottom-resist layer in the bi-layer resist stack is chemically compatible with the pristine PMMA or PMMA -based dielectric layer.
9. The thin film transistor as claimed in claim 7, wherein the thick bottom-resist layer in the bi-layer resist stack is a methacrylic-polymer based resist.
10. The thin film transistor as claimed in claim 7, wherein the methacrylic-polymer based resist is a polyglutarimide or poly-(dimethylglutarimide) based resist obtained through imidization of PMMA.
11. The thin film transistor as claimed in claim 7, wherein the thick bottom-resist layer is a polymethylglutarimide (PMGI) resist layer, preferably PMGI or LOR resist layer.
12. The thin film transistor as claimed in claim 7, wherein the upper resist layer is a g-line, i- line, broadband, deep UV, or 193nm (positive or negative tone) photoresist, preferably MICROPOSIT 's SI 800 series photoresist.
13. The thin film transistor as claimed in claim 1, wherein the semiconducting layer is made of an inorganic semiconductor material selected from the group comprising amorphous- silicon, an organic semiconductor material including DPP-DTT (Poly[[2,3,5,6-tetrahydro- 2,5-bis(2-octyldodecyl)-3,6-dioxopyrrolo[3,4-c]pyrrole-l,4-diyl]-2,5 thiophenediylthieno[3,2 b]thiophene-2,5-diyl-2,5-thiophenediyl]), or an oxide semiconductor material including IGZO (Indium gallium zinc oxide), more preferably an organic polymer semiconductor including P3HT (Poly(3-hexylthiophene-2,5-diyl)).
14. A method for manufacturing the thin film transistor as claimed in claim 1 by performing conventional UV/deep-UV lithography using a bi-layer resist stack, comprising the steps of: a. forming a photo-lithographically patterned electrically conducting gate electrode; b. forming pristine PMMA or PMMA based dielectric layer on top of electrically conducting gate electrode; c. forming a bi-layer resist stack over the pristine PMMA or PMMA based dielectric layer prepared in step (b), wherein the bi-layer resist stack comprising:
(i) a thick bottom-resist layer deposited directly over the pristine PMMA or PMMA based dielectric layer by spin coating followed by annealing of the formed layer at a temperature in the range of 70°C to 150°C and
(ii) a thin upper resist layer deposited on top of the bottom-resist layer by spin coating; d. exposing the bi-layer resist stack to the suitable UV or deep-UV radiation through a photomask; e. developing the exposed bi-layer resist stack using a compatible developer to form photolithographically patterned source and drain electrode structures; f. depositing an electrically conducting layer as claimed in claim 5 for source and drain electrodes over the patterned structures; g. performing lift-off of the electrically conducting source and drain electrode layer and top-resist layer using a suitable photoresist stripper to realize photolithographically patterned electrically conducting source and drain electrodes as claimed in claim 1 ; h. removing the bottom-resist layer using the compatible developer followed by DI water cleaning; i. preferably performing surface treatment of patterned source and drain electrodes; j . forming the semiconducting layer as claimed in claim 1, being positioned over the top of the photolithographically patterned electrically conducting source and drain electrodes.
15. The method as claimed in claim 14, wherein the thick bottom-resist layer is annealed more preferably at 115 °C temperature.
16. The method as claimed in claim 14, wherein the developer is based on tetra methyl ammonium hydroxide (TMAH), preferably MICROPOSIT MF-319 or MF-321.
17. The method as claimed in claim 14, wherein the photoresist stripper is isopropyl alcohol.
18. The method as claimed in claim 14, wherein the photoresist stripper is maintained at a temperature in the range of 35°C to 55°C during the metal lift-off, The method as claimed in claim 14, wherein the surface treatment improves the carrier transport at the interface between the source and drain electrodes and the semiconductor layer.
PCT/IN2023/050394 2022-05-20 2023-04-21 Pmma gate dielectric based patterned bottom-gate bottom contact type organic thin film transistor WO2023223337A1 (en)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110147726A1 (en) * 2008-06-30 2011-06-23 Sumitomo Chemical Company, Limited Organic thin film transistor, method for manufacturing the same, display member using the organic thin film transistor, and display
WO2012057196A1 (en) * 2010-10-27 2012-05-03 住友化学株式会社 Organic thin film transistor with excellent charge injection properties

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110147726A1 (en) * 2008-06-30 2011-06-23 Sumitomo Chemical Company, Limited Organic thin film transistor, method for manufacturing the same, display member using the organic thin film transistor, and display
WO2012057196A1 (en) * 2010-10-27 2012-05-03 住友化学株式会社 Organic thin film transistor with excellent charge injection properties

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