CN111477742A

CN111477742A - Organic thin film transistor and preparation method thereof

Info

Publication number: CN111477742A
Application number: CN201910069990.7A
Authority: CN
Inventors: 冯林润; 刘哲; 凯伦·帕拉巴·拉杰夫; 西蒙·多米尼克·奥吉尔
Original assignee: New Dove Ltd
Current assignee: New Dove Ltd
Priority date: 2019-01-24
Filing date: 2019-01-24
Publication date: 2020-07-31

Abstract

An organic thin film transistor and a method for fabricating the same. The preparation method comprises the steps of forming a back gate on a substrate through patterning; forming an organic back gate dielectric layer on the substrate and the back gate; forming a source electrode and a drain electrode on the organic back gate dielectric layer through patterning; forming an organic semiconductor channel layer on the organic back gate dielectric layer, the source electrode and the drain electrode; forming an organic top gate dielectric layer on the organic semiconductor channel layer; forming a top gate on the organic top gate dielectric layer through patterning; the organic semiconductor channel layer and the organic top-gate dielectric layer are etched using the top-gate as a hard mask. The organic thin film transistor is prepared by the method. The method omits the procedure of patterning the dielectric layer, saves the number of photomasks, saves the cost and simplifies the process.

Description

Organic thin film transistor and preparation method thereof

Technical Field

The present application relates to, but is not limited to, the field of semiconductor devices, and in particular, to, but not limited to, an organic thin film transistor and a method of fabricating the same.

Background

A Thin Film Transistor (TFT) is a key electronic component in modern microelectronics technologies, and has been widely used in the field of flat panel displays. The thin film transistor mainly includes a gate electrode, an insulating layer, a semiconductor layer, a source electrode, and a drain electrode.

In recent years, flexible display devices that can be bent and straightened by a user have been the focus of research. In order to manufacture such a flexible display device, a flexible plastic is used substantially instead of a glass substrate, and an Organic Thin Film Transistor (OTFT) including an Organic Semiconductor (OSC) is used instead of a switching device including an inorganic material.

The starting point of designing thin film transistors (including organic thin film transistors and inorganic thin film transistors) comprising back gates is to facilitate the control of the turn-on voltage of thin film transistor devices and to adjust the instability of the thin film transistors under bias voltage stress, and another potential role is to utilize the back gates to serve as light shielding layers of active channels of the thin film transistors.

In order to span from standard top gate organic thin film transistors to top gate organic thin film transistors that include a back gate, two additional masks are typically required, one for patterning the back gate itself and the other for patterning the top gate dielectric layer and the active channel layer. The process flow for conventionally preparing a top gate organic thin film transistor containing a back gate is as follows:

1) patterning a back gate using a first mask;

2) patterning the organic back gate dielectric layer using a second photomask;

3) patterning the source and drain electrodes using a third mask;

4) patterning the top gate by using a fourth photomask, and etching the organic semiconductor channel layer and the organic top gate dielectric layer by using the patterned top gate as a hard mask through a dry method;

5) patterning the first passivation layer using a fifth photomask;

6) patterning the interconnect layer using a sixth photomask;

7) patterning the second passivation layer using a seventh photo-mask;

8) the top pixel electrode is patterned using an eighth mask.

Disclosure of Invention

The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

In the preparation process of the top gate organic thin film transistor containing the back gate, the preparation process is complicated due to the use of the photomask for many times, the manufacturing time is increased, and the cost is increased. The inventor of the application optimizes the preparation process of the top gate organic thin film transistor comprising the back gate through careful research for many years, and finally achieves the purposes of saving a manufacturing photomask and a large amount of manufacturing time, thereby reducing the direct cost and the indirect cost of the manufacturing process.

The present application provides a method of fabricating an organic thin film transistor. The method comprises the following steps:

forming a back gate on the substrate by patterning;

forming an organic back gate dielectric layer on the substrate and the back gate;

forming a source electrode and a drain electrode on the organic back gate dielectric layer through patterning;

forming an organic semiconductor channel layer on the organic back gate dielectric layer, the source electrode and the drain electrode;

forming an organic top gate dielectric layer on the organic semiconductor channel layer;

forming a top gate on the organic top gate dielectric layer through patterning;

the organic semiconductor channel layer and the organic top-gate dielectric layer are etched using the top-gate as a hard mask.

In some embodiments, the organic semiconductor channel layer and the organic top gate dielectric layer may be etched until the back gate is the etch endpoint, while etching exposes the source and drain electrodes.

In some embodiments, after etching the organic semiconductor channel layer and the organic top gate dielectric layer, the method may further comprise:

forming a patterned first passivation layer exposing the back gate, the top gate, and the source or drain electrode;

forming a patterned interconnection layer, so that the back gate and the top gate are interconnected through the interconnection layer, and the source electrode or the drain electrode is interconnected with the other part of the interconnection layer;

forming a patterned second passivation layer exposing the interconnection layer interconnected with the source or drain electrode;

and forming a top pixel electrode through patterning, wherein the top pixel electrode is interconnected with the source electrode or the drain electrode through an interconnection layer.

In some embodiments, the etching of the organic semiconductor channel layer and the organic top gate dielectric layer may also end up on the lower surface of the organic semiconductor channel layer, while the etching exposes the source and drain electrodes.

forming a patterned first passivation layer, wherein the first passivation layer and the organic back gate dielectric layer are patterned and etched until the back gate is an etching end point, and the top gate, the source electrode or the drain electrode are exposed;

In some embodiments, the substrate may be a flexible substrate; before forming the back gate by patterning on the substrate, the method may further include: a substrate is provided on which a flexible substrate is disposed.

In some embodiments, the patterning may be performed using a reticle.

In some embodiments, the organic semiconductor channel layer material may be selected from small molecule or high molecular type organic semiconductor materials, and the like.

In some embodiments, the small molecule organic semiconductor material is selected from one or more of the following: triphenylamine-based organic semiconductors, polyacene-based (polyacenes) organic semiconductors, fullerenes, phthalocyanines, perylene derivative organic semiconductors, cyanine-based organic semiconductors, or the like; the polymeric organic semiconductor material is selected from one or more of the following materials: polyacetylene-type organic semiconductors, polyaromatic ring-type organic semiconductors, copolymer-type organic semiconductors, or the like. Preferably, the polyacene-based organic semiconductor may be a pentacene-type organic semiconductor; more preferably, the pentacene-type organic semiconductor may be selected from 1,4,8, 11-tetramethylbis-triethylsilylethynylpentacene. For example, the organic semiconductor channel layer material can be selected from butadiene styrene triphenylamine organic semiconductors, polythiophene, polyaniline, polypyrrole and the like.

In some embodiments, the materials of the organic back gate dielectric layer, the organic top gate dielectric layer, the first passivation layer, and the second passivation layer may each be independently selected from one or more of the following materials: a polymer capable of being crosslinked so as to be solvent-resistant, or a polymer insoluble in levoglucosenone, dihydrolevoglucosenone or a derivative thereof, or the like.

In some embodiments, the materials of the organic back gate dielectric layer, the organic top gate dielectric layer, the first passivation layer, and the second passivation layer may each be independently selected from one or more of the following materials: polymers having greater than 30% by weight fluorine and soluble in fluorinated or perfluorinated solvents, and the like.

In some embodiments, the materials of the organic back gate dielectric layer, the organic top gate dielectric layer, the first passivation layer, and the second passivation layer may each be independently selected from soluble amorphous fluoropolymers and the like.

In some embodiments, the materials of the organic back gate dielectric layer, the organic top gate dielectric layer, the first passivation layer, and the second passivation layer may each be independently selected from one or more of the following materials: perfluoro (1-butenyl vinyl ether) polymer (Perfluoro (1-butenyl vinyl ether) polymer, CYTOP, Asahi Co., Ltd.), Teflon AF (DuPont Co., Ltd.), Teflon AD (Solvay Co., Ltd.), Fluoropel (Cytonix Co., Ltd.)Si), SU8, vinylidene fluoride-trifluoroethylene-chlorofluoroethylene (poly (vinylidene fluoride-trifluoroethylene-chlorotrifluoroethylene), P (VDF-TrFE-CFE)), cycloolefin polymer resin (cycloolefin resin, ZEOCOAT @)^TMZeon corporation), etc.;

wherein, the Fluoropel belongs to the series of hydrophobic coating materials and is a fluorine-containing polymer solution in fluorine solvent;

SU8 is an epoxy-based negative photoresist consisting of a bisphenol a novolac epoxy resin, which is soluble in organic solvents (gamma-butyrolactone GB L or cyclopentanone, depending on the formulation) and up to 10 wt% of mixed triarylsulfonium/hexafluoroantimonate (as photoacid generator) and has the following molecular structure:

。

in some embodiments, suitable solvents for the fluorinated organic back gate dielectric layer, organic top gate dielectric layer may include: fluorinert FC43 fluorinated liquid (trade name, 3M), Novec electron fluorinated liquid, HFE7500 or HFE7700 (trade name, hydrofluoroether, 3M), and the like.

The present application also provides an organic thin film transistor. The organic thin film transistor is prepared by the method.

The present application also provides an organic thin film transistor. The organic thin film transistor comprises a substrate, a back gate, an organic back gate dielectric layer, a source electrode, a drain electrode, an organic semiconductor channel layer, an organic top gate dielectric layer and a top gate;

the back gate is positioned on the substrate, and part of the back gate is used as a bridging point for metal interconnection of an upper layer and a lower layer; the organic back gate dielectric layer covers the back gate and part of the substrate, and the bridging point is exposed;

arranging a source electrode and a drain electrode on the organic back gate dielectric layer at intervals;

the organic semiconductor channel layer covers part of the source electrode or the drain electrode and part of the organic back gate dielectric layer;

the organic top gate dielectric layer completely covers the organic semiconductor channel layer;

the top gate completely covers the organic top gate dielectric layer.

In some embodiments, the organic thin film transistor may further include a substrate on which the base is disposed; the substrate is a flexible substrate.

In some embodiments, the organic thin film transistor may further include a first passivation layer, an interconnection layer, a second passivation layer, and a top pixel electrode;

the first passivation layer is arranged on one surface, far away from the substrate, of the organic thin film transistor, and the bridging point, part of the top gate and part of the source electrode or the drain electrode are exposed;

the back gate with the exposed bridging point is connected with the top gate through the interconnection layer, the source electrode or the drain electrode is connected with the top pixel electrode through the interconnection layer, and the interconnection layer part connected with the source electrode or the drain electrode is disconnected with the interconnection layers of other parts;

the second passivation layer is disposed between the interconnection layer and the top pixel electrode, and exposes a portion of the interconnection layer connected to the source or drain electrode.

In some embodiments, the organic back gate dielectric layer may expose a portion of the substrate not covered by the top gate.

In some embodiments, the materials of the back gate, the top gate, the interconnect layer, and the top pixel electrode may each be independently selected from one or more of the following materials: au, Ag, Ti, Al, Mo, Indium Tin Oxide (ITO), or the like.

In some embodiments, the substrate material may be selected from one or more of a group consisting of a mother glass, a plastic substrate, a metal, or the like.

For inorganic thin film transistors, Cl is used for etching both metal and inorganic film layers₂、BCl₃、CF₄、SF₆And the etching selectivity of the corrosive gas to the metal and inorganic film is very low, which is very unfavorable for defining an etching end point, controlling a series of key parameters such as a lateral etching slope angle, a characteristic dimension, etching in-plane/inter-wafer uniformity and the like, so that the etching of the inorganic film by using the metal mask is difficult to realize in actual production. The preparation method is used for preparing organic thin film crystalsThe transistor is beneficial to controlling the various parameters and improves various performances of the prepared device.

Compared with the prior art, the beneficial effect that this application has lies in:

1. the process of patterning the dielectric layer is omitted, the number of light masks is saved, on one hand, the cost of a large amount of direct materials and indirect materials is saved, on the other hand, the manufacturing process is simplified, the engineering yield is greatly improved, and the rejection rate of products is reduced; the manufacturing process is simplified, the productivity in unit time is greatly improved, the scale effect of the product is reduced, the fixed investment cost is reduced, and therefore the economic benefit is greatly improved.

2. The metal pattern (top gate) is used as a hard mask, so that damage of process gas or plasma to the surface (including the side) of an organic material and the interface of the organic material and metal when the organic semiconductor channel layer and/or the organic top gate dielectric layer are independently etched is effectively reduced without using an etching barrier layer, the defect density of the surface and the interface of a functional layer is reduced, the injection and transport efficiency of current carriers of the thin film transistor is improved, the electric leakage problem of the thin film transistor is effectively improved, and the stability of a thin film transistor device is improved.

3. The top gate is used as a hard mask, and the patterns of the organic semiconductor channel layer and the organic top gate dielectric layer are obtained by using a self-alignment process, so that the times of mask exposure and alignment between layers are reduced. The parasitic capacitance between the top gate and the back gate is effectively reduced, and the high-frequency characteristic of the device is further improved.

4. The organic semiconductor channel layer and the organic top gate dielectric layer are continuously formed and etched in a one-step method, the probability of poor products such as particles introduced in the manufacturing process is greatly reduced, and the yield of devices is improved.

5. The thicknesses of the organic semiconductor channel layer and the organic top gate dielectric layer can be changed as required, the flatness of formed films is effectively improved, the operating voltage of the thin film transistor can be better controlled on the conductive channel, and meanwhile, the simpler physical structure facilitates calculation and simulation of devices.

6. Interconnection among different metal electrode layers can be realized only by adjusting process parameters such as etching time, so that the design of functional devices including thin film transistors and the sheet flowing mode are more flexible.

Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the application. The objectives and other advantages of the application may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

Drawings

The accompanying drawings are included to provide a further understanding of the claimed subject matter and are incorporated in and constitute a part of this specification, illustrate embodiments of the subject matter and together with the description serve to explain the principles of the subject matter and not to limit the subject matter.

Fig. 1a to fig. 1g in fig. 1 are schematic structural diagrams of cross sections of devices obtained in respective steps in a method for manufacturing an organic thin film transistor according to an embodiment of the present application;

fig. 2a to 2g in fig. 2 are schematic structural diagrams of cross sections of devices obtained in respective steps in a method for manufacturing an organic thin film transistor according to another embodiment of the present application;

fig. 3 is a graph showing the transfer characteristics and mobility of a ring-shaped (Corbino) device prepared in the example of the present application at a back gate voltage of + 1.5V;

fig. 4 is a graph showing the transfer characteristic and mobility of a ring-shaped (Corbino) device prepared in the example of the present application at a back gate voltage of + 3.5V.

In the figure: 100. a substrate; 101. a flexible substrate; 102. a back gate; 103. an organic back gate dielectric layer; 104. source/drain electrodes; 105. an organic semiconductor channel layer; 106. an organic top gate dielectric layer; 107. top gate; 108. a first passivation layer; 109. an interconnect layer; 110. a second passivation layer; 111. a top pixel electrode.

Detailed Description

To make the objects, technical solutions and advantages of the present application more apparent, embodiments of the present application will be described in detail below with reference to the accompanying drawings. It should be noted that the embodiments and features of the embodiments in the present application may be arbitrarily combined with each other without conflict.

According to the preparation method of the organic thin film transistor, firstly, a photomask is used for patterning the back gate layer, then the top gate serves as a hard mask, and the interconnection between the back gate and other metal layers (mainly bridging between the source electrode/drain electrode and the gate electrode layer) is completed by combining the subsequent etching of different organic layers. The application optimizes the via hole structures on the organic semiconductor channel layer, the organic back gate dielectric layer, the organic top gate dielectric layer, the first passivation layer and the second passivation layer. The dry etching step and the process parameters finally achieve the purpose of saving the photomask in the step of patterning the dielectric layer and a large amount of process time, and thereby reduce the direct cost and the indirect cost of the manufacturing process.

In the method for manufacturing an organic thin film transistor provided by the present application, before the OTFT manufacturing process starts, a preparation process may be performed on a substrate, the preparation process including: providing a substrate, optionally depositing a flexible substrate on the substrate; optionally, a sub-layer of cross-linked buffer layer material is applied on the substrate (in the case of a non-deposited flexible substrate) or the flexible substrate (in the case of a deposited flexible substrate on a substrate), as desired to provide the organic semiconductor material with a surface having certain surface energy characteristics. For example, the sub-layer may be coated under vacuum at a temperature of from ambient to 150 ℃ using a thermally crosslinked buffer organic material P11 (Neudrive, UK). In the method for fabricating an organic thin film transistor provided in the present application, a plasma treatment may be optionally used to remove photoresist scum, or improve material properties or contact at process sites such as ion activation treatment of the surface of the functional layer, thinning of direct materials such as photoresist or other organic materials, modification of the edges and sidewalls of organic patterns, and removal of indirect material scum and residues. For example, after stripping the photoresist from the source and drain electrodes, the surface is treated with plasma to remove any unwanted organic residues on the surface of the source and drain electrodes, improving the yield and uniformity of the OTFT array. After the plasma treatment, a surface with a high polar component of the free energy is formed, which may be formed by polar oxygen-containing species formed on the surface of the sub-layerSubstance induced. Increasing the surface free energy of the substrate is beneficial because it improves wettability. For example, the surface of the sample can be treated by placing the substrate in a plasma cleaning chamber and running a plasma cycle, and the treatment parameter can be power P0-5000W, O₂The sccm of Ar is 0.5sccm to 500sccm, the processing time t is 0.5s to 5000 s.

In the preparation method of the organic thin film transistor provided by the application, the metal layers can be prepared by adopting a thermal evaporation method, a sputtering method and other processes, the metal layers comprise a back gate layer, a source electrode layer, a drain electrode layer, a top gate layer, an interconnection layer, a top pixel electrode layer and the like, and the metal layers can be prepared by adopting conventional process steps and parameters.

In the preparation method of the organic thin film transistor provided by the application, the functional film layers can be patterned by adopting the processes of photolithography and the like, each functional layer comprises a back gate layer, an organic back gate dielectric layer, a source electrode layer, a drain electrode layer, a first passivation layer, a second passivation layer, an interconnection layer, a top pixel electrode layer and the like, and the functional film layers can be patterned by adopting the conventional process steps and parameters. For example, the following process steps can be used: firstly, coating a layer of positive (or negative) light resistance on the surface of a target functional layer and baking to remove a solvent; then, patterning the OTFT through a mask by using ultraviolet light, wherein the pattern mask is specially used for each layer pattern of the OTFT, and carrying out alignment and exposure on a mask aligner; removing the photoresist pattern which does not need to be reserved by using a developing solution, and then etching off the lower target functional layer on a dry etching machine or etching off the lower target functional layer on a spin coater by using an acid etching solution; finally, any residual photoresist on the electrode is removed by using a floodlight exposure and photoresist stripping liquid, and a target pattern is obtained on the target functional layer. The following process parameters may be selected: ultraviolet rays are adopted, and the exposure is 5mJ/cm²-500mJ/cm²Proximity exposure mode, N₂The pressure is 0.5Bar-500Bar, the coating, developing and photoresist stripping rotation speed is 100rpm-5000rpm, the coating, developing and photoresist stripping time is t 0.5s-500s, the photoresist baking temperature is normal temperature to 150 ℃, and the photoresist baking time is t 0.5s-500 s. And, coating, developing, baking and resist strippingCan be carried out in multiple steps and cycles.

In the method of manufacturing an organic thin film transistor provided in the present application, optionally, a metal surface modification, i.e., a Self-assembled thin film (SAM) deposition, may be performed immediately after the step of plasma-treating the source and drain electrodes, by a process step of applying a SAM solution in a divided monolayer, and then performing two isopropyl alcohol (IPA) washes and bakes. For example, a spin coating process can be used, and the process parameters are as follows: the SAM material and IPA are used in an amount of 1 ml/inch substrate to 20 ml/inch substrate, the coating speed is 100rpm to 5000rpm, the coating time is 0.5s to 500s, the baking temperature is normal temperature to 150 ℃, and the baking time is 0.5s to 500 s. The coating and baking may be performed in multiple steps and cycles.

In the method for preparing the organic thin film transistor, after the steps of SAM deposition and final cooling, the substrate is transferred to a spin coater or a slit coater to coat the organic semiconductor channel layer and the organic top gate dielectric layer. The coating process can adopt spin coating, and the process parameters can be as follows: the dosage of the organic semiconductor channel layer material and the organic top gate dielectric layer material is as follows: 1 ml/inch substrate-20 ml/inch substrate, coating speed: 100rpm-5000rpm, coating time t of 0.5s-500s, baking temperature of normal temperature-150 deg.c and baking time t of 0.5s-500 s. The coating and baking may be performed in multiple steps and cycles.

Implementation mode one

In the first embodiment of the present application, a method for manufacturing an organic thin film transistor is provided, and a process of the method is described in detail below with reference to fig. 1a to 1 g. The method for manufacturing an organic thin film transistor according to an embodiment includes:

S11: providing a substrate 100, wherein the substrate material can be one or more selected from a group consisting of a mother glass, a plastic substrate, a metal and the like;

depositing a flexible substrate 101 on the substrate 100, where the flexible substrate 101 may be polyethylene naphthalate (PEN), or the like;

depositing a first metal layer on the flexible substrate 101, the first metal layer material may be selected from one or more of the following materials: au, Ag, Ti, Al, Mo, etc., or ITO having metallic characteristics may also be used;

patterning the first metal layer through a first photomask to obtain a back gate 102;

the cross-sectional structure of the device obtained in step S11 is schematically shown in fig. 1 a.

S12: an organic back gate dielectric layer 103 is deposited on the flexible substrate 101 and the back gate 102, and the material of the organic back gate dielectric layer 103 may be selected from one or more of the following materials: CYTOP, Teflon AF, Hyflon AD, Fluoropel, SU8, P (VDF-TrFE-CFE), ZEOCOAT^TMEtc.;

depositing a second metal layer on the organic back gate dielectric layer 103, the second metal layer material may be selected from one or more of the following materials: au, Ag, Ti, Al, Mo, etc., or ITO may be used;

patterning the second metal layer through a second photomask to obtain a source/drain electrode 104;

the cross-sectional structure of the device obtained in step S12 is schematically shown in fig. 1 b.

In step S12, the process of patterning the dielectric layer is omitted, and the number of masks used in the process is reduced. The reduction of the number of the light covers in the preparation process saves a large amount of direct material and indirect material costs, simplifies the manufacturing process, greatly improves the productivity in unit time, thins the cost of fixed investment due to the scale effect of the product, greatly improves the project yield, reduces the rejection rate of the product, and greatly improves the economic efficiency.

S13: an organic semiconductor channel layer 105 is deposited on the organic back gate dielectric layer 103 and the source/drain electrodes 104, and the material of the organic semiconductor channel layer 105 may be selected from small molecule or high molecule type organic semiconductor materials and the like: the small molecule type organic semiconductor material is selected from one or more of the following materials: triphenylamine-based organic semiconductors, polyacene-based organic semiconductors, fullerenes, phthalocyanines, perylene derivative organic semiconductors, cyanine-based organic semiconductors, or the like; the polymeric organic semiconductor material is selected from one or more of the following materials: polyacetylene type organic moietiesA conductor, a polyaromatic ring type organic semiconductor or a copolymer type organic semiconductor, and the like. Preferably, the polyacene-based organic semiconductor may be a pentacene-type organic semiconductor; more preferably, the pentacene-type organic semiconductor may be selected from 1,4,8, 11-tetramethylbis-triethylsilylethynylpentacene. For example, the organic semiconductor channel layer material can be selected from butadiene styrene triphenylamine organic semiconductors, polythiophene, polyaniline, polypyrrole and the like.

Depositing an organic top gate dielectric layer 106 on the organic semiconductor channel layer 105, the organic top gate dielectric layer 106 material may be selected from one or more of the following materials: CYTOP, Teflon AF, Hyflon AD, Fluoropel, SU8, P (VDF-TrFE-CFE), ZEOCOAT^TMEtc.;

depositing a third metal layer on the organic top gate dielectric layer 106, wherein the third metal layer may be selected from one or more of the following materials: au, Ag, Ti, Al, Mo, etc., or ITO may be used;

patterning the third metal layer through a third photomask to obtain a top gate 107;

etching the organic top gate dielectric layer 106, the organic semiconductor channel layer 105 and the organic back gate dielectric layer 103 with the top gate 107 serving as a hard mask until the back gate 102 is an etching end point, and simultaneously etching to expose the source or drain electrode 104;

the cross-sectional structure of the device obtained in step S13 is schematically shown in fig. 1 c.

In step S13, the top gate 107 is used as a hard mask, and the organic top gate dielectric layer 106, the organic semiconductor channel layer 105, and the organic back gate dielectric layer 103 are etched at the same time, without using an etching barrier layer (under this condition, it is equivalent to omitting a mask for patterning the etching barrier layer, which also saves cost, simplifies process), effectively reduces the damage of the process gas itself or plasma to the surface and side of the organic material and metal interface when the organic semiconductor channel layer 105 and/or the organic top gate dielectric layer 106 are etched alone, reduces the defect density on the surface and interface of the functional layer, improves the injection and transport efficiency of carriers, effectively improves the leakage problem of the thin film transistor, and increases the stability of the thin film transistor.

In step S13, the organic semiconductor channel layer 105 and the organic top gate dielectric layer 106 are patterned using a "self-aligned" process, using the top gate 107 as a hard mask, reducing the number of mask exposures that are registered from layer to layer. The parasitic capacitance between the top gate 107 and the back gate 102 is effectively reduced, and the high-frequency characteristics of the thin film transistor are further improved.

In step S13, the organic semiconductor channel layer 105 and the organic top gate dielectric layer 106 are continuously formed and etched by a one-step method, so that the probability of introducing particles during the manufacturing process is greatly reduced, and the yield of the device is improved.

In step S13, the thicknesses of the organic semiconductor channel layer 105 and the organic top gate dielectric layer 106 can be changed as required, and the flatness of the formed film is effectively improved, so that the operating voltage of the thin film transistor can be better controlled over the conductive channel, and the simpler physical structure facilitates the calculation and simulation of the device.

S14: depositing a first passivation layer 108 on the flexible substrate 101, the back gate 102, the top gate 107, and the source/drain electrode 104, wherein the first passivation layer 108 may be made of one or more materials selected from the group consisting of: CYTOP, Teflon AF, Hyflon AD, Fluoropel, SU8, P (VDF-TrFE-CFE), ZEOCOAT^TMEtc.;

patterning the first passivation layer 108 through a fourth photo-mask to expose one back gate 102, the top gate 107, and the source or drain electrode 104;

the cross-sectional structure of the device obtained in step S14 is schematically shown in fig. 1 d.

S15: an interconnection layer 109 is deposited on the first passivation layer 108, the back gate 102, the top gate 107, and the source or drain electrode 104, and the interconnection layer 109 material may be selected from one or more of the following materials: au, Ag, Ti, Al, Mo, etc., or ITO may be used;

patterning the interconnection layer 109 through a fifth photomask, so that the back gate 102 and the top gate 107 are interconnected through the interconnection layer 109, and the source electrode or the drain electrode 104 is interconnected with another part of the interconnection layer 109;

the cross-sectional structure of the device obtained in step S15 is schematically shown in fig. 1 e.

S16: depositing a second passivation layer 110 on the interconnection layer 109 and the first passivation layer 108, wherein the material of the second passivation layer 110 may be selected from one or more of the following materials: CYTOP, Teflon AF, Hyflon AD, Fluoropel, SU8, P (VDF-TrFE-CFE), ZEOCOAT^TMEtc.;

patterning the second passivation layer 110 through a sixth photo-mask to expose the interconnection layer 109 interconnected with the source or drain electrode 104;

the cross-sectional structure of the device obtained in step S16 is schematically shown in fig. 1 f.

S17: depositing a top pixel electrode 111 on the second passivation layer 110 and the interconnection layer 109, wherein the top pixel electrode 111 and the source or drain electrode 104 are interconnected through the interconnection layer 109, and the material of the top pixel electrode 111 is selected from one or more of the following materials: au, Ag, Ti, Al, Mo, etc., or ITO may be used; preparing an organic thin film transistor;

the cross-sectional structure of the device obtained in step S17 is schematically shown in fig. 1 g.

In the manufacturing method of the first embodiment, the dielectric layer does not need to be patterned, and the mask used in this step is omitted. Subsequently, when the organic semiconductor channel layer 105 and the organic top gate dielectric layer 106 are etched, the top gate 107 is used as a hard mask to dry etch the organic semiconductor channel layer 105 and the organic top gate dielectric layer 106, the etching time is prolonged, and the etching is not finished until the back gate 102, that is, the dielectric layer is etched in the step. Then, after the first passivation layer 108 is etched in a conventional etching time and the interconnection layer 109 is deposited, the interconnection layer 109 above can be interconnected with the source/drain electrode 104 below and the back gate 102.

Embodiment one a schematic cross-sectional structure of the organic thin film transistor prepared in accordance with the first embodiment is shown in fig. 1 g. The method comprises the following steps: the organic light emitting diode comprises a substrate 100, a flexible substrate 101, a back gate 102, an organic back gate dielectric layer 103, source/drain electrodes 104, an organic semiconductor channel layer 105, an organic top gate dielectric layer 106, a top gate 107, a first passivation layer 108, an interconnection layer 109, a second passivation layer 110 and a top pixel electrode 111.

Wherein, the flexible substrate 101 completely covers the substrate 100; back gates 102 are arranged on the flexible substrate 101 at intervals, and a part of the back gate 102 simultaneously serves as a bridging point for metal interconnections of upper and lower layers, for example: a bridge point of the source/drain electrode 104 and the back gate 102, or a bridge point of the top gate 107 and the back gate 102, or a bridge point of the top pixel electrode 111 and the back gate 102; the organic back gate dielectric layer 103 covers the back gate 102 and the flexible substrate 101 not covered by the back gate 102, and bridge points of the back gate 102 in upper and lower metal interconnection layers and the flexible substrate 101 not covered by the top gate 107 are exposed; source/drain electrodes 104 are arranged on the organic back gate dielectric layer 103 at intervals; the organic semiconductor channel layer 105 covers a part of the source electrode or the drain electrode 104, a part of a lead-out wire of the source electrode or the drain electrode 104 and the organic back gate dielectric layer 103 at the interval part between the source electrode and the drain electrode 104, wherein the part of the lead-out wire is connected with the drain electrode 104 on the same layer, but is not used as the drain electrode of the TFT device in function, but is used as a metal pattern of signal wires such as current, voltage and the like; completely covering the organic top gate dielectric layer 106 on the organic semiconductor channel layer 105; a top gate 107 is arranged on the organic top gate dielectric layer 106, and the top gate 107 completely covers the organic top gate dielectric layer 106; a first passivation layer 108 is arranged on each layer, and bridge contacts of the back gate 102 and metal interconnections of the upper layer and the lower layer, part of the top gate 107 and part of the source electrode or the drain electrode 104 are exposed; forming an interconnection layer 109 on the first passivation layer 108, the exposed back gate 102, the top gate 107 and the source or drain electrode 104, wherein the back gate 102 is connected with the top gate 107 through the interconnection layer 109, the source or drain electrode 104 is connected with the top pixel electrode 111 through the interconnection layer 109, and the interconnection layer 109 connected with the source or drain electrode 104 is disconnected from the interconnection layer 109 at other parts; a second passivation layer 110 is provided on the above layers, in which a portion of the interconnection layer 109 connected to the source or drain electrode is exposed.

Second embodiment

In the second embodiment of the present application, another method for manufacturing an organic thin film transistor is provided, and the process of the manufacturing method is described in detail below with reference to fig. 2a to 2 g. The method for manufacturing an organic thin film transistor according to the second embodiment includes:

S21: providing a substrate 100The substrate material can be one or more selected from the group consisting of a mother glass, a plastic substrate, a metal, and the like;

depositing a flexible substrate 101 on a substrate 100, wherein the flexible substrate 101 can be PEN;

depositing a first metal layer on the flexible substrate 101, the first metal layer material may be selected from one or more of the following materials: au, Ag, Ti, Al, Mo, etc., or an ITO layer may be used;

patterning the first metal layer through a first photomask to obtain two back gates 102;

the cross-sectional structure of the device obtained in step S21 is schematically shown in fig. 2 a.

S22: an organic back gate dielectric layer 103 is deposited on the flexible substrate 101 and the back gate 102, and the material of the organic back gate dielectric layer 103 may be selected from one or more of the following materials: CYTOP, Teflon AF, Hyflon AD, Fluoropel, SU8, P (VDF-TrFE-CFE), ZEOCOAT^TMEtc.;

the cross-sectional structure of the device obtained in step S22 is schematically shown in fig. 2 b.

In step S22, the process of patterning the dielectric layer is omitted, and the number of masks used in the process is reduced.

S23: an organic semiconductor channel layer 105 is deposited on the organic back gate dielectric layer 103 and the source/drain electrodes 104, and the material of the organic semiconductor channel layer 105 may be selected from small molecule or high molecule type organic semiconductor materials and the like: the small molecule type organic semiconductor material is selected from one or more of the following materials: triphenylamine-based organic semiconductors, polyacene-based organic semiconductors, fullerenes, phthalocyanines, perylene derivative organic semiconductors, cyanine-based organic semiconductors, or the like; the polymeric organic semiconductor material is selected from one or more of the following materials: polyacetylene-type organic semiconductors, polyaromatic ring-type organic semiconductors, copolymer-type organic semiconductors, or the like. Superior foodAlternatively, the polyacene organic semiconductor may be a pentacene organic semiconductor; more preferably, the pentacene-type organic semiconductor may be selected from 1,4,8, 11-tetramethylbis-triethylsilylethynylpentacene. For example, the organic semiconductor channel layer material can be selected from butadiene styrene triphenylamine organic semiconductors, polythiophene, polyaniline, polypyrrole and the like.

etching the organic top gate dielectric layer 106 and the organic semiconductor channel layer 105 using the top gate 107 as a hard mask until the end of the lower surface of the organic semiconductor channel layer 105;

the cross-sectional structure of the device obtained in step S23 is schematically shown in fig. 2 c.

In step S23, the organic top gate dielectric layer 106 and the organic semiconductor channel layer 105 are simultaneously etched using a "self-aligned" process using the top gate 107 as a hard mask, and the organic semiconductor channel layer 105 and the organic top gate dielectric layer 106 are sequentially film-formed and etched using a one-step process.

S24: depositing a first passivation layer 108 on the organic back gate dielectric layer 103, the top gate 107, and the source/drain electrode 104, wherein the first passivation layer 108 may be made of one or more materials selected from the group consisting of: CYTOP, Teflon AF, Hyflon AD, Fluoropel, SU8, P (VDF-TrFE-CFE), ZEOCOAT^TMEtc.;

patterning and etching the first passivation layer 108 and the organic back gate dielectric layer 103 through a fourth photomask until the back gate 102 is an etching end point, and exposing one back gate 102, the top gate 107 and the source electrode or the drain electrode 104;

the cross-sectional structure of the device obtained in step S24 is schematically shown in fig. 2 d.

In step S24, an alternative way of etching the organic back gate dielectric layer 103 is provided, and it is also not necessary to separately pattern the organic back gate dielectric layer 103, which reduces the use of a photomask and also does not need to use an etching stop layer (under this condition, it is equivalent to a photomask with a patterned etching stop layer also omitted, which also saves the cost and simplifies the process).

S25: an interconnection layer 109 is deposited on the first passivation layer 108, the back gate 102, the top gate 107, and the source or drain electrode 104, and the interconnection layer 109 material may be selected from one or more of the following materials: au, Ag, Ti, Al, Mo, etc., or ITO may be used;

the cross-sectional structure of the device obtained in step S25 is schematically shown in fig. 2 e.

S26: depositing a second passivation layer 110 on the interconnection layer 109 and the first passivation layer 108, wherein the material of the second passivation layer 110 may be selected from one or more of the following materials: CYTOP, Teflon AF, Hyflon AD, Fluoropel, SU8, P (VDF-TrFE-CFE), ZEOCOAT^TMEtc.;

the cross-sectional structure of the device obtained in step S26 is schematically shown in fig. 2 f.

S27: depositing a top pixel electrode 111 on the second passivation layer 110 and the interconnection layer 109, wherein the top pixel electrode 111 and the source or drain electrode 104 are interconnected through the interconnection layer 109, and the material of the top pixel electrode 111 may be selected from one or more of the following materials: au, Ag, Ti, Al, Mo, etc., or ITO may be used;

preparing an organic thin film transistor;

the cross-sectional structure of the device obtained in step S27 is schematically shown in fig. 2 g.

In the manufacturing method of the second embodiment, the dielectric layer does not need to be patterned, and the mask used in this step is omitted. In etching the organic semiconductor channel layer 105 and the organic top gate dielectric layer 106, the organic semiconductor channel layer 105 and the organic top gate dielectric layer 106 are dry-etched with a conventional etching time by using the top gate 107 as a hard mask, and the etching end point is the lower surface of the organic top gate dielectric layer 106. When the first passivation layer 108 is subsequently etched, the etching time is prolonged until the back gate layer is etched, i.e., the dielectric layer is etched together in this step. In this manner of etching, most of the dielectric layer on the flexible substrate 101 will be retained. After the subsequent deposition of the interconnection layer 109, the interconnection layer 109 above can be interconnected with the source/drain electrode 104 below and the back gate 102.

Compared with the manufacturing method of the first embodiment of the present application, in the manufacturing method of the second embodiment, the exposure time of the source/drain electrode 104 in the plasma environment is less, and the lateral etching of the organic semiconductor channel layer 105 and the organic top gate dielectric layer 106 is less. Therefore, the manufacturing method of the second embodiment of the present application can control the pattern quality more effectively, improve the uniformity of the device, and reduce the cost.

Fig. 2g shows a schematic cross-sectional structure of the organic thin film transistor prepared according to the second embodiment. The method comprises the following steps: the organic light emitting diode comprises a substrate 100, a flexible substrate 101, a back gate 102, an organic back gate dielectric layer 103, source/drain electrodes 104, an organic semiconductor channel layer 105, an organic top gate dielectric layer 106, a top gate 107, a first passivation layer 108, an interconnection layer 109, a second passivation layer 110 and a top pixel electrode 111.

Wherein, the flexible substrate 101 completely covers the substrate 100; back gates 102 are arranged on the flexible substrate 101 at intervals, and a part of the back gates 102 are simultaneously used as bridging points for metal interconnection of upper and lower layers; the organic back gate dielectric layer 103 covers the back gate 102 and the flexible substrate 101 not covered by the back gate 102, and bridge points of the back gate 102, which are interconnected with upper and lower layers of metal, are exposed; source/drain electrodes 104 are arranged on the organic back gate dielectric layer 103 at intervals; the organic semiconductor channel layer 105 covers a part of the source electrode or drain electrode 104, a part of the lead-out wire of the source electrode or drain electrode 104, and the organic back gate dielectric layer 103 at the interval part between the source electrode and the drain electrode 104; completely covering the organic top gate dielectric layer 106 on the organic semiconductor channel layer 105; a top gate 107 is arranged on the organic top gate dielectric layer 106, and the top gate 107 completely covers the organic top gate dielectric layer 106; a first passivation layer 108 is arranged on each layer, and bridge contacts of the back gate 102 and metal interconnections of the upper layer and the lower layer, part of the top gate 107 and part of the source electrode or the drain electrode 104 are exposed; forming an interconnection layer 109 on the first passivation layer 108, the exposed back gate 102, the top gate 107 and the source or drain electrode 104, wherein the back gate 102 is connected with the top gate 107 through the interconnection layer 109, the source or drain electrode 104 is connected with the top pixel electrode 111 through the interconnection layer 109, and the interconnection layer 109 connected with the source or drain electrode 104 is disconnected from the interconnection layer 109 at other parts; a second passivation layer 110 is provided on the above layers, in which a portion of the interconnection layer 109 connected to the source or drain electrode is exposed.

Example 1:

example 1 relates to the fabrication of back-gated OTFT devices according to the process flow shown in figures 1 a-1 g.

A glass substrate of size 10cm × cm (manufacturer: Corning, model: Eagle XG) was cleaned using ultrasonication in an alkaline cleaner Deconex (3% w/w aqueous solution) for 20 minutes, then rinsed in ultra pure water and dried using compressed air 100nm Ti and 20nm Au were sputtered onto the substrate to form a back gate metal layer, then the metal layer was patterned using photolithography and wet chemical etching (for Ti the etching solution was an aqueous solution of nitric acid and ammonium fluoride, manufacturer: OM Group, code: UPC 048; for Au the etching solution was an aqueous solution of iodine and potassium iodide, manufacturer: OM Group, code: UPC041) after etching, the photoresist was removed by flood exposure and development.

After the P11 sublayer was fabricated, an organic back gate dielectric layer was fabricated (same fabrication process as the organic top gate dielectric layer), then 50nm Au was sputtered on the substrate, and the source and drain electrodes were fabricated using a combination of photolithography and wet etching techniques (etchant composition of potassium iodide and iodine in water). Various designs of source and drain electrodes are grouped together on the same mask, including linear channel devices and circular (corbeno) channel devices. After removing the residual photoresist from the source and drain electrode contacts by UV exposure and spin development, the substrate was examined under an optical microscope and the characteristic length of the device channel was measured in several areas of the substrate.

Before fabrication of Organic Thin Film Transistors (OTFTs), a surface treatment system (manufacturer: Plasma EtchInc. model: PE100) was used with Ar/O₂The substrate is plasma treated. The treatment was carried out at a flow rate of 50sccm of each gas and an RF power of 250W for 65 seconds.

Before spin-coating the Organic Semiconductor (OSC) channel layer, a solution of 10mM 3-fluoro-4-methoxythiophenol in ethylene propylene glycol was added dropwise to the electrode surface for 1 minute, then rinsed in ethylene propylene glycol (2 times) and dried on a hot plate at 100 ℃ for 1 minute. An OSC ink was prepared, specifically 1,4,8, 11-tetramethylbis-triethylsilylethynylpentacene (TM-TES) and a binder (1 part TM-TES and 2 parts binder by weight) in a 30:70 (weight ratio) copolymer of 4-isopropylcyano-PTAA and 2, 4-dimethylpolytriamine dissolved in a 9:1 (weight ratio) mixed solvent system consisting of 1,2,3, 4-tetrahydronaphthalene to isopropanol. It was then spin-coated at 1250rpm for 60 seconds (spin coater manufacturer: Suss, model: RC12) onto an SD electrode, followed by baking on a hot plate at 100 ℃ for 60 seconds. A solution of 1 part of Cytop809M (manufacturer: Asahi Glass) and 1 part of FC43 solvent (manufacturer: Acros Organics) was spin coated at 1500rpm for 20 seconds for the organic back gate dielectric layer and the organic top gate dielectric layer, and the samples were baked on a hot plate at 100 ℃ for 60 seconds. The thicknesses of the organic back gate dielectric layer and the organic top gate dielectric layer are respectively 300 nm.

Au of 50nm was then deposited on the substrate by thermal evaporation and the top gate electrode was patterned by a combination of photolithography and wet etching as previously described. After this, the photoresist on Au was removed by UV exposure and development.

Dry etching of a patterned OSC layer

Using Aurion RIE system patterning of organic top gate dielectric layer, Organic Semiconductor (OSC) channel layer, organic back gate dielectric layer by Reactive Ion Etching (RIE). The process pressure is 0.07hPa, the power is 2250W, the process time is 60s, and O is₂The flow rate was 150 sccm. Removal of the organic top gate dielectric layer, Organic Semiconductor (OSC) channel layer, organic back gate dielectric layer was confirmed by inspection under cross-polarized optical microscopy, and the removed regions showed no evidence of crystalline OSC film remaining. The organic top gate dielectric layer, Organic Semiconductor (OSC) channel layer, organic back gate dielectric layer were removed by dry etching as confirmed using a Dektak profilometer.

Passivation layer (SU-8)

The first passivation layer and second passivation layer solution formulations in this example contained 2.5g of EPON-SU-8 based polymer and 17g of solvent (Cyrene and hexanol 9:1 (weight ratio)). The passivation layer solution formulation also contained 0.5g of triarylsulfonium hexafluoroantimonate solution (dissolved in propylene carbonate, 50% by weight) as a cross-linking agent.

The solution formulation of SU-8 and photoinitiator in Cyrene/hexanol was spin coated at 500rpm for 10 seconds, then at 1250rpm for 30 seconds, and then baked on a hotplate at 95 ℃ for 2 minutes to form a dry film. The film was then exposed to UV light irradiation (365 nm wavelength) through a photomask (defined as VIA layer mask) in a hard contact mode (exposure: 100mJ) using a mask aligner (manufacturer and model: EVG6200) to selectively expose portions of the film. The VIA layer mask is aligned with the first metal layer to ensure that VIAs are formed over the bottom metal pattern. The film was post-exposed to 95 ℃ for 2 minutes. The film was dried by rinsing with MicropositTM EC solvent (manufacturer: Rohm and Haas) for 30 seconds, then spinning at 1000rpm, rinsing with developer for 5 seconds, and then spinning at 2500rpm for 30 seconds.

Au of 50nm was then deposited on the substrate by sputtering and the layer was patterned by photolithography and wet etching to form a top pixel electrode pattern structure connecting the via holes.

OTFT device characterization of example 1

OTFT devices were tested using a semi-automatic probe station (manufacturer and model: Wentworth Pegasus 300S) and a semiconductor parametric analyzer (manufacturer and model: Keithley S4200). And a statistically significant number of OTFT device measurements were made on each substrate. The Keithley semiconductor test analysis system calculates the linear mobility μ according to the following equation:

in the above formula, L is the channel length of the transistor, W is the channel width of the transistor, I_DSIs the current from the drain electrode to the source electrode, C_iIs the dielectric capacitance per unit area. Unless otherwise stated, the drain-source voltage V_DSSet to-2V, gate voltage V_GSThe scan is performed from TFT depletion to accumulation state (typically from +20V to-29V in 1V steps). The reported mobility values are the average of the 5 highest points in the accumulated state for each transistor. The following test results also show channel length data and show the average of the device measurements. To eliminate a small portion of the device with gate leakage, the ratio of gate current to source-drain current is at a maximum of V_GSValue of while V_DSAt a bias of-2V, if the ratio is below 10 (i.e. the gate current is greater than 10% of the source-drain current), the device is excluded from the test results. The standard deviation of the mobility is expressed as a percentage of the mean value, and the number of devices measured is also identified in the results. On-state voltage (V) of transistor_to) Defined as the gate voltage point at which the logarithm of the drain current with respect to the gate voltage is at a maximum. The on/off ratio is defined as the maximum current in the accumulation state (i.e., at V)_g-29V) divided by the off current at depletion. The test includes a bias voltage V applied to the back gate electrode to control the device_TOThe bias used is shown in the chart of the results below.

Test results of example 1

(1) The results of the ring (Corbino) device test at a back gate voltage of +1.5V are shown in table 1:

table 1 device performance test structure (back gate voltage +1.5V) prepared in example 1

At this time, the transfer characteristics and mobility curves of the ring (Corbino) device are shown in fig. 3.

(2) The results of the ring (Corbino) device test at a back gate voltage of +3.5V are shown in table 2:

table 2 device performance test structure (back gate voltage +3.5V) prepared in example 1

At this time, the transfer characteristics and mobility curves of the ring (Corbino) device are shown in fig. 4.

As can be seen from tables 1-2 and FIGS. 3-4, the back gate bias OTFT device with good conduction characteristics and high uniformity can be prepared by the method of the application, and the standard deviation of the mobility is better.

Example 2

Example 2 relates to the fabrication of back-gated OTFT devices according to the process flow shown in figures 2 a-2 g.

A glass substrate of size 10cm × 10cm (manufacturer: Corning, model: Eagle XG) was cleaned using ultrasonication in an alkaline cleaner Deconex (3% w/w aqueous solution) for 20 minutes, then rinsed in ultra pure water and dried using compressed air 100nm Ti and 20nm Au were sputtered onto the substrate to form a back gate metal layer, which was then patterned using photolithography and wet chemical etching (for Ti the etching solution is an aqueous solution of nitric acid and ammonium fluoride, manufacturer: OM Group, code: UPC 048; for Au the etching solution is an aqueous solution of iodine and potassium iodide, manufacturer: OM Group, code: UPC041) after etching, the photoresist was removed by flood exposure and development, then spin coated onto the substrate as a buffer layer (also called a sublayer) with a cross-linkable polymer (P11) (publicly available from NeuDrive, uk.) after spin coating, the substrate was first placed on a hot plate at 95 ℃ for 2 minutes and then the hard baked layer was measured at 150 ℃ for 60 minutes at a final thickness of 11.

After the P11 sublayer was prepared, 50nm Au was sputtered on the substrate, and then the source and drain electrodes were prepared using a combination of photolithography and wet etching techniques (etchant composition of potassium iodide and iodine in water). Various designs of source and drain electrodes are grouped together on the same mask, including linear channel devices and circular (Corbino) channel devices. After removing the residual photoresist from the source and drain electrode contacts by UV exposure and spin development, the substrate was examined under an optical microscope and the characteristic length of the device channel was measured in several areas of the substrate.

Before spin-coating the Organic Semiconductor (OSC) channel layer, a solution of 10mM 3-fluoro-4-methoxythiophenol in ethylene propylene glycol was added dropwise to the electrode surface for 1 minute, then rinsed in ethylene propylene glycol (2 times) and dried on a hot plate at 100 ℃ for 1 minute. An OSC ink was prepared, specifically 1,4,8, 11-tetramethylbis-triethylsilylethynylpentacene (TM-TES) and a binder (1 part TM-TES:2 parts binder by weight) in which a 30:70 (weight ratio) copolymer of 4-isopropylcyano-PTAA and 2, 4-dimethylpolytriamine was dissolved in a mixed solvent system consisting of 9:1 (weight ratio) 1,2,3, 4-tetrahydronaphthalene to isopropanol. It was then spin-coated at 1250rpm for 60 seconds (spin coater manufacturer: Suss, model: RC12) onto an SD electrode, followed by baking on a hot plate at 100 ℃ for 60 seconds. For the organic back gate dielectric layer and the organic top gate dielectric layer, a solution of 1 part of Cytop809M (manufacturer: Asahi Glass) and 1 part of FC43 solvent (manufacturer: Acros Organics) was spin coated at 1500rpm for 20 seconds and the sample was baked on a hot plate at 100 ℃ for 60 seconds. The thicknesses of the organic back gate dielectric layer and the organic top gate dielectric layer are respectively 300 nm.

Dry etching of a patterned OSC layer

The Organic Semiconductor (OSC) channel layer and the organic top gate dielectric layer were patterned by Reactive Ion Etching (RIE) using an Aurion RIE system. The process pressure is 0.07hPa, the power is 2250W, the process time is 25s, O₂The flow rate was 150 sccm. Removal of the Organic Semiconductor (OSC) channel layer and organic top gate dielectric layer was confirmed by inspection under cross-polarized optical microscopy, and the removed regions showed no evidence of crystalline OSC film remaining.

Passivation layer (SU-8)

The SU-8 solution formulation was spin coated at 500rpm for 10 seconds, 1250rpm for 30 seconds, and then baked at 95 ℃ for 2 minutes on a hot plate to form a dry film. The film was exposed to UV (broad band g, h, I line, 1000mJ) light using a Tamarack mask alignment exposure machine and baked at 115 ℃ for 5 minutes. Shipley S1805 photoresist was spin coated and baked at 115 ℃ for 1 minute to give a film layer with a thickness of 1.8 microns. A VIA layer mask (dark field mask) was exposed in alignment with the first metal layer using a mask alignment exposure machine (manufacturer model: EVG6200) to ensure VIA patterning on the underlying metal electrodes using an exposure energy of 84 mJ. After exposure, the photoresist is developed and the feature pattern is inspected. The via shapes in the photoresist film layer were transferred into the SU8 film by Reactive Ion Etching (RIE) using a dry etching system (manufacturer model: Aurion RIE). Process pressure 0.07hPa, power 730W, process time 315s, O₂Flow 100sccm, Ar flow 40sccm, CF₄The flow rate was 10 sccm. After optical inspection of the through-holes, the remaining photoresist was removed by flood exposure and development.

The method of characterization of the OTFT device is the same as that of example 1.

Test results of example 2

(1) The results of testing a ring (Corbino) device at a range of back gate voltages are shown in table 3:

table 3 device performance test structure prepared in example 2

16 devices were measured for each back gate voltage used, with a yield of 94% or greater measured per group. As can be seen from table 3, the back gate bias OTFT device with good conduction characteristics and high uniformity can be prepared by the method of the present application, and the standard deviation of mobility is better.

Although the embodiments disclosed in the present application are described above, the descriptions are only for the convenience of understanding the present application, and are not intended to limit the present application. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the disclosure as defined by the appended claims.

Claims

1. A method of fabricating an organic thin film transistor, comprising the steps of:

forming a back gate on the substrate by patterning;

forming a top gate on the organic top gate dielectric layer through patterning;

etching the organic semiconductor channel layer and the organic top-gate dielectric layer using the top-gate as a hard mask.

2. The method of claim 1, wherein the organic semiconductor channel layer and the organic top gate dielectric layer are etched until the back gate is an etch endpoint while etching exposes the source electrode and the drain electrode.

3. The method of claim 2, after etching the organic semiconductor channel layer and the organic top gate dielectric layer, the method further comprising:

forming a patterned interconnection layer, so that the back gate and the top gate are interconnected through the interconnection layer, and the source electrode or the drain electrode is interconnected with another part of the interconnection layer;

forming a patterned second passivation layer exposing the interconnection layer interconnected with the source electrode or the drain electrode;

and forming a top pixel electrode through patterning, wherein the top pixel electrode is interconnected with the source electrode or the drain electrode through the interconnection layer.

4. The method of claim 1, wherein etching the organic semiconductor channel layer and the organic top gate dielectric layer to a lower surface of the organic semiconductor channel layer ends while etching exposes the source electrode and the drain electrode.

5. The method of claim 4, after etching the organic semiconductor channel layer and the organic top gate dielectric layer, the method further comprising:

forming a patterned first passivation layer, wherein the first passivation layer and the organic back gate dielectric layer are patterned and etched until the back gate is an etch endpoint, while exposing the top gate, and the source electrode or the drain electrode;

6. The method of any one of claims 1-5, wherein the substrate is a flexible substrate;

before forming a back gate by patterning on the substrate, the method further comprises: providing a substrate on which the flexible substrate is disposed.

7. The method of any of claims 1-5, wherein the patterning is performed using a photomask.

8. The method according to one of claims 1 to 5, wherein the organic semiconductor channel layer material is selected from a small-molecule type organic semiconductor material or a high-molecule type organic semiconductor material.

9. The method of claim 8, wherein the small molecule organic semiconductor material is selected from one or more of the following: triphenylamine organic semiconductors, polyacene organic semiconductors, fullerene, phthalocyanine, perylene derivative organic semiconductors, or cyanine organic semiconductors; the high molecular type organic semiconductor material is selected from one or more of the following materials: polyacetylene-type organic semiconductors, polyaromatic ring-type organic semiconductors, or copolymer-type organic semiconductors.

10. The method of claim 3 or 5, wherein the material of the organic back gate dielectric layer, the organic top gate dielectric layer, the first passivation layer and the second passivation layer are each independently selected from one or more of the following: a polymer capable of being crosslinked to render it solvent resistant, or a polymer that is insoluble in levoglucosenone, dihydrolevoglucosenone, or derivatives thereof.

11. The method of claim 3 or 5, wherein the materials of the organic back gate dielectric layer, the organic top gate dielectric layer, the first passivation layer, and the second passivation layer are each independently selected from polymers having greater than 30% fluorine by weight and being soluble in fluorinated or perfluorinated solvents.

12. The method of claim 3 or 5, wherein the material of the organic back gate dielectric layer, the organic top gate dielectric layer, the first passivation layer and the second passivation layer are each independently selected from one or more of the following: perfluoro (1-butenyl vinyl ether) polymer, Teflon AF, Hyflon AD, Fluoropel, SU8, vinylidene fluoride-trifluoroethylene-chlorofluoroethylene (P (VDF-TrFE-CFE)), cycloolefin polymer resin.

13. An organic thin film transistor prepared by the method of any one of claims 1 to 12.

14. An organic thin film transistor comprising a substrate, a back gate, an organic back gate dielectric layer, a source electrode, a drain electrode, an organic semiconductor channel layer, an organic top gate dielectric layer, and a top gate;

the back gate is positioned on the substrate, and a part of the back gate is used as a bridging point of upper and lower layer metal interconnection; the organic back gate dielectric layer covers the back gate and part of the substrate, and the bridging point is exposed;

the source electrode and the drain electrode are arranged on the organic back gate dielectric layer at intervals;

the organic semiconductor channel layer covers a portion of the source or drain electrode and a portion of the organic back gate dielectric layer;

the top gate completely covers the organic top gate dielectric layer.

15. An organic thin film transistor as claimed in claim 14, further comprising a substrate, the base being disposed on the substrate; the substrate is a flexible substrate.

16. An organic thin film transistor according to claim 14, further comprising a first passivation layer, an interconnection layer, a second passivation layer, and a top pixel electrode;

wherein the first passivation layer is arranged on one surface of the organic thin film transistor far away from the substrate, and exposes the bridge contact, part of the top gate and part of the source electrode or the drain electrode;

the back gate with the bridge connection point exposed is connected with the top gate through the interconnection layer, the source electrode or the drain electrode is connected with the top pixel electrode through the interconnection layer, and the interconnection layer part connected with the source electrode or the drain electrode is disconnected with the interconnection layer of other parts;

the second passivation layer is disposed between the interconnection layer and the top pixel electrode, and exposes a portion of the interconnection layer connected to the source electrode or the drain electrode.

17. An organic thin film transistor as claimed in claim 16, wherein the organic back gate dielectric layer exposes a portion of the substrate not covered by the top gate.

18. An organic thin film transistor according to any of claims 14 to 17, wherein the organic semiconductor channel layer material is selected from a small molecule or high molecular type organic semiconductor material; preferably, the small molecule type organic semiconductor material is selected from one or more of the following materials: triphenylamine organic semiconductors, polyacene organic semiconductors, fullerene, phthalocyanine, perylene derivative organic semiconductors, or cyanine organic semiconductors; the high molecular type organic semiconductor material is selected from one or more of the following materials: polyacetylene-type organic semiconductors, polyaromatic ring-type organic semiconductors, or copolymer-type organic semiconductors.

19. An organic thin film transistor according to claim 16 or 17, wherein the material of the organic back gate dielectric layer, the organic top gate dielectric layer, the first passivation layer and the second passivation layer are each independently selected from one or more of the following: perfluoro (1-butenyl vinyl ether) polymer, Teflon AF, Hyflon AD, Fluoropel, SU8, vinylidene fluoride-trifluoroethylene-chlorofluoroethylene (P (VDF-TrFE-CFE)), cycloolefin polymer resin.

20. An organic thin film transistor as claimed in claim 16 or 17, wherein the material of the back gate, the top gate, the interconnect layer and the top pixel electrode are each independently selected from one or more of the following: au, Ag, Ti, Al, Mo or ITO.