WO2023221506A1 - 公共电压校正电路、显示面板和显示装置 - Google Patents

公共电压校正电路、显示面板和显示装置 Download PDF

Info

Publication number
WO2023221506A1
WO2023221506A1 PCT/CN2022/141162 CN2022141162W WO2023221506A1 WO 2023221506 A1 WO2023221506 A1 WO 2023221506A1 CN 2022141162 W CN2022141162 W CN 2022141162W WO 2023221506 A1 WO2023221506 A1 WO 2023221506A1
Authority
WO
WIPO (PCT)
Prior art keywords
voltage
offset
circuit
preset gray
correction
Prior art date
Application number
PCT/CN2022/141162
Other languages
English (en)
French (fr)
Inventor
李德怀
李荣荣
Original Assignee
惠科股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 惠科股份有限公司 filed Critical 惠科股份有限公司
Publication of WO2023221506A1 publication Critical patent/WO2023221506A1/zh

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/041—Temperature compensation

Definitions

  • the present application relates to the technical field of display panels, and in particular to a common voltage correction circuit, a display panel and a display device.
  • the liquid crystal layer in the LCD panel will have a DC bias voltage, so that the rotation degree of the liquid crystal molecules cannot correctly change with the change of the driving voltage difference, resulting in the LCD panel The display effect is poor.
  • the main purpose of this application is to provide a public voltage correction circuit, aiming to solve the problem of ambient temperature affecting the display effect of the liquid crystal display panel.
  • the common voltage correction circuit proposed in this application is applied to a display panel.
  • the display panel includes: a common electrode line, a gray-scale voltage generating circuit and a common voltage generating circuit.
  • the gray-scale voltage generating circuit is used to output The first preset gray scale voltage and the second preset gray scale voltage
  • the common voltage generation circuit is used to output a common voltage to the common electrode line
  • the common voltage correction circuit includes:
  • Offset detection circuit the first input end and the second input end of the offset detection circuit are respectively connected to the gray scale voltage generating circuit to respectively access the first preset gray scale voltage and the second preset gray scale voltage. step voltage, the offset detection circuit is used to determine the degree of DC offset affected by the ambient temperature at both ends of the liquid crystal layer based on the first preset gray scale voltage and the second preset gray scale voltage, and output the offset shift detection signal; and,
  • Correction voltage generation circuit the input end of the correction voltage generation circuit is connected to the output end of the offset detection circuit, the output end of the correction voltage generation circuit is connected to the common electrode line, the correction voltage generation circuit is According to the offset detection signal, a corresponding correction voltage is generated and output to the common electrode line to correct the common voltage received by the common electrode line until both ends of the liquid crystal layer are affected by the ambient temperature. DC offset is eliminated.
  • the offset detection circuit includes:
  • a first offset detection circuit the input end of the first offset detection circuit is used to access the first preset gray scale voltage, and the first offset detection circuit is used to adjust the voltage according to the first preset gray scale voltage. step voltage, determine the DC offset degree of the first preset gray-scale voltage, and output a first offset degree detection signal;
  • a second offset detection circuit the input end of the first offset detection circuit is used to connect to the second preset gray scale voltage, and the second offset detection circuit is used to detect the second preset gray scale voltage according to the second offset detection circuit. step voltage, determine the DC offset degree of the second preset gray-scale voltage, and output a second offset degree detection signal; and,
  • the DC offset determination circuit is used to determine the DC offset degree affected by the ambient temperature at both ends of the liquid crystal layer based on the first offset degree detection signal and the second offset degree detection signal, and output the offset degree. shift detection signal.
  • the input terminal of the first offset detection circuit includes a positive input terminal and a negative input terminal
  • the first offset detection circuit includes: a first resistor, a second resistor, a third resistor, a fourth resistor, and a first resistor. resistors and the first operational amplifier;
  • the first end of the first resistor is the positive input end of the first offset detection circuit, the second end of the first resistor, the inverting input end of the first operational amplifier, and the second resistor
  • the first end of the second resistor is interconnected, the second end of the second resistor is connected to the output end of the first operational amplifier, and the output end of the first operational amplifier is the output end of the first offset detection circuit
  • the first end of the third resistor is the negative input end of the first offset detection circuit, the second end of the third resistor, the positive input end of the first operational amplifier, the fourth resistor
  • the first end of the fourth resistor is interconnected, and the second end of the fourth resistor is grounded.
  • the input terminal of the second offset detection circuit includes a positive input terminal and a negative input terminal
  • the second offset detection circuit includes: a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, resistor and second operational amplifier;
  • the first end of the fifth resistor is the positive input end of the second offset detection circuit, the second end of the fifth resistor, the inverting input end of the second operational amplifier, the sixth resistor
  • the first end of the sixth resistor is interconnected, the second end of the sixth resistor is connected to the output end of the second operational amplifier, and the output end of the second operational amplifier is the output end of the second offset detection circuit
  • the first end of the seventh resistor is the negative input end of the second offset detection circuit, the second end of the seventh resistor, the positive input end of the second operational amplifier, and the eighth resistor
  • the first end of the eighth resistor is interconnected, and the second end of the eighth resistor is grounded.
  • the DC offset determination circuit includes:
  • a third operational amplifier, the non-inverting input terminal, the inverting input terminal and the output terminal of the third operational amplifier are respectively the first input terminal, the second input terminal and the output terminal of the DC bias determination circuit.
  • the correction voltage generating circuit includes:
  • a memory that stores a preset DC offset degree-preset correction voltage value mapping table
  • Correction voltage generation circuit the input end of the correction voltage generation circuit is connected to the output end of the offset detection circuit, the data end of the correction voltage generation circuit is communicatively connected with the memory, the correction voltage generation circuit is used to According to the offset detection signal, the preset DC offset degree-preset correction voltage value mapping table is called to find the preset correction voltage value corresponding to the offset detection signal, and generate and output the corresponding correction Voltage;
  • a digital-to-analog conversion circuit the input end of the digital-to-analog conversion circuit is connected to the output end of the correction voltage generation circuit, the output end of the digital-to-analog conversion circuit is the output end of the correction voltage generation circuit, and the digital-to-analog conversion circuit
  • the conversion circuit is used to perform digital-to-analog conversion on the connected correction voltage and then output it.
  • the common voltage correction circuit further includes:
  • Buffer circuit the first input terminal and the second input terminal of the buffer circuit are respectively connected to the output terminal of the correction voltage generating circuit and the output terminal of the common voltage generating circuit, and the output terminal of the buffer circuit is connected to the The common electrode line is connected, and the buffer circuit is used to correct the common voltage according to the correction voltage, buffer the corrected common voltage, and then output it to the common electrode line.
  • This application also proposes a display panel, which includes:
  • a gray-scale voltage generating circuit for outputting a first preset gray-scale voltage and a second preset gray-scale voltage
  • a common voltage generating circuit connected to the common electrode line, for outputting a common voltage to the common electrode line:
  • the common voltage correction circuit is respectively connected to the common electrode line, the gray scale voltage generating circuit and the common voltage generating circuit.
  • the gray-scale voltage generating circuit is used to output N channels of preset gray-scale voltages, where N is a positive integer;
  • the preset gray-scale voltage with the smallest voltage value among the N preset gray-scale voltages is the first preset gray-scale voltage
  • the preset gray-scale voltage with the largest voltage value among the N preset gray-scale voltages is The gray scale voltage is the second preset gray scale voltage.
  • This application also proposes a display device, which includes the above-mentioned display panel.
  • the technical solution of this application uses an offset detection circuit to determine the degree of DC offset affected by the ambient temperature at both ends of the liquid crystal layer based on the first preset gray scale voltage and the second preset gray scale voltage, and output the offset.
  • the detection signal is sent to the correction voltage generation circuit, so that the correction voltage generation circuit generates a corresponding correction voltage and outputs it to the common electrode line to correct the common voltage received by the common electrode line, so that the corrected common voltage can be Neutralize the DC bias voltage caused by excess impurity charges, thereby eliminating the impact of the DC bias voltage on the liquid crystal molecules, that is, eliminating the degree of DC offset affected by the ambient temperature at both ends of the liquid crystal layer, thereby solving the problem This solves the problem of ambient temperature affecting the display effect of the LCD panel.
  • the technical solution of this application is to automatically obtain two preset gray-scale voltages to eliminate DC offset. There is no need to set up an environmental temperature detection module, which is conducive to reducing the PCB area occupied by the public voltage correction circuit of this application. Since it is automatically obtained, This application can also automatically correct the public voltage in real time as the ambient temperature changes, so as to completely minimize the impact of the ambient temperature on the liquid crystal layer, thus helping to improve the display stability of the LCD panel in the full use temperature range. sex.
  • Figure 1 is a module schematic diagram of an embodiment of the public voltage correction circuit of the present application.
  • Figure 2 is a module schematic diagram of another embodiment of the public voltage correction circuit of the present application.
  • Figure 3 is a circuit schematic diagram of another embodiment of the public voltage correction circuit of the present application.
  • Figure 4 is a module schematic diagram of an embodiment of the display panel of the present application.
  • This application proposes a common voltage correction circuit that can be applied to liquid crystal display panels.
  • the liquid crystal display panel may include: a common electrode line, a gray scale voltage generating circuit and a common voltage generating circuit.
  • the gray scale voltage generating circuit is used to output the first preset gray scale voltage and the second preset gray scale voltage.
  • the common voltage generating circuit is used to output the first preset gray scale voltage and the second preset gray scale voltage. To output the common voltage to the common electrode line.
  • an afterimage i.e., image persistence
  • the screen of the liquid crystal display device remains unchanged. You can see traces of the previous still image, which is the phenomenon of high-temperature afterimages on the LCD panel.
  • the common voltage correction circuit includes:
  • Offset detection circuit 10 the first input terminal and the second input terminal of the offset detection circuit 10 are respectively connected to the gray scale voltage generating circuit 50, so as to respectively access the first preset gray scale voltage and the second input terminal of the offset detection circuit 10.
  • the offset detection circuit 10 is used to determine the degree of DC offset affected by the ambient temperature at both ends of the liquid crystal layer according to the first preset gray-scale voltage and the second preset gray-scale voltage. , and output the offset detection signal; and,
  • Correction voltage generation circuit 20 the input terminal of the correction voltage generation circuit 20 is connected to the output terminal of the offset detection circuit 10, the output terminal of the correction voltage generation circuit 20 is connected to the common electrode line 40, the The correction voltage generation circuit 20 is used to generate a corresponding correction voltage according to the offset detection signal and output it to the common electrode line 40 to correct the common voltage VCOM received by the common electrode line 40 until the The DC offset affected by ambient temperature at both ends of the liquid crystal layer is eliminated.
  • the gray-scale voltage generating circuit 50 can output N channels of preset gray-scale voltages with successively increasing voltage values, and the number of N can be determined by the color depth (Bit) of the display panel.
  • the gray-scale voltage generation circuit 50 can output 256 preset gray-scale voltages with successively increasing voltage values.
  • the first preset gray-scale voltage has the smallest value and is used to control the liquid crystal layer accordingly. No flipping; the preset grayscale voltage value of channel 256 is the largest, which is used to control the maximum deflection of the liquid crystal layer.
  • the voltage difference between the preset gray-scale voltage with a larger voltage value and the corresponding preset gray-scale voltage with a smaller voltage value is the preset voltage difference.
  • the first preset gray-scale voltage and the second preset gray-scale voltage may be the two preset gray-scale voltages among the N preset gray-scale voltages that have a larger voltage difference or are the largest.
  • the offset detection circuit 10 can run corresponding hardware circuits or software programs or algorithms to determine, based on the first preset gray-scale voltage and the second preset gray-scale voltage, how much they are affected by the DC bias voltage at ambient temperature.
  • the degree to which both ends of the liquid crystal layer are affected by the DC bias voltage at ambient temperature that is, the degree of DC offset
  • an offset detection signal representing the degree of DC offset can be output; among which, the preset gray scale
  • the influence of voltage on DC bias voltage can be divided into positive offset (increase) and negative offset (decrease).
  • the second preset gray-scale voltage when it is determined that the first preset gray-scale voltage produces a positive offset, the second preset gray-scale voltage produces a positive offset, and the positive offset of the first preset gray-scale voltage is greater than the second preset gray-scale voltage.
  • the degree of DC offset can be a positive DC offset.
  • the offset detection circuit 10 can output an offset detection signal corresponding to the positive DC offset degree.
  • the second preset gray-scale voltage When it is determined that the first preset gray-scale voltage does not produce an offset and the second preset gray-scale voltage produces a negative offset; or when it is determined that the first preset gray-scale voltage produces a positive offset, the second preset gray-scale voltage When a positive offset is generated and the positive offset of the first preset gray-scale voltage is less than the positive offset of the second preset gray-scale voltage; or when it is determined that the first preset gray-scale voltage generates a negative offset, the When the two preset gray-scale voltages produce a negative offset, and the negative offset of the first preset gray-scale voltage is less than the negative offset of the second preset gray-scale voltage, the DC offset level can be a negative DC offset level.
  • the offset detection circuit 10 can output an offset detection signal corresponding to the degree of negative DC offset. It should be noted that when the first preset gray-scale voltage and the second preset gray-scale voltage both produce positive or negative offsets, and the positive or negative offsets of the two are equal, even if this When there is a DC bias voltage at both ends of the liquid crystal layer, the voltage difference between the first preset gray scale voltage and the second preset gray scale voltage is still the preset voltage difference, that is, the DC offset degree can be zero DC offset at this time. At this time, the offset detection circuit 10 can output an offset detection signal corresponding to a zero DC offset degree.
  • the correction voltage generation circuit 20 can run corresponding hardware circuits or software programs and algorithms to analyze and calculate the offset detection signal to obtain the DC offset degree represented by the offset detection signal, and can query the preset mapping table by calling Or run the corresponding correction voltage value calculation algorithm to further determine the correction voltage value corresponding to the offset detection signal, and generate a correction voltage value of a corresponding size and output it to the common electrode line 40 to match the common voltage VCOM currently received by the common electrode line 40 Superposition is performed so that the voltage value of the common voltage VCOM can increase, decrease, or remain unchanged accordingly, thereby realizing correction of the common voltage VCOM.
  • the correction voltage of the generated output is a positive voltage value, so that the common voltage VCOM increases; when the offset detection signal represents the degree of negative DC offset, the output is generated.
  • the correction voltage is a negative voltage value, the common voltage VCOM is reduced; when the offset detection signal represents a zero DC offset degree, the correction voltage generated and output is a zero voltage value, so that the common voltage VCOM remains unchanged.
  • Such setting allows the corrected common voltage VCOM to neutralize the DC bias voltage caused by excess impurity charges, thereby eliminating the impact of the DC bias voltage on the liquid crystal molecules, that is, eliminating the impact on both ends of the liquid crystal layer.
  • the degree of DC offset affected by the ambient temperature thus solves the problem of the ambient temperature affecting the display effect of the LCD panel.
  • the technical solution of this application is to automatically obtain two preset gray-scale voltages to eliminate DC offset. There is no need to set up an environmental temperature detection module, which is conducive to reducing the PCB area occupied by the public voltage correction circuit of this application.
  • This application solution can also automatically correct the common voltage VCOM in real time as the ambient temperature changes, so as to minimize the impact of the ambient temperature on the liquid crystal layer, thus helping to improve the display performance of the liquid crystal display panel in the full use temperature range. stability.
  • the offset detection circuit 10 includes:
  • a first offset detection circuit 11 The input terminal of the first offset detection circuit 11 is used to access the first preset gray scale voltage.
  • the first offset detection circuit 11 is used to adjust the first offset detection circuit 11 according to the first offset detection circuit 11. Preset gray-scale voltage, determine the DC offset degree of the first preset gray-scale voltage, and output a first offset degree detection signal;
  • Second offset detection circuit 12 The input end of the first offset detection circuit 11 is used to access the second preset gray scale voltage.
  • the second offset detection circuit 12 is used to adjust the second offset detection circuit 12 according to the second preset gray scale voltage. Preset gray-scale voltage, determine the DC offset degree of the second preset gray-scale voltage, and output a second offset degree detection signal; and,
  • the first input terminal and the second input terminal of the DC offset determination circuit 13 are respectively connected with the output terminal of the first offset detection circuit 11 and the second offset detection circuit 12.
  • the output end is connected, and the DC offset determination circuit 13 is used to determine the DC offset degree affected by the ambient temperature at both ends of the liquid crystal layer based on the first offset degree detection signal and the second offset degree detection signal, and output the offset detection signal.
  • the first detection offset circuit can compare the connected first preset gray-scale voltage with the corresponding gray-scale voltage threshold or the preset reference voltage, and can determine the first preset gray-scale voltage according to the determination result.
  • the voltage is affected by the DC bias voltage at ambient temperature, that is, the DC offset degree of the first preset gray-scale voltage, and can generate and output a corresponding first offset degree detection signal, thereby achieving the first preset gray-scale voltage DC offset detection.
  • the second detection offset circuit can compare the connected second preset gray-scale voltage with the corresponding gray-scale voltage threshold or the preset reference voltage, and can determine based on the determination result that the second preset gray-scale voltage is affected by the ambient temperature.
  • the influence of the DC bias voltage is the degree of DC offset of the second preset gray-scale voltage, and a corresponding second offset degree detection signal can be generated and output, thereby realizing DC offset detection of the second preset gray-scale voltage.
  • the DC offset determination circuit can perform corresponding operations on the first offset detection signal and the second offset detection signal, such as addition or subtraction, and then use the operation result as the DC offset degree affected by the ambient temperature at both ends of the liquid crystal layer. And output the corresponding offset detection signal, thereby realizing the DC offset degree detection at both ends of the step liquid crystal layer.
  • the solution of this application implements the offset detection circuit 10 by using the first offset detection circuit 11, the second offset detection circuit 12 and the DC offset circuit as three independent circuits.
  • the DC offset detection of the second offset detection circuit 12 fails, the impact on the final output result of the DC offset determination circuit 13 is effectively reduced.
  • the input terminal of the first offset detection circuit 11 includes a positive input terminal and a negative input terminal.
  • the first offset detection circuit 11 includes: a first resistor R1, a second resistor R2, a third Resistor R3, fourth resistor R4 and first operational amplifier A1;
  • the first terminal of the first resistor R1 is the positive input terminal of the first offset detection circuit 11, and the second terminal of the first resistor R1 and the inverting input terminal of the first operational amplifier A1 are The first end of the second resistor R2 is interconnected, the second end of the second resistor R2 is connected to the output end of the first operational amplifier A1, and the output end of the first operational amplifier A1 is the first
  • the output terminal of the offset detection circuit 11 the first terminal of the third resistor R3 is the negative input terminal of the first offset detection circuit 11, the second terminal of the third resistor R3, the first operation terminal
  • the non-inverting input terminal of the amplifier A1 and the first terminal of the fourth resistor R4 are connected to each other, and the second terminal of the fourth resistor R4 is grounded.
  • the first end of the first resistor R1 and the first end of the third resistor R3 can be connected in one-to-one correspondence with the negative output end and the positive output end of the gray-scale voltage generating circuit 50 for outputting the first preset gray-scale voltage, so as to realize Connect to the first preset gray scale voltage.
  • the first resistor R1, the second resistor R2, the third resistor R3, the fourth resistor R4 and the first operational amplifier A1 form a subtractor, so that the first operational amplifier A1 can convert the input signal from its positive input terminal to Subtraction calculation is performed with the input signal at its inverting input end, and the subtraction calculation result can be output as the first offset degree detection signal.
  • the input terminal of the second offset detection circuit 12 includes a positive input terminal and a negative input terminal.
  • the second offset detection circuit 12 includes: a fifth resistor R5, a sixth resistor R6, a seventh resistor Resistor R7, eighth resistor R8 and second operational amplifier A2;
  • the first terminal of the fifth resistor R5 is the positive input terminal of the second offset detection circuit 12, and the second terminal of the fifth resistor R5 and the inverting input terminal of the second operational amplifier A2 are The first end of the sixth resistor R6 is connected to each other, the second end of the sixth resistor R6 is connected to the output end of the second operational amplifier A2, and the output end of the second operational amplifier A2 is the second The output end of the offset detection circuit 12, the first end of the seventh resistor R7 is the negative input end of the second offset detection circuit 12, the second end of the seventh resistor R7, the second operation The non-inverting input terminal of the amplifier A2 and the first terminal of the eighth resistor R8 are connected to each other, and the second terminal of the eighth resistor R8 is connected to ground.
  • the first end of the fifth resistor R5 and the first end of the seventh resistor R7 can be connected to the negative output end and the positive output end of the gray-scale voltage generating circuit 50 for outputting the second preset gray-scale voltage in one-to-one correspondence, so as to realize Connect to the second preset gray scale voltage.
  • the fifth resistor R5, the sixth resistor R6, the seventh resistor R7, the eighth resistor R8 and the second operational amplifier A2 form a subtractor, so that the second operational amplifier A2 can convert the input signal from its non-inverting input terminal to Subtraction calculation is performed with the input signal at its inverting input terminal, and the subtraction calculation result can be output as the second offset degree detection signal.
  • the DC offset determination circuit 13 includes:
  • the third operational amplifier A3 has a non-inverting input terminal, an inverting input terminal and an output terminal respectively being the first input terminal, the second input terminal and the output terminal of the DC bias determination circuit 13 .
  • the third operational amplifier A3 functions as a comparator to compare the first offset degree detection signal with the second offset degree detection signal, and can use the corresponding level signal as an offset detection signal according to the comparison result. signal output. Specifically: when the comparison result is that the first offset degree detection signal is greater than the second offset degree detection signal, an offset detection signal with a high level signal is output to represent the positive DC offset degree; when the comparison result is that the first offset degree detection signal is When the shift degree detection signal is smaller than the second shift degree detection signal, an offset detection signal with a low level signal is output, and an offset detection signal with a low level signal is output to represent the negative DC offset degree.
  • the correction voltage generating circuit 20 includes:
  • the memory 21 stores a preset DC offset degree-preset correction voltage value mapping table
  • Correction voltage generation circuit 22 The input terminal of the correction voltage generation circuit 22 is connected to the output terminal of the offset detection circuit 10. The data terminal of the correction voltage generation circuit 22 is communicatively connected with the memory 21. The correction voltage generation circuit 22 has an input terminal connected to the output terminal of the offset detection circuit 10. The voltage generation circuit 22 is configured to call the preset DC offset degree-preset correction voltage value mapping table according to the offset detection signal to find the preset correction voltage value corresponding to the offset detection signal, And generate and output the corresponding correction voltage;
  • Digital-to-analog conversion circuit 23 The input terminal of the digital-to-analog conversion circuit 23 is connected to the output terminal of the correction voltage generation circuit 22.
  • the output terminal of the digital-to-analog conversion circuit 23 is the output terminal of the correction voltage generation circuit 20.
  • the digital-to-analog conversion circuit 23 is used to perform digital-to-analog conversion on the accessed correction voltage and then output it.
  • the memory 21 may pre-store a plurality of preset DC offset levels and a plurality of preset correction voltage values, and each preset DC offset level may be stored in association with a preset correction voltage value to form a preset Set the DC offset degree-preset correction voltage value mapping table.
  • Each preset DC offset degree, each correction voltage value, and the corresponding relationship between the two can be obtained through a large number of preliminary experiments, and are not limited here.
  • the correction voltage generating circuit 22 may be implemented using a processor or a flip-flop circuit. After determining the DC offset degree corresponding to the offset detection signal, the correction voltage generation circuit 22 can call the preset DC offset degree-preset correction voltage value mapping table to look up the table to obtain the DC offset degree corresponding to or closest to the DC offset degree.
  • the preset DC offset degree and the corresponding preset correction voltage value can also run corresponding hardware circuits or software programs and algorithms to generate and output a correction voltage with a preset correction voltage value to the digital-to-analog conversion circuit 23 to be converted into an analog signal by the digital-to-analog conversion circuit 23 and then output.
  • the memory 21 is implemented by RAM, and the correction voltage generating circuit 22 includes a rising edge triggered D flip-flop U1 .
  • the clock terminal of the D flip-flop U1 is the input terminal of the correction voltage generating circuit 22, and the D terminal is the data terminal, so that when the offset detection signal of the high-level signal output by the third operational amplifier A3 is received, the output of the memory 21 is connected.
  • the high-level signal of the digital signal is output as a correction voltage, thereby generating and outputting a correction voltage with a positive voltage value.
  • the correction voltage generation circuit 22 may further include a falling edge triggered D flip-flop U1.
  • the clock terminals of two D flip-flops U1 are interconnected to form the input terminal of the correction voltage generation circuit 22.
  • the two D flip-flops U1 The D terminals of the flip-flop U1 are respectively connected to the memory 21, so that when the offset detection signal of the low-level signal output by the third operational amplifier A3 is received, the falling edge triggered D flip-flop U1 is connected to the output of the memory 21.
  • the low-level signal of the digital signal is output as a correction voltage, thereby generating and outputting a correction voltage with a negative voltage value.
  • the solution of this application can quickly obtain the corresponding correction voltage value by looking up the table. Compared with using a programmable device to calculate the correction voltage value in real time, it is less affected by the ambient temperature and is more convenient for high-brush design of the display device.
  • the common voltage correction circuit further includes:
  • Buffer circuit 30 The first input terminal and the second input terminal of the buffer circuit 30 are respectively connected to the output terminal of the correction voltage generation circuit 20 and the output terminal of the common voltage generation circuit 60.
  • the buffer circuit 30 has The output terminal is connected to the common electrode line 40.
  • the buffer circuit 30 is used to correct the common voltage VCOM according to the correction voltage, buffer the corrected common voltage VCOM, and then output it to the the common electrode line 40.
  • the solution of this application is designed with a buffer circuit 30.
  • the buffer circuit 30 is used to correct the common voltage VCOM according to the correction voltage, and the corrected common voltage VCOM is buffered and output as a signal. It should be noted that with this arrangement, even if there is no correction voltage, the common electrode line 40 is connected to the common voltage VCOM that has been buffered by the signal of the buffer circuit 30. Therefore, when the correction voltage is superimposed midway, the voltage on the common electrode line 40 can be effectively reduced. The fluctuation of the common voltage VCOM is beneficial to improving the stability of the display.
  • the buffer circuit 30 includes a ninth resistor R9 , a tenth resistor R10 , an eleventh resistor R11 , a twelfth resistor R12 and a fourth operational amplifier; the first end of the ninth resistor R9 and the fourth operational amplifier
  • the first terminal of the tenth resistor R10 is respectively the first input terminal and the second input terminal of the buffer circuit 30, the second terminal of the ninth resistor R9, the first terminal of the tenth resistor R10 and the non-inverting input terminal of the fourth operational amplifier.
  • the inverting input terminal of the output terminal of the fourth operational amplifier, the second terminal of the eleventh resistor R11 and the first terminal of the twelfth resistor R12 are interconnected, and the tenth
  • the first end of a resistor R11 is connected to the output end of the fourth operational amplifier
  • the second end of the twelfth resistor R12 is connected to the preset voltage
  • the output end of the fourth operational amplifier is the output end of the buffer circuit 30 .
  • This application also proposes a display panel.
  • the display panel includes a common electrode line 40 , a gray-scale voltage generation circuit 50 and a common voltage correction circuit.
  • the specific structure of the common voltage correction circuit refers to the above-mentioned embodiments. Since this display panel adopts all the features of all the above-mentioned embodiments, The technical solution therefore at least has all the beneficial effects brought by the technical solution of the above embodiments, and will not be described again one by one.
  • the gray scale voltage generating circuit 50 is used to output the first preset gray scale voltage and the second preset gray scale voltage
  • the common voltage generating circuit 60 is connected to the common electrode line 40 and is used to output the common voltage VCOM to the common electrode. line
  • the common voltage correction circuit is respectively connected to the common electrode line 40, the gray scale voltage generating circuit 50 and the common voltage generating circuit 60 to respectively access the first preset gray scale voltage, the second preset gray scale voltage and the common voltage. VCOM, and output the corrected common voltage VCOM value to the common electrode line 40 .
  • the gray-scale voltage generating circuit 50 is used to output N channels of preset gray-scale voltages, where N is a positive integer;
  • the preset gray-scale voltage with the smallest voltage value among the N preset gray-scale voltages is the first preset gray-scale voltage
  • the preset gray-scale voltage with the largest voltage value among the N preset gray-scale voltages is The gray scale voltage is the second preset gray scale voltage.
  • N is 256, in which the voltage value of the first preset gray-scale voltage is the maximum voltage value, that is, the 0th-level preset gray-scale voltage V0, and the remaining 256 preset gray-scale voltages are It is assumed that the gray-scale voltage can be continuously obtained by dividing the previous gray-scale voltage, so the voltage value of the 256th preset gray-scale voltage is the minimum voltage value, which is the 255th-level preset gray-scale voltage V255.
  • the color depth of the display panel can also be designed as 6Bit, 10Bit or 12Bit, which is not limited here.
  • This application plan selects the last preset gray level voltage with the smallest voltage value and the 0th level preset gray level voltage with the largest voltage value among the N preset gray level voltages as the first preset gray level voltage and the third preset gray level voltage respectively.
  • the second preset gray-scale voltage is helpful to improve the accuracy of detecting the DC offset degree at both ends of the liquid crystal layer.
  • This application also proposes a display device, which includes a common electrode line 40, a gray-scale voltage generation circuit 50 and a common voltage correction circuit.
  • the specific structure of the common voltage correction circuit refers to the above embodiment. Since this display device adopts the above-mentioned All technical solutions of all embodiments, therefore at least have all the beneficial effects brought by the technical solutions of the above embodiments, will not be described again one by one here.

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

公开了一种公共电压校正电路、显示面板和显示装置，其中，公共电压校正电路包括: 偏移检测电路(10)用于根据第一预设灰阶电压和第二预设灰阶电压，确定液晶层两端受环境温度影响的直流偏移程度，并输出偏移检测信号；以及，校正电压产生电路(20)用于根据该偏移检测信号，生成相应的校正电压并输出至公共电极线(40)，以对公共电极线(40)接收到的公共电压(VCOM)进行校正，直至液晶层两端受环境温度影响的直流偏移程度消除。

Description

公共电压校正电路、显示面板和显示装置
相关申请
本申请要求于2022年5月17日申请的、申请号为202210532067.4的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示面板技术领域，特别涉及一种公共电压校正电路、显示面板和显示装置。
 背景技术
目前，在高温或者低温的环境温度下，液晶显示面板中的液晶层会存在直流偏置电压，以使得液晶分子的旋转程度不能正确地随着驱动电压差的改变而改变，从而导致液晶显示面板的显示效果较差。
 技术问题
本申请的主要目的是提供一种公共电压校正电路，旨在解决环境温度影响液晶显示面板显示效果的问题。
为实现上述目的，本申请提出的公共电压校正电路，应用于显示面板，所述显示面板包括：公共电极线、灰阶电压产生电路和公共电压产生电路，所述灰阶电压产生电路用于输出第一预设灰阶电压和第二预设灰阶电压，所述公共电压产生电路用于输出公共电压至所述公共电极线，所述公共电压校正电路包括：
偏移检测电路，所偏移检测电路的第一输入端和第二输入端分别与所述灰阶电压产生电路连接，以分别接入所述第一预设灰阶电压和第二预设灰阶电压，所述偏移检测电路用于根据所述第一预设灰阶电压和所述第二预设灰阶电压，确定液晶层两端受环境温度影响的直流偏移程度，并输出偏移检测信号；以及，
校正电压产生电路，所述校正电压产生电路的输入端与所述偏移检测电路的输出端连接，所述校正电压产生电路的输出端与所述公共电极线连接，所述校正电压产生电路用于根据所述偏移检测信号，生成相应的校正电压并输出至所述公共电极线，以对所述公共电极线接收到的公共电压进行校正，直至所述液晶层两端受环境温度影响的直流偏移程度消除。
在一实施例中，所述偏移检测电路包括：
第一偏移检测电路，所述第一偏移检测电路的输入端用于接入所述第一预设灰阶电压，所述第一偏移检测电路用于根据所述第一预设灰阶电压，确定所述第一预设灰阶电压的直流偏移程度，并输出第一偏移程度检测信号；
第二偏移检测电路，所述第一偏移检测电路的输入端用于接入所述第二预设灰阶电压，所述第二偏移检测电路用于根据所述第二预设灰阶电压，确定所述第二预设灰阶电压的直流偏移程度，并输出第二偏移程度检测信号；以及，
直流偏置确定电路，所述直流偏置确定电路的第一输入端和第二输入端分别与所述第一偏移检测电路的输出端和所述第二偏移检测电路的输出端连接，所述直流偏置确定电路用于根据所述第一偏移程度检测信号和所述第二偏移程度检测信号，确定液晶层两端受环境温度影响的直流偏移程度，并输出所述偏移检测信号。
在一实施例中，所述第一偏移检测电路的输入端包括正极输入端和负极输入端，所述第一偏移检测电路包括：第一电阻、第二电阻、第三电阻、第四电阻以及第一运算放大器；
所述第一电阻的第一端为所述第一偏移检测电路的正极输入端，所述第一电阻的第二端、所述第一运算放大器的反相输入端、所述第二电阻的第一端互连，所述第二电阻的第二端与所述第一运算放大器的输出端连接，所述第一运算放大器的输出端为所述第一偏移检测电路的输出端，所述第三电阻的第一端为所述第一偏移检测电路的负极输入端，所述第三电阻的第二端、所述第一运算放大器的正相输入端、所述第四电阻的第一端互连，所述第四电阻的第二端接地。
在一实施例中，所述第二偏移检测电路的输入端包括正极输入端和负极输入端，所述第二偏移检测电路包括：第五电阻、第六电阻、第七电阻、第八电阻以及第二运算放大器；
所述第五电阻的第一端为所述第二偏移检测电路的正极输入端，所述第五电阻的第二端、所述第二运算放大器的反相输入端、所述第六电阻的第一端互连，所述第六电阻的第二端与所述第二运算放大器的输出端连接，所述第二运算放大器的输出端为所述第二偏移检测电路的输出端，所述第七电阻的第一端为所述第二偏移检测电路的负极输入端，所述第七电阻的第二端、所述第二运算放大器的正相输入端、所述第八电阻的第一端互连，所述第八电阻的第二端接地。
在一实施例中，所述直流偏置确定电路包括：
第三运算放大器，所述第三运算放大器的正相输入端、反相输入端、输出端分别为所述直流偏置确定电路的第一输入端、第二输入端、输出端。
在一实施例中，所述校正电压产生电路包括：
存储器，存储有预设直流偏移程度-预设校正电压值映射表；
校正电压生成电路，所述校正电压生成电路的输入端与所述偏移检测电路的输出端连接，所述校正电压生成电路的数据端与所述存储器通信连接，所述校正电压生成电路用于根据所述偏移检测信号，调用所述预设直流偏移程度-预设校正电压值映射表，以查找得到与所述偏移检测信号对应的预设校正电压值，并生成输出相应的校正电压；
数模转换电路，所述数模转换电路的输入端与所述校正电压生成电路的输出端连接，所述数模转换电路的输出端为所述校正电压产生电路的输出端，所述数模转换电路用于对接入的所述校正电压进行数模转换后输出。
在一实施例中，所述公共电压校正电路还包括：
缓冲电路，所述缓冲电路的第一输入端和第二输入端分别与所述校正电压产生电路的输出端和所述公共电压产生电路的输出端连接，所述缓冲电路的输出端与所述公共电极线连接，所述缓冲电路用于根据所述校正电压对所述公共电压进行校正，并将校正后的所述公共电压进行信号缓冲后，输出至所述公共电极线。
本申请还提出一种显示面板，所述显示面板包括：
公共电极线；
灰阶电压产生电路，用于输出第一预设灰阶电压和第二预设灰阶电压；
公共电压产生电路，与所述公共电极线连接，用于输出公共电压至所述公共电极线：以及，
如上述的公共电压校正电路，所述公共电压校正电路分别与所述公共电极线、所述灰阶电压产生电路和所述公共电压产生电路连接。
在一实施例中，所述灰阶电压产生电路用于输出N路预设灰阶电压，N为正整数；
所述N路预设灰阶电压中电压值最小的该路预设灰阶电压为所述第一预设灰阶电压，所述N路预设灰阶电压中电压值最大的该路预设灰阶电压为所述第二预设灰阶电压。
本申请还提出一种显示装置，所述显示装置包括如上述的显示面板。
本申请技术方案通过采用偏移检测电路根据所述第一预设灰阶电压和所述第二预设灰阶电压，确定液晶层两端受环境温度影响的直流偏移程度，并输出偏移检测信号至校正电压产生电路，以使校正电压产生电路生成相应的校正电压并输出至所述公共电极线，以对所述公共电极线接收到的公共电压进行校正，使得校正后的公共电压可对因多余杂质电荷而带来的直流偏置电压进行中和，从而消除了直流偏置电压对于液晶分子的影响，也即消除了液晶层两端受环境温度影响的直流偏移程度，进而解决了环境温度影响液晶显示面板显示效果的问题。此外，本申请技术方案为自动获取两路预设灰阶电压来消除直流偏移，无需设置环境温度检测模块，有利于降低本申请公共电压校正电路所占的PCB面积，且由于为自动获取，使得本申请还可随着环境温度的变换，自动对公共电压进行实时校正，以彻底将环境温度对于液晶层的影响降至最低，因而有利于提高液晶显示面板在全使用温度区间下的显示稳定性。
 附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图示出的结构获得其他的附图。
图1为本申请公共电压校正电路一实施例的模块示意图；
图2为本申请公共电压校正电路另一实施例的模块示意图；
图3为本申请公共电压校正电路又一实施例的电路示意图；
图4为本申请显示面板一实施例的模块示意图。
本申请目的的实现、功能特点及优点将结合实施例，参照附图做进一步说明。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请的一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
另外，在本申请中如涉及“第一”、“第二”等的描述仅用于描述目的，而不能理解为指示或暗示其相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括至少一个该特征。另外，各个实施例之间的技术方案可以相互结合，但是必须是以本领域普通技术人员能够实现为基础，当技术方案的结合出现相互矛盾或无法实现时应当认为这种技术方案的结合不存在，也不在本申请要求的保护范围之内。
实施例一：
本申请提出一种公共电压校正电路，可应用于液晶显示面板。
液晶显示面板可包括：公共电极线、灰阶电压产生电路和公共电压产生电路，灰阶电压产生电路用于输出第一预设灰阶电压和第二预设灰阶电压，公共电压产生电路用于输出公共电压至公共电极线。当液晶显示面板处于高温或低温的环境温度中时，TFT特性偏移，电子迁移率等特性发生变化，使得液晶盒中存在的不必要的杂质电荷变多，以导致液晶层两侧存在直流偏置电压，液晶分子的旋转程度将不再能够正确地随着驱动电压差的改变而改变。例如，在高温的环境温度中使用液晶显示装置持续显示同一幅静止画面一段时间后，有可能会出现残像（即影像残留），此时，即便改变显示画面的内容，液晶显示装置的屏幕上仍然可以看到之前的静止图像的痕迹，这就是液晶显示面板的高温残像的现象。
针对此问题，参照图1至图3，在一实施例中，所述公共电压校正电路包括：
偏移检测电路10，所偏移检测电路10的第一输入端和第二输入端分别与所述灰阶电压产生电路50连接，以分别接入所述第一预设灰阶电压和第二预设灰阶电压，所述偏移检测电路10用于根据所述第一预设灰阶电压和所述第二预设灰阶电压，确定液晶层两端受环境温度影响的直流偏移程度，并输出偏移检测信号；以及，
校正电压产生电路20，所述校正电压产生电路20的输入端与所述偏移检测电路10的输出端连接，所述校正电压产生电路20的输出端与所述公共电极线40连接，所述校正电压产生电路20用于根据所述偏移检测信号，生成相应的校正电压并输出至所述公共电极线40，以对所述公共电极线40接收到的公共电压VCOM进行校正，直至所述液晶层两端受环境温度影响的直流偏移程度消除。
需要说明的是，灰阶电压产生电路50可输出电压值依次增大的N路预设灰阶电压，N的数量可由显示面板的色深（Bit）来决定。例如：在8Bit的显示面板中，灰阶电压产生电路50可输出电压值依次增大的256路预设灰阶电压，其中，第1路预设灰阶电压值最小，用以对应控制液晶层不翻转；第256路预设灰阶电压值最大，用以控制液晶层发生最大程度偏转。在正常温度下，N路预设灰阶电压中，较大电压值的预设灰阶电压和对应的较小电压值的预设灰阶电压二者的电压差值为预设电压差值，例如：第一路预设灰阶电压和第256路预设灰阶电压的电压差值；或者，第二路预设灰阶电压和第255路预设灰阶电压的电压差值；或者，第三路预设灰阶电压和第254路预设灰阶电压的电压差值等。因而如若液晶层两端存在直流偏置电压，会体现在上述预设电压差值上，即会使得预设电压差值发生变化，因此偏移检测电路10可通过检测第一预设灰阶电压和第二预设灰阶电压，来实现对液晶层两端直流偏置电压的检测。
本实施例中，第一预设灰阶电压和第二预设灰阶电压可为N路预设灰阶电压中电压差值较大或者最大的两路预设灰阶电压。偏移检测电路10可运行相应的硬件电路或者软件程序或算法，根据第一预设灰阶电压和第二预设灰阶电压，分别确定二者在环境温度下受直流偏置电压的影响大小，以及可根据确定结果进一步确定液晶层两端整体受环境温度下直流偏置电压的影响程度，即直流偏移程度，并输出表征直流偏移程度的偏移检测信号；其中，预设灰阶电压受直流偏置电压的影响大小可分为正偏移（增大）和负偏移（降低）。
具体为：当确定第一预设灰阶电压产生正偏移，第二预设灰阶电压产生正偏移，且第一预设灰阶电压的正偏移量大于第二预设灰阶电压的正偏移量时；或者，当确定第一预设灰阶电压产生正偏移，第二预设灰阶电压不产生偏移或者产生负偏移时，直流偏移程度可为正直流偏移程度，此时偏移检测电路10可输出与正直流偏移程度对应的偏移检测信号。当确定第一预设灰阶电压不产生偏移，第二预设灰阶电压产生负偏移时；或者，当确定第一预设灰阶电压产生正偏移，第二预设灰阶电压产生正偏移，且第一预设灰阶电压的正偏移量小于第二预设灰阶电压的正偏移量时；或者，当确定第一预设灰阶电压产生负偏移，第二预设灰阶电压产生负偏移，且第一预设灰阶电压的负偏移量小于第二预设灰阶电压的负偏移量时，直流偏移程度可为负直流偏移程度，此时偏移检测电路10可输出与负直流偏移程度对应的偏移检测信号。需要额外说明的是，当第一预设灰阶电压和第二预设灰阶电压均产生正偏移或者负偏移，且二者的正偏移量或者负偏移量相等时，即便此时液晶层两端存在直流偏置电压，但第一预设灰阶电压和第二预设灰阶电压的电压差依然为预设电压差值，即此时直流偏移程度可为零直流偏移程度，此时偏移检测电路10可输出表征零直流偏移程度对应的偏移检测信号。
校正电压产生电路20可运行相应的硬件电路或软件程序和算法，以对偏移检测信号进行分析运算，以得到偏移检测信号表征的直流偏移程度，并可通过调用查询预设的映射表或者运行相应的校正电压值计算算法，进一步确定与偏移检测信号对应校正电压值，并生成相应大小的校正电压值输出至公共电极线40，以与公共电极线40当前接收到的公共电压VCOM进行叠加，使得公共电压VCOM的电压值可对应增大、减小或者不变，从而实现对公共电压VCOM的校正。具体为：当偏移检测信号表征正直流偏移程度，则生成输出的校正电压为正电压值时，以使公共电压VCOM增大；当偏移检测信号表征负直流偏移程度，则生成输出的校正电压为负电压值时，以使公共电压VCOM减小；当偏移检测信号表征零直流偏移程度，则生成输出的校正电压为零电压值时，以使公共电压VCOM不变。
如此设置，使得校正后的公共电压VCOM可对因多余杂质电荷而带来的直流偏置电压进行中和，从而消除了直流偏置电压对于液晶分子的影响，也即消除了液晶层两端受环境温度影响的直流偏移程度，进而解决了环境温度影响液晶显示面板显示效果的问题。此外，本申请技术方案为自动获取两路预设灰阶电压来消除直流偏移，无需设置环境温度检测模块，有利于降低本申请公共电压校正电路所占的PCB面积，且由于为自动获取，使得本申请方案还可随着环境温度的变换，自动对公共电压VCOM进行实时校正，以将环境温度对于液晶层的影响降至最低，因而有利于提高液晶显示面板在全使用温度区间下的显示稳定性。
参照图1至图3，在一实施例中，所述偏移检测电路10包括：
第一偏移检测电路11，所述第一偏移检测电路11的输入端用于接入所述第一预设灰阶电压，所述第一偏移检测电路11用于根据所述第一预设灰阶电压，确定所述第一预设灰阶电压的直流偏移程度，并输出第一偏移程度检测信号；
第二偏移检测电路12，所述第一偏移检测电路11的输入端用于接入所述第二预设灰阶电压，所述第二偏移检测电路12用于根据所述第二预设灰阶电压，确定所述第二预设灰阶电压的直流偏移程度，并输出第二偏移程度检测信号；以及，
直流偏置确定电路13，所述直流偏置确定电路13的第一输入端和第二输入端分别与所述第一偏移检测电路11的输出端和所述第二偏移检测电路12的输出端连接，所述直流偏置确定电路13用于根据所述第一偏移程度检测信号和所述第二偏移程度检测信号，确定液晶层两端受环境温度影响的直流偏移程度，并输出所述偏移检测信号。
本实施例中，第一检测偏移电路可将接入的第一预设灰阶电压与相应的灰阶电压阈值或者预设基准电压进行比较，并可根据确定结果确定第一预设灰阶电压受环境温度下直流偏置电压的影响大小，即第一预设灰阶电压的直流偏移程度，并可生成输出相应的第一偏移程度检测信号，从而实现第一预设灰阶电压的直流偏移检测。第二检测偏移电路可将接入的第二预设灰阶电压与相应的灰阶电压阈值或者预设基准电压进行比较，并可根据确定结果确定第二预设灰阶电压受环境温度下直流偏置电压的影响大小，即第二预设灰阶电压的直流偏移程度，并可生成输出相应的第二偏移程度检测信号，从而实现第二预设灰阶电压的直流偏移检测。直流偏置确定电路可将第一偏移检测信号和第二偏移检测信号进行相应的运算，例如加法运算或者减法运算后将运算结果作为液晶层两端受环境温度影响的直流偏移程度，并输出相应的偏移检测信号，从而实现阶液晶层两端的直流偏移程度检测。
本申请方案通过采用第一偏移检测电路11、第二偏移检测电路12和直流偏移电路三者彼此独立的电路来实现偏移检测电路10，可在第一偏移检测电路11或者第二偏移检测电路12的直流偏移检测出现故障时，有效减小对于直流偏置确定电路13最终输出结果的影响。
在一实施例中，所述第一偏移检测电路11的输入端包括正极输入端和负极输入端，所述第一偏移检测电路11包括：第一电阻R1、第二电阻R2、第三电阻R3、第四电阻R4以及第一运算放大器A1；
所述第一电阻R1的第一端为所述第一偏移检测电路11的正极输入端，所述第一电阻R1的第二端、所述第一运算放大器A1的反相输入端、所述第二电阻R2的第一端互连，所述第二电阻R2的第二端与所述第一运算放大器A1的输出端连接，所述第一运算放大器A1的输出端为所述第一偏移检测电路11的输出端，所述第三电阻R3的第一端为所述第一偏移检测电路11的负极输入端，所述第三电阻R3的第二端、所述第一运算放大器A1的正相输入端、所述第四电阻R4的第一端互连，所述第四电阻R4的第二端接地。
第一电阻R1的第一端和第三电阻R3的第一端可与灰阶电压产生电路50用于输出第一预设灰阶电压的负极输出端和正极输出端一一对应连接，以实现接入第一预设灰阶电压。本实施例中，第一电阻R1、第二电阻R2、第三电阻R3、第四电阻R4以及第一运算放大器A1组成减法器，以使第一运算放大器A1可将其正相输入端的输入信号与其反相输入端的输入信号进行减法计算，并可将减法计算结果作为第一偏移程度检测信号输出。
在一实施例中，所述第二偏移检测电路12的输入端包括正极输入端和负极输入端，所述第二偏移检测电路12包括：第五电阻R5、第六电阻R6、第七电阻R7、第八电阻R8以及第二运算放大器A2；
所述第五电阻R5的第一端为所述第二偏移检测电路12的正极输入端，所述第五电阻R5的第二端、所述第二运算放大器A2的反相输入端、所述第六电阻R6的第一端互连，所述第六电阻R6的第二端与所述第二运算放大器A2的输出端连接，所述第二运算放大器A2的输出端为所述第二偏移检测电路12的输出端，所述第七电阻R7的第一端为所述第二偏移检测电路12的负极输入端，所述第七电阻R7的第二端、所述第二运算放大器A2的正相输入端、所述第八电阻R8的第一端互连，所述第八电阻R8的第二端接地。
第五电阻R5的第一端和第七电阻R7的第一端可与灰阶电压产生电路50用于输出第二预设灰阶电压的负极输出端和正极输出端一一对应连接，以实现接入第二预设灰阶电压。本实施例中，第五电阻R5、第六电阻R6、第七电阻R7、第八电阻R8以及第二运算放大器A2组成减法器，以使第二运算放大器A2可将其正相输入端的输入信号与其反相输入端的输入信号进行减法计算，并可将减法计算结果作为第二偏移程度检测信号输出。
在一实施例中，所述直流偏置确定电路13包括：
第三运算放大器A3，所述第三运算放大器A3的正相输入端、反相输入端、输出端分别为所述直流偏置确定电路13的第一输入端、第二输入端、输出端。
本实施例中，第三运算放大器A3起比较器作用，以将第一偏移程度检测信号与第二偏移程度检测信号进行比较，并可根据比较结果将相应的电平信号作为偏移检测信号输出。具体为：当比较结果为第一偏移程度检测信号大于第二偏移程度检测信号时，输出高电平信号的偏移检测信号，以表征正直流偏移程度；当比较结果为第一偏移程度检测信号小于第二偏移程度检测信号时，输出低电平信号的偏移检测信号，输出低电平信号的偏移检测信号，以表征负直流偏移程度。
参照图1至图3，在一实施例中，所述校正电压产生电路20包括：
存储器21，存储有预设直流偏移程度-预设校正电压值映射表；
校正电压生成电路22，所述校正电压生成电路22的输入端与所述偏移检测电路10的输出端连接，所述校正电压生成电路22的数据端与所述存储器21通信连接，所述校正电压生成电路22用于根据所述偏移检测信号，调用所述预设直流偏移程度-预设校正电压值映射表，以查找得到与所述偏移检测信号对应的预设校正电压值，并生成输出相应的校正电压；
数模转换电路23，所述数模转换电路23的输入端与所述校正电压生成电路22的输出端连接，所述数模转换电路23的输出端为所述校正电压产生电路20的输出端，所述数模转换电路23用于对接入的所述校正电压进行数模转换后输出。
本实施例中，存储器21中可预存储有多个预设直流偏移程度和多个预设校正电压值，每一预设直流偏移程度可与一预设校正电压值关联存储以形成预设直流偏移程度-预设校正电压值映射表。各预设直流偏移程度和各校正电压值以及二者的对应关联关系可通过大量预先实验获取，在此不做限定。校正电压生成电路22可采用处理器或者触发器电路来实现。校正电压生成电路22可在确定偏移检测信号对应的直流偏移程度后，调用预设直流偏移程度-预设校正电压值映射表，以查表得到与直流偏移程度对应的或者最为接近的预设直流偏移程度，以及对应的预设校正电压值。校正电压生成电路22还可运行相应的硬件电路或者软件程序和算法，生成输出具有预设校正电压值的校正电压至数模转换电路23，以经数模转换电路23转换为模拟信号后输出。
在图3所述实例中，存储器21采用RAM来实现，校正电压生成电路22包括一个上升沿触发的D触发器U1来实现。D触发器U1的时钟端为校正电压生成电路22的输入端，D端为数据端，以在接收到第三运算放大器A3输出的高电平信号的偏移检测信号时，接入存储器21输出的数字信号的高电平信号并作为校正电压输出，从而实现生成输出具有正电压值的校正电压。在另一实施例中，校正电压生成电路22还可包括一个下降沿触发的D触发器U1，两个D触发器U1的时钟端互连以构成校正电压生成电路22的输入端，两个D触发器U1的D端分别与存储器21连接，如此可在接收到第三运算放大器A3输出的低电平信号的偏移检测信号时，使得下降沿触发的D触发器U1接入存储器21输出的数字信号的低电平信号并作为校正电压输出，从而实现生成输出具有负电压值的校正电压。
本申请方案通过查表以快速得到对应的校正电压值，相较于采用可编程器件实时计算校正电压值而言，受环境温度的影响更小，且更便于显示装置的高刷设计。
参照图1至图3，在一实施例中，所述公共电压校正电路还包括：
缓冲电路30，所述缓冲电路30的第一输入端和第二输入端分别与所述校正电压产生电路20的输出端和所述公共电压产生电路60的输出端连接，所述缓冲电路30的输出端与所述公共电极线40连接，所述缓冲电路30用于根据所述校正电压对所述公共电压VCOM进行校正，并将校正后的所述公共电压VCOM进行信号缓冲后，输出至所述公共电极线40。
在实际应用中发现如果直接将校正电压输出至公共电极线40来实现校正，会造成公共电极线40上公共电压VCOM的不稳定，进而影响显示效果。针对此问题，本申请方案设计有缓冲电路30，通过缓冲电路30来根据校正电压对公共电压VCOM进行校正，并将校正后的公共电压VCOM进行信号缓冲后输出。需要说明的是，如此设置，即便没有校正电压，公共电极线40接入的也为经缓冲电路30信号缓冲后的公共电压VCOM，因而在中途叠加校正电压时，可有效降低公共电极线40上公共电压VCOM的波动，有利于提高显示的稳定性。
在图3所示实施例中，缓冲电路30包括第九电阻R9、第十电阻R10、第十一电阻R11、第十二电阻R12以及第四运算放大器；第九电阻R9的第一端和第十电阻R10的第一端分别为缓冲电路30的第一输入端和第二输入端，第九电阻R9的第二端、第十电阻R10的第一端和第四运算放大器的正相输入端互连，以实现校正电压和公共电压VCOM的叠加，第四运算放大器的输出端反相输入端、第十一电阻R11的第二端和第十二电阻R12的第一端互连，第十一电阻R11的第一端与第四运算放大器的输出端连接，第十二电阻R12的第二端接入预设电压，第四运算放大器的输出端为缓冲电路30的输出端。
实施例二：
本申请还提出一种显示面板。
参照图4，该显示面板包括公共电极线40、灰阶电压产生电路50和公共电压校正电路，该公共电压校正电路的具体结构参照上述实施例，由于本显示面板采用了上述所有实施例的全部技术方案，因此至少具有上述实施例的技术方案所带来的所有有益效果，在此不再一一赘述。
其中，灰阶电压产生电路50，用于输出第一预设灰阶电压和第二预设灰阶电压；公共电压产生电路60，与公共电极线40连接，用于输出公共电压VCOM至共电极线；公共电压校正电路，分别与公共电极线40、灰阶电压产生电路50和公共电压产生电路60连接，以分别接入第一预设灰阶电压、第二预设灰阶电压和公共电压VCOM，并输出校正后公共电压VCOM值公共电极线40。
在一实施例中，所述灰阶电压产生电路50用于输出N路预设灰阶电压，N为正整数；
所述N路预设灰阶电压中电压值最小的该路预设灰阶电压为所述第一预设灰阶电压，所述N路预设灰阶电压中电压值最大的该路预设灰阶电压为所述第二预设灰阶电压。
以图3所示实施例的8Bit为例，N为256，其中第一路预设灰阶电压的电压值为最大电压值，也即为第0阶预设灰阶电压V0，其余256路预设灰阶电压可不断通过上一阶灰阶电压分压得到，因此第256路预设灰阶电压的电压值为最小电压值，也即为第255阶预设灰阶电压V255。当然实际应用中，显示面板的色深还可为6Bit、10Bit或者12Bit设计，在此不做限定。本申请方案通过选用N路预设灰阶电压中电压值最小的最后一阶预设灰阶电压和电压值最大的第0阶预设灰阶电压来分别作为第一预设灰阶电压和第二预设灰阶电压，有利于提高液晶层两端直流偏移程度检测的精准性。
实施例三：
本申请还提出一种显示装置，该显示装置包括公共电极线40、灰阶电压产生电路50和公共电压校正电路，该公共电压校正电路的具体结构参照上述实施例，由于本显示装置采用了上述所有实施例的全部技术方案，因此至少具有上述实施例的技术方案所带来的所有有益效果，在此不再一一赘述。
以上所述仅为本申请的可选实施例，并非因此限制本申请的专利范围，凡是在本申请的申请构思下，利用本申请说明书及附图内容所作的等效结构变换，或直接/间接运用在其他相关的技术领域均包括在本申请的专利保护范围内。

Claims (15)

  1. 一种公共电压校正电路，应用于显示面板，所述显示面板包括：公共电极线(40)、灰阶电压产生电路(50)和公共电压产生电路(60)，所述灰阶电压产生电路(50)用于输出第一预设灰阶电压和第二预设灰阶电压，所述公共电压产生电路(60)用于输出公共电压(VCOM)至所述公共电极线(40)，其中，所述公共电压校正电路包括：
    偏移检测电路(10)，所偏移检测电路(10)的第一输入端和第二输入端分别与所述灰阶电压产生电路(50)连接，以分别接入所述第一预设灰阶电压和第二预设灰阶电压，所述偏移检测电路(10)用于根据所述第一预设灰阶电压和所述第二预设灰阶电压，确定液晶层两端受环境温度影响的直流偏移程度，并输出偏移检测信号；以及，
    校正电压产生电路(20)，所述校正电压产生电路(20)的输入端与所述偏移检测电路(10)的输出端连接，所述校正电压产生电路(20)的输出端与所述公共电极线(40)连接，所述校正电压产生电路(20)用于根据所述偏移检测信号，生成相应的校正电压并输出至所述公共电极线(40)，以对所述公共电极线(40)接收到的公共电压(VCOM)进行校正，直至所述液晶层两端受环境温度影响的直流偏移程度消除。
  2. 如权利要求1所述的公共电压校正电路，其中，所述偏移检测电路(10)包括：
    第一偏移检测电路(11)，所述第一偏移检测电路(11)的输入端用于接入所述第一预设灰阶电压，所述第一偏移检测电路(11)用于根据所述第一预设灰阶电压，确定所述第一预设灰阶电压的直流偏移程度，并输出第一偏移程度检测信号；
    第二偏移检测电路(12)，所述第一偏移检测电路(11)的输入端用于接入所述第二预设灰阶电压，所述第二偏移检测电路(12)用于根据所述第二预设灰阶电压，确定所述第二预设灰阶电压的直流偏移程度，并输出第二偏移程度检测信号；以及，
    直流偏置确定电路(13)，所述直流偏置确定电路(13)的第一输入端和第二输入端分别与所述第一偏移检测电路(11)的输出端和所述第二偏移检测电路(12)的输出端连接，所述直流偏置确定电路(13)用于根据所述第一偏移程度检测信号和所述第二偏移程度检测信号，确定液晶层两端受环境温度影响的直流偏移程度，并输出所述偏移检测信号。
  3. 如权利要求2所述的公共电压校正电路，其中，所述第一偏移检测电路(11)的输入端包括正极输入端和负极输入端，所述第一偏移检测电路(11)包括：第一电阻(R1)、第二电阻(R2)、第三电阻(R3)、第四电阻(R4)以及第一运算放大器(A1)；
    所述第一电阻(R1)的第一端为所述第一偏移检测电路(11)的正极输入端，所述第一电阻(R1)的第二端、所述第一运算放大器(A1)的反相输入端、所述第二电阻(R2)的第一端互连，所述第二电阻(R2)的第二端与所述第一运算放大器(A1)的输出端连接，所述第一运算放大器(A1)的输出端为所述第一偏移检测电路(11)的输出端，所述第三电阻(R3)的第一端为所述第一偏移检测电路(11)的负极输入端，所述第三电阻(R3)的第二端、所述第一运算放大器(A1)的正相输入端、所述第四电阻(R4)的第一端互连，所述第四电阻(R4)的第二端接地。
  4. 如权利要求2所述的公共电压校正电路，其中，所述第二偏移检测电路(12)的输入端包括正极输入端和负极输入端，所述第二偏移检测电路(12)包括：第五电阻(R5)、第六电阻(R6)、第七电阻(R7)、第八电阻(R8)以及第二运算放大器(A2)；
    所述第五电阻(R5)的第一端为所述第二偏移检测电路(12)的正极输入端，所述第五电阻(R5)的第二端、所述第二运算放大器(A2)的反相输入端、所述第六电阻(R6)的第一端互连，所述第六电阻(R6)的第二端与所述第二运算放大器(A2)的输出端连接，所述第二运算放大器(A2)的输出端为所述第二偏移检测电路(12)的输出端，所述第七电阻(R7)的第一端为所述第二偏移检测电路(12)的负极输入端，所述第七电阻(R7)的第二端、所述第二运算放大器(A2)的正相输入端、所述第八电阻(R8)的第一端互连，所述第八电阻(R8)的第二端接地。
  5. 如权利要求2所述的公共电压校正电路，其中，所述直流偏置确定电路(13)包括：
    第三运算放大器(A3)，所述第三运算放大器(A3)的正相输入端、反相输入端、输出端分别为所述直流偏置确定电路(13)的第一输入端、第二输入端、输出端。
  6. 如权利要求1所述的公共电压校正电路，其中，所述校正电压产生电路(20)包括：
    存储器(21)，存储有预设直流偏移程度-预设校正电压值映射表；
    校正电压生成电路(22)，所述校正电压生成电路(22)的输入端与所述偏移检测电路(10)的输出端连接，所述校正电压生成电路(22)的数据端与所述存储器(21)通信连接，所述校正电压生成电路(22)用于根据所述偏移检测信号，调用所述预设直流偏移程度-预设校正电压值映射表，以查找得到与所述偏移检测信号对应的预设校正电压值，并生成输出相应的校正电压；
    数模转换电路(23)，所述数模转换电路(23)的输入端与所述校正电压生成电路(22)的输出端连接，所述数模转换电路(23)的输出端为所述校正电压产生电路(20)的输出端，所述数模转换电路(23)用于对接入的所述校正电压进行数模转换后输出。
  7. 如权利要求1所述的公共电压校正电路，其中，所述公共电压校正电路还包括：
    缓冲电路(30)，所述缓冲电路(30)的第一输入端和第二输入端分别与所述校正电压产生电路(20)的输出端和所述公共电压产生电路(60)的输出端连接，所述缓冲电路(30)的输出端与所述公共电极线(40)连接，所述缓冲电路(30)用于根据所述校正电压对所述公共电压(VCOM)进行校正，并将校正后的所述公共电压(VCOM)进行信号缓冲后，输出至所述公共电极线(40)。
  8. 如权利要求1所述的公共电压校正电路，其中，所述灰阶电压产生电路(50)可输出电压值依次增大的N路预设灰阶电压，N的数量可由显示面板的色深来决定。
  9. 如权利要求8所述的公共电压校正电路，其中，正常温度下，N路预设灰阶电压中，较大电压值的预设灰阶电压和对应的较小电压值的预设灰阶电压二者的电压差值为预设电压差值。
  10. 如权利要求8所述的公共电压校正电路，其中，第一预设灰阶电压和第二预设灰阶电压可为N路预设灰阶电压中电压差值较大或者最大的两路预设灰阶电压，所述偏移检测电路(10)可运行相应的硬件电路或者软件程序或算法，根据第一预设灰阶电压和第二预设灰阶电压，分别确定二者在环境温度下受直流偏置电压的影响大小，以及根据确定结果确定液晶层两端整体受环境温度下的直流偏移程度，并输出表征直流偏移程度的偏移检测信号；其中，预设灰阶电压的直流偏移程度分为正偏移和负偏移。
  11. 如权利要求8所述的公共电压校正电路，其中，当确定第一预设灰阶电压产生正偏移，第二预设灰阶电压产生正偏移，且第一预设灰阶电压的正偏移量大于第二预设灰阶电压的正偏移量时；或者，
    当确定第一预设灰阶电压产生正偏移，第二预设灰阶电压不产生偏移或者产生负偏移时，直流偏移程度可为正直流偏移程度，所述偏移检测电路(10)可输出与正直流偏移程度对应的偏移检测信号。
  12. 如权利要求8所述的公共电压校正电路，其中，当确定第一预设灰阶电压不产生偏移，第二预设灰阶电压产生负偏移时；或者，当确定第一预设灰阶电压产生正偏移，第二预设灰阶电压产生正偏移，且第一预设灰阶电压的正偏移量小于第二预设灰阶电压的正偏移量时；或者，当确定第一预设灰阶电压产生负偏移，第二预设灰阶电压产生负偏移，且第一预设灰阶电压的负偏移量小于第二预设灰阶电压的负偏移量时，直流偏移程度可为负直流偏移程度，所述偏移检测电可输出与负直流偏移程度对应的偏移检测信号。
  13. 一种显示面板，所述显示面板包括：
    公共电极线(40)；
    灰阶电压产生电路(50)，用于输出第一预设灰阶电压和第二预设灰阶电压；
    公共电压产生电路(60)，与所述公共电极线(40)连接，用于输出公共电压(VCOM)至所述公共电极线(40)：以及，
    公共电压校正电路，所述公共电压校正电路分别与所述公共电极线(40)、所述灰阶电压产生电路(50)和所述公共电压产生电路(60)连接；
    所述公共电压校正电路包括：
    偏移检测电路(10)，所偏移检测电路(10)的第一输入端和第二输入端分别与所述灰阶电压产生电路(50)连接，以分别接入所述第一预设灰阶电压和第二预设灰阶电压，所述偏移检测电路(10)用于根据所述第一预设灰阶电压和所述第二预设灰阶电压，确定液晶层两端受环境温度影响的直流偏移程度，并输出偏移检测信号；以及，
    校正电压产生电路(20)，所述校正电压产生电路(20)的输入端与所述偏移检测电路(10)的输出端连接，所述校正电压产生电路(20)的输出端与所述公共电极线(40)连接，所述校正电压产生电路(20)用于根据所述偏移检测信号，生成相应的校正电压并输出至所述公共电极线(40)，以对所述公共电极线(40)接收到的公共电压(VCOM)进行校正，直至所述液晶层两端受环境温度影响的直流偏移程度消除。
  14. 如权利要求13所述的显示面板，其中，所述灰阶电压产生电路(50)用于输出N路预设灰阶电压，N为正整数；
    所述N路预设灰阶电压中电压值最小的该路预设灰阶电压为所述第一预设灰阶电压，所述N路预设灰阶电压中电压值最大的该路预设灰阶电压为所述第二预设灰阶电压。
  15. 一种显示装置，其中，所述显示装置包括显示面板，所述显示面板包括：
    公共电极线(40)；
    灰阶电压产生电路(50)，用于输出第一预设灰阶电压和第二预设灰阶电压；
    公共电压产生电路(60)，与所述公共电极线(40)连接，用于输出公共电压(VCOM)至所述公共电极线(40)：以及，
    公共电压校正电路，所述公共电压校正电路分别与所述公共电极线(40)、所述灰阶电压产生电路(50)和所述公共电压产生电路(60)连接；
    所述公共电压校正电路包括：
    偏移检测电路(10)，所偏移检测电路(10)的第一输入端和第二输入端分别与所述灰阶电压产生电路(50)连接，以分别接入所述第一预设灰阶电压和第二预设灰阶电压，所述偏移检测电路(10)用于根据所述第一预设灰阶电压和所述第二预设灰阶电压，确定液晶层两端受环境温度影响的直流偏移程度，并输出偏移检测信号；以及，
    校正电压产生电路(20)，所述校正电压产生电路(20)的输入端与所述偏移检测电路(10)的输出端连接，所述校正电压产生电路(20)的输出端与所述公共电极线(40)连接，所述校正电压产生电路(20)用于根据所述偏移检测信号，生成相应的校正电压并输出至所述公共电极线(40)，以对所述公共电极线(40)接收到的公共电压(VCOM)进行校正，直至所述液晶层两端受环境温度影响的直流偏移程度消除。
PCT/CN2022/141162 2022-05-17 2022-12-22 公共电压校正电路、显示面板和显示装置 WO2023221506A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202210532067.4 2022-05-17
CN202210532067.4A CN114664271B (zh) 2022-05-17 2022-05-17 公共电压校正电路、显示面板和显示装置

Publications (1)

Publication Number Publication Date
WO2023221506A1 true WO2023221506A1 (zh) 2023-11-23

Family

ID=82038262

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/141162 WO2023221506A1 (zh) 2022-05-17 2022-12-22 公共电压校正电路、显示面板和显示装置

Country Status (2)

Country Link
CN (1) CN114664271B (zh)
WO (1) WO2023221506A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114664271B (zh) * 2022-05-17 2022-09-27 惠科股份有限公司 公共电压校正电路、显示面板和显示装置

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080143703A1 (en) * 2006-12-15 2008-06-19 Innocom Technology (Shenzhen) Co., Ltd. Driving circuit, driving method and liquid crystal display using same
CN101727858A (zh) * 2008-10-10 2010-06-09 北京京东方光电科技有限公司 残像消除方法及装置
CN102903344A (zh) * 2012-09-27 2013-01-30 合肥京东方光电科技有限公司 公共电极电压补偿方法、装置及时序控制器
CN104571701A (zh) * 2014-12-29 2015-04-29 深圳市华星光电技术有限公司 图像均匀性显示的方法、装置及系统
CN105632396A (zh) * 2016-03-04 2016-06-01 京东方科技集团股份有限公司 一种灰阶电压校准装置、系统、方法及显示装置
CN106847157A (zh) * 2017-03-24 2017-06-13 上海天马有机发光显示技术有限公司 一种显示面板的亮度补偿方法及装置
CN112562607A (zh) * 2020-12-17 2021-03-26 昆山龙腾光电股份有限公司 用于显示面板的公共电压补偿电路，补偿方法及显示装置
CN114187861A (zh) * 2021-12-10 2022-03-15 惠州华星光电显示有限公司 显示装置驱动方法和显示装置
CN114664271A (zh) * 2022-05-17 2022-06-24 惠科股份有限公司 公共电压校正电路、显示面板和显示装置

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5926162A (en) * 1996-12-31 1999-07-20 Honeywell, Inc. Common electrode voltage driving circuit for a liquid crystal display
JPH11183871A (ja) * 1997-12-19 1999-07-09 Canon Inc 液晶ディスプレイ装置
JP3983123B2 (ja) * 2002-07-11 2007-09-26 シャープ株式会社 半導体検査装置及び半導体検査方法
JP4569081B2 (ja) * 2003-07-08 2010-10-27 ソニー株式会社 表示装置および投射型表示装置
TWI336876B (en) * 2004-11-10 2011-02-01 Himax Tech Inc Data driving system and display having adjustable common voltage
JP2007033514A (ja) * 2005-07-22 2007-02-08 Casio Comput Co Ltd 液晶表示装置及び表示駆動回路
KR20080001955A (ko) * 2006-06-30 2008-01-04 엘지.필립스 엘시디 주식회사 액정표시소자의 구동 장치 및 방법
US20090040167A1 (en) * 2007-08-06 2009-02-12 Wein-Town Sun Programmable nonvolatile memory embedded in a timing controller for storing lookup tables
CN101567170B (zh) * 2008-04-25 2012-07-04 群康科技(深圳)有限公司 液晶显示器及其驱动方法
US20100214271A1 (en) * 2009-02-25 2010-08-26 Seiko Epson Corporation Liquid crystal device, temperature detection method, and electronic apparatus
TWI441153B (zh) * 2011-08-11 2014-06-11 Hannstar Display Corp 顯示裝置及其伽瑪電壓產生器
CN103295550B (zh) * 2013-05-31 2015-03-11 京东方科技集团股份有限公司 一种驱动电压确定方法及装置
KR102105329B1 (ko) * 2013-12-31 2020-04-29 삼성디스플레이 주식회사 표시 장치 및 그 구동 방법
KR20160012309A (ko) * 2014-07-23 2016-02-03 삼성디스플레이 주식회사 표시 장치 및 그것의 구동 방법
KR20160082813A (ko) * 2014-12-29 2016-07-11 삼성디스플레이 주식회사 액정 표시 장치 및 그 구동 방법
CN105096894B (zh) * 2015-09-16 2018-09-04 京东方科技集团股份有限公司 一种残像消除方法、驱动系统和显示装置
CN105632449B (zh) * 2016-04-06 2018-04-10 京东方科技集团股份有限公司 一种显示面板的伽马电压调节方法及装置
CN106847212A (zh) * 2017-02-23 2017-06-13 北京京东方专用显示科技有限公司 公共电压控制电路及方法、显示面板及显示装置
CN107068091B (zh) * 2017-04-28 2019-09-13 昆山龙腾光电有限公司 电压产生电路、显示装置以及公共电压调节方法
CN112885280A (zh) * 2021-01-22 2021-06-01 重庆惠科金渝光电科技有限公司 一种显示装置的驱动方法、装置、显示设备及存储介质

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080143703A1 (en) * 2006-12-15 2008-06-19 Innocom Technology (Shenzhen) Co., Ltd. Driving circuit, driving method and liquid crystal display using same
CN101727858A (zh) * 2008-10-10 2010-06-09 北京京东方光电科技有限公司 残像消除方法及装置
CN102903344A (zh) * 2012-09-27 2013-01-30 合肥京东方光电科技有限公司 公共电极电压补偿方法、装置及时序控制器
CN104571701A (zh) * 2014-12-29 2015-04-29 深圳市华星光电技术有限公司 图像均匀性显示的方法、装置及系统
CN105632396A (zh) * 2016-03-04 2016-06-01 京东方科技集团股份有限公司 一种灰阶电压校准装置、系统、方法及显示装置
CN106847157A (zh) * 2017-03-24 2017-06-13 上海天马有机发光显示技术有限公司 一种显示面板的亮度补偿方法及装置
CN112562607A (zh) * 2020-12-17 2021-03-26 昆山龙腾光电股份有限公司 用于显示面板的公共电压补偿电路，补偿方法及显示装置
CN114187861A (zh) * 2021-12-10 2022-03-15 惠州华星光电显示有限公司 显示装置驱动方法和显示装置
CN114664271A (zh) * 2022-05-17 2022-06-24 惠科股份有限公司 公共电压校正电路、显示面板和显示装置

Also Published As

Publication number Publication date
CN114664271B (zh) 2022-09-27
CN114664271A (zh) 2022-06-24

Similar Documents

Publication Publication Date Title
JP4479710B2 (ja) 液晶用駆動装置、液晶用駆動方法及び液晶表示装置
JP4638182B2 (ja) 液晶表示装置と、これの駆動方法及びその装置
KR101344834B1 (ko) 타이밍 컨트롤러, 이를 포함하는 액정표시장치 및 이의구동방법
TWI661409B (zh) 顯示驅動器、光電裝置及電子機器
US11348547B2 (en) Method and apparatus for compensating display voltage, display apparatus and display device
WO2023221506A1 (zh) 公共电压校正电路、显示面板和显示装置
KR20090099229A (ko) 디지털 감마 보정 시스템 및 보정방법
CN109767737B (zh) 公共电压补偿方法及其显示装置
TW200813930A (en) Display device and method capable of adjusting slew rate
KR20080012541A (ko) 구동 ｉｃ, 액정 표시 장치 및 표시 시스템
CN210136714U (zh) 公共电压驱动电路及显示装置
US11232761B2 (en) Ghost relieving circuit for display panel, display panel and ghost relieving method for display panel
JP3068465B2 (ja) 液晶表示装置
JP4266808B2 (ja) 液晶表示装置の基準電圧発生回路
JPH07253765A (ja) 液晶アクティブマトリクス表示装置
CN114267312A (zh) 残像优化电路及方法
CN109979406B (zh) 驱动电路、显示装置和电压补偿控制方法
KR20200017608A (ko) 표시 장치 및 이의 구동 방법
WO2015066938A1 (zh) 珈玛电压调整装置的调整方法
CN111326126B (zh) 信号提供电路、信号提供方法及显示装置
CN220913877U (zh) 应用于显示面板的驱动控制部
JPH02217894A (ja) 液晶表示装置の駆動装置
US11430363B1 (en) Data driving circuit and display apparatus with reduced power consumption
JPH0336519A (ja) 液晶表示装置の駆動装置
TW200535779A (en) Liquid crystal display and processing method thereof

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22942526

Country of ref document: EP

Kind code of ref document: A1