WO2023221342A1 - Ddr双列直插式存储模块、存储系统及其操作方法 - Google Patents

Ddr双列直插式存储模块、存储系统及其操作方法 Download PDF

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WO2023221342A1
WO2023221342A1 PCT/CN2022/117251 CN2022117251W WO2023221342A1 WO 2023221342 A1 WO2023221342 A1 WO 2023221342A1 CN 2022117251 W CN2022117251 W CN 2022117251W WO 2023221342 A1 WO2023221342 A1 WO 2023221342A1
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data
channel
group
signal bits
data signal
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PCT/CN2022/117251
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English (en)
French (fr)
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张凉
黄明
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芯动微电子科技(武汉)有限公司
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Priority to US17/994,324 priority Critical patent/US12026050B2/en
Publication of WO2023221342A1 publication Critical patent/WO2023221342A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/12015—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising clock generation or timing circuitry
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present invention belongs to the field of memory technology, and more specifically, relates to a DDR dual-in-line memory module, a memory system and an operating method using a data buffer for error correction.
  • DDR is the abbreviation of DDR SDRAM.
  • the current Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM) standard provides a memory module that can support dual-in-line memory. Module, DIMM) device channel.
  • DIMM Double Data Rate Synchronous Dynamic Random Access Memory
  • ECC Error Correcting Code
  • DDR5 flash-generation DDR SDRAM
  • MC Memory Controller
  • the memory controller is usually on the main processor (CPU/Host) chip, and the main processor is updated slowly, it is difficult for most general-purpose CPU manufacturers to integrate high-performance error correction functions, or error correction codes that are particularly effective for certain DRAM particles.
  • the mapping structure is designed into the memory controller, which makes it difficult for the error correction capability of the memory controller to meet practical needs.
  • the present invention provides a DDR dual-in-line memory module, a memory system and an operating method thereof that utilize error correction in a data buffer, and can achieve high performance on a memory stick. Error detection and correction can greatly reduce the bit error rate of the entire memory module.
  • a DDR dual in-line memory module including: a first channel, the first channel includes a first group of DRAM particles and a third group of DRAM particles corresponding to the first group.
  • the first data buffer is also used to obtain all data signal bits of the first channel from the first group of DRAM particles during a read operation, and detect all data signal bits of the first channel obtained from the first group of DRAM particles. Whether there are error codes in the data, and if there are error codes, perform error correction on the data in all data signal bits of the first channel obtained from the first group of DRAM particles before sending them out.
  • the above-mentioned DDR dual in-line memory module also includes a circuit board, and the first channel also includes a second group of DRAM particles; the first group of DRAM particles is disposed on the first side of the circuit board, and the second group of DRAM particles It is arranged on the second side of the circuit board opposite to the first side; the first data buffer also corresponds to the second group of DRAM particles; the first group of DRAM particles and the second group of DRAM particles do not work at the same time.
  • the first data buffer is also used to obtain all data signal bits input to the first channel during a write operation, and perform ECC encoding on the data in all data signal bits input to the first channel to generate ECC check code, and send the generated ECC check code and data in all data signal bits input to the first channel to the second group of DRAM particles.
  • the first data buffer is also used to obtain all data signal bits of the first channel from the second group of DRAM particles during a read operation, and detect all data signal bits of the first channel obtained from the second group of DRAM particles. Whether there are error codes in the data, and if there are error codes, correct the data in all the data signal bits of the first channel obtained from the second group of DRAM particles before sending them out.
  • the first data buffer includes a first data transceiver, a second data transceiver, an ECC encoder, and an ECC decoder.
  • the ECC encoder and the ECC decoder are respectively connected between a first data transceiver and a second data transceiver, and the second data transceiver is connected to the first group of DRAMs.
  • the first data transceiver is configured to receive all data signal bits input to the first channel under triggering of a clock signal; the ECC encoder is configured to encode all data signal bits input to the first channel.
  • the data in is ECC encoded to generate an ECC check code; the second data transceiver is used to send the generated ECC check code and data in all data signal bits input to the first channel to the first group of DRAM particles.
  • the second data transceiver is also used to obtain all the data signal bits of the first channel from the first group of DRAM particles under the trigger of the clock signal; the ECC decoder is used to detect the data from the first group of DRAM particles. Whether there are error codes in the data in all the data signal bits of the first channel acquired by the particle, and if there are error codes, after error correction is performed on the data in all the data signal bits of the first channel acquired from the first group of DRAM particles. Output, when there is no error code, output the data in all the data signal bits of the first channel obtained from the first group of DRAM particles; the first data transceiver is also used to send the data output by the ECC decoder.
  • the first data buffer further includes a first selector and a second selector.
  • the ECC encoder is connected between the first selector and the first data transceiver
  • the ECC decoder is connected between the second selector and the second data transceiver
  • the first selector is connected between the first selector and the first data transceiver.
  • the second selector is connected between the first data transceiver and the second data transceiver
  • the second data transceiver is connected to the first group of DRAM particles.
  • the first data transceiver is used to receive and output all data signal bits input to the first channel under the trigger of a clock signal;
  • the ECC encoder is used to encode all data input to the first channel.
  • the data in the signal bits is ECC encoded to generate an ECC check code, and the generated ECC check code and the data in all data signal bits input to the first channel are output.
  • the first selector is used to select whether to turn on the ECC function during a write operation; when the ECC function is turned on, the first selector selects to send the output of the ECC encoder to the first group of DRAM through the second data transceiver. particles; when the ECC function is turned off, the first selector selects to send the output of the first data transceiver to the first group of DRAM particles through the second data transceiver.
  • the second data transceiver is used to obtain all the data signal bits of the first channel from the first group of DRAM particles and output them under the trigger of the clock signal;
  • the ECC decoder is used to detect the data from the first group of DRAM particles. Whether there are error codes in the data in all the data signal bits of the first channel acquired by the particle, and if there are error codes, after error correction is performed on the data in all the data signal bits of the first channel acquired from the first group of DRAM particles. Output, when there is no error code, output the data in all the data signal bits of the first channel obtained from the first group of DRAM particles.
  • the second selector is used to select whether to turn on the ECC function during the read operation. When the ECC function is turned on, the second selector selects to send the output of the ECC decoder through the first data transceiver; when the ECC function is turned off When , the second selector selects to send the output of the second data transceiver through the first data transceiver.
  • the first data transceiver includes a plurality of first receiving modules; the plurality of first receiving modules are used to obtain and output all data signal bits input to the first channel during a write operation.
  • the first receiving module includes a first receiver, a second receiver and a first D flip-flop; the first receiver is used to receive the data signal input to the first channel and output it to the first D flip-flop.
  • the second receiver is used to receive the write sampling clock and output it to the clock signal input end of the first D flip-flop.
  • the positive output end of the first D flip-flop is input to the rising edge of the write sampling clock. The data signal output of the first channel.
  • the second data transceiver includes a plurality of second receiving modules; the plurality of second receiving modules are used to obtain all data signal bits of the first channel from the first group of DRAM particles and output them during a read operation.
  • the second receiving module includes a third receiver, a fourth receiver and a second D flip-flop; the third receiver is used to receive the data signal from the first group of DRAM particles and output it to the second D flip-flop.
  • the input terminal of the flip-flop, the fourth receiver is used to receive the read sampling clock and output it to the clock signal input terminal of the second D flip-flop.
  • the positive output terminal of the second D flip-flop will come from the rising edge of the read sampling clock.
  • the data signal output of a group of DRAM particles is used to receive the data signal from the first group of DRAM particles and output it to the second D flip-flop.
  • the first data transceiver further includes a first transmitting module configured to output a signal from the ECC decoder or a signal from the second data transceiver in a read operation.
  • the second data transceiver further includes a second sending module, which is used to output the signal from the ECC encoder or the signal from the first data transceiver during the write operation.
  • a storage system including a CPU and the above-mentioned DDR dual in-line memory module; the CPU is used to perform read and write operations on the DDR dual in-line memory module.
  • a storage system including a CPU and a DDR dual in-line memory module;
  • the DDR dual in-line memory module includes a first channel, and the first channel includes a first group of DRAM particles and a first data buffer corresponding to the first group of DRAM particles;
  • the first data buffer is used to send data in all data signal bits sent by the CPU to the first channel to the first group of DRAM particles during a write operation, and during a read operation All data signal bits of the first channel are obtained from the first group of DRAM particles; the first data buffer is also used for ECC error correction in write operations and read operations.
  • the first data buffer is used to obtain all data signal bits input to the first channel from the CPU during a write operation, and perform ECC encoding on the data in all data signal bits input to the first channel to generate ECC check code, and send the generated ECC check code and data in all data signal bits input to the first channel to the first group of DRAM particles.
  • the first data buffer is also used to obtain all data signal bits of the first channel from the first group of DRAM particles during a read operation, and detect all data signal bits of the first channel obtained from the first group of DRAM particles. Whether there are error codes in the data, and if there are error codes, correct the data in all the data signal bits of the first channel obtained from the first group of DRAM particles before sending them to the CPU.
  • the first channel further includes a second group of DRAM particles; the first group of DRAM particles is disposed on the first side of the circuit board, and the second group of DRAM particles is disposed on the second side of the circuit board opposite to the first side. ;
  • the first data buffer also corresponds to the second group of DRAM particles; the first group of DRAM particles and the second group of DRAM particles do not work at the same time.
  • the first data buffer is also used to obtain all data signal bits input to the first channel from the CPU during a write operation, and perform ECC encoding on the data in all data signal bits input to the first channel. , generate an ECC check code, and send the generated ECC check code and data in all data signal bits input to the first channel to the second group of DRAM particles.
  • the first data buffer is also used to obtain all data signal bits of the first channel from the second group of DRAM particles during a read operation, and detect all data signal bits of the first channel obtained from the second group of DRAM particles. Whether there are error codes in the data, and if there are error codes, correct the data in all the data signal bits of the first channel obtained from the second group of DRAM particles before sending them to the CPU.
  • the DDR dual in-line memory module further includes a second channel, and the second channel includes a third group of DRAM particles and a second data buffer corresponding to the third group of DRAM particles; the second data buffer is used to sending data in all data signal bits sent by the CPU to the second channel to a third group of DRAM particles in the write operation, and acquiring all data signal bits of the second channel from the third group of DRAM particles in the read operation; the second data The buffer is also used for ECC error correction during write and read operations.
  • the second data buffer is used to obtain all data signal bits input to the second channel from the CPU during a write operation, and perform ECC encoding on the data in all data signal bits input to the second channel to generate ECC check code, and send the generated ECC check code and data in all data signal bits input to the second channel to the third group of DRAM particles.
  • the second data buffer is also used to obtain all data signal bits of the second channel from the third group of DRAM particles during a read operation, and detect all data signal bits of the second channel obtained from the third group of DRAM particles. Whether there is an error code in the data, and if there is an error code, correct the data in all the data signal bits of the second channel obtained from the third group of DRAM particles before sending it to the CPU.
  • the second channel further includes a fourth group of DRAM particles; a third group of DRAM particles are disposed on the first side of the circuit board, and a fourth group of DRAM particles is disposed on the second side of the circuit board; a second data buffer It also corresponds to the fourth group of DRAM particles; the third group of DRAM particles and the fourth group of DRAM particles do not work at the same time.
  • the second data buffer is also used to obtain all data signal bits input to the second channel from the CPU during a write operation, and perform ECC encoding on the data in all data signal bits input to the second channel. , generate an ECC check code, and send the generated ECC check code and data in all data signal bits input to the first channel to the fourth group of DRAM particles.
  • the second data buffer is also used to obtain all data signal bits of the second channel from the fourth group of DRAM particles during a read operation, and detect all data signal bits of the second channel obtained from the fourth group of DRAM particles. Whether there are error codes in the data, and if there are error codes, correct the data in all the data signal bits of the second channel obtained from the fourth group of DRAM particles before sending them to the CPU.
  • the first data buffer includes a first data transceiver, a second data transceiver, an ECC encoder, and an ECC decoder.
  • the ECC encoder and the ECC decoder are respectively connected between a first data transceiver and a second data transceiver, and the second data transceiver is connected to the first group of DRAMs.
  • the first data buffer further includes a first selector and a second selector.
  • the ECC encoder is connected between the first selector and the first data transceiver
  • the ECC decoder is connected between the second selector and the second data transceiver
  • the first selector is connected between the first selector and the first data transceiver.
  • the second selector is connected between the first data transceiver and the second data transceiver
  • the second data transceiver is connected to the first group of DRAM particles.
  • the second data buffer has the same structure as the first data buffer.
  • an operating method of a DDR dual in-line memory module includes: acquiring all data signal bits of the channel from the outside; performing data on all the data signal bits acquired from the outside. ECC encoding generates an ECC check code; the ECC check code and the data in all data signal bits are sent to the DRAM particles in the channel.
  • the above-mentioned ECC encoding of the data in the data signal bits obtained from the outside is performed to generate an ECC check code; the ECC check code and the data in the data signal bits are sent together to The operation of the DRAM particle in the channel.
  • the above-mentioned ECC encoding of the data in the data signal bits obtained from the outside is not performed to generate an ECC check code; the ECC check code and the data in the data signal bits are sent together.
  • the operation is given to the DRAM particle of the channel; instead, all the data signal bits obtained from the outside are sent to the DRAM particle of the channel.
  • the above operation method also includes: obtaining all data signal bits of the channel from the DRAM particle; determining whether all data signal bits obtained from the DRAM particle have error codes; if there are error codes, obtaining the data signal bits Correct the errors before sending them out.
  • the ECC function when the ECC function is turned on, the above-mentioned operation of determining whether all data signal bits obtained from the DRAM particles have error codes is performed; if there are error codes, the obtained data signal bits are corrected before being sent out.
  • the above method further includes storing error information.
  • the above-mentioned operation of judging whether all data signal bits obtained from the DRAM particles have error codes is not performed; if there are error codes, the obtained data signal bits are corrected before being sent out; Instead, all data signal bits obtained from the DRAM particles are sent out.
  • an operating method of a DDR dual in-line memory module including: performing a write operation, acquiring all data signal bits input to the channel, and converting all data signal bits input to the channel into Send the data to the DRAM particle; perform a read operation, obtain all the data signal bits of the channel from the DRAM particle, and send the data in all the data signal bits of the channel obtained from the DRAM particle; during the read operation and write operation, perform ECC error correction.
  • ECC encoding is performed on data in all data signal bits input to the channel to generate an ECC check code; the ECC check code and data in all data signal bits are sent to the DRAM together Particles.
  • the read operation it is determined whether all data signal bits obtained from the DRAM particles have error codes; if there are error codes, the obtained data signal bits are corrected before being sent out.
  • the above technical solution conceived by the present invention has the following beneficial effects: all data buffers (Data Buffer, DB) originally belonging to a channel (channel) are integrated together, so that A channel has a data buffer, and at the same time, the data buffer has an error correction function, that is, error correction coding is performed on the data from the CPU, error detection is performed on the data from the memory particles, and automatic error correction and error reporting are realized. Since the integrated data buffer can obtain all the data of the channel where it is located, high-performance error detection and correction can be achieved on the memory stick, greatly reducing the bit error rate of the entire memory stick.
  • Data Buffer, DB data buffers originally belonging to a channel (channel) are integrated together, so that A channel has a data buffer, and at the same time, the data buffer has an error correction function, that is, error correction coding is performed on the data from the CPU, error detection is performed on the data from the memory particles, and automatic error correction and error reporting are realized. Since the integrated data buffer can obtain all the data of the channel where it is located
  • Figure 1 is a schematic diagram of the layout and wiring of a DDR5LRDIMM memory module
  • Figure 2 is a schematic layout and wiring diagram of a DDR5 DIMM memory module using data buffer error correction according to an embodiment of the present invention
  • Figure 3 is a schematic diagram of the layout and wiring of a DDR5 DIMM memory module using data buffer error correction according to another embodiment of the present invention.
  • Figure 4 is a schematic layout and wiring diagram of a DDR5 DIMM memory module using data buffer error correction according to another embodiment of the present invention.
  • Figure 5 is a schematic diagram of the layout and wiring of a DDR5 DIMM memory module using data buffer error correction according to another embodiment of the present invention.
  • Figures 6A and 6B are respectively schematic layout and wiring diagrams of a DDR5DIMM memory module using data buffer error correction according to another embodiment of the present invention.
  • Figure 7 is a schematic diagram of the layout and wiring of a DDR5 DIMM memory module using data buffer error correction according to another embodiment of the present invention.
  • Figure 8 is a schematic block diagram of the DDR DIMM memory read and write operation process according to one embodiment of the present invention.
  • Figure 9 is a schematic block diagram of the DDR DIMM memory read and write operation process according to another embodiment of the present invention.
  • Figure 10 is a structural block diagram of the first data transceiver according to the embodiment of the present invention.
  • FIG. 11 is a structural block diagram of the second data transceiver according to the embodiment of the present invention.
  • Figure 12 is a schematic flowchart of a memory write operation according to an embodiment of the present invention.
  • Figure 13 is a schematic structural diagram corresponding to the memory write operation process according to the embodiment of the present invention.
  • Figure 14 is a schematic flow chart of a memory read operation according to an embodiment of the present invention.
  • Figure 15 is a schematic structural diagram corresponding to the memory read operation process according to the embodiment of the present invention.
  • Figure 1 is a schematic diagram of the layout and wiring of a DDR5 load reduced DIMM (Load Reduced DIMM, LRDIMM) memory module.
  • DIMM Large Reduced DIMM
  • memory particles on both sides of the memory stick (for example, both sides of the printed circuit board or PCB board).
  • the front side is Rank0 (the first Rank), and the back side is Rank1.
  • Channel A (the first channel) and channel B (the second channel) respectively have 10 ⁇ 4 DRAM particles on the front (the first group of DRAM particles and the third group of DRAM particles) and 10 ⁇ 4 DRAM particles on the back (the second group of DRAM particles).
  • the Registering Clock Driver (RCD) and DB are both set on the front of the memory module (the RCD of Rank1 in Figure 1 is only used to show the connection relationship).
  • RCD connects the memory particles on both sides through command/address lines
  • each DB connects both sides with its corresponding memory particles through data lines (the connection of the data lines in Rank1 in Figure 1 is not shown), that is, one side of each DB is connected to the front Two memory particles and two memory particles on the back.
  • the other side of each DB is connected to the gold finger on the edge of the memory bar, and then connected to the DDR data line of the CPU through the motherboard.
  • Rank0 and Rank1 will not work at the same time. At a certain moment, either Rank0 will work, or Rank1 will work, or neither Rank0 nor Rank1 will work.
  • Each DB is only responsible for one-fifth of the data of its channel.
  • FIG. 2 is a schematic diagram of the layout and wiring of a DDR5 DIMM memory module using data buffer error correction according to an embodiment of the present invention.
  • the five DBs of channel A and channel B are integrated together, and the error correction function is further added to form a data buffer with error correction capability (in the following Marked as DBECC).
  • DBECC first data cache
  • channel A has a DBECC (first data cache), which is used to process all data of read operations (from DRAM to CPU) and write operations (from CPU to DRAM) on channel A, and implement ECC encoding, Decoding, automatic error correction and error reporting.
  • channel B has a DBECC (second data cache) to process all data for read operations (from DRAM to CPU) and write operations (from CPU to DRAM) on channel B, and implement ECC encoding, decoding, automatic error correction and error reporting.
  • DBECC second data cache
  • One side of the DBECC is connected to multiple memory particles in its channel, the other side is connected to the gold finger on the edge of the memory bar, and then connected to the DDR data line of the CPU through the motherboard.
  • the memory particles of channel A and channel B can have the same layout. Taking channel A as an example, Rank0 has 10 ⁇ 4 DRAM particles. These 10 ⁇ 4 DRAM particles are set in two rows, and each row is set with 5 ⁇ 4 DRAM particles. Rank1 also has 10 ⁇ 4 DRAM particles. These 10 ⁇ 4 DRAM particles are set in two rows, with 5 ⁇ 4 DRAM particles set in each row.
  • the RCD and two DBECCs are both set on the front of the memory module (the RCD of Rank1 in Figure 2 is only used to show the connection relationship), and the RCD is set between the memory particles of channel A and the memory particles of channel B.
  • the DBECCs of channel A and channel B are respectively set at the position of the third row after the two rows of DRAM particles in Rank0.
  • width and height of the DRAM particles and the width and height of the DBECC shown in Figure 2 are only examples. According to the actual storage capacity and manufacturing process, the width and height of the DRAM particles can be customized, and the width and height of the DBECC can also be optimized according to the layout of the DRAM particles on the memory bar, which is not limited by the present invention.
  • Figure 3 is a schematic diagram of the layout and wiring of a DDR5 DIMM memory module using data buffer error correction according to another embodiment of the present invention.
  • the position of DBECC is adjusted, and the position of the memory particles is adjusted accordingly.
  • the 10 ⁇ 4 DRAM particles of Rank 0 are set in two rows.
  • the number of memory particles in the first row is different from the number of memory particles in the second row.
  • DBECC is set to a smaller number of DRAM particles.
  • Memory particles are provided in the row where the memory particles are located, that is, on both sides of the DBECC.
  • DBECC is set at the closest position to the middle within a row where a smaller number of memory particles are located.
  • 6 memory particles are set in the first row
  • 4 memory particles are set in the second row
  • DBECC is set in the middle of the 4 memory particles in the second row, that is, there are 2 memory particles on each side of DBECC.
  • 7 memory particles are set in the first row
  • 3 memory particles are set in the second row
  • DBECC is set at the closest position to the middle of the 3 memory particles in the second row. That is, there are 2 memory particles on one side of DBECC and 2 memory particles on the other.
  • Rank1 of channel A has the same memory particle layout as Rank0
  • channel B has the same memory particle layout and DBECC layout as channel A.
  • Figure 4 is a schematic diagram of the layout and wiring of a DDR5 DIMM memory module using data buffer error correction according to another embodiment of the present invention.
  • the position of DBECC is adjusted, and the position of the memory particles is adjusted accordingly.
  • the 10 ⁇ 4 DRAM particles of Rank 0 are divided into two rows, and each row is equipped with 5 ⁇ 4 DRAM particles.
  • DBECC is set across rows between the first row of memory particles and the second row of memory particles. In some implementations, the DBECC is placed closest to the middle of the first and second rows of memory particles.
  • DBECC has 3 memory granules on one side of the first and second rows, and 2 memory granules on the other side of the first and second rows.
  • Rank1 of channel A has the same memory particle layout as Rank0
  • channel B has the same memory particle layout and DBECC layout as channel A.
  • both Rank0 and Rank1 of a single channel have an even number of memory particles.
  • DBECC provides a 40-bit data signal to 10 ⁇ 4 DRAM particles. These 40-bit data In the signal, 32 bits are data and 8 bits are ECC check code. It should be understood that the memory particles of Rank0 and Rank1 of a single channel in the embodiment of the present invention can also be an odd number, and the present invention does not limit this.
  • Rank0 of channel A has 11 ⁇ 4 DRAM particles. These 11 ⁇ 4 DRAM particles are set in two rows. The number of memory particles in the first row is different from the number of memory particles in the second row. DBECC Set in a row with a smaller number of memory granules, that is, memory granules are set on both sides of the DBECC. In some implementations, DBECC is set at the closest position to the middle within a row where a smaller number of memory particles are located. For example, 7 memory particles are set in the first row, 4 memory particles are set in the second row, and DBECC is set in the middle of the 4 memory particles in the second row, that is, there are 2 memory particles on each side of DBECC.
  • Rank1 of channel A has the same memory particle layout as Rank0
  • channel B has the same memory particle layout and DBECC layout as channel A.
  • DBECC provides 44-bit data signals to 11 ⁇ 4 DRAM particles.
  • 32 bits are data and 12 bits are ECC check code.
  • DBECC can provide 48-bit data signals to 12 ⁇ 4 DRAM particles. Among these 48-bit data signals, 32 bits are data and 16 bits are ECC check code.
  • the memory particles are all ⁇ 4 DRAM. It should be understood that the memory particles of the DDR DIMM in the embodiment of the present invention can also be ⁇ 8 DRAM.
  • Rank0 of channel A has 5 ⁇ 8 DRAM particles. These 5 ⁇ 8 DRAM particles are set in the same row, and DBECC is set in the second row after the row of DRAM particles in Rank 0.
  • Rank1 of channel A has the same memory particle layout as Rank0, and channel B has the same memory particle layout and DBECC layout as channel A.
  • DBECC provides 40-bit data signals to 5 ⁇ 8 DRAM particles. Among these 40-bit data signals, 32 bits are data and 8 bits are ECC check codes.
  • Figure 6B is the case where Rank0 of channel A has 6 ⁇ 8 DRAM particles.
  • DBECC provides a 48-bit data signal to the 6 ⁇ 8 DRAM particles.
  • 32 bits are data and 16 bits are ECC check codes.
  • DBECC can provide 56-bit data signals to 7 x8 DRAM particles. Among these 56-bit data signals, 32 bits are data and 24 bits are ECC check codes.
  • the first Rank has multiple row positions, and the data buffer and the first group of DRAM particles occupy different row positions.
  • the first Rank has a plurality of row positions, the first group of DRAM particles occupies the plurality of row positions, and the data buffer occupies one or more row positions of the first group of DRAM particles.
  • the data buffer occupies one row position of the first group of DRAM particles, and in Figure 4, the data buffer occupies all two row positions of the first group of DRAM particles.
  • the DDR DIMM in the embodiment of the present invention may also have only one Rank.
  • the DDR DIMM memory module is only equipped with DRAM particles on the front and has only one Rank0.
  • Rank0 of channel A has 10 ⁇ 4 DRAM particles
  • DBECC is set on the back of the memory module (the DBECC on the front is only used to illustrate the connection relationship).
  • Channel B has the same memory particle layout and DBECC layout as channel A.
  • DBECC provides a 40-bit data signal to 10 ⁇ 4 DRAM particles. Among these 40-bit data signals, 32 bits are data and 8 bits are ECC check codes.
  • the best layout and wiring method can be specifically determined according to the width and height of DRAM particles and the number of ranks of the memory stick.
  • the present invention There are no restrictions on this.
  • FIG 8 is a schematic block diagram of the DDR DIMM memory read and write operation process according to the embodiment of the present invention.
  • DBECC 701 connects CPU and DRAM particles respectively.
  • DBECC 701 receives all the data signal bits of its channel from the CPU, performs ECC encoding on the data in all data signal bits, generates a new ECC check code, and combines the newly generated ECC check code with the data. Sent together to DRAM particles.
  • DBECC 701 receives all data signal bits of its channel from the DRAM particle, including data bits and check code bits, and detects whether there are error codes in the data in all data signal bits. If there are no error codes, it will The data in all data signal bits is sent to the CPU; if there is an error code, DBECC will automatically correct the error and send the corrected data to the CPU.
  • DBECC 701 includes a first data transceiver, a second data transceiver and an ECC error correction module 703.
  • the ECC error correction module 703 further includes an ECC encoder and an ECC decoder.
  • the first data transceiver receives all the data signal bits of its channel from the CPU on the rising edge of the system clock.
  • the ECC encoder performs ECC encoding on the data in all data signal bits to generate a new ECC checksum. code, the newly generated ECC check code and the data in all data signal bits are sent to the DRAM particle through the second data transceiver.
  • the second data transceiver receives all data signal bits of its channel at the rising edge of the system clock, including data bits and check code bits.
  • the ECC decoder detects whether there are errors in the data in all data signal bits. , if there is no error code, the data in all data signal bits will be sent to the CPU through the first data transceiver; if there is an error code, the ECC decoder will automatically correct the error and pass the error-corrected data through the first data transceiver. Transceiver sends to CPU.
  • the ECC decoder will also store specific error information in a local register after automatic error correction for the CPU to read out and perform subsequent processing.
  • FIG. 9 is a schematic block diagram of the DDR DIMM memory read and write operation process according to another embodiment of the present invention.
  • DBECC 801 includes a first data transceiver, a second data transceiver, an ECC error correction module 703, a first selector and a second selector.
  • the first data transceiver receives all the data signal bits of its channel from the CPU on the rising edge of the system clock.
  • the ECC encoder The data in the bits is ECC encoded to generate a new ECC check code.
  • the newly generated ECC check code and the data in all data signal bits are output from the first selector to the second data transceiver.
  • the transceiver sends it to the DRAM particle; when the control end of the first selector chooses to turn off the ECC function, the first selector outputs all the data signal bits received by the first data transceiver to the second data transceiver, and passes the second data
  • the transceiver sends it to the DRAM particle, in which case the system relies on the CPU's memory controller for error correction.
  • the second data transceiver receives all the data signal bits of its channel from the DRAM particle at the rising edge of the system clock, including data bits and check code bits.
  • the control end of the second selector selects to turn on the ECC function
  • the ECC decoder automatically corrects the error and outputs the corrected data from the second selector to the first data transceiver, and then sends it to the CPU through the first data transceiver.
  • the second selector When the control end of the second selector chooses to turn off the ECC function, the second selector outputs all the data signal bits received by the second data transceiver to the first data transceiver, and sends them to the CPU through the first data transceiver. In this case, the system will rely on the CPU's memory controller for error correction.
  • control terminals of the first selector and the second selector have the same signal input.
  • first data transceiver and the second data transceiver have the same structure.
  • FIG 10 is a structural block diagram of the first data transceiver according to the embodiment of the present invention.
  • the first data transceiver 901 includes a plurality of first receiving modules 903 and a first sending module 905.
  • the plurality of first receiving modules 903 are connected to the CPU and are used to obtain all data signal bits of the channel from the CPU. And the acquired data signals are sent to the first selector and ECC encoder respectively.
  • the first sending module 905 is connected to the second selector and is used to send the data signal output by the second selector to the CPU.
  • the first receiving module 903 includes a first receiver (RX1), a second receiver (RX2) and a first D flip-flop.
  • the first receiver is used to receive the data signal from the CPU and output it to the input terminal (D terminal) of the first D flip-flop
  • the second receiver is used to receive the sampling clock (DQS) from the CPU and output it to the first
  • the clock signal input terminal of the D flip-flop and the forward output terminal (Q terminal) of the first D flip-flop output the data signal from the CPU at the rising edge of the clock signal.
  • the first sending module 905 includes a read first-in-first-out module (Read FIFO) and a first transmitter (TX1).
  • the read first-in-first-out module is used to obtain the data signal from the second selector and send the data signal to the CPU through the first transmitter.
  • the second data transceiver 1001 includes a plurality of second receiving modules 1003 and a second sending module 1005.
  • the plurality of second receiving modules 1003 are respectively connected to DRAM memory particles for obtaining data from the DRAM memory particles. data signal, and sends the acquired data signal to the second selector and the ECC decoder respectively.
  • the second sending module 1005 is connected to the first selector and is used to send the data signal output by the first selector to the DRAM memory particle.
  • the second receiving module 1003 includes a third receiver (RX3), a fourth receiver (RX4) and a second D flip-flop.
  • the third receiver is used to receive the data signal from the DRAM and output it to the input terminal (D terminal) of the second D flip-flop
  • the fourth receiver is used to receive the sampling clock (MDQS) and output it to the second D flip-flop.
  • the clock signal input terminal, the forward output terminal (Q terminal) of the second D flip-flop outputs the data signal from the DRAM at the rising edge of the clock signal.
  • the second sending module 1005 includes a write first-in-first-out module (Write FIFO) and a second transmitter (TX2).
  • the write first-in-first-out module is used to obtain the data signal from the first selector and send the data signal to the DRAM particle through the second transmitter.
  • Figure 12 is a schematic flow diagram of the memory write operation process according to the embodiment of the present invention.
  • Figure 13 is a schematic structural diagram corresponding to the memory write operation process according to the embodiment of the present invention.
  • Figure 14 is a schematic diagram of the memory read operation process according to the embodiment of the present invention.
  • Figure 15 is a schematic diagram of the memory read operation process according to the embodiment of the present invention. Structural diagram corresponding to the memory read operation process of the embodiment.
  • the memory read and write operation process of the embodiment of the present invention will be described in detail below, taking Rank0 of a single channel with 10 ⁇ 4 DRAM particles as an example.
  • the write operation process of the DDR dual in-line memory module includes:
  • Step 1201 Obtain all data signal bits of the channel from the CPU.
  • multiple first receiving modules 903 acquire all the data signal bits of the channel from the CPU on the rising edge of the DQ sampling clock (DQS). There are a total of 40 bits of data signal, of which 32 bits are data and 8 bits are ECC. Check code, each first receiving module 903 obtains a 4-bit data signal, that is, a DQ Nibble, respectively labeled Nibble0-9. Among them, DQ represents the data line connecting the CPU and DBECC.
  • Step 1203 When the ECC function is turned on, perform ECC encoding on the data in all data signal bits obtained from the outside to generate an ECC check code.
  • the ECC encoder will perform ECC on 32-bit data (in the embodiment of the present invention, 32-bit data can be composed of Nibble0-7) Encode, generate a new 8-bit ECC check code, and output the newly generated 8-bit ECC check code and 32-bit data.
  • Step 1205 Send the ECC check code and the data in all data signal bits to the DRAM particle in the channel.
  • the first selector 1101 selects to output the newly generated 8-bit ECC check code output by the ECC encoder together with the 32-bit data, and sends it to the DRAM particle through the write first-in-first-out module and the second transmitter. It is understandable that when the ECC function is turned on, DBECC can ignore the 8-bit ECC code (such as Nibble8-9) sent by the CPU, and use the new 8-bit ECC check code calculated by itself for transmission and subsequent verification. process.
  • ECC code such as Nibble8-9
  • Step 1207 When the ECC function is turned off, send all data signal bits acquired from the outside to the DRAM particles in the channel.
  • DBECC will send the 40-bit signal from the CPU (for example, it can be composed of Nibble0-9) directly to the DRAM particle through the Write FIFO and the second transmitter.
  • the system relies on the CPU memory controller for error correction.
  • the read operation process of the DDR dual in-line memory module includes:
  • Step 1401 Obtain all data signal bits of the channel from the DRAM particle.
  • multiple second receiving modules 1003 obtain all the data signal bits of the channel from the DRAM memory particle on the rising edge of the MDQ sampling clock (MDQS), a total of 40 bits of data signal, where 32 bits are data and 8 bits are ECC check codes.
  • MDQ represents the data line connecting DBECC to DRAM particles.
  • Step 1403 When the ECC function is turned on, determine whether all data signal bits obtained from the DRAM particles contain error codes.
  • Step 1405 If there are error codes, correct all acquired data signal bits before sending them out.
  • the ECC decoder will automatically correct the error.
  • the second selector 1201 selects the error-corrected data signal output by the ECC decoder to pass through the read first-in-first-out module and the first transmitter. Sent to CPU. In this case, DBECC will also store specific error information in local registers for the CPU to read and perform subsequent processing.
  • Step 1407 If there are no error codes, output all data signal bits obtained from the DRAM particles.
  • the second selector 1201 selects to pass all the data signal bits obtained from the DRAM particles output by the ECC decoder through the read first-in-first-out module and the first transmission sent to the CPU.
  • Step 1409 When the ECC function is turned off, output all data signal bits obtained from the DRAM particles.
  • the second selector 1201 selects that all the data signal bits of the channel obtained from the DRAM memory particles output by the multiple second receiving modules will be directly read through FIFO module and first transmitter send to CPU. In this case, the system relies on the CPU memory controller for error correction.
  • error correction codes such as Hamming coding, Reed-Solomon cipher, or other block codes (Block codes) or convolutional codes (Convolutional codes).
  • Block codes Reed-Solomon cipher
  • Convolutional codes convolutional codes
  • the DRAM memory particles may be DDR4, DDR5, DDR6, LPDDR or GDDR, or may be LPDDR4, LPDDR5 or LPDDR5x, or other forms of DRAM memory particles, which the present invention does not limit.
  • references to the terms “one embodiment,” “some embodiments,” “an example,” “specific examples,” or “some examples” or the like means that specific features are described in connection with the embodiment or example.
  • structures, materials or features are included in at least one embodiment or example of the present application.
  • the specific features, structures, materials or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
  • those skilled in the art may combine and combine different embodiments or examples and features of different embodiments or examples described in this specification unless they are inconsistent with each other.
  • first and second are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of indicated technical features. Thus, features defined as “first” and “second” may explicitly or implicitly include at least one of these features. In the description of this application, “plurality” means two or more than two, unless otherwise explicitly and specifically limited.
  • Any process or method description in a flowchart or otherwise described herein may be understood to represent a representation that includes one or more (two or more) executable instructions for implementing the specified logical functions or steps of the process.
  • a module, fragment, or portion of code may be understood to represent a representation that includes one or more (two or more) executable instructions for implementing the specified logical functions or steps of the process.
  • a module, fragment, or portion of code may be understood to represent a representation that includes one or more (two or more) executable instructions for implementing the specified logical functions or steps of the process.
  • a module, fragment, or portion of code includes additional implementations in which functions may be performed out of the order shown or discussed, including in a substantially concurrent manner or in the reverse order, depending on the functionality involved.
  • logic and/or steps represented in the flowcharts or otherwise described herein, for example, may be considered a sequenced list of executable instructions for implementing the logical functions, and may be embodied in any computer-readable medium, For use by, or in combination with, instruction execution systems, devices or devices (such as computer-based systems, systems including processors or other systems that can fetch instructions from and execute instructions from the instruction execution system, device or device) or equipment.
  • various parts of the present application may be implemented in hardware, software, firmware, or a combination thereof.
  • various steps or methods may be implemented in software or firmware stored in a memory and executed by a suitable instruction execution system. All or part of the steps of the method in the above embodiment can be completed by instructing relevant hardware through a program.
  • the program can be stored in a computer-readable storage medium. When executed, the program includes one of the steps of the method embodiment or other steps. combination.
  • each functional unit in various embodiments of the present application can be integrated into a processing module, or each unit can exist physically alone, or two or more units can be integrated into one module.
  • the above integrated modules can be implemented in the form of hardware or software function modules. If the above integrated modules are implemented in the form of software function modules and sold or used as independent products, they can also be stored in a computer-readable storage medium.
  • the storage medium can be a read-only memory, a magnetic disk or an optical disk, etc.

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Abstract

本发明公开了一种利用数据缓存器纠错的DDR双列直插式存储模块、存储系统及其操作方法，DDR双列直插式存储模块包括：第一信道，第一信道包括第一组DRAM颗粒和与第一组DRAM颗粒对应的第一数据缓存器；第一数据缓存器用于在写操作中获取输入至第一信道的所有数据信号位，并对输入至第一信道的所有数据信号位中的数据进行ECC编码，产生ECC校验码，将产生的ECC校验码和输入至第一信道的所有数据信号位中的数据发送给第一组DRAM颗粒。本发明在内存条上就能实现高性能的检错和纠错，能够极大地降低整个内存条的误码率。

Description

DDR双列直插式存储模块、存储系统及其操作方法 技术领域
本发明属于存储器技术领域，更具体地，涉及一种利用数据缓存器纠错的DDR双列直插式存储模块、存储系统及其操作方法。
背景技术
DDR是DDR SDRAM的简称，当前的双倍速率同步动态随机存取存储器(Double Data Rate Synchronous Dynamic Random Access Memory，DDR SDRAM)标准提供一个可支持双列直插式存储模块(Dual-in-line Memory Module，DIMM)设备的通道。随着工艺尺寸的减小、运行速率的增加以及存储容量的增加，内存颗粒存储数据出错的可能性会长期存在。如何通过纠错码技术，使得即使在内存颗粒出现多个错误的情况下，也能实时自动地进行纠错，确保系统正常运行，是一个非常重要的稳定性要求。
在硬件层面，目前内存系统中实现纠错码(Error Correcting Code，ECC)的技术途径主要包括：(1)依靠内存颗粒自身进行纠错，例如，DDR5(第五代DDR SDRAM)内存颗粒本身有1比特纠错码。由于实际情况下很可能会出现更多的错码，因此，这种纠错能力相对比较薄弱。(2)利用内存控制器(Memory Controller，MC)进行纠错。由于内存控制器通常在主处理器(CPU/Host)芯片上，主处理器更新换代较慢，多数通用CPU厂家难以把高性能纠错功能，或者针对某些DRAM颗粒特别有效的纠错码和映射结构设计到内存控制器里，导致内存控制器的纠错能力难以满足现实需要。
发明内容
针对现有技术的以上缺陷或改进需求，本发明提供了一种利用数据缓存器纠错的DDR双列直插式存储模块、存储系统及其操作方法，在内存条上就能实现高性能的检错和纠错，能够极大地降低整个内存条的误码率。
为实现上述目的，按照本发明的一个方面，提供了一种DDR双列直插式存 储模块，包括：第一信道，第一信道包括第一组DRAM颗粒和与第一组DRAM颗粒对应的第一数据缓存器；第一数据缓存器用于在写操作中获取输入至第一信道的所有数据信号位，并对输入至第一信道的所有数据信号位中的数据进行ECC编码，产生ECC校验码，将产生的ECC校验码和输入至第一信道的所有数据信号位中的数据发送给第一组DRAM颗粒。
在一些实施方式中，第一数据缓存器还用于在读操作中从第一组DRAM颗粒获取第一信道的所有数据信号位，检测从第一组DRAM颗粒获取的第一信道的所有数据信号位中的数据是否存在错码，以及在存在错码时，对从第一组DRAM颗粒获取的第一信道的所有数据信号位中的数据进行纠错后再发送出去。
在一些实施方式中，上述DDR双列直插式存储模块还包括电路板，第一信道还包括第二组DRAM颗粒；第一组DRAM颗粒设置于电路板的第一面，第二组DRAM颗粒设置于电路板的与第一面相反的第二面；第一数据缓存器还对应于第二组DRAM颗粒；第一组DRAM颗粒和第二组DRAM颗粒不同时工作。
在一些实施方式中，第一数据缓存器还用于在写操作中获取输入至第一信道的所有数据信号位，并对输入至第一信道的所有数据信号位中的数据进行ECC编码，产生ECC校验码，将产生的ECC校验码和输入至第一信道的所有数据信号位中的数据发送给第二组DRAM颗粒。
在一些实施方式中，第一数据缓存器还用于在读操作中从第二组DRAM颗粒获取第一信道的所有数据信号位，检测从第二组DRAM颗粒获取的第一信道的所有数据信号位中的数据是否存在错码，以及在存在错码时，对从第二组DRAM颗粒获取的第一信道的所有数据信号位中的数据进行纠错后再发送出去。
在一些实施方式中，第一数据缓存器包括第一数据收发器、第二数据收发器、ECC编码器和ECC解码器。
在一些实施方式中，ECC编码器和ECC解码器分别连接在第一数据收发器和第二数据收发器之间，第二数据收发器连接第一组DRAM。
在一些实施方式中，在写操作中，第一数据收发器用于在时钟信号的触发下接收输入至第一信道的所有数据信号位；ECC编码器用于对输入至第一信道的 所有数据信号位中的数据进行ECC编码，产生ECC校验码；第二数据收发器用于将产生的ECC校验码和输入至第一信道的所有数据信号位中的数据发送给第一组DRAM颗粒。
在一些实施方式中，在读操作中，第二数据收发器还用于在时钟信号的触发下从第一组DRAM颗粒获取第一信道的所有数据信号位；ECC解码器用于检测从第一组DRAM颗粒获取的第一信道的所有数据信号位中的数据是否存在错码，以及在存在错码时，将从第一组DRAM颗粒获取的第一信道的所有数据信号位中的数据进行纠错后输出，在不存在错码时，将从第一组DRAM颗粒获取的第一信道的所有数据信号位中的数据输出；第一数据收发器还用于将ECC解码器输出的数据发送出去。
在一些实施方式中，第一数据缓存器还包括第一选择器和第二选择器。
在一些实施方式中，ECC编码器连接在第一选择器和第一数据收发器之间，ECC解码器连接在第二选择器和第二数据收发器之间，第一选择器连接在第一数据收发器和第二数据收发器之间，第二选择器连接在第一数据收发器和第二数据收发器之间，第二数据收发器连接第一组DRAM颗粒。
在一些实施方式中，在写操作中，第一数据收发器用于在时钟信号的触发下接收输入至第一信道的所有数据信号位并输出；ECC编码器用于对输入至第一信道的所有数据信号位中的数据进行ECC编码，产生ECC校验码，并将产生的ECC校验码和输入至第一信道的所有数据信号位中的数据输出。
在一些实施方式中，第一选择器用于在写操作中选择是否打开ECC功能；在ECC功能打开时，第一选择器选择将ECC编码器的输出通过第二数据收发器发送给第一组DRAM颗粒；在ECC功能关闭时，第一选择器选择将第一数据收发器的输出通过第二数据收发器发送给第一组DRAM颗粒。
在一些实施方式中，在读操作中，第二数据收发器用于在时钟信号的触发下从第一组DRAM颗粒获取第一信道的所有数据信号位并输出；ECC解码器用于检测从第一组DRAM颗粒获取的第一信道的所有数据信号位中的数据是否存在错码，以及在存在错码时，将从第一组DRAM颗粒获取的第一信道的所有数据 信号位中的数据进行纠错后输出，在不存在错码时，将从第一组DRAM颗粒获取的第一信道的所有数据信号位中的数据输出。
在一些实施方式中，第二选择器用于在读操作中选择是否打开ECC功能，在ECC功能打开时，第二选择器选择将ECC解码器的输出通过第一数据收发器发送出去；在ECC功能关闭时，第二选择器选择将第二数据收发器的输出通过第一数据收发器发送出去。
在一些实施方式中，第一数据收发器包括多个第一接收模块；多个第一接收模块用于在写操作中获取输入至第一信道的所有数据信号位并输出。
在一些实施方式中，第一接收模块包括第一接收器、第二接收器和第一D触发器；第一接收器用于接收输入至第一信道的数据信号并将其输出至第一D触发器的输入端，第二接收器用于接收写采样时钟并将其输出至第一D触发器的时钟信号输入端，第一D触发器的正向输出端在写采样时钟的上升沿将输入至第一信道的数据信号输出。
在一些实施方式中，第二数据收发器包括多个第二接收模块；多个第二接收模块用于在读操作中从第一组DRAM颗粒获取第一信道的所有数据信号位并输出。
在一些实施方式中，第二接收模块包括第三接收器、第四接收器和第二D触发器；第三接收器用于接收来自第一组DRAM颗粒的数据信号并将其输出至第二D触发器的输入端，第四接收器用于接收读采样时钟并将其输出至第二D触发器的时钟信号输入端，第二D触发器的正向输出端在读采样时钟的上升沿将来自第一组DRAM颗粒的数据信号输出。
在一些实施方式中，第一数据收发器还包括第一发送模块，第一发送模块用于在读操作中将来自ECC解码器的信号或者来自第二数据收发器的信号输出。
在一些实施方式中，第二数据收发器还包括第二发送模块，第二发送模块用于在写操作中将来自ECC编码器的信号或者来自第一数据收发器的信号输出。
按照本发明的另一个方面，提供了一种存储系统，包括CPU和上述DDR双列直插式存储模块；CPU用于对DDR双列直插式存储模块执行读写操作。
按照本发明的又一方面，提供了一种存储系统，包括CPU和DDR双列直插式存储模块；DDR双列直插式存储模块包括第一信道，第一信道包括第一组DRAM颗粒和与第一组DRAM颗粒对应的第一数据缓存器；第一数据缓存器用于在写操作中将CPU发送至第一信道的所有数据信号位中的数据发送至第一组DRAM颗粒，以及在读操作中从第一组DRAM颗粒获取第一信道的所有数据信号位；第一数据缓存器还用于在写操作和读操作中进行ECC纠错。
在一些实施方式中，第一数据缓存器用于在写操作中从CPU获取输入至第一信道的所有数据信号位，并对输入至第一信道的所有数据信号位中的数据进行ECC编码，产生ECC校验码，将产生的ECC校验码和输入至第一信道的所有数据信号位中的数据发送给第一组DRAM颗粒。
在一些实施方式中，第一数据缓存器还用于在读操作中从第一组DRAM颗粒获取第一信道的所有数据信号位，检测从第一组DRAM颗粒获取的第一信道的所有数据信号位中的数据是否存在错码，以及在存在错码时，对从第一组DRAM颗粒获取的第一信道的所有数据信号位中的数据进行纠错后再发送至CPU。
在一些实施方式中，第一信道还包括第二组DRAM颗粒；第一组DRAM颗粒设置于电路板的第一面，第二组DRAM颗粒设置于电路板的与第一面相反的第二面；第一数据缓存器还对应于第二组DRAM颗粒；第一组DRAM颗粒和第二组DRAM颗粒不同时工作。
在一些实施方式中，第一数据缓存器还用于在写操作中从CPU获取输入至第一信道的所有数据信号位，并对输入至第一信道的所有数据信号位中的数据进行ECC编码，产生ECC校验码，将产生的ECC校验码和输入至第一信道的所有数据信号位中的数据发送给第二组DRAM颗粒。
在一些实施方式中，第一数据缓存器还用于在读操作中从第二组DRAM颗粒获取第一信道的所有数据信号位，检测从第二组DRAM颗粒获取的第一信道的所有数据信号位中的数据是否存在错码，以及在存在错码时，对从第二组DRAM颗粒获取的第一信道的所有数据信号位中的数据进行纠错后再发送至 CPU。
在一些实施方式中，DDR双列直插式存储模块还包括第二信道，第二信道包括第三组DRAM颗粒和与第三组DRAM颗粒对应的第二数据缓存器；第二数据缓存器用于在写操作中将CPU发送至第二信道的所有数据信号位中的数据发送至第三组DRAM颗粒，以及在读操作中从第三组DRAM颗粒获取第二信道的所有数据信号位；第二数据缓存器还用于在写操作和读操作中进行ECC纠错。
在一些实施方式中，第二数据缓存器用于在写操作中从CPU获取输入至第二信道的所有数据信号位，并对输入至第二信道的所有数据信号位中的数据进行ECC编码，产生ECC校验码，将产生的ECC校验码和输入至第二信道的所有数据信号位中的数据发送给第三组DRAM颗粒。
在一些实施方式中，第二数据缓存器还用于在读操作中从第三组DRAM颗粒获取第二信道的所有数据信号位，检测从第三组DRAM颗粒获取的第二信道的所有数据信号位中的数据是否存在错码，以及在存在错码时，对从第三组DRAM颗粒获取的第二信道的所有数据信号位中的数据进行纠错后再发送至CPU。
在一些实施方式中，第二信道还包括第四组DRAM颗粒；第三组DRAM颗粒设置于电路板的第一面，第四组DRAM颗粒设置于电路板的第二面；第二数据缓存器还对应于第四组DRAM颗粒；第三组DRAM颗粒和第四组DRAM颗粒不同时工作。
在一些实施方式中，第二数据缓存器还用于在写操作中从CPU获取输入至第二信道的所有数据信号位，并对输入至第二信道的所有数据信号位中的数据进行ECC编码，产生ECC校验码，将产生的ECC校验码和输入至第一信道的所有数据信号位中的数据发送给第四组DRAM颗粒。
在一些实施方式中，第二数据缓存器还用于在读操作中从第四组DRAM颗粒获取第二信道的所有数据信号位，检测从第四组DRAM颗粒获取的第二信道的所有数据信号位中的数据是否存在错码，以及在存在错码时，对从第四组 DRAM颗粒获取的第二信道的所有数据信号位中的数据进行纠错后再发送至CPU。
在一些实施方式中，第一数据缓存器包括第一数据收发器、第二数据收发器、ECC编码器和ECC解码器。
在一些实施方式中，ECC编码器和ECC解码器分别连接在第一数据收发器和第二数据收发器之间，第二数据收发器连接第一组DRAM。
在一些实施方式中，第一数据缓存器还包括第一选择器和第二选择器。
在一些实施方式中，ECC编码器连接在第一选择器和第一数据收发器之间，ECC解码器连接在第二选择器和第二数据收发器之间，第一选择器连接在第一数据收发器和第二数据收发器之间，第二选择器连接在第一数据收发器和第二数据收发器之间，第二数据收发器连接第一组DRAM颗粒。
在一些实施方式中，第二数据缓存器具有与第一数据缓存器相同的结构。
按照本发明的又一个方面，提供了一种DDR双列直插式存储模块的操作方法，包括：从外部获取所在信道的所有数据信号位；对从外部获取的所有数据信号位中的数据进行ECC编码，产生ECC校验码；将ECC校验码和所有数据信号位中的数据一起发送给所在信道的DRAM颗粒。
在一些实施方式中，在ECC功能打开时，执行上述对从外部获取的数据信号位中的数据进行ECC编码，产生ECC校验码；将ECC校验码和数据信号位中的数据一起发送给所在信道的DRAM颗粒的操作。
在一些实施方式中，在ECC功能关闭时，不执行上述对从外部获取的数据信号位中的数据进行ECC编码，产生ECC校验码；将ECC校验码和数据信号位中的数据一起发送给所在信道的DRAM颗粒的操作；而是将从外部获取的所有数据信号位发送给所在信道的DRAM颗粒。
在一些实施方式中，上述操作方法还包括：从DRAM颗粒获取所在信道的所有数据信号位；判断从DRAM颗粒获取的所有数据信号位是否存在错码；如果存在错码，将获取的数据信号位纠错后再发送出去。
在一些实施方式中，在ECC功能打开时，执行上述判断从DRAM颗粒获 取的所有数据信号位是否存在错码；如果存在错码，将获取的数据信号位纠错后再发送出去的操作。
在一些实施方式中，如果存在错码，上述方法还包括存储错误信息。
在一些实施方式中，在ECC功能关闭时，不执行上述判断从DRAM颗粒获取的所有数据信号位是否存在错码；如果存在错码，将获取的数据信号位纠错后再发送出去的操作；而是将从DRAM颗粒获取的所有数据信号位发送出去。
按照本发明的又一个方面，提供了一种DDR双列直插式存储模块的操作方法，包括：执行写操作，获取输入至信道的所有数据信号位，将输入至信道的所有数据信号位中的数据发送至DRAM颗粒；执行读操作，从DRAM颗粒获取信道的所有数据信号位，将从DRAM颗粒获取的信道的所有数据信号位中的数据发送出去；在读操作和写操作的过程中，进行ECC纠错。
在一些实施方式中，在写操作中，对输入至信道的所有数据信号位中的数据进行ECC编码，产生ECC校验码；将ECC校验码和所有数据信号位中的数据一起发送至DRAM颗粒。
在一些实施方式中，在读操作中，判断从DRAM颗粒获取的所有数据信号位是否存在错码；如果存在错码，将获取的数据信号位纠错后再发送出去。
总体而言，通过本发明所构思的以上技术方案与现有技术相比，具有以下有益效果：将原属于一个信道(channel)的所有数据缓存器(Data Buffer,，DB)集成到一起，使得一个信道具有一个数据缓存器，同时使这个数据缓存器具有纠错功能，即，对来自CPU的数据进行纠错编码，对来自内存颗粒的数据进行检错，并实现自动纠错和报错。由于集成后的数据缓存器能够获取其所在信道的全部数据，在内存条上就能实现高性能的检错和纠错，极大地降低了整个内存条的误码率。
附图说明
图1是一种DDR5LRDIMM内存条的布局布线示意图；
图2是本发明一个实施例的利用数据缓存器纠错的DDR5 DIMM内存条的 布局布线示意图；
图3是本发明另一个实施例的利用数据缓存器纠错的DDR5 DIMM内存条的布局布线示意图；
图4是本发明又一个实施例的利用数据缓存器纠错的DDR5 DIMM内存条的布局布线示意图；
图5是本发明又一个实施例的利用数据缓存器纠错的DDR5 DIMM内存条的布局布线示意图；
图6A和图6B分别是本发明又一个实施例的利用数据缓存器纠错的DDR5DIMM内存条的布局布线示意图；
图7是本发明又一个实施例的利用数据缓存器纠错的DDR5 DIMM内存条的布局布线示意图；
图8本发明一个实施例的DDR DIMM内存读写操作过程的示意性框图；
图9是本发明又一个实施例的DDR DIMM内存读写操作过程的示意性框图；
图10是本发明实施例的第一数据收发器的结构框图；
图11是本发明实施例的第二数据收发器的结构框图；
图12是本发明实施例的内存写操作流程示意图；
图13是本发明实施例的内存写操作过程对应的结构示意图；
图14是本发明实施例的内存读操作流程示意图；
图15是本发明实施例的内存读操作过程对应的结构示意图。
具体实施方式
为了使本发明的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本发明进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。正如本领域技术人员可以认识到的那样，在不脱离本申请的精神或范围的情况下，可通过各种不同方式修改所描述的实施例。因此，附图和描述被认为本质上是示例性的而非限制性的。
图1是DDR5负载减少型DIMM(Load Reduced DIMM,，LRDIMM)内存条的布局布线示意图。如图1所示，该内存条两面(例如印制电路板或PCB板的两面)都有内存颗粒，共2个Rank，每面各一个Rank，正面为Rank0(第一Rank)，反面是Rank1(第二Rank)。信道A(第一信道)和信道B(第二信道)分别具有正面10个×4 DRAM颗粒(第一组DRAM颗粒和第三组DRAM颗粒)、反面10个×4 DRAM颗粒(第二组DRAM颗粒和第四组DRAM颗粒)以及5个数据缓存器(DB)。时钟锁存驱动器(Registering Clock Driver,，RCD)和DB均设置在内存条的正面(图1中Rank1的RCD仅用于展现连接关系)。RCD通过命令/地址线连接两面的内存颗粒，各DB通过数据线连接两面与其对应的内存颗粒(图1中Rank1中数据线的连接未示出)，即，每个DB的一侧连接正面的两个内存颗粒和反面的两个内存颗粒，每个DB的另一侧连到内存条边沿的金手指，再通过主板连接CPU的DDR数据线。Rank0和Rank1不会同时工作，在某一时刻，或者是Rank0工作，或者是Rank1工作，或者Rank0和Rank1均不工作，每个DB只负责其所在信道的五分之一的数据。
图2是本发明一个实施例的利用数据缓存器纠错的DDR5 DIMM内存条的布局布线示意图。如图2所示，在图1所示结构的基础上，将信道A和信道B的5个DB分别集成到一起，并进一步增加纠错功能，形成具有纠错能力的数据缓存器(在下文中标记为DBECC)。也就是说，信道A具有一个DBECC(第一数据缓存器)，用于处理信道A上的读操作(从DRAM到CPU)和写操作(从CPU到DRAM)的所有数据，并实现ECC编码、解码、自动纠错和报错。信道B亦是如此，即信道B具有一个DBECC(第二数据缓存器)，用于处理信道B上的读操作(从DRAM到CPU)和写操作(从CPU到DRAM)的所有数据，并实现ECC编码、解码、自动纠错和报错。DBECC的一侧连接其所在信道的多个内存颗粒，另一侧连到内存条边沿的金手指，再通过主板连接CPU的DDR数据线。
信道A和信道B的内存颗粒可以具有相同的布局。以信道A为例，Rank0具有10个×4 DRAM颗粒，这10个×4 DRAM颗粒分两行设置，每行各设置5 个×4 DRAM颗粒。Rank1也具有10个×4 DRAM颗粒，这10个×4 DRAM颗粒分两行设置，每行设置5个×4 DRAM颗粒。RCD和两个DBECC均设置在内存条的正面(图2中Rank1的RCD仅用于展现连接关系)，RCD设置在信道A的内存颗粒和信道B的内存颗粒之间。信道A和信道B的DBECC分别设置在Rank0的两行DRAM颗粒之后的第三行所在的位置。
应当了解，图2中所示的DRAM颗粒的宽度和高度，DBECC的宽度和高度，仅作为示例。根据实际存储容量和制造工艺，DRAM颗粒的宽度和高度可以定制，DBECC的宽度和高度也可以根据内存条上DRAM颗粒的布局进行优化，本发明对此不做限制。
图3是本发明另一个实施例的利用数据缓存器纠错的DDR5 DIMM内存条的布局布线示意图。如图3所示，在图2所示结构的基础上，将DBECC的位置作了调整，并对应地调整了内存颗粒的位置。具体地，以信道A为例，将Rank0的10个×4 DRAM颗粒分两行设置，其中第一行内存颗粒的数量与第二行内存颗粒的数量不相同，DBECC设置在具有较少数量的内存颗粒所在的行内，即，DBECC的两侧均设置有内存颗粒。在一些实施方式中，DBECC设置在具有较少数量的内存颗粒所在的行内最靠近中间的位置。例如，图3中，第一行设置6个内存颗粒，第二行设置4个内存颗粒，DBECC设置在第二行4个内存颗粒的中间位置，即DBECC的两侧各有2个内存颗粒。再例如，第一行设置7个内存颗粒，第二行设置3个内存颗粒，DBECC设置在第二行3个内存颗粒的最靠近中间的位置，即DBECC的一侧有2个内存颗粒，另一侧有1个内存颗粒。信道A的Rank1具有与Rank0相同的内存颗粒布局，信道B具有与信道A相同的内存颗粒布局和DBECC布局。
图4是本发明又一个实施例的利用数据缓存器纠错的DDR5 DIMM内存条的布局布线示意图。如图4所示，在图2所示结构的基础上，将DBECC的位置作了调整，并对应地调整了内存颗粒的位置。具体地，以信道A为例，将Rank0的10个×4 DRAM颗粒分两行设置，每行各设置5个×4 DRAM颗粒。DBECC跨行设置在第一行内存颗粒和第二行内存颗粒之间。在一些实施方式中，DBECC 设置在第一行和第二行内存颗粒的最靠近中间的位置。例如，DBECC在第一行和第二行的一侧各有3个内存颗粒，在第一行和第二行的另一侧各有2个内存颗粒。信道A的Rank1具有与Rank0相同的内存颗粒布局，信道B具有与信道A相同的内存颗粒布局和DBECC布局。
在图2至4所示的实施例中，单个信道的Rank0和Rank1均具有偶数个内存颗粒，在Rank0或Rank1工作时，DBECC提供40位数据信号给10个×4 DRAM颗粒，这40位数据信号中，32位是数据，8位是ECC校验码。应当理解，本发明实施例的单个信道的Rank0和Rank1的内存颗粒还可以为奇数个，本发明对此不做限制。
如图5所示，信道A的Rank0具有11个×4 DRAM颗粒，这11个×4 DRAM颗粒分两行设置，其中第一行内存颗粒的数量与第二行内存颗粒的数量不相同，DBECC设置在具有较少数量的内存颗粒所在的行内，即，DBECC的两侧均设置有内存颗粒。在一些实施方式中，DBECC设置在具有较少数量的内存颗粒所在的行内最靠近中间的位置。例如，第一行设置7个内存颗粒，第二行设置4个内存颗粒，DBECC设置在第二行4个内存颗粒的中间位置，即DBECC的两侧各有2个内存颗粒。信道A的Rank1具有与Rank0相同的内存颗粒布局，信道B具有与信道A相同的内存颗粒布局和DBECC布局。
具体地，DBECC提供44位数据信号给11个×4 DRAM颗粒。这44位数据信号中，32位是数据，12位是ECC校验码。
可以理解的是，校验码越多，其具备的纠错能力越强。为了能纠正更多地误码，也可以产生更多地校验码，但是对应地需要有更多的×4 DRAM颗粒来支持。例如，DBECC可以提供48位数据信号给12个×4 DRAM颗粒。这48位数据信号中，32位是数据，16位是ECC校验码。
在图2至5所示的实施例中，内存颗粒均为×4 DRAM。应当理解，本发明实施例的DDR DIMM的内存颗粒还可以为×8 DRAM。
如图6A所示，信道A的Rank0具有5个×8 DRAM颗粒，这5个×8 DRAM颗粒设置在同一行，DBECC设置在Rank0的一行DRAM颗粒之后的第二行所 在的位置。信道A的Rank1具有与Rank0相同的内存颗粒布局，信道B具有与信道A相同的内存颗粒布局和DBECC布局。DBECC提供40位数据信号给5个×8 DRAM颗粒，这40位数据信号中，32位是数据，8位是ECC校验码。
图6B是信道A的Rank0具有6个×8 DRAM颗粒的情形。6个×8 DRAM颗粒，DBECC提供48位数据信号给6个×8 DRAM颗粒，这48位数据信号中，32位是数据，16位是ECC校验码。
同样地，校验码越多，其具备的纠错能力越强。为了能纠正更多地误码，也可以产生更多地校验码，但是对应地需要有更多的x8 DRAM颗粒来支持。例如，DBECC可以提供56位数据信号给7个x8 DRAM颗粒。这56位数据信号中，32位是数据，24位是ECC校验码。
在图2至6所示的实施例中，均包含两个Rank，即Rank0和Rank1。在图2、图6A和图6B中，第一Rank具有多个行位置，数据缓存器和第一组DRAM颗粒占据不同的行位置。在图3至5中，第一Rank具有多个行位置，第一组DRAM颗粒占据该多个行位置，数据缓存器占据第一组DRAM颗粒的一个或多个行位置。例如，图3和图5中，数据缓存器占据第一组DRAM颗粒的一个行位置，图4中，数据缓存器占据第一组DRAM颗粒的所有两个行位置。
应当理解，本发明实施例的DDR DIMM还可以只具有一个Rank。如图7所示，DDR DIMM内存条仅正面设置有DRAM颗粒，只有一个Rank0。信道A的Rank0具有10个×4 DRAM颗粒，DBECC设置在内存条的反面(正面的DBECC仅用于说明连接关系)。信道B具有与信道A相同的内存颗粒布局和DBECC布局。DBECC提供40位数据信号给10个×4 DRAM颗粒，这40位数据信号中，32位是数据，8位是ECC校验码。
以上只是给出了一些内存条上用DBECC的布局布线的例子，在实际实现中，可以根据DRAM颗粒的宽度和高度，内存条有几个Rank，来具体决定最佳的布局布线方式，本发明对此不作限制。
图8为本发明实施例的DDR DIMM内存读写操作过程的示意性框图。如图8所示，DBECC 701分别连接CPU和DRAM颗粒。在写操作过程中，DBECC  701从CPU接收其所在信道的所有数据信号位，对所有数据信号位中的数据进行ECC编码，产生新的ECC校验码，将新产生的ECC校验码和数据一起发送给DRAM颗粒。在读操作过程中，DBECC 701从DRAM颗粒接收其所在信道的所有数据信号位，包括数据位和校验码位，检测所有数据信号位中的数据是否存在错码，如果不存在错码，则将所有数据信号位中的数据发送给CPU；如果存在错码，DBECC在自动纠错后，将纠错后的数据发送给CPU。
具体地，如图8所示，DBECC 701包括第一数据收发器、第二数据收发器和ECC纠错模块703，ECC纠错模块703进一步包括ECC编码器和ECC解码器。在写操作过程中，第一数据收发器在系统时钟的上升沿从CPU接收其所在信道的所有数据信号位，ECC编码器对所有数据信号位中的数据进行ECC编码，产生新的ECC校验码，将新产生的ECC校验码和所有数据信号位中的数据一起通过第二数据收发器发送给DRAM颗粒。在读操作过程中，第二数据收发器在系统时钟的上升沿接收其所在信道的所有数据信号位，包括数据位和校验码位，ECC解码器检测所有数据信号位中的数据是否存在错码，如果不存在错码，则将所有数据信号位中的数据通过第一数据收发器发送给CPU；如果存在错码，ECC解码器在自动纠错后，将纠错后的数据通过第一数据收发器发送给CPU。
在一些实施方式中，如果存在错误，ECC解码器在自动纠错后，还将具体的错误信息存储在本地寄存器中，以供CPU读出并进行后续处理。
图9是本发明又一个实施例的DDR DIMM内存读写操作过程的示意性框图。如图9所示，DBECC 801包括第一数据收发器、第二数据收发器、ECC纠错模块703、第一选择器和第二选择器。在写操作过程中，第一数据收发器在系统时钟的上升沿从CPU接收其所在信道的所有数据信号位，当第一选择器的控制端选择打开ECC功能时，ECC编码器对所有数据信号位中的数据进行ECC编码，产生新的ECC校验码，将新产生的ECC校验码和所有数据信号位中的数据一起由第一选择器输出至第二数据收发器，通过第二数据收发器发送给DRAM颗粒；当第一选择器的控制端选择关闭ECC功能时，第一选择器将第一数据收发器接收到的所有数据信号位输出至第二数据收发器，通过第二数据收 发器发送给DRAM颗粒，这种情况下，系统会依赖CPU的内存控制器进行纠错。
在读操作过程中，第二数据收发器在系统时钟的上升沿从DRAM颗粒接收其所在信道的所有数据信号位，包括数据位和校验码位，当第二选择器的控制端选择打开ECC功能时，ECC解码器检测所有数据信号位中的数据是否存在错码，如果不存在错码，则将所有数据信号位中的数据由第二选择器输出至第一数据收发器，通过第一数据收发器发送给CPU；如果存在错码，ECC解码器在自动纠错后，将纠错后的数据由第二选择器输出至第一数据收发器，通过第一数据收发器发送给CPU。当第二选择器的控制端选择关闭ECC功能时，第二选择器将第二数据收发器接收到的所有数据信号位输出至第一数据收发器，通过第一数据收发器发送给CPU，这种情况下，系统会依赖CPU的内存控制器进行纠错。
在一些实施方式中，第一选择器和第二选择器的控制端具有相同的信号输入。在一些实施方式中，第一数据收发器和第二数据收发器具有相同的结构。
图10是本发明实施例的第一数据收发器的结构框图。如图10所示，第一数据收发器901包括多个第一接收模块903和第一发送模块905，多个第一接收模块903连接CPU，用于从CPU获取所在信道的所有数据信号位，并将获取的数据信号分别发送给第一选择器和ECC编码器。第一发送模块905连接第二选择器，用于将第二选择器输出的数据信号发送给CPU。
具体地，第一接收模块903包括第一接收器(RX1)、第二接收器(RX2)和第一D触发器。第一接收器用于接收来自CPU的数据信号并将其输出至第一D触发器的输入端(D端)，第二接收器用于接收来自CPU的采样时钟(DQS)并将其输出至第一D触发器的时钟信号输入端，第一D触发器的正向输出端(Q端)在时钟信号的上升沿将来自CPU的数据信号输出。
第一发送模块905包括读先进先出模块(Read FIFO)和第一发送器(TX1)。读先进先出模块用于获取来自第二选择器的数据信号，并通过第一发送器将该数据信号发送给CPU。
类似地，如图11所示，第二数据收发器1001包括多个第二接收模块1003 和第二发送模块1005，多个第二接收模块1003分别连接DRAM内存颗粒，用于从DRAM内存颗粒获取数据信号，并将获取的数据信号分别发送给第二选择器和ECC解码器。第二发送模块1005连接第一选择器，用于将第一选择器输出的数据信号发送给DRAM内存颗粒。
具体地，第二接收模块1003包括第三接收器(RX3)、第四接收器(RX4)和第二D触发器。第三接收器用于接收来自DRAM的数据信号并将其输出至第二D触发器的输入端(D端)，第四接收器用于接收采样时钟(MDQS)并将其输出至第二D触发器的时钟信号输入端，第二D触发器的正向输出端(Q端)在时钟信号的上升沿将来自DRAM的数据信号输出。
第二发送模块1005包括写先进先出模块(Write FIFO)和第二发送器(TX2)。写先进先出模块用于获取来自第一选择器的数据信号，并通过第二发送器将该数据信号发送给DRAM颗粒。
图12是本发明实施例的内存写操作流程示意图，图13是本发明实施例的内存写操作过程对应的结构示意图，图14是本发明实施例的内存读操作流程示意图，图15是本发明实施例的内存读操作过程对应的结构示意图。下面以单个信道的Rank0具有10个×4 DRAM颗粒为例对本发明实施例的内存读写操作过程进行详细说明。
如图12所示，本发明实施例的DDR双列直插式存储模块的写操作过程包括：
步骤1201：从CPU获取所在信道的所有数据信号位。
如图13所示，多个第一接收模块903在DQ采样时钟(DQS)的上升沿从CPU获取所在信道的所有数据信号位，一共40位数据信号，其中32位是数据，8位是ECC校验码，每个第一接收模块903获取4位数据信号，即一个DQ Nibble，分别标记为Nibble0-9。其中，DQ表示CPU与DBECC连接的数据线。
步骤1203：在ECC功能打开时，对从外部获取的所有数据信号位中的数据进行ECC编码，产生ECC校验码。
如图13所示，当第一选择器1101的ECC功能打开时(默认设置)，ECC 编码器会对32位数据(在本发明实施例中，可以由Nibble0-7组成32位数据)进行ECC编码，产生新的8位ECC校验码，输出新产生的8位ECC校验码和32位数据。
步骤1205：将ECC校验码和所有数据信号位中的数据一起发送给所在信道的DRAM颗粒。
如图13所示，第一选择器1101选择将ECC编码器输出的新产生的8位ECC校验码和32位数据一起输出，通过写先进先出模块和第二发送器发送给DRAM颗粒。可以理解的是，在ECC功能打开的时候，DBECC可忽略CPU发来的8位ECC码(例如Nibble8-9)，而采用自身计算出的新的8位ECC校验码进行传输和后续校验流程。
步骤1207：在ECC功能关闭时，将从外部获取的所有数据信号位发送给所在信道的DRAM颗粒。
如图13所示，当第一选择器1101的ECC功能关闭时，DBECC会把CPU发来的40位信号(例如可以由Nibble0-9组成)直接通过Write FIFO和第二发送器发送给DRAM颗粒。这种情况下，系统会依赖CPU内存控制器进行纠错。
如图14所示，本发明实施例的DDR双列直插式存储模块的读操作过程包括：
步骤1401：从DRAM颗粒获取所在信道的所有数据信号位。
如图15所示，在内存读操作过程中，多个第二接收模块1003在MDQ采样时钟(MDQS)的上升沿从DRAM内存颗粒获取所在信道的所有数据信号位，一共40位数据信号，其中32位是数据，8位是ECC校验码，每个第二接收模块1003获取4位数据信号，即一个MDQ Nibble，一共10个Nibble。其中，MDQ表示DBECC与DRAM颗粒连接的数据线。
步骤1403：在ECC功能打开时，判断从DRAM颗粒获取的所有数据信号位是否存在错码。
如图15所示，当第二选择器1201的ECC功能打开时(默认设置)，首先通过ECC解码器解码判断是否存在错码。
步骤1405：如果存在错码，将获取的所有数据信号位纠错后再发送出去。
如图15所示，如果存在错码，ECC解码器就会进行自动纠错，第二选择器1201选择将ECC解码器输出的纠错后的数据信号通过读先进先出模块和第一发送器发送给CPU。这种情况下，DBECC还会把具体的错误信息存储在本地寄存器中，以供CPU读出并进行后续处理。
步骤1407：如果不存在错码，将从DRAM颗粒获取的所有数据信号位输出。
如图15所示，如果不存在错码，则数据信号不需要改变，第二选择器1201选择将ECC解码器输出的从DRAM颗粒获取的所有数据信号位通过读先进先出模块和第一发送器发送给CPU。
步骤1409：在ECC功能关闭时，将从DRAM颗粒获取的所有数据信号位输出。
如图15所示，当第二选择器1201的ECC功能关闭时，第二选择器1201选择将多个第二接收模块输出的从DRAM内存颗粒获取的所在信道的所有数据信号位会直接通过读先进先出模块和第一发送器发送给CPU。这种情况下，系统会依赖CPU内存控制器进行纠错。
在本发明实施例中，纠错码有很多选择，比如汉明编码，里德所罗门密码，也可以是其他的区块码(Block codes)或者卷积码(Convolutional codes)。码长和具体映射需要根据内存颗粒出错的特性来决定。
在本发明实施例中，DRAM内存颗粒可以是DDR4、DDR5、DDR6、LPDDR或者GDDR，也可以是LPDDR4、LPDDR5或者LPDDR5x，还可以是其他形态的DRAM内存颗粒，本发明对此不做限制。
在本说明书的描述中，参考术语“一个实施例”、“一些实施例”、“示例”、“具体示例”、或“一些示例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特点包括于本申请的至少一个实施例或示例中。而且，描述的具体特征、结构、材料或者特点可以在任一个或多个实施例或示例中以合适的方式结合。此外，在不相互矛盾的情况下，本领域的技术人员可以将本说明书中描述的不同实施例或示例以及不同实施例或示例的特征进行结合和组合。
此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或隐含地包括至少一个该特征。在本申请的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
流程图中或在此以其他方式描述的任何过程或方法描述可以被理解为，表示包括一个或多个(两个或两个以上)用于实现特定逻辑功能或过程的步骤的可执行指令的代码的模块、片段或部分。并且本申请的优选实施方式的范围包括另外的实现，其中可以不按所示出或讨论的顺序，包括根据所涉及的功能按基本同时的方式或按相反的顺序，来执行功能。
在流程图中表示或在此以其他方式描述的逻辑和/或步骤，例如，可以被认为是用于实现逻辑功能的可执行指令的定序列表，可以具体实现在任何计算机可读介质中，以供指令执行系统、装置或设备(如基于计算机的系统、包括处理器的系统或其他可以从指令执行系统、装置或设备取指令并执行指令的系统)使用，或结合这些指令执行系统、装置或设备而使用。
应理解的是，本申请的各部分可以用硬件、软件、固件或它们的组合来实现。在上述实施方式中，多个步骤或方法可以用存储在存储器中且由合适的指令执行系统执行的软件或固件来实现。上述实施例方法的全部或部分步骤是可以通过程序来指令相关的硬件完成，该程序可以存储于一种计算机可读存储介质中，该程序在执行时，包括方法实施例的步骤之一或其组合。
此外，在本申请各个实施例中的各功能单元可以集成在一个处理模块中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个模块中。上述集成的模块既可以采用硬件的形式实现，也可以采用软件功能模块的形式实现。上述集成的模块如果以软件功能模块的形式实现并作为独立的产品销售或使用时，也可以存储在一个计算机可读存储介质中。该存储介质可以是只读存储器，磁盘或光盘等。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到其各 种变化或替换，这些都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以权利要求的保护范围为准。

Claims (49)

  1. 一种DDR双列直插式存储模块，其特征在于，包括：第一信道，所述第一信道包括第一组DRAM颗粒和与所述第一组DRAM颗粒对应的第一数据缓存器；所述第一数据缓存器用于在写操作中获取输入至所述第一信道的所有数据信号位，并对输入至所述第一信道的所有数据信号位中的数据进行ECC编码，产生ECC校验码，将产生的ECC校验码和输入至所述第一信道的所有数据信号位中的数据发送给所述第一组DRAM颗粒。
  2. 如权利要求1所述的DDR双列直插式存储模块，其特征在于，所述第一数据缓存器还用于在读操作中从所述第一组DRAM颗粒获取所述第一信道的所有数据信号位，检测从所述第一组DRAM颗粒获取的所述第一信道的所有数据信号位中的数据是否存在错码，以及在存在错码时，对从所述第一组DRAM颗粒获取的所述第一信道的所有数据信号位中的数据进行纠错后再发送出去。
  3. 如权利要求1所述的DDR双列直插式存储模块，其特征在于，还包括电路板，所述第一信道还包括第二组DRAM颗粒；所述第一组DRAM颗粒设置于所述电路板的第一面，所述第二组DRAM颗粒设置于所述电路板的与所述第一面相反的第二面；所述第一数据缓存器还对应于所述第二组DRAM颗粒；所述第一组DRAM颗粒和所述第二组DRAM颗粒不同时工作。
  4. 如权利要求3所述的DDR双列直插式存储模块，其特征在于，所述第一数据缓存器还用于在写操作中获取输入至所述第一信道的所有数据信号位，并对输入至所述第一信道的所有数据信号位中的数据进行ECC编码，产生ECC校验码，将产生的ECC校验码和输入至所述第一信道的所有数据信号位中的数据发送给所述第二组DRAM颗粒。
  5. 如权利要求3所述的DDR双列直插式存储模块，其特征在于，所述第一数据缓存器还用于在读操作中从所述第二组DRAM颗粒获取所述第一信道的所有数据信号位，检测从所述第二组DRAM颗粒获取的所述第一信道的所有数据信号位中的数据是否存在错码，以及在存在错码时，对从所述第二组DRAM 颗粒获取的所述第一信道的所有数据信号位中的数据进行纠错后再发送出去。
  6. 如权利要求1至5中任一项所述的DDR双列直插式存储模块，其特征在于，所述第一数据缓存器包括第一数据收发器、第二数据收发器、ECC编码器和ECC解码器。
  7. 如权利要求6所述的DDR双列直插式存储模块，其特征在于，所述ECC编码器和所述ECC解码器分别连接在所述第一数据收发器和所述第二数据收发器之间，所述第二数据收发器连接所述第一组DRAM。
  8. 如权利要求6所述的DDR双列直插式存储模块，其特征在于，在写操作中，所述第一数据收发器用于在时钟信号的触发下接收输入至所述第一信道的所有数据信号位；所述ECC编码器用于对输入至所述第一信道的所有数据信号位中的数据进行ECC编码，产生ECC校验码；所述第二数据收发器用于将产生的ECC校验码和输入至所述第一信道的所有数据信号位中的数据发送给所述第一组DRAM颗粒。
  9. 如权利要求6所述的DDR双列直插式存储模块，其特征在于，在读操作中，所述第二数据收发器还用于在时钟信号的触发下从所述第一组DRAM颗粒获取所述第一信道的所有数据信号位；所述ECC解码器用于检测从所述第一组DRAM颗粒获取的所述第一信道的所有数据信号位中的数据是否存在错码，以及在存在错码时，将从所述第一组DRAM颗粒获取的所述第一信道的所有数据信号位中的数据进行纠错后输出，在不存在错码时，将从所述第一组DRAM颗粒获取的所述第一信道的所有数据信号位中的数据输出；所述第一数据收发器还用于将所述ECC解码器输出的数据发送出去。
  10. 如权利要求6所述的DDR双列直插式存储模块，其特征在于，所述第一数据缓存器还包括第一选择器和第二选择器。
  11. 如权利要求10所述的DDR双列直插式存储模块，其特征在于，所述ECC编码器连接在所述第一选择器和所述第一数据收发器之间，所述ECC解码器连接在所述第二选择器和所述第二数据收发器之间，所述第一选择器连接在所述第一数据收发器和所述第二数据收发器之间，所述第二选择器连接在所述 第一数据收发器和所述第二数据收发器之间，所述第二数据收发器连接所述第一组DRAM颗粒。
  12. 如权利要求10所述的DDR双列直插式存储模块，其特征在于，在写操作中，所述第一数据收发器用于在时钟信号的触发下接收输入至所述第一信道的所有数据信号位并输出；所述ECC编码器用于对输入至所述第一信道的所有数据信号位中的数据进行ECC编码，产生ECC校验码，并将产生的ECC校验码和输入至所述第一信道的所有数据信号位中的数据输出。
  13. 如权利要求12所述的DDR双列直插式存储模块，其特征在于，所述第一选择器用于在写操作中选择是否打开ECC功能；在ECC功能打开时，所述第一选择器选择将所述ECC编码器的输出通过所述第二数据收发器发送给所述第一组DRAM颗粒；在ECC功能关闭时，所述第一选择器选择将所述第一数据收发器的输出通过所述第二数据收发器发送给所述第一组DRAM颗粒。
  14. 如权利要求10所述的DDR双列直插式存储模块，其特征在于，在读操作中，所述第二数据收发器用于在时钟信号的触发下从所述第一组DRAM颗粒获取所述第一信道的所有数据信号位并输出；所述ECC解码器用于检测从所述第一组DRAM颗粒获取的所述第一信道的所有数据信号位中的数据是否存在错码，以及在存在错码时，将从所述第一组DRAM颗粒获取的所述第一信道的所有数据信号位中的数据进行纠错后输出，在不存在错码时，将从所述第一组DRAM颗粒获取的所述第一信道的所有数据信号位中的数据输出。
  15. 如权利要求14所述的DDR双列直插式存储模块，其特征在于，所述第二选择器用于在读操作中选择是否打开ECC功能，在ECC功能打开时，所述第二选择器选择将所述ECC解码器的输出通过所述第一数据收发器发送出去；在ECC功能关闭时，所述第二选择器选择将所述第二数据收发器的输出通过所述第一数据收发器发送出去。
  16. 如权利要求6所述的DDR双列直插式存储模块，其特征在于，所述第一数据收发器包括多个第一接收模块；所述多个第一接收模块用于在写操作中获取输入至所述第一信道的所有数据信号位并输出。
  17. 如权利要求16所述的DDR双列直插式存储模块，其特征在于，所述第一接收模块包括第一接收器、第二接收器和第一D触发器；所述第一接收器用于接收输入至所述第一信道的数据信号并将其输出至所述第一D触发器的输入端，所述第二接收器用于接收写采样时钟并将其输出至所述第一D触发器的时钟信号输入端，所述第一D触发器的正向输出端在写采样时钟的上升沿将输入至所述第一信道的数据信号输出。
  18. 如权利要求6所述的DDR双列直插式存储模块，其特征在于，所述第二数据收发器包括多个第二接收模块；所述多个第二接收模块用于在读操作中从所述第一组DRAM颗粒获取所述第一信道的所有数据信号位并输出。
  19. 如权利要求18所述的DDR双列直插式存储模块，其特征在于，所述第二接收模块包括第三接收器、第四接收器和第二D触发器；所述第三接收器用于接收来自所述第一组DRAM颗粒的数据信号并将其输出至所述第二D触发器的输入端，所述第四接收器用于接收读采样时钟并将其输出至所述第二D触发器的时钟信号输入端，所述第二D触发器的正向输出端在读采样时钟的上升沿将来自所述第一组DRAM颗粒的数据信号输出。
  20. 如权利要求6所述的DDR双列直插式存储模块，其特征在于，所述第一数据收发器还包括第一发送模块，所述第一发送模块用于在读操作中将来自所述ECC解码器的信号或者来自所述第二数据收发器的信号输出。
  21. 如权利要求6所述的DDR双列直插式存储模块，其特征在于，所述第二数据收发器还包括第二发送模块，所述第二发送模块用于在写操作中将来自所述ECC编码器的信号或者来自所述第一数据收发器的信号输出。
  22. 一种存储系统，其特征在于，包括CPU和权利要求1至21中任一项所述的DDR双列直插式存储模块；所述CPU用于对所述DDR双列直插式存储模块执行读写操作。
  23. 一种存储系统，其特征在于，包括CPU和DDR双列直插式存储模块；所述DDR双列直插式存储模块包括第一信道，所述第一信道包括第一组DRAM颗粒和与所述第一组DRAM颗粒对应的第一数据缓存器；所述第一数据缓存器 用于在写操作中将所述CPU发送至所述第一信道的所有数据信号位中的数据发送至所述第一组DRAM颗粒，以及在读操作中从所述第一组DRAM颗粒获取所述第一信道的所有数据信号位；所述第一数据缓存器还用于在写操作和读操作中进行ECC纠错。
  24. 如权利要求23所述的存储系统，其特征在于，所述第一数据缓存器用于在写操作中从所述CPU获取输入至所述第一信道的所有数据信号位，并对输入至所述第一信道的所有数据信号位中的数据进行ECC编码，产生ECC校验码，将产生的ECC校验码和输入至所述第一信道的所有数据信号位中的数据发送给所述第一组DRAM颗粒。
  25. 如权利要求23所述的存储系统，其特征在于，所述第一数据缓存器还用于在读操作中从所述第一组DRAM颗粒获取所述第一信道的所有数据信号位，检测从所述第一组DRAM颗粒获取的所述第一信道的所有数据信号位中的数据是否存在错码，以及在存在错码时，对从所述第一组DRAM颗粒获取的所述第一信道的所有数据信号位中的数据进行纠错后再发送至所述CPU。
  26. 如权利要求23所述的存储系统，其特征在于，还包括电路板，所述第一信道还包括第二组DRAM颗粒；所述第一组DRAM颗粒设置于所述电路板的第一面，所述第二组DRAM颗粒设置于所述电路板的与所述第一面相反的第二面；所述第一数据缓存器还对应于所述第二组DRAM颗粒；所述第一组DRAM颗粒和所述第二组DRAM颗粒不同时工作。
  27. 如权利要求26所述的存储系统，其特征在于，所述第一数据缓存器还用于在写操作中从所述CPU获取输入至所述第一信道的所有数据信号位，并对输入至所述第一信道的所有数据信号位中的数据进行ECC编码，产生ECC校验码，将产生的ECC校验码和输入至所述第一信道的所有数据信号位中的数据发送给所述第二组DRAM颗粒。
  28. 如权利要求26所述的存储系统，其特征在于，所述第一数据缓存器还用于在读操作中从所述第二组DRAM颗粒获取所述第一信道的所有数据信号位，检测从所述第二组DRAM颗粒获取的所述第一信道的所有数据信号位中的数据 是否存在错码，以及在存在错码时，对从所述第二组DRAM颗粒获取的所述第一信道的所有数据信号位中的数据进行纠错后再发送至所述CPU。
  29. 如权利要求23至28中任一项所述的存储系统，其特征在于，所述DDR双列直插式存储模块还包括第二信道，所述第二信道包括第三组DRAM颗粒和与所述第三组DRAM颗粒对应的第二数据缓存器；所述第二数据缓存器用于在写操作中将所述CPU发送至所述第二信道的所有数据信号位中的数据发送至所述第三组DRAM颗粒，以及在读操作中从所述第三组DRAM颗粒获取所述第二信道的所有数据信号位；所述第二数据缓存器还用于在写操作和读操作中进行ECC纠错。
  30. 如权利要求29所述的存储系统，其特征在于，所述第二数据缓存器用于在写操作中从所述CPU获取输入至所述第二信道的所有数据信号位，并对输入至所述第二信道的所有数据信号位中的数据进行ECC编码，产生ECC校验码，将产生的ECC校验码和输入至所述第二信道的所有数据信号位中的数据发送给所述第三组DRAM颗粒。
  31. 如权利要求29所述的存储系统，其特征在于，所述第二数据缓存器还用于在读操作中从所述第三组DRAM颗粒获取所述第二信道的所有数据信号位，检测从所述第三组DRAM颗粒获取的所述第二信道的所有数据信号位中的数据是否存在错码，以及在存在错码时，对从所述第三组DRAM颗粒获取的所述第二信道的所有数据信号位中的数据进行纠错后再发送至所述CPU。
  32. 如权利要求29所述的存储系统，其特征在于，所述第二信道还包括第四组DRAM颗粒；所述第三组DRAM颗粒设置于所述电路板的第一面，所述第四组DRAM颗粒设置于所述电路板的第二面；所述第二数据缓存器还对应于所述第四组DRAM颗粒；所述第三组DRAM颗粒和所述第四组DRAM颗粒不同时工作。
  33. 如权利要求32所述的存储系统，其特征在于，所述第二数据缓存器还用于在写操作中从所述CPU获取输入至所述第二信道的所有数据信号位，并对输入至所述第二信道的所有数据信号位中的数据进行ECC编码，产生ECC校 验码，将产生的ECC校验码和输入至所述第一信道的所有数据信号位中的数据发送给所述第四组DRAM颗粒。
  34. 如权利要求32所述的存储系统，其特征在于，所述第二数据缓存器还用于在读操作中从所述第四组DRAM颗粒获取所述第二信道的所有数据信号位，检测从所述第四组DRAM颗粒获取的所述第二信道的所有数据信号位中的数据是否存在错码，以及在存在错码时，对从所述第四组DRAM颗粒获取的所述第二信道的所有数据信号位中的数据进行纠错后再发送至所述CPU。
  35. 如权利要求29所述的存储系统，其特征在于，所述第一数据缓存器包括第一数据收发器、第二数据收发器、ECC编码器和ECC解码器。
  36. 如权利要求35所述的存储系统，其特征在于，所述ECC编码器和所述ECC解码器分别连接在所述第一数据收发器和所述第二数据收发器之间，所述第二数据收发器连接所述第一组DRAM。
  37. 如权利要求35所述的存储系统，其特征在于，所述第一数据缓存器还包括第一选择器和第二选择器。
  38. 如权利要求37所述的存储系统，其特征在于，所述ECC编码器连接在所述第一选择器和所述第一数据收发器之间，所述ECC解码器连接在所述第二选择器和所述第二数据收发器之间，所述第一选择器连接在所述第一数据收发器和所述第二数据收发器之间，所述第二选择器连接在所述第一数据收发器和所述第二数据收发器之间，所述第二数据收发器连接所述第一组DRAM颗粒。
  39. 如权利要求29所述的存储系统，其特征在于，所述第二数据缓存器具有与所述第一数据缓存器相同的结构。
  40. 一种DDR双列直插式存储模块的操作方法，其特征在于，包括：
    从外部获取所在信道的所有数据信号位；
    对从外部获取的所有数据信号位中的数据进行ECC编码，产生ECC校验码；
    将ECC校验码和所有数据信号位中的数据一起发送给所在信道的DRAM颗粒。
  41. 如权利要求40所述的操作方法，其特征在于，在ECC功能打开时，执行所述将ECC校验码和数据信号位中的数据一起发送给所在信道的DRAM颗粒的操作。
  42. 如权利要求40所述的操作方法，其特征在于，在ECC功能关闭时，将从外部获取的所有数据信号位发送给所在信道的DRAM颗粒。
  43. 如权利要求40至42中任一项所述的操作方法，其特征在于，还包括：
    从DRAM颗粒获取所在信道的所有数据信号位；
    判断从DRAM颗粒获取的所有数据信号位是否存在错码；
    如果存在错码，将获取的数据信号位纠错后再发送出去。
  44. 如权利要求43所述的操作方法，其特征在于，在ECC功能打开时，执行所述将获取的数据信号位纠错后再发送出去的操作。
  45. 如权利要求43所述的操作方法，其特征在于，如果存在错码，所述方法还包括存储错误信息。
  46. 如权利要求43所述的操作方法，其特征在于，在ECC功能关闭时，将从DRAM颗粒获取的所有数据信号位发送出去。
  47. 一种DDR双列直插式存储模块的操作方法，其特征在于，包括：
    执行写操作，获取输入至信道的所有数据信号位，将输入至信道的所有数据信号位中的数据发送至DRAM颗粒；
    执行读操作，从DRAM颗粒获取信道的所有数据信号位，将从DRAM颗粒获取的信道的所有数据信号位中的数据发送出去；
    在读操作和写操作的过程中，进行ECC纠错。
  48. 如权利要求47所述的DDR双列直插式存储模块的操作方法，其特征在于，在写操作中，对输入至信道的所有数据信号位中的数据进行ECC编码，产生ECC校验码；将ECC校验码和所有数据信号位中的数据一起发送至DRAM颗粒。
  49. 如权利要求47所述的DDR双列直插式存储模块的操作方法，其特征在于，在读操作中，判断从DRAM颗粒获取的所有数据信号位是否存在错码； 如果存在错码，将获取的数据信号位纠错后再发送出去。
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