WO2023214504A1 - Electronic component - Google Patents

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Publication number
WO2023214504A1
WO2023214504A1 PCT/JP2023/015175 JP2023015175W WO2023214504A1 WO 2023214504 A1 WO2023214504 A1 WO 2023214504A1 JP 2023015175 W JP2023015175 W JP 2023015175W WO 2023214504 A1 WO2023214504 A1 WO 2023214504A1
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Prior art keywords
electrode
capacitor
pattern
wiring pattern
electronic component
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PCT/JP2023/015175
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French (fr)
Japanese (ja)
Inventor
真也 立花
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株式会社村田製作所
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Publication of WO2023214504A1 publication Critical patent/WO2023214504A1/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01FMAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F17/00Fixed inductances of the signal type 
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01FMAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F27/00Details of transformers or inductances, in general
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01GCAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00Fixed capacitors; Processes of their manufacture
    • H01G4/30Stacked capacitors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01GCAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00Fixed capacitors; Processes of their manufacture
    • H01G4/40Structural combinations of fixed capacitors with other electric elements, the structure mainly consisting of a capacitor, e.g. RC combinations
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H7/00Multiple-port networks comprising only passive electrical elements as network components
    • H03H7/01Frequency selective two-port networks

Definitions

  • the present disclosure relates to electronic components.
  • An electronic component is known that is an integrated filter device in which an inductor (coil) and a capacitor (capacitor) are provided inside an insulator made by laminating a plurality of insulator layers.
  • Patent Document 1 Japanese Unexamined Patent Publication No. 2013-21449 (Patent Document 1) describes a filter device in which an inductor and a capacitor are built into an insulator on which external electrodes are formed. In this filter device, when the insulator is viewed from above, the inductor is stacked on the capacitor.
  • each electrode When realizing a filter device using small parts, it is necessary to design each electrode to be small while ensuring the desired capacitance in the part constituting the capacitor.
  • Factors that change the capacitance of a capacitor in the process of manufacturing components include the area of the electrodes and the distance between the electrodes. In particular, factors that cause the area of the electrode to vary include misalignment of the electrode and variations in the dimensions of the electrode.
  • miniaturizing electronic components it is desired to have a structure that reduces the variation in capacitance of the capacitor during the manufacturing process while suppressing the area occupied by the capacitor in the electronic component.
  • an object of the present disclosure is to provide an electronic component that can reduce fluctuations in the capacitance of the capacitor during the manufacturing process while suppressing the area occupied by the capacitor in the electronic component.
  • An electronic component includes an insulator having a pair of principal surfaces facing each other and a side surface connecting the principal surfaces, and electrodes formed in each of at least three layers within the insulator.
  • an electrode connected to a wiring pattern protruding from one side of the overlapping electrodes is provided. Therefore, it is possible to reduce the variation in capacitance of the capacitor during the manufacturing process while suppressing the area occupied by the capacitor in the electronic component.
  • FIG. 1 is a perspective view of a filter device according to an embodiment.
  • FIG. 2 is a side view of a filter device according to an embodiment.
  • FIG. 2 is a circuit diagram of a filter device according to an embodiment.
  • FIG. 1 is an exploded plan view showing the configuration of a filter device according to an embodiment.
  • FIG. 2 is a plan view of an electrode that constitutes a capacitor of a filter device according to an embodiment.
  • FIG. 3 is a plan view of an electrode constituting a capacitor for comparison.
  • 7 is a plan view of an electrode constituting a capacitor according to Modification 1.
  • FIG. FIG. 7 is a plan view of an electrode constituting a capacitor according to a second modification.
  • a filter device will be described in detail as an example of an electronic component according to an embodiment with reference to the drawings.
  • the same reference numerals are attached to the same or corresponding parts in the drawings, and the description thereof will not be repeated.
  • the electronic component according to the embodiment is not limited to a filter device.
  • FIG. 1 is a perspective view of a filter device 100 according to an embodiment.
  • FIG. 2 is a side view of the filter device 100 according to the embodiment.
  • the short side direction of the filter device 100 is the X direction
  • the long side direction is the Y direction
  • the height direction is the Z direction.
  • the filter device 100 is a rectangular parallelepiped-shaped chip component in which two inductors and one capacitor are stacked in the Z direction.
  • the filter device 100 includes an insulator 3 in which a plurality of insulating substrates (insulator layers) on which a conductor pattern of an inductor L1, a conductor pattern of an inductor L2, and an electrode pattern of a capacitor C1 are formed are laminated, as shown in FIGS. 1 and 2. Consists of. Note that the stacking direction of the insulating substrates is the Z direction, and the direction of the arrow indicates the upper layer direction.
  • the insulating substrate is made of, for example, an insulating material containing borosilicate glass as a main component, or an insulating resin such as alumina, zirconia, or polyimide resin. Further, in the insulator 3, the interface between the plurality of insulating substrates may not be clearly defined due to processing such as firing or hardening.
  • an external electrode 4a first external electrode
  • an external electrode 4b second external electrode
  • the insulator 3 has a pair of main surfaces facing each other, and the lower main surface in FIG. 1 is the mounting surface, and this surface faces the circuit board.
  • the lower main surface in FIG. 1 is also referred to as a bottom surface
  • the upper main surface in FIG. 1 is also referred to as a top surface.
  • the external electrodes 4a and 4b not only are electrode patterns formed on the bottom surface of the insulator 3, but also electrode patterns are formed on the side surfaces connecting the main surfaces of the insulator 3.
  • the external electrodes 4a and 4b are U-shaped. Therefore, the electrode patterns of the external electrodes 4a provided on the opposing side surfaces of the insulator 3 and the bottom surface of the insulator 3 are at the same potential.
  • the electrode patterns of the external electrodes 4b provided on the opposing side surfaces of the insulator 3 and the bottom surface of the insulator 3 are at the same potential.
  • the external electrode 4a and the external electrode 4b are both provided with electrode patterns on three sides of the insulator 3.
  • the present invention is not limited thereto, and it is sufficient that both the external electrode 4a and the external electrode 4b have an electrode pattern on at least one surface of the insulator 3.
  • the external electrode 4a is provided with an electrode pattern on two sides of the long side (YZ plane) of the insulator 3
  • the external electrode 4b is provided with an electrode pattern on one side of the short side (XZ plane) of the insulator 3.
  • the electrode pattern may be provided only on the surface.
  • the conductor pattern 1a of the inductor L1 and the external electrode 4a are electrically connected on the side surface of the insulator 3 via the wiring pattern 11a, as shown in FIG.
  • the conductor pattern 1c of the inductor L1 and the external electrode 4b are electrically connected on the side surface of the insulator 3 via the wiring pattern 11c (see FIG. 4).
  • the conductor pattern 2d of the inductor L2 and the external electrode 4b are electrically connected on the side surface of the insulator 3 via the wiring pattern 12d, although not shown in FIG. 1 (see FIG. 4).
  • the electrode pattern 5f of the capacitor C1 is electrically connected to the conductor pattern 2e of the inductor L2 via a via conductor 34 (interlayer conductor).
  • the electrode pattern 5h of the capacitor C1 and the external electrode 4a are electrically connected on the side surface of the insulator 3 via the wiring pattern 6h, as shown in FIG.
  • the electrode pattern 5h and the external electrode 4a are also electrically connected on the bottom surface of the insulator 3 via the via conductor 35 and the via conductor 37 (see FIG. 4).
  • the inductor L1 has a plurality of conductor patterns 1a, 1b, and 1c stacked in parallel to the main surface of the insulator 3.
  • the conductor pattern 1a and the conductor pattern 1b are electrically connected by a via conductor 31, and the conductor pattern 1b and the conductor pattern 1c are electrically connected by a via conductor 32.
  • the inductor L2 has a plurality of conductor patterns 2d and 2e stacked below the inductor L1 in parallel to the main surface of the insulator 3.
  • the conductor pattern 2d and the conductor pattern 2e are electrically connected through a via conductor 33.
  • the capacitor C1 has a plurality of electrode patterns 5f, 5g, and 5h stacked on top of each other with an insulating layer interposed therebetween below the inductor L2. That is, the capacitor C1 has a structure in which two capacitor elements constituted by electrode patterns 5f, 5g, and 5h formed in each of three layers are connected in series.
  • the capacitor C1 is provided in a region where there is little overlap with the inductor L1 and the inductor L2 when viewed in plan from the stacking direction. Note that the inductor L1 and the inductor L2 are provided so as to overlap when viewed in plan from the stacking direction. Further, the inductor L2 and the capacitor C1 are connected in series within the insulator 3 to form an LC series circuit.
  • FIG. 3 is a circuit diagram of the filter device 100 according to the embodiment.
  • the filter device 100 includes a first terminal P1, an inductor L1 connected to the first terminal P1, an inductor L2 connected in parallel to the inductor L1 and the first terminal P1, and a capacitor C1 connected in series with the inductor L2. and a second terminal P2 connected to the inductor L1 and the capacitor C1.
  • the first terminal P1 corresponds to the external electrode 4b shown in FIG. 1
  • the second terminal P2 corresponds to the external electrode 4a shown in FIG.
  • the filter device 100 is not limited to the case where the inductor L1 and the inductor L2 are magnetically coupled to each other, and may have a configuration where the inductor L1 and the inductor L2 are not magnetically coupled to each other.
  • the direction in which the magnetic field is generated in the inductor L1 and the direction in which the magnetic field is generated in the inductor L2 are not limited to the opposite directions as shown in FIG. 1, but may be the same direction. good.
  • FIG. 4 is an exploded plan view showing the configuration of the filter device 100 according to the embodiment.
  • each of conductor patterns 1a to 1c, 2d, 2e, wiring patterns 11a, 11c, 12d, 6h, 7h, 8h to 8j, 9i, 9j, and electrode patterns 5f, 5g, 5h are , are formed on the insulating substrates 3a to 3j by a printing method.
  • a conductor pattern 1a that constitutes a part of the inductor L1 is formed on the insulating substrate 3a.
  • the conductor pattern 1a is formed so as to extend approximately 3/4 of the way clockwise from the upper left side in the figure of the insulating substrate 3a.
  • the starting end of the conductor pattern 1a is electrically connected to the external electrode 4a via the wiring pattern 11a.
  • a connecting portion 31a connected to the via conductor 31 is provided near the end of the conductive pattern 1a.
  • a conductor pattern 1b that constitutes a part of the inductor L1 is formed on the insulating substrate 3b.
  • the conductor pattern 1b is formed so as to extend approximately 3/4 of the way clockwise from the lower left side in the figure of the insulating substrate 3b.
  • a connecting portion 31b connected to the via conductor 31 is provided near the starting end of the conductive pattern 1b.
  • a connection portion 32b connected to the via conductor 32 is provided near the end of the conductor pattern 1b.
  • a conductor pattern 1c forming a part of the inductor L1 is formed on the insulating substrate 3c.
  • the conductor pattern 1c is formed so as to extend approximately 3/4 of the way clockwise from the lower right side in the figure of the insulating substrate 3c.
  • a connecting portion 32c that connects to the via conductor 32 is provided near the starting end of the conductor pattern 1c.
  • the terminal end of the conductor pattern 1c is electrically connected to the external electrode 4b via the wiring pattern 11c.
  • the inductor L1 has conductor patterns 1a to 1c connected in series to form a coil with approximately two turns.
  • a conductor pattern 2d forming a part of the inductor L2 is formed on the insulating substrate 3d.
  • the conductor pattern 2d is formed so as to go around about 3/4 clockwise from the upper right side in the figure of the insulating substrate 3d.
  • the starting end of the conductor pattern 2d is electrically connected to the external electrode 4b via the wiring pattern 12d.
  • a connection portion 33d that connects to the via conductor 33 is provided near the end of the conductor pattern 2d.
  • a conductor pattern 2e that constitutes a part of the inductor L2 is formed on the insulating substrate 3e.
  • the conductor pattern 2e is formed so as to extend approximately 3/4 of the way clockwise from the upper left side in the figure of the insulating substrate 3e.
  • a connecting portion 33e that connects to the via conductor 33 is provided near the starting end of the conductor pattern 2e.
  • a connection portion 34e connected to the via conductor 34 is provided near the end of the conductor pattern 2e.
  • the inductor L2 has conductor patterns 2e and 2f connected in series to form a coil with about 1.5 turns.
  • An electrode pattern 5f that constitutes one electrode (first electrode) of the capacitor C1 is formed on the insulating substrate 3f. Since the electrode pattern 5f is provided at a position that does not overlap with the center of the area where the openings of the inductors L1 and L2 overlap when viewed in plan from the stacking direction, it is particularly affected by the magnetic field created by the inductors L1 and L2.
  • the filter device 100 can be realized using small components without interfering with the magnetic field at the center of the opening, which is easily received.
  • the electrode pattern 5f has a connecting portion 34f that connects to the via conductor 34.
  • An electrode pattern 5g that constitutes one electrode (second electrode) of the capacitor C1 is formed on the insulating substrate 3g.
  • the electrode pattern 5g is provided at a position overlapping the electrode pattern 5f formed on the insulating substrate 3f when viewed in plan from the stacking direction.
  • the area of the electrode pattern 5g is larger than the area of the electrode pattern 5f.
  • An electrode pattern 5h that constitutes one electrode (third electrode) of the capacitor C1 is formed on the insulating substrate 3h.
  • the electrode pattern 5h is provided at a position overlapping with the electrode pattern 5g formed on the insulating substrate 3g when viewed in plan from the stacking direction.
  • the area of the electrode pattern 5h is smaller than the area of the electrode pattern 5g.
  • the electrode pattern 5h is electrically connected to the external electrode 4a via a wiring pattern 6h.
  • the wiring pattern 6h is illustrated as two wirings extending from the long side of the electrode pattern 5h to the external electrode 4a, it may be composed of one wiring or three or more wirings. Further, the wiring pattern 6h has a connecting portion 35h that connects to the via conductor 35.
  • the capacitor C1 two capacitor elements constituted by three electrodes are connected in series by arranging the electrode patterns 5f to 5h formed in each of the three layers so as to overlap when viewed from the stacking direction in plan.
  • the structure is as follows.
  • the electrode pattern 5g (the electrode pattern of the second electrode) has a larger electrode area than the electrode pattern 5f (the electrode pattern of the first electrode) and the electrode pattern 5h (the electrode pattern of the third electrode).
  • the wiring pattern 6h connected to the electrode pattern 5h protrudes from one side of the electrode pattern 5g.
  • a wiring pattern 7h and a wiring pattern 8h are further formed on the insulating substrate 3h.
  • the wiring pattern 7h and the wiring pattern 8h partially overlap and are electrically connected.
  • the wiring pattern 8h has a connecting portion 36h that connects to the via conductor 36.
  • the wiring pattern 7h is electrically connected to an external electrode 4b (see FIG. 1) formed on the long side of the insulating substrate 3h. Therefore, the wiring pattern 7h functions as a wiring that electrically connects the external electrode 4b and the wiring pattern 8h.
  • a wiring pattern 8i and a wiring pattern 9i are formed on the insulating substrate 3i.
  • the wiring pattern 8i is provided at a position overlapping the wiring pattern 8h formed on the insulating substrate 3h when viewed in plan from the stacking direction.
  • the wiring pattern 9i is provided at a position overlapping the wiring pattern 6h formed on the insulating substrate 3h when viewed in plan from the stacking direction.
  • the wiring pattern 8i has a connecting portion 36i that connects to the via conductor 36.
  • the wiring pattern 9i has a connecting portion 35i that connects to the via conductor 35 and a connecting portion 37i that connects to the via conductor 37.
  • a wiring pattern 8j and a wiring pattern 9j are formed on the insulating substrate 3j.
  • the wiring pattern 8j is provided at a position overlapping the wiring pattern 8i formed on the insulating substrate 3i when viewed in plan from the stacking direction.
  • the wiring pattern 9j is provided at a position overlapping the wiring pattern 9i formed on the insulating substrate 3i when viewed in plan from the stacking direction.
  • the wiring pattern 8j has a connecting portion 36j that connects to the via conductor 36.
  • the wiring pattern 9j has a connecting portion 37j that connects to the via conductor 37.
  • a connecting portion 37k that connects the external electrode 4a and the via conductor 37, and a connecting portion 36k that connects the external electrode 4b and the via conductor 36 are formed on the insulating substrate 3k.
  • the wiring pattern 6h is not only electrically connected to the side surface of the external electrode 4a, but also electrically connected to the bottom surface of the external electrode 4a via the via conductor 35 and the via conductor 37.
  • the wiring inside the insulator 3 Electrical connection can be maintained through the path passing through pattern 6h, via conductor 35, and via conductor 37.
  • the wiring patterns 9i, 9j and the via conductors 35, 37 may not be provided.
  • the wiring pattern 7h is not only electrically connected to the side surface of the external electrode 4b, but also electrically connected to the bottom surface of the external electrode 4b via the wiring pattern 8h and the via conductor 36.
  • the wiring inside the insulator 3 Electrical connection can be maintained through the paths passing through patterns 7h, 8h and via conductor 36.
  • the wiring patterns 7h, 8h to 8j and the via conductor 36 may not be provided.
  • the filter device 100 employs a capacitor C1 having a structure in which two capacitor elements constituted by three electrodes (electrode patterns 5f to 5h) are connected in series. Furthermore, the capacitor C1 is configured such that at least a portion of the wiring pattern 6h connected to the electrode pattern 5h protrudes from one side of the electrode pattern 5g. The configuration of this capacitor C1 will be explained in more detail.
  • FIG. 5 is a plan view of the electrodes forming the capacitor C1 of the filter device 100 according to the embodiment.
  • FIG. 6 is a plan view of an electrode forming a capacitor to be compared.
  • the capacitor C1 is constructed by arranging the electrode patterns 5f to 5h shown in FIG. This structure has a structure in which a capacitor element C1b including a part of the pattern 6h) and a capacitor element C1b are connected in series.
  • electrode patterns 5f and 5h with small areas are arranged above and below the electrode pattern 5g with a large area in the stacking direction.
  • the capacitance of a capacitor is determined by the overlapping area of opposing electrodes
  • the capacitance is determined by the area of the electrode pattern 5f.
  • the electrode pattern 5h (including a part of the wiring pattern 6h) Capacity is determined by area.
  • the capacitance of the capacitor C1 does not change.
  • the electrode patterns 5f and 5h have a large area like the electrode patterns 51f and 51h due to dimensional variations due to the manufacturing process, the capacitance of the capacitor C1 will fluctuate.
  • a capacitor Ca made up of an electrode pattern 5a and an electrode pattern 5b is made up of two layers of electrodes with the same interlayer distance as the electrode pattern 5f and the electrode pattern 5g shown in FIG. Therefore, in order to have the same capacity as the capacitor C1 shown in FIG. 5, it is necessary to reduce the area of each electrode of the capacitor Ca. Since dimensional variations due to the manufacturing process are constant regardless of the electrode size, when the electrode pattern 5a changes to the electrode pattern 51a, the capacitance of the capacitor Ca changes. In the capacitor Ca, since the area of the electrode pattern 5a, which is smaller than the area of the electrode patterns 5f and 5h shown in FIG. 5, varies, the rate of change in the capacitance of the capacitor Ca varies greatly. In other words, in this embodiment, electrode patterns 5f and 5h having a larger area than electrode pattern 5a shown in FIG. The fluctuation rate of the capacitance of the capacitor C1 is reduced compared to the above.
  • the capacitor C1 by configuring the capacitor C1 by arranging the electrode patterns 5f and 5h, which have smaller areas than the electrode pattern 5g, above and below in the stacking direction, the positions of the electrode patterns 5f and 5h with respect to the electrode pattern 5g can be adjusted due to the manufacturing process. Even if it deviates, the capacitance of the capacitor C1 does not change as long as it overlaps with the electrode pattern 5g.
  • a wiring pattern 6h is connected to the electrode pattern 5h. Therefore, the portion where the wiring pattern 6h and the electrode pattern 5g overlap when viewed in plan from the stacking direction is also included in the capacitance of the capacitor C1.
  • the wiring pattern 6h changes to a wiring pattern 61h as shown in FIG. 5.
  • the area of the wiring pattern 6h that overlaps with the electrode pattern 5g changes only in the direction of the wiring width of the wiring pattern 6h
  • the area of the wiring pattern 6h that overlaps with the electrode pattern 5g changes only in the direction of the wiring width of the wiring pattern 6h
  • the area of the wiring pattern 6h that overlaps with the electrode pattern 5g changes only in the direction of the wiring width of the wiring pattern 6h.
  • Equation 1 the variation in the capacitance of the capacitor C1 can be expressed as shown in Equation 1.
  • the capacitance of the capacitor C1 is C
  • the relative permittivity is ⁇ r
  • the area of the electrode patterns is S
  • the distance between the electrode patterns is D.
  • Equation 1 in order to suppress the variation in the capacitance C of the capacitor C1, at least one of the variation in the relative permittivity ⁇ r , the variation in the area S of the electrode patterns, and the variation in the distance D between the electrode patterns is suppressed. need to be reduced.
  • fluctuations in the capacitance C of the capacitor C1 are suppressed by focusing on fluctuations in the area S of the electrode pattern.
  • the area of the electrode pattern 5f is 150 ⁇ m x 300 ⁇ m
  • the area of the electrode pattern 5g is 200 ⁇ m x 350 ⁇ m
  • the area of the electrode pattern 5h is 150 ⁇ m x 300 ⁇ m
  • the area of the wiring pattern 6h extending from the electrode pattern 5h. is 100 ⁇ m x 100 ⁇ m x 2 pieces.
  • the effective area of the electrode as a capacitor is the area of the smaller electrode pattern 5f (150 ⁇ m ⁇ 300 ⁇ m).
  • the effective area of the electrode as a capacitor is the area of the smaller electrode pattern 5h (150 ⁇ m ⁇ 300 ⁇ m). Further, in the capacitor (a part of the capacitor element C1b) constituted by the wiring pattern 6h extending from the electrode pattern 5h and the electrode pattern 5g, the effective area of the electrode as a capacitor is 25 ⁇ m ⁇ 100 ⁇ m ⁇ 2.
  • a capacitor element C1a composed of an electrode pattern 5f and an electrode pattern 5g
  • a capacitor element C1b composed of an electrode pattern 5g and an electrode pattern 5h (including a part of a wiring pattern 6h) are connected in series. It has a similar structure. Therefore, the capacitance of the capacitor C1 can be determined by the product of the sum of the capacitance of the capacitor element C1a and the capacitance of the capacitor element C1b.
  • the area of the electrode that is effective as a capacitor in capacitor C1 is the area of the electrode that is effective as capacitor element C1a (the area of electrode pattern 5f), and the area of the electrode that is effective as capacitor element C1b (the area of electrode pattern 5h and the wiring pattern). (area including part of 6h). Therefore, in the specific example described above, the area of the electrode that is effective as a capacitor in the capacitor C1 can be determined to be approximately 23684 ⁇ m 2 .
  • the area of the electrode pattern 5c is 150 ⁇ m x 315.8 ⁇ m
  • the area of the electrode pattern 5d is 200 ⁇ m x 365 ⁇ m. .8 ⁇ m
  • the area of the electrode pattern 5e needs to be 150 ⁇ m ⁇ 315.8 ⁇ m.
  • the amount of variation ⁇ S in the electrode area of capacitor C1 is , approximately 35355 ⁇ m2 .
  • the amount of variation ⁇ S in the area of the electrode in the capacitor Cb shown in FIG. 6(b) is approximately 36471 ⁇ m 2 .
  • the capacitor C1 was able to suppress the variation ⁇ S in the electrode area by about 3% compared to the capacitor Cb. This is because, in the capacitor C1, variations in the area of the wiring pattern 6h in the length direction of the wiring pattern 6h can be ignored. Therefore, since the capacitor C1 has the wiring pattern 6h protruding from the side of the overlapping electrode pattern 5g when viewed in plan from the stacking direction, variations in the capacitance of the capacitor C1 can be reduced in the manufacturing process.
  • FIG. 7 is a plan view of the electrodes forming the capacitor C1 according to the first modification.
  • FIG. 7A shows an electrode in which a wiring pattern 6ha protrudes from the center of the long side of the electrode pattern 5h.
  • the wiring pattern 61ha indicated by a broken line shows the shape of the wiring pattern 6ha after dimensional variations have occurred.
  • the electrode pattern 5h has a rectangular shape when viewed in plan from the stacking direction, and the wiring width of the wiring pattern 6ha is shorter than the length of one side of the electrode pattern 5h. Therefore, when the combined shape of the electrode pattern 5h and the wiring pattern 6ha shown in FIG.
  • connection position of the upper and lower wiring patterns 6ha with respect to the electrode pattern 5h does not have to be at the center, and furthermore, the connection positions may be at different positions on the upper and lower sides.
  • the wiring width is shorter than the length of one side of the electrode pattern 5h, but in the wiring pattern 6hb shown in FIG. 7(b), the wiring width is shorter than the length of one side of the electrode pattern 5h. It is the same as the length.
  • FIG. 7B shows an electrode in which a wiring pattern 6hb protrudes from the long side of the electrode pattern 5h. Note that the wiring pattern 61hb indicated by a broken line shows the shape of the wiring pattern 6hb after dimensional variations have occurred. When the combined shape of the electrode pattern 5h and the wiring pattern 6hb is viewed in plan from the stacking direction, it has a rectangular shape. In the case of FIG.
  • the boundary between the electrode pattern 5h and the wiring pattern 6hb is unclear, so when viewed from the stacking direction, the electrode pattern 5h and the wiring It is sufficient that the integrated pattern 6hb protrudes from any side of the electrode pattern 5g.
  • the wiring pattern 6ha is connected to each of the two long sides (two opposing sides) of the electrode pattern 5h, but the wiring pattern 6ha is connected to one of the long sides. But that's fine.
  • the wiring pattern 6hb is connected to each of the two long sides (two opposing sides) of the electrode pattern 5h, but the wiring pattern 6hb is connected to one of the long sides. It may also be a configuration in which
  • the wiring pattern is not limited to the configuration in which it is connected to the long side of the electrode pattern 5h, but may be configured to be connected to the short side of the electrode pattern 5h.
  • FIG. 7C shows an electrode in which a wiring pattern 6hc protrudes from the short side of the electrode pattern 5h.
  • the wiring pattern 61hc indicated by a broken line shows the shape of the wiring pattern 6hc after dimensional variations have occurred.
  • the combined shape of the electrode pattern 5h and the wiring pattern 6hc is viewed in plan from the stacking direction, it has a T-shape.
  • FIG. 7C shows an electrode in which a wiring pattern 6hc protrudes from the short side of the electrode pattern 5h.
  • the wiring pattern 61hc indicated by a broken line shows the shape of the wiring pattern 6hc after dimensional variations have occurred.
  • the wiring pattern 6hc is connected to one short side of the electrode pattern 5h, but a configuration may be adopted in which the wiring pattern 6hc is connected to two short sides. As shown in FIG. 7C, the connection position of the wiring pattern 6hc with respect to the electrode pattern 5h does not have to be in the center, but may be shifted to either the upper or lower side.
  • the capacitor C1 has a structure in which two capacitor elements constituted by the electrode pattern 5f, the electrode pattern 5g, and the electrode pattern 5h formed in each of three layers are connected in series.
  • a structure may be employed in which a plurality of capacitor elements each formed by an electrode pattern are connected in series.
  • FIG. 8 is a plan view of an electrode configuring a capacitor C1A according to modification 2. As shown in FIG. 8, the capacitor C1A has a structure in which four capacitor elements each formed by electrode patterns 5i to 5m formed in five layers are connected in series.
  • the electrode pattern 5i has a rectangular shape, and the wiring pattern 6i is connected to two short sides (two opposing sides). Note that the electrode pattern 51i indicated by a broken line indicates the shape of the electrode pattern 5i after dimensional variations have occurred. The wiring pattern 61i indicated by a broken line shows the shape of the wiring pattern 6i after dimensional variations have occurred. The electrode pattern 5j has a rectangular shape with a larger area than the electrode pattern 5i. Note that the electrode pattern 51j indicated by a broken line indicates the shape of the electrode pattern 5j after dimensional variations have occurred.
  • the electrode pattern 5k has a rectangular shape with a smaller area than the electrode pattern 5j. Note that the electrode pattern 51k indicated by a broken line indicates the shape of the electrode pattern 5k after dimensional variations have occurred.
  • the structure of the electrode patterns 5j to 5k is such that the electrode pattern 5j, which has a large area, is sandwiched between the electrode pattern 5i, which has a small area, and the electrode pattern 5k, above and below in the stacking direction.
  • the electrode pattern 5l has a rectangular shape with a larger area than the electrode pattern 5k. Note that the electrode pattern 51l indicated by a broken line shows the shape of the electrode pattern 5l after dimensional variations have occurred.
  • the electrode pattern 5m has a rectangular shape, and the wiring pattern 6m is connected to two long sides (two opposing sides). Note that the electrode pattern 51m indicated by a broken line shows the shape of the electrode pattern 5m after dimensional variations have occurred. The wiring pattern 61m indicated by a broken line shows the shape of the wiring pattern 6m after dimensional variations have occurred.
  • the structure of the electrode patterns 5k to 5m is such that the electrode pattern 5l, which has a large area, is sandwiched between the electrode pattern 5k, which has a small area, and the electrode pattern 5m, above and below in the stacking direction.
  • the capacitor C1A can ignore the variation in the area of the wiring pattern 6i in the length direction of the wiring pattern 6i, and by connecting the wiring pattern 6m to the electrode pattern 5m, the wiring pattern 6i can be ignored. Since variations in the area of the wiring pattern 6m in the length direction of the pattern 6m can be ignored, variations in capacitance can be suppressed.
  • Capacitor C1A has two structures in which an electrode pattern with a large area is sandwiched between two electrode patterns with a small area above and below in the stacking direction, and a wiring pattern is connected to one of the electrode patterns with a small area in each structure. Any configuration is fine. It is sufficient that at least a portion of the wiring pattern protrudes from one side of the overlapping electrodes when viewed in plan from the stacking direction.
  • the electrode patterns 5i, 5k, and 5m provided above and below in the stacking direction of the large-area electrode patterns 5j, 5l may all have the same area or different areas. That is, the areas of the electrode patterns 5i, 5k, and 5m need only be smaller than the areas of the electrode patterns 5j, 5l.
  • the electrode patterns 5f and 5h provided above and below the electrode pattern 5g having a large area in the stacking direction may have the same area or different areas. In other words, the areas of the electrode patterns 5f and 5h need only be smaller than the area of the electrode pattern 5g.
  • the capacitor C1 shown in FIG. 1 has been described with a configuration in which the wiring pattern 6h is electrically connected to the external electrode 4a, it may be configured such that the wiring pattern 6h is not electrically connected to the external electrode 4a. Similarly, the wiring patterns 6i and 6m of the capacitor C1A may also be configured to be electrically connected to the external electrodes or not connected.
  • capacitor C1 and the capacitor C1A have been described as an example employed in a filter device, but if the elements constituted by electrodes formed in at least three layers are connected in series to constitute a capacitor, then The structure of capacitor C1 and capacitor C1A may be adopted for any component.
  • the filter device 100 includes an insulator 3 having a pair of main surfaces facing each other and a side surface connecting the main surfaces, and at least three layers formed in each of the insulator 3. and a capacitor C1 in which elements constituted by electrodes are connected in series.
  • the capacitor C1 is arranged at a position where the electrode patterns 5f to 5h formed in each layer overlap each other when viewed in plan from the stacking direction, and the electrode pattern 5h formed in at least one layer has at least one wiring.
  • Pattern 6h is electrically connected. At least a portion of the wiring pattern 6h protrudes from one side of the overlapping electrode pattern 5g when viewed in plan from the stacking direction.
  • the filter device 100 has a capacitor C1 in which elements constituted by the electrode patterns 5f to 5h formed in each of at least three layers are connected in series, and the capacitor C1 protrudes from one side of the overlapping electrode pattern 5g. Since the electrode pattern 5h is connected to the wiring pattern 6h, it is possible to suppress the ratio of the area occupied by the capacitor C1 in the filter device 100, and reduce fluctuations in the capacitance of the capacitor C1 during the manufacturing process.
  • the electronic component according to the present disclosure includes an insulator having a pair of principal surfaces facing each other and a side surface connecting the principal surfaces, and electrodes formed in each of at least three layers within the insulator. a capacitor in which elements are connected in series, the capacitor is arranged in a position where electrodes formed in each layer overlap each other when viewed in plan from the stacking direction, and the capacitor has an electrode formed in at least one layer; In this case, at least one wiring pattern is electrically connected, and at least a part of the wiring pattern protrudes from one side of the overlapping electrodes when viewed in plan from the stacking direction.
  • the electronic component according to the present disclosure is a capacitor in which elements constituted by electrodes formed in at least three layers are connected in series, and connected to a wiring pattern protruding from one side of the overlapping electrodes. Since the capacitor has an electrode, it is possible to suppress the proportion of the area occupied by the capacitor in the electronic component and reduce fluctuations in capacitance of the capacitor during the manufacturing process.
  • the capacitor is composed of three layers, including a first electrode formed in the first layer and a second electrode formed in the second layer, when viewed in plan from the stacking direction. a second electrode that overlaps with the first electrode; and a third electrode that is formed in a third layer and overlaps with the second electrode when viewed in plan from the stacking direction, and is connected to the third electrode. At least a portion of the pattern protrudes from one side of the second electrode.
  • the second electrode has a larger electrode area than the first and third electrodes.
  • the capacitance of the capacitor is determined by the areas of the first electrode and the third electrode.
  • the wiring pattern includes one side of the electrodes that overlap when viewed from the stacking direction, and a portion of the wiring pattern from the side opposite to the one side. It's sticking out. As a result, variations in the area of the wiring pattern in the protruding direction do not contribute to variations in the capacitance of the capacitor.
  • the electronic component according to any one of (1) to (5) further includes an inductor formed in a different layer from the capacitor, and the inductor is connected in series with the capacitor. Thereby, the electronic component can constitute a filter device with the inductor and the capacitor.
  • the electrode of the capacitor has a rectangular shape when viewed from the stacking direction, and the wiring width of the wiring pattern is shorter than the length of one side of the electrode. This increases the degree of freedom in the position where the wiring pattern is connected to the electrode.
  • the wiring width of the wiring pattern is the same as the length of one side of the connected electrode. As a result, the shape of the electrode connected to the wiring pattern becomes rectangular.
  • the inductor includes a first inductor and a second inductor connected in parallel to the first inductor.
  • the electronic component can constitute a filter device with a plurality of inductors and a capacitor.
  • the second inductor is magnetically coupled to the first inductor.
  • the electronic component can utilize mutual inductance between the first inductor and the second inductor.

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Abstract

The present disclosure provides an electronic component in which variations of the capacitance of a capacitor in a manufacturing process are reduced while suppressing the proportion of the area occupied by the capacitor in the electronic component. A filter device (100) as an example of the electronic component according to the present disclosure comprises: an insulator (3) that has a pair of main surfaces opposing each other and a side surface that connects the main surfaces; and a capacitor (C1) in which elements constituted by electrodes respectively formed in at least three layers in the insulator (3) are connected in series. In the capacitor (C1), electrode patterns (5f to 5h) formed in the respective layers are disposed in positions overlapping each other when viewed in plan from a stacking direction, and at least one wiring pattern (6h) is electrically connected to the electrode pattern (5h) formed in at least one layer. At least a portion of the wiring pattern (6h) extends beyond a side of the electrode pattern (5g) that overlaps thereon when viewed in plan from the stacking direction.

Description

電子部品electronic components
 本開示は、電子部品に関する。 The present disclosure relates to electronic components.
 複数の絶縁体層を積層した絶縁体の内部にインダクタ(コイル)とキャパシタ(コンデンサ)とを設け、一体化したフィルタ装置である電子部品が知られている。フィルタ装置の一例として、特開2013-21449号公報(特許文献1)には、外部電極を形成した絶縁体に、インダクタ、およびキャパシタを内蔵するフィルタ装置が記載されている。当該フィルタ装置では、絶縁体を天面側から平面視した場合に、キャパシタの上にインダクタが積層されている。 An electronic component is known that is an integrated filter device in which an inductor (coil) and a capacitor (capacitor) are provided inside an insulator made by laminating a plurality of insulator layers. As an example of a filter device, Japanese Unexamined Patent Publication No. 2013-21449 (Patent Document 1) describes a filter device in which an inductor and a capacitor are built into an insulator on which external electrodes are formed. In this filter device, when the insulator is viewed from above, the inductor is stacked on the capacitor.
特開2013-21449号公報Japanese Patent Application Publication No. 2013-21449
 フィルタ装置を小型部品で実現する場合、キャパシタを構成する部分では、所望の容量を確保しつつ、各電極を小さく設計する必要がある。部品を製造するプロセスにおいてキャパシタの容量が変動する要素として、電極の面積と、電極間距離とがある。特に、電極の面積が変動する要素として、電極の位置ズレや電極の寸法ばらつきなどがある。電子部品を小型化する場合に、当該電子部品でのキャパシタが占める面積の割合を抑えつつ、製造するプロセスにおいてキャパシタの容量の変動を小さくする構造が望まれている。 When realizing a filter device using small parts, it is necessary to design each electrode to be small while ensuring the desired capacitance in the part constituting the capacitor. Factors that change the capacitance of a capacitor in the process of manufacturing components include the area of the electrodes and the distance between the electrodes. In particular, factors that cause the area of the electrode to vary include misalignment of the electrode and variations in the dimensions of the electrode. When miniaturizing electronic components, it is desired to have a structure that reduces the variation in capacitance of the capacitor during the manufacturing process while suppressing the area occupied by the capacitor in the electronic component.
 そこで、本開示の目的は、電子部品でのキャパシタが占める面積の割合を抑えつつ、製造するプロセスにおいてキャパシタの容量の変動を低減できる電子部品を提供することである。 Therefore, an object of the present disclosure is to provide an electronic component that can reduce fluctuations in the capacitance of the capacitor during the manufacturing process while suppressing the area occupied by the capacitor in the electronic component.
 本開示の一形態に係る電子部品は、互いに対向する1対の主面と主面間を結ぶ側面とを有する絶縁体と、絶縁体内において少なくとも3層の各々に形成される電極により構成される素子が直列に接続されたキャパシタと、を備える。キャパシタは、各々の層に形成される電極が積層方向から平面視した場合に互いに重なる位置に配置され、少なくとも1つの層に形成される電極には、少なくとも1つの配線パターンが電気的に接続される。配線パターンの少なくとも一部が、積層方向から平面視した場合に重なる電極の一辺からはみ出している。 An electronic component according to an embodiment of the present disclosure includes an insulator having a pair of principal surfaces facing each other and a side surface connecting the principal surfaces, and electrodes formed in each of at least three layers within the insulator. A capacitor in which elements are connected in series. The capacitor is arranged such that electrodes formed on each layer overlap each other when viewed in plan from the stacking direction, and at least one wiring pattern is electrically connected to the electrode formed on at least one layer. Ru. At least a portion of the wiring pattern protrudes from one side of the overlapping electrodes when viewed in plan from the stacking direction.
 本開示の一形態によれば、少なくとも3層の各々に形成される電極により構成される素子が直列に接続されたキャパシタで、重なる電極の一辺からはみ出している配線パターンと接続している電極を有しているので、電子部品でのキャパシタが占める面積の割合を抑えつつ、製造するプロセスにおいてキャパシタの容量の変動を低減できる。 According to one embodiment of the present disclosure, in a capacitor in which elements constituted by electrodes formed in at least three layers are connected in series, an electrode connected to a wiring pattern protruding from one side of the overlapping electrodes is provided. Therefore, it is possible to reduce the variation in capacitance of the capacitor during the manufacturing process while suppressing the area occupied by the capacitor in the electronic component.
実施の形態に係るフィルタ装置の斜視図である。FIG. 1 is a perspective view of a filter device according to an embodiment. 実施の形態に係るフィルタ装置の側面図である。FIG. 2 is a side view of a filter device according to an embodiment. 実施の形態に係るフィルタ装置の回路図である。FIG. 2 is a circuit diagram of a filter device according to an embodiment. 実施の形態に係るフィルタ装置の構成を示す分解平面図である。FIG. 1 is an exploded plan view showing the configuration of a filter device according to an embodiment. 実施の形態に係るフィルタ装置のキャパシタを構成する電極の平面図である。FIG. 2 is a plan view of an electrode that constitutes a capacitor of a filter device according to an embodiment. 比較対象のキャパシタを構成する電極の平面図である。FIG. 3 is a plan view of an electrode constituting a capacitor for comparison. 変形例1に係るキャパシタを構成する電極の平面図である。7 is a plan view of an electrode constituting a capacitor according to Modification 1. FIG. 変形例2に係るキャパシタを構成する電極の平面図である。FIG. 7 is a plan view of an electrode constituting a capacitor according to a second modification.
 以下に、実施の形態に係る電子部品の一例としてフィルタ装置について、図面を参照しながら詳細に説明する。なお、図中同一または相当部分には同一符号を付してその説明は繰り返さない。また、実施の形態に係る電子部品は、フィルタ装置に限定されない。 Below, a filter device will be described in detail as an example of an electronic component according to an embodiment with reference to the drawings. In addition, the same reference numerals are attached to the same or corresponding parts in the drawings, and the description thereof will not be repeated. Further, the electronic component according to the embodiment is not limited to a filter device.
 (実施の形態)
 [フィルタ装置の構造]
 まず、実施の形態に係るフィルタ装置について図面を参照しながら説明する。図1は、実施の形態に係るフィルタ装置100の斜視図である。図2は、実施の形態に係るフィルタ装置100の側面図である。ここで、図1および図2では、フィルタ装置100の短辺方向をX方向、長辺方向をY方向、高さ方向をZ方向としている。
(Embodiment)
[Structure of filter device]
First, a filter device according to an embodiment will be described with reference to the drawings. FIG. 1 is a perspective view of a filter device 100 according to an embodiment. FIG. 2 is a side view of the filter device 100 according to the embodiment. Here, in FIGS. 1 and 2, the short side direction of the filter device 100 is the X direction, the long side direction is the Y direction, and the height direction is the Z direction.
 フィルタ装置100は、2つのインダクタと1つのキャパシタとをZ方向に積層した直方体状のチップ部品である。フィルタ装置100は、図1および図2に示すようにインダクタL1の導体パターン、インダクタL2の導体パターンおよびキャパシタC1の電極パターンを形成した絶縁基板(絶縁体層)が複数枚積層された絶縁体3で構成される。なお、絶縁基板の積層方向はZ方向で、矢印の向きが上層方向を示している。また、絶縁基板は、例えば、硼珪酸ガラスを主成分とする絶縁材料や、アルミナ、ジルコニア、ポリイミド樹脂等の絶縁樹脂などの材料からなる。さらに、絶縁体3は、焼成や硬化等の処理によって、複数の絶縁基板の界面が明確となっていない場合がある。 The filter device 100 is a rectangular parallelepiped-shaped chip component in which two inductors and one capacitor are stacked in the Z direction. The filter device 100 includes an insulator 3 in which a plurality of insulating substrates (insulator layers) on which a conductor pattern of an inductor L1, a conductor pattern of an inductor L2, and an electrode pattern of a capacitor C1 are formed are laminated, as shown in FIGS. 1 and 2. Consists of. Note that the stacking direction of the insulating substrates is the Z direction, and the direction of the arrow indicates the upper layer direction. Further, the insulating substrate is made of, for example, an insulating material containing borosilicate glass as a main component, or an insulating resin such as alumina, zirconia, or polyimide resin. Further, in the insulator 3, the interface between the plurality of insulating substrates may not be clearly defined due to processing such as firing or hardening.
 また、フィルタ装置100は、Y方向に2箇所、図1に示すような外部電極4a(第1外部電極)、および外部電極4b(第2外部電極)が絶縁体3に形成されている。なお、絶縁体3は、互いに対向する1対の主面を有しており、図1の下側の主面が実装面であり、この面が回路基板に対向する。本実施の形態では、図1の下側の主面を底面、図1の上側の主面を天面ともいう。 Further, in the filter device 100, an external electrode 4a (first external electrode) and an external electrode 4b (second external electrode) as shown in FIG. 1 are formed on the insulator 3 at two locations in the Y direction. Note that the insulator 3 has a pair of main surfaces facing each other, and the lower main surface in FIG. 1 is the mounting surface, and this surface faces the circuit board. In this embodiment, the lower main surface in FIG. 1 is also referred to as a bottom surface, and the upper main surface in FIG. 1 is also referred to as a top surface.
 外部電極4aおよび外部電極4bは、絶縁体3の底面に電極パターンが形成されているだけでなく、絶縁体3の主面間を結ぶ側面にも電極パターンが形成されている。絶縁体3を短辺側の側面(XZ面)から見た場合、外部電極4aおよび外部電極4bはU字形状をしている。そのため、絶縁体3の対向する側面および絶縁体3の底面にそれぞれに設けられる外部電極4aの電極パターンは同電位である。同様に、絶縁体3の対向する側面および絶縁体3の底面にそれぞれに設けられる外部電極4bの電極パターンは同電位である。 For the external electrodes 4a and 4b, not only are electrode patterns formed on the bottom surface of the insulator 3, but also electrode patterns are formed on the side surfaces connecting the main surfaces of the insulator 3. When the insulator 3 is viewed from the short side (XZ plane), the external electrodes 4a and 4b are U-shaped. Therefore, the electrode patterns of the external electrodes 4a provided on the opposing side surfaces of the insulator 3 and the bottom surface of the insulator 3 are at the same potential. Similarly, the electrode patterns of the external electrodes 4b provided on the opposing side surfaces of the insulator 3 and the bottom surface of the insulator 3 are at the same potential.
 外部電極4aおよび外部電極4bは、ともに絶縁体3の3面に電極パターンが設けられていると説明した。しかし、これに限られず、外部電極4aおよび外部電極4bは、ともに絶縁体3の少なくとも1面に電極パターンが設けられていればよい。例えば、外部電極4aは、絶縁体3の長辺側の側面(YZ面)の2面に電極パターンが設けられ、外部電極4bは、絶縁体3の短辺側の側面(XZ面)の1面のみに電極パターンが設けられてもよい。 It has been explained that the external electrode 4a and the external electrode 4b are both provided with electrode patterns on three sides of the insulator 3. However, the present invention is not limited thereto, and it is sufficient that both the external electrode 4a and the external electrode 4b have an electrode pattern on at least one surface of the insulator 3. For example, the external electrode 4a is provided with an electrode pattern on two sides of the long side (YZ plane) of the insulator 3, and the external electrode 4b is provided with an electrode pattern on one side of the short side (XZ plane) of the insulator 3. The electrode pattern may be provided only on the surface.
 インダクタL1の導体パターン1aと外部電極4aとは、図1に示すように配線パターン11aを介して絶縁体3の側面で電気的に接続されている。インダクタL1の導体パターン1cと外部電極4bとは、図1では図示されていないが配線パターン11cを介して絶縁体3の側面で電気的に接続されている(図4参照)。また、インダクタL2の導体パターン2dと外部電極4bとは、図1では図示されていないが配線パターン12dを介して絶縁体3の側面で電気的に接続されている(図4参照)。 The conductor pattern 1a of the inductor L1 and the external electrode 4a are electrically connected on the side surface of the insulator 3 via the wiring pattern 11a, as shown in FIG. Although not shown in FIG. 1, the conductor pattern 1c of the inductor L1 and the external electrode 4b are electrically connected on the side surface of the insulator 3 via the wiring pattern 11c (see FIG. 4). Further, the conductor pattern 2d of the inductor L2 and the external electrode 4b are electrically connected on the side surface of the insulator 3 via the wiring pattern 12d, although not shown in FIG. 1 (see FIG. 4).
 キャパシタC1の電極パターン5fは、図1に示すようにインダクタL2の導体パターン2eとビア導体34(層間導体)で電気的に接続されている。キャパシタC1の電極パターン5hと外部電極4aとは、図1に示すように配線パターン6hを介して絶縁体3の側面で電気的に接続されている。電極パターン5hと外部電極4aとは、ビア導体35およびビア導体37を介して絶縁体3の底面でも電気的に接続されている(図4参照)。 As shown in FIG. 1, the electrode pattern 5f of the capacitor C1 is electrically connected to the conductor pattern 2e of the inductor L2 via a via conductor 34 (interlayer conductor). The electrode pattern 5h of the capacitor C1 and the external electrode 4a are electrically connected on the side surface of the insulator 3 via the wiring pattern 6h, as shown in FIG. The electrode pattern 5h and the external electrode 4a are also electrically connected on the bottom surface of the insulator 3 via the via conductor 35 and the via conductor 37 (see FIG. 4).
 インダクタL1は、図2に示すように、絶縁体3の主面に対して平行に、複数の導体パターン1a,1b,1cが積み重ねられている。導体パターン1aと導体パターン1bとはビア導体31で電気的に接続され、導体パターン1bと導体パターン1cとはビア導体32で電気的に接続されている。インダクタL2は、図2に示すように、インダクタL1の下層に絶縁体3の主面に対して平行に、複数の導体パターン2d,2eが積み重ねられている。導体パターン2dと導体パターン2eとはビア導体33で電気的に接続されている。 As shown in FIG. 2, the inductor L1 has a plurality of conductor patterns 1a, 1b, and 1c stacked in parallel to the main surface of the insulator 3. The conductor pattern 1a and the conductor pattern 1b are electrically connected by a via conductor 31, and the conductor pattern 1b and the conductor pattern 1c are electrically connected by a via conductor 32. As shown in FIG. 2, the inductor L2 has a plurality of conductor patterns 2d and 2e stacked below the inductor L1 in parallel to the main surface of the insulator 3. The conductor pattern 2d and the conductor pattern 2e are electrically connected through a via conductor 33.
 キャパシタC1は、図2に示すように、インダクタL2の下層に複数の電極パターン5f,5g,5hが絶縁層を介して積み重ねられている。つまり、キャパシタC1は、3層の各々に形成される電極パターン5f,5g,5hにより構成される2つのコンデンサ素子が直列に接続された構造である。キャパシタC1は、積層方向から平面視した場合、インダクタL1およびインダクタL2と重なりの少ない領域に設けられている。なお、インダクタL1とインダクタL2は、積層方向から平面視した場合、重なるように設けられている。また、インダクタL2とキャパシタC1とは、絶縁体3内で直列に接続されLC直列回路を構成している。 As shown in FIG. 2, the capacitor C1 has a plurality of electrode patterns 5f, 5g, and 5h stacked on top of each other with an insulating layer interposed therebetween below the inductor L2. That is, the capacitor C1 has a structure in which two capacitor elements constituted by electrode patterns 5f, 5g, and 5h formed in each of three layers are connected in series. The capacitor C1 is provided in a region where there is little overlap with the inductor L1 and the inductor L2 when viewed in plan from the stacking direction. Note that the inductor L1 and the inductor L2 are provided so as to overlap when viewed in plan from the stacking direction. Further, the inductor L2 and the capacitor C1 are connected in series within the insulator 3 to form an LC series circuit.
 図3は、実施の形態に係るフィルタ装置100の回路図である。フィルタ装置100は、第1端子P1と、第1端子P1と接続されるインダクタL1と、インダクタL1と並列に第1端子P1と接続されるインダクタL2と、インダクタL2と直列に接続されるキャパシタC1と、インダクタL1およびキャパシタC1と接続される第2端子P2と、を含む。なお、第1端子P1は、図1に示す外部電極4bに対応し、第2端子P2は、図1に示す外部電極4aに対応する。 FIG. 3 is a circuit diagram of the filter device 100 according to the embodiment. The filter device 100 includes a first terminal P1, an inductor L1 connected to the first terminal P1, an inductor L2 connected in parallel to the inductor L1 and the first terminal P1, and a capacitor C1 connected in series with the inductor L2. and a second terminal P2 connected to the inductor L1 and the capacitor C1. Note that the first terminal P1 corresponds to the external electrode 4b shown in FIG. 1, and the second terminal P2 corresponds to the external electrode 4a shown in FIG.
 なお、インダクタL1とインダクタL2とは、互いに磁気結合(結合係数k)をしている。これにより、インダクタL1とインダクタL2との間に、相互インダクタンスMが発生する。もちろん、フィルタ装置100は、インダクタL1とインダクタL2とが互いに磁気結合している場合に限定されず、インダクタL1とインダクタL2とが互いに磁気結合していない構成であってもよい。また、配線パターン11cから電流が流れたときにインダクタL1の磁界の発生する向きとインダクタL2の磁界の発生する向きとは図1のように反対向きである場合に限られず同じ向きであっても良い。 Note that the inductor L1 and the inductor L2 are magnetically coupled to each other (coupling coefficient k). As a result, mutual inductance M is generated between inductor L1 and inductor L2. Of course, the filter device 100 is not limited to the case where the inductor L1 and the inductor L2 are magnetically coupled to each other, and may have a configuration where the inductor L1 and the inductor L2 are not magnetically coupled to each other. Further, when a current flows from the wiring pattern 11c, the direction in which the magnetic field is generated in the inductor L1 and the direction in which the magnetic field is generated in the inductor L2 are not limited to the opposite directions as shown in FIG. 1, but may be the same direction. good.
 [フィルタ装置の分解平面図]
 次に、分解平面図を用いて各層の構成について説明する。図4は、実施の形態に係るフィルタ装置100の構成を示す分解平面図である。まず、図4に示すように、導体パターン1a~1c,2d,2e、配線パターン11a,11c,12d,6h,7h,8h~8j,9i,9j、および電極パターン5f,5g,5hの各々は、絶縁基板3a~3jに印刷工法で形成される。
[Exploded plan view of filter device]
Next, the structure of each layer will be explained using an exploded plan view. FIG. 4 is an exploded plan view showing the configuration of the filter device 100 according to the embodiment. First, as shown in FIG. 4, each of conductor patterns 1a to 1c, 2d, 2e, wiring patterns 11a, 11c, 12d, 6h, 7h, 8h to 8j, 9i, 9j, and electrode patterns 5f, 5g, 5h are , are formed on the insulating substrates 3a to 3j by a printing method.
 絶縁基板3aには、インダクタL1の一部を構成する導体パターン1aが形成されている。導体パターン1aは、絶縁基板3aの図中左上側から右回りに約3/4周するように形成されている。導体パターン1aの始端は、配線パターン11aを介して外部電極4aと電気的に接続される。導体パターン1aの終端の近傍には、ビア導体31と接続する接続部31aが設けられている。 A conductor pattern 1a that constitutes a part of the inductor L1 is formed on the insulating substrate 3a. The conductor pattern 1a is formed so as to extend approximately 3/4 of the way clockwise from the upper left side in the figure of the insulating substrate 3a. The starting end of the conductor pattern 1a is electrically connected to the external electrode 4a via the wiring pattern 11a. A connecting portion 31a connected to the via conductor 31 is provided near the end of the conductive pattern 1a.
 絶縁基板3bには、インダクタL1の一部を構成する導体パターン1bが形成されている。導体パターン1bは、絶縁基板3bの図中左下側から右回りに約3/4周するように形成されている。導体パターン1bの始端の近傍には、ビア導体31と接続する接続部31bが設けられている。導体パターン1bの終端の近傍には、ビア導体32と接続する接続部32bが設けられている。 A conductor pattern 1b that constitutes a part of the inductor L1 is formed on the insulating substrate 3b. The conductor pattern 1b is formed so as to extend approximately 3/4 of the way clockwise from the lower left side in the figure of the insulating substrate 3b. A connecting portion 31b connected to the via conductor 31 is provided near the starting end of the conductive pattern 1b. A connection portion 32b connected to the via conductor 32 is provided near the end of the conductor pattern 1b.
 絶縁基板3cには、インダクタL1の一部を構成する導体パターン1cが形成されている。導体パターン1cは、絶縁基板3cの図中右下側から右回りに約3/4周するように形成されている。導体パターン1cの始端の近傍には、ビア導体32と接続する接続部32cが設けられている。導体パターン1cの終端は、配線パターン11cを介して外部電極4bと電気的に接続される。インダクタL1は、導体パターン1a~1cを直列接続させて、約2巻きのコイルを構成している。 A conductor pattern 1c forming a part of the inductor L1 is formed on the insulating substrate 3c. The conductor pattern 1c is formed so as to extend approximately 3/4 of the way clockwise from the lower right side in the figure of the insulating substrate 3c. A connecting portion 32c that connects to the via conductor 32 is provided near the starting end of the conductor pattern 1c. The terminal end of the conductor pattern 1c is electrically connected to the external electrode 4b via the wiring pattern 11c. The inductor L1 has conductor patterns 1a to 1c connected in series to form a coil with approximately two turns.
 絶縁基板3dには、インダクタL2の一部を構成する導体パターン2dが形成されている。導体パターン2dは、絶縁基板3dの図中右上側から右回りに約3/4周するように形成されている。導体パターン2dの始端は、配線パターン12dを介して外部電極4bと電気的に接続される。導体パターン2dの終端の近傍には、ビア導体33と接続する接続部33dが設けられている。 A conductor pattern 2d forming a part of the inductor L2 is formed on the insulating substrate 3d. The conductor pattern 2d is formed so as to go around about 3/4 clockwise from the upper right side in the figure of the insulating substrate 3d. The starting end of the conductor pattern 2d is electrically connected to the external electrode 4b via the wiring pattern 12d. A connection portion 33d that connects to the via conductor 33 is provided near the end of the conductor pattern 2d.
 絶縁基板3eには、インダクタL2の一部を構成する導体パターン2eが形成されている。導体パターン2eは、絶縁基板3eの図中左上側から右回りに約3/4周するように形成されている。導体パターン2eの始端の近傍には、ビア導体33と接続する接続部33eが設けられている。導体パターン2eの終端の近傍には、ビア導体34と接続する接続部34eが設けられている。インダクタL2は、導体パターン2e,2fを直列接続させて、約1.5巻きのコイルを構成している。 A conductor pattern 2e that constitutes a part of the inductor L2 is formed on the insulating substrate 3e. The conductor pattern 2e is formed so as to extend approximately 3/4 of the way clockwise from the upper left side in the figure of the insulating substrate 3e. A connecting portion 33e that connects to the via conductor 33 is provided near the starting end of the conductor pattern 2e. A connection portion 34e connected to the via conductor 34 is provided near the end of the conductor pattern 2e. The inductor L2 has conductor patterns 2e and 2f connected in series to form a coil with about 1.5 turns.
 絶縁基板3fには、キャパシタC1の一つの電極(第1電極)を構成する電極パターン5fが形成されている。電極パターン5fは、積層方向から平面視した場合に、インダクタL1,L2の開口部が重なった領域の中心とは重ならない位置に設けられているので、インダクタL1,L2で作る磁界のうち特に影響を受けやすい開口中央部の磁界を邪魔せず、小型部品でフィルタ装置100を実現できる。電極パターン5fは、ビア導体34と接続する接続部34fを有している。 An electrode pattern 5f that constitutes one electrode (first electrode) of the capacitor C1 is formed on the insulating substrate 3f. Since the electrode pattern 5f is provided at a position that does not overlap with the center of the area where the openings of the inductors L1 and L2 overlap when viewed in plan from the stacking direction, it is particularly affected by the magnetic field created by the inductors L1 and L2. The filter device 100 can be realized using small components without interfering with the magnetic field at the center of the opening, which is easily received. The electrode pattern 5f has a connecting portion 34f that connects to the via conductor 34.
 絶縁基板3gには、キャパシタC1の一つの電極(第2電極)を構成する電極パターン5gが形成されている。電極パターン5gは、積層方向から平面視した場合に、絶縁基板3fに形成された電極パターン5fと重なる位置に設けられている。電極パターン5gの面積は、電極パターン5fの面積より大きい。 An electrode pattern 5g that constitutes one electrode (second electrode) of the capacitor C1 is formed on the insulating substrate 3g. The electrode pattern 5g is provided at a position overlapping the electrode pattern 5f formed on the insulating substrate 3f when viewed in plan from the stacking direction. The area of the electrode pattern 5g is larger than the area of the electrode pattern 5f.
 絶縁基板3hには、キャパシタC1の一つの電極(第3電極)を構成する電極パターン5hが形成されている。電極パターン5hは、積層方向から平面視した場合に、絶縁基板3gに形成された電極パターン5gと重なる位置に設けられている。電極パターン5hの面積は、電極パターン5gの面積より小さい。電極パターン5hは、配線パターン6hを介して外部電極4aと電気的に接続される。なお、配線パターン6hは、電極パターン5hの長辺側から外部電極4aへと延びる2本の配線として図示してあるが、1本の配線または3本以上の配線で構成してもよい。また、配線パターン6hは、ビア導体35と接続する接続部35hを有している。 An electrode pattern 5h that constitutes one electrode (third electrode) of the capacitor C1 is formed on the insulating substrate 3h. The electrode pattern 5h is provided at a position overlapping with the electrode pattern 5g formed on the insulating substrate 3g when viewed in plan from the stacking direction. The area of the electrode pattern 5h is smaller than the area of the electrode pattern 5g. The electrode pattern 5h is electrically connected to the external electrode 4a via a wiring pattern 6h. Although the wiring pattern 6h is illustrated as two wirings extending from the long side of the electrode pattern 5h to the external electrode 4a, it may be composed of one wiring or three or more wirings. Further, the wiring pattern 6h has a connecting portion 35h that connects to the via conductor 35.
 キャパシタC1は、3層の各々に形成される電極パターン5f~5hを、積層方向から平面視した場合に重なるように配置することで、3つの電極により構成される2つのコンデンサ素子が直列に接続された構造となる。キャパシタC1は、電極パターン5g(第2電極の電極パターン)が電極パターン5f(第1電極の電極パターン)および電極パターン5h(第3電極の電極パターン)に比べて電極の面積が大きくなっている。また、電極パターン5hに接続される配線パターン6hの少なくとも一部が、電極パターン5gの一辺からはみ出している。このように、キャパシタC1を構成することで、後述するように、フィルタ装置100でのキャパシタC1が占める面積の割合を抑えつつ、製造するプロセスにおいてキャパシタC1の容量の変動を低減できる。 In the capacitor C1, two capacitor elements constituted by three electrodes are connected in series by arranging the electrode patterns 5f to 5h formed in each of the three layers so as to overlap when viewed from the stacking direction in plan. The structure is as follows. In the capacitor C1, the electrode pattern 5g (the electrode pattern of the second electrode) has a larger electrode area than the electrode pattern 5f (the electrode pattern of the first electrode) and the electrode pattern 5h (the electrode pattern of the third electrode). . Furthermore, at least a portion of the wiring pattern 6h connected to the electrode pattern 5h protrudes from one side of the electrode pattern 5g. By configuring the capacitor C1 in this way, as will be described later, it is possible to suppress the proportion of the area occupied by the capacitor C1 in the filter device 100, and to reduce fluctuations in the capacitance of the capacitor C1 during the manufacturing process.
 絶縁基板3hには、さらに配線パターン7hおよび配線パターン8hが形成されている。配線パターン7hと配線パターン8hとは一部が重なっており、電気的に接続されている。また、配線パターン8hは、ビア導体36と接続する接続部36hを有している。配線パターン7hは、絶縁基板3hの長辺に形成されている外部電極4b(図1参照)と電気的に接続されている。そのため、配線パターン7hは、外部電極4bと配線パターン8hとを電気的に接続する配線として機能している。 A wiring pattern 7h and a wiring pattern 8h are further formed on the insulating substrate 3h. The wiring pattern 7h and the wiring pattern 8h partially overlap and are electrically connected. Further, the wiring pattern 8h has a connecting portion 36h that connects to the via conductor 36. The wiring pattern 7h is electrically connected to an external electrode 4b (see FIG. 1) formed on the long side of the insulating substrate 3h. Therefore, the wiring pattern 7h functions as a wiring that electrically connects the external electrode 4b and the wiring pattern 8h.
 絶縁基板3iには、配線パターン8iおよび配線パターン9iが形成されている。配線パターン8iは、積層方向から平面視した場合に、絶縁基板3hに形成された配線パターン8hと重なる位置に設けられている。配線パターン9iは、積層方向から平面視した場合に、絶縁基板3hに形成された配線パターン6hと重なる位置に設けられている。配線パターン8iは、ビア導体36と接続する接続部36iを有している。配線パターン9iは、ビア導体35と接続する接続部35i、ビア導体37と接続する接続部37iを有している。 A wiring pattern 8i and a wiring pattern 9i are formed on the insulating substrate 3i. The wiring pattern 8i is provided at a position overlapping the wiring pattern 8h formed on the insulating substrate 3h when viewed in plan from the stacking direction. The wiring pattern 9i is provided at a position overlapping the wiring pattern 6h formed on the insulating substrate 3h when viewed in plan from the stacking direction. The wiring pattern 8i has a connecting portion 36i that connects to the via conductor 36. The wiring pattern 9i has a connecting portion 35i that connects to the via conductor 35 and a connecting portion 37i that connects to the via conductor 37.
 絶縁基板3jには、配線パターン8jおよび配線パターン9jが形成されている。配線パターン8jは、積層方向から平面視した場合に、絶縁基板3iに形成された配線パターン8iと重なる位置に設けられている。配線パターン9jは、積層方向から平面視した場合に、絶縁基板3iに形成された配線パターン9iと重なる位置に設けられている。配線パターン8jは、ビア導体36と接続する接続部36jを有している。配線パターン9jは、ビア導体37と接続する接続部37jを有している。 A wiring pattern 8j and a wiring pattern 9j are formed on the insulating substrate 3j. The wiring pattern 8j is provided at a position overlapping the wiring pattern 8i formed on the insulating substrate 3i when viewed in plan from the stacking direction. The wiring pattern 9j is provided at a position overlapping the wiring pattern 9i formed on the insulating substrate 3i when viewed in plan from the stacking direction. The wiring pattern 8j has a connecting portion 36j that connects to the via conductor 36. The wiring pattern 9j has a connecting portion 37j that connects to the via conductor 37.
 絶縁基板3kには、外部電極4aとビア導体37とを接続する接続部37k、および外部電極4bとビア導体36とを接続する接続部36kが形成されている。配線パターン6hは、外部電極4aの側面と電気的に接続されているだけでなく、ビア導体35およびビア導体37を介して外部電極4aの底面とも電気的に接続されている。これにより、絶縁体3の側面に形成された外部電極4aと絶縁体3の底面に形成された外部電極4aとを通る経路において電気的な接続が切断された場合でも、絶縁体3内の配線パターン6h、ビア導体35およびビア導体37を通る経路で電気的な接続を維持できる。もちろん、このような冗長な構成が不要であれば、配線パターン9i,9j、およびビア導体35,37を設けなくてもよい。 A connecting portion 37k that connects the external electrode 4a and the via conductor 37, and a connecting portion 36k that connects the external electrode 4b and the via conductor 36 are formed on the insulating substrate 3k. The wiring pattern 6h is not only electrically connected to the side surface of the external electrode 4a, but also electrically connected to the bottom surface of the external electrode 4a via the via conductor 35 and the via conductor 37. As a result, even if the electrical connection is broken in the path passing between the external electrode 4a formed on the side surface of the insulator 3 and the external electrode 4a formed on the bottom surface of the insulator 3, the wiring inside the insulator 3 Electrical connection can be maintained through the path passing through pattern 6h, via conductor 35, and via conductor 37. Of course, if such a redundant configuration is unnecessary, the wiring patterns 9i, 9j and the via conductors 35, 37 may not be provided.
 配線パターン7hは、外部電極4bの側面と電気的に接続されているだけでなく、配線パターン8hおよびビア導体36を介して外部電極4bの底面とも電気的に接続されている。これにより、絶縁体3の側面に形成された外部電極4bと絶縁体3の底面に形成された外部電極4bとを通る経路において電気的な接続が切断された場合でも、絶縁体3内の配線パターン7h,8h、およびビア導体36を通る経路で電気的な接続を維持できる。もちろん、このような冗長な構成が不要であれば、配線パターン7h,8h~8j、およびビア導体36を設けなくてもよい。 The wiring pattern 7h is not only electrically connected to the side surface of the external electrode 4b, but also electrically connected to the bottom surface of the external electrode 4b via the wiring pattern 8h and the via conductor 36. As a result, even if the electrical connection is broken in the path passing between the external electrode 4b formed on the side surface of the insulator 3 and the external electrode 4b formed on the bottom surface of the insulator 3, the wiring inside the insulator 3 Electrical connection can be maintained through the paths passing through patterns 7h, 8h and via conductor 36. Of course, if such a redundant configuration is unnecessary, the wiring patterns 7h, 8h to 8j and the via conductor 36 may not be provided.
 [キャパシタC1の構成]
 フィルタ装置100では、3つの電極(電極パターン5f~5h)により構成される2つのコンデンサ素子が直列に接続された構造のキャパシタC1を採用している。さらに、キャパシタC1は、電極パターン5hに接続される配線パターン6hの少なくとも一部が、電極パターン5gの一辺からはみ出す構成としている。このキャパシタC1の構成についてさらに詳しく説明する。
[Configuration of capacitor C1]
The filter device 100 employs a capacitor C1 having a structure in which two capacitor elements constituted by three electrodes (electrode patterns 5f to 5h) are connected in series. Furthermore, the capacitor C1 is configured such that at least a portion of the wiring pattern 6h connected to the electrode pattern 5h protrudes from one side of the electrode pattern 5g. The configuration of this capacitor C1 will be explained in more detail.
 図5は、実施の形態に係るフィルタ装置100のキャパシタC1を構成する電極の平面図である。図6は、比較対象のキャパシタを構成する電極の平面図である。キャパシタC1は、図5に示す電極パターン5f~5hを積層方向に重ねて配置することで、電極パターン5fと電極パターン5gとで構成されるコンデンサ素子C1aと、電極パターン5gと電極パターン5h(配線パターン6hの一部を含む)とで構成されるコンデンサ素子C1bとが直列接続された構造である。キャパシタC1では、面積の大きい電極パターン5gの積層方向の上下に、面積の小さい電極パターン5f,5hが配置されている。 FIG. 5 is a plan view of the electrodes forming the capacitor C1 of the filter device 100 according to the embodiment. FIG. 6 is a plan view of an electrode forming a capacitor to be compared. The capacitor C1 is constructed by arranging the electrode patterns 5f to 5h shown in FIG. This structure has a structure in which a capacitor element C1b including a part of the pattern 6h) and a capacitor element C1b are connected in series. In the capacitor C1, electrode patterns 5f and 5h with small areas are arranged above and below the electrode pattern 5g with a large area in the stacking direction.
 キャパシタの容量は、対向する電極の重なる面積により決まるため、面積の大きい電極パターン5gと面積の小さい電極パターン5fとで構成されるコンデンサ素子C1aでは、電極パターン5fの面積で容量が決まることになる。同様に、面積の大きい電極パターン5gと面積の小さい電極パターン5h(配線パターン6hの一部を含む)とで構成されるコンデンサ素子C1bでは、電極パターン5h(配線パターン6hの一部を含む)の面積で容量が決まることになる。 Since the capacitance of a capacitor is determined by the overlapping area of opposing electrodes, in the capacitor element C1a composed of an electrode pattern 5g with a large area and an electrode pattern 5f with a small area, the capacitance is determined by the area of the electrode pattern 5f. . Similarly, in the capacitor element C1b composed of the electrode pattern 5g having a large area and the electrode pattern 5h having a small area (including a part of the wiring pattern 6h), the electrode pattern 5h (including a part of the wiring pattern 6h) Capacity is determined by area.
 そのため、図5に示すように、電極パターン5gが製造プロセスによる寸法ばらつきで電極パターン51gのように面積が大きくなってもキャパシタC1の容量は変動しない。一方、電極パターン5f,5hが製造プロセスによる寸法ばらつきで電極パターン51f,51hのように面積が大きくなるとキャパシタC1の容量が変動することになる。 Therefore, as shown in FIG. 5, even if the electrode pattern 5g has a large area like the electrode pattern 51g due to dimensional variations due to the manufacturing process, the capacitance of the capacitor C1 does not change. On the other hand, if the electrode patterns 5f and 5h have a large area like the electrode patterns 51f and 51h due to dimensional variations due to the manufacturing process, the capacitance of the capacitor C1 will fluctuate.
 図6(a)に示すように、電極パターン5aと電極パターン5bとで構成されるキャパシタCaは、図5に示す電極パターン5fと電極パターン5gと同じ層間距離で、2層の電極で構成されたキャパシタであるため、図5に示すキャパシタC1と同じ容量にするにはキャパシタCaの各電極の面積を小さくする必要がある。製造プロセスによる寸法ばらつきは電極サイズに関わらず一定であるため、電極パターン5aが電極パターン51aに変化するとキャパシタCaの容量が変動することになる。キャパシタCaでは、図5に示す電極パターン5f,5hの面積よりも小さい電極パターン5aの面積が変動するのでキャパシタCaの容量の変化率としては大きく変動することになる。つまり、本実施の形態では、図6(a)に示す電極パターン5aより大きい面積の電極パターン5f,5hを採用し、いずれか一方が製造プロセスによる寸法ばらつきで面積が変動しても、キャパシタCaに比べキャパシタC1の容量の変動率を低減している。 As shown in FIG. 6(a), a capacitor Ca made up of an electrode pattern 5a and an electrode pattern 5b is made up of two layers of electrodes with the same interlayer distance as the electrode pattern 5f and the electrode pattern 5g shown in FIG. Therefore, in order to have the same capacity as the capacitor C1 shown in FIG. 5, it is necessary to reduce the area of each electrode of the capacitor Ca. Since dimensional variations due to the manufacturing process are constant regardless of the electrode size, when the electrode pattern 5a changes to the electrode pattern 51a, the capacitance of the capacitor Ca changes. In the capacitor Ca, since the area of the electrode pattern 5a, which is smaller than the area of the electrode patterns 5f and 5h shown in FIG. 5, varies, the rate of change in the capacitance of the capacitor Ca varies greatly. In other words, in this embodiment, electrode patterns 5f and 5h having a larger area than electrode pattern 5a shown in FIG. The fluctuation rate of the capacitance of the capacitor C1 is reduced compared to the above.
 また、電極パターン5gに比べて面積の小さい電極パターン5f,5hを積層方向の上下に配置してキャパシタC1を構成することで、製造プロセスにより電極パターン5gに対して電極パターン5f,5hの位置がずれても、電極パターン5gと重なる範囲であればキャパシタC1の容量は変動しない。 In addition, by configuring the capacitor C1 by arranging the electrode patterns 5f and 5h, which have smaller areas than the electrode pattern 5g, above and below in the stacking direction, the positions of the electrode patterns 5f and 5h with respect to the electrode pattern 5g can be adjusted due to the manufacturing process. Even if it deviates, the capacitance of the capacitor C1 does not change as long as it overlaps with the electrode pattern 5g.
 さらに、本実施の形態では、図5に示すように、電極パターン5hに配線パターン6hを接続している。そのため、積層方向から平面視した場合に配線パターン6hと電極パターン5gとが重なる部分もキャパシタC1の容量に含まれることになる。配線パターン6hは、製造プロセスによる寸法ばらつきで面積が変動した場合、図5に示すように配線パターン61hに変化する。配線パターン6hから配線パターン61hに変化した場合に、電極パターン5gと重なる配線パターン6hの面積は、配線パターン6hの配線幅の方向のみ変動し、電極パターン5gの一辺、および当該一辺と対向する辺からはみ出している配線パターン6hの長さ方向には変動しない。 Further, in this embodiment, as shown in FIG. 5, a wiring pattern 6h is connected to the electrode pattern 5h. Therefore, the portion where the wiring pattern 6h and the electrode pattern 5g overlap when viewed in plan from the stacking direction is also included in the capacitance of the capacitor C1. When the area of the wiring pattern 6h changes due to dimensional variations due to the manufacturing process, the wiring pattern 6h changes to a wiring pattern 61h as shown in FIG. 5. When changing from the wiring pattern 6h to the wiring pattern 61h, the area of the wiring pattern 6h that overlaps with the electrode pattern 5g changes only in the direction of the wiring width of the wiring pattern 6h, and the area of the wiring pattern 6h that overlaps with the electrode pattern 5g changes only in the direction of the wiring width of the wiring pattern 6h, and the area of the wiring pattern 6h that overlaps with the electrode pattern 5g changes only in the direction of the wiring width of the wiring pattern 6h. There is no change in the length direction of the wiring pattern 6h that protrudes from the wiring pattern 6h.
 一方、図6(b)に示すように、電極パターン5cと電極パターン5dと電極パターン5eとで構成されるキャパシタCbでは、電極パターン5eに配線パターンを接続していない。そのため、電極パターン5eは、配線パターンを接続していない部分も電極パターン5gと重なる面積として変動することになり、電極の寸法ばらつきがキャパシタCbの容量の変動に影響を与えることになる。よって、本実施の形態では、電極パターン5hに配線パターン6hを接続することで、配線パターン6hの長さ方向に対する配線パターン6hの面積の変動を無視できるので、キャパシタC1の容量の変動を低減できる。 On the other hand, as shown in FIG. 6(b), in the capacitor Cb composed of the electrode pattern 5c, the electrode pattern 5d, and the electrode pattern 5e, no wiring pattern is connected to the electrode pattern 5e. Therefore, the area of the electrode pattern 5e that is not connected to the wiring pattern also varies as it overlaps with the electrode pattern 5g, and the variation in the dimensions of the electrodes affects the variation in the capacitance of the capacitor Cb. Therefore, in the present embodiment, by connecting the wiring pattern 6h to the electrode pattern 5h, variations in the area of the wiring pattern 6h with respect to the length direction of the wiring pattern 6h can be ignored, and therefore variations in the capacitance of the capacitor C1 can be reduced. .
 さらに、具体的な数値を用いてキャパシタC1の容量の変動を低減できることを説明する。キャパシタC1の容量の変動について、誤差の伝搬理論を適用すると、式1のようにあらわすことができる。 Furthermore, it will be explained that the fluctuation in the capacitance of the capacitor C1 can be reduced using specific numerical values. By applying the error propagation theory, the variation in the capacitance of the capacitor C1 can be expressed as shown in Equation 1.
Figure JPOXMLDOC01-appb-M000001
Figure JPOXMLDOC01-appb-M000001
 ここで、キャパシタC1の容量をC、比誘電率をε、電極パターンの面積をS、電極パターン間の距離をDとする。 Here, the capacitance of the capacitor C1 is C, the relative permittivity is ε r , the area of the electrode patterns is S, and the distance between the electrode patterns is D.
 式1から分かるように、キャパシタC1の容量Cの変動を抑えるためには、比誘電率εの変動、電極パターンの面積Sの変動、電極パターン間の距離Dの変動のうち少なくとも1つを低減する必要がある。本実施の形態では、電極パターンの面積Sの変動に着目してキャパシタC1の容量Cの変動を抑えている。 As can be seen from Equation 1, in order to suppress the variation in the capacitance C of the capacitor C1, at least one of the variation in the relative permittivity ε r , the variation in the area S of the electrode patterns, and the variation in the distance D between the electrode patterns is suppressed. need to be reduced. In this embodiment, fluctuations in the capacitance C of the capacitor C1 are suppressed by focusing on fluctuations in the area S of the electrode pattern.
 以下の説明では、電極パターンの面積Sを一定とした場合に、製造プロセスによる寸法ばらつきで変動する面積の変動量ΔSを評価することで、キャパシタC1の容量Cの変動を低減できるか否かについて確認する。以下で説明するシミュレーション結果は、製造プロセスによる寸法ばらつきを50μm、位置ズレを50μmとして計算している。 In the following explanation, if the area S of the electrode pattern is constant, we will discuss whether it is possible to reduce the variation in the capacitance C of the capacitor C1 by evaluating the amount of variation ΔS in the area that varies due to dimensional variations due to the manufacturing process. confirm. The simulation results described below are calculated assuming that the dimensional variation due to the manufacturing process is 50 μm and the positional deviation is 50 μm.
 図5に示すキャパシタC1では、電極パターン5fの面積が150μm×300μm、電極パターン5gの面積が200μm×350μm、電極パターン5hの面積が150μm×300μm、電極パターン5hから延びる配線パターン6hの部分の面積が100μm×100μm×2本とする。電極パターン5fと電極パターン5gとで構成されるコンデンサ素子C1aにおいて容量として有効な電極の面積は、面積が小さい方の電極パターン5fの面積(150μm×300μm)となる。電極パターン5gと電極パターン5hとで構成されるキャパシタ(コンデンサ素子C1bの一部)において容量として有効な電極の面積は、面積が小さい方の電極パターン5hの面積(150μm×300μm)となる。さらに、電極パターン5hから延びる配線パターン6hの部分と電極パターン5gとで構成されるキャパシタ(コンデンサ素子C1bの一部)において容量として有効な電極の面積は、25μm×100μm×2となる。 In the capacitor C1 shown in FIG. 5, the area of the electrode pattern 5f is 150 μm x 300 μm, the area of the electrode pattern 5g is 200 μm x 350 μm, the area of the electrode pattern 5h is 150 μm x 300 μm, and the area of the wiring pattern 6h extending from the electrode pattern 5h. is 100 μm x 100 μm x 2 pieces. In the capacitor element C1a composed of the electrode pattern 5f and the electrode pattern 5g, the effective area of the electrode as a capacitor is the area of the smaller electrode pattern 5f (150 μm×300 μm). In the capacitor (part of capacitor element C1b) composed of the electrode pattern 5g and the electrode pattern 5h, the effective area of the electrode as a capacitor is the area of the smaller electrode pattern 5h (150 μm×300 μm). Further, in the capacitor (a part of the capacitor element C1b) constituted by the wiring pattern 6h extending from the electrode pattern 5h and the electrode pattern 5g, the effective area of the electrode as a capacitor is 25 μm×100 μm×2.
 キャパシタC1は、電極パターン5fと電極パターン5gとで構成されるコンデンサ素子C1aと電極パターン5gと電極パターン5h(配線パターン6hの一部を含む)とで構成されるコンデンサ素子C1bとが直列接続された構造となっている。そのため、キャパシタC1の容量は、コンデンサ素子C1aの容量とコンデンサ素子C1bの容量との和分の積で求めることができる。同じように、キャパシタC1で容量として有効な電極の面積は、コンデンサ素子C1aとして有効な電極の面積(電極パターン5fの面積)と、コンデンサ素子C1bとして有効な電極の面積(電極パターン5hと配線パターン6hの一部とを含む面積)との和分の積で求めることができる。そのため、前述の具体例において、キャパシタC1で容量として有効な電極の面積は、約23684μmと求めることができる。 In the capacitor C1, a capacitor element C1a composed of an electrode pattern 5f and an electrode pattern 5g, and a capacitor element C1b composed of an electrode pattern 5g and an electrode pattern 5h (including a part of a wiring pattern 6h) are connected in series. It has a similar structure. Therefore, the capacitance of the capacitor C1 can be determined by the product of the sum of the capacitance of the capacitor element C1a and the capacitance of the capacitor element C1b. Similarly, the area of the electrode that is effective as a capacitor in capacitor C1 is the area of the electrode that is effective as capacitor element C1a (the area of electrode pattern 5f), and the area of the electrode that is effective as capacitor element C1b (the area of electrode pattern 5h and the wiring pattern). (area including part of 6h). Therefore, in the specific example described above, the area of the electrode that is effective as a capacitor in the capacitor C1 can be determined to be approximately 23684 μm 2 .
 図6(b)に示すキャパシタCbで容量として有効な電極の面積が約23684μmとなるようにするには、電極パターン5cの面積を150μm×315.8μm、電極パターン5dの面積を200μm×365.8μm、電極パターン5eの面積を150μm×315.8μmとする必要がある。 In order to make the area of the electrode effective as a capacitor in the capacitor Cb shown in FIG. 6(b) approximately 23684 μm2 , the area of the electrode pattern 5c is 150 μm x 315.8 μm, and the area of the electrode pattern 5d is 200 μm x 365 μm. .8 μm, and the area of the electrode pattern 5e needs to be 150 μm×315.8 μm.
 製造プロセスによる寸法ばらつきは、電極パターンに対して独立事象として発生することから、誤差の伝搬の考えを元に寸法ばらつきが50μmであると計算すると、キャパシタC1での電極の面積の変動量ΔSは、約35355μmとなる。一方、図6(b)に示すキャパシタCbでの電極の面積の変動量ΔSは、約36471μmとなる。 Dimensional variation due to the manufacturing process occurs as an independent event with respect to the electrode pattern, so if we calculate that the dimensional variation is 50 μm based on the concept of error propagation, the amount of variation ΔS in the electrode area of capacitor C1 is , approximately 35355 μm2 . On the other hand, the amount of variation ΔS in the area of the electrode in the capacitor Cb shown in FIG. 6(b) is approximately 36471 μm 2 .
 キャパシタC1は、キャパシタCbに比べ電極の面積の変動量ΔSを約3%抑えることができた。これは、キャパシタC1において、配線パターン6hの長さ方向に対する配線パターン6hの面積の変動を無視することができるためである。よって、キャパシタC1では、積層方向から平面視した場合に重なる電極パターン5gの辺からはみ出している配線パターン6hを有しているので、製造するプロセスにおいてキャパシタC1の容量の変動を低減できる。 The capacitor C1 was able to suppress the variation ΔS in the electrode area by about 3% compared to the capacitor Cb. This is because, in the capacitor C1, variations in the area of the wiring pattern 6h in the length direction of the wiring pattern 6h can be ignored. Therefore, since the capacitor C1 has the wiring pattern 6h protruding from the side of the overlapping electrode pattern 5g when viewed in plan from the stacking direction, variations in the capacitance of the capacitor C1 can be reduced in the manufacturing process.
 また、キャパシタC1の電極パターン5gの面積は、200μm×350μm=70000μmとなっているが、図6(b)に示すキャパシタCbの電極パターン5dの面積は、キャパシタC1の配線パターン6hがないため電極パターン5eを大きくする必要があり、製造時のズレを考慮したマージンを含めることで、200μm×365.8μm=73160μmとなっている。そのため、キャパシタC1は、キャパシタCbに比べ積層方向から平面視した場合の面積を小さくできるので、電子部品でのキャパシタが占める面積の割合を抑えることができる。 Further, the area of the electrode pattern 5g of the capacitor C1 is 200 μm x 350 μm = 70000 μm 2 , but the area of the electrode pattern 5d of the capacitor Cb shown in FIG. 6(b) is because there is no wiring pattern 6h of the capacitor C1. It is necessary to increase the size of the electrode pattern 5e, and the size is 200 μm×365.8 μm=73160 μm 2 by including a margin in consideration of deviations during manufacturing. Therefore, the area of the capacitor C1 when viewed in plan from the stacking direction can be made smaller than that of the capacitor Cb, so that the proportion of the area occupied by the capacitor in the electronic component can be suppressed.
 [キャパシタC1の変形例]
 次に、キャパシタC1の変形例について説明する。図7は、変形例1に係るキャパシタC1を構成する電極の平面図である。図7(a)では、電極パターン5hの長辺の中央部から配線パターン6haがはみ出している電極が図示されている。なお、破線で示す配線パターン61haは、寸法ばらつきが生じた後の配線パターン6haの形状を示す。電極パターン5hは、積層方向から平面視した場合の形状が矩形形状であり、配線パターン6haの配線幅は、電極パターン5hの一辺の長さより短くなっている。そのため、図7(a)に示す電極パターン5hと配線パターン6haとを合わせた形状を積層方向から平面視した場合、十字形状となっている。また、図7(a)のように電極パターン5hに対して上下の配線パターン6haの接続位置は中央でなくてもよく、さらに当該接続位置は上下で異なる位置でもよい。
[Modified example of capacitor C1]
Next, a modification of the capacitor C1 will be described. FIG. 7 is a plan view of the electrodes forming the capacitor C1 according to the first modification. FIG. 7A shows an electrode in which a wiring pattern 6ha protrudes from the center of the long side of the electrode pattern 5h. Note that the wiring pattern 61ha indicated by a broken line shows the shape of the wiring pattern 6ha after dimensional variations have occurred. The electrode pattern 5h has a rectangular shape when viewed in plan from the stacking direction, and the wiring width of the wiring pattern 6ha is shorter than the length of one side of the electrode pattern 5h. Therefore, when the combined shape of the electrode pattern 5h and the wiring pattern 6ha shown in FIG. 7(a) is viewed in plan from the stacking direction, it has a cross shape. Moreover, as shown in FIG. 7A, the connection position of the upper and lower wiring patterns 6ha with respect to the electrode pattern 5h does not have to be at the center, and furthermore, the connection positions may be at different positions on the upper and lower sides.
 図7(a)に示す配線パターン6haでは、配線幅が電極パターン5hの一辺の長さより短くなっているが、図7(b)に示す配線パターン6hbでは、配線幅が電極パターン5hの一辺の長さと同じである。図7(b)では、電極パターン5hの長辺から配線パターン6hbがはみ出している電極が図示されている。なお、破線で示す配線パターン61hbは、寸法ばらつきが生じた後の配線パターン6hbの形状を示す。電極パターン5hと配線パターン6hbとを合わせた形状を積層方向から平面視した場合、矩形形状となっている。図7(b)の場合、実際の構造では電極パターン5hと配線パターン6hbの境界は不明瞭であるため、積層方向から平面視した場合に、積層した電極パターン5gに対して電極パターン5hと配線パターン6hbの一体化したパターンが電極パターン5gのいずれかの辺よりはみ出ていればよい。 In the wiring pattern 6ha shown in FIG. 7(a), the wiring width is shorter than the length of one side of the electrode pattern 5h, but in the wiring pattern 6hb shown in FIG. 7(b), the wiring width is shorter than the length of one side of the electrode pattern 5h. It is the same as the length. FIG. 7B shows an electrode in which a wiring pattern 6hb protrudes from the long side of the electrode pattern 5h. Note that the wiring pattern 61hb indicated by a broken line shows the shape of the wiring pattern 6hb after dimensional variations have occurred. When the combined shape of the electrode pattern 5h and the wiring pattern 6hb is viewed in plan from the stacking direction, it has a rectangular shape. In the case of FIG. 7(b), in the actual structure, the boundary between the electrode pattern 5h and the wiring pattern 6hb is unclear, so when viewed from the stacking direction, the electrode pattern 5h and the wiring It is sufficient that the integrated pattern 6hb protrudes from any side of the electrode pattern 5g.
 図7(a)では、電極パターン5hの2つの長辺(対向する2つの辺)のそれぞれに配線パターン6haが接続されているが、いずれか一方の長辺に配線パターン6haが接続される構成でもよい。同様に、図7(b)では、電極パターン5hの2つの長辺(対向する2つの辺)のそれぞれに配線パターン6hbが接続されているが、いずれか一方の長辺に配線パターン6hbが接続される構成でもよい。 In FIG. 7A, the wiring pattern 6ha is connected to each of the two long sides (two opposing sides) of the electrode pattern 5h, but the wiring pattern 6ha is connected to one of the long sides. But that's fine. Similarly, in FIG. 7(b), the wiring pattern 6hb is connected to each of the two long sides (two opposing sides) of the electrode pattern 5h, but the wiring pattern 6hb is connected to one of the long sides. It may also be a configuration in which
 また、配線パターンは、電極パターン5hの長辺に接続される構成に限定されず、電極パターン5hの短辺に接続される構成でもよい。図7(c)では、電極パターン5hの短辺から配線パターン6hcがはみ出している電極が図示されている。なお、破線で示す配線パターン61hcは、寸法ばらつきが生じた後の配線パターン6hcの形状を示す。電極パターン5hと配線パターン6hcとを合わせた形状を積層方向から平面視した場合、T字形状となっている。もちろん、図7(c)では、電極パターン5hの1つの短辺に配線パターン6hcが接続されているが、2の短辺に配線パターン6hcが接続される構成でもよい。図7(c)のように電極パターン5hに対して配線パターン6hcの接続位置は中央でなくてもよく、当該接続位置を上下どちらかに寄せてもよい。 Further, the wiring pattern is not limited to the configuration in which it is connected to the long side of the electrode pattern 5h, but may be configured to be connected to the short side of the electrode pattern 5h. FIG. 7C shows an electrode in which a wiring pattern 6hc protrudes from the short side of the electrode pattern 5h. Note that the wiring pattern 61hc indicated by a broken line shows the shape of the wiring pattern 6hc after dimensional variations have occurred. When the combined shape of the electrode pattern 5h and the wiring pattern 6hc is viewed in plan from the stacking direction, it has a T-shape. Of course, in FIG. 7(c), the wiring pattern 6hc is connected to one short side of the electrode pattern 5h, but a configuration may be adopted in which the wiring pattern 6hc is connected to two short sides. As shown in FIG. 7C, the connection position of the wiring pattern 6hc with respect to the electrode pattern 5h does not have to be in the center, but may be shifted to either the upper or lower side.
 キャパシタC1は、3層の各々に形成される電極パターン5f、電極パターン5g、および電極パターン5hにより構成される2つのコンデンサ素子が直列に接続された構造であると説明したが、4層以上の各々に形成される電極パターンにより構成される複数のコンデンサ素子が直列に接続された構造であってもよい。図8は、変形例2に係るキャパシタC1Aを構成する電極の平面図である。キャパシタC1Aは、図8に示すように、5層の各々に形成される電極パターン5i~5mにより構成される4つのコンデンサ素子が直列に接続された構造である。 It has been explained that the capacitor C1 has a structure in which two capacitor elements constituted by the electrode pattern 5f, the electrode pattern 5g, and the electrode pattern 5h formed in each of three layers are connected in series. A structure may be employed in which a plurality of capacitor elements each formed by an electrode pattern are connected in series. FIG. 8 is a plan view of an electrode configuring a capacitor C1A according to modification 2. As shown in FIG. 8, the capacitor C1A has a structure in which four capacitor elements each formed by electrode patterns 5i to 5m formed in five layers are connected in series.
 電極パターン5iは、矩形形状であり、2つの短辺(対向する2つの辺)に配線パターン6iが接続されている。なお、破線で示す電極パターン51iは、寸法ばらつきが生じた後の電極パターン5iの形状を示す。破線で示す配線パターン61iは、寸法ばらつきが生じた後の配線パターン6iの形状を示す。電極パターン5jは、電極パターン5iより面積が大きい矩形形状である。なお、破線で示す電極パターン51jは、寸法ばらつきが生じた後の電極パターン5jの形状を示す。 The electrode pattern 5i has a rectangular shape, and the wiring pattern 6i is connected to two short sides (two opposing sides). Note that the electrode pattern 51i indicated by a broken line indicates the shape of the electrode pattern 5i after dimensional variations have occurred. The wiring pattern 61i indicated by a broken line shows the shape of the wiring pattern 6i after dimensional variations have occurred. The electrode pattern 5j has a rectangular shape with a larger area than the electrode pattern 5i. Note that the electrode pattern 51j indicated by a broken line indicates the shape of the electrode pattern 5j after dimensional variations have occurred.
 電極パターン5kは、電極パターン5jより面積が小さい矩形形状である。なお、破線で示す電極パターン51kは、寸法ばらつきが生じた後の電極パターン5kの形状を示す。電極パターン5j~5kの構造は、面積の大きい電極パターン5jの積層方向の上下に、面積の小さい電極パターン5iと電極パターン5kとで挟んだ構造である。 The electrode pattern 5k has a rectangular shape with a smaller area than the electrode pattern 5j. Note that the electrode pattern 51k indicated by a broken line indicates the shape of the electrode pattern 5k after dimensional variations have occurred. The structure of the electrode patterns 5j to 5k is such that the electrode pattern 5j, which has a large area, is sandwiched between the electrode pattern 5i, which has a small area, and the electrode pattern 5k, above and below in the stacking direction.
 さらに、電極パターン5lは、電極パターン5kより面積が大きい矩形形状である。なお、破線で示す電極パターン51lは、寸法ばらつきが生じた後の電極パターン5lの形状を示す。 Further, the electrode pattern 5l has a rectangular shape with a larger area than the electrode pattern 5k. Note that the electrode pattern 51l indicated by a broken line shows the shape of the electrode pattern 5l after dimensional variations have occurred.
 電極パターン5mは、矩形形状であり、2つの長辺(対向する2つの辺)に配線パターン6mが接続されている。なお、破線で示す電極パターン51mは、寸法ばらつきが生じた後の電極パターン5mの形状を示す。破線で示す配線パターン61mは、寸法ばらつきが生じた後の配線パターン6mの形状を示す。電極パターン5k~5mの構造は、面積の大きい電極パターン5lの積層方向の上下に、面積の小さい電極パターン5kと電極パターン5mとで挟んだ構造である。 The electrode pattern 5m has a rectangular shape, and the wiring pattern 6m is connected to two long sides (two opposing sides). Note that the electrode pattern 51m indicated by a broken line shows the shape of the electrode pattern 5m after dimensional variations have occurred. The wiring pattern 61m indicated by a broken line shows the shape of the wiring pattern 6m after dimensional variations have occurred. The structure of the electrode patterns 5k to 5m is such that the electrode pattern 5l, which has a large area, is sandwiched between the electrode pattern 5k, which has a small area, and the electrode pattern 5m, above and below in the stacking direction.
 キャパシタC1Aは、電極パターン5iに配線パターン6iを接続することで、配線パターン6iの長さ方向に対する配線パターン6iの面積の変動を無視でき、電極パターン5mに配線パターン6mを接続することで、配線パターン6mの長さ方向に対する配線パターン6mの面積の変動を無視できるので、容量の変動を抑えることができる。 By connecting the wiring pattern 6i to the electrode pattern 5i, the capacitor C1A can ignore the variation in the area of the wiring pattern 6i in the length direction of the wiring pattern 6i, and by connecting the wiring pattern 6m to the electrode pattern 5m, the wiring pattern 6i can be ignored. Since variations in the area of the wiring pattern 6m in the length direction of the pattern 6m can be ignored, variations in capacitance can be suppressed.
 キャパシタC1Aは、面積の大きい電極パターンの積層方向の上下に、面積の小さい2つの電極パターンで挟んだ構造を2つ有し、それぞれの構造において面積の小さい電極パターンの一方に配線パターンを接続した構成であればよい。配線パターンは、少なくとも一部が、積層方向から平面視した場合に重なる電極の一辺からはみ出していればよい。 Capacitor C1A has two structures in which an electrode pattern with a large area is sandwiched between two electrode patterns with a small area above and below in the stacking direction, and a wiring pattern is connected to one of the electrode patterns with a small area in each structure. Any configuration is fine. It is sufficient that at least a portion of the wiring pattern protrudes from one side of the overlapping electrodes when viewed in plan from the stacking direction.
 キャパシタC1Aは、図8に示すように面積の大きい電極パターン5j,5lの積層方向の上下に設ける電極パターン5i,5k,5mの面積がすべて同じ面積であっても異なる面積であってもよい。つまり、電極パターン5i,5k,5mの面積は、電極パターン5j,5lの面積より小さければよい。 In the capacitor C1A, as shown in FIG. 8, the electrode patterns 5i, 5k, and 5m provided above and below in the stacking direction of the large-area electrode patterns 5j, 5l may all have the same area or different areas. That is, the areas of the electrode patterns 5i, 5k, and 5m need only be smaller than the areas of the electrode patterns 5j, 5l.
 同様に、キャパシタC1は、図5に示すように、面積の大きい電極パターン5gの積層方向の上下に設ける電極パターン5f,5hの面積がすべて同じ面積であっても異なる面積であってもよい。つまり、電極パターン5f,5hの面積は、電極パターン5gの面積より小さければよい。 Similarly, in the capacitor C1, as shown in FIG. 5, the electrode patterns 5f and 5h provided above and below the electrode pattern 5g having a large area in the stacking direction may have the same area or different areas. In other words, the areas of the electrode patterns 5f and 5h need only be smaller than the area of the electrode pattern 5g.
 図1に示すキャパシタC1は、配線パターン6hが外部電極4aと電気的に接続する構成を説明したが、配線パターン6hが外部電極4aと電気的に接続されない構成であってもよい。同様に、キャパシタC1Aの配線パターン6i,6mも外部電極と電気的に接続される構成であっても、接続されない構成であってもよい。 Although the capacitor C1 shown in FIG. 1 has been described with a configuration in which the wiring pattern 6h is electrically connected to the external electrode 4a, it may be configured such that the wiring pattern 6h is not electrically connected to the external electrode 4a. Similarly, the wiring patterns 6i and 6m of the capacitor C1A may also be configured to be electrically connected to the external electrodes or not connected.
 キャパシタC1およびキャパシタC1Aは、フィルタ装置に採用される例について説明したが、少なくとも3層の各々に形成される電極により構成される素子が直列に接続されてキャパシタを構成する電子部品であれば、いずれの部品にキャパシタC1およびキャパシタC1Aの構造を採用してもよい。 The capacitor C1 and the capacitor C1A have been described as an example employed in a filter device, but if the elements constituted by electrodes formed in at least three layers are connected in series to constitute a capacitor, then The structure of capacitor C1 and capacitor C1A may be adopted for any component.
 以上のように、実施の形態に係るフィルタ装置100は、互いに対向する1対の主面と主面間を結ぶ側面とを有する絶縁体3と、絶縁体3内において少なくとも3層の各々に形成される電極により構成される素子が直列に接続されたキャパシタC1と、を備えている。キャパシタC1は、各々の層に形成される電極パターン5f~5hが積層方向から平面視した場合に互いに重なる位置に配置され、少なくとも1つの層に形成される電極パターン5hには、少なくとも1つの配線パターン6hが電気的に接続される。配線パターン6hの少なくとも一部は、積層方向から平面視した場合に重なる電極パターン5gの一辺からはみ出している。 As described above, the filter device 100 according to the embodiment includes an insulator 3 having a pair of main surfaces facing each other and a side surface connecting the main surfaces, and at least three layers formed in each of the insulator 3. and a capacitor C1 in which elements constituted by electrodes are connected in series. The capacitor C1 is arranged at a position where the electrode patterns 5f to 5h formed in each layer overlap each other when viewed in plan from the stacking direction, and the electrode pattern 5h formed in at least one layer has at least one wiring. Pattern 6h is electrically connected. At least a portion of the wiring pattern 6h protrudes from one side of the overlapping electrode pattern 5g when viewed in plan from the stacking direction.
 これにより、実施の形態に係るフィルタ装置100は、少なくとも3層の各々に形成される電極パターン5f~5hにより構成される素子が直列に接続されたキャパシタC1で、重なる電極パターン5gの一辺からはみ出している配線パターン6hと接続している電極パターン5hを有しているので、フィルタ装置100でのキャパシタC1が占める面積の割合を抑えつつ、製造するプロセスにおいてキャパシタC1の容量の変動を低減できる。 As a result, the filter device 100 according to the embodiment has a capacitor C1 in which elements constituted by the electrode patterns 5f to 5h formed in each of at least three layers are connected in series, and the capacitor C1 protrudes from one side of the overlapping electrode pattern 5g. Since the electrode pattern 5h is connected to the wiring pattern 6h, it is possible to suppress the ratio of the area occupied by the capacitor C1 in the filter device 100, and reduce fluctuations in the capacitance of the capacitor C1 during the manufacturing process.
 (態様)
 (1)本開示に係る電子部品は、互いに対向する1対の主面と主面間を結ぶ側面とを有する絶縁体と、絶縁体内において少なくとも3層の各々に形成される電極により構成される素子が直列に接続されたキャパシタと、を備え、キャパシタは、各々の層に形成される電極が積層方向から平面視した場合に互いに重なる位置に配置され、少なくとも1つの層に形成される電極には、少なくとも1つの配線パターンが電気的に接続され、配線パターンの少なくとも一部が、積層方向から平面視した場合に重なる電極の一辺からはみ出している。
(mode)
(1) The electronic component according to the present disclosure includes an insulator having a pair of principal surfaces facing each other and a side surface connecting the principal surfaces, and electrodes formed in each of at least three layers within the insulator. a capacitor in which elements are connected in series, the capacitor is arranged in a position where electrodes formed in each layer overlap each other when viewed in plan from the stacking direction, and the capacitor has an electrode formed in at least one layer; In this case, at least one wiring pattern is electrically connected, and at least a part of the wiring pattern protrudes from one side of the overlapping electrodes when viewed in plan from the stacking direction.
 これにより、本開示に係る電子部品は、少なくとも3層の各々に形成される電極により構成される素子が直列に接続されたキャパシタで、重なる電極の一辺からはみ出している配線パターンと接続している電極を有しているので、電子部品でのキャパシタが占める面積の割合を抑えつつ、製造するプロセスにおいてキャパシタの容量の変動を低減できる。 Accordingly, the electronic component according to the present disclosure is a capacitor in which elements constituted by electrodes formed in at least three layers are connected in series, and connected to a wiring pattern protruding from one side of the overlapping electrodes. Since the capacitor has an electrode, it is possible to suppress the proportion of the area occupied by the capacitor in the electronic component and reduce fluctuations in capacitance of the capacitor during the manufacturing process.
 (2)(1)に記載の電子部品において、キャパシタは、3層で構成され、第1層目に形成される第1電極と、第2層目に形成され、積層方向から平面視した場合に前記第1電極と重なる第2電極と、第3層目に形成され、積層方向から平面視した場合に前記第2電極と重なる第3電極と、を含み、第3電極に接続される配線パターンの少なくとも一部は、第2電極の一辺からはみ出している。これにより、3層で構成されるキャパシタにおいて、電子部品でのキャパシタが占める面積の割合を抑えつつ、製造するプロセスにおいてキャパシタの容量の変動を低減できる。 (2) In the electronic component described in (1), the capacitor is composed of three layers, including a first electrode formed in the first layer and a second electrode formed in the second layer, when viewed in plan from the stacking direction. a second electrode that overlaps with the first electrode; and a third electrode that is formed in a third layer and overlaps with the second electrode when viewed in plan from the stacking direction, and is connected to the third electrode. At least a portion of the pattern protrudes from one side of the second electrode. As a result, in a capacitor composed of three layers, it is possible to suppress the proportion of the area occupied by the capacitor in the electronic component, and to reduce fluctuations in capacitance of the capacitor during the manufacturing process.
 (3)(2)に記載の電子部品において、キャパシタは、第2電極が第1電極および第3電極に比べて電極の面積が大きい。これにより、第1電極および第3電極の面積でキャパシタの容量が決まる。 (3) In the electronic component described in (2), in the capacitor, the second electrode has a larger electrode area than the first and third electrodes. As a result, the capacitance of the capacitor is determined by the areas of the first electrode and the third electrode.
 (4)(1)~(3)のいずれか1項に記載の電子部品において、配線パターンは、積層方向から平面視した場合に重なる電極の一辺、および当該一辺と対向する辺から一部がはみ出している。これにより、はみ出している方向への配線パターンの面積の変動はキャパシタの容量の変動に寄与しない。 (4) In the electronic component according to any one of (1) to (3), the wiring pattern includes one side of the electrodes that overlap when viewed from the stacking direction, and a portion of the wiring pattern from the side opposite to the one side. It's sticking out. As a result, variations in the area of the wiring pattern in the protruding direction do not contribute to variations in the capacitance of the capacitor.
 (5)(1)~(4)のいずれか1項に記載の電子部品において、絶縁体の側面に設けられる外部電極を、さらに備え、配線パターンは、外部電極と電気的に接続されている。これにより、配線パターンを介して、外部電極から電極に電力を供給できる。 (5) The electronic component according to any one of (1) to (4), further comprising an external electrode provided on a side surface of the insulator, and the wiring pattern is electrically connected to the external electrode. . Thereby, power can be supplied from the external electrode to the electrode via the wiring pattern.
 (6)(1)~(5)のいずれか1項に記載の電子部品において、キャパシタと異なる層に形成されるインダクタを、さらに備え、インダクタは、キャパシタに対して直列に接続される。これにより、電子部品は、インダクタと、キャパシタとで、フィルタ装置を構成することができる。 (6) The electronic component according to any one of (1) to (5) further includes an inductor formed in a different layer from the capacitor, and the inductor is connected in series with the capacitor. Thereby, the electronic component can constitute a filter device with the inductor and the capacitor.
 (7)(1)~(6)のいずれか1項に記載の電子部品において、キャパシタの電極は、積層方向から平面視した場合の形状が矩形形状であり、配線パターンの配線幅は、接続している電極の一辺の長さより短い。これにより、配線パターンを電極に接続する位置の自由度が高くなる。 (7) In the electronic component according to any one of (1) to (6), the electrode of the capacitor has a rectangular shape when viewed from the stacking direction, and the wiring width of the wiring pattern is shorter than the length of one side of the electrode. This increases the degree of freedom in the position where the wiring pattern is connected to the electrode.
 (8)(1)~(6)のいずれか1項に記載の電子部品において、配線パターンの配線幅は、接続している電極の一辺の長さと同じである。これにより、配線パターンを接続した電極の形状が矩形形状となる。 (8) In the electronic component according to any one of (1) to (6), the wiring width of the wiring pattern is the same as the length of one side of the connected electrode. As a result, the shape of the electrode connected to the wiring pattern becomes rectangular.
 (9)(1)~(7)のいずれか1項に記載の電子部品において、キャパシタの電極と、当該電極と接続している配線パターンとを合わせた形状を積層方向から平面視した場合、十字形状またはT字形状である。これにより、配線パターンを電極に接続する位置の自由度が高くなる。 (9) In the electronic component according to any one of (1) to (7), when the combined shape of the electrode of the capacitor and the wiring pattern connected to the electrode is viewed in plan from the stacking direction, It is cross-shaped or T-shaped. This increases the degree of freedom in the position where the wiring pattern is connected to the electrode.
 (10)(6)に記載の電子部品において、インダクタは、第1インダクタと、第1インダクタに対して並列接続する第2インダクタとを有する。これにより、電子部品は、複数のインダクタと、キャパシタとで、フィルタ装置を構成することができる。 (10) In the electronic component described in (6), the inductor includes a first inductor and a second inductor connected in parallel to the first inductor. Thereby, the electronic component can constitute a filter device with a plurality of inductors and a capacitor.
 (11)(10)に記載の電子部品において、第2インダクタは、第1インダクタと磁気結合している。これにより、電子部品は、第1インダクタと第2インダクタとの相互インダクタンスを利用できる。 (11) In the electronic component described in (10), the second inductor is magnetically coupled to the first inductor. Thereby, the electronic component can utilize mutual inductance between the first inductor and the second inductor.
 今回開示された実施の形態はすべての点で例示であって制限的なものではないと考えられるべきである。本発明の範囲は、上記した説明ではなく、請求の範囲によって示され、請求の範囲と均等の意味および範囲内でのすべての変更が含まれることが意図される。 The embodiments disclosed this time should be considered to be illustrative in all respects and not restrictive. The scope of the present invention is indicated by the claims rather than the above description, and it is intended that equivalent meanings and all changes within the scope of the claims are included.
 1a~1c,2d~2f 導体パターン、3 絶縁体、3a~3k 絶縁基板、4a,4b 外部電極、31~37 ビア導体、100 フィルタ装置、C1,C1A,Ca,Cb キャパシタ、C1a,C1b コンデンサ素子、L1,L2 インダクタ。 1a to 1c, 2d to 2f conductor pattern, 3 insulator, 3a to 3k insulating substrate, 4a, 4b external electrode, 31 to 37 via conductor, 100 filter device, C1, C1A, Ca, Cb capacitor, C1a, C1b capacitor element , L1, L2 inductor.

Claims (11)

  1.  互いに対向する1対の主面と前記主面間を結ぶ側面とを有する絶縁体と、
     前記絶縁体内において少なくとも3層の各々に形成される電極により構成される素子が直列に接続されたキャパシタと、を備え、
     前記キャパシタは、
      各々の層に形成される電極が積層方向から平面視した場合に互いに重なる位置に配置され、
      少なくとも1つの層に形成される電極には、少なくとも1つの配線パターンが電気的に接続され、
     前記配線パターンの少なくとも一部が、積層方向から平面視した場合に重なる電極の一辺からはみ出している、電子部品。
    an insulator having a pair of principal surfaces facing each other and a side surface connecting the principal surfaces;
    a capacitor in which elements constituted by electrodes formed in each of at least three layers in the insulator are connected in series,
    The capacitor is
    The electrodes formed in each layer are arranged at positions overlapping each other when viewed from the stacking direction in plan,
    At least one wiring pattern is electrically connected to the electrode formed in at least one layer,
    An electronic component in which at least a portion of the wiring pattern protrudes from one side of overlapping electrodes when viewed from above in a stacking direction.
  2.  前記キャパシタは、3層で構成され、
      第1層目に形成される第1電極と、
      第2層目に形成され、積層方向から平面視した場合に前記第1電極と重なる第2電極と、
      第3層目に形成され、積層方向から平面視した場合に前記第2電極と重なる第3電極と、を含み、
     前記第3電極に接続される前記配線パターンの少なくとも一部は、前記第2電極の一辺からはみ出している、請求項1に記載の電子部品。
    The capacitor is composed of three layers,
    a first electrode formed in the first layer;
    a second electrode formed in a second layer and overlapping the first electrode when viewed in plan from the stacking direction;
    a third electrode formed in a third layer and overlapping with the second electrode when viewed in plan from the stacking direction;
    The electronic component according to claim 1, wherein at least a portion of the wiring pattern connected to the third electrode protrudes from one side of the second electrode.
  3.  前記キャパシタは、前記第2電極が前記第1電極および前記第3電極に比べて電極の面積が大きい、請求項2に記載の電子部品。 The electronic component according to claim 2, wherein in the capacitor, the second electrode has a larger electrode area than the first electrode and the third electrode.
  4.  前記配線パターンは、積層方向から平面視した場合に重なる電極の一辺、および当該一辺と対向する辺から一部がはみ出している、請求項1~請求項3のいずれか1項に記載の電子部品。 The electronic component according to any one of claims 1 to 3, wherein the wiring pattern partially protrudes from one side of the overlapping electrodes when viewed in plan from the stacking direction, and a side opposite to the one side. .
  5.  前記絶縁体の前記側面に設けられる外部電極を、さらに備え、
     前記配線パターンは、前記外部電極と電気的に接続されている、請求項1~請求項4のいずれか1項に記載の電子部品。
    further comprising an external electrode provided on the side surface of the insulator,
    The electronic component according to claim 1, wherein the wiring pattern is electrically connected to the external electrode.
  6.  前記キャパシタと異なる層に形成されるインダクタを、さらに備え、
     前記インダクタは、前記キャパシタに対して直列に接続される、請求項1~請求項5のいずれか1項に記載の電子部品。
    further comprising an inductor formed in a different layer from the capacitor,
    The electronic component according to claim 1, wherein the inductor is connected in series with the capacitor.
  7.  前記キャパシタの電極は、積層方向から平面視した場合の形状が矩形形状であり、
     前記配線パターンの配線幅は、接続している電極の一辺の長さより短い、請求項1~請求項6のいずれか1項に記載の電子部品。
    The electrode of the capacitor has a rectangular shape when viewed in plan from the stacking direction,
    7. The electronic component according to claim 1, wherein the wiring width of the wiring pattern is shorter than the length of one side of the connected electrode.
  8.  前記配線パターンの配線幅は、接続している電極の一辺の長さと同じである、請求項1~請求項6のいずれか1項に記載の電子部品。 The electronic component according to any one of claims 1 to 6, wherein the wiring width of the wiring pattern is the same as the length of one side of the connected electrode.
  9.  前記キャパシタの電極と、当該電極と接続している前記配線パターンとを合わせた形状を積層方向から平面視した場合、十字形状またはT字形状である、請求項1~請求項7のいずれか1項に記載の電子部品。 Any one of claims 1 to 7, wherein the combined shape of the electrode of the capacitor and the wiring pattern connected to the electrode is cross-shaped or T-shaped when viewed in plan from the stacking direction. Electronic components listed in section.
  10.  前記インダクタは、第1インダクタと、前記第1インダクタに対して並列接続する第2インダクタとを有する、請求項6に記載の電子部品。 The electronic component according to claim 6, wherein the inductor includes a first inductor and a second inductor connected in parallel to the first inductor.
  11.  前記第2インダクタは、前記第1インダクタと磁気結合している、請求項10に記載の電子部品。 The electronic component according to claim 10, wherein the second inductor is magnetically coupled to the first inductor.
PCT/JP2023/015175 2022-05-02 2023-04-14 Electronic component WO2023214504A1 (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5920241A (en) * 1997-05-12 1999-07-06 Emc Technology Llc Passive temperature compensating LC filter
JP2005136011A (en) * 2003-10-28 2005-05-26 Kyocera Corp Laminated electronic part
JP2006311203A (en) * 2005-04-28 2006-11-09 Tdk Corp Lc compound component and its manufacturing method
JP2013162013A (en) * 2012-02-07 2013-08-19 Tdk Corp Laminate capacitor

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5920241A (en) * 1997-05-12 1999-07-06 Emc Technology Llc Passive temperature compensating LC filter
JP2005136011A (en) * 2003-10-28 2005-05-26 Kyocera Corp Laminated electronic part
JP2006311203A (en) * 2005-04-28 2006-11-09 Tdk Corp Lc compound component and its manufacturing method
JP2013162013A (en) * 2012-02-07 2013-08-19 Tdk Corp Laminate capacitor

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