WO2023213102A1

WO2023213102A1 - Sampling device, related equipment, and control method

Info

Publication number: WO2023213102A1
Application number: PCT/CN2023/074732
Authority: WO
Inventors: 章文强; 冯君校; 殷士辉; 景蔚亮; 王正波; 廖恒
Original assignee: 华为技术有限公司
Priority date: 2022-05-05
Filing date: 2023-02-07
Publication date: 2023-11-09
Also published as: CN117054750A

Abstract

A sampling device (12), related equipment, and a control method. The sampling device comprises a first sampling plane (122), a first voltage supply circuit (123), X second voltage supply circuits (124), a controller (121), and a reading circuit (125). By means of the property that the polarization direction of each ferroelectric capacitor is reversed according to a certain probability, the probability distribution of a probability event is simulated and a sample of the probability distribution is obtained, so as to implement a sampling operation. Specifically, by adjusting the voltages at two ends of the ferroelectric capacitor, the reversal probability of the polarization direction of the ferroelectric capacitor is the same as the probability of a different outcome that may occur in the probability event, so that whether the different outcome that may occur in the probability event occurs can be determined according to read polarization direction reversal of the ferroelectric capacitor, so as to complete sampling of the probability event. Overhead of the chip area for implementing a sampling operation can be reduced.

Description

Sampling device, related equipment and control method

This application claims priority to the Chinese patent application filed with the China Patent Office on May 5, 2022, with the application number 202210480895.8 and the application title "A sampling device, related equipment and control method", the entire content of which is incorporated by reference. in this application.

Technical field

The present application relates to the field of electronic technology, and in particular, to a sampling device, related equipment and a control method.

Background technique

Probabilistic calculations are widely used in important fields such as image segmentation and medical diagnosis, such as Bayesian network models. However, in large-scale probabilistic models, the dependencies between nodes are very complex and cannot be directly solved by Bayesian formula. Generally, the Markov Chain Monte Carlo (MCMC) method is used. Solve. In the process of solving the probability model using the MCMC method, a large number of conditional probability distributions in the probability model need to be sampled. For the hardware used for calculation, such as a central processing unit (Center Processing Unit, CPU) or a graphics processor (Graphic Processing Unit, GPU). Currently, the sampling circuit used to implement sampling operations requires a large area on the CPU or GPU chip.

However, the current technology has certain limits on chip area. If the chip area remains unchanged, if you want to make the chip have more and stronger functions, you need to pursue integrating more circuits on a chip with a limited area. Or devices, that is to say, the circuits or devices in the chip need to be made smaller and smaller, occupying less area to meet people's demand for chips with more and stronger functions. Therefore, how to provide a sampling device that occupies a smaller area and reduce the chip area overhead of implementing the sampling operation is an issue that needs to be solved urgently.

Contents of the invention

Embodiments of the present application provide a sampling device, related equipment and a control method, which can reduce the cost of chip area for implementing sampling operations.

In a first aspect, embodiments of the present application provide a sampling device, which may include a first sampling plane, a first voltage supply circuit, X second voltage supply circuits, a controller and a reading circuit, where the first sampling plane includes X first ferroelectric capacitors; X is an integer greater than 0; wherein, the first electrode of each of the X first ferroelectric capacitors is connected to the first voltage supply circuit; The first voltage supply circuit is used to provide a first voltage to the first electrode of each of the first ferroelectric capacitors; the second electrode of the x-th first ferroelectric capacitor among the X first ferroelectric capacitors Connected to the x-th second voltage supply circuit among the X second voltage supply circuits; x takes 1, 2,...,X, and the x-th second voltage supply circuit is used to provide The second electrode of the first ferroelectric capacitor provides a second voltage; the controller is respectively connected to the first voltage supply circuit and the X second voltage supply circuits; the controller is used to: receive a sampling instruction , the sampling instructions include X probability values; based on the X probability values, the first voltage supply circuit and/or the X second voltage supply circuits are respectively controlled to adjust the first voltage and/or the a second voltage; the voltage difference between the first voltage and the second voltage on the xth first ferroelectric capacitor corresponds to the xth probability value among the X probability values; the reading circuit for reading the polarization direction of each first ferroelectric capacitor; wherein the polarization direction of each first ferroelectric capacitor is based on the voltage difference between the first voltage and the second voltage. Flip between the first polarization direction and the second polarization direction.

In the embodiment of the present application, a sampling device based on a ferroelectric capacitor is provided. When the sampling device is used to implement a sampling operation, it can reduce the occupation of the chip area by the sampling circuit or the sampling device, so that the chip can have more spare area for integration. Other functional circuits or devices meet people's needs for chips with more and stronger functions. Specifically, for example, when using the sampling device to sample a certain random event (such as event A), the occurrence process of the event A can be simulated through a ferroelectric capacitor to determine whether multiple different results corresponding to the event A occur, to achieve For the purpose of sampling event A, firstly, by adjusting the voltage difference across the ferroelectric capacitor, the probability of flipping the polarization direction of different ferroelectric capacitors corresponds to the probability of different outcomes of event A, so that the polarization direction of the ferroelectric capacitor can be adjusted according to Flip with a certain probability; then read the flipping situation of the polarization direction of the ferroelectric capacitor. Because there is generally a mutually exclusive relationship between different results of actual events, a ferroelectric whose polarization direction flips can be determined based on the reading results. capacitor, it is considered that a certain result of event A corresponding to the ferroelectric capacitor occurs, and is used as the sampling result of this sampling. In summary, when the ferroelectric capacitor-based sampling device provided by this application is used in the actual sampling process, the polarization direction flip probability distribution of each ferroelectric capacitor is consistent with the probability distribution of different outcomes of probabilistic events, and the judgment of the above sampling results The logic also conforms to the development law of actual events. Therefore, the sampling device provided by this application can be used in the actual sampling process. As far as the current technology is concerned, the area of the ferroelectric capacitor is smaller than the area of the register. Therefore, unlike the solution that uses more registers to implement the sampling operation, the sampling device provided by this application also occupies a smaller area of the chip; in addition, this application provides In the sampling device, the upper electrodes or lower electrodes (i.e., the first electrode) of the Reduce the chip area occupied by the sampling device.

In a possible implementation, the first electrode or the second electrode of each first ferroelectric capacitor is connected to the reading circuit.

In the embodiment of the present application, the reading circuit in the sampling device can be connected to the upper electrode or the lower electrode of the ferroelectric capacitor, so that the circuit implementation of the sampling device is more flexible, thereby improving the applicability of the sampling device.

In a possible implementation, the first electrode includes an upper electrode or a lower electrode, the second electrode includes an upper electrode or a lower electrode, and the first electrode and the second electrode are different electrodes.

In the embodiment of the present application, the first electrode of the ferroelectric capacitor in the sampling device can be the upper electrode or the lower electrode, and the first electrodes of the multiple ferroelectric capacitors in the sampling plane can be connected to the first voltage supply circuit, that is, That is, the first voltage supply circuit can be shared by the upper electrodes of multiple ferroelectric capacitors or the lower electrodes of multiple ferroelectric capacitors, which makes the implementation of the sampling device more flexible, thus improving the applicability of the sampling device.

In a possible implementation, the first voltage supply circuit includes a first field effect transistor or a first digital-to-analog conversion circuit; and the X second voltage supply circuits include second field effect transistors or second digital-to-analog conversion circuits. conversion circuit.

In the embodiment of the present application, the first voltage supply circuit in the sampling device may be a field effect transistor or a digital-to-analog conversion circuit; the second voltage supply circuit may be a field effect transistor or a digital-to-analog conversion circuit, that is, That is to say, the two sets of voltage supply circuits included in the sampling device can both be field effect transistors or digital-to-analog conversion circuits, or they can be a combination of field effect transistors and digital-to-analog conversion circuits. Since the field effect transistors and digital-to-analog conversion circuits have simple structures and small areas, the sampling device uses them to provide voltages to the upper and lower electrodes at both ends of the ferroelectric capacitor, which can not only further reduce the chip area overhead.

In a possible implementation, the first voltage supply circuit or the X second voltage supply circuits are integrated in the reading circuit.

In the embodiment of the present application, the voltage supply circuit used in the sampling device to provide voltage for the upper electrode or the lower electrode of the ferroelectric capacitor can be integrated in the reading circuit, and part of the structure in the reading circuit is reused, thereby reducing the number of circuits. overhead, further reducing the chip area occupied by the sampling device.

In a possible implementation, the first sampling plane further includes X second ferroelectric capacitors, the first electrode of each first ferroelectric capacitor and the X second ferroelectric capacitors the first electrode of each second ferroelectric capacitor, to The first voltage supply circuit is connected in parallel and shares the first voltage supply circuit.

In the embodiment of the present application, the same sampling plane in the sampling device may include multiple groups (for example, Y group) of ferroelectric capacitors, and the first electrodes (such as the upper electrode) of multiple ferroelectric capacitors in different groups may share the same power supply. voltage circuit (i.e., the first voltage supply circuit), that is to say, a voltage supply circuit can provide voltage to the first electrodes of X*Y ferroelectric capacitors in the same sampling plane, which greatly reduces the number of voltage supply circuits. quantity, further reducing the chip area occupied by the sampling device.

In a possible implementation, the first sampling plane further includes X second ferroelectric capacitors, and the second electrode of the xth first ferroelectric capacitor is connected to the The second electrode of the x-th second ferroelectric capacitor in the capacitor is connected in parallel with the x-th second voltage supply circuit, sharing the x-th second voltage supply circuit; x is 1 or 2 ,...,X.

In the embodiment of the present application, the same sampling plane in the sampling device may include multiple groups (for example, Y group) of ferroelectric capacitors, and the second electrodes of multiple ferroelectric capacitors with the same serial number in different groups (when x has the same value). (the following electrodes) can share the same voltage supply circuit (i.e., the x-th second voltage supply circuit), that is to say, one voltage supply circuit can provide voltage for the second electrodes of Y ferroelectric capacitors in the same sampling plane. , which greatly reduces the number of voltage supply circuits and further reduces the chip area occupied by the sampling device.

In a possible implementation, the sampling device further includes a second sampling plane, the second sampling plane includes X third ferroelectric capacitors, each of the X third ferroelectric capacitors The first electrode of the electric capacitor and the first electrode of each of the first ferroelectric capacitors are connected in parallel with the first voltage supply circuit and share the first voltage supply circuit.

In the embodiment of the present application, the sampling device includes multiple sampling planes (for example, S sampling planes), and the first electrodes (such as the upper electrodes) of multiple groups of ferroelectric capacitors in different sampling planes can share the same voltage supply circuit ( That is, the first voltage supply circuit), that is to say, a voltage supply circuit can provide voltage for the first electrodes of S*Y ferroelectric capacitors in different sampling planes; in addition, if the ferroelectric capacitors in different groups in the same sampling plane When the electric capacitors can also share the voltage supply circuit, then one voltage supply circuit can provide voltage for the first electrodes of S*X*Y ferroelectric capacitors in different sampling planes, which greatly reduces the number of voltage supply circuits. Further reducing the chip area occupied by the sampling device.

In a possible implementation, the sampling device further includes a second sampling plane, the second sampling plane includes X third ferroelectric capacitors, and the second second sampling plane of the The electrode and the second electrode of the x-th third ferroelectric capacitor among the X third ferroelectric capacitors are connected in parallel with the x-th second voltage supply circuit, sharing the second voltage supply Circuit; x takes 1, 2,...,X.

In the embodiment of the present application, the sampling device includes multiple sampling planes (for example, S sampling planes), and the second electrodes of multiple ferroelectric capacitors with the same serial number (when x has the same value) in different groups in different sampling planes (as follows) electrodes) can share the same voltage supply circuit (i.e., the x-th second voltage supply circuit), that is to say, one voltage supply circuit can provide voltage for the second electrodes of S*Y ferroelectric capacitors in different sampling planes. , when the first electrodes of multiple groups of ferroelectric capacitors with the same serial number in the same sampling plane can also share the voltage supply circuit, then one of the voltage supply circuits can be S*X*Y ferroelectric capacitors in different sampling planes. The first electrode of the capacitor provides voltage, which greatly reduces the number of voltage supply circuits and further reduces the chip area occupied by the sampling device.

In a possible implementation, the first electrode or the second electrode of each first ferroelectric capacitor is connected to the reading circuit in a parallel manner and shares the reading circuit; The first sampling plane also includes X second ferroelectric capacitors, the first electrode or the first electrode of each of the first ferroelectric capacitors and the X second ferroelectric capacitors. The second electrode is connected in parallel with the reading circuit and shares the reading circuit.

In the embodiment of the present application, the same sampling plane in the sampling device may include multiple groups of ferroelectric capacitors, and the first electrodes or second electrodes (such as the upper electrodes) of multiple ferroelectric capacitors in the same group may share the same reading circuit. (i.e. reading circuit), And multiple ferroelectric capacitors in different groups can also share the reading circuit. That is to say, one reading circuit can read the reversal of polarization directions of X*Y ferroelectric capacitors in the same sampling plane. This greatly reduces the number of reading circuits and further reduces the chip area occupied by the sampling device.

In a possible implementation, the sampling device further includes a second sampling plane, the second sampling plane includes X third ferroelectric capacitors, each of the first ferroelectric capacitors and the The first electrode or the second electrode of each third ferroelectric capacitor among the three ferroelectric capacitors is connected in parallel with the reading circuit and shares the reading circuit.

In the embodiment of the present application, the sampling device may include multiple sampling planes (for example, S sampling planes). Each sampling plane may include one or more groups of ferroelectric capacitors (for example, Y group). Different groups in different sampling planes may The first electrode or the second electrode (such as the upper electrode) of multiple ferroelectric capacitors can share the same reading circuit (i.e., reading circuit). In other words, a reading circuit can convert S* in different sampling planes. The flipping conditions of the polarization directions of Y ferroelectric capacitors are read out; and if the ferroelectric capacitors in different groups of the same sampling plane can also share the reading, then a reading circuit can read out the polarization directions of the Y ferroelectric capacitors. The flipping conditions of the polarization directions of S*X*Y ferroelectric capacitors are read out, which greatly reduces the number of reading circuits and further reduces the chip area occupied by the sampling device.

In a possible implementation, when the voltage difference between the first voltage of the first electrode and the second voltage of the second electrode is greater than or equal to a preset threshold, the corresponding first The polarization direction of the ferroelectric capacitor flips between the first polarization direction and the second polarization direction; when the voltage difference is less than the preset threshold, the polarization direction of the corresponding first ferroelectric capacitor The polarization direction is flipped between the first polarization direction and the second polarization direction according to the probability value corresponding to the voltage difference.

In the embodiment of the present application, the sampling device includes the reversal of the polarization direction of one or more ferroelectric capacitors, which is related to the voltage difference across the ferroelectric capacitor. When the voltage difference reaches a certain value, the polarization direction of the ferroelectric capacitor will Flip; when the voltage difference fails to reach a certain value, the polarization direction of the ferroelectric capacitor will flip according to the probability value corresponding to the specific value of the voltage difference.

In the second aspect, embodiments of the present application provide a sampling device, which may include a first voltage supply circuit, X second voltage supply circuits, a controller and a reading circuit. The sampling device is coupled to the first sampling plane, so The first sampling plane includes X first ferroelectric capacitors; X is an integer greater than 0; wherein the first electrode of each first ferroelectric capacitor in the voltage circuit connection; the first voltage supply circuit is used to provide a first voltage to the first electrode of each of the first ferroelectric capacitors; the x-th first ferroelectric capacitor among the The second electrode of the electric capacitor is connected to the x-th second voltage supply circuit among the X second voltage supply circuits; x is 1, 2,...,X, and the x-th second voltage supply circuit is used for Provide a second voltage to the second electrode of the x-th first ferroelectric capacitor; the controller is connected to the first voltage supply circuit and the X second voltage supply circuit respectively; the control The device is configured to: receive a sampling instruction, the sampling instruction including X probability values; respectively control the first voltage supply circuit and/or the X second voltage supply circuits to adjust the first voltage supply circuit based on the X probability values. voltage and/or the second voltage; the voltage difference between the first voltage and the second voltage on the x-th first ferroelectric capacitor corresponds to the x-th probability value among the X probability values ; The reading circuit is used to read the polarization direction of each of the first ferroelectric capacitors; wherein the polarization direction of each of the first ferroelectric capacitors is based on the first voltage and the second The voltage difference flips between the first polarization direction and the second polarization direction.

In a possible implementation, the first sampling plane further includes X second ferroelectric capacitors, the first electrode of each first ferroelectric capacitor and the X second ferroelectric capacitors The first electrode of each second ferroelectric capacitor is connected in parallel with the first voltage supply circuit and shares the first voltage supply circuit.

In a possible implementation, the sampling device is also coupled to a second sampling plane, the second sampling plane includes X third ferroelectric capacitors, each of the X third ferroelectric capacitors The first electrode of the ferroelectric capacitor and the first electrode of each first ferroelectric capacitor are connected in parallel with the first voltage supply circuit and share the first voltage supply circuit.

In a possible implementation, the sampling device is also coupled to a second sampling plane, the second sampling plane includes X third ferroelectric capacitors, and the xth first ferroelectric capacitor has The two electrodes are connected to the x-th second voltage supply circuit in parallel with the second electrode of the x-th third ferroelectric capacitor among the Voltage circuit; x takes 1, 2,...,X.

In a possible implementation, when the voltage difference between the first voltage and the second voltage is greater than or equal to a preset threshold, the polarization direction of the corresponding first ferroelectric capacitor is in the first polarization direction. flip between the direction and the second polarization direction; when the voltage difference is less than the preset threshold, the polarization direction of the corresponding first ferroelectric capacitor is in the first polarization direction according to the probability value corresponding to the voltage difference. flip between the polarization direction and the second polarization direction.

In a third aspect, embodiments of the present application provide a ferroelectric capacitor array, which may include a first sampling plane, the first sampling plane including X first ferroelectric capacitors, the first sampling plane being coupled to a sampling device, The sampling device includes a first voltage supply circuit, X second voltage supply circuits, a controller and a reading circuit; X is an integer greater than 0; wherein each of the X first ferroelectric capacitors The first electrode of the electric capacitor is connected to the first voltage supply circuit; the first voltage supply circuit is used to provide a first voltage to the first electrode of each of the first ferroelectric capacitors; the X The second electrode of the x-th first ferroelectric capacitor among the first ferroelectric capacitors is connected to the x-th second voltage supply circuit among the X second voltage supply circuits; x is 1, 2,...,X, The x-th second voltage supply circuit is used to provide a second voltage to the second electrode of the x-th first ferroelectric capacitor; the controller is respectively connected to the first voltage supply circuit and the X second voltage supply circuits are connected; the controller is configured to: receive sampling instructions, the sampling instructions include X probability values; respectively control the first voltage supply circuit and/or the X second voltage supply circuits adjust the first voltage and/or the second voltage; the voltage difference between the first voltage and the second voltage on the xth first ferroelectric capacitor corresponds to The x-th probability value among the X probability values; the reading circuit is used to read the polarization direction of each first ferroelectric capacitor; wherein, the polarization direction of each first ferroelectric capacitor The direction is flipped between a first polarization direction and a second polarization direction based on a voltage difference between the first voltage and the second voltage.

In a possible implementation, the ferroelectric capacitor array further includes a second sampling plane, the second sampling plane includes X third ferroelectric capacitors, each of the X third ferroelectric capacitors The first electrodes of the three ferroelectric capacitors and the first electrodes of each of the first ferroelectric capacitors are connected to the first voltage supply circuit in a parallel manner, and share the first voltage supply circuit.

In a possible implementation, the ferroelectric capacitor array further includes a second sampling plane, the second sampling plane includes X third ferroelectric capacitors, and the xth first ferroelectric capacitor is The second electrode and the second electrode of the x-th third ferroelectric capacitor among the X third ferroelectric capacitors are connected in parallel with the x-th second voltage supply circuit, sharing the second Voltage supply circuit; x takes 1, 2,...,X.

In a possible implementation, the ferroelectric capacitor array further includes a second sampling plane, the second sampling plane includes X third ferroelectric capacitors, each of the first ferroelectric capacitors and the The first electrode or the second electrode of each of the third ferroelectric capacitors is connected in parallel with the reading circuit and shares the reading circuit.

In a fourth aspect, embodiments of the present application provide a control method that is applicable to the sampling device provided in any one of the above first and second aspects and possible implementations in combination with the first and second aspects. The method includes: controlling the first voltage supply circuit and/or the X second voltage supply circuits by the controller to perform a first adjustment on the first voltage and/or the second voltage, and each The polarization direction of the first ferroelectric capacitor is initialized to the first polarization direction; Receive sampling instructions through the controller, the sampling instructions include X probability values; and based on the X probability values, respectively control the first voltage supply circuit and/or the X second voltage supply circuits to The first voltage and or the second voltage are subjected to a second adjustment, and the voltage difference between the first voltage and the second voltage on the x-th first ferroelectric capacitor corresponds to one of the X probability values. The xth probability value of The voltage difference between the first voltage and the second voltage flips from the first polarization direction to the second polarization direction.

In the embodiment of the present application, before using the above-mentioned sampling device for sampling, the polarization direction of the ferroelectric capacitor can be initialized to return it to the initial state (that is, the first polarization direction, or the second polarization direction). ); Because there is generally a mutually exclusive relationship between different results of actual events, after completing the sampling, the reading circuit only needs to read the state of the polarization direction of the ferroelectric capacitor after this sampling to determine the ferroelectric one by one. Whether the polarization direction of the capacitor has flipped (it can be determined one by one in a certain order or randomly), and the polarization direction of the first flipped ferroelectric capacitor can be used as the sampling result; if the last ferroelectric capacitor is determined, If the polarization direction of the previous ferroelectric capacitor has not flipped, it is not necessary to judge whether the polarization direction of the last ferroelectric capacitor has flipped. It can be considered that the polarization direction of the last ferroelectric capacitor has flipped and is regarded as Sampling results. If the polarization direction of the ferroelectric capacitor is not initialized before sampling, additional storage devices are needed to record and save the polarization direction state of the ferroelectric capacitor before sampling, and the polarization direction state of the ferroelectric capacitor after this sampling needs to be stored. Only by comparing the polarization direction state of the ferroelectric capacitor with the state before this sampling recorded and saved by the storage device can it be determined whether the polarization direction of the ferroelectric capacitor has flipped; in addition, since the flipping probability of the polarization direction of the ferroelectric capacitor is different from that of the ferroelectric capacitor The current state is also related. If initialization is not performed, during the actual process of sampling and adjusting the voltage across the ferroelectric capacitor, it may appear that the upper electrode voltage of some ferroelectric capacitors is greater than the lower electrode voltage, and that of some ferroelectric capacitors The upper electrode voltage is smaller than the lower electrode voltage, and the circuit complexity is higher, which may require a specific voltage supply circuit to achieve. Therefore, when the sampling device provided by the embodiment of the present application uses the control method provided by the present application to implement the sampling operation, the sampling logic can be simplified, the requirements of the sampling device for the voltage supply circuit can be reduced, and the applicability of the sampling device can be improved.

In a possible implementation, the method further includes: when the first sampling plane also includes X second ferroelectric capacitors, reading each of the second ferroelectric capacitors through the reading circuit. The polarization direction of the capacitor.

In the embodiment of the present application, when the above-mentioned sampling device is used for sampling, ferroelectric capacitors of multiple groups (for example, Y group) in the same sampling plane can be used for sampling at the same time. That is to say, one sampling plane can be used to sample a certain probability. Events are sampled Y times at the same time, which can effectively improve sampling efficiency.

In a possible implementation, when the sampling device further includes a second sampling plane, and the second sampling plane includes X third ferroelectric capacitors, each of the third ferroelectric capacitors is read through the reading circuit. Three polarization directions of ferroelectric capacitors.

In the embodiment of the present application, when the above-mentioned sampling device is used for sampling, after one sampling is completed through a certain sampling plane, subsequent sampling can be performed through other sampling planes first. Considering that the number of flips of the polarization direction of the ferroelectric capacitor is limited, Using different sampling planes for sampling can allocate the sampling workload on different sampling planes, so that the number of flips of different ferroelectric capacitors can be balanced, thereby extending the service life of the sampling device and reducing maintenance costs. Of course, different sampling planes can also be used for sampling at the same time, which can effectively improve the sampling efficiency.

In a fifth aspect, embodiments of the present application provide a semiconductor chip that includes the sampling device provided in any one of the above-mentioned first and second aspects and possible implementations in combination with the first and second aspects.

In a sixth aspect, embodiments of the present application provide an electronic device, which includes a sampling device provided in any one of the above-mentioned first and second aspects and possible implementations in combination with the first and second aspects; the The electronic device further includes a main processor coupled to the sampling device, and the main processor is used to send sampling instructions to the sampling device to and receive the sampling results of the sampling device; the electronic device also includes a memory, which is used to save the program instructions and data necessary for the operation of the main processor and the sampling device; the electronic device may also include a communication interface for the Electronic devices communicate with other devices or communication networks.

In a seventh aspect, embodiments of the present application provide an electronic device that has the function of implementing any of the control methods of the sampling device in the fourth aspect. This function can be implemented by hardware, or it can be implemented by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above functions.

In an eighth aspect, the present application provides a computer storage medium that stores a computer program. When the computer program is executed by a sampling device, the sampling device can perform the control described in any one of the fourth aspects. Method flow.

In a ninth aspect, embodiments of the present application provide a computer program. The computer program includes instructions. When the computer program is implemented by any of the above-mentioned first and second aspects and possible implementation methods combining the first and second aspects, When the provided sampling device is executed, the sampling device can execute the control method flow described in any one of the above fourth aspects.

In a tenth aspect, the present application provides a chip system, which includes the sampling device provided in any one of the above-mentioned first and second aspects and possible implementations in combination with the first and second aspects. In a possible design, the chip system further includes a processor and a memory, and the memory is used to save necessary or relevant program instructions and data of the sampling device and the processor. The chip system may be composed of chips, or may include chips and other discrete devices.

In an eleventh aspect, the present application provides a system-on-a-chip SoC chip. The SoC chip includes the sampling device provided in any one of the above-mentioned first and second aspects and possible implementations combined with the first and second aspects, and The sampling device is coupled with a processor, internal memory and external memory, and the internal memory and external memory are used to save necessary or relevant program instructions and data of the sampling device and the processor. The SoC chip can be composed of chips, or can also include chips and other discrete devices.

Description of the drawings

In order to more clearly explain the technical solutions in the embodiments of the present application or the background technology, the drawings required to be used in the embodiments or the background technology of the present application will be described below. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without exerting creative efforts.

Figure 1a is a schematic structural diagram of an electronic device provided by an embodiment of the present application.

Figure 1b is a schematic structural diagram of another electronic device provided by an embodiment of the present application.

Figure 1c is a schematic diagram of the overall structure of a sampling device provided by an embodiment of the present application.

Figure 1d is a schematic diagram of the overall structure of another sampling device provided by an embodiment of the present application.

Figure 2a is a schematic diagram of a sampling device suitable for two-class probability distribution provided by an embodiment of the present application.

Figure 2b is a schematic diagram of a sampling device suitable for multi-class probability distribution provided by an embodiment of the present application.

Figure 3a is a schematic three-dimensional structural diagram of a sampling device provided by an embodiment of the present application.

Figure 3b is a schematic three-dimensional structural diagram of another sampling device provided by an embodiment of the present application.

Figure 3c is a schematic three-dimensional structural diagram of another sampling device provided by an embodiment of the present application.

Figure 3d is a schematic three-dimensional structural diagram of another sampling device provided by an embodiment of the present application.

Figure 3e is a schematic three-dimensional structural diagram of another sampling device provided by an embodiment of the present application.

Figure 4 is a schematic flowchart of the control method of the sampling device provided by the embodiment of the present application.

Detailed ways

The embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application.

The terms “first”, “second”, “third” and “fourth” in the description, claims and drawings of this application are used to distinguish different objects, rather than to describe a specific sequence. . Furthermore, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally also includes steps or units that are not listed, or optionally also includes Other steps or units inherent to such processes, methods, products or devices.

Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in one or more embodiments of the present application. The appearances of this phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those skilled in the art understand, both explicitly and implicitly, that the embodiments described herein may be combined with other embodiments.

First, some terms used in this application are explained to facilitate understanding by those skilled in the art.

(1) Ferroelectric Cap (FeC), its core technology is ferroelectric crystal material. The working principle of ferroelectric crystals is: when an electric field is added to the ferroelectric crystal material, the central atom in the crystal will move along the direction of the electric field with a certain probability and unify into one direction to reach a stable state (that is, the polarization direction); where, Each free-floating central atom in the crystal has only two stable states. One is the first polarization direction (or the second polarization direction), which can be recorded as "0" in logic, and the other is the second polarization direction ( Or the first polarization direction) can be recorded as "1". The central atom can stay in a stable state for more than 100 years at normal temperature and without an electric field. Compared with the pseudo-random number generation circuit and the register circuit mainly used in the sampling circuit in the prior art to implement the sampling operation, the ferroelectric capacitor has a smaller area and smaller volume. Therefore, in the embodiment of the present application, the polarization direction of the ferroelectric capacitor is probabilistically flipped according to the electric field, and the polarization direction of one or more ferroelectric capacitors is flipped with probability by adjusting the voltage at both ends of the ferroelectric capacitor. As the probability corresponding to one or more possible outcomes of a probabilistic event, a sampling circuit or device based on ferroelectric capacitors can be obtained, thereby reducing the cost of chip area.

(2) Bayesian Network is a graphical probability network based on probabilistic reasoning, including nodes and directed edges connecting the nodes. Among them, nodes represent random variables, and directed edges between nodes represent the mutual relationships between nodes (generally from parent nodes to their child nodes). Conditional probabilities are used to express the strength of node relationships. Nodes without parent nodes can use prior probabilities. express. Bayesian networks are based on Bayesian formulas and are suitable for expressing and analyzing uncertain and probabilistic events, and can make inferences from incomplete, imprecise or uncertain knowledge or information. However, as the scale of the probability model becomes larger and larger, the dependencies between the various nodes in the model become more complex and cannot be solved directly through the Bayesian formula. The Markov chain Monte Carlo method is generally used to solve the problem. The method requires sampling a large number of conditional probabilities, but the sampling circuit in the existing technology occupies a large chip area. In the embodiment of the present application, a sampling circuit or sampling device based on ferroelectric capacitor is proposed, which can be applied to the process of using MCMC to sample and solve a large number of conditional probabilities in probability models, and can reduce the chip area required by the sampling circuit or sampling device. occupancy, it should be noted that this application implements The sampling circuit or sampling device provided in the example can also be applied to other machine learning sampling scenarios, and is not specifically limited here.

(3) Markov Chain Monte Carlo (MCMC) is a random sampling method that is widely used in fields such as machine learning, deep learning, and natural language processing. MCMC is used to do some complex tasks. The approximate solution of operations is the basis for solving many complex models or algorithms. In the embodiment of the present application, a ferroelectric capacitor-based sampling circuit or sampling device is proposed, which can be applied to the process of using MCMC to sample and solve a large number of conditional probabilities in probability models, and can reduce the impact of the sampling circuit or sampling device on the chip area. occupied.

First, analyze and propose the specific technical problems to be solved by this application. In the existing technology, mainstream sampling operations are mostly implemented by using a cumulative probability distribution sampling circuit, which includes a pseudo-random number generation circuit, a cumulative probability distribution function storage table, a search circuit and other sub-circuits.

The above-mentioned scheme of implementing sampling operation based on cumulative probability distribution sampling circuit has the following shortcomings:

The overall circuit occupies a large area of the chip. In the existing technology, circuits that implement sampling operations include pseudo-random number generation circuits, cumulative probability distribution function storage tables, search circuits and other sub-circuits. Among them, the pseudo-random number generation circuit generally uses a linear feedback shift register (Linear Feedback Shift Register). , LFSR) circuit implementation. The number of registers in an LFSR circuit is generally called the number of stages of the LFSR. The sequence of data currently stored in each register in an LFSR circuit is generally called a state. An n-level LFSR circuit has the most Stores 2 ⁿ -1 states. After the LFSR circuit outputs one bit and the feedback function adds one bit (usually the rightmost (end) digital output, and then the data of the overall LFSR circuit moves one bit to the right), the LFSR circuit becomes Moved to the next state. For example, a 3-level LFSR circuit includes 3 linear feedback shift registers, which can store up to 3 bits of data at the same time and store up to 2 ³ -1, that is, 7 states. When the sampling operation needs to generate more random numbers, the LFSR circuit requires more registers. In addition, the LFSR circuit also has a certain periodicity. Since an n-level LFSR circuit can only traverse 2 ⁿ -1 states at most, when the LFSR circuit shifts to a certain extent, repeated states may occur. In order to ensure sampling The randomness and sampling accuracy also require the LFSR circuit to include a larger number of registers. In addition to the pseudo-random number generation circuit, the cumulative probability distribution function storage table generally uses multi-bit registers. It can be seen that both the pseudo-random number generation circuit and the cumulative probability distribution function storage table in the cumulative probability distribution sampling circuit require a large number of registers. As far as the current technology is concerned, the register area is large, which leads to the need for a cumulative probability distribution sampling circuit. It occupies a larger chip area, resulting in a larger overall chip area overhead.

In order to solve the problem in the prior art that the cumulative probability distribution sampling circuit is used to implement the sampling operation, which occupies a large chip area and causes a large overhead in the overall chip area, this application comprehensively considers the shortcomings of the prior art and wants to solve the problem. Technical issues include the following:

Design sampling circuits or sampling devices that occupy less chip area. In the embodiment of the present application, a sampling device is proposed that uses the polarization direction of a ferroelectric capacitor to flip according to a certain probability to implement a sampling operation. Specifically, the sampling device is used to sample a certain random event (such as event A). When, the occurrence process of the event A can be simulated through the ferroelectric capacitor to determine whether various different results corresponding to the event A occur, so as to achieve the purpose of sampling the event A. First, the voltage across the ferroelectric capacitor can be adjusted to make multiple The probability of flipping the polarization direction of the ferroelectric capacitor is the same as the probability of different possible outcomes of event A. Therefore, based on the read flip of the polarization direction of the ferroelectric capacitor, it can be determined whether the different possible outcomes of event A are occurs to achieve the purpose of sampling. As far as the current technology is concerned, the area of the ferroelectric capacitor is much smaller than that of the register. The sampling circuit or sampling device based on the ferroelectric capacitor provided in the embodiment of the present application can reduce the chip area occupied by the sampling circuit unit. That is to say, the cost of chip area is reduced.

To sum up, in the existing technology, the scheme of using the cumulative probability distribution sampling circuit for sampling will occupy a large chip area. It is difficult to meet people's demand for chips with more and stronger functions. Therefore, the sampling circuit or sampling device provided by this application can be used to solve the above technical problems.

In order to better understand the sampling device provided by the embodiment of the present application, the structure and applicable scenarios of the sampling device provided by the embodiment of the present application will be exemplified below. It can be understood that the structure and application scenarios of the sampling device described in the embodiments of the present application are for the purpose of more clearly illustrating the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided by the embodiments of the present application.

Referring to Figure 1a, Figure 1a is a schematic structural diagram of an electronic device provided by an embodiment of the present application. The electronic device 01 provided by the present application may include one or more main processors 11 and one or more sampling devices 12. Memory (not shown) may be included. The electronic device may be a Subscriber Unit (Subscriber Unit), a Cellular Phone (Cellular Phone), a Smart Phone (Smart Phone), a Personal Computer (Personal Compute, PC), a Personal Digital Assistant (Personal Digital Assistant, PDA) computer, a tablet computer, Handheld devices (Handset), laptop computers (Laptop Computer), Machine Type Communication (MTC) terminals, smart wearable devices, etc.

The main processor 11 may be a central processing unit (CPU), a graphics processing unit (GPU), or a chip with other functions, and is used for sending sampling instructions, receiving sampling results, and other necessary operations. In the embodiment of the present application, the main processor 11 can send a sampling instruction to the controller 121 of the sampling device 12 so that the controller 121 can control the first voltage supply circuit 123 based on the relevant information (such as X probability values) in the sampling instruction. and the second voltage supply circuit 124 adjusts the provided voltage, and sets the polarization direction flip probability of the multiple ferroelectric capacitors in the first sampling plane to the corresponding probability value in the sampling instruction; finally, the main processor 11 can receive and analyze the read The sampling result read by the circuit 125 for the first sampling plane is obtained.

The sampling device 12 includes a controller 121, a first sampling plane 122, a first voltage supply circuit 123, a second voltage supply circuit 124 and a reading circuit 125. Among them, the controller 121 is used to receive the sampling instruction sent by the main processor 11, and control the first voltage supply circuit 123 and the second voltage supply circuit 124 to adjust the provided voltage based on the relevant information included in the sampling instruction; the first sampling plane 122 includes one or more ferroelectric capacitors; the first voltage supply circuit 123 and the second voltage supply circuit 124 respectively provide voltages to the first electrode and the second electrode of the one or more ferroelectric capacitors in the first sampling plane 122, The polarization direction of one or more ferroelectric capacitors can be flipped according to the probability value corresponding to the voltage difference between the two ends; the reading circuit 125 is used to read the polarization direction of the one or more ferroelectric capacitors and send it to the host. Processor 11.

The memory is used to store the preparation data required by the main processor 11 and the sampling device 12 to perform the sampling task (such as the voltage difference and polarization direction reversal probability value mapping table), the intermediate data generated during the sampling process, and the data after the sampling is completed. Result data. Memory can include one or more local memories (Local Memory), one or more registers (Register), one or more first-level caches (L1 Cache), one or more second-level caches (L2 Cache), and various types of Buffer, etc.

In a possible implementation, the sampling device in the electronic device provided by the present application may not include the first sampling plane. See Figure 1b. Figure 1b is a schematic structural diagram of another electronic device provided by an embodiment of the present application. The electronic device 02 provided in this application may include one or more main processors 21, one or more sampling devices 22, and one or more first sampling planes 23, and may also include a memory (not shown in the figure). For the functions and connection relationships of each unit in the electronic device 02 , reference can be made to the relevant description of the electronic device 01 , and will not be described again here.

As for the specific structure of the sampling device provided by this application, please refer to Figure 1c. Figure 1c is a schematic diagram of the overall structure of a sampling device provided by an embodiment of this application. The sampling device 12 may include a controller 121, a first sampling plane 122, The first voltage supply circuit 123, the second voltage supply circuit 124 and the reading circuit 125. Among them, the controller 121 is connected to the first voltage supply circuit 123, the second voltage supply circuit 124 and the reading circuit 125 respectively. The controller 121 is used to receive the data sent by the main processor 11. sampling instructions, and based on the relevant information included in the sampling instructions, control the first voltage supply circuit 123 and the second voltage supply circuit 124 to adjust the provided voltage, and control the reading circuit 125 to read one or more of the first sampling planes The polarization direction of the ferroelectric capacitor; the first sampling plane 122 includes one or more ferroelectric capacitors, the first voltage supply circuit 123 and the second voltage supply circuit 124 are respectively connected to one or more ferroelectric capacitors in the first sampling plane 122 The first electrode and the second electrode of the capacitor are connected to provide voltage to them, so that their polarization directions can be flipped according to the probability value corresponding to the voltage difference between the two ends; the reading circuit 125 is connected to one or more of the first sampling planes The first electrode or the second electrode of the ferroelectric capacitor is connected.

In a possible implementation manner, the sampling device provided by the embodiment of the present application may not include the first sampling plane. See Figure 1d. Figure 1d is a schematic diagram of the overall structure of another sampling device provided by the embodiment of the present application. The device 22 may include a controller 221, a first voltage supply circuit 222, a second voltage supply circuit 223, and a reading circuit 224. The functions and connection relationships of each unit in the sampling device 22 may refer to the relevant description of the sampling device 12 above. I won’t go into details here.

In order to facilitate understanding of the structure of the sampling device and the principle of implementing the sampling operation provided by the embodiments of the present application, the following first takes a sampling circuit or sampling device suitable for two-class probability distribution as an example for further illustrative explanation. Referring to Figure 2a, Figure 2a is a schematic diagram of a sampling device suitable for two-class probability distribution provided by an embodiment of the present application. The two-class sampling device may include two voltage supply circuits (i.e., a first voltage supply circuit and X The second voltage supply circuit, X is 1), a reading circuit and a sampling plane (the framed part of (a) in Figure 2a), the sampling plane includes a ferroelectric capacitor (i.e. X first ferroelectric capacitors , T is used as a representation of the first voltage supply circuit, and a digital-to-analog conversion circuit is used as a representation of the second voltage supply circuit. The drain of the field effect transistor T is connected to the upper electrode of the ferroelectric capacitor (that is, corresponding to the first electrode), and is connected to the read The digital-to-analog conversion circuit is connected to the lower electrode (corresponding to the second electrode) of the ferroelectric capacitor. Among them, the gate of the field effect transistor T is connected to the control line (CL) and the source of the field effect transistor T. Connected to the Bit Line (BL), the on or off of the field effect transistor T can be controlled by adjusting the voltage on the control line, and the voltage value provided by the field effect transistor T can be adjusted by adjusting the voltage on the bit line side. , the storage node (Storage Node, SN) is a logical node assumed for the convenience of understanding. The voltage at this node is the voltage value V _SN provided by the field effect transistor T. The word line (World Line, WL) and The lower electrode of the ferroelectric capacitor is connected. When there are multiple ferroelectric capacitors in the sampling device, the specific ferroelectric capacitor can be determined through the bit line and word line. In the device shown in (a) in Figure 2a, the structure of the ferroelectric capacitor is generally upper electrode-ferroelectric material-lower electrode. The basic principle of the sampling device is that the reversal probability of the polarization direction of the ferroelectric capacitor is affected by the voltage pulse amplitude. Value modulation, as shown in (b) of Figure 2a, the probability of the polarization direction flip of the ferroelectric capacitor can be modulated by applying different voltages on both ends of the ferroelectric capacitor. For example, the probability corresponding to the voltage difference Vc is p0, through By adjusting the size of Vc, the probability p0 of the polarization direction flip of the ferroelectric capacitor can be modulated from 0 to 1. For example, an event A corresponds to two different outcomes, established or not (or yes or no, or can or cannot), as shown in (c) in Figure 2a. The probability of being true is p0, and the probability of not being true is p1. The probability of the polarization direction flip of the capacitor is modulated to p0. When the reading circuit reads the polarization direction flip of the ferroelectric capacitor, if it is found that the polarization direction has flipped, it can be considered that the event A in the current sampling is established, otherwise it is not established. It can be understood that the above-mentioned first voltage supply circuit can be a field effect transistor, a digital-to-analog conversion circuit, or other circuits that can provide voltage; the above-mentioned second voltage supply circuit can be a digital-to-analog conversion circuit, or it can be A field effect transistor, or other circuit that can provide voltage, is not specifically limited here. It should also be noted that the above-mentioned first electrode of the ferroelectric capacitor may be an upper electrode or a lower electrode, and the above-mentioned second electrode may be an upper electrode or a lower electrode, as long as the first electrode of the ferroelectric capacitor and the third electrode are The two electrodes only need to be different electrodes, and there is no specific limitation here.

In a possible implementation, the first voltage supply circuit or the second voltage supply circuit can be integrated into the reading circuit, that is to say, the reading circuit can be used for the upper electrode or the lower electrode of the ferroelectric capacitor. Supply voltage, after the ferroelectric capacitor flips the polarization direction according to the probability value corresponding to the voltage difference between the two ends, the reading circuit then flips the polarization direction of the ferroelectric capacitor. Read out, further reducing the sampling device’s occupation of the overall chip area.

Then, a sampling circuit or a sampling device suitable for multi-class probability distribution is taken as an example for further illustrative explanation. Please refer to Figure 2b. Figure 2b is a schematic diagram of a sampling device suitable for multi-class probability distribution provided by an embodiment of the present application. The multi-class sampling device may include a field effect transistor T (i.e., a first voltage supply circuit), a A reading circuit, multiple digital-to-analog conversion circuits (i.e., a first ferroelectric capacitor), the controller in the sampling device is connected to the first voltage supply circuit, the second voltage supply circuit and the reading circuit respectively (not shown in the figure). For the convenience of understanding, a field effect transistor is used in the figure. T is used as a representation of the first voltage supply circuit, and X digital-to-analog conversion circuits are used as a representation of ) is connected to the reading circuit, and multiple digital-to-analog conversion circuits are connected to the lower electrodes (corresponding to the second electrodes) of multiple ferroelectric capacitors. Among them, the gate of the field effect transistor T is connected to the control line (Control Line, CL), the source of the field effect transistor T is connected to the bit line (Bit Line, BL). The on or off of the field effect transistor T can be controlled by adjusting the voltage on the control line, and can be adjusted by adjusting the voltage on the bit line side. The voltage value that the field effect transistor T can provide. The storage node (Storage Node, SN) is a logical node assumed for the convenience of understanding. The voltage at this node is the voltage value V _SN provided by the field effect transistor T. , the word line (World Line, WL) is connected to the lower electrode of the ferroelectric capacitor, and the specific ferroelectric capacitor can be determined through the bit line and word line. In the device shown in (a) in Figure 2b, the basic principle of the sampling device is that the flip probability of the polarization direction of each ferroelectric capacitor is modulated by the voltage pulse amplitude. As shown in (b) in Figure 2b, different iron The probability of flipping the polarization direction of an electric capacitor can be modulated by applying different voltages to both ends of different ferroelectric capacitors. This process can be referred to the two-class probability distribution scenario, which will not be described again here. For example, an event A corresponds to multiple different outcomes. For example, event A includes a0, a1, a2,..., aS-1, a total of S different outcomes. As shown in (c) in Figure 2b, the probability of a0 occurring is p0, a1 The probability of occurrence is p1, the probability of aS-1 occurring is pS-1, and the probability of flipping the polarization directions of multiple ferroelectric capacitors (C0 to CS-1) is modulated to p0, p1,..., pS-1 respectively; After using the reading circuit to read the polarization direction reversal of the ferroelectric capacitor, because there is generally a mutually exclusive relationship between different results of actual events, each ferroelectric capacitor can be determined one by one based on the reading results of the reading circuit. Whether the capacitor has flipped (it can be determined one by one in a certain order, or it can be determined one by one randomly), and the polarization direction of the first ferroelectric capacitor that flips is used as the sampling result; if the last ferroelectric capacitor is determined, the previous If there is still no polarization direction flip of the ferroelectric capacitor, it is not necessary to determine whether the polarization direction of the last ferroelectric capacitor has flipped. It can be considered that the polarization direction of the last ferroelectric capacitor has flipped, and it is used as the sampling result. For example, if it is first discovered that the polarization direction of a certain ferroelectric capacitor (such as C1) has flipped, it can be considered that the result a1 of event A occurred in the current sampling; if the polarization direction of C1 has not flipped, it can be judged that Whether the polarization direction of C2 is reversed. If the polarization direction of C2 is reversed, it is considered that the result of event A in this sampling is a2; if the polarization directions of the first S-2 ferroelectric capacitors are not reversed, it is considered that The result of event A in this sampling is aS-1. It can be understood that the above-mentioned first voltage supply circuit can be a field effect transistor, a digital-to-analog conversion circuit, or other circuits that can provide voltage; the above-mentioned second voltage supply circuit can be a digital-to-analog conversion circuit, or it can be Field effect transistors, or other circuits that can provide voltage, and different second voltage supply circuits corresponding to different ferroelectric capacitors can provide the same voltage or different voltages, which are not specifically limited here. It should be noted that the first electrode of the ferroelectric capacitor may be an upper electrode or a lower electrode, and the second electrode may be an upper electrode or a lower electrode, as long as the first electrode and the second electrode of the ferroelectric capacitor are The electrodes only need to be different electrodes, and are not specifically limited here. It should also be noted that the above-mentioned first voltage supply circuit or second voltage supply circuit can be integrated into the reading circuit, that is to say, the reading circuit can supply voltage to the upper electrode or the lower electrode of the ferroelectric capacitor. . It should also be noted that the sampling circuit or sampling device suitable for multi-class probability distribution provided in the embodiment of the present application is also suitable for two-class probability distribution scenarios. It only needs to adjust the voltage across a certain ferroelectric capacitor to make it extremely The probability of flipping the direction corresponds to the probability of binary classification, and other ferroelectric capacitors do not need to participate in sampling.

This application also provides a sampling device with a three-dimensional structure based on a ferroelectric capacitor array, which can combine multiple applicable Sampling circuits based on multi-class probability distributions form a three-dimensional array. Please refer to Figure 3a. Figure 3a is a schematic diagram of a three-dimensional structure of a sampling device provided by an embodiment of the present application. The sampling device may include multiple sampling planes (i.e., multiple first sampling planes). sampling plane), each sampling plane includes multiple ferroelectric capacitors (for example, X row * Y column, X and Y are greater than 0), the sampling device includes multiple field effect transistors (ie, multiple first voltage supply circuits), A plurality of digital-to-analog conversion circuits (ie, multiple sets of A reading circuit is connected (not shown in the figure). For better understanding, the field effect transistor T is used as a diagram of the first voltage supply circuit, and a digital-to-analog conversion circuit is used as a diagram of the second voltage supply circuit. The field effect transistor T is used as a diagram of the first voltage supply circuit. The drain of the effect transistor T is connected to the upper electrodes of the ) is connected to the lower electrode (corresponding to the second electrode) of the ferroelectric capacitor, and CL can be perpendicular to BL. It is understandable that the above-mentioned first voltage supply circuit and the second voltage supply circuit may be field effect transistors, digital-to-analog conversion circuits, or other circuits that can provide voltage, which will not be described again here. It should also be noted that the first electrode and the second electrode of the ferroelectric capacitor may be the upper electrode or the lower electrode, as long as the first electrode and the second electrode are different electrodes, which will not be described again here. The sampling device with a three-dimensional structure can make full use of the advantages of the array structure and increase the sampling speed.

In a possible implementation, the second electrodes of different ferroelectric capacitors in rows with the same serial number in different sampling planes of the above-mentioned sampling device with a three-dimensional structure can share a second voltage supply circuit. See Figure 3b. Figure 3b is An embodiment of the present application provides a schematic diagram of the three-dimensional structure of another sampling device, in which, among multiple sampling planes (including the first sampling plane and the second sampling plane), the ferroelectric capacitor in the xth row in a certain plane is connected to another The x-th row of ferroelectric capacitors with the same value in a plane can respectively share a set of digital-to-analog conversion circuits (i.e., the second electrode of the x-th first ferroelectric capacitor and the X-th third ferroelectric capacitor The second electrode of the x-th third ferroelectric capacitor is connected in parallel with the x-th second voltage supply circuit and shares the second voltage supply circuit), and the controller in the sampling device is respectively connected with the The first voltage supply circuit, the second voltage supply circuit and the reading circuit are connected (not shown in the figure). In the structure of the sampling device, by sharing the second voltage supply circuit, the number of components in the device is reduced. Therefore, the sampling device can further reduce the occupation of the chip area.

In a possible implementation, in a certain sampling plane of the above-mentioned sampling device with a three-dimensional structure, the first electrodes of ferroelectric capacitors in different columns can share the first voltage supply circuit. See Figure 3c. Figure 3c is a diagram of this invention. A schematic diagram of the three-dimensional structure of another sampling device provided by the embodiment of the application, in which, among multiple sampling planes (including the first sampling plane and the second sampling plane), the *Y ferroelectric capacitors may be connected in parallel to the first voltage supply circuit, thereby sharing the first voltage supply circuit (the first electrode of each first ferroelectric capacitor and each of the X second ferroelectric capacitors). The first electrode of a second ferroelectric capacitor is connected in parallel with the first voltage supply circuit). In the structure of the sampling device, by sharing the first voltage supply circuit, the number of components in the device is reduced. Therefore, the sampling device can further reduce the occupation of the chip area. Optionally, the first voltage supply circuit can also be shared between different sampling planes to provide voltage (i.e., first voltage) for the first electrode of the ferroelectric capacitor in each plane. See Figure 3d. Figure 3d is an embodiment of the present application. A schematic diagram of the three-dimensional structure of another sampling device is provided, in which the first electrodes of multiple ferroelectric capacitors in different sampling planes are connected in parallel to the drain of the field effect transistor T (i.e., the first voltage supply circuit). The control in the sampling device The devices are respectively connected to the first voltage supply circuit, the second voltage supply circuit and the reading circuit (not shown in the figure). Therefore, the sampling device can further reduce the occupation of chip area.

In a possible implementation, in the above-mentioned sampling device with a three-dimensional structure, the first voltage supply circuit, the second voltage supply circuit and the reading circuit can be shared between different sampling planes. See Figure 3e. Figure 3e is a diagram of the present invention. The application embodiment provides a schematic diagram of a three-dimensional structure of another sampling device, in which multiple ferroelectric capacitors at different sampling planes (including the first sampling plane and the second sampling plane) are connected in parallel to a field effect transistor T (i.e., the first supply On the drain of the voltage circuit), the ferroelectric capacitors in the same row in different sampling planes are connected in parallel to a set of digital-to-analog conversion circuits (i.e., X second voltage supply circuits), and the ferroelectric capacitors in different sampling planes are connected to a reading On the circuit, the controller in the sampling device is connected to the first voltage supply circuit, the second voltage supply circuit and the Read circuit connections (not shown). Therefore, the sampling device can further reduce the occupation of chip area.

The following uses the scenario of Bayesian network inference calculation as an example to illustrate the control method of the device with a three-dimensional structure in the above sampling device.

Referring to Figure 4, Figure 4 is a schematic flow chart of the control method of the sampling device provided by the embodiment of the present application. Taking Bayesian network inference calculation as an example, starting from node 0 (ie, input node) of the Bayesian network until Up to the output node, the following steps S400 to S402 are included:

Step S400: Initialize the ferroelectric capacitor.

Specifically, the ferroelectric capacitance C in a certain sampling plane or all sampling planes in the sampling device in Figure 3a can be initialized to an initial state (such as the first polarization direction or the second polarization direction, which can respectively correspond to "0 ” or “1”), for example, initialize the ferroelectric capacitor of the first sampling plane to the initial state “0”. Alternatively, you can first determine the current state of the ferroelectric capacitor (“0” or “1”) , and then combine the characteristics of the ferroelectric capacitor to probabilistically flip the polarization direction, and adjust the voltage difference between the upper and lower electrodes of the ferroelectric capacitor to complete the initialization. For example, when the "0" state of the ferroelectric capacitor is used as the initial state, the voltage can be adjusted so that The upper electrode voltage is less than the lower electrode voltage, and the voltage difference meets the flip threshold.

Optionally, after initializing the state of the ferroelectric capacitor, the voltage of the digital-to-analog conversion circuit connected to the lower electrode of the ferroelectric capacitor can be set to a constant greater than 0, for example, it can be set to half of the write voltage (Vw /2), to prevent the ferroelectric capacitor from accidentally flipping when the field effect transistor is turned on.

Optionally, the initialization of the ferroelectric capacitor may be performed before the controller of the sampling device receives the sampling instruction from the main processor, or may be performed after receiving the sampling instruction. Among them, the sampling instructions can include probability values that different results of each node in the Bayesian network may occur, and the probability values can be expressed based on byte status and byte length. For example, the byte status representing a certain probability value P is 00011101. (29 after converting from binary to decimal), and its byte length is 8 (which can represent 256 states), then the probability value P can be 29/256, which is about 11.33%.

Step S401: Adjust the voltage across the ferroelectric capacitor according to the probability value of the n-th node and the sampling result of the parent node.

Specifically, after the initialization is completed, the voltage difference between the upper and lower electrodes of the ferroelectric capacitor is adjusted again, so that the polarization direction flip probability corresponding to the adjusted voltage difference is consistent with the probability value of various results at node 0 of the Bayesian network. Equally, optionally, assuming that the upper electrode of the ferroelectric capacitor is connected to the field effect transistor, the field effect transistor can be turned on by applying a voltage to CL, thereby precharging the logic node SN to Vpre (that is, the voltage that the field effect transistor can provide value), and adjust the voltage value provided by the digital-to-analog conversion circuit connected to the other end of the ferroelectric capacitor of the first sampling plane. Among them, in Bayesian network, the parent node is the previous node of the current node. If the current node is an input node, it has no parent node. For the sampling of non-input nodes, the polarization direction flip probability of the ferroelectric capacitor can be determined based on the sampling results of the parent node and the conditional probability between the node and the parent node.

Step S402: Read the sampling result of the n-th node.

Specifically, after applying voltage to both ends of the ferroelectric capacitor, the polarization direction reversal of the ferroelectric capacitor can be read out through the reading circuit, because there is generally a mutually exclusive relationship between different results of actual events. Therefore, based on the reading results of the reading circuit, it can be determined one by one whether each ferroelectric capacitor has flipped (it can be determined one by one in a certain order, or it can be determined one by one randomly), and the polarization of the first ferroelectric capacitor that has flipped can be determined one by one. The direction is used as the sampling result of Bayesian network node 0; if the polarization direction of the previous ferroelectric capacitor has not flipped when the last ferroelectric capacitor is determined, there is no need to determine whether the polarization direction of the last ferroelectric capacitor has occurred. Flip, it can be considered that the polarization direction of the last ferroelectric capacitor has flipped, and is used as the sampling result of Bayesian network node 0. Understandably, the ferroelectric capacitors of all columns in the first sampling plane can participate in the sampling of node 0. When all columns participate in sampling at the same time, it can be considered that node 0 has been sampled Y times. After completing the sampling of node 0, the second sampling plane can be used to sample node 1 of the Bayesian network. Optionally, the ferroelectric capacitance of the second sampling plane can be initialized to the initial state first (or When initializing the first sample plane, initialize them together), and then adjust the field effect transistor or digital-to-analog conversion circuit according to the conditional probability value of the Bayesian network (that is, when different results occur at node 0, the probability of different results at node 1) The voltage makes the flip probability of the polarization direction of the ferroelectric capacitor equal to the conditional probability value corresponding to node 1. Finally, the reading circuit is used to read the sampling result of node 1. Understandably, subsequent nodes in the Bayesian network also undergo the process of initializing the initial state, adjusting the voltage difference, and reading the flip situation, until the sampling of the output node is completed, and finally the final result is output, thereby determining the relationship between the output node and the input node. relation.

It should be noted that the flip probability of the polarization direction of the ferroelectric capacitor is related to the current state of the ferroelectric capacitor. For example, if the current state of the ferroelectric capacitor is "0", the voltage of its upper electrode needs to be set to be greater than that of the lower electrode. Voltage can make the state "0" of the polarization direction flip to the state "1" of the polarization direction with a certain probability; if the current state of the ferroelectric capacitor is "1", the voltage of its upper electrode needs to be set to be smaller than that of the lower electrode Voltage can make the state "1" in the polarization direction flip to the state "0" in the polarization direction with a certain probability. Therefore, if the state "0" is positioned as the initial state, when initializing the ferroelectric capacitor, the upper electrode voltage can be set to be smaller than the lower electrode voltage, so that the voltage difference meets the threshold; and if the state "1" is positioned as the initial state, When initializing the ferroelectric capacitor, the upper electrode voltage can be set to be greater than the lower electrode voltage, so that the voltage difference meets the threshold.

It should also be noted that in the above scenario using Bayesian network inference calculation as an example, considering that the number of flips of the polarization direction of the ferroelectric capacitor is limited, different sampling planes are used to sample different nodes of the Bayesian network. The load can be shared on different sampling planes so that the number of flips of different ferroelectric capacitors can be balanced, thereby extending the service life of the sampling device and reducing maintenance costs. Understandably, all the sampling planes in the above-mentioned sampling device can also be sampled sequentially for the nodes in the Bayesian network at the same time, or the same sampling plane can be continuously used for sampling until the polarization direction of the ferroelectric capacitor in the sampling plane is When the number of flips reaches the upper limit, sampling will be performed through other sampling planes, which are not specifically limited here. In addition, the number of possible results in different nodes of the Bayesian network can be the same or different. Generally speaking, the number of rows of ferroelectric capacitors in the sampling plane will be greater than or equal to the number of possible results in the node, that is, That is, when the ferroelectric capacitors in the same row correspond to different results at different nodes, the number of rows may be greater than the number of results at the nodes, and the extra ferroelectric capacitors do not need to participate in the sampling of the current node. Optionally, when obtaining the probability value of the Bayesian network, you can determine how many rows of ferroelectric capacitors in a column need to be used, so that you can turn off the voltage at one end of the ferroelectric capacitors in other rows so that they do not participate in sampling. When reading, the reading circuit may also only read the reversal of the polarization direction of the ferroelectric capacitor participating in the sampling.

Understandably, when the sampling operation is implemented through the above-mentioned sampling device, the essence of the implementation of the sampling device is to use the characteristics of the polarization direction of one or more ferroelectric capacitors to flip according to a certain probability to simulate the occurrence process of a probabilistic event and determine the event. Whether corresponding multiple different results occur, thereby realizing the sampling operation, which is different from the existing technology scheme that uses a large number of registers to complete the sampling operation. As far as the current technology is concerned, the area of the ferroelectric capacitor is much smaller than that of the register. The sampling circuit or sampling device based on ferroelectric capacitors in the embodiments of the present application can reduce the chip area occupied by the sampling circuit unit, that is, reduce the cost of the chip area.

This application also provides a semiconductor chip, which includes the sampling device provided in all the above embodiments of this application. It can be understood that, regarding the functions and functions of each part of the sampling device, reference can be made to the specific implementation manners in the embodiments shown in FIGS. 1 a to 4 above, and will not be described again here.

This application also provides an electronic device, which includes the sampling device provided in all the above embodiments of this application. It can be understood that, regarding the functions and functions of each part of the sampling device, reference can be made to each of the above-mentioned Figures 1a to 4. The specific implementation manner in the embodiment will not be described again here. Optionally, the electronic device may also include a communication interface for the electronic device to communicate with other devices or communication networks.

This application also provides an electronic device, which has the function of implementing any of the above control methods of the sampling device. This function can be implemented by hardware, or it can be implemented by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above functions.

The present application provides a computer storage medium. The computer storage medium stores a computer program. When the computer program is executed by a sampling device, the sampling device can execute the above control method process.

The present application provides a computer program. The computer program includes instructions. When the computer program is executed by a sampling device, the sampling device can execute the above control method process.

This application provides a chip system, which includes any of the above sampling devices. In a possible design, the chip system further includes a processor and a memory, and the memory is used to save necessary or relevant program instructions and data of the sampling device and the processor. The chip system may be composed of chips, or may include chips and other discrete devices.

This application provides a system-on-chip SoC chip. The SoC chip includes the sampling device provided by any of the above implementations, a processor coupled to the sampling device, an internal memory, and an external memory. The SoC chip can be composed of chips, or can also include chips and other discrete devices.

It should be noted that the connection relationships involved in this embodiment, such as series connection or parallel connection, refer to electrical connections, which may not only be directly connected through wires, but may also be coupled through other electrical methods.

In the above embodiments, each embodiment is described with its own emphasis. For parts that are not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments. As mentioned above, the above embodiments are only used to illustrate the technical solution of the present invention, but not to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the foregoing. The technical solutions described in each embodiment may be modified, or some of the technical features may be equivalently replaced; however, these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of each embodiment of the present invention.

Claims

A sampling device, characterized in that the sampling device includes a first sampling plane, a first voltage supply circuit, X second voltage supply circuits, a controller and a reading circuit, and the first sampling plane includes X second voltage supply circuits. A ferroelectric capacitor; X is an integer greater than 0;

Wherein, the first electrode of each first ferroelectric capacitor among the X first ferroelectric capacitors is connected to the first voltage supply circuit; the first voltage supply circuit is used to the first electrode of the capacitor provides a first voltage;

The second electrode of the x-th first ferroelectric capacitor among the X first ferroelectric capacitors is connected to the x-th second voltage supply circuit among the X second voltage supply circuits; x is 1, 2,... ..., X, the x-th second voltage supply circuit is used to provide a second voltage to the second electrode of the x-th first ferroelectric capacitor;

The controller is connected to the first voltage supply circuit and the X second voltage supply circuits respectively; the controller is used to: receive a sampling instruction, the sampling instruction includes X probability values; based on the X The probability value controls the first voltage supply circuit and/or the X second voltage supply circuits to adjust the first voltage and/or the second voltage respectively; the x-th first ferroelectric capacitor has The voltage difference between the first voltage and the second voltage corresponds to the x-th probability value among the X probability values;

The reading circuit is used to read the polarization direction of each of the first ferroelectric capacitors; wherein the polarization direction of each of the first ferroelectric capacitors is based on the first voltage and the second voltage. The voltage difference flips between the first polarization direction and the second polarization direction.
The device of claim 1, wherein the first electrode or the second electrode of each first ferroelectric capacitor is connected to the reading circuit.
The device according to any one of claims 1-2, wherein the first electrode includes an upper electrode or a lower electrode, the second electrode includes an upper electrode or a lower electrode, and the first electrode is connected to the upper electrode or the lower electrode. The second electrode is a different electrode.
The device according to any one of claims 1 to 3, characterized in that the first voltage supply circuit includes a first field effect transistor or a first digital-to-analog conversion circuit; and the X second voltage supply circuits include The second field effect transistor or the second digital-to-analog conversion circuit.
The device according to any one of claims 1 to 4, characterized in that the first voltage supply circuit or the X second voltage supply circuits are integrated in the reading circuit.
The device according to any one of claims 1 to 5, wherein the first sampling plane further includes X second ferroelectric capacitors, and the first electrode of each first ferroelectric capacitor The first electrode of each second ferroelectric capacitor in the X second ferroelectric capacitors is connected in parallel with the first voltage supply circuit and shares the first voltage supply circuit.
The device according to any one of claims 1 to 6, wherein the first sampling plane further includes X second ferroelectric capacitors, and the second second ferroelectric capacitor of the The electrode and the second electrode of the x-th second ferroelectric capacitor among the X second ferroelectric capacitors are connected in parallel with the x-th second voltage supply circuit, sharing the x-th second ferroelectric capacitor. Two voltage supply circuits; x takes 1, 2,...,X.
The device according to any one of claims 1 to 7, wherein the sampling device further includes a second sampling plane, the second sampling plane includes X third ferroelectric capacitors, and the X third ferroelectric capacitors Each of the third ferroelectric capacitors in the three ferroelectric capacitors The first electrode and the first electrode of each first ferroelectric capacitor are connected in parallel to the first voltage supply circuit and share the first voltage supply circuit.
The device according to any one of claims 1 to 8, wherein the sampling device further includes a second sampling plane, the second sampling plane includes X third ferroelectric capacitors, and the xth The second electrode of the first ferroelectric capacitor and the second electrode of the x-th third ferroelectric capacitor among the X third ferroelectric capacitors are connected in parallel with the x-th second voltage supply The circuit connection shares the second voltage supply circuit; x is 1, 2,...,X.
The device according to any one of claims 1 to 9, wherein the first electrode or the second electrode of each first ferroelectric capacitor is connected in parallel with the reading circuit. connection, sharing the reading circuit; the first sampling plane also includes X second ferroelectric capacitors, each of the first ferroelectric capacitors and each of the X second ferroelectric capacitors. The first electrode or the second electrode of the capacitor is connected in parallel with the reading circuit and shares the reading circuit.
The device according to any one of claims 1 to 10, wherein the sampling device further includes a second sampling plane, the second sampling plane includes X third ferroelectric capacitors, each of the third A ferroelectric capacitor and the first electrode or the second electrode of each third ferroelectric capacitor in the X third ferroelectric capacitors are connected in parallel with the reading circuit, sharing the reading circuit Take the circuit.
The device according to any one of claims 1 to 11, characterized in that when the voltage difference between the first voltage and the second voltage is greater than or equal to a preset threshold, the corresponding first ferroelectric capacitor The polarization direction flips between the first polarization direction and the second polarization direction; when the voltage difference is less than the preset threshold, the polarization direction of the corresponding first ferroelectric capacitor is in accordance with the The probability value corresponding to the voltage difference is flipped between the first polarization direction and the second polarization direction.
A sampling device, characterized in that the sampling device includes a first voltage supply circuit, X second voltage supply circuits, a controller and a reading circuit, the sampling device is coupled to a first sampling plane, the first The sampling plane includes X first ferroelectric capacitors; X is an integer greater than 0;

Wherein, the first electrode of each first ferroelectric capacitor among the X first ferroelectric capacitors is connected to the first voltage supply circuit; the first voltage supply circuit is used to the first electrode of the capacitor provides a first voltage;

The second electrode of the x-th first ferroelectric capacitor among the X first ferroelectric capacitors is connected to the x-th second voltage supply circuit among the X second voltage supply circuits; x is 1, 2,... ..., X, the x-th second voltage supply circuit is used to provide a second voltage to the second electrode of the x-th first ferroelectric capacitor;

The controller is connected to the first voltage supply circuit and the X second voltage supply circuits respectively; the controller is used to: receive a sampling instruction, the sampling instruction includes X probability values; based on the X The probability value controls the first voltage supply circuit and/or the X second voltage supply circuits to adjust the first voltage and/or the second voltage respectively; the x-th first ferroelectric capacitor has The voltage difference between the first voltage and the second voltage corresponds to the x-th probability value among the X probability values;

The reading circuit is used to read the polarization direction of each of the first ferroelectric capacitors; wherein the polarization direction of each of the first ferroelectric capacitors is based on the first voltage and the second voltage. The voltage difference flips between the first polarization direction and the second polarization direction.
A ferroelectric capacitor array, characterized in that the ferroelectric capacitor array includes a first sampling plane, and the first sampling plane The sample plane includes X first ferroelectric capacitors, and the first sampling plane is coupled to a sampling device. The sampling device includes a first voltage supply circuit, an integer greater than 0;

Wherein, the first electrode of each first ferroelectric capacitor among the X first ferroelectric capacitors is connected to the first voltage supply circuit; the first voltage supply circuit is used to the first electrode of the capacitor provides a first voltage;

The second electrode of the x-th first ferroelectric capacitor among the X first ferroelectric capacitors is connected to the x-th second voltage supply circuit among the X second voltage supply circuits; x is 1, 2,... ..., X, the x-th second voltage supply circuit is used to provide a second voltage to the second electrode of the x-th first ferroelectric capacitor;

The controller is connected to the first voltage supply circuit and the X second voltage supply circuits respectively; the controller is used to: receive a sampling instruction, the sampling instruction includes X probability values; based on the X The probability value controls the first voltage supply circuit and/or the X second voltage supply circuits to adjust the first voltage and/or the second voltage respectively; the x-th first ferroelectric capacitor has The voltage difference between the first voltage and the second voltage corresponds to the x-th probability value among the X probability values;

The reading circuit is used to read the polarization direction of each of the first ferroelectric capacitors; wherein the polarization direction of each of the first ferroelectric capacitors is based on the first voltage and the second voltage. The voltage difference flips between the first polarization direction and the second polarization direction.
A control method for a sampling device, characterized in that the method is applicable to the sampling device according to any one of claims 1 to 13, and the method includes:

The controller controls the first voltage supply circuit and/or the X second voltage supply circuits to perform a first adjustment on the first voltage and/or the second voltage. The polarization direction of a ferroelectric capacitor is initialized to the first polarization direction;

The controller receives a sampling instruction, the sampling instruction includes X probability values; and based on the X probability values, the first voltage supply circuit and/or the X second voltage supply circuits are respectively controlled to The first voltage and or the second voltage are subjected to a second adjustment, and the voltage difference between the first voltage and the second voltage on the x-th first ferroelectric capacitor corresponds to one of the X probability values. The xth probability value of ;

The polarization direction of each first ferroelectric capacitor of the ferroelectric capacitor is read by the reading circuit; wherein the polarization direction of each first ferroelectric capacitor is based on the first voltage and the first ferroelectric capacitor. The voltage difference between the two voltages flips from the first polarization direction to the second polarization direction.
The method of claim 15, further comprising:

When the first sampling plane further includes X second ferroelectric capacitors, the polarization direction of each second ferroelectric capacitor is read through the reading circuit.
The method according to any one of claims 15-16, characterized in that the method further includes:

When the sampling device further includes a second sampling plane, and the second sampling plane includes X third ferroelectric capacitors, the polarization direction of each of the third ferroelectric capacitors is read through the reading circuit.
An electronic device, characterized in that it includes the sampling device according to any one of claims 1-13, the electronic device further includes a main processor, the main processor is coupled to the sampling device, the The main processor is used to send sampling instructions to the sampling device and receive sampling results from the sampling device; the electronic device also includes a memory, and the memory is used to save necessary information when the main processor and the sampling device are running. Program instructions and data.