TWI822145B - Storage circuit, chip, data processing method, and electronic device - Google Patents

Abstract

A storage circuit, a chip, a data processing method, and an electronic device are disclosed. The storage circuit includes: an input control circuit and a memory. The input control circuit is configured to: receive n input data and an input control signal; perform first data processing on the n input data based on the input control signal to obtain n intermediate data corresponding to the n input data one by one; and write the n intermediate data and a sign signal corresponding to the n input data into the memory; the memory is configured to store the n intermediate data and the sign signal; different values of the sign signal respectively represent different processing processes of the first data processing, and n is a positive integer.

Description

Storage circuits, chips, data processing methods and electronic devices

Embodiments of the present disclosure relate to a storage circuit, a chip, a data processing method and an electronic device. [Related Application Cross-Reference]

This application claims priority from Chinese Patent Application No. 202110750668.8 submitted on July 2, 2021. The disclosure of the above Chinese patent application is hereby cited in its entirety as part of this application.

Cache is a memory located between the chip's Central Processing Unit (CPU) and main memory (Dynamic Random Access Memory, DRAM). It is small in size but runs very fast. , Usually, the cache memory is composed of static memory (Static Random Access Memory, SRAM).

This content is provided to introduce in a simplified form the concepts that are later described in detail in the Detailed Description. This content part is not intended to identify key features or essential features of the claimed technical solution, nor is it intended to be used to limit the scope of the claimed technical solution.

At least one embodiment of the present disclosure provides a storage circuit including: an input control circuit and a memory. The input control circuit is configured to: receive n input data and an input control signal; based on the input control signal, perform first data processing on the n input data to obtain a one-to-one correspondence with the n input data. n intermediate data; writing the n intermediate data and the flag signal corresponding to the n input data into the memory; the memory is configured to store the n intermediate data and the flag signal ; Different values of the flag signal respectively represent different processing processes of the first data processing, and n is a positive integer.

At least one embodiment of the present disclosure further provides a chip including the storage circuit according to any of the above embodiments.

At least one embodiment of the present disclosure also provides a data processing method, applied to the storage circuit according to any embodiment of the present disclosure, including: receiving the n input data and the input control signal; based on the input control signal, Perform the first data processing on the n input data to obtain the n intermediate data corresponding to the n input data; store the n intermediate data and the n input data The corresponding flag signal, where n is a positive integer.

At least one embodiment of the present disclosure also provides an electronic device, including: a processing device. The processing device includes a storage circuit according to any of the above embodiments.

Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although certain embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be construed as limited to the embodiments set forth herein, but rather these embodiments are provided for greater understanding. A thorough and complete understanding of this disclosure. It should be understood that the drawings and embodiments of the present disclosure are for illustrative purposes only and are not intended to limit the scope of the present disclosure.

It should be understood that various steps described in the method implementations of the present disclosure may be executed in different orders and/or in parallel. Furthermore, method embodiments may include additional steps and/or omit performance of illustrated steps. The scope of the present disclosure is not limited in this regard.

As used herein, the term "include" and its variations are open-ended, ie, "including but not limited to." The term "based on" means "based at least in part on." The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; and the term "some embodiments" means "at least some embodiments". Relevant definitions of other terms will be given in the description below. It should be noted that concepts such as “first” and “second” mentioned in this disclosure are only used to distinguish different devices, modules or units, and are not used to limit the order of functions performed by these devices, modules or units. Or interdependence.

It should be noted that the modifications of "one" and "plurality" mentioned in this disclosure are illustrative and not restrictive. Those skilled in the art will understand that unless the context clearly indicates otherwise, it should be understood as "one or Multiple”.

The names of messages or information exchanged between multiple devices in the embodiments of the present disclosure are for illustrative purposes only and are not used to limit the scope of these messages or information.

The study found that the core of anti-aging design of cache memory from the architectural level is to keep the duty cycle of the SRAM unit to store data at 50%. However, the existing technology has a complex structure and requires major changes to the cache memory, resulting in a large area overhead.

At least one embodiment of the present disclosure provides a storage circuit, a chip, a data processing method and an electronic device. The storage circuit includes an input control circuit and a memory. The input control circuit is configured to: receive n input data and input control signals; perform first data processing on the n input data based on the input control signal to obtain n intermediate data corresponding to the n input data; The n intermediate data and the flag signals corresponding to the n input data are written into the memory; the memory is configured to store the n intermediate data and the flag signals. Different values of the flag signal respectively represent different processing processes of the first data processing, and n is a positive integer.

In the storage circuit provided by the embodiment of the present disclosure, the input data is subjected to first data processing based on the input control signal to obtain intermediate data, so that the intermediate data stored in the memory meets the user's needs, for example, in the memory When buffering the memory, the input data stored in the cache memory can be continuously inverted based on this input control signal to ensure that the duty cycle of the data stored in the cache memory is close to or equal to 50%, thereby delaying the The aging of the cache memory effectively reduces the impact of the aging effect on the cache memory, greatly extending the service life of the cache memory and reducing design overhead. In addition, the flag signal is used to identify the type of the first data processing, so that when the intermediate data is output, the intermediate data can be processed based on the flag signal to obtain accurate output data (for example, the same as the input data).

The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings, but the present disclosure is not limited to these specific embodiments. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of some well-known functions and well-known components.

FIG. 1A is a schematic diagram of a storage circuit provided by at least one embodiment of the present disclosure; FIG. 1B is a schematic diagram of another storage circuit provided by at least one embodiment of the present disclosure.

As shown in FIG. 1A , in some embodiments of the present disclosure, the storage circuit 10 includes an input control circuit 100 and a memory 200 . For example, the memory 200 may be a cache memory, such as a first-level cache memory (L1 Cache) or a second-level cache memory (L2 Cache). It should be noted that the memory 200 can also be other types of memory, which is not limited in this disclosure.

For example, the input control circuit 100 is configured to: receive n pieces of input data and input control signals; based on the input control signals, perform first data processing on the n pieces of input data to obtain n intermediate pieces corresponding to the n pieces of input data. Data; write n intermediate data and flag signals corresponding to n input data into the memory 200. The memory 200 is configured to store n intermediate data and flag signals.

For example, different values of the flag signal respectively represent different processing processes of the first data processing, and n is a positive integer.

For example, each input data can be one bit (1 bit) data. For example, each input data can be a binary number, and the value of each input data can be a binary number 1 or 0. It should be noted that the present disclosure is not limited to this, and each input data can also be two-bit data (ie, 2 bit), three-bit data (ie, 3 bit), etc.

For example, in some embodiments, the input control circuit 100 is further configured to: determine a flag signal corresponding to the n input data based on the input control signal.

For example, in some embodiments, the input control signal can be one bit of data (ie, 1 bit), and the flag signal can also be one bit of data. The input control signal and the flag signal can be binary numbers, for example, the input control signal can be 0. or 1, the flag signal can also be 0 or 1. However, the present disclosure is not limited to this. The input control signal and the flag signal can also be two-bit data (i.e. 2 bit), three-bit data (i.e. 3 bit), etc. For example, the input control signal can be 00, 01, 10 or 11, The flag signal can also be 00, 01, 10 or 11. In addition, the input control signals and flag signals can also be ternary numbers, quaternary numbers, or decimal numbers. This disclosure does not limit the specific expression forms and numerical values of the input control signals and flag signals.

For example, in some examples, the flag signal is the same as the input control signal, that is, the input control circuit 100 directly inputs the input control signal into the memory 200 as the flag signal. At this time, if the input control signal is 1, then the flag signal is 1; if the input control signal is 0, the flag signal is 0. For another example, in other examples, the flag signal and the input control signal can be inverted to each other, that is, the input control circuit 100 can perform inversion processing on the input control signal to obtain the flag signal. At this time, if the input control signal is 1, then The flag signal is 0; if the input control signal is 0, the flag signal is 1. It should be noted that in the embodiment of the present disclosure, the input control signal and the flag signal are the same and both are one-bit data for description.

For example, as shown in FIG. 1B , the storage circuit 10 further includes an input control signal generator 300 . The input control signal generator 300 is configured to generate an input control signal and output the input control signal to the input control circuit 100 . In the storage circuit provided in this embodiment, the input control signal is generated by the input control signal generator 300 located outside the memory 200, and based on the input control signal, the first data processing of the input data is controlled to obtain the input control signal. It is simple and flexible. By outputting input control signals that meet different needs through the input control signal generator 300, different data processing of the input data can be implemented to facilitate the realization of different design requirements.

For example, the different values of the flag signal are randomly generated values. The different values of the flag signal include a first value and a second value. The first value may be 1 and the second value may be 0, so the flag signal may be composed of 0 and 1. The constituted random number sequence, for example, the flag signal can be expressed as 00011010110111010010…. For example, on the whole, such as in the entire life cycle of the cache memory, the ratio of the first value and the second value of the flag signal is within a predetermined range, and the predetermined range may be 2/3~3/2. Therefore, In the random number sequence of the flag signal, the ratio between the number of first values and the total number of values in the random number sequence (that is, the number of data (one bit) included in the random number sequence) can be 40% to 60 %. The embodiment of the present disclosure takes the first value as 1 and the second value as 0 as an example for description.

For example, in some embodiments, the flag signal is a 1-bit random number sequence in which the first value and the second value appear randomly, and the change interval between two adjacent values in the flag signal is 1 minute. That is, the change of the flag signal may be: the value of the flag signal is the first value in the first minute, the value of the flag signal is the second value in the second minute, and the value of the flag signal is the second value in the third minute. In the fourth minute the value of the flag signal is the first value, and so on. The duty cycle of this random number sequence is about 50%, that is, the flag signal has the first value 50% of the time during the entire life cycle of the cache memory.

For example, since the input control signal and the flag signal are the same, that is, different values of the input control signal may also include a first value and a second value, on the whole, that is, in the entire life cycle of the cache memory, the third value of the input control signal The ratio of the first value to the second value is within a predetermined range. The input control signal generator 300 can randomly output a value of the input control signal every minute. That is to say, in the first minute, the input control signal generator 300 can output a first value. At this time, the value of the input control signal is The first value, within the second minute, the input control signal generator 300 can output the second value, at this time, the value of the input control signal is the second value, within the third minute, the input control signal generator 300 can output the second value. Two values, in the fourth minute, the input control signal generator 300 can output the first value, and so on. For example, within a period of one month, the ratio of the first value and the second value of the input control signal is within a predetermined range.

It should be noted that the present disclosure does not limit the specific value of the input control signal generated by the input control signal generator 300 in each time period. For example, the input control signal generator 300 can generate the input control signal between the first minute and the tenth minute (or the tenth minute). The first value is output from one minute to sixty minutes, etc.), that is, the value of the input control signal at this time is the first value. The input control signal generator 300 can output the first value from the eleventh minute to the twenty-fifth minute (or the sixth minute). The second value is output within ten minutes to eighty-five minutes, etc.), that is, the value of the input control signal at this time is the second value, and so on. The input control signal generator 300 randomly generates the first value or the second value, as long as it is ensured that overall (during the life cycle of the cache memory), the ratio of the first value and the second value of the input control signal is within a predetermined range. That’s it.

For example, the input control signal can be directly generated using a random number generation unit in the chip, that is, the input control signal generator 300 can be a random number generation unit in the chip.

For example, if the value of the flag signal is the first value, it means that the first data processing is inversion processing; if the value of the flag signal is the second value, it means that the first data processing is maintenance processing. The processing process of the inversion processing and the processing process of the maintenance processing are different. same. That is to say, when the value of the input control signal is the first value, the first data processing is inversion processing; when the value of the input control signal is the second value, the first data processing is the holding process. At this time, the input control signal When the circuit 100 performs the first data processing on n input data based on the input control signal to obtain n intermediate data corresponding to the n input data, the circuit 100 performs the following steps: responding to the value of the input control signal is the first value, the n input data are inverted to obtain n intermediate data; in response to the value of the input control signal being the second value, the n input data are maintained and processed to obtain n intermediate data, That is, n input data are directly used as n intermediate data.

For example, in embodiments of the present disclosure, the intermediate data obtained by inverting the input data is different from the input data, and the intermediate data obtained by maintaining the input data is the same as the input data. Taking the input data as binary data as an example, inversion processing means: if the input data is 1, then the intermediate data obtained after inverting the input data is 0; if the input data is 0, then the input data is inverted. The intermediate data obtained after phase processing is 1; the retention processing means: if the input data is 1, then the intermediate data obtained after the retention processing of the input data is 1; if the input data is 0, the input data is retained. The intermediate data obtained after that is 0.

It should be noted that the present disclosure is not limited to the situation described above. In some embodiments, the value of the flag signal is the first value, indicating that the first data processing is mapping processing based on the first mapping table; the value of the flag signal is the second value. The value indicates that the first data processing is mapping processing based on the second mapping table, and the processing process of the mapping processing based on the first mapping table is different from the processing process of the mapping processing based on the second mapping table. For example, in some embodiments, the input data may be a 2-digit binary number, and the mapping process based on the first mapping table means: map data 00 to data 11, map data 01 to data 10, map data 10 to data 01, map data 11 to data 00; the mapping processing based on the second mapping table means: map data 00 to data 00, map data 01 to data 01, map data 10 to data 10, map data 11 to data 11. At this time, when the input data is 00, the intermediate data obtained after mapping the input data based on the first mapping table is 11, and the intermediate data obtained after mapping the input data based on the second mapping table is 00 .

In addition, in addition to the first value and the second value, the different values of the flag signal may also include a third value, etc., and the embodiments of the present disclosure do not specifically limit the number of different values. For example, the value of the flag signal is the third value, indicating that the first data processing is mapping processing based on the third mapping table; the processing process of the mapping processing based on the third mapping table is different from the processing process of the mapping processing based on the first mapping table. Processing process of mapping processing based on the second mapping table.

For example, as shown in FIG. 1B , the storage circuit 10 further includes an output control circuit 400 . The output control circuit 400 is configured to: read n intermediate data and flag signals from the memory 200; based on the flag signal, perform second data processing on the n intermediate data to obtain n corresponding to the n intermediate data one-to-one. output data; output the n output data.

For example, if the value of the flag signal is a first value, it means that the second data processing is an inversion process; if the value of the flag signal is a second value, it means that the second data processing is a holding process. At this time, when the output control circuit 400 performs the second data processing on the n intermediate data based on the flag signal to obtain n output data corresponding to the n intermediate data, the following steps are performed: In response to the flag signal The value of is the first value, and the n intermediate data are inverted to obtain n output data; the value in response to the flag signal is the second value, and the n intermediate data are maintained and processed to obtain n output data. , that is, directly use n intermediate data as n output data.

For example, n input data and n output data are the same, thereby ensuring that the output data is the same as the input data stored in the memory. For example, if n is 10, and n input data are 0110001010, then n output data are also 0110001010.

FIG. 2 is a schematic structural diagram of a storage circuit provided by some embodiments of the present disclosure.

For example, as shown in FIG. 2 , the input control circuit 100 includes n input sub-circuits 101 corresponding to n input data one-to-one. The memory 200 also includes a write data interface and an output data interface. The write data interface includes n write data bits 201 corresponding to n input sub-circuits. For example, each black rectangular block in Figure 2 represents a Write data bit 201.

For example, the first input terminal of each input sub-circuit 101 receives a corresponding input data Is, the second input terminal of each input sub-circuit 101 receives the input control signal Cs, and the output terminal of each input sub-circuit 101 is connected to the write The corresponding write data bit 201 in the input data interface, each input sub-circuit 101 is configured to perform first data processing on the input data Is based on the input control signal Cs, to obtain the intermediate data Ms corresponding to the input data Is, Intermediate data is written into the write data bit 201. For example, in the example shown in FIG. 2 , the input control signal Cs is directly output to the memory 200 as a flag signal corresponding to the input data.

For example, as shown in Figure 2, the output control circuit 400 includes n output sub-circuits 401 that correspond to n intermediate data in a one-to-one manner, and the output data interface includes n output data bits 202 that correspond to the n output sub-circuits 401 in a one-to-one manner. For example, each rectangular block with diagonal hatching in Figure 2 represents an output data bit 202.

For example, the first input terminal of each output sub-circuit 401 is connected to the corresponding output data bit 202 in the output data interface to receive a corresponding intermediate data Ms, and the second input terminal of each output sub-circuit 401 receives the flag signal Ss. , the output end of each output sub-circuit 401 is used to output the output data Os corresponding to the intermediate data Ms, and each output sub-circuit 401 is configured to perform second data processing on the intermediate data Ms based on the flag signal Ss to obtain the The output data Os corresponding to the intermediate data Ms is output.

It should be noted that in the embodiment of the present disclosure, the first data processing and the second data processing can be any suitable processing, as long as the duty cycle of the data stored in the cache memory is ensured to be close to or equal to 50%. This disclosure does not place specific restrictions on it. The above description regarding the processing of the first data also applies to the processing of the second data unless there is any contradiction.

For example, each input subcircuit 101 includes a mutually exclusive OR gate, which includes two input terminals and one output terminal. At this time, if the value of the input control signal is a first value, that is, 1, then when the input When the data is 1, the intermediate data corresponding to the input data output by the input sub-circuit 101 is 0; when the input data is 0, the intermediate data corresponding to the input data output by the input sub-circuit 101 is 1, thereby realizing the The input data is inverted; if the value of the input control signal is the second value, that is, 0, then when the input data is 1, the intermediate data corresponding to the input data output by the input sub-circuit 101 is 1; when the input data is When 0, the intermediate data corresponding to the input data output by the input sub-circuit 101 is 0, thereby realizing the holding process of the input data.

For example, each output subcircuit 401 includes a mutually exclusive OR gate, which includes two input terminals and one output terminal. At this time, if the value of the flag signal is the first value, that is, 1, then when the intermediate data When is 1, the output data corresponding to the intermediate data output by the output sub-circuit 401 is 0; when the intermediate data is 0, the output data corresponding to the intermediate data output by the output sub-circuit 401 is 1, thereby realizing the intermediate data The data is inverted; if the value of the flag signal is the second value, that is, 0, then when the intermediate data is 1, the output data corresponding to the intermediate data output by the output sub-circuit 401 is 1; when the intermediate data is 0 , the output data corresponding to the intermediate data output by the output sub-circuit 401 is 0, thereby realizing the holding process of the input data.

It should be noted that the present disclosure is not limited to this. The input sub-circuit 101 can also be implemented as an exclusive OR gate, etc. In this case, the first value of the input control signal is 0, and the second value of the input control signal is 1; the output sub-circuit 401 can also be implemented as an exclusive OR gate. In this case, the first value of the flag signal is 0 and the second value of the flag signal is 1. The input subcircuit 101 and/or the output subcircuit 401 can also be implemented as other circuit structures, as long as the above functions can be achieved.

For example, the memory 200 may be a cache memory. As shown in FIG. 2 , the cache memory includes a plurality of data static memories 210 and a plurality of flag static memories 220 . The n intermediate data Ms are respectively stored in corresponding n data static memories 210 among the plurality of data static memories 210 , and the flag signal Ss is stored in a corresponding flag static memory 220 among the plurality of flag static memories 220 .

For example, when the input control circuit 100 performs the step of writing n pieces of intermediate data and the flag signal into the memory 200, it includes performing the following operations: acquiring the first writing address corresponding to the n pieces of input data and the second writing address corresponding to the flag signal. write address; determine n data static memories based on the first write address; determine flag static memories based on the second write address; write n intermediate data into n data static memories in one-to-one correspondence, and Write the flag signal to the flag static memory.

For example, when the output control circuit 400 performs the step of reading n intermediate data and the flag signal, it includes performing the following operations: obtaining the first read address corresponding to the n intermediate data and the second read address corresponding to the flag signal; Based on the first read address, determine n data static memories that store n intermediate data; based on the second read address, determine the flag static memory that stores the flag signal; read n data static memories from the n data static memories Intermediate data, and read the flag signal from the flag static memory.

For example, the first read address and the first write address are the same, and the second read address and the second write address are the same.

For example, multiple data static memories 210 and multiple flag static memories 220 constitute multiple static memory rows, and n data static memories and flag static memories are located in the same static memory row. For example, in some embodiments, n data static memories and flag static memories may constitute a static memory row. At this time, the number of static memories in each static memory row is n+1, and each The static memory row is used to store n intermediate data and a flag signal; in other embodiments, the n data static memories and flag static memories can be part of the static memory in a static memory row, for example, Each static memory row can include (2n+2) static memories. At this time, each static memory row includes 2n data static memories and 2 flag static memories. This disclosure does not limit the number and arrangement of data static memories and flag static memories in the memory 200 .

For example, the number of data static memories and the number of flag static memories in each static memory row are determined by the hardware. For example, in some embodiments, the static memory row includes 64 data static memories and 2 Flag static memory, 32 input data can be written into the 1st to 32nd data static memory at the same time, then the data stored in the 1st to 32nd data static memory corresponds to a flag signal, and the flag signal is One of the two flag static memories stored in the static memory row; the other 32 input data are simultaneously written into the 33rd to 64th data static memories, then the 33rd to 64th data static memories The data stored in each data static memory corresponds to a flag signal, and the flag signal is stored in the other of the two flag static memories in the static memory row.

For example, as shown in Figure 2, the storage circuit 10 also includes an external data writing interface 500 and an external reading data interface 550. The external writing data interface 500 is configured to output n input data Is to the input control circuit 100. The external reading data interface 500 is configured to output n input data Is to the input control circuit 100. The data acquisition interface 550 is configured to receive n pieces of output data Os output from the output control circuit 400 .

In the existing cache memory, each static memory row only includes a plurality of static memories for storing input data. Compared with the existing cache memory, each static memory row provided by the embodiment of the present disclosure has A static memory row may include a plurality of static memories (i.e., data static memory) for storing input data, and at least one static memory (i.e., flag static memory) for storing data corresponding to the input. sign signal.

For example, assume that each static memory line of the cache memory includes n static memories, that is, it can store n bits of data, that is, n input data, and the external data written to the cache memory at the same time or the cache memory At the same time, the output data is also n bits, so the input control circuit 100 includes n mutually exclusive OR gates with two input terminals, and the output control circuit 400 also includes n mutually exclusive OR gates with two input terminals.

In the input control circuit 100, the first input end of each exclusive OR gate is connected to the corresponding bit of the external write data interface 500, and the output end of each exclusive OR gate is connected to the write data interface of the cache memory. The corresponding write data bit 201 is connected, that is, the first input end of the i-th mutex OR gate is connected to the i-th bit of the external write data interface 500, and the output end of the i-th mutex OR gate is connected to the cache memory. The i-th write data bit 201 of the write data interface is connected, and the second input terminals of all mutually exclusive OR gates receive input control signals. When the value of the input control signal is the first value, the input data is inverted and then written into the cache memory. For example, if the input data is 1 (high level), then after passing the mutual exclusion OR gate, the input data is actually input to the cache memory. The intermediate data in the cache memory is 0 (low level); when the value of the input control signal is the second value, the input data remains unchanged and is written into the cache memory. For example, if the input data is 1 (high level) ), then after passing the mutex or gate, the intermediate data actually input to the cache memory is 1 (high level).

For example, in the output control circuit 400, the first input end of each exclusive OR gate is connected to the corresponding output data bit 202 in the output data interface of the cache memory, and the output end of each exclusive OR gate is connected to the external read Connecting the corresponding bits in the data interface 550, the second input terminal of each exclusive OR gate is used to receive the flag signal output by the cache memory (for example, the flag signal can also be output to the output control circuit through an output data bit 202 400), that is, the output terminal of the i-th mutually exclusive OR gate is connected to the i-th bit in the external data reading interface 550, and the first input terminal of the i-th mutually exclusive OR gate is connected to the i-th output of the cache memory. Data bit 202 is connected, and the second input terminal of all exclusive OR gates receives the flag signal.

For example, in the cache memory provided by the embodiment of the present disclosure, a static memory for storing a flag signal is added to record whether the data corresponding to the flag signal is inverted. For example, each static memory line in the original cache memory includes n static memories. After adding the static memory for storing flag signals, each static memory line includes n+1 static memories. When the value of the flag signal is the first value, it means that the data corresponding to the flag signal are all inverted and saved; when the value of the flag signal is the second value, it means that the data corresponding to the flag signal remain in their original state.

Therefore, in the embodiment of the present disclosure, depending on the value of the input control signal, the data written into the cache memory from the external data writing interface 500 is inverted or remains unchanged and stored in the cache memory. The corresponding data is stored in the static memory, and the flag signal corresponding to the data is stored in the flag static memory. The flag signal is used to indicate whether the data stored in the cache memory is inverted. When reading stored data from the cache memory, according to the flag signal corresponding to the data to be read, if the data to be read is inverted, the data is inverted again and output to the external data reading interface 550; If the data to be read is not inverted, the data is directly output to the external data reading interface 550.

Assume that before anti-aging processing is performed on the cache memory, during the life cycle of the cache memory, the duty cycle of a certain static memory in the cache memory to store data is x. Based on the embodiments of the present disclosure, it is provided Storage circuit, since the flag signal is a random number sequence with a duty cycle of 50%, the duty cycle of the static memory in the cache memory is adjusted to 50%*x+50%* (1-x ) = 50%, thereby achieving the goal of having a duty cycle of 50% for each static memory in the cache memory, reducing the impact of aging on the cache memory and extending the life of the cache memory. service life.

In the embodiment of the present disclosure, for binary data, "duty cycle" represents the ratio of the time the static memory stores data 1 to the unit time within the unit time. The duty cycle is usually less than 1. "Unit time" is set according to actual needs, and can be one day, two days, one month, one year, the life cycle of static memory, etc.

In the storage circuit provided by the embodiment of the present disclosure, only additional static memory is added to the cache memory to record the flag signal. Compared with using a multi-bit error correction code to verify and correct the erroneous bits ( In terms of correcting one bit of erroneous data (a seven-bit error correction code is required), this reduces the use of error correction codes and greatly reduces design overhead; at the same time, it does not affect the cache consistency of the cache memory, and the external interface does not need to make any changes. The high-speed buffer memory can be read and written, and the compatibility is good.

It should be noted that in the present disclosure, the input control circuit 100, the memory 200, the input control signal generator 300, the output control circuit 400, etc. in the storage circuit 10 can be implemented using hardware circuits. For example, the hardware circuits can include Resistors, capacitors, diodes, transistors and other components.

FIG. 3 is a schematic diagram of a wafer provided by at least one embodiment of the present disclosure.

As shown in FIG. 3 , some embodiments of the present disclosure also provide a wafer 20 , which is an integrated circuit. The wafer 20 includes the storage circuit 10 described in any of the above embodiments.

For example, in some embodiments, the wafer 20 further includes a substrate on which the storage circuit 10 is disposed. For example, the substrate may be a semiconductor wafer.

For example, the chip 20 can be integrated inside a central processing unit or on a motherboard.

Regarding the technical effects that can be achieved by the chip 20 , reference may be made to the relevant descriptions in the above embodiments of the storage circuit, and repeated descriptions will not be repeated.

Figure 4 is a flow chart of a data processing method provided by at least one embodiment of the present disclosure.

For example, the data processing method provided by the present disclosure can be applied to the storage circuit 10 described in any of the above embodiments. As shown in Figure 4, the data processing method includes the following steps S40 to S42.

Step S40: Receive n input data and input control signals.

Step S41: Based on the input control signal, perform first data processing on the n input data to obtain n intermediate data corresponding to the n input data.

Step S42: Store n intermediate data and flag signals corresponding to n input data.

For example, different values of the flag signal respectively represent different processing processes of the first data processing, and n is a positive integer.

For example, in some embodiments, the data processing method further includes: determining a flag signal based on the input control signal. Different values of the flag signal include a first value and a second value.

For example, based on the input control signal, performing first data processing on n pieces of input data to obtain n pieces of intermediate data that correspond one-to-one to the n pieces of input data includes: responding to the value of the flag signal determined based on the input control signal being the first First value, n input data are inverted to obtain n intermediate data; in response to the value of the flag signal determined based on the input control signal being a second value, n input data are used as n intermediate data.

For example, in some embodiments, the data processing method further includes: reading n intermediate data and a flag signal; based on the flag signal, performing second data processing on the n intermediate data to obtain a one-to-one correspondence with the n intermediate data. n output data; output n output data.

For example, in the case where different values of the flag signal include a first value and a second value, based on the flag signal, perform second data processing on the n intermediate data to obtain n output data corresponding to the n intermediate data. , including: in response to the value of the flag signal being the first value, inverting n intermediate data to obtain n output data; in response to the value of the flag signal being the second value, using n intermediate data as n output data .

Regarding the technical effects that can be achieved by the data processing method, please refer to the relevant descriptions in the above embodiments of the storage circuit, and repeated details will not be repeated.

FIG. 5 is a schematic diagram of an electronic device provided by at least one embodiment of the present disclosure.

As shown in Figure 5, some embodiments of the present disclosure also provide an electronic device 5000. The electronic device 5000 includes a processing device 5100. The processing device 5100 includes the storage circuit 10 described in any of the above embodiments.

For example, the processing device 5100 may be a central processing unit (CPU), a graphics processing unit (GPU), or the like. The storage circuit 10 can be integrated inside the central processing unit. The processing device 5100 can also be other forms of processing units with data processing capabilities and/or program execution capabilities, such as field programmable gate arrays (FPGA) or tensor processing units (TPU); for example, a central processing unit can With X86 or ARM architecture etc.

Regarding the technical effects that can be achieved by the electronic device 5000, reference may be made to the relevant descriptions in the above embodiments of the storage circuit, and repeated descriptions will not be repeated.

Referring now to FIG. 6 , FIG. 6 shows a schematic structural diagram of an electronic device 600 suitable for implementing embodiments of the present disclosure. Electronic devices in embodiments of the present disclosure may include, but are not limited to, mobile phones, notebook computers, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMP (portable multimedia players), vehicle-mounted terminals ( Mobile terminals such as car navigation terminals), wearable electronic devices, and fixed terminals such as digital TVs, desktop computers, smart home devices, etc. The electronic device shown in FIG. 6 is only an example and should not impose any limitations on the functions and scope of use of the embodiments of the present disclosure.

For example, the storage circuit 10 provided by the present disclosure can be provided in the electronic device 600 .

As shown in FIG. 6 , the electronic device 600 may include a processing device (such as a central processing unit, a graphics processor, etc.) 601 , which may be loaded into a random access device according to a program stored in a read-only memory (ROM) 602 or from a storage device 608 . Access the program in the memory (RAM) 603 to perform various appropriate actions and processes. In the RAM 603, various programs and data required for the operation of the electronic device 600 are also stored. The processing device 601, ROM 602 and RAM 603 are connected to each other through a bus 604. Input/output (I/O) interface 605 is also connected to bus 604 .

Generally, the following devices can be connected to the I/O interface 605: input devices 606 including, for example, a touch screen, touch pad, keyboard, mouse, camera, microphone, accelerometer, gyroscope, etc.; including, for example, a liquid crystal display (LCD), speakers, vibration An output device 607 such as a computer; a storage device 608 including a magnetic tape, a hard disk, etc.; and a communication device 609. The communication device 609 may allow the electronic device 600 to communicate wirelessly or wiredly with other devices to exchange data. Although FIG. 6 illustrates electronic device 600 with various means, it should be understood that implementation or availability of all illustrated means is not required. More or fewer means may alternatively be implemented or provided.

In particular, according to embodiments of the present disclosure, the processes described above with reference to the flowcharts may be implemented as computer software programs. For example, embodiments of the present disclosure include a computer program product that includes a computer program carried on a non-transitory computer-readable medium, the computer program including program code for executing the method illustrated in the flowchart to execute the method according to the above. One or more steps in the data processing method described in this article. In such an embodiment, the computer program may be downloaded and installed from the network via communication device 609, or from storage device 608, or from ROM 602. When the computer program is executed by the processing device 601, it can cause the processing device 601 to perform the above functions defined in the data processing method of the embodiment of the present disclosure.

It should be noted that, in the context of the present disclosure, a computer-readable medium may be a tangible medium that may contain or be stored for use by or in conjunction with an instruction execution system, apparatus, or device. program. The computer-readable medium may be a computer-readable signal medium or a computer-readable storage medium or any combination of the above two. The computer-readable storage medium may be, for example, but is not limited to: electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices or components, or any combination of the above. More specific examples of computer readable storage media may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard drive, random access memory (RAM), read only memory (ROM), Erasable programmable read-only memory (EPROM or flash memory), fiber optics, portable compact disk read-only memory (CD-ROM), optical memory devices, magnetic memory devices, or any suitable combination of the above. In this disclosure, a computer-readable storage medium may be any tangible medium that contains or stores a program for use by or in connection with an instruction execution system, device, or component. In the present disclosure, the computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, which carries computer-readable program code. Such propagated data signals may take many forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. A computer-readable signal medium may also be any computer-readable medium other than a computer-readable storage medium that can send, propagate, or transmit a program for use by or in connection with an instruction execution system, device, or component . Program code embodied on a computer-readable medium may be transmitted using any appropriate medium, including but not limited to: wire, optical fiber cable, RF (radio frequency), etc., or any suitable combination of the foregoing.

The above-mentioned computer-readable medium may be included in the above-mentioned electronic device; it may also exist independently without being assembled into the electronic device.

Computer program code for performing operations of the present disclosure may be written in one or more programming languages, including but not limited to object-oriented programming languages such as Java, Smalltalk, C++, and conventional programming languages, or a combination thereof. A procedural programming language, such as "C" or a similar programming language. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer, or entirely on the remote computer or server execute on. In the case of a remote computer, the remote computer can be connected to the user computer through any kind of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computer (such as an Internet service provider through Internet connection).

The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operations of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each box in the flowchart or block diagram may represent a module, segment, or portion of code that contains one or more logic for implementing the specified Function executable instructions. It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown one after another may actually execute substantially in parallel, or they may sometimes execute in the reverse order, depending on the functionality involved. It will also be noted that each block in the block diagram and/or flowchart illustration, and combinations of blocks in the block diagram and/or flowchart illustration, can be configured with dedicated hardware-based hardware that performs the specified function or operation. system, or can be implemented using a combination of dedicated hardware and computer instructions.

The units involved in the embodiments of the present disclosure may be implemented in software or hardware. Among them, the name of a unit does not constitute a limitation on the unit itself under certain circumstances.

The functions described above herein may be performed, at least in part, by one or more hardware logic components. For example, without limitation, exemplary types of hardware logic components that may be used include: field programmable gate array (FPGA), application specific integrated circuit (ASIC), application specific standard product (ASSP), system on chip (SOC) , Complex Programmable Logic Device (CPLD), etc.

According to one or more embodiments of the present disclosure, a storage circuit includes: an input control circuit and a memory. The input control circuit is configured to: receive n input data and input control signals; perform first data processing on the n input data based on the input control signal to obtain n intermediate data corresponding to the n input data; n intermediate data and flag signals corresponding to n input data are written into the memory; the memory is configured to store n intermediate data and flag signals; different values of the flag signals respectively represent different processing processes of the first data processing, n is a positive integer.

According to one or more embodiments of the present disclosure, the storage circuit further includes: an input control signal generator configured to generate the input control signal and output the input control signal to the input control circuit.

According to one or more embodiments of the present disclosure, the flag signal is the same as the input control signal.

According to one or more embodiments of the present disclosure, the different values of the flag signal are randomly generated values.

According to one or more embodiments of the present disclosure, the different values of the flag signal include a first value and a second value, and a ratio of the first value and the second value is within a predetermined range.

According to one or more embodiments of the present disclosure, if the value of the flag signal is a first value, it indicates that the first data processing is inversion processing; if the value of the flag signal is a second value, it indicates that the first data processing is a holding process.

According to one or more embodiments of the present disclosure, the predetermined range is 2/3~3/2.

According to one or more embodiments of the present disclosure, the storage circuit further includes: an output control circuit, the output control circuit is configured to: read n intermediate data and flag signals from the memory; based on the flag signal, process the n intermediate data Perform second data processing to obtain n pieces of output data corresponding to n pieces of intermediate data; output n pieces of output data.

According to one or more embodiments of the present disclosure, different values of the flag signal include a first value and a second value, the ratio of the first value and the second value is within a predetermined range, and the value of the flag signal being the first value represents the second value. The data processing is inversion processing; the value of the flag signal being the second value indicates that the second data processing is holding processing.

According to one or more embodiments of the present disclosure, the input control circuit includes n input sub-circuits corresponding to n input data one-to-one. The memory also includes a data writing interface and an output data interface. The data writing interface includes n There are n write data bits in one-to-one correspondence with each input sub-circuit. The first input terminal of each input sub-circuit receives a corresponding input data, and the second input terminal of each input sub-circuit receives an input control signal. Each input The output end of the sub-circuit is connected to the corresponding write data bit in the write data interface. Each input sub-circuit is configured to perform first data processing on the input data based on the input control signal to obtain an intermediate corresponding to the input data. data, write the intermediate data into the write data bit; the output control circuit includes n output sub-circuits that correspond to the n intermediate data one-to-one, and the output data interface includes n output data bits that correspond to the n output sub-circuits one-to-one , the first input terminal of each output sub-circuit is connected to the corresponding output data bit in the output data interface to receive a corresponding intermediate data, the second input terminal of each output sub-circuit receives the flag signal, and each output sub-circuit The output terminal is used to output output data corresponding to the intermediate data, and each output sub-circuit is configured to perform second data processing on the intermediate data based on the flag signal to obtain output data corresponding to the intermediate data, and output the output data .

According to one or more embodiments of the present disclosure, each input subcircuit includes an exclusive OR gate, and each output subcircuit includes an exclusive OR gate.

According to one or more embodiments of the present disclosure, the memory is a cache memory. The cache memory includes a plurality of data static memories and a plurality of flag static memories. The n intermediate data are respectively stored in the plurality of data static memories. In the corresponding n data static memories in the memory, the flag signal is stored in a corresponding flag static memory among the plurality of flag static memories.

According to one or more embodiments of the present disclosure, multiple data static memories and multiple flag static memories constitute multiple static memory rows, and n data static memories and flag static memories are located in the same static memory row.

According to one or more embodiments of the present disclosure, the storage circuit further includes an external write data interface configured to output n input data to the input control circuit.

According to one or more embodiments of the present disclosure, the storage circuit further includes an external data reading interface configured to receive n pieces of output data output from the output control circuit.

According to one or more embodiments of the present disclosure, a wafer includes the storage circuit according to any of the above embodiments.

According to one or more embodiments of the present disclosure, a data processing method is applied to the storage circuit according to any embodiment of the present disclosure. The data processing method includes: receiving n input data and input control signals; based on the input control signals, Perform first data processing on the n input data to obtain n intermediate data corresponding to the n input data; store the n intermediate data and the flag signals corresponding to the n input data, where n is a positive integer.

According to one or more embodiments of the present disclosure, the data processing method further includes: determining a flag signal based on the input control signal; wherein the different values of the flag signal include a first value and a second value, and based on the input control signal, for n The input data is subjected to first data processing to obtain n intermediate data corresponding to the n input data, including: in response to the value of the flag signal determined based on the input control signal being the first value, inverting the n input data. n pieces of intermediate data are obtained; in response to the value of the flag signal determined based on the input control signal being the second value, the n pieces of input data are used as n pieces of intermediate data.

According to one or more embodiments of the present disclosure, the data processing method further includes: reading n intermediate data and a flag signal; based on the flag signal, performing second data processing on the n intermediate data to obtain the same data as the n intermediate data. One corresponding n output data; output n output data.

According to one or more embodiments of the present disclosure, different values of the flag signal include a first value and a second value. Based on the flag signal, second data processing is performed on the n intermediate data to obtain a one-to-one correspondence with the n intermediate data. The n output data include: in response to the value of the flag signal being the first value, n intermediate data are inverted to obtain n output data; in response to the value of the flag signal being the second value, the n intermediate data are As n output data.

According to one or more embodiments of the present disclosure, an electronic device includes a processing device. The processing device includes a storage circuit according to any of the above embodiments.

The above description is only a description of the preferred embodiments of the present disclosure and the technical principles applied. Those skilled in the art should understand that the disclosure scope involved in the present disclosure is not limited to technical solutions composed of specific combinations of the above technical features, but should also cover solutions composed of the above technical features or without departing from the above disclosed concept. Other technical solutions formed by any combination of equivalent features. For example, a technical solution is formed by replacing the above features with technical features with similar functions disclosed in this disclosure (but not limited to).

Furthermore, although operations are depicted in a specific order, this should not be understood as requiring that these operations be performed in the specific order shown or performed in a sequential order. Under certain circumstances, multitasking and parallel processing may be advantageous. Likewise, although several specific implementation details are included in the above discussion, these should not be construed as limiting the scope of the present disclosure. Certain features that are described in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination.

Although the present subject matter has been described in language specific to structural features and/or methodological logical acts, it is to be understood that the subject matter defined in the scope of the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are merely example forms of implementing the claimed scope.

Regarding this disclosure, there are still several points that need to be explained:

(1) The drawings of the embodiments of this disclosure only refer to structures related to the embodiments of this disclosure, and other structures may refer to common designs.

(2) For clarity, in the drawings used to describe embodiments of the present disclosure, the thickness and size of layers or structures are exaggerated. It will be understood that when an element such as a layer, film, region or substrate is referred to as being "on" or "under" another element, it can be "directly on" or "under" the other element. Or intermediate elements may be present.

(3) If there is no conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. The protection scope of the present disclosure should be subject to the protection scope of the patent application.

10:Storage circuit 20:wafer 100:Input control circuit 101:Input subcircuit 200:Memory 201: Write data bit 202: Output data bit 210: Data static memory 220: Flag static memory 300: Input control signal generator 400: Output control circuit 401: Output subcircuit 500: External data writing interface 550: External data reading interface 600: Electronic equipment 601: Processing device 602:ROM 603:RAM 604:Bus 605:I/O interface 606:Input device 607:Output device 608:Storage device 609: Communication device 5000: Electronic equipment 5100: Processing device Cs: input control signal Ms:Intermediate information Is: Enter data Os: output data S40, S41, S42: steps Ss: sign signal

The above and other features, advantages, and aspects of various embodiments of the present disclosure will become more apparent with reference to the following detailed description taken in conjunction with the accompanying drawings. Throughout the drawings, the same or similar reference numbers refer to the same or similar elements. It should be understood that the drawings are schematic and that elements and elements are not necessarily drawn to scale. FIG. 1A is a schematic diagram of a storage circuit provided by at least one embodiment of the present disclosure. FIG. 1B is a schematic diagram of another storage circuit provided by at least one embodiment of the present disclosure. FIG. 2 is a schematic structural diagram of a storage circuit provided by some embodiments of the present disclosure. FIG. 3 is a schematic diagram of a wafer provided by at least one embodiment of the present disclosure. Figure 4 is a flow chart of a data processing method provided by at least one embodiment of the present disclosure. FIG. 5 is a schematic diagram of an electronic device provided by at least one embodiment of the present disclosure. FIG. 6 is a schematic structural diagram of an electronic device provided by at least one embodiment of the present disclosure.

10:Storage circuit

100:Input control circuit

200:Memory

Claims (18)

A storage circuit, including: an input control circuit and a memory, wherein the input control circuit is configured to: receive n input data and input control signals; based on the input control signal, perform a first operation on the n input data. A data processing to obtain n intermediate data corresponding to the n input data; writing the n intermediate data and the flag signal corresponding to the n input data into the memory; The memory is configured to store the n intermediate data and the flag signal; wherein different values of the flag signal respectively represent different processing processes of the first data processing, n is a positive integer, and wherein, the Different values of the flag signal include a first value and a second value, and the ratio of the first value to the second value is within a predetermined range, and the predetermined range is 2/3~3/2. The storage circuit of claim 1, further comprising: an input control signal generator, wherein the input control signal generator is configured to generate the input control signal and output the input control signal to the input control circuit. The storage circuit of claim 1, wherein the flag signal is the same as the input control signal. The storage circuit of claim 1, wherein the different values of the flag signal are randomly generated values. The storage circuit according to claim 1, wherein the value of the flag signal is the first value, indicating that the first data processing is an inversion process; the value of the flag signal is the second value, indicating that the first data processing is an inversion process. The first data processing is retention processing. The storage circuit according to claim 1, further comprising: an output control circuit, wherein the output control circuit is configured to: read the n intermediate data and the flag signal from the memory; based on the The flag signal is used to perform second data processing on the n intermediate data to obtain n output data corresponding to the n intermediate data one-to-one; and the n output data are output. The storage circuit of claim 6, wherein the different values of the flag signal include a first value and a second value, the ratio of the first value to the second value is within a predetermined range, and the flag signal If the value of the flag signal is the first value, it indicates that the second data processing is an inversion process; if the value of the flag signal is the second value, it indicates that the second data processing is a holding process. The storage circuit of claim 6, wherein the input control circuit includes n input sub-circuits corresponding to the n input data, and the memory also includes a data writing interface and an output data interface, The write data interface includes n write data bits corresponding to the n input sub-circuits one-to-one, The first input terminal of each input sub-circuit receives a corresponding input data, the second input terminal of each input sub-circuit receives the input control signal, and the output terminal of each input sub-circuit is connected to the writing data interface. corresponding written data bits in, each input sub-circuit is configured to perform the first data processing on the input data based on the input control signal to obtain intermediate data corresponding to the input data, and The intermediate data is written into the write data bit; the output control circuit includes n output sub-circuits corresponding to the n intermediate data, and the output data interface includes n output sub-circuits. n output data bits in one-to-one correspondence, the first input end of each output sub-circuit is connected to the corresponding output data bit in the output data interface to receive a corresponding intermediate data, and the second input end of each output sub-circuit The input terminal receives the flag signal, the output terminal of each output sub-circuit is used to output output data corresponding to the intermediate data, and each output sub-circuit is configured to perform all processing on the intermediate data based on the flag signal. The second data processing is performed to obtain output data corresponding to the intermediate data, and the output data is output. The storage circuit of claim 8, wherein each input sub-circuit includes a mutual exclusive OR gate, and each output sub-circuit includes a mutual exclusive OR gate. The storage circuit according to any one of claims 1 to 9, wherein the memory is a cache memory, and the cache memory includes a plurality of data static memories and a plurality of flag static memories, The n intermediate data are stored in corresponding n data static memories among the plurality of data static memories, and the flag signal is stored in a corresponding flag static memory among the plurality of flag static memories. body. The storage circuit of claim 10, wherein the plurality of data static memories and the plurality of flag static memories constitute a plurality of static memory rows, and the n data static memories and the flag static memories The memory is located in the same static memory row. The storage circuit according to any one of claims 6-9, further comprising an external data writing interface and an external reading data interface, wherein the external data writing interface is configured to output the n input data to In the input control circuit, the external data reading interface is configured to receive the n output data output from the output control circuit. A chip including the storage circuit according to any one of claims 1-12. A data processing method, applied to the storage circuit described in any one of claims 1-12, including: receiving the n input data and the input control signal; based on the input control signal, processing the n input data Perform the first data processing on the data to obtain the n intermediate data corresponding to the n input data one-to-one; store the n intermediate data and the flag signals corresponding to the n input data, Wherein, n is a positive integer, and wherein the different values of the flag signal include a first value and a second value, the ratio of the first value and the second value is within a predetermined range, and the predetermined range is 2 /3~3/2. The data processing method as described in claim 14, further comprising: determining the flag signal based on the input control signal; performing the first data processing on the n input data based on the input control signal, so as to Obtaining the n intermediate data corresponding to the n input data in a one-to-one manner includes: in response to the value of the flag signal determined based on the input control signal being the first value, converting the n input data The data is inverted to obtain the n pieces of intermediate data; in response to the value of the flag signal determined based on the input control signal being the second value, the n pieces of input data are used as the n pieces of intermediate data. . The data processing method as described in claim 14, further comprising: reading the n intermediate data and the flag signal; performing second data processing on the n intermediate data based on the flag signal to obtain the n output data corresponding to the n intermediate data one-to-one; output the n output data. The data processing method as described in claim 16, wherein, based on the flag signal, second data processing is performed on the n intermediate data to obtain n output data corresponding to the n intermediate data one-to-one, The method includes: in response to the value of the flag signal being the first value, inverting the n intermediate data to obtain the n output data; In response to the value of the flag signal being the second value, the n intermediate data are used as the n output data. An electronic device includes: a processing device, wherein the processing device includes the storage circuit according to any one of claims 1-12.

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