CN117054750A

CN117054750A - Sampling device, related equipment and control method

Info

Publication number: CN117054750A
Application number: CN202210480895.8A
Authority: CN
Inventors: 章文强; 冯君校; 殷士辉; 景蔚亮; 王正波; 廖恒
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2022-05-05
Filing date: 2022-05-05
Publication date: 2023-11-14
Also published as: WO2023213102A1

Abstract

The application discloses a sampling device, related equipment and a control method, and provides the sampling device which can comprise a first sampling plane, a first voltage supply circuit, X second voltage supply circuits, a controller and a reading circuit. Specifically, the voltage at two ends of the ferroelectric capacitor can be adjusted to enable the probability of turning over the polarization direction of the ferroelectric capacitor to be the same as the probability of different results possibly occurring in the probability event, so that whether different results possibly occurring in the probability event occur or not can be determined according to the read polarization direction turning over situation of the ferroelectric capacitor, and sampling of the probability event is completed. The sampling device provided by the application can reduce the cost of the chip area for realizing the sampling operation.

Description

Sampling device, related equipment and control method

Technical Field

The present application relates to the field of electronic technologies, and in particular, to a sampling apparatus, a related device, and a control method.

Background

Probability computation is widely used in important fields such as image segmentation and medical diagnosis, for example, in bayesian network models. However, in a large-scale probability model, the dependency relationship between nodes is very complex, and cannot be directly solved by a bayesian formula, and generally, a markov chain monte carlo (Markov Chain Monte Carlo, MCMC) method is adopted for solving. In the process of solving the probability model by adopting the MCMC method, a large number of conditional probability distributions in the probability model need to be sampled, and for hardware used for calculation, such as a central processing unit (Center Processing Unit, CPU) or a graphics processor (Graphic Processing Unit, GPU), a sampling circuit currently used for implementing the sampling operation needs to occupy a large area on a CPU or GPU chip.

However, the current technology has a certain limit requirement on the chip area, and in order to make the chip have more and stronger functions under the condition of constant chip area, it is required to pursue to integrate more circuits or devices on the chip with limited area, that is, the circuits or devices in the chip need to be made smaller and smaller, and occupy less area to meet the demands of people for more and stronger functions of the chip. Therefore, how to provide a sampling device with a smaller occupied area, and to reduce the cost of implementing the sampling operation on the chip area, is a problem to be solved.

Disclosure of Invention

The embodiment of the application provides a sampling device, related equipment and a control method, which can reduce the cost of chip area for realizing sampling operation.

In a first aspect, an embodiment of the present application provides a sampling device, which may include a first sampling plane, a first voltage supply circuit, X second voltage supply circuits, a controller, and a reading circuit, where the first sampling plane includes X first ferroelectric capacitors; x is an integer greater than 0; wherein, the first electrode of each first ferroelectric capacitor in the X first ferroelectric capacitors is connected with the first voltage supply circuit; the first voltage supply circuit is used for supplying a first voltage to the first electrode of each first ferroelectric capacitor; the second electrode of the X first ferroelectric capacitor is connected with the X second voltage supply circuit; x is 1, 2, … … and X, and the xth second voltage supply circuit is used for supplying a second voltage to the second electrode of the xth first ferroelectric capacitor; the controller is respectively connected with the first voltage supply circuit and the X second voltage supply circuits; the controller is used for: receiving a sampling instruction, wherein the sampling instruction comprises X probability values; controlling the first voltage supply circuit and/or the X second voltage supply circuits to adjust the first voltage and/or the second voltage respectively based on the X probability values; the voltage difference between the first voltage and the second voltage on the xth first ferroelectric capacitor corresponds to an xth probability value of the X probability values; the reading circuit is used for reading the polarization direction of each first ferroelectric capacitor; wherein the polarization direction of each of the first ferroelectric capacitors is reversed between a first polarization direction and a second polarization direction based on a voltage difference between the first voltage and the second voltage.

In the embodiment of the application, the sampling device based on the ferroelectric capacitor is provided, when the sampling device is used for realizing sampling operation, the occupation of a sampling circuit or the sampling device to the area of a chip can be reduced, so that the chip can have more spare areas to integrate circuits or devices with other functions, and the requirements of people on the chip with more and stronger functions are met. Specifically, for example, when the sampling device is used for sampling a certain random event (such as an event A), the occurrence process of the event A can be simulated through the ferroelectric capacitor, whether a plurality of different results corresponding to the event A occur or not is determined, the purpose of sampling the event A is achieved, and the polarization direction overturning probability of the different ferroelectric capacitors can be corresponding to the occurrence probability of the different results of the event A by adjusting the voltage difference between two ends of the ferroelectric capacitor, so that the polarization direction of the ferroelectric capacitor can be overturned according to a certain probability; and then the turning situation of the polarization direction of the ferroelectric capacitor is read, and because different results of actual events generally have mutual exclusion relation, the ferroelectric capacitor with the turned polarization direction can be determined based on the reading result, and a certain result of the event A corresponding to the ferroelectric capacitor is considered to occur and is taken as the sampling result of the sampling. In summary, in the sampling device based on ferroelectric capacitors provided by the application, in the actual sampling process, the polarization direction inversion probability distribution of each ferroelectric capacitor is consistent with the probability distribution of different results of probability events, and the judgment logic for the sampling results is also consistent with the development rule of the actual events, so that the sampling device provided by the application can be used in the actual sampling process. In the prior art, the area of the ferroelectric capacitor is smaller than that of the register, so that the sampling device provided by the application occupies smaller area of a chip, different from a scheme of realizing sampling operation by using more registers; in addition, in the sampling device provided by the application, the upper electrodes or the lower electrodes (namely the first electrodes) of the X ferroelectric capacitors in the sampling plane can share one voltage supply circuit (namely the first voltage supply circuit), so that the number of the voltage supply circuits is reduced, and the occupation of the sampling device on the chip area is further reduced.

In one possible implementation, the first electrode or the second electrode of each of the first ferroelectric capacitors is connected to the reading circuit.

In the embodiment of the application, the reading circuit in the sampling device can be connected with the upper electrode or the lower electrode of the ferroelectric capacitor, so that the circuit of the sampling device has more flexibility, and the applicability of the sampling device is improved.

In one possible implementation, the first electrode includes an upper electrode or a lower electrode, and the second electrode includes an upper electrode or a lower electrode, the first electrode being a different electrode than the second electrode.

In the embodiment of the application, the first electrode of the ferroelectric capacitor in the sampling device can be an upper electrode or a lower electrode, and the first electrodes of the plurality of ferroelectric capacitors in the sampling plane can be connected with the first voltage supply circuit, that is, the upper electrodes of the plurality of ferroelectric capacitors or the lower electrodes of the plurality of ferroelectric capacitors can be shared by the first voltage supply circuit, so that the implementation of the sampling device is more flexible, and the applicability of the sampling device is improved.

In one possible implementation manner, the first voltage supply circuit includes a first field effect transistor or a first digital-to-analog conversion circuit; the X second voltage supply circuits comprise second field effect transistors or second digital-to-analog conversion circuits.

In the embodiment of the application, the first voltage supply circuit in the sampling device can be a field effect transistor or a digital-to-analog conversion circuit; the second voltage supply circuit may be a field effect transistor, or may be a digital-to-analog conversion circuit, that is, the two groups of voltage supply circuits included in the sampling device may be both field effect transistors or digital-to-analog conversion circuits, or may be a combination of the field effect transistors and the digital-to-analog conversion circuits. Because the field effect tube and the digital-to-analog conversion circuit have simple structures and smaller areas, the sampling device provides voltages for the upper electrode and the lower electrode at the two ends of the ferroelectric capacitor by using the field effect tube and the digital-to-analog conversion circuit, and the cost of the area of the chip can be further reduced.

In one possible implementation, the first voltage supply circuit or the X second voltage supply circuits are integrated in the read circuit.

In the embodiment of the application, the voltage supply circuit for supplying voltage to the upper electrode or the lower electrode of the ferroelectric capacitor in the sampling device can be integrated in the reading circuit, and part of structures in the reading circuit are multiplexed, so that the circuit cost can be reduced, and the occupation of the sampling device to the chip area is further reduced.

In a possible implementation manner, the first sampling plane further includes X second ferroelectric capacitors, the first electrode of each of the first ferroelectric capacitors and the first electrode of each of the X second ferroelectric capacitors are connected in parallel with the first voltage supply circuit, and the first voltage supply circuit is shared.

In the embodiment of the application, in the same sampling plane, the sampling device may include multiple groups (for example, Y groups) of ferroelectric capacitors, and the first electrodes (the upper electrodes) of the multiple ferroelectric capacitors in different groups may share the same voltage supply circuit (i.e., the first voltage supply circuit), that is, one voltage supply circuit may provide voltages for the first electrodes of x×y ferroelectric capacitors in the same sampling plane, which greatly reduces the number of voltage supply circuits and further reduces the occupation of the sampling device to the chip area.

In a possible implementation manner, the first sampling plane further includes X second ferroelectric capacitors, the second electrode of the X first ferroelectric capacitor and the second electrode of the X second ferroelectric capacitor are connected in parallel with the X second voltage supply circuit, and the X second voltage supply circuit is shared; x is 1, 2, … …, X.

In the embodiment of the application, in the same sampling plane, the sampling device can comprise a plurality of groups (for example, Y groups) of ferroelectric capacitors, the second electrodes (the lower electrodes) of the plurality of ferroelectric capacitors with the same serial numbers (when x takes the same value) in different groups can share the same voltage supply circuit (namely, the x second voltage supply circuit), that is, one voltage supply circuit can supply voltage for the second electrodes of the Y ferroelectric capacitors in the same sampling plane, thus greatly reducing the number of the voltage supply circuits and further reducing the occupation of the sampling device to the chip area.

In a possible implementation manner, the sampling device further includes a second sampling plane, where the second sampling plane includes X third ferroelectric capacitors, and the first electrode of each third ferroelectric capacitor of the X third ferroelectric capacitors and the first electrode of each first ferroelectric capacitor are connected in parallel with the first voltage supply circuit, and share the first voltage supply circuit.

In the embodiment of the present application, the sampling device includes a plurality of sampling planes (e.g., S sampling planes), and the first electrodes (upper electrodes) of the ferroelectric capacitors of the plurality of groups in different sampling planes may share the same voltage supply circuit (i.e., the first voltage supply circuit), that is, one voltage supply circuit may supply voltages to the first electrodes of the s×y ferroelectric capacitors in different sampling planes; in addition, if the ferroelectric capacitors in different groups of the same sampling plane can also share the voltage supply circuit, one voltage supply circuit can supply voltages to the first electrodes of the s×x×y ferroelectric capacitors in different sampling planes, which greatly reduces the number of the voltage supply circuits and further reduces the occupation of the sampling device on the chip area.

In a possible implementation manner, the sampling device further includes a second sampling plane, where the second sampling plane includes X third ferroelectric capacitors, the second electrode of the X first ferroelectric capacitor and the second electrode of the X third ferroelectric capacitor are connected in parallel with the X second voltage supply circuit, and the second voltage supply circuit is shared; x is 1, 2, … …, X.

In the embodiment of the present application, the sampling device includes a plurality of sampling planes (e.g., S sampling planes), and the second electrodes (such as the lower electrodes) of the plurality of ferroelectric capacitors having the same serial numbers (X has the same value) in different groups in different sampling planes may share the same voltage supply circuit (i.e., the X-th second voltage supply circuit), that is, one voltage supply circuit may provide voltages for the second electrodes of the S-X-Y ferroelectric capacitors in different sampling planes, and when the first electrodes of the plurality of ferroelectric capacitors having the same serial numbers in the same sampling plane may share the voltage supply circuit, one voltage supply circuit may provide voltages for the first electrodes of the S-X-Y ferroelectric capacitors in different sampling planes, which greatly reduces the number of voltage supply circuits and further reduces the occupation of the sampling device to the chip area.

In one possible implementation, the first electrode or the second electrode of each of the first ferroelectric capacitors is connected in parallel with the reading circuit, sharing the reading circuit; the first sampling plane further includes X second ferroelectric capacitors, and the first electrode or the second electrode of each of the first ferroelectric capacitor and the X second ferroelectric capacitors is connected in parallel with the reading circuit, sharing the reading circuit.

In the embodiment of the application, a plurality of groups of ferroelectric capacitors can be included in the same sampling plane in the sampling device, the first electrodes or the second electrodes (the upper electrodes) of the plurality of ferroelectric capacitors in the same group can share the same reading circuit (namely the reading circuit), and the plurality of ferroelectric capacitors in different groups can share the reading circuit, namely one reading circuit can read the inversion condition of the polarization directions of the X, X and Y ferroelectric capacitors in the same sampling plane, thereby greatly reducing the number of the reading circuits and further reducing the occupation of the sampling device to the chip area.

In a possible implementation, the sampling device further comprises a second sampling plane, the second sampling plane comprising X third ferroelectric capacitors, the first electrode or the second electrode of each of the first ferroelectric capacitor and each of the X third ferroelectric capacitors being connected in parallel with the reading circuit, sharing the reading circuit.

In the embodiment of the present application, the sampling device may include a plurality of sampling planes (e.g. S sampling planes), each sampling plane may include one or more groups of ferroelectric capacitors (e.g. Y groups), and the first electrodes or the second electrodes (e.g. the upper electrodes) of the plurality of ferroelectric capacitors in different groups of different sampling planes may share the same reading circuit (i.e. the reading circuit), that is, one reading circuit may read the inversion condition of the polarization directions of the s×y ferroelectric capacitors in different sampling planes; and if the ferroelectric capacitors in different groups of the same sampling plane can also share the reading, one reading circuit can read the inversion condition of the polarization directions of the S, X and Y ferroelectric capacitors in different sampling planes, so that the number of the reading circuits is greatly reduced, and the occupation of the sampling device to the chip area is further reduced.

In one possible implementation, when a voltage difference between the first voltage of the first electrode and the second voltage of the second electrode is greater than or equal to a preset threshold, a polarization direction of the corresponding first ferroelectric capacitor is flipped between the first polarization direction and the second polarization direction; and when the voltage difference is smaller than the preset threshold value, the polarization direction of the corresponding first ferroelectric capacitor is turned over between the first polarization direction and the second polarization direction according to the probability value corresponding to the voltage difference.

In the embodiment of the application, the sampling device comprises one or more ferroelectric capacitors, and the polarization direction of the ferroelectric capacitors is reversed when the voltage difference reaches a certain value, wherein the voltage difference is related to the voltage difference between two ends of the ferroelectric capacitors; when the voltage difference fails to reach a certain value, the polarization direction of the ferroelectric capacitor is turned over according to the probability value corresponding to the specific value of the voltage difference.

In a second aspect, an embodiment of the present application provides a sampling device, which may include a first voltage supply circuit, X second voltage supply circuits, a controller, and a reading circuit, where the sampling device is coupled to a first sampling plane, and the first sampling plane includes X first ferroelectric capacitors; x is an integer greater than 0; wherein, the first electrode of each first ferroelectric capacitor in the X first ferroelectric capacitors is connected with the first voltage supply circuit; the first voltage supply circuit is used for supplying a first voltage to the first electrode of each first ferroelectric capacitor; the second electrode of the X first ferroelectric capacitor is connected with the X second voltage supply circuit; x is 1, 2, … … and X, and the xth second voltage supply circuit is used for supplying a second voltage to the second electrode of the xth first ferroelectric capacitor; the controller is respectively connected with the first voltage supply circuit and the X second voltage supply circuits; the controller is used for: receiving a sampling instruction, wherein the sampling instruction comprises X probability values; controlling the first voltage supply circuit and/or the X second voltage supply circuits to adjust the first voltage and/or the second voltage respectively based on the X probability values; the voltage difference between the first voltage and the second voltage on the xth first ferroelectric capacitor corresponds to an xth probability value of the X probability values; the reading circuit is used for reading the polarization direction of each first ferroelectric capacitor; wherein the polarization direction of each of the first ferroelectric capacitors is reversed between a first polarization direction and a second polarization direction based on a voltage difference between the first voltage and the second voltage.

In a possible implementation manner, the sampling device is further coupled with a second sampling plane, and the second sampling plane includes X third ferroelectric capacitors, where the first electrode of each third ferroelectric capacitor of the X third ferroelectric capacitors and the first electrode of each first ferroelectric capacitor are connected in parallel with the first voltage supply circuit, and the first voltage supply circuit is shared.

In a possible implementation manner, the sampling device is further coupled to a second sampling plane, and the second sampling plane includes X third ferroelectric capacitors, where the second electrode of the X first ferroelectric capacitor and the second electrode of the X third ferroelectric capacitor are connected in parallel to the X second voltage supply circuit, and the second voltage supply circuit is shared; x is 1, 2, … …, X.

In one possible implementation manner, when the voltage difference between the first voltage and the second voltage is greater than or equal to a preset threshold, the polarization direction of the corresponding first ferroelectric capacitor is flipped between the first polarization direction and the second polarization direction; and when the voltage difference is smaller than the preset threshold value, the polarization direction of the corresponding first ferroelectric capacitor is turned over between the first polarization direction and the second polarization direction according to the probability value corresponding to the voltage difference.

In a third aspect, an embodiment of the present application provides a ferroelectric capacitor array, which may include a first sampling plane, where the first sampling plane includes X first ferroelectric capacitors, and the first sampling plane is coupled to a sampling device, where the sampling device includes a first voltage supply circuit, X second voltage supply circuits, a controller, and a reading circuit; x is an integer greater than 0; wherein, the first electrode of each first ferroelectric capacitor in the X first ferroelectric capacitors is connected with the first voltage supply circuit; the first voltage supply circuit is used for supplying a first voltage to the first electrode of each first ferroelectric capacitor; the second electrode of the X first ferroelectric capacitor is connected with the X second voltage supply circuit; x is 1, 2, … … and X, and the xth second voltage supply circuit is used for supplying a second voltage to the second electrode of the xth first ferroelectric capacitor; the controller is respectively connected with the first voltage supply circuit and the X second voltage supply circuits; the controller is used for: receiving a sampling instruction, wherein the sampling instruction comprises X probability values; controlling the first voltage supply circuit and/or the X second voltage supply circuits to adjust the first voltage and/or the second voltage respectively based on the X probability values; the voltage difference between the first voltage and the second voltage on the xth first ferroelectric capacitor corresponds to an xth probability value of the X probability values; the reading circuit is used for reading the polarization direction of each first ferroelectric capacitor; wherein the polarization direction of each of the first ferroelectric capacitors is reversed between a first polarization direction and a second polarization direction based on a voltage difference between the first voltage and the second voltage.

In a possible implementation manner, the ferroelectric capacitor array further includes a second sampling plane, where the second sampling plane includes X third ferroelectric capacitors, and the first electrode of each third ferroelectric capacitor of the X third ferroelectric capacitors and the first electrode of each first ferroelectric capacitor are connected in parallel with the first voltage supply circuit, and share the first voltage supply circuit.

In a possible implementation manner, the ferroelectric capacitor array further includes a second sampling plane, where the second sampling plane includes X third ferroelectric capacitors, the second electrode of the X first ferroelectric capacitor and the second electrode of the X third ferroelectric capacitor are connected in parallel with the X second voltage supply circuit, and the second voltage supply circuit is shared; x is 1, 2, … …, X.

In a possible implementation, the ferroelectric capacitor array further comprises a second sampling plane, the second sampling plane comprising X third ferroelectric capacitors, the first electrode or the second electrode of each of the first ferroelectric capacitor and each of the X third ferroelectric capacitors being connected in parallel with the reading circuit, sharing the reading circuit.

In a fourth aspect, embodiments of the present application provide a control method, which is applicable to the first aspect and the second aspect and the sampling device provided in combination with any one of possible implementation manners of the first aspect and the second aspect. The method comprises the following steps: the controller controls the first voltage supply circuit and/or the X second voltage supply circuits to perform first adjustment on the first voltage and/or the second voltage, and the polarization direction of each first ferroelectric capacitor is initialized to be the first polarization direction; receiving, by the controller, a sampling instruction, the sampling instruction comprising X probability values; the first voltage supply circuit and/or the X second voltage supply circuits are/is controlled to carry out second adjustment on the first voltage and/or the second voltage based on the X probability values, and the voltage difference between the first voltage and the second voltage on the xth first ferroelectric capacitor corresponds to the xth probability value in the X probability values; reading the polarization direction of each first ferroelectric capacitor of the ferroelectric capacitors through the reading circuit; wherein a polarization direction of each of the first ferroelectric capacitors is flipped from the first polarization direction to the second polarization direction based on a voltage difference of the first voltage and the second voltage.

In the embodiment of the application, before the sampling device is used for sampling, the polarization direction of the ferroelectric capacitor can be initialized to return to the initial state (namely, the first polarization direction or the second polarization direction); because different results of actual events generally have mutual exclusion relation, after sampling is completed, a reading circuit only needs to read the state of the polarization direction of the ferroelectric capacitor after the sampling, so that whether the polarization direction of the ferroelectric capacitor is overturned or not can be determined one by one (can be determined one by one according to a certain sequence or can be determined one by one at random), and the polarization direction of the ferroelectric capacitor which is overturned first can be used as a sampling result; if the polarization direction of the last ferroelectric capacitor is not inverted before the last ferroelectric capacitor is determined, whether the polarization direction of the last ferroelectric capacitor is inverted or not can be judged, and the polarization direction of the last ferroelectric capacitor can be considered to be inverted and used as a sampling result. If the polarization direction of the ferroelectric capacitor is not initialized before sampling, an additional storage device is needed, the polarization direction state of the ferroelectric capacitor before the sampling is recorded and stored, and the polarization direction state of the ferroelectric capacitor after the sampling is finished is compared with the state before the sampling recorded and stored by the storage device, so that whether the polarization direction of the ferroelectric capacitor is overturned or not can be determined; in addition, since the inversion probability of the ferroelectric capacitor polarization direction is related to the current state of the ferroelectric capacitor, if the ferroelectric capacitor is not initialized, the upper electrode voltage of the existing ferroelectric capacitor may be larger than the lower electrode voltage and the upper electrode voltage of the existing ferroelectric capacitor may be smaller than the lower electrode voltage in the process of actually sampling and adjusting the voltages at the two ends of the ferroelectric capacitor, so that the circuit complexity is high and a specific voltage supply circuit may be required for realizing the inversion probability. Therefore, when the sampling device provided by the embodiment of the application realizes sampling operation by using the control method provided by the application, the sampling logic can be simplified, the requirement of the sampling device on a voltage supply circuit is reduced, and the applicability of the sampling device is improved.

In a possible implementation manner, the method further includes: when the first sampling plane further includes X second ferroelectric capacitors, a polarization direction of each of the second ferroelectric capacitors is read by the reading circuit.

In the embodiment of the application, when the sampling device is used for sampling, ferroelectric capacitors of a plurality of groups (for example, Y groups) in the same sampling plane can be used for sampling at the same time, that is, one sampling plane can be used for sampling a certain probability event for Y times at the same time, so that the sampling efficiency can be effectively improved.

In a possible implementation manner, when the sampling device further includes a second sampling plane, the second sampling plane includes X third ferroelectric capacitors, a polarization direction of each of the third ferroelectric capacitors is read by the reading circuit.

In the embodiment of the application, when the sampling device is used for sampling, after one sampling is finished through one sampling plane, the subsequent sampling can be firstly carried out through other sampling planes, and the sampling is carried out by using different sampling planes in consideration of the fact that the turnover times of the polarization direction of the ferroelectric capacitor are limited, so that the sampled workload can be shared on the different sampling planes, the turnover times of the different ferroelectric capacitors can be balanced, the service life of the sampling device is prolonged, and the maintenance cost is reduced. Of course, the sampling can be simultaneously performed by using different sampling planes, so that the sampling efficiency can be effectively improved.

In a fifth aspect, an embodiment of the present application provides a semiconductor chip, where the semiconductor chip includes the first aspect and the second aspect and a sampling device provided in combination with any one of possible implementation manners of the first aspect and the second aspect.

In a sixth aspect, an embodiment of the present application provides an electronic device, where the electronic device includes the first aspect and the second aspect, and a sampling apparatus provided in combination with any one of possible implementation manners of the first aspect and the second aspect; the electronic device further comprises a main processor, wherein the main processor is coupled with the sampling device and is used for sending a sampling instruction to the sampling device and receiving a sampling result of the sampling device; the electronic device further comprises a memory for storing program instructions and data necessary for the main processor and the sampling means to run; the electronic device may also include a communication interface for the electronic device to communicate with other devices or communication networks.

In a seventh aspect, an embodiment of the present application provides an electronic device having a function of implementing a control method of any one of the sampling devices in the fourth aspect. The functions can be realized by hardware, and can also be realized by executing corresponding software by hardware. The hardware or software includes one or more modules corresponding to the functions described above.

In an eighth aspect, the present application provides a computer storage medium storing a computer program which, when executed by a sampling apparatus, causes the sampling apparatus to execute the control method flow of any one of the fourth aspects above.

In a ninth aspect, an embodiment of the present application provides a computer program, which includes instructions that, when executed by a sampling device provided in any one of the above first aspect and second aspect and in combination with any one of the possible implementation manners of the first aspect and the second aspect, enable the sampling device to perform the control method flow described in any one of the above fourth aspect.

In a tenth aspect, the present application provides a chip system comprising the first and second aspects described above and a sampling device provided in combination with any one of the possible implementations of the first and second aspects. In one possible design, the system-on-chip further includes a processor and a memory for holding necessary or relevant program instructions and data for the sampling device and the processor. The chip system can be composed of chips, and can also comprise chips and other discrete devices.

In an eleventh aspect, the present application provides a system-on-a-chip SoC chip including the sampling device provided in any one of the above first and second aspects and in combination with any one of the possible implementations of the first and second aspects, a processor coupled to the sampling device, an internal memory and an external memory, the internal memory and the external memory being configured to store necessary or relevant program instructions and data of the sampling device and the processor. The SoC chip may be formed by a chip, or may include a chip and other discrete devices.

Drawings

In order to more clearly describe the embodiments of the present application or the technical solutions in the background art, the following description will describe the drawings that are required to be used in the embodiments of the present application or the background art. It is evident that the drawings in the following description are only some embodiments of the present application and that other drawings may be obtained from these drawings without inventive effort for a person of ordinary skill in the art.

Fig. 1a is a schematic structural diagram of an electronic device according to an embodiment of the present application.

Fig. 1b is a schematic structural diagram of another electronic device according to an embodiment of the present application.

Fig. 1c is a schematic diagram of an overall structure of a sampling device according to an embodiment of the present application.

Fig. 1d is a schematic overall structure of another sampling device according to an embodiment of the present application.

Fig. 2a is a schematic diagram of a sampling device suitable for classifying probability distributions according to an embodiment of the present application.

Fig. 2b is a schematic diagram of a sampling apparatus suitable for multi-classification probability distribution according to an embodiment of the present application.

Fig. 3a is a schematic three-dimensional structure of a sampling device according to an embodiment of the present application.

Fig. 3b is a schematic three-dimensional structure of another sampling device according to an embodiment of the present application.

Fig. 3c is a schematic three-dimensional structure of another sampling device according to an embodiment of the present application.

Fig. 3d is a schematic three-dimensional structure of another sampling device according to an embodiment of the present application.

Fig. 3e is a schematic three-dimensional structure of another sampling device according to an embodiment of the present application.

Fig. 4 is a flowchart of a control method of a sampling device according to an embodiment of the present application.

Detailed Description

Embodiments of the present application will be described below with reference to the accompanying drawings in the embodiments of the present application.

The terms "first," "second," "third," and "fourth" and the like in the description and in the claims and drawings are used for distinguishing between different objects and not necessarily for describing a particular sequential or chronological order. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those listed steps or elements but may include other steps or elements not listed or inherent to such process, method, article, or apparatus.

Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in one or more embodiments of the application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.

First, some terms in the present application will be explained in order to be understood by those skilled in the art.

(1) Ferroelectric capacitors (Ferroelectric Cap, feC) whose core technology is ferroelectric crystalline materials. The working principle of ferroelectric crystal is: when an electric field is added to the ferroelectric crystal material, central atoms in the crystal move along the direction of the electric field according to a certain probability and are unified into one direction to reach a stable state (namely, polarization direction); wherein, each free floating central atom in the crystal has only 2 stable states, one is that the first polarization direction (or the second polarization direction) can be marked as 0 in logic, the other is that the second polarization direction (or the first polarization direction) can be marked as 1, and the central atom can stay in the stable state for more than 100 years under the condition of normal temperature and no electric field. Compared with the scheme that the pseudo-random number generating circuit and the register circuit are mainly adopted in the sampling circuit in the prior art to realize sampling operation, the ferroelectric capacitor is smaller in area and size. Therefore, in the embodiment of the application, the polarization direction reversal probability of one or more ferroelectric capacitors is expressed as the probability corresponding to one or more results of probability event occurrence by utilizing the characteristic that the polarization direction of the ferroelectric capacitors is subjected to probabilistic reversal according to the electric field and adjusting the voltages at two ends of the ferroelectric capacitors, so that the sampling circuit or the sampling device based on the ferroelectric capacitors can be obtained, and the cost on the chip area is reduced.

(2) A Bayesian Network (Bayesian Network) is a graphical probabilistic Network based on probabilistic reasoning, and includes nodes and directed edges connecting the nodes. Wherein nodes represent random variables, directed edges between nodes represent interrelationships between nodes (generally pointed to their child nodes by parent nodes), the strength of the node relationships is expressed with conditional probabilities, and nodes without parent nodes can be expressed with prior probabilities. Bayesian networks are based on bayesian formulas, which are adapted to express and analyze uncertainty and probabilistic events from which inferences can be made from incomplete, inaccurate, or uncertain knowledge or information. However, as the scale of the probability model is larger and larger, the dependency relationship between each node in the model is more complex, and the probability model cannot be directly solved through a Bayesian formula, and a Markov chain Monte Carlo method is generally used for solving, wherein the method needs to sample a large number of conditional probabilities, but a sampling circuit in the prior art occupies a large chip area. In the embodiment of the application, a sampling circuit or sampling device based on ferroelectric capacitor is provided, which is applicable to the process of sampling and solving a large number of conditional probabilities in a probability model by using MCMC, and can reduce the occupation of the sampling circuit or sampling device to the chip area.

(3) Markov chain Monte Carlo (Markov Chain Monte Carlo, MCMC) is a random sampling method which is widely applied in the fields of machine learning, deep learning, natural language processing and the like, and the approximate solution of complex operations by using the MCMC is the basis of the solution of a plurality of complex models or algorithms. In the embodiment of the application, the sampling circuit or the sampling device based on the ferroelectric capacitor is provided, and can be suitable for the process of sampling and solving a large number of conditional probabilities in a probability model by using MCMC, so that the occupation of the sampling circuit or the sampling device on the chip area can be reduced.

First, the technical problems to be solved by the present application are analyzed and presented. In the prior art, the mainstream sampling operation is mostly implemented by adopting a cumulative probability distribution sampling circuit, and the circuit comprises a pseudo-random number generating circuit, a cumulative probability distribution function storage table, a lookup circuit and other sub-circuits.

The scheme for realizing the sampling operation based on the cumulative probability distribution sampling circuit has the following defects:

the whole circuit occupies a larger area of the chip. In the prior art, the circuit for implementing the sampling operation includes sub-circuits such as a pseudo-random number generating circuit, an accumulated probability distribution function memory table, and a search circuit, wherein the pseudo-random number generating circuit is typically implemented by a linear feedback shift register (Linear Feedback Shift Register, LFSR) circuit, the number of registers in the LFSR circuit is typically referred to as the number of stages of the LFSR, the sequence of data currently stored in each register in an LFSR circuit is typically referred to as a state, and an n-stage LFSR circuit stores at most 2 ⁿ -1 state, after the LFSR circuit outputs one bit, complemented by a feedback function (typically the right-most (end) digital output, and then the overall LFSR circuit data is shifted one bit to the right), the LFSR circuit moves to the next state. For example, a 3-stage LFSR circuit includes 3 linear feedback shift registers, storing at most 3 bits of data simultaneously, and storing at most 2 ³ -1, 7 states. The more random numbers that need to be generated by the sampling operation, the more registers that are needed by the LFSR circuit. In addition, the LFSR circuit also has a certain periodicity, since an n-stage LFSR circuit can only traverse 2 at most ⁿ 1 states, so that when the LFSR circuit is shifted to a certain extent, a repetitive state may occur, and the LFSR circuit is required to include a large number of registers in order to ensure randomness of sampling and sampling accuracy. Except for false followerBesides the number generation circuit, the cumulative probability distribution function memory table is also a register with multiple bits. It can be seen that the pseudo random number generating circuit and the cumulative probability distribution function storage table in the cumulative probability distribution sampling circuit both need a larger number of registers, but in the prior art, the register area is larger, which results in that the cumulative probability distribution sampling circuit needs to occupy a larger chip area, and the overhead of the whole chip area is larger.

In order to solve the problem of large cost of the whole chip area caused by large occupied chip area in the scheme of realizing sampling operation by adopting a cumulative probability distribution sampling circuit in the prior art, the application comprehensively considers the defects in the prior art, and the technical problems to be solved include the following aspects:

sampling circuits or sampling devices are designed that occupy less chip area. In the embodiment of the application, a sampling device for realizing sampling operation by utilizing the characteristic that the polarization direction of a ferroelectric capacitor is turned over according to a certain probability is provided, specifically, when the sampling device is used for sampling a certain random event (such as an event A), the occurrence process of the event A can be simulated through the ferroelectric capacitor, whether various different results corresponding to the event A occur or not is determined, the purpose of sampling the event A is achieved, firstly, the voltage at two ends of the ferroelectric capacitor can be adjusted, so that the turning over probability of the polarization directions of the ferroelectric capacitors is the same as the probability of different results possibly occurring in the event A respectively, and therefore, whether the different results possibly occurring in the event A occur or not can be determined according to the read polarization direction turning over situation of the ferroelectric capacitor, and the purpose of sampling is achieved. In the prior art, the area of the ferroelectric capacitor is smaller than that of the register, and the sampling circuit or the sampling device based on the ferroelectric capacitor provided by the embodiment of the application can reduce the occupation of a sampling circuit unit on the area of a chip, namely the cost on the area of the chip.

In summary, the scheme of sampling by using the cumulative probability distribution sampling circuit in the prior art occupies a larger chip area, and is difficult to satisfy the demands of people for more and stronger functions of the chip. Therefore, the sampling circuit or the sampling device provided by the application can be used for solving the technical problems.

In order to better understand the sampling device provided by the embodiment of the present application, the structure and the applicable scenario of the sampling device provided by the embodiment of the present application will be described in the following exemplary. It can be understood that the structure and the application scenario of the sampling device described in the embodiment of the present application are for more clearly describing the technical solution of the embodiment of the present application, and do not constitute a limitation on the technical solution provided by the embodiment of the present application.

Referring to fig. 1a, fig. 1a is a schematic structural diagram of an electronic device according to an embodiment of the present application, where the electronic device 01 may include one or more main processors 11 and one or more sampling devices 12, and may further include a memory (not shown in the figure). The electronic device may be a Subscriber Unit (Subscriber Unit), a Cellular Phone (Cellular Phone), a Smart Phone (Smart Phone), a Personal Computer (PC), a Personal digital assistant (Personal Digital Assistant, PDA) Computer, a tablet, a handheld device (Handset), a Laptop (Laptop Computer), a machine type communication (Machine Type Communication, MTC) terminal, a Smart wearable device, or the like.

The main processor 11 may be a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), or a chip with other functions, and is configured to send sampling instructions, receive sampling results, and perform other necessary operations. In this embodiment of the present application, the main processor 11 may send a sampling instruction to the controller 121 of the sampling device 12, so that the controller 121 can control the first voltage supply circuit 123 and the second voltage supply circuit 124 to adjust the provided voltages based on the related information (such as X probability values) in the sampling instruction, and set the polarization direction flip probabilities of the plurality of ferroelectric capacitors in the first sampling plane as the corresponding probability values in the sampling instruction; finally, the main processor 11 may receive and analyze the read sampling result of the read circuit 125 for the first sampling plane.

The sampling device 12 includes a controller 121, a first sampling plane 122, a first voltage supply circuit 123, a second voltage supply circuit 124, and a reading circuit 125. Wherein the controller 121 is configured to receive a sampling instruction sent by the main processor 11, and control the first voltage supply circuit 123 and the second voltage supply circuit 124 to adjust the supplied voltage based on the related information included in the sampling instruction; the first sampling plane 122 includes one or more ferroelectric capacitors; the first voltage supply circuit 123 and the second voltage supply circuit 124 respectively supply voltages to the first electrode and the second electrode of one or more ferroelectric capacitors in the first sampling plane 122, so that the polarization direction of the one or more ferroelectric capacitors can be turned over according to the probability value corresponding to the voltage difference between the two ends; the reading circuit 125 is configured to read the polarization directions of the one or more ferroelectric capacitors and send the read directions to the main processor 11.

The memory is used for storing preparation data (such as a mapping table of voltage difference and polarization direction turning probability value) required by the main processor 11 and the sampling device 12 to execute the sampling task, intermediate data generated in the sampling process, and result data after the sampling is completed. The Memory may include one or more Local memories (Local memories), one or more registers (registers), one or more level one caches (L1 caches), one or more level two caches (L2 caches), and various types of buffers (buffers), etc.

In a possible implementation manner, the sampling device in the electronic device provided by the present application may not include the first sampling plane, and referring to fig. 1b, fig. 1b is a schematic structural diagram of another electronic device provided by an embodiment of the present application, where the electronic device 02 provided by the present application may include one or more main processors 21, one or more sampling devices 22, one or more first sampling planes 23, and may further include a memory (not shown in the figure). The functions and connection relationships of each unit in the electronic device 02 may refer to the related descriptions of the electronic device 01, which are not described herein.

As to the specific structure of the sampling device provided by the present application, fig. 1c may be referred to, and fig. 1c is a schematic diagram illustrating the overall structure of the sampling device according to an embodiment of the present application, where the sampling device 12 may include a controller 121, a first sampling plane 122, a first voltage supply circuit 123, a second voltage supply circuit 124, and a reading circuit 125. The controller 121 is connected to the first voltage supply circuit 123, the second voltage supply circuit 124, and the reading circuit 125, and the controller 121 is configured to receive a sampling instruction sent by the main processor 11, control the first voltage supply circuit 123 and the second voltage supply circuit 124 to adjust the provided voltage based on related information included in the sampling instruction, and read the polarization direction of one or more ferroelectric capacitors in the first sampling plane in the control reading circuit 125; the first sampling plane 122 includes one or more ferroelectric capacitors, and the first voltage supply circuit 123 and the second voltage supply circuit 124 are respectively connected to the first electrode and the second electrode of the one or more ferroelectric capacitors in the first sampling plane 122, and supply voltages to them, so that their polarization directions can be reversed according to probability values corresponding to the voltage differences at both ends; the read circuit 125 is connected to the first electrode or the second electrode of one or more ferroelectric capacitors in the first sampling plane.

In a possible implementation manner, the sampling device provided in the embodiment of the present application may not include the first sampling plane, and fig. 1d is a schematic overall structure of another sampling device provided in the embodiment of the present application, and fig. 1d is a schematic diagram of an overall structure of another sampling device provided in the embodiment of the present application, and the sampling device 22 may include a controller 221, a first voltage supply circuit 222, a second voltage supply circuit 223, and a reading circuit 224, where functions and connection relationships of each unit in the sampling device 22 may be referred to the related description of the above-mentioned sampling device 12, and are not repeated herein.

In order to facilitate understanding of the structure of the sampling device and the principle of implementing the sampling operation provided in the embodiments of the present application, a sampling circuit or sampling device suitable for two-class probability distribution is first taken as an example, and further exemplary description is given below. Referring to fig. 2a, fig. 2a is a schematic diagram of a sampling device suitable for a binary probability distribution according to an embodiment of the present application, where the binary sampling device may include two voltage supply circuits (i.e., a first voltage supply circuit and X second voltage supply circuits, X is taken to be 1), a reading circuit, and a sampling plane (e.g., a frame selection portion of (a) in fig. 2 a), the sampling plane includes a ferroelectric capacitor (i.e., X first ferroelectric capacitors, X is taken to be 1), and a controller in the sampling device is connected to the first voltage supply circuit, the second voltage supply circuit, and the reading circuit, respectively (not shown in the figure), and for better understanding, the field effect transistor T is used as the voltage supply circuit in the figure The first voltage supply circuit is used as a second voltage supply circuit, the drain electrode of the field effect transistor T is connected with the upper electrode (corresponding to the first electrode) of the ferroelectric capacitor and is connected with the reading circuit, the digital-to-analog conversion circuit is connected with the lower electrode (corresponding to the second electrode) of the ferroelectric capacitor, wherein the grid electrode of the field effect transistor T is connected with a Control Line (CL), the source electrode of the field effect transistor T is connected with a Bit Line (Bit Line, BL), the on-off state of the field effect transistor T can be controlled by adjusting the voltage on the Control Line, the voltage value provided by the field effect transistor T can be adjusted by adjusting the voltage on the Bit Line side, the Storage Node (Storage Node, SN) is a logical Node which is assumed for easy understanding, and the voltage at the Node is the voltage value V provided by the field effect transistor T _SN A Word Line (WL) is connected to the lower electrode of the ferroelectric capacitor, and when a plurality of ferroelectric capacitors exist in the sampling device, a specific ferroelectric capacitor can be determined by the bit Line and the word Line. In the device shown in fig. 2a (a), the ferroelectric capacitor is generally configured as an upper electrode, a ferroelectric material and a lower electrode, and the basic principle of the sampling device is that the probability of inverting the polarization direction of the ferroelectric capacitor is modulated by the amplitude of a voltage pulse, as shown in fig. 2a (b), the probability of inverting the polarization direction of the ferroelectric capacitor can be modulated by applying different voltages to two ends of the ferroelectric capacitor, for example, the probability corresponding to a voltage difference Vc is p0, and the modulation of the probability p0 of inverting the polarization direction of the ferroelectric capacitor from 0 to 1 can be realized by adjusting the magnitude of Vc. For example, when one event a corresponds to two different results, namely, a true and a false (or yes or no) are satisfied, as shown in fig. 2a (c), the probability of being satisfied is p0, the probability of being false is p1, the probability of inverting the polarization direction of the ferroelectric capacitor is modulated to p0, and when the reading circuit reads the polarization direction inversion condition of the ferroelectric capacitor, if the polarization direction is found to be inverted, it can be considered that the event a is satisfied in the sub-sampling, and otherwise, is not satisfied. It can be understood that the first voltage supply circuit may be a field effect transistor, a digital-to-analog conversion circuit, or other circuits capable of providing voltage; the second voltage supply circuit may be a digital-to-analog conversion circuit, a field effect transistor, or other circuits capable of providing voltage, in which This is not particularly limited. The first electrode of the ferroelectric capacitor may be an upper electrode, or may be a lower electrode, and the second electrode may be an upper electrode, or may be a lower electrode, so long as the first electrode and the second electrode of the ferroelectric capacitor are different electrodes, and the present application is not limited specifically.

In one possible implementation manner, the first voltage supply circuit or the second voltage supply circuit may be integrated in the reading circuit, that is, the reading circuit may supply voltage to the upper electrode or the lower electrode of the ferroelectric capacitor, after the ferroelectric capacitor turns over according to the probability value corresponding to the voltage difference between the two ends, the reading circuit reads out the situation that the polarization direction of the ferroelectric capacitor turns over, so as to further reduce the occupation of the sampling device on the whole chip area.

Further exemplary description will be made using a sampling circuit or sampling device suitable for multi-class probability distribution. Referring to fig. 2b, fig. 2b is a schematic diagram of a sampling device suitable for multi-class probability distribution according to an embodiment of the present application, where the multi-class sampling device may include a field-effect transistor T (i.e., a first voltage supply circuit), a reading circuit, a plurality of digital-to-analog conversion circuits (i.e., X second voltage supply circuits), and a sampling plane (e.g., a frame selection portion of (a) in fig. 2 b), where the sampling plane includes a plurality of ferroelectric capacitors (i.e., X first ferroelectric capacitors), a controller in the sampling device is respectively connected to the first voltage supply circuit, the second voltage supply circuit, and the reading circuit (not shown), and for convenience of understanding, a field-effect transistor T is used as a schematic of the first voltage supply circuit, X digital-to-analog conversion circuits are used as a schematic of the X second voltage supply circuits, drains of the field-effect transistor T are connected to upper electrodes (i.e., corresponding to the first electrodes) of the plurality of ferroelectric capacitors and to the reading circuit, the plurality of ferroelectric capacitors are connected to lower electrodes (i.e., corresponding to the second electrodes) of the sampling plane, where the gate-effect transistor T is connected to a Control Line (Bit Line), the Control Line (BL) is connected to a Control Line) of a Line (BL) which can be turned on or off by a Bit Line) at an adjustable voltage value (BL) of the Line voltage Line side of the Line (BL) of the Line) is provided A Storage Node (SN) is a logical Node assumed for easy understanding, and the voltage at the Node is the voltage value V provided by the fet T _SN A Word Line (WL) is connected to the lower electrode of the ferroelectric capacitor, and a specific ferroelectric capacitor can be determined by the bit Line and the word Line. In the device shown in fig. 2b (a), the basic principle of the sampling device is that the probability of inverting the polarization direction of each ferroelectric capacitor is modulated by the voltage pulse amplitude, as shown in fig. 2b (b), the probability of inverting the polarization direction of different ferroelectric capacitors can be modulated by applying different voltages to two ends of different ferroelectric capacitors, and this process can refer to a two-class probability distribution scenario, which is not described herein. For example, one event a corresponds to a plurality of different results, for example, event a includes a0, a1, a2, …, aS well aS a S different results, aS shown in (C) in fig. 2b, the probability of occurrence of a0 is p0, the probability of occurrence of a1 is p1, the probability of occurrence of aS-1 is pS-1, and the probabilities of polarization direction reversal of a plurality of ferroelectric capacitors (C0 to CS-1) are respectively modulated to p0, p1, …, pS-1; after the polarization direction overturn condition of the ferroelectric capacitors is read by the reading circuit, because mutual exclusion relation exists between different results of actual events, whether each ferroelectric capacitor is overturned or not can be determined one by one based on the reading result of the reading circuit (can be determined one by one according to a certain sequence or can be determined one by one at random), and the polarization direction of the ferroelectric capacitor which is overturned first is taken as a sampling result; if the polarization direction of the last ferroelectric capacitor is not inverted before the last ferroelectric capacitor is determined, whether the polarization direction of the last ferroelectric capacitor is inverted or not can be judged, and the polarization direction of the last ferroelectric capacitor can be considered to be inverted and used as a sampling result. For example, if the polarization direction of one ferroelectric capacitor (e.g., C1) is first found to be inverted, it can be considered that the result a1 of the event a occurs in the sub-sampling; if the polarization direction of C1 is not inverted, judging whether the polarization direction of C2 is inverted, and if the polarization direction of C2 is inverted, considering the result of the event A in the current sampling as a2; if the polarization directions of the front S-2 ferroelectric capacitors are not inverted, the result of the event A in the current sampling is considered aS aS-1. It is to be understood that, The first voltage supply circuit can be a field effect transistor, a digital-to-analog conversion circuit or other circuits capable of providing voltage; the second voltage supply circuit may be a digital-to-analog conversion circuit, a field effect transistor, or other circuits capable of providing voltages, and different second voltage supply circuits corresponding to different ferroelectric capacitors may provide the same voltage or different voltages, which is not limited herein. The first electrode of the ferroelectric capacitor may be an upper electrode, or may be a lower electrode, and the second electrode may be an upper electrode, or may be a lower electrode, so long as the first electrode and the second electrode of the ferroelectric capacitor are different electrodes, and the present application is not limited specifically. It should be noted that the first voltage supply circuit or the second voltage supply circuit may be integrated in the reading circuit, that is, the reading circuit may supply voltage to the upper electrode or the lower electrode of the ferroelectric capacitor. It should be further noted that, the sampling circuit or the sampling device suitable for multi-classification probability distribution provided in the embodiment of the present application is also suitable for a two-classification probability distribution scenario, and only the voltage at two ends of a certain ferroelectric capacitor needs to be adjusted, so that the probability of turning the polarization direction corresponds to the two-classification probability, and other ferroelectric capacitors do not participate in sampling.

The application also provides a sampling device with a three-dimensional structure based on a ferroelectric capacitor array, which can form a three-dimensional array by a plurality of sampling circuits suitable for multi-classification probability distribution, please refer to fig. 3a, fig. 3a is a schematic diagram of a three-dimensional structure of the sampling device provided by the embodiment of the application, the sampling device can include a plurality of sampling planes (i.e. a plurality of first sampling planes), each sampling plane includes a plurality of ferroelectric capacitors (for example, X rows and Y columns, X and Y are greater than 0), the sampling device includes a plurality of field effect transistors (i.e. a plurality of first voltage supply circuits), a plurality of digital-to-analog conversion circuits (i.e. a plurality of groups of X second voltage supply circuits), and a plurality of reading circuits, wherein a controller in the sampling device is respectively connected with the plurality of first voltage supply circuits, the plurality of second voltage supply circuits and the plurality of reading circuits (not shown in the figure), for better understanding, the sampling device uses the field effect transistor T as a schematic representation of the first voltage supply circuits, uses the field effect transistor T as the second voltage supply circuits, and the drain electrode of the field effect transistor T is connected with a corresponding electrode in the same line of the same capacitor as the first voltage supply circuit (i.e. a corresponding electrode in the same plane, i.e. a plurality of X second voltage supply circuits are connected with the ferroelectric circuit (i.e. a vertical electrode and a corresponding to the ferroelectric capacitor is connected with the second electrode). It can be understood that the first voltage supply circuit and the second voltage supply circuit may be field effect transistors, digital-to-analog conversion circuits, or other circuits capable of providing voltages, which are not described herein. It should be noted that, the first electrode and the second electrode of the ferroelectric capacitor may be an upper electrode or a lower electrode, so long as the first electrode and the second electrode are different electrodes, and will not be described herein. The sampling device with the three-dimensional structure can fully utilize the advantages of the array structure and improve the sampling speed.

In a possible implementation manner, the second electrodes of the different ferroelectric capacitors of the same row in the different sampling planes of the sampling device having the three-dimensional structure may share a second voltage supply circuit, fig. 3b may be a schematic three-dimensional structure diagram of another sampling device provided in an embodiment of the present application, where, in a plurality of sampling planes (including the first sampling plane and the second sampling plane), the ferroelectric capacitors of an X-th row in a certain plane and the ferroelectric capacitors of an X-th row having the same value in another plane may respectively share a set of digital-to-analog conversion circuits (i.e., the second electrode of the X-th first ferroelectric capacitor and the second electrode of the X-th third ferroelectric capacitor are connected in parallel with the X-th second voltage supply circuit, and share the second voltage supply circuit), and the controller in the sampling device is respectively connected to the first voltage supply circuit, the second voltage supply circuit and the reading circuit (not shown in the drawing). In the structure of the sampling device, the number of elements in the device is reduced by sharing the second voltage supply circuit, so the sampling device can further reduce the occupation of the chip area.

In one possible implementation manner, in a certain sampling plane of the sampling device having a three-dimensional structure, the first electrodes of the ferroelectric capacitors in different columns may share a first voltage supply circuit, and fig. 3c may be a schematic three-dimensional structure of another sampling device provided in an embodiment of the present application, where x×y ferroelectric capacitors in different columns (e.g., Y columns) in a certain plane (including a first sampling plane and a second sampling plane) may be connected in parallel to the first voltage supply circuit, so as to share the first voltage supply circuit (the first electrode of each of the first ferroelectric capacitors and the first electrode of each of the X second ferroelectric capacitors) in parallel to the first voltage supply circuit. In the structure of the sampling device, the number of elements in the device is reduced by sharing the first voltage supply circuit, so the sampling device can further reduce the occupation of the chip area. Optionally, the first voltage supply circuit may be shared between different sampling planes to supply a voltage to the first electrode of the ferroelectric capacitor in each plane (i.e., the first voltage), and fig. 3d is a schematic three-dimensional structure of another sampling device according to an embodiment of the present application, where the first electrodes of the ferroelectric capacitors in the different sampling planes are connected in parallel to the drain electrode of the field effect transistor T (i.e., the first voltage supply circuit), and the controller in the sampling device is connected to the first voltage supply circuit, the second voltage supply circuit, and the reading circuit (not shown in the figure). Therefore, the sampling device can further reduce the occupation of the chip area.

In a possible implementation manner, in the sampling device with a three-dimensional structure, the first voltage supply circuit, the second voltage supply circuit and the reading circuit may be shared between different sampling planes, and fig. 3e is a schematic three-dimensional structure of another sampling device provided by the embodiment of the present application, where a plurality of ferroelectric capacitors in different sampling planes (including the first sampling plane and the second sampling plane) are connected in parallel to the drain electrode of one field effect transistor T (i.e., the first voltage supply circuit), the ferroelectric capacitors in the same row in different sampling planes are connected in parallel to a set of digital-to-analog conversion circuits (i.e., X second voltage supply circuits), the ferroelectric capacitors in different sampling planes are connected to one reading circuit, and a controller in the sampling device is connected to the first voltage supply circuit, the second voltage supply circuit and the reading circuit, respectively (not shown in the figure). Therefore, the sampling device can further reduce the occupation of the chip area.

A control method of the apparatus having a three-dimensional structure in the above-described sampling apparatus will be exemplarily described below taking a scene of bayesian network reasoning calculation as an example.

Referring to fig. 4, fig. 4 is a flowchart of a control method of a sampling device according to an embodiment of the present application, taking bayesian network inference calculation as an example, starting from a node 0 (i.e. an input node) of a bayesian network until an output node, including the following steps S400 to S402:

Step S400: the ferroelectric capacitor is initialized.

Specifically, the ferroelectric capacitor C in a certain sampling plane or all sampling planes in the sampling device in fig. 3a may be initialized to an initial state (for example, the first polarization direction or the second polarization direction may correspond to "0" or "1", respectively), for example, the ferroelectric capacitor in the first sampling plane may be initialized to an initial state "0", optionally, the current state ("0" or "1") of the ferroelectric capacitor may be determined first, and then, in combination with the characteristic that the ferroelectric capacitor probabilistically inverts the polarization direction, the voltage difference between the upper electrode and the lower electrode of the ferroelectric capacitor may be adjusted, so that the initialization is completed, for example, when the "0" state of the ferroelectric capacitor is taken as the initial state, the voltage may be adjusted so that the upper electrode voltage is smaller than the lower electrode voltage, and the voltage difference satisfies the inversion threshold.

Alternatively, after initializing the state of the ferroelectric capacitor, the voltage of the digital-to-analog conversion circuit connected to the lower electrode of the ferroelectric capacitor may be set to a constant greater than 0, for example, may be set to half the write voltage (Vw/2), so as to prevent the ferroelectric capacitor from being erroneously turned when the field effect transistor is turned on.

Alternatively, the ferroelectric capacitor may be initialized before the controller of the sampling device receives the sampling instruction of the main processor, or may be initialized after the controller of the sampling device receives the sampling instruction. Wherein the sampling instruction may include a probability value that a different result of each node in the bayesian network may occur, and the probability value may be represented based on a byte state and a byte length, for example, the byte state representing a certain probability value P is 00011101 (29 after binary decimal) and the byte length thereof is 8 (that is, 256 states may be represented), and the probability value P may be 29/256, about 11.33%.

Step S401: and adjusting the voltages at two ends of the ferroelectric capacitor according to the probability value of the nth node and the sampling result of the father node.

Specifically, after initialization is completed, the voltage difference between the upper electrode and the lower electrode of the ferroelectric capacitor is adjusted again, so that the polarization direction overturning probability corresponding to the adjusted voltage difference is equal to the probability value of each type of result of the node 0 of the bayesian network, optionally, assuming that the upper electrode of the ferroelectric capacitor is connected with the field effect transistor, the field effect transistor can be conducted by applying voltage to CL, thereby precharging the logic node SN to Vpre (i.e. the voltage value which can be provided by the field effect transistor), and adjusting the voltage value provided by the digital-to-analog conversion circuit which is connected with the other end of the ferroelectric capacitor of the first sampling plane. In the bayesian network, a parent node is a node before a current node, and if the current node is an input node, the parent node is not present. For sampling of non-input nodes, the polarization direction flip probability of the ferroelectric capacitor can be determined according to the sampling result of the father node and the conditional probability of the node and the father node.

Step S402: and reading the sampling result of the nth node.

Specifically, after voltage is applied to two ends of the ferroelectric capacitor, the polarization direction inversion condition of the ferroelectric capacitor can be read out through the reading circuit, and because different results of actual events generally have mutual exclusion relation, whether each ferroelectric capacitor is inverted or not can be determined one by one based on the reading result of the reading circuit (can be determined one by one according to a certain sequence or can be determined one by one at random), and the polarization direction of the ferroelectric capacitor which is inverted first is taken as a sampling result of the Bayesian network node 0; if the polarization direction of the last ferroelectric capacitor is still not inverted when the last ferroelectric capacitor is determined, whether the polarization direction of the last ferroelectric capacitor is inverted or not can be judged, and the polarization direction of the last ferroelectric capacitor can be considered to be inverted and used as a sampling result of the Bayesian network node 0. It will be appreciated that the ferroelectric capacitors of all columns in the first sampling plane may participate in the sampling of node 0, and that node 0 may be considered sampled Y times when all columns participate in the sampling simultaneously. After the sampling of the node 0 is completed, the node 1 of the bayesian network may be sampled by using the second sampling plane, optionally, the ferroelectric capacitor of the second sampling plane may be initialized to an initial state (or may be initialized together when the first sampling plane is initialized), then the voltage of the field effect transistor or the digital-analog conversion circuit is adjusted according to the conditional probability value of the bayesian network (that is, the occurrence probability of different results of the node 1 under the condition that different results of the node 0 occur), so that the turning probability of the polarization direction of the ferroelectric capacitor is equal to the conditional probability value corresponding to the node 1, and finally the sampling result of the node 1 is read by using the reading circuit. Understandably, the subsequent nodes in the bayesian network also perform the processes of initializing an initial state, adjusting a voltage difference, and reading a turnover condition until sampling of the output node is completed, and finally outputting a final result, thereby determining the relationship between the output node and the input node.

It should be noted that, the inversion probability of the polarization direction of the ferroelectric capacitor is related to the current state of the ferroelectric capacitor, for example, if the current state of the ferroelectric capacitor is "0", the voltage of the upper electrode of the ferroelectric capacitor needs to be set to be greater than the voltage of the lower electrode, so that the state "0" of the polarization direction can be inverted to the state "1" of the polarization direction according to a certain probability; if the current state of the ferroelectric capacitor is "1", the voltage of the upper electrode of the ferroelectric capacitor needs to be set smaller than the voltage of the lower electrode, so that the state "1" of the polarization direction can be inverted to the state "0" of the polarization direction according to a certain probability. Therefore, if the state "0" is positioned in the initial state, the upper electrode voltage may be set to be smaller than the lower electrode voltage and the voltage difference may be made to satisfy the threshold value when the ferroelectric capacitor is initialized; if the state "1" is positioned in the initial state, the upper electrode voltage may be set to be greater than the lower electrode voltage and the voltage difference may be set to satisfy the threshold value when the ferroelectric capacitor is initialized.

In the scenario taking the bayesian network reasoning calculation as an example, considering that the number of times of turning the polarization direction of the ferroelectric capacitor is limited, different nodes of the bayesian network are sampled by using different sampling planes, and loads can be distributed on the different sampling planes, so that the number of times of turning the different ferroelectric capacitors can be balanced, the service life of the sampling device is prolonged, and the maintenance cost is reduced. It can be understood that all the sampling planes in the above-mentioned sampling device may be used to sample the nodes in the bayesian network sequentially at the same time, or the same sampling plane may be used to sample continuously until the number of times of turning the ferroelectric capacitor polarization direction in the sampling plane reaches the upper limit, and then the sampling is performed by other sampling planes, which is not limited herein specifically. In addition, the number of results that may occur at different nodes of the bayesian network may be the same or different, and in general, the number of lines of ferroelectric capacitors in the sampling plane may be greater than or equal to the number of results that may occur at the node, that is, when the ferroelectric capacitors in the same line correspond to different results at different nodes, the number of lines may occur to be greater than the number of results at the node, and the number of ferroelectric capacitors may not participate in sampling at the current node. Optionally, when the probability value of the bayesian network is obtained, it can determine how many ferroelectric capacitors in a column are needed, so that the ferroelectric capacitors in other rows can be prevented from being sampled by turning off the voltages at one ends of the ferroelectric capacitors in other rows, and the reading circuit can only turn over the polarization direction of the ferroelectric capacitors which are sampled during reading.

As can be appreciated, when the sampling operation is implemented by the sampling device, because the implementation essence of the sampling device is to simulate the occurrence process of a probability event by utilizing the characteristic that the polarization direction of one or more ferroelectric capacitors is turned over according to a certain probability, and determine whether various different results corresponding to the event occur, so as to implement the sampling operation, unlike the scheme that the sampling operation is implemented by utilizing a large number of registers in the prior art, the area of the ferroelectric capacitors is smaller than that of the registers in the prior art.

The application also provides a semiconductor chip comprising the sampling device provided in all the above embodiments of the application. It will be appreciated that the functions and roles of the parts in the sampling device may be correspondingly referred to the specific implementation manner in the embodiments in fig. 1a to fig. 4, and are not repeated herein.

The application also provides electronic equipment comprising the sampling device provided in all the embodiments of the application. It will be appreciated that the functions and roles of the parts in the sampling device may be correspondingly referred to the specific implementation manner in the embodiments in fig. 1a to fig. 4, and are not repeated herein. Optionally, the electronic device may further comprise a communication interface for the electronic device to communicate with other devices or communication networks.

The application also provides electronic equipment which has the function of realizing the control method of any one of the sampling devices. The functions can be realized by hardware, and can also be realized by executing corresponding software by hardware. The hardware or software includes one or more modules corresponding to the functions described above.

The present application provides a computer storage medium storing a computer program which, when executed by a sampling device, enables the sampling device to perform the control method flow described above.

The present application provides a computer program comprising instructions which, when executed by a sampling device, enable the sampling device to perform the control method flow described above.

The application provides a chip system, which comprises any one of the sampling devices. In one possible design, the system-on-chip further includes a processor and a memory for holding necessary or relevant program instructions and data for the sampling device and the processor. The chip system can be composed of chips, and can also comprise chips and other discrete devices.

The application provides a system-on-chip (SoC) chip, which comprises a sampling device provided by any one of the implementation modes, a processor coupled with the sampling device, an internal memory and an external memory. The SoC chip may be formed by a chip, or may include a chip and other discrete devices.

It should be noted that, the connection relationship, such as series connection or parallel connection, in this embodiment refers to electrical connection, which may be not only direct connection through a wire, but also coupling through other electrical functions.

In the foregoing embodiments, the descriptions of the embodiments are emphasized, and for parts of one embodiment that are not described in detail, reference may be made to related descriptions of other embodiments. The above embodiments are only for illustrating the technical solution of the present application, and not for limiting the same; although the application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. The sampling device is characterized by comprising a first sampling plane, a first voltage supply circuit, X second voltage supply circuits, a controller and a reading circuit, wherein the first sampling plane comprises X first ferroelectric capacitors; x is an integer greater than 0;

wherein, the first electrode of each first ferroelectric capacitor in the X first ferroelectric capacitors is connected with the first voltage supply circuit; the first voltage supply circuit is used for supplying a first voltage to the first electrode of each first ferroelectric capacitor;

the second electrode of the X first ferroelectric capacitor is connected with the X second voltage supply circuit; x is 1, 2, … … and X, and the xth second voltage supply circuit is used for supplying a second voltage to the second electrode of the xth first ferroelectric capacitor;

the controller is respectively connected with the first voltage supply circuit and the X second voltage supply circuits; the controller is used for: receiving a sampling instruction, wherein the sampling instruction comprises X probability values; controlling the first voltage supply circuit and/or the X second voltage supply circuits to adjust the first voltage and/or the second voltage respectively based on the X probability values; the voltage difference between the first voltage and the second voltage on the xth first ferroelectric capacitor corresponds to an xth probability value of the X probability values;

The reading circuit is used for reading the polarization direction of each first ferroelectric capacitor; wherein the polarization direction of each of the first ferroelectric capacitors is reversed between a first polarization direction and a second polarization direction based on a voltage difference between the first voltage and the second voltage.

2. The apparatus of claim 1, wherein the first electrode or the second electrode of each of the first ferroelectric capacitors is connected to the read circuit.

3. The device of any one of claims 1-2, wherein the first electrode comprises an upper electrode or a lower electrode and the second electrode comprises an upper electrode or a lower electrode, the first electrode being a different electrode than the second electrode.

4. A device according to any of claims 1-3, wherein the first voltage supply circuit comprises a first field effect transistor or a first digital to analog conversion circuit; the X second voltage supply circuits comprise second field effect transistors or second digital-to-analog conversion circuits.

5. The apparatus of any of claims 1-4, wherein the first voltage supply circuit or the X second voltage supply circuits are integrated in the read circuit.

6. The apparatus of any of claims 1-5, wherein the first sampling plane further comprises X second ferroelectric capacitors, the first electrode of each of the first ferroelectric capacitors and the first electrode of each of the X second ferroelectric capacitors connected in parallel with the first voltage supply circuit, sharing the first voltage supply circuit.

7. The apparatus of any of claims 1-6, wherein the first sampling plane further comprises X second ferroelectric capacitors, the second electrode of the X-th first ferroelectric capacitor and the second electrode of the X-th second ferroelectric capacitor of the X-th second ferroelectric capacitors being connected in parallel with the X-th second voltage supply circuit, sharing the X-th second voltage supply circuit; x is 1, 2, … …, X.

8. The apparatus of any of claims 1-7, wherein the sampling apparatus further comprises a second sampling plane comprising X third ferroelectric capacitors, the first electrode of each of the X third ferroelectric capacitors and the first electrode of each of the first ferroelectric capacitors connected in parallel with the first voltage supply circuit, sharing the first voltage supply circuit.

9. The apparatus of any of claims 1-8, wherein the sampling apparatus further comprises a second sampling plane comprising X third ferroelectric capacitors, the second electrode of the X-th first ferroelectric capacitor and the second electrode of the X-th third ferroelectric capacitor being connected in parallel with the X-th second voltage supply circuit, sharing the second voltage supply circuit; x is 1, 2, … …, X.

10. The apparatus of any of claims 1-9, wherein the first electrode or the second electrode of each of the first ferroelectric capacitors is connected in parallel with the read circuit, sharing the read circuit; the first sampling plane further includes X second ferroelectric capacitors, and the first electrode or the second electrode of each of the first ferroelectric capacitor and the X second ferroelectric capacitors is connected in parallel with the reading circuit, sharing the reading circuit.

11. The apparatus of any of claims 1-10, wherein the sampling apparatus further comprises a second sampling plane comprising X third ferroelectric capacitors, the first electrode or the second electrode of each of the first ferroelectric capacitors and the X third ferroelectric capacitors being connected in parallel with the read circuit, sharing the read circuit.

12. The apparatus of any of claims 1-11, wherein when a voltage difference between the first voltage and the second voltage is greater than or equal to a preset threshold, a polarization direction of the corresponding first ferroelectric capacitor is flipped between the first polarization direction and the second polarization direction; and when the voltage difference is smaller than the preset threshold value, the polarization direction of the corresponding first ferroelectric capacitor is turned over between the first polarization direction and the second polarization direction according to the probability value corresponding to the voltage difference.

13. A sampling device, characterized in that the sampling device comprises a first voltage supply circuit, X second voltage supply circuits, a controller and a reading circuit, the sampling device is coupled with a first sampling plane, and the first sampling plane comprises X first ferroelectric capacitors; x is an integer greater than 0;

14. A ferroelectric capacitor array, wherein the ferroelectric capacitor array comprises a first sampling plane, the first sampling plane comprises X first ferroelectric capacitors, the first sampling plane is coupled with a sampling device, and the sampling device comprises a first voltage supply circuit, X second voltage supply circuits, a controller and a reading circuit; x is an integer greater than 0;

15. A method of controlling a sampling device, the method being applicable to a sampling device according to any one of claims 1 to 13, the method comprising:

the controller controls the first voltage supply circuit and/or the X second voltage supply circuits to perform first adjustment on the first voltage and/or the second voltage, and the polarization direction of each first ferroelectric capacitor is initialized to be the first polarization direction;

Receiving, by the controller, a sampling instruction, the sampling instruction comprising X probability values; the first voltage supply circuit and/or the X second voltage supply circuits are/is controlled to carry out second adjustment on the first voltage and/or the second voltage based on the X probability values, and the voltage difference between the first voltage and the second voltage on the xth first ferroelectric capacitor corresponds to the xth probability value in the X probability values;

reading the polarization direction of each first ferroelectric capacitor of the ferroelectric capacitors through the reading circuit; wherein a polarization direction of each of the first ferroelectric capacitors is flipped from the first polarization direction to the second polarization direction based on a voltage difference of the first voltage and the second voltage.

16. The method of claim 15, wherein the method further comprises:

when the first sampling plane further includes X second ferroelectric capacitors, a polarization direction of each of the second ferroelectric capacitors is read by the reading circuit.

17. The method of any one of claims 15-16, wherein the method further comprises:

when the sampling device further comprises a second sampling plane, the second sampling plane comprises X third ferroelectric capacitors, and the polarization direction of each third ferroelectric capacitor is read by the reading circuit.

18. An electronic device comprising the sampling apparatus of any one of claims 1-13, the electronic device further comprising a main processor coupled to the sampling apparatus, the main processor configured to send sampling instructions to the sampling apparatus and receive sampling results of the sampling apparatus; the electronic device further comprises a memory for storing program instructions and data necessary for the main processor and the sampling means to run.