WO2023211509A1 - Crossbar array with self-formed micro channel insulator metal transition and self-aligned to rram filament - Google Patents

Crossbar array with self-formed micro channel insulator metal transition and self-aligned to rram filament Download PDF

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Publication number
WO2023211509A1
WO2023211509A1 PCT/US2022/071983 US2022071983W WO2023211509A1 WO 2023211509 A1 WO2023211509 A1 WO 2023211509A1 US 2022071983 W US2022071983 W US 2022071983W WO 2023211509 A1 WO2023211509 A1 WO 2023211509A1
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WIPO (PCT)
Prior art keywords
forming layer
filament
channel
rram
self
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Application number
PCT/US2022/071983
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French (fr)
Inventor
Minxian ZHANG
Ning GE
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Tetramem Inc.
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Publication date
Application filed by Tetramem Inc. filed Critical Tetramem Inc.
Priority to PCT/US2022/071983 priority Critical patent/WO2023211509A1/en
Publication of WO2023211509A1 publication Critical patent/WO2023211509A1/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/24—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/20—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes
    • H10B63/22—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes of the metal-insulator-metal type
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays

Definitions

  • the present disclosure generally related to a crossbar array circuit with an Insulator- Metal Transition (IMT) and a Resistive Random-Access Memory (RRAM) and more specifically to a crossbar array circuit with self-formed micro channels in IMT and selfaligned micro channels to filaments in the RRAM.
  • IMT Insulator- Metal Transition
  • RRAM Resistive Random-Access Memory
  • a crossbar array circuit may include horizontal metal wire rows and vertical metal wire columns (or other electrodes) intersecting with each other, with crossbar devices formed at the intersecting points.
  • the crossbar array may be used in non-volatile solid-state memory, signal processing, control systems, high-speed image processing, neural network, and other applications.
  • An RRAM is a two-terminal passive device that is capable of changing resistance upon sufficient electrical stimulations, which have attracted significant attention for high- performance nonvolatile memory applications.
  • the resistance of the RRAM may be electrically switched between two states: high-resistance state (HRS) and a low-resistance state (LRS).
  • HRS high-resistance state
  • LRS low-resistance state
  • the switching event from HRS to LRS is called “Set” or “On” switching process.
  • the switching from LRS to HRS is called “Reset” or “Off’ switching process.
  • a selector is required for voltage delivery to a selected RRAM device, to reduce sneak path current, to improve read and write operation, and to reduce array’s power consumption.
  • Transistor has been used as the selector to form a one transistor and one memristor (1T1R) structure. Since the transistor is a three-terminal device, and it may need to deliver high reset current, its size is large which increases silicon area and cost.
  • the technology disclosed is a crossbar array circuit with an IMT and an RRAM and more specifically to a crossbar array circuit with self-formed micro channels in the IMT and self-aligned the micro channels to filaments in the RRAM are disclosed.
  • an apparatus includes: a bottom electrode; a filament forming layer formed on the bottom electrode; a channel forming layer formed on the filament forming layer; and a top electrode formed on the channel forming layer, wherein the filament forming layer is configured to form a filament within the filament forming layer, and the channel forming layer is configured to form a channel within the channel forming layer when applying a switching voltage upon the filament forming layer and the channel forming layer.
  • a material of the filament forming layer includes TaO x (where x ⁇ 2.5), HfO x (where x ⁇ 2), TiOx(where x ⁇ 2.0), or the combination thereof.
  • a material of the channel forming layer includes Nb20s, NbCh, V2O5, VO2, Ti2C>3, Ti2C>5, TiCh, LaCoCh, SmNiCh, or the combination thereof.
  • a material of the bottom electrode and/or the top electrode includes Pd, Pt, Ir, W, Ta, Hf, Nb, V, Ti, TiN, TaN, NbN, or the combination of other conductive materials thereof.
  • a material of the channel includes VO2, NbCh, V2O5/VO2, Nb2Os/NbO2, or the combination thereof.
  • a material of the filament includes an oxygen vacancy rich material.
  • the channel forming layer includes an IMT, a Mott transition, or an NDR.
  • the filament forming layer includes an RRAM.
  • the channel forming layer is configured to form the IMT channel within the channel forming layer when a Joule heating is occurred from the filament forming layer.
  • the apparatus further includes: a column wire connecting to the bottom electrode; and a row wire connecting to the top electrode.
  • FIG. 1 is a block diagram illustrating an example crossbar circuit in accordance with some implementations of the present disclosure.
  • FIG. 2 is a block diagram illustrating an example cross-point device formed between a first row electrode and a first column electrode of the crossbar circuit in accordance with some implementations of the present disclosure.
  • FIGS. 3 A-3C show charts illustrating schematic 1 S 1R switching I-V curves of some implementations of the present disclosure.
  • FIG. 4 shows one example of the selector in accordance with some implementations of the present disclosure.
  • FIG. 5 shows a block diagram illustrating the 1S1R stack with no filament and no channel in accordance with the implementations of the present disclosure.
  • FIG. 6A shows a block diagram illustrating the 1S1R stack with a filament formed upon an initial current/voltage in accordance with the implementations of the present disclosure.
  • FIG. 6B shows a block diagram illustrating the 1S1R stack with the filament and a channel formed upon a switching current/voltage in accordance with the implementations of the present disclosure.
  • FIG. 7 shows example of a biasing scheme for a crossbar array when writing to a cell.
  • FIG. 8A shows a calculated phase diagram for the system Nb-0 illustrating an equilibrium between NbCF and Nb2Os.
  • FIG. 8B shows a diagram of conductivity and magnetic susceptibility vs. (reciprocal) temperature illustrating some properties for Nb-0 system.
  • FIG. 9A shows a section of the V-0 phase diagram involving VO2-V2O5 system.
  • FIG. 9B shows VO2 resistivity change with temperature.
  • FIG. 10 shows a thermodynamic estimation diagram illustrating Gibbs potential change per gram atom of different metals of the IMT material.
  • FIG. 11 shows a process flowchart of the self-formed IMT channels and self-aligned the channels to filaments in the RRAM.
  • a crossbar array circuit with self-formed IMP micro channels and self-aligned the micro channels to filaments in the RRAM is provided.
  • the technologies described in the present disclosure may provide the following technical advantages.
  • the disclosed technology provides a distinct design of a self-formed channel, volatile, high non-linearity and threshold switching IMT to be a selector and a non-volatile RRAM to be a memristor which forms a one selector one memristor (1S1R) structure of the crossbar array circuit.
  • the structural design of IMT and RRAM stack may reduce sneaky path current, improve read and write operation, and reduce array’s power consumption.
  • the self-formed channels and self-aligned to filaments design of the IMT may provide a higher current density and a higher non-linearity which is highly desirable.
  • the selection of IMT material may make the self-formed channels selfalign to filaments of the RRAM under an operating temperature of the crossbar array circuit.
  • the disclosed technology may also provide technical advantages in applications such as smart wearable electronics, neural networks, signal processing, image recognition, etc. Systems and methods of forming a crossbar array with self-formed micro channel IMT and self-aligned to RRAM filaments are therefore desired.
  • FIG. 1 is a block diagram 100 illustrating an example crossbar circuit 110 in accordance with some implementations of the present disclosure.
  • the crossbar circuit 110 includes a first row electrode 101, a first column electrode 102, and a cross-point device 103.
  • FIG. 2 is a block diagram 200 illustrating an example cross-point device 203 formed between a first row electrode 201 and a first column electrode 202 of the crossbar circuit 110 described above.
  • the cross-point device 203 includes a 1S1R stack 2031.
  • FIGS. 3A-3C show charts 310, 320, and 330 illustrating schematic 1S1R cell switching I-V curves of some implementations of the present disclosure.
  • the RRAM switches between LRS and HRS.
  • FIG. 3B shows an IV curve of a selector which has a threshold switching feature that when the voltage is higher than threshold voltage Vth, selector’s resistance is much lower the that of the RRAM.
  • FIG. 3C shows an IV curve of a 1 SIR cell which has a threshold switching feature and an RRAM feature that switching between LRS and HRS. It shows when V ⁇ Vth, the 1S1R cell resistance is dominated by the selector. When V>Vth, the 1S1R cell resistance is dominated by RRAM.
  • a conventional selector may be a transistor which is a three- terminal device and may be required to deliver high current, its size can be large which may increase silicon area and cost.
  • Other selectors may be serially connected with the memristor by an additional electrode between selector and memristor.
  • a simplified layer stack of 1 SIR including a special selector and its matching memristor is provided.
  • FIG. 4 shows one example of the selector in accordance with the implementations of the present disclosure. It is called an insulator-metal transition (IMT), a Mott transition, or a negative-differential-resistance (NDR). IMT may be N-shaped which is voltage controlled, or S-shaped which is current controlled. FIG. 4 is an S -shaped/ current controlled IMT.
  • the IV curve of the S-shaped IMT can be divided into three parts: Part 1 is the device in high resistance state (HRS) which has positive resistance; Part 2 is the device in transition from HRS to LRS, where the resistance is negative; and Part 3 is the device in low resistance state (LRS) which has positive resistance.
  • HRS high resistance state
  • Part 2 is the device in transition from HRS to LRS, where the resistance is negative
  • Part 3 is the device in low resistance state (LRS) which has positive resistance.
  • IMT switch When current flow through the device, the joule heating may increase device temperature to above its IMT temperature, device resistance may be dramatically changed due to the phase change. When the current is removed, the device can be cooled down and the device returned to HRS. Therefore, IMT switch may be nonlinear and volatile.
  • FIG. 5 shows a block diagram 500 illustrating the virgin or fresh or as fabricated device 1S1R stack 550 with no filament and no channel in accordance with the implementations of the present disclosure.
  • the 1S1R stack 550 is the same as the 1S1R stack 2031 in FIG. 2.
  • the 1S1R stack 550 includes a bottom electrode 501, a filament forming layer 503 formed on the bottom electrode 501, a channel forming layer 505 formed on the filament forming layer 503, and a top electrode 507 formed on the channel forming layer 505.
  • the filament forming layer 503 should be close enough to provide joule heat to the channel forming layer 505 to achieve the self-forming and self-aligned features. It should be pointed out that the positions of layer 503 and 505 can be exchanged.
  • a material of the filament forming layer 503 includes TaO x (where x ⁇ 2.5), HfO x (where x ⁇ 2.0), TiO x ( where x ⁇ 2.0), or the combination thereof.
  • a material of the channel forming layer 505 includes Nb20s, NbCh, V2O5, VO2, Ti2Ch, Ti20s, TiCh, LaCoCh, SmNiCh, or the combination thereof.
  • a material of the bottom electrode 501 and/or the top electrode 507 includes Pd, Pt, Ir, W, Ta, Hf, Nb, V, Ti, TiN, TaN, NbN, or the combination or of alloy other conductive materials thereof.
  • FIG. 6A shows a block diagram 600 illustrating the 1S1R stack 630 with a filament 6031 formed upon an initial current/voltage in accordance with the implementations of the present disclosure.
  • the filament 6031 is formed within the filament forming layer 603 which may be seen as a filament in an RRAM.
  • an oxygen vacancy rich filament (i.e., Ta-rich or Hf-rich) 6031 is formed in the filament forming layer 603. Since the filament in RRAM concentrated all current to a local area at the RRAM/selector interface (which is the interface of the filament forming layer 603 and the channel forming layer 605), the channel forming layer 605 began to be heated at that local area.
  • FIG. 6B shows a block diagram 650 illustrating the 1S1R stack 680 with the filament 6031 and a channel 6051 formed upon a switching current/voltage in accordance with the implementations of the present disclosure.
  • the filament 6031 is formed within the filament forming layer 603 and the channel 6051 is formed within the channel forming layer 605.
  • Factor 1 is the joule heating from filament 6031, that the heat can improve the oxygen diffusion exponentially in the volume marked by channel 6051.
  • Factor 2 is the oxygen vacancy rich composition in filament 6031, that can drive oxygen to diffuse from volume market by channel 6051 to filament 6031.
  • channel 6051 becomes oxygen poor compared to the rest channel forming layer 605. This will enable most current to pass through channel 6051, while little or no leakage current will pass through the rest channel forming layer 605.
  • a NbCh channel 6051 is formed within the Nb20s channel forming layer 605. Since Nb20s is dielectric which has low leakage current, all the switching current flow through NbO2 channel. Therefore, an electrical path is formed by the NbCh channel 6051 and the Ta-rich filament 6031. This is so-called the process of selfformed micro channels of the IMT (channel forming layer) and self-aligned the channels to the filaments of RRAM (filament forming layer).
  • the self-formed NbCh micro channel is surrounded by Nb20s dielectric matrix, all current will pass the micro channel with very high current density, the intense joule heating can effectively promote insulator-metal transition and may provide a higher nonlinearity from the insulator-metal transition.
  • Nb20s 2NbC>2 + O (in Ta-rich filament)
  • a material of the channel 6051 includes VO2, NbCh, V2O5/VO2, Nb2Os/NbO2, or the combination thereof.
  • a material of the filament 6031 includes an oxygen vacancy rich material.
  • the filament state of RRAM will not be changed by just removing the current and will stay in its resistance state. Therefore, the RRAM is still a non-volatile switching and so as the entire 1S1R stack. It is noted that the RRAM filament state may be changed only when there is a high current/voltage applied to set or reset the RRAM.
  • FIG. 7 shows a block diagram 700 illustrating an example of a biasing scheme for a crossbar array when writing to a cell.
  • the top row line is biased at +V
  • the right column line is biased at ground
  • all the other row lines and column lines are biased at V/2.
  • the first cell 701 is the selected cell, where the selector in the first cell 701 is at full voltage V and is in LRS.
  • Second cells 703 and third cells 705 have selectors at half voltage V/2 (half selected cells) and are in HRS (please see FIG. 3B that half voltage is lower than threshold voltage and full voltage is higher than threshold voltage).
  • Fourth cells 707 are at zero voltage (unselected cells) and selectors in the fourth cells 707 are in HRS. Therefore, there is only one selected selector is at LRS and the rest selectors (half select and unselected) are all at HRS. Accordingly, the sneak path current is mitigated in a crossbar array in accordance with the implementations of the present disclosure.
  • FIG. 8A shows a calculated phase diagram 800 for the system Nb-0 illustrating an equilibrium between NbCh and Nb2Os
  • FIG. 8B shows a diagram 850 of conductivity and magnetic susceptibility vs. (reciprocal) temperature illustrating some properties for NbCF system.
  • NbCh will be transformed to metallic NbCh around 800°C.
  • Nb2Os is a dielectric material with a dielectric constant around 41 and a band gap around 3.4 eV, very little leakage current can pass through Nb2Os. All current will pass through the IMT channel, to reach a high current density, to promote the insulator metal transition, and to achieve a high selector ratio.
  • FIG. 9A shows a section of V-0 binary phase diagram 900 involving the VO2-V2O5 system and FIG. 9B shows a diagram 950 illustrating VO2 resistivity change by temperature.
  • VO2 is in the insulating state, and will be transformed to metallic VO2 around 67°. It is, therefore, a good oxide candidate for a low switching current/voltage IMT operation.
  • FIG. 10 shows a thermodynamic estimation diagram 1000 illustrating Gibbs potential change per gram atom of different metals of the IMT material.
  • a reaction involving Nb2Os and NbCh can be spontaneous as the Gibbs energy for the following reaction might be negative:
  • Nb2Os 2NbO2 + O (in Ta-rich filament)
  • FIG. 11 shows a process flowchart 1100 of the self-formed IMT channels and selfaligned the channels to filaments in the RRAM. As shown in FIG. 11, during the initial state also shown in FIG. 5, a 1 SIR stack is fabricated and both the filaments in RRAM and channels in IMT are not formed yet during this stage.
  • the filament in RRAM is formed and the Joule heating from filament and oxygen vacancy rich nature of the filament makes oxygen to diffuse from adjacent channel forming layer into the filament, and the channel of IMT forms as well.
  • An electrical path is thus formed involving IMT channel and RRAM filament, as shown in FIG. 6B.
  • the voltage polarity is reversed.
  • the voltage will first drop across selector, the high current density through IMT channel will cause IMT channel to change from insulative to metallic state from joule heating. Subsequently, the voltage will then drop across the RRAM cell to complete to reset operation.
  • the filament in RRAM is raptured after reset, the raptured filament connected with the IMT channel is still the lowest resistance path through the 1 S 1R cell that the current will always flow through the path along the IMT channel and the RRAM filament during 1S1R operation.
  • the phrase “if it is determined (that a stated condition precedent is true)” or “if (a stated condition precedent is true)” or “when (a stated condition precedent is true)” may be construed to mean “upon determining” or “in response to determining” or “in accordance with a determination” or “upon detecting” or “in response to detecting” that the stated condition precedent is true, depending on the context.

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Abstract

Crossbar array circuits with self-formed channels in the IMT and self-aligned the channels to filaments in the RRAM are disclosed. An example apparatus includes: a bottom electrode; a filament forming layer formed on the bottom electrode; a channel forming layer formed on the filament forming layer; and a top electrode formed on the channel forming layer, wherein the filament forming layer is configured to form a filament within the filament forming layer, and the channel forming layer is configured to form a channel within the channel forming layer when applying a switching voltage upon the filament forming layer and the channel forming layer.

Description

CROSSBAR ARRAY WITH SELF-FORMED MICRO CHANNEL INSULATOR METAL TRANSITION AND SELF-ALIGNED TO RRAM FILAMENT
TECHNICAL FIELD
[0001] The present disclosure generally related to a crossbar array circuit with an Insulator- Metal Transition (IMT) and a Resistive Random-Access Memory (RRAM) and more specifically to a crossbar array circuit with self-formed micro channels in IMT and selfaligned micro channels to filaments in the RRAM.
BACKGROUND
[0002] Traditionally, a crossbar array circuit may include horizontal metal wire rows and vertical metal wire columns (or other electrodes) intersecting with each other, with crossbar devices formed at the intersecting points. The crossbar array may be used in non-volatile solid-state memory, signal processing, control systems, high-speed image processing, neural network, and other applications.
[0003] An RRAM is a two-terminal passive device that is capable of changing resistance upon sufficient electrical stimulations, which have attracted significant attention for high- performance nonvolatile memory applications. The resistance of the RRAM may be electrically switched between two states: high-resistance state (HRS) and a low-resistance state (LRS). The switching event from HRS to LRS is called “Set” or “On” switching process. Conversely, the switching from LRS to HRS is called “Reset” or “Off’ switching process.
[0004] In an RRAM crossbar array circuit, a selector is required for voltage delivery to a selected RRAM device, to reduce sneak path current, to improve read and write operation, and to reduce array’s power consumption. Transistor has been used as the selector to form a one transistor and one memristor (1T1R) structure. Since the transistor is a three-terminal device, and it may need to deliver high reset current, its size is large which increases silicon area and cost. SUMMARY
[0005] The technology disclosed is a crossbar array circuit with an IMT and an RRAM and more specifically to a crossbar array circuit with self-formed micro channels in the IMT and self-aligned the micro channels to filaments in the RRAM are disclosed.
[0006] In some implementations, an apparatus includes: a bottom electrode; a filament forming layer formed on the bottom electrode; a channel forming layer formed on the filament forming layer; and a top electrode formed on the channel forming layer, wherein the filament forming layer is configured to form a filament within the filament forming layer, and the channel forming layer is configured to form a channel within the channel forming layer when applying a switching voltage upon the filament forming layer and the channel forming layer.
[0007] In some implementations, a material of the filament forming layer includes TaOx (where x < 2.5), HfOx (where x < 2), TiOx(where x < 2.0), or the combination thereof.
[0008] In some implementations, a material of the channel forming layer includes Nb20s, NbCh, V2O5, VO2, Ti2C>3, Ti2C>5, TiCh, LaCoCh, SmNiCh, or the combination thereof.
[0009] In some implementations, a material of the bottom electrode and/or the top electrode includes Pd, Pt, Ir, W, Ta, Hf, Nb, V, Ti, TiN, TaN, NbN, or the combination of other conductive materials thereof.
[0010] In some implementations, a material of the channel includes VO2, NbCh, V2O5/VO2, Nb2Os/NbO2, or the combination thereof.
[0011] In some implementations, a material of the filament includes an oxygen vacancy rich material.
[0012] In some implementations, the channel forming layer includes an IMT, a Mott transition, or an NDR.
[0013] In some implementations, the filament forming layer includes an RRAM.
[0014] In some implementations, the channel forming layer is configured to form the IMT channel within the channel forming layer when a Joule heating is occurred from the filament forming layer.
[0015] In some implementations, the apparatus further includes: a column wire connecting to the bottom electrode; and a row wire connecting to the top electrode. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] FIG. 1 is a block diagram illustrating an example crossbar circuit in accordance with some implementations of the present disclosure.
[0017] FIG. 2 is a block diagram illustrating an example cross-point device formed between a first row electrode and a first column electrode of the crossbar circuit in accordance with some implementations of the present disclosure.
[0018] FIGS. 3 A-3C show charts illustrating schematic 1 S 1R switching I-V curves of some implementations of the present disclosure.
[0019] FIG. 4 shows one example of the selector in accordance with some implementations of the present disclosure.
[0020] FIG. 5 shows a block diagram illustrating the 1S1R stack with no filament and no channel in accordance with the implementations of the present disclosure.
[0021] FIG. 6A shows a block diagram illustrating the 1S1R stack with a filament formed upon an initial current/voltage in accordance with the implementations of the present disclosure.
[0022] FIG. 6B shows a block diagram illustrating the 1S1R stack with the filament and a channel formed upon a switching current/voltage in accordance with the implementations of the present disclosure.
[0023] FIG. 7 shows example of a biasing scheme for a crossbar array when writing to a cell.
[0024] FIG. 8A shows a calculated phase diagram for the system Nb-0 illustrating an equilibrium between NbCF and Nb2Os.
[0025] FIG. 8B shows a diagram of conductivity and magnetic susceptibility vs. (reciprocal) temperature illustrating some properties for Nb-0 system.
[0026] FIG. 9A shows a section of the V-0 phase diagram involving VO2-V2O5 system.
[0027] FIG. 9B shows VO2 resistivity change with temperature.
[0028] FIG. 10 shows a thermodynamic estimation diagram illustrating Gibbs potential change per gram atom of different metals of the IMT material.
[0029] FIG. 11 shows a process flowchart of the self-formed IMT channels and self-aligned the channels to filaments in the RRAM. [0030] The implementations disclosed herein are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings. Like reference numerals refer to corresponding parts throughout the drawings.
DETAILED DESCRIPTION
[0031] A crossbar array circuit with self-formed IMP micro channels and self-aligned the micro channels to filaments in the RRAM is provided. The technologies described in the present disclosure may provide the following technical advantages.
[0032] First, the disclosed technology provides a distinct design of a self-formed channel, volatile, high non-linearity and threshold switching IMT to be a selector and a non-volatile RRAM to be a memristor which forms a one selector one memristor (1S1R) structure of the crossbar array circuit.
[0033] Second, the structural design of IMT and RRAM stack, as described in the present disclosure, may reduce sneaky path current, improve read and write operation, and reduce array’s power consumption.
[0034] Third, the self-formed channels and self-aligned to filaments design of the IMT may provide a higher current density and a higher non-linearity which is highly desirable.
[0035] Fourth, the selection of IMT material may make the self-formed channels selfalign to filaments of the RRAM under an operating temperature of the crossbar array circuit.
[0036] Finally, the disclosed technology may also provide technical advantages in applications such as smart wearable electronics, neural networks, signal processing, image recognition, etc. Systems and methods of forming a crossbar array with self-formed micro channel IMT and self-aligned to RRAM filaments are therefore desired.
[0037] FIG. 1 is a block diagram 100 illustrating an example crossbar circuit 110 in accordance with some implementations of the present disclosure. As shown in FIG. 1, the crossbar circuit 110 includes a first row electrode 101, a first column electrode 102, and a cross-point device 103.
[0038] FIG. 2 is a block diagram 200 illustrating an example cross-point device 203 formed between a first row electrode 201 and a first column electrode 202 of the crossbar circuit 110 described above. The cross-point device 203 includes a 1S1R stack 2031. [0039] FIGS. 3A-3C show charts 310, 320, and 330 illustrating schematic 1S1R cell switching I-V curves of some implementations of the present disclosure. In FIG. 3 A, the RRAM switches between LRS and HRS. FIG. 3B shows an IV curve of a selector which has a threshold switching feature that when the voltage is higher than threshold voltage Vth, selector’s resistance is much lower the that of the RRAM. When the voltage is lower than threshold voltage Vth, the selector’s resistance is much higher than that of RRAM. This is very desirable that in a crossbar array it is possible to have only one selected cell to have voltage above Vth (very low resistance from selector) and the rest cells to have voltage below Vth (very high resistance from selectors). Therefore, the selectors may block the sneaky path current in a crossbar array. FIG. 3C shows an IV curve of a 1 SIR cell which has a threshold switching feature and an RRAM feature that switching between LRS and HRS. It shows when V<Vth, the 1S1R cell resistance is dominated by the selector. When V>Vth, the 1S1R cell resistance is dominated by RRAM.
[0040] As mentioned above, a conventional selector may be a transistor which is a three- terminal device and may be required to deliver high current, its size can be large which may increase silicon area and cost. Other selectors may be serially connected with the memristor by an additional electrode between selector and memristor. In the present implementations, a simplified layer stack of 1 SIR including a special selector and its matching memristor is provided.
[0041] FIG. 4 shows one example of the selector in accordance with the implementations of the present disclosure. It is called an insulator-metal transition (IMT), a Mott transition, or a negative-differential-resistance (NDR). IMT may be N-shaped which is voltage controlled, or S-shaped which is current controlled. FIG. 4 is an S -shaped/ current controlled IMT. The IV curve of the S-shaped IMT can be divided into three parts: Part 1 is the device in high resistance state (HRS) which has positive resistance; Part 2 is the device in transition from HRS to LRS, where the resistance is negative; and Part 3 is the device in low resistance state (LRS) which has positive resistance.
[0042] When current flow through the device, the joule heating may increase device temperature to above its IMT temperature, device resistance may be dramatically changed due to the phase change. When the current is removed, the device can be cooled down and the device returned to HRS. Therefore, IMT switch may be nonlinear and volatile.
[0043] FIG. 5 shows a block diagram 500 illustrating the virgin or fresh or as fabricated device 1S1R stack 550 with no filament and no channel in accordance with the implementations of the present disclosure. In some implementations, the 1S1R stack 550 is the same as the 1S1R stack 2031 in FIG. 2. The 1S1R stack 550 includes a bottom electrode 501, a filament forming layer 503 formed on the bottom electrode 501, a channel forming layer 505 formed on the filament forming layer 503, and a top electrode 507 formed on the channel forming layer 505. In some implementations, there are more layers inserted between the electrode and layers. However, in some implementations, the filament forming layer 503 should be close enough to provide joule heat to the channel forming layer 505 to achieve the self-forming and self-aligned features. It should be pointed out that the positions of layer 503 and 505 can be exchanged.
[0044] In some implementations, a material of the filament forming layer 503 includes TaOx(where x < 2.5), HfOx( where x < 2.0), TiOx( where x < 2.0), or the combination thereof. [0045] In some implementations, a material of the channel forming layer 505 includes Nb20s, NbCh, V2O5, VO2, Ti2Ch, Ti20s, TiCh, LaCoCh, SmNiCh, or the combination thereof.
[0046] In some implementations, a material of the bottom electrode 501 and/or the top electrode 507 includes Pd, Pt, Ir, W, Ta, Hf, Nb, V, Ti, TiN, TaN, NbN, or the combination or of alloy other conductive materials thereof.
[0047] FIG. 6A shows a block diagram 600 illustrating the 1S1R stack 630 with a filament 6031 formed upon an initial current/voltage in accordance with the implementations of the present disclosure. When the initial current/voltage began to apply on the 1 S1R stack 630, the filament 6031 is formed within the filament forming layer 603 which may be seen as a filament in an RRAM. During the forming, an oxygen vacancy rich filament (i.e., Ta-rich or Hf-rich) 6031 is formed in the filament forming layer 603. Since the filament in RRAM concentrated all current to a local area at the RRAM/selector interface (which is the interface of the filament forming layer 603 and the channel forming layer 605), the channel forming layer 605 began to be heated at that local area.
[0048] FIG. 6B shows a block diagram 650 illustrating the 1S1R stack 680 with the filament 6031 and a channel 6051 formed upon a switching current/voltage in accordance with the implementations of the present disclosure. When the switching current/voltage applied on the 1S1R stack 680, the filament 6031 is formed within the filament forming layer 603 and the channel 6051 is formed within the channel forming layer 605. There are two physical factors to self-form the channel 6051 above filament 6031. Factor 1 is the joule heating from filament 6031, that the heat can improve the oxygen diffusion exponentially in the volume marked by channel 6051. Factor 2 is the oxygen vacancy rich composition in filament 6031, that can drive oxygen to diffuse from volume market by channel 6051 to filament 6031. Therefore, the volume market by channel 6051 becomes oxygen poor compared to the rest channel forming layer 605. This will enable most current to pass through channel 6051, while little or no leakage current will pass through the rest channel forming layer 605. For instance, a NbCh channel 6051 is formed within the Nb20s channel forming layer 605. Since Nb20s is dielectric which has low leakage current, all the switching current flow through NbO2 channel. Therefore, an electrical path is formed by the NbCh channel 6051 and the Ta-rich filament 6031. This is so-called the process of selfformed micro channels of the IMT (channel forming layer) and self-aligned the channels to the filaments of RRAM (filament forming layer).
[0049] Since the self-formed NbCh micro channel is surrounded by Nb20s dielectric matrix, all current will pass the micro channel with very high current density, the intense joule heating can effectively promote insulator-metal transition and may provide a higher nonlinearity from the insulator-metal transition.
[0050] It is noted that when local volume Nb20s become local NbCh, the oxygen diffuses to the filament 6031 as:
[0051] Nb20s = 2NbC>2 + O (in Ta-rich filament)
[0052] In some implementations, a material of the channel 6051 includes VO2, NbCh, V2O5/VO2, Nb2Os/NbO2, or the combination thereof.
[0053] In some implementations, a material of the filament 6031 includes an oxygen vacancy rich material.
[0054] Next, when current is off, the heat is dissipated, so the metallic NbCh will be transformed back to the insulative NbCh. It is a volatile switching. Combined all the processes and physical mechanism, local Joule heating from the filaments through micro channels of NbCF makes the channel forming layer 605 (the IMT) to have non-linear I-V, threshold switching, and volatile switching features.
[0055] Meanwhile, when the current is off, the filament state of RRAM will not be changed by just removing the current and will stay in its resistance state. Therefore, the RRAM is still a non-volatile switching and so as the entire 1S1R stack. It is noted that the RRAM filament state may be changed only when there is a high current/voltage applied to set or reset the RRAM.
[0056] FIG. 7 shows a block diagram 700 illustrating an example of a biasing scheme for a crossbar array when writing to a cell. In this example, the top row line is biased at +V, the right column line is biased at ground, all the other row lines and column lines are biased at V/2. The first cell 701 is the selected cell, where the selector in the first cell 701 is at full voltage V and is in LRS. Second cells 703 and third cells 705 have selectors at half voltage V/2 (half selected cells) and are in HRS (please see FIG. 3B that half voltage is lower than threshold voltage and full voltage is higher than threshold voltage). Fourth cells 707 are at zero voltage (unselected cells) and selectors in the fourth cells 707 are in HRS. Therefore, there is only one selected selector is at LRS and the rest selectors (half select and unselected) are all at HRS. Accordingly, the sneak path current is mitigated in a crossbar array in accordance with the implementations of the present disclosure.
[0057] FIG. 8A shows a calculated phase diagram 800 for the system Nb-0 illustrating an equilibrium between NbCh and Nb2Os, and FIG. 8B shows a diagram 850 of conductivity and magnetic susceptibility vs. (reciprocal) temperature illustrating some properties for NbCF system. During the insulating state, generally at room temperature, the NbCh will be transformed to metallic NbCh around 800°C. Since Nb2Os is a dielectric material with a dielectric constant around 41 and a band gap around 3.4 eV, very little leakage current can pass through Nb2Os. All current will pass through the IMT channel, to reach a high current density, to promote the insulator metal transition, and to achieve a high selector ratio.
[0058] FIG. 9A shows a section of V-0 binary phase diagram 900 involving the VO2-V2O5 system and FIG. 9B shows a diagram 950 illustrating VO2 resistivity change by temperature. At room temperature, VO2 is in the insulating state, and will be transformed to metallic VO2 around 67°. It is, therefore, a good oxide candidate for a low switching current/voltage IMT operation.
[0059] FIG. 10 shows a thermodynamic estimation diagram 1000 illustrating Gibbs potential change per gram atom of different metals of the IMT material. A reaction involving Nb2Os and NbCh can be spontaneous as the Gibbs energy for the following reaction might be negative:
[0060] Nb2Os = 2NbO2 + O (in Ta-rich filament)
[0061] FIG. 11 shows a process flowchart 1100 of the self-formed IMT channels and selfaligned the channels to filaments in the RRAM. As shown in FIG. 11, during the initial state also shown in FIG. 5, a 1 SIR stack is fabricated and both the filaments in RRAM and channels in IMT are not formed yet during this stage.
[0062] Next, when increasing the device voltage (or current) to a forming voltage, a filament begins to form in the RRAM cell during this stage, which is also shown in Fig. 6A.
[0063] Next, the filament in RRAM is formed and the Joule heating from filament and oxygen vacancy rich nature of the filament makes oxygen to diffuse from adjacent channel forming layer into the filament, and the channel of IMT forms as well. An electrical path is thus formed involving IMT channel and RRAM filament, as shown in FIG. 6B.
[0064] Next, when a set voltage is applied to 1S1R cell, as a voltage divider, the voltage is initially dropped across the selector, due to the selector’s high resistance (since selectors HRS is much higher than RRAM’s HRS, as shown in FIG. 3). As the IMT channel is embedded within dielectric or semiconductor selector matrix, all current will pass through the IMT channel, the joule heating may cause the IMT channel to effectively change from insulative to metallic states. When the IMT channel is in low resistance state, as a new voltage divider, the voltage will be dropped across the RRAM cell (since selector’s LRS is much lower than RRAM’s LRS, as shown in FIG. 3) to complete the set operation.
[0065] Next, when applying a reset process, the voltage polarity is reversed. The voltage will first drop across selector, the high current density through IMT channel will cause IMT channel to change from insulative to metallic state from joule heating. Subsequently, the voltage will then drop across the RRAM cell to complete to reset operation. Although the filament in RRAM is raptured after reset, the raptured filament connected with the IMT channel is still the lowest resistance path through the 1 S 1R cell that the current will always flow through the path along the IMT channel and the RRAM filament during 1S1R operation.
[0066] Plural instances may be provided for components, operations or structures described herein as a single instance. Finally, boundaries between various components, operations, and data stores are somewhat arbitrary, and particular operations are illustrated in the context of specific illustrative configurations. Other allocations of functionality are envisioned and may fall within the scope of the implementation(s). In general, structures and functionality presented as separate components in the example configurations may be implemented as a combined structure or component. Similarly, structures and functionality presented as a single component may be implemented as separate components. These and other variations, modifications, additions, and improvements fall within the scope of the implementation(s).
[0067] It will also be understood that, although the terms “first,” “second,” etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first column could be termed a second column, and, similarly, a second column could be termed the first column, without changing the meaning of the description, so long as all occurrences of the “first column” are renamed consistently and all occurrences of the “second column” are renamed consistently. The first column and the second are columns both column s, but they are not the same column.
[0068] The terminology used herein is for the purpose of describing particular implementations only and is not intended to be limiting of the claims. As used in the description of the implementations and the appended claims, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
[0069] As used herein, the term “if may be construed to mean “when” or “upon” or “in response to determining” or “in accordance with a determination” or “in response to detecting,” that a stated condition precedent is true, depending on the context. Similarly, the phrase “if it is determined (that a stated condition precedent is true)” or “if (a stated condition precedent is true)” or “when (a stated condition precedent is true)” may be construed to mean “upon determining” or “in response to determining” or “in accordance with a determination” or “upon detecting” or “in response to detecting” that the stated condition precedent is true, depending on the context.
[0070] The foregoing description included example systems, methods, techniques, instruction sequences, and computing machine program products that embody illustrative implementations. For purposes of explanation, numerous specific details were set forth in order to provide an understanding of various implementations of the inventive subject matter. It will be evident, however, to those skilled in the art that implementations of the inventive subject matter may be practiced without these specific details. In general, well- known instruction instances, protocols, structures, and techniques have not been shown in detail.
[0071] The foregoing description, for purpose of explanation, has been described with reference to specific implementations. However, the illustrative discussions above are not intended to be exhaustive or to limit the implementations to the precise forms disclosed. Many modifications and variations are possible in view of the above teachings. The implementations were chosen and described in order to best explain the principles and their practical applications, to thereby enable others skilled in the art to best utilize the implementations and various implementations with various modifications as are suited to the particular use contemplated.

Claims

WHAT IS CLAIMED IS:
1. An apparatus comprising: a bottom electrode; a filament forming layer formed on the bottom electrode; a channel forming layer formed on the filament forming layer; and a top electrode formed on the channel forming layer, wherein the filament forming layer is configured to form a filament within the filament forming layer, and the channel forming layer is configured to form a channel within the channel forming layer when applying a switching voltage upon the filament forming layer and the channel forming layer.
2. The apparatus as claimed in claim 1, wherein a material of the filament forming layer comprises TaOx( where x < 2.5), HfOx( where x < 2), TiOx(where x < 2), or a combination thereof.
3. The apparatus as claimed in claim 1, wherein a material of the channel forming layer comprises Nb20s, V2O5, Ti2Ch, Ti20s, TiCh, LaCoCL, SmNiCL, or a combination thereof.
4. The apparatus as claimed in claim 1, wherein a material of the bottom electrode and/or the top electrode comprise Pd, Pt, Ir, W, Ta, Hf, Nb, V, Ti, TiN, TaN, NbN, or a combination of alloy or other conductive materials thereof.
5. The apparatus as claimed in claim 1, wherein a material of the channel comprises VO2, NbCh, V2O5/VO2, Nb2Os/NbO2, or the combination thereof.
6. The apparatus as claimed in claim 1, wherein a material of the filament comprises an oxygen vacancy rich material.
7. The apparatus as claimed in claim 1, wherein the channel forming layer comprises an IMT, a Mott transition, or an NDR.
8. The apparatus as claimed in claim 1, wherein the filament forming layer comprises an RRAM.
9. The apparatus as claimed in claim 1, wherein the channel forming layer is configured to form the channel within the channel forming layer when a Joule heating is applied from the filament forming layer.
10. The apparatus as claimed in claim 1, further comprises: a column wire connecting to the bottom electrode; and a row wire connecting to the top electrode.
PCT/US2022/071983 2022-04-28 2022-04-28 Crossbar array with self-formed micro channel insulator metal transition and self-aligned to rram filament WO2023211509A1 (en)

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US20140269002A1 (en) * 2013-03-14 2014-09-18 Crossbar, Inc. Two-terminal memory with intrinsic rectifying characteristic
US20170243924A1 (en) * 2014-12-19 2017-08-24 Hewlett Packard Enterprise Development Lp Negative differential resistance (ndr) device based on fast diffusive metal atoms
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US20200312911A1 (en) * 2019-03-27 2020-10-01 Tetramem Inc. Reducing cell-to-cell switch variation in crossbar array circuits

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140269002A1 (en) * 2013-03-14 2014-09-18 Crossbar, Inc. Two-terminal memory with intrinsic rectifying characteristic
US20170243924A1 (en) * 2014-12-19 2017-08-24 Hewlett Packard Enterprise Development Lp Negative differential resistance (ndr) device based on fast diffusive metal atoms
US20190363250A1 (en) * 2018-05-23 2019-11-28 Purdue Research Foundation Phase transition based resistive random-access memory
US20200312911A1 (en) * 2019-03-27 2020-10-01 Tetramem Inc. Reducing cell-to-cell switch variation in crossbar array circuits

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