WO2023208039A1 - 一种主板、内存系统及数据传输方法 - Google Patents

一种主板、内存系统及数据传输方法 Download PDF

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Publication number
WO2023208039A1
WO2023208039A1 PCT/CN2023/090842 CN2023090842W WO2023208039A1 WO 2023208039 A1 WO2023208039 A1 WO 2023208039A1 CN 2023090842 W CN2023090842 W CN 2023090842W WO 2023208039 A1 WO2023208039 A1 WO 2023208039A1
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WO
WIPO (PCT)
Prior art keywords
ddr
slot
rcd
commands
motherboard
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PCT/CN2023/090842
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English (en)
French (fr)
Inventor
李兆男
安万全
方毅
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华为技术有限公司
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Publication of WO2023208039A1 publication Critical patent/WO2023208039A1/zh

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4265—Bus transfer protocol, e.g. handshake; Synchronisation on a point to point bus
    • G06F13/4273—Bus transfer protocol, e.g. handshake; Synchronisation on a point to point bus using a clocked protocol
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5011—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals
    • G06F9/5016—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals the resource being the memory

Definitions

  • the present application relates to the field of storage technology, and in particular to a motherboard, a memory system and a data transmission method.
  • DDR Double Data Rate synchronous dynamic random-access memory
  • a motherboard that supports DDR5 is called a DDR5 motherboard, and a DDR5 motherboard can only use DDR5 memory.
  • the current DDR5 memory is not stable enough and the cost is high. How to use DDR4 on a DDR5 motherboard to achieve flexibility in memory use is an urgent problem that needs to be solved.
  • Embodiments of the present application provide a motherboard, a memory system, and a data transmission method to achieve flexibility in DDR usage.
  • embodiments of the present application provide a motherboard, which is provided with a double-rate synchronous dynamic random access memory DDR slot, a data buffer DB, a registered clock driver RCD, and a central processing unit CPU slot.
  • the DDR slot The slot is adapted to the first DDR, and the bus protocol between the DDR slot and the CPU slot is a bus protocol adapted to the second DDR; the RCD is used to transfer the second DDR from the CPU side
  • the command is converted into a command to be executed by the first DDR, the DDR slot is connected to the DB and the RCD, and the CPU slot is connected to the DB and the RCD.
  • RCD, DB and DDR are integrated into the memory slot.
  • DB, RCD and the first DDR are decoupled.
  • DB and RCD are set in the motherboard provided by this application.
  • RCD can Convert commands from the second DDR on the CPU side into commands to be executed on the first DDR, thereby enabling the first DDR to be used on the second DDR motherboard. Even if the first DDR is damaged, the effectiveness of DB and RCD will not be affected. , facilitates the replacement of DDR, thereby achieving flexibility in DDR use.
  • the bus protocol between the DDR slot and the CPU slot is a bus protocol adapted to the second DDR
  • the data transmission rate of the lower version DDR data can be increased by using the bus protocol of the higher version DDR.
  • the motherboard provided in this application is a DDR5 motherboard
  • you can DDR4 is applied to DDR5 motherboards, so compared to DDR4 being applied to DDR4 motherboards, DDR4 data can be transmitted using the DDR5 bus protocol, which increases the transmission rate.
  • the RCD includes a command/address CA converter, which is used to input commands from the second DDR on the CPU side and output commands from the first DDR.
  • a command/address CA converter which is used to input commands from the second DDR on the CPU side and output commands from the first DDR.
  • the command of the second DDR from the CPU side can be converted into the command of the first DDR through the CA converter.
  • the command of the first DDR can be adapted to the first DDR. , can be used directly for the first DDR.
  • the RCD further includes a micro control unit MCU, which is configured to input commands from the second DDR on the CPU side and output programmable commands of the first DDR.
  • a micro control unit MCU which is configured to input commands from the second DDR on the CPU side and output programmable commands of the first DDR.
  • the commands of the second DDR can be converted into programmable commands of the first DDR through the MCU.
  • the programmable commands can simplify the operation logic, and the operability of the DDR can be enhanced by programming customized commands.
  • the RCD also includes a multiplexer MUX, a first group of data pins and a second group of data pins are provided on the MUX, and the first group of data pins are used to convert the A DDR command output, the second group of data pins is used to output the programmable command of the first DDR.
  • a multiplexer MUX a multiplexer MUX
  • a first group of data pins and a second group of data pins are provided on the MUX
  • the first group of data pins are used to convert the A DDR command output
  • the second group of data pins is used to output the programmable command of the first DDR.
  • the MUX can be used to choose to output directly converted commands of the first DDR or programmable commands of the first DDR, thereby providing more command options and improving the flexibility of DDR operations.
  • the DB includes a delay adjustment module and a transaction control module;
  • the transaction control module is used to input the command to be executed from the RCD, expand the command to be executed into multiple commands to be executed, and Output delay control information;
  • the delay adjustment module is used to input the delay control information and multi-channel data from the first DDR side, output the multi-channel data after the adjusted delay, and output the adjusted delay of multiple commands to be executed.
  • the DB also includes a read buffer register and a write buffer register
  • the delay adjustment module includes a plurality of first buffer registers and a plurality of second buffer registers; wherein the plurality of first buffer registers and the The reading buffer registers are connected, and any first buffer register is used to input the delay control information, one channel of data in the multi-channel data, and output one channel of data after adjusting the time delay; the plurality of second buffer registers Connected to the write buffer register, any second buffer register is used to input the delay control information, one of the multiple to-be-executed commands, and output one of the to-be-executed commands after adjusting the delay.
  • a first buffer register can be configured for each channel of data
  • a second buffer register can be configured for each channel of command to be executed, so that the delay of any channel of data or any channel of command to be executed can be adjusted through the buffer register, ensuring that any channel of data or any channel of command to be executed can be All the way to normal operation of the command to be executed.
  • the DB also includes a register control word RCW module, which is used to input the command to be executed and output the delay control information.
  • RCW module register control word
  • the delay control information can be obtained by parsing the command to be executed, so that the delay control information can be output efficiently.
  • the motherboard is also configured to shield the DB and the RCD when it is detected that the DDR inserted into the DDR slot is the second DDR; wherein the DDR slot is adapted to the first DDR.
  • DDR is not adapted to the second DDR, the DDR slot is adapted to the first DDR adapter card, and the first DDR adapter card is used to connect the second DDR.
  • the first DDR is DDR4
  • the second DDR is DDR5.
  • inventions of the present application provide a memory system.
  • the memory system includes a DDR and a motherboard.
  • the motherboard is provided with a DDR slot, a DB, an RCD and a CPU slot.
  • the DDR slot is adapted to the first DDR.
  • the bus protocol between the DDR slot and the CPU slot is a bus protocol adapted to the second DDR; the RCD is used to convert commands from the second DDR on the CPU side into the The command to be executed of the first DDR, the DDR is set in the DDR slot, the DDR slot is connected to the DB and the RCD, and the CPU slot is connected to the DB and the RCD.
  • the memory system further includes a first DDR adapter card, the DDR is the second DDR, and the DDR slot is adapted to the first DDR but not to the second DDR, so The DDR slot is adapted to a first DDR adapter card, and the first DDR adapter card is connected to the second DDR.
  • the motherboard is also configured to detect that the DDR inserted into the DDR slot is the DDR. During the second DDR, the DB and the RCD are shielded.
  • the two DDR slots correspond to the two DBs and the two RCDs and are connected respectively
  • the CPU slot corresponds to the DBs and the two RCDs and are connected respectively.
  • inventions of the present application provide a data transmission method, which can be used in the memory system of the second aspect.
  • the memory system includes a first DDR and a motherboard.
  • the motherboard is provided with a DDR slot, a DB , RCD and CPU slot, the DDR slot is adapted to the first DDR, and the bus protocol between the DDR slot and the CPU slot is a bus protocol adapted to the second DDR;
  • the first DDR is arranged in the DDR slot, the DDR slot is connected to the DB and the RCD, the CPU slot is connected to the DB and the RCD, and the method includes: the RCD will come from
  • the commands of the second DDR on the CPU side are converted into commands to be executed by the first DDR; the first DDR executes the commands to be executed.
  • the method further includes: the first DDR outputs data to the DB; and the DB outputs the adjusted time-delayed data.
  • Figure 1 is a schematic architectural diagram of a memory system provided by an embodiment of the present application.
  • Figure 2 is a schematic diagram of the architecture of an RCD in a memory system provided by an embodiment of the present application
  • Figure 3 is a schematic diagram of the architecture of a DB in a memory system provided by an embodiment of the present application.
  • FIG. 4 is a schematic diagram of a data transmission method that can be implemented by a memory system provided by an embodiment of the present application.
  • multiple in the embodiments of this application refers to two or more than two.
  • the term “multiple” in the embodiments of this application can also be understood as “at least two”.
  • At least one can be understood as one or more, for example, one, two or more.
  • including at least one means including one, two or more, and does not limit which ones are included.
  • A, B and C is included, then it may include A, B, C, A and B, A and C, B and C, or A and B and C.
  • “And/or” describes the relationship between related objects, indicating that there can be three relationships.
  • a and/or B can mean: A exists alone, A and B exist simultaneously, and B exists alone.
  • the character "/" unless otherwise specified, generally indicates that the related objects are in an "or” relationship.
  • ordinal numbers such as “first” and “second” mentioned in the embodiments of this application are used to distinguish multiple objects and are not used to limit the order, timing, priority or importance of multiple objects.
  • Embodiments of the present application provide a memory system.
  • the memory system includes a first DDR and a motherboard.
  • the motherboard supports a bus protocol adapted to the second DDR.
  • the system can realize the use of the first DDR with the second DDR.
  • the motherboard is provided with a DDR slot, a data buffer (DB), a register clock driver (RCD) and a central processing unit (CPU) slot.
  • the DDR slot The slot is adapted to the first DDR, the DDR slot can be inserted into the first DDR, the bus protocol between the DDR slot and the CPU slot is a bus protocol adapted to the second DDR, and the RCD is used to The commands from the second DDR on the CPU side are converted into commands to be executed by the first DDR.
  • the DDR slot is connected to the DB and the RCD, and the CPU slot is connected to the DB and the RCD. RCD connection, the CPU slot can plug the CPU.
  • the commands of the second DDR output by the CPU can be transmitted through the bus protocol of the second DDR, converted by RCD into commands to be executed by the first DDR, and output to the first DDR for execution.
  • the first DDR After executing the pending command of the first DDR, data may be returned, and the returned data can be transmitted to the CPU side through the bus protocol of the second DDR.
  • the type of DDR is not limited.
  • the following description takes the first DDR as DDR4 and the second DDR as DDR5 as an example.
  • the memory system includes at least one DDR4 and DDR5 motherboard,
  • the bus protocol between the DDR slot 10 and the CPU slot 30 in the DDR5 motherboard is a bus protocol adapted to DDR5.
  • the DDR4 models in at least one DDR4 can be the same or different, and the number of at least one DDR4 is not limited. For example, it can be 1 DDR4 or 2 DDR4.
  • a DDR5 motherboard is provided with a DDR slot 10.
  • the DDR slot 10 can be a DDR5 dual inline memory module (DIMM) socket.
  • DIMM dual inline memory module
  • the DDR5 motherboard can also be equipped with memory chip 20 and CPU slot 30.
  • Memory chip 20 is equipped with RCD201 and DB202.
  • RCD201 can be used to convert DDR5 commands into DDR4 commands.
  • the number of DDR slots 10 and memory sets 20 can be set to be the same as the number of DDR4.
  • Figure 1 takes 2 DDR slots 10, 2 memory sets 20 and 2 DDR4 as an example.
  • 1 DDR slot 10 corresponds to 1 memory set 20, and also corresponds to 1 DDR4.
  • FIG. 1 is only a possible example. This architecture can flexibly add and delete modules according to specific situations.
  • the memory set 20 may not be provided.
  • one memory set 20 can be connected to the CPU slot 30, or two memory sets 20 can be connected.
  • Each DDR4 of at least one DDR4 corresponds to a DDR slot 10 and a memory set.
  • chip 20, DDR4 is arranged in the DDR slot 10, the DDR slot 10 is connected to the memory set 20, and the memory set 20 is connected to the CPU slot 30.
  • the DDR5 motherboard shown in Figure 1 can also be adapted to the original second DDR (DDR5), and when it is detected that the DDR inserted into the DDR slot 10 is DDR5, RCD201 and DB202 are shielded, and the DDR slot 10 and A first DDR adapter card is adapted, and the first DDR adapter card is used to connect the second DDR.
  • DDR5 original second DDR
  • the number of DDR4 is 2, the number of DDR slots 10 is 2, and the number of memory chips is 2.
  • the 2 DDR4s are respectively installed in the 2 DDR slots 10, and the 2 DDR slots 10 and 2
  • the memory sets 20 correspond to each other and are connected respectively, and the CPU slot 30 is connected to the two memory sets 20 .
  • the type of DDR4 in at least one DDR4 can be different, and the settings of RCD201 corresponding to each DDR4 also need to be adapted to DDR4, the parameters of the dynamic random access memory (DRAM) of RCD201 are those corresponding to DDR4 parameter.
  • the memory system shown in Figure 1 is just a possible example, and this architecture can flexibly set the number of modules according to specific situations.
  • the CPU slot 30 can also be configured to be connected to a memory chip 20. There can be many examples of memory systems, which will not be described again here.
  • the memory chip and DDR are integrated into the DDR slot 10.
  • RCD201 and DB202 are decoupled from DDR4. Even if DDR4 is damaged, it will not affect the effectiveness of RCD201 and DB202, making it easy to replace the DDR. Therefore, the memory chip 20 can transmit data between DDR4 and the CPU, so that DDR4 can be used in DDR5 motherboards, thereby realizing the memory system in Figure 1.
  • the bus protocol between the DDR slot 10 and the CPU slot 30 is a bus protocol adapted to DDR5, DDR4 data can be transmitted using a bus protocol of a higher version of DDR, thereby increasing the data transmission rate.
  • RCD201 includes a command/address (CA) converter 2011, a command recognition module 2012, a microcontroller unit (MCU) 2013, and a multiplexer (multiplexer, MUX) 2014 and phase locked loop (PLL) 2015.
  • CA command/address
  • MCU microcontroller unit
  • MUX multiplexer
  • PLL phase locked loop
  • the CA converter 2011 is connected to the command identification module 2012, MUX2014, and PLL2015, the command identification module 2012 is connected to the MCU2013, MUX2014, and the MCU2013 is connected to the MUX2014.
  • RCD2011 can complete two functions: the first function is to convert the DDR5 commands from the CPU side into DDR4 commands and output the DDR4 commands to DDR4; the second function is to convert the DDR5 commands from the CPU side Convert the command into a programmable command and output the programmable command to DDR4.
  • MCU2013 can switch to implement these two functions.
  • the implementation process of these two functions can be as follows:
  • the implementation process of the first function can be as follows:
  • the command identification module 2012 is connected to the CPU socket 30 , and the CPU socket 30 can input DDR5 commands from the CPU side to the command identification module 2012 .
  • the command recognition module 2012 recognizes the DDR5 command, it can input the DDR5 command to the CA converter 2011.
  • the CA converter 2011 can convert the DDR5 command from the CPU side into a DDR4 command on the DDR4 side.
  • the converted DDR4 command is used for DDR4 recognition and execution.
  • the CA converter 2011 can convert the converted DDR4 command Output to MUX2014, which then outputs the converted DDR4 commands.
  • MUX2014 can transmit the converted DDR4 commands to DB202 through the first set of data pins, and then transmit them to DDR4 from DB202. It can also directly output the converted DDR4 commands to DDR4 through the first set of data pins.
  • DDR4 commands are directly converted by CA converters and can be used directly for DDR4.
  • a first group of data pins and a second group of data pins are provided on the MUX2014 in the RCD201.
  • the first group of data pins and the second group of data pins can both be bidirectional data control pins (bi- directional data strobe, MDQS/MDQ).
  • the first group of data pins is used to output converted DDR4 commands
  • the second group of data pins is used to output converted programmable commands.
  • the implementation process of the second function can be as follows:
  • DDR5 commands from the CPU side may be input to the command identification module 2012 by the CPU socket 30 .
  • the command recognition module 2012 recognizes the DDR5 command, it can input the DDR5 command to the micro control unit MCU2013.
  • MCU2013 obtains the DDR5 command, it can convert the DDR5 command from the CPU side into a programmable command on the DDR4 side.
  • the converted programmable command is used for DDR4 recognition and execution.
  • MCU2013 can output the converted programmable command to MUX2014 , and then output by MUX2014.
  • MUX2014 can transmit the converted programmable commands to DDR4 through the second set of data pins.
  • MUX2014 can choose to output the converted DDR4 commands according to the settings, or it can choose to output the converted programmable commands.
  • MUX2014 outputs programmable commands to simplify the operation logic, and can customize functions through programming to enhance DDR operability.
  • the architecture shown in Figure 2 is only an example of RCD201. This architecture can flexibly add and delete components according to specific situations, and set the connection relationships between components.
  • the CA converter 2011 can also be connected to the MCU 2013, and the MUX 2014 does not need to be set, and the MCU 2013 outputs DDR4 commands or programmable commands.
  • the architecture shown in Figure 2 can provide more command options and improve the flexibility of DDR operations.
  • DB202 includes a delay adjustment module 2021, a read buffer register (read buffer, RB) 2022, a write buffer register (writer buffer, WB) 2023, and a command decoder (command decoder). , CD) 2024, register control word (RCW) module 2025 and transaction control (transaction control, TC) module 2026. Still taking the first DDR as DDR4 and the second DDR as DDR5 as an example, the specific structure and function of DB202 will be described in detail.
  • the delay adjustment module 2021 is connected to the read buffer register 2022, the write buffer register 2023 and the transaction control module 2026, the command decoder 2024 is connected to the register control word module 2025 and the transaction control module 2026, and the register control word module 2025 is connected to the transaction control module 2026 connection, the above connection relationship can be shown in Figure 3.
  • the delay adjustment module 2021 is provided with a third group of data pins and a fourth group of data pins.
  • the third group of data pins and the fourth group of data pins can both be bidirectional data control pins, and the third group of data can be recorded
  • the pin is MDQS
  • the fourth group of data pins is MDQ.
  • the third group of MDQS is used to transmit multiple input data of the read buffer register 2022, In the example shown in Figure 3, the third group of data pins is divided into two parts: MDQS_A and MDQS_B. Each part of MDQS_A and MDQS_B is divided into two channels.
  • the fourth group of data pins is divided into MDQ_A and MDQ_B.
  • the third group of data pins is used to input multiple channels of first chip select information from the DDR4 side (a total of 4 channels in Figure 3), and the fourth group of data pins is used to input multiple channels of first chip select information from the DDR4 side.
  • the transaction control module 2026 is used to input the command to be executed from the RCD 201, and to output the delay control information, the command to be executed and the second chip select information, so The command to be executed is a DDR4 command or a programmable command.
  • the transaction control module 2026 inputs the command to be executed from the RCD 201 specifically as follows: the command decoder 2024 is connected to the MCU 2013, the MCU 2013 outputs the command identification information, and the command decoder 2024 identifies the command. The information is parsed to obtain the command to be executed, and the command decoder 2024 outputs the command to be executed to the transaction control module 2026.
  • the specific way in which the transaction control module 2026 outputs the delay control information is that the RCW module 2025 is connected to the command decoder 2024, the command decoder 2024 sends the command to be executed to the RCW module 2025, and the RCW module 2025 generates the delay control information according to the command to be executed.
  • the RCW module 2025 can pre-set the delay parameters of the corresponding commands according to different command types. When the RCW module 2025 obtains the specific command to be executed, it can generate specific delay control information according to the delay parameters of the corresponding commands. .
  • the delay adjustment module 2021 is used to input the delay control information and adjust the delay of the multiple channels of first chip select information (a total of 4 channels in Figure 3) to be consistent. , and adjust the delay of the multiple channels of data (total 4 channels in Figure 3) to be consistent, and also used to input the command to be executed and expand it into multiple channels to be executed (2 channels in total in Figure 3), and all The delays of the multiple channels of commands to be executed are adjusted to be consistent, and the second chip select information is input and expanded into multiple channels of second chip select information (2 channels in total in Figure 3), and the multiple channels of second chip select are The information delay is adjusted to be consistent. Based on the delay adjustment module 2021, the delay of DDR4 can be adapted to the DDR5 motherboard, ensuring that DDR4 is used for the operation of DDR5 motherboards.
  • the delay adjustment module 2021 includes a plurality of first buffer registers 20211 and a plurality of second buffer registers 20212;
  • the plurality of first buffer registers 20211 are connected to the read buffer register 2022, and any first buffer register 20211 is used to input the delay control information from the transaction control module 2026, the delay control information from the DDR4 side
  • the delay of any channel of data can be adjusted to ensure the normal operation of any channel of data.
  • the plurality of second buffer registers 20212 are connected to the write buffer register 2023. Any second buffer register 20212 is used to input the delay control information from the transaction control module 2026, a second chip select information and All the commands to be executed, and the commands to be executed after the output adjustment time delay. By configuring a second buffer register for each command to be executed, the delay of any command to be executed is adjusted to ensure the normal operation of any command to be executed.
  • the architecture shown in Figure 3 is only an example of DB202.
  • This architecture can flexibly add and delete components according to specific situations, and set the connection relationships between components.
  • the command decoder 2024 may not be connected to the RCW module 2025, and the RCW module 2025 may be directly connected to the MUX2013, with the MUX2013 outputting DDR4 commands or programmable commands to the RCW module 2025; the command decoder 2024 may not be provided, and the command decoder 2024 may be configured by MUX2013 outputs DDR4 commands or programmable commands to the transaction control module 2026.
  • Step 401 RCD201 obtains the second DDR (DDR5) command from the CPU side.
  • Step 402 RCD201 converts the DDR5 command from the CPU side into a DDR4 command to be executed.
  • the command to be executed can be a DDR4 command and a programmable command.
  • Step 403 RCD201 outputs the command to be executed to DDR4 or DB202.
  • Step 404 DDR4 executes the command to be executed.
  • DDR4 may return corresponding data after executing the pending command, such as after executing the read command.
  • Step 405 DDR4 returns the multi-channel first chip select information and multi-channel data to DB202.
  • Step 406 DB202 adjusts the delays of multiple channels of first chip select information to be consistent, and adjusts the delays of multiple channels of data to be consistent.
  • Step 407 DB202 outputs the multi-channel first chip select information after adjusting the time delay and the multi-channel data after adjusting the time delay to the CPU slot 30.
  • step 404 The process can be ended after execution.

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Abstract

本发明公开了一种主板、内存系统以及数据传输方法，其中主板上设置有DDR插槽、DB、RCD和CPU插槽，DDR插槽与第一DDR适配，DDR插槽与CPU插槽之间的总线协议为适配于第二DDR的总线协议；RCD用于将来自CPU侧的第二DDR的命令转换为第一DDR的待执行命令，第一DDR设置于DDR插槽中，DDR插槽与DB、RCD连接，CPU插槽与DB、RCD连接，由于DB、RCD和第一DDR解耦，即便第一DDR损坏，也不会影响DB、RCD的有效性，便于DDR的更换，从而实现将第一DDR用于第二DDR的主板，提升DDR使用的灵活性。

Description

一种主板、内存系统及数据传输方法
相关申请的交叉引用
本申请要求于2022年4月26日提交中国专利局、申请号为202210446583.5、发明名称为“一种主板、内存系统及数据传输方法”的中国专利申请的优先权，所述专利申请的全部内容通过引用结合在本申请中。
技术领域
本申请涉及存储技术领域，尤其涉及一种主板、内存系统及数据传输方法。
背景技术
随着内存技术的发展，内存速率越来越高。目前业界已推出双倍率同步动态随机存储器(Double Data Ratesynchronous dynamic random-access memory，DDR)DDR5，DDR5的速率已提升至4800Mbps。通常电子设备(如服务器)内存的数据传输速率要求都会跟随当前最高工艺。
目前业界主板和DDR的类型是绑定的。举例来说，支持DDR5的主板称为DDR5主板，DDR5主板只能使用DDR5内存。然而目前DDR5内存还不够稳定并且成本较高，如何实现将DDR4用于一个DDR5主板，实现内存使用的灵活性，是一个亟待解决的问题。
发明内容
本申请实施例提供一种主板、内存系统以及数据传输方法，用于实现DDR使用的灵活性。
第一方面，本申请实施例提供一种主板，所述主板上设置有双倍率同步动态随机存储器DDR插槽、数据缓冲器DB、寄存时钟驱动器RCD和中央处理器CPU插槽，所述DDR插槽与第一DDR适配，所述DDR插槽与所述CPU插槽之间的总线协议为适配于第二DDR的总线协议；所述RCD用于将来自CPU侧的所述第二DDR的命令转换为所述第一DDR的待执行命令，所述DDR插槽与所述DB、所述RCD连接，所述CPU插槽与所述DB、所述RCD连接。
传统内存系统中，RCD、DB和DDR一体插在内存插槽中，而通过本申请提供的主板，DB、RCD和第一DDR解耦，DB、RCD设置于本申请提供的主板中，RCD可以将来自CPU侧的第二DDR的命令转换为第一DDR的待执行命令，从而实现将第一DDR用于第二DDR的主板，即便第一DDR损坏，也不会影响DB、RCD的有效性，便于DDR的更换，从而实现了DDR使用的灵活性。并且由于所述DDR插槽与所述CPU插槽之间的总线协议为适配于第二DDR的总线协议，可以使得低版本DDR的数据通过使用高版本DDR的总线协议提升数据传输速率。举例来说，当本申请提供的主板为DDR5主板时，可以将 DDR4应用于DDR5主板，那么相对于DDR4应用于DDR4主板，DDR4的数据可以采用DDR5的总线协议传输，提升了传输速率。
可选的，所述RCD包括命令/地址CA转换器，所述CA转换器用于输入来自CPU侧的所述第二DDR的命令，且输出所述第一DDR的命令。
采用上述方式，通过CA转换器可以将来自CPU侧的所述第二DDR的命令转换为第一DDR的命令，通过命令地址间的转换，可以使得第一DDR的命令能够适配于第一DDR，可以直接用于第一DDR。
可选的，所述RCD还包括微控制单元MCU，所述MCU用于输入来自所述CPU侧的所述第二DDR的命令，且输出所述第一DDR的可编程命令。
上述方式下，通过MCU可以将第二DDR的命令转化为第一DDR的可编程命令，可编程命令可以简化操作逻辑，且可以通过编程自定义命令，增强DDR的可操作性。
可选的，所述RCD还包括多路复用器MUX，所述MUX上设置了第一组数据引脚和第二组数据引脚，所述第一组数据引脚用于将所述第一DDR的命令输出，所述第二组数据引脚用于将所述第一DDR的可编程命令输出。
上述方式下，可以通过MUX选择输出直接转换的第一DDR的命令或者是第一DDR的可编程命令，从而能够提供更多的命令选择，提升了对DDR操作的灵活性。
可选的，所述DB包括时延调整模块和事务控制模块；所述事务控制模块用于输入来自所述RCD的所述待执行命令，将所述待执行命令扩展为多路待执行命令以及输出时延控制信息；所述时延调整模块用于输入所述时延控制信息和来自所述第一DDR侧的多路数据，输出调整时延后的多路数据，以及输出调整时延后的多路待执行命令。
上述方式下，通过输出时延控制信息，可以输出调整时延后的多路待执行命令、调整时延后的多路数据，从而即便第一DDR与第二DDR的时延不同，也可以进行调整，从而保证了第一DDR用于第二DDR的正常运行。
可选的，所述DB还包括读缓冲寄存器和写缓冲寄存器，所述时延调整模块包括多个第一缓冲寄存器和多个第二缓冲寄存器；其中，所述多个第一缓冲寄存器与所述读缓冲寄存器连接，任一第一缓冲寄存器用于输入所述时延控制信息、所述多路数据中的一路数据，以及输出调整时延后的一路数据；所述多个第二缓冲寄存器与所述写缓冲寄存器连接，任一第二缓冲寄存器用于输入所述时延控制信息、所述多路待执行命令中的一路待执行命令，以及输出调整时延后的一路待执行命令。
上述方式下，可以给每一路数据配置第一缓冲寄存器，每一路待执行命令配置第二缓冲寄存器，从而通过缓冲寄存器调整任一路数据或者任一路待执行命令的时延，保障任一路数据或者任一路待执行命令的正常运行。
可选的，所述DB还包括寄存控制字RCW模块，所述RCW模块用于输入所述待执行命令，以及输出所述时延控制信息。
上述方式下，通过寄存控制字RCW模块，可以通过对待执行命令进行解析，得到时延控制信息，从而可以高效地输出时延控制信息。
可选的，所述主板还用于在检测到插入所述DDR插槽的DDR为所述第二DDR时，屏蔽所述DB和所述RCD；其中，所述DDR插槽适配于第一DDR，不适配于所述第二DDR，所述DDR插槽与第一DDR转接卡适配，所述第一DDR转接卡用于连接所述第二DDR。
可选的，所述第一DDR为DDR4，所述第二DDR为DDR5。
第二方面，本申请实施例提供一种内存系统，该内存系统包括DDR和主板，所述主板上设置有DDR插槽、DB、RCD和CPU插槽，所述DDR插槽与第一DDR适配，所述DDR插槽与所述CPU插槽之间的总线协议为适配于第二DDR的总线协议；所述RCD用于将来自CPU侧的所述第二DDR的命令转换为所述第一DDR的待执行命令，所述DDR设置于所述DDR插槽中，所述DDR插槽与所述DB、所述RCD连接，所述CPU插槽与所述DB、所述RCD连接。
可选的，所述内存系统还包括第一DDR转接卡，所述DDR为所述第二DDR，所述DDR插槽适配于第一DDR，不适配于所述第二DDR，所述DDR插槽与第一DDR转接卡适配，所述第一DDR转接卡与所述第二DDR连接，所述主板还用于在检测到插入所述DDR插槽的DDR为所述第二DDR时，屏蔽所述DB和所述RCD。
可选的，所述第一DDR为2个，所述DDR插槽为2个，所述DB为2个，所述RCD为2个，2个第一DDR分别设置于2个DDR插槽内，所述2个DDR插槽与2个DB、2个RCD均一一对应并分别连接，所述CPU插槽与所述DB、2个RCD均一一对应并分别连接。
上述方式中，通过在内存系统中实现两个第一DDR，可以同时实现CPU与两个DDR的数据传输，从而实现内存的性能翻倍。
第三方面，本申请实施例提供一种数据传输方法，该数据传输方法可用于第二方面的内存系统，所述内存系统包括第一DDR和主板，所述主板上设置有DDR插槽、DB、RCD和CPU插槽，所述DDR插槽与第一DDR适配，所述DDR插槽与所述CPU插槽之间的总线协议为适配于第二DDR的总线协议；所述第一DDR设置于所述DDR插槽中，所述DDR插槽与所述DB、所述RCD连接，所述CPU插槽与所述DB、所述RCD连接，所述方法包括：所述RCD将来自CPU侧的第二DDR的命令转换为所述第一DDR的待执行命令；所述第一DDR执行所述待执行命令。
可选的，所述方法还包括：所述第一DDR输出数据至所述DB；所述DB输出调整时延后的数据。
以上第二方面到第三方面的有益效果，请参见第一方面的有益效果，不重复赘述。
附图说明
图1为本申请实施例提供的一种内存系统的架构示意图；
图2为本申请实施例提供的一种内存系统中RCD的架构示意图；
图3为本申请实施例提供的一种内存系统中DB的架构示意图；
图4为本申请实施例提供的一种内存系统可实现的一种数据传输方法示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。
以下实施例中所使用的术语只是为了描述特定实施例的目的，而并非旨在作为对本申请的限制。如在本申请的说明书和所附权利要求书中所使用的那样，单数表达形式“一个”、“一种”、“所述”、“上述”、“该”和“这一”旨在也包括例如“一个或多个”这种表达形式，除非其上下文中明确地有相反指示。还应当理解，在本申请实施例中，“一个或多个”是指一个或两个以上(包含两个)；“和/或”，描述关联对象的关联关系，表示可以存在三种关系；例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B的情况，其中A、B可以是单数或者复数。字符“/”一般表示前后关联对象是一种“或”的关系。
在本说明书中描述的参考“一个实施例”或“一些实施例”等意味着在本申请的一个或多个实施例中包括结合该实施例描述的特定特征、结构或特点。由此，在本说明书中的不同之处出现的语句“在一个实施例中”、“在一些实施例中”、“在其他一些实施例中”、“在另外一些实施例中”等不是必然都参考相同的实施例，而是意味着“一个或多个但不是所有的实施例”，除非是以其他方式另外特别强调。术语“包括”、“包含”、“具有”及它们的变形都意味着“包括但不限于”，除非是以其他方式另外特别强调。
本申请实施例中的术语“多个”是指两个或两个以上，鉴于此，本申请实施例中也可以将“多个”理解为“至少两个”。“至少一个”，可理解为一个或多个，例如理解为一个、两个或更多个。例如，包括至少一个，是指包括一个、两个或更多个，而且不限制包括的是哪几个。例如，包括A、B和C中的至少一个，那么包括的可以是A、B、C，A和B，A和C，B和C，或A和B和C。同理，对于“至少一种”等描述的理解，也是类似的。“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。另外，字符“/”，如无特殊说明，一般表示前后关联对象是一种“或”的关系。
除非有相反的说明，本申请实施例提及“第一”、“第二”等序数词用于对多个对象进行区分，不用于限定多个对象的顺序、时序、优先级或者重要程度。
为了便于理解，对本申请实施例涉及的术语进行解释说明，该术语的解释说明也作为对本申请实施例发明内容的一部分。
本申请实施例提供一种内存系统，该内存系统包括第一DDR和主板，该主板支持总线协议为适配于第二DDR的总线协议，该系统可以实现将第一DDR用于与第二DDR适配的主板。其中，所述主板上设置有DDR插槽、数据缓冲器(data buffer，DB)、寄存时钟驱动器(register clock driver，RCD)和中央处理器(central processing unit，CPU)插槽，所述DDR插槽与第一DDR适配，DDR插槽可以插入第一DDR，所述DDR插槽与所述CPU插槽之间的总线协议为适配于第二DDR的总线协议，所述RCD用于将来自CPU侧的所述第二DDR的命令转换为所述第一DDR的待执行命令，所述DDR插槽与所述DB、所述RCD连接，所述CPU插槽与所述DB、所述RCD连接，所述CPU插槽可以插入CPU。显然，该内存系统中，CPU输出的第二DDR的命令可以通过第二DDR的总线协议传输，并由RCD转换为第一DDR的待执行命令，并输出至第一DDR中执行，第一DDR执行了第一DDR的待执行命令后，可能会返回数据，返回的数据可以通过第二DDR的总线协议传输至CPU侧。
本申请实施例中，并不限定DDR的类型，下面以第一DDR为DDR4且第二DDR为DDR5为例说明。如图1所示，举例来说，该内存系统包括至少一个DDR4和DDR5主板， DDR5主板中DDR插槽10与所述CPU插槽30之间的总线协议为适配于DDR5的总线协议。其中，至少一个DDR4中DDR4的型号可以相同也可以不同，至少一个DDR4的数量也不做限定，举例来说，可以为1个DDR4，也可以为2个DDR4。DDR5主板上设置了DDR插槽10，举例来说，DDR插槽10可以为DDR5双列直插内存模块(dual inline memory modules，DIMM)插座。DDR5主板上还可以设置内存套片20和CPU插槽30，内存套片20上设置了RCD201和DB202，RCD201可以用于将DDR5命令转换为DDR4命令。DDR插槽10和内存套片20的数量可以设置与DDR4的数量相同。图1中以2个DDR插槽10、2个内存套片20和2个DDR4为例，如1个DDR插槽10对应1个内存套片20，还对应1个DDR4。需要说明的是，图1示出的内存系统只是一种可能的示例，该架构可以根据具体情形灵活增删模块，如也可以不设置内存套片20。
图1示出的内存系统中，CPU插槽30上可以连接一个内存套片20，也可以连接两个内存套片20，至少一个DDR4中每个DDR4对应于一个DDR插槽10和一个内存套片20，DDR4设置于DDR插槽10内，DDR插槽10与内存套片20连接，内存套片20与CPU插槽30连接。
需要说明的是，图1示出的DDR5主板也可以适配原版的第二DDR(DDR5)，且在检测到插入DDR插槽10的DDR为DDR5时，屏蔽RCD201和DB202，DDR插槽10与第一DDR转接卡适配，所述第一DDR转接卡用于连接所述第二DDR。
举例来说，DDR4为2个时，DDR插槽10为2个，内存套片20也为2个，2个DDR4分别设置于2个DDR插槽10内，2个DDR插槽10与2个内存套片20一一对应并分别连接，CPU插槽30与2个内存套片20连接。需要说明的是，由于至少一个DDR4中DDR4的类型可以不同，而每个DDR4对应RCD201的设置也需要与DDR4适配，RCD201的动态随机存储器(dynamic random access memory，DRAM)的参数为对应DDR4的参数。需要说明的是，图1示出的内存系统只是一种可能的示例，该架构可以根据具体情形灵活设置各模块的数量。举例来说，CPU插槽30也可以设置连接一个内存套片20，内存系统还可以有多种例子，在此不再赘述。
传统内存系统中，内存套片和DDR一体插在DDR插槽10中。而由图1可知，RCD201和DB202和DDR4是解耦的，即便DDR4损坏，也不会影响RCD201和DB202的有效性，便于DDR的更换。从而内存套片20可以传输DDR4与CPU之间的数据，使得DDR4可以用于DDR5主板，实现了图1中的内存系统。并且由于所述DDR插槽10与所述CPU插槽30之间的总线协议为适配于DDR5的总线协议，可以使得DDR4的数据通过使用高版本DDR的总线协议传输，提升数据传输速率。
如图2所示，RCD201一种可能的架构中，RCD201包括命令/地址(command/address，CA)转换器2011、命令识别模块2012、微控制单元(microcontrollerunit，MCU)2013、多路复用器(multiplexer，MUX)2014和锁相环(phase locked loop，PLL)2015。仍然以第一DDR为DDR4，且第二DDR为DDR5为例，详细说明RCD201的具体结构和功能。
其中，CA转换器2011与命令识别模块2012、MUX2014、PLL2015连接，命令识别模块2012与MCU2013、MUX2014连接，MCU2013与MUX2014连接，上述连接关系可以如图2所示。RCD2011可以完成两个功能：第一个功能，将来自CPU侧的DDR5命令转换为DDR4命令，输出DDR4命令至DDR4；第二个功能，将来自CPU侧的DDR5命 令转换为可编程命令，输出可编程命令至DDR4。并且，MCU2013可以切换实现这两个功能。这两个功能的实现过程可以如下：
第一个功能的实现过程可以如下：
命令识别模块2012与CPU插槽30连接，可以由CPU插槽30将来自CPU侧的DDR5命令输入至命令识别模块2012。命令识别模块2012识别到DDR5命令后，可以将DDR5命令输入至CA转换器2011。CA转换器2011在获取到DDR5命令后，可以将来自CPU侧的DDR5命令转换为DDR4侧的DDR4命令，转换后的DDR4命令用于DDR4识别并执行，CA转换器2011可以将转换后的DDR4命令输出至MUX2014，再由MUX2014将转换后的DDR4命令输出。MUX2014具体可以通过第一组数据引脚将转换后的DDR4命令传输至DB202，再由DB202传输至DDR4，也可以直接通过第一组数据引脚将转换后的DDR4命令输出至DDR4。DDR4命令是由CA转换器直接转换得到的，可以直接用于DDR4。
本申请实施例中，RCD201中的MUX2014上设置第一组数据引脚和第二组数据引脚，第一组数据引脚和第二组数据引脚可以均为双向数据控制引脚(bi-directional data strobe，MDQS/MDQ)。其中，第一组数据引脚用于输出转换后的DDR4命令，第二组数据引脚用于输出转换后的可编程命令。
第二个功能的实现过程可以如下：
可以由CPU插槽30将来自CPU侧的DDR5命令输入至命令识别模块2012。命令识别模块2012识别到DDR5命令后，可以将DDR5命令输入至微控制单元MCU2013。MCU2013在获取到DDR5命令后，可以将来自CPU侧的DDR5命令转换为DDR4侧的可编程命令，转换后的可编程命令用于DDR4识别并执行，MCU2013可以将转换后的可编程命令输出至MUX2014，再由MUX2014输出。MUX2014具体可以将转换后的可编程命令通过第二组数据引脚传输至DDR4。需要说明的是，MUX2014可以根据设置选取将转换后的DDR4命令输出，也可以选择将转换后的可编程命令输出，MUX2014输出可编程命令可以简化操作逻辑，且可以通过编程自定义功能，增强DDR的可操作性。
需要说明的是，图2示出的架构仅为RCD201一种示例，该架构可以根据具体情形灵活增删各部件，以及设置各部件之间的连接关系。举例来说，CA转换器2011也可以与MCU2013连接，可以不设置MUX2014，由MCU2013输出为DDR4命令或可编程命令。图2示出的架构能够提供更多的命令选择，提升了对DDR操作的灵活性。
如图3所示，DB202一种可能的架构中，DB202包括时延调整模块2021、读缓冲寄存器(read buffer，RB)2022、写缓冲寄存器(writer buffer，WB)2023、命令解码器(command decoder，CD)2024、寄存器控制字(register control word，RCW)模块2025和事务控制(transaction control，TC)模块2026。仍然以第一DDR为DDR4，且第二DDR为DDR5为例，详细说明DB202的具体结构和功能。
其中，时延调整模块2021与读缓冲寄存器2022、写缓冲寄存器2023以及事务控制模块2026连接，命令解码器2024与寄存器控制字模块2025以及事务控制模块2026连接，寄存器控制字模块2025与事务控制模块2026连接，上述连接关系具体可以如图3所示。
时延调整模块2021上设置了第三组数据引脚和第四组数据引脚，第三组数据引脚和第四组数据引脚可以均为双向数据控制引脚，可以记第三组数据引脚为MDQS，记第四组数据引脚为MDQ。其中，第三组MDQS用于传输所述读缓冲寄存器2022的多路输入数据， 图3示出的例子中，第三组数据引脚分为MDQS_A和MDQS_B两部分，MDQS_A和MDQS_B每部分均分为两路，第四组数据引脚分为MDQ_A和MDQ_B。
其中，所述第三组数据引脚用于输入来自所述DDR4侧的多路第一片选信息(图3中共4路)，所述第四组数据引脚用于输入来自所述DDR4侧的多路数据(图3中共4路)，所述事务控制模块2026用于输入来自所述RCD201的待执行命令，以及输出时延控制信息和所述待执行命令和第二片选信息，所述待执行命令为DDR4命令或可编程命令。
一种可能的实现方式中，事务控制模块2026输入来自所述RCD201的待执行命令的方式具体可以为，命令解码器2024与MCU2013连接，由MCU2013输出命令标识信息，由命令解码器2024对命令标识信息解析，获得待执行命令，并由命令解码器2024输出待执行命令至事务控制模块2026。事务控制模块2026输出时延控制信息的方式具体可以为，RCW模块2025与命令解码器2024连接，命令解码器2024将待执行命令至RCW模块2025，RCW模块2025根据待执行命令生成时延控制信息，并将时延控制信息输出至事务控制模块2026，再由事务控制模块2026输出时延控制信息。其中，RCW模块2025可以根据不同的命令类型，预先设置相应命令的时延参数，当RCW模块2025获得具体的待执行命令后，便可以根据相应命令的时延参数，生成具体的时延控制信息。
在所述时延调整模块2021中，所述时延调整模块2021用于输入所述时延控制信息，将所述多路第一片选信息(图3中共4路)的时延调整为一致，且将所述多路数据的时延(图3中共4路)调整为一致，还用于输入所述待执行命令并扩展为多路待执行命令(图3中共2路)，并将所述多路待执行命令的时延调整为一致，以及输入所述第二片选信息并扩展为多路第二片选信息(图3中共2路)，并将所述多路第二片选信息的时延调整为一致。基于时延调整模块2021，可以使得DDR4的时延能够适应DDR5主板，保证了DDR4用于DDR5主板的运行。
图3示出的例子中，所述时延调整模块2021包括多个第一缓冲寄存器20211和多个第二缓冲寄存器20212；
其中，所述多个第一缓冲寄存器20211与所述读缓冲寄存器2022连接，任一第一缓冲寄存器20211用于输入来自所述事务控制模块2026的所述时延控制信息、来自所述DDR4侧的一路第一片选信息及一路数据，以及输出调整时延后的一路数据，通过给每一路数据配置第一缓冲寄存器，调整任一路数据的时延，保障任一路数据的正常运行。
所述多个第二缓冲寄存器20212与所述写缓冲寄存器2023连接，任一第二缓冲寄存器20212用于输入来自所述事务控制模块2026的所述时延控制信息、一路第二片选信息及一路待执行命令，以及输出调整时延后的待执行命令。通过给每一路待执行命令配置第二缓冲寄存器，调整任一路待执行命令的时延，保障任一路待执行命令的正常运行。
需要说明的是，图3示出的架构仅为DB202的一种示例，该架构可以根据具体情形灵活增删各部件，以及设置各部件之间的连接关系。举例来说，命令解码器2024也可以不与RCW模块2025连接，RCW模块2025可以直接与MUX2013连接，由MUX2013输出DDR4命令或可编程命令至RCW模块2025；也可以不设置命令解码器2024，由MUX2013输出DDR4命令或可编程命令至事务控制模块2026，这些例子都可以根据实际需要设置，在此不再赘述。
基于图1～图3内存系统的描述，如图4所示，为本申请实施例提供的一种内存系统可实现的一种数据传输方法，图4示出的方法可以用于图1～图3所描述的内存系统。仍然以 第一DDR为DDR4，且第二DDR为DDR5为例，详细说明图4示出的数据传输方法。
步骤401：RCD201获取来自CPU侧的第二DDR(DDR5)命令。
步骤402：RCD201将来自CPU侧的DDR5命令转换为DDR4的待执行命令。
其中，待执行命令可以为DDR4命令和可编程命令。
步骤403：RCD201将待执行命令输出至DDR4或者DB202。
步骤404：DDR4执行待执行命令。
DDR4执行待执行命令后会可能会返回相应的数据，如执行读取命令之后。
步骤405：DDR4返回多路第一片选信息和多路数据至DB202。
步骤406：DB202将多路第一片选信息的时延调整一致，且将多路数据的时延调整一致。
步骤407：DB202将调整时延后的多路第一片选信息以及调整时延后的多路数据输出至CPU插槽30。
显然，图4示出的流程也仅是一种可能的流程，一些步骤可以为可选的步骤，如步骤405～步骤407为可选的步骤，当待执行命令为写入命令时，步骤404执行后可以结束流程。

Claims (14)

  1. 一种主板，其特征在于，所述主板上设置有双倍率同步动态随机存储器DDR插槽、数据缓冲器DB、寄存时钟驱动器RCD和中央处理器CPU插槽，所述DDR插槽与第一DDR适配，所述DDR插槽与所述CPU插槽之间的总线协议为适配于第二DDR的总线协议；
    所述RCD用于将来自CPU侧的所述第二DDR的命令转换为所述第一DDR的待执行命令，所述DDR插槽与所述DB、所述RCD连接，所述CPU插槽与所述DB、所述RCD连接。
  2. 如权利要求1所述的主板，其特征在于，所述RCD包括命令/地址CA转换器，所述CA转换器用于输入来自CPU侧的所述第二DDR的命令，且输出所述第一DDR的命令。
  3. 如权利要求2所述的主板，其特征在于，所述RCD还包括微控制单元MCU，所述MCU用于输入来自所述CPU侧的所述第二DDR的命令，且输出所述第一DDR的可编程命令。
  4. 如权利要求3所述的主板，其特征在于，所述RCD还包括多路复用器MUX，所述MUX上设置了第一组数据引脚和第二组数据引脚，所述第一组数据引脚用于将所述第一DDR的命令输出，所述第二组数据引脚用于将所述第一DDR的可编程命令输出。
  5. 如权利要求1至4任一所述的主板，其特征在于，所述DB包括时延调整模块和事务控制模块；
    所述事务控制模块用于输入来自所述RCD的所述待执行命令，将所述待执行命令扩展为多路待执行命令以及输出时延控制信息；
    所述时延调整模块用于输入所述时延控制信息和来自所述第一DDR侧的多路数据，输出调整时延后的多路数据，以及输出调整时延后的多路待执行命令。
  6. 如权利要求5所述的主板，其特征在于，所述DB还包括读缓冲寄存器和写缓冲寄存器，所述时延调整模块包括多个第一缓冲寄存器和多个第二缓冲寄存器；
    其中，所述多个第一缓冲寄存器与所述读缓冲寄存器连接，任一第一缓冲寄存器用于输入所述时延控制信息、所述多路数据中的一路数据，以及输出调整时延后的一路数据；
    所述多个第二缓冲寄存器与所述写缓冲寄存器连接，任一第二缓冲寄存器用于输入所述时延控制信息、所述多路待执行命令中的一路待执行命令，以及输出调整时延后的一路待执行命令。
  7. 如权利要求5或6所述的主板，其特征在于，所述DB还包括寄存控制字RCW模块，所述RCW模块用于输入所述待执行命令，以及输出所述时延控制信息。
  8. 如权利要求1至7任一项所述的主板，其特征在于，
    所述主板还用于在检测到插入所述DDR插槽的DDR为所述第二DDR时，屏蔽所述DB和所述RCD；
    其中，所述DDR插槽适配于第一DDR，不适配于所述第二DDR，所述DDR插槽与第一DDR转接卡适配，所述第一DDR转接卡用于连接所述第二DDR。
  9. 如权利要求1至8任一项所述的主板，其特征在于，所述第一DDR为DDR4，所述第二DDR为DDR5。
  10. 一种内存系统，其特征在于，所述内存系统包括DDR和主板，所述主板上设置有DDR插槽、DB、RCD和CPU插槽，所述DDR插槽与第一DDR适配，所述DDR插槽与 所述CPU插槽之间的总线协议为适配于第二DDR的总线协议；
    所述RCD用于将来自CPU侧的所述第二DDR的命令转换为所述第一DDR的待执行命令，所述DDR设置于所述DDR插槽中，所述DDR插槽与所述DB、所述RCD连接，所述CPU插槽与所述DB、所述RCD连接。
  11. 如权利要求10所述的系统，其特征在于，所述内存系统还包括第一DDR转接卡，所述DDR为所述第二DDR，所述DDR插槽适配于第一DDR，不适配于所述第二DDR，所述DDR插槽与第一DDR转接卡适配，所述第一DDR转接卡与所述第二DDR连接，所述主板还用于在检测到插入所述DDR插槽的DDR为所述第二DDR时，屏蔽所述DB和所述RCD。
  12. 如权利要求10或11所述的系统，其特征在于，所述第一DDR为2个，所述DDR插槽为2个，所述DB为2个，所述RCD为2个，2个第一DDR分别设置于2个DDR插槽内，所述2个DDR插槽与2个DB、2个RCD均一一对应并分别连接，所述CPU插槽与所述DB、2个RCD均一一对应并分别连接。
  13. 一种数据传输方法，其特征在于，所述方法用于一种内存系统，所述内存系统包括第一DDR和主板，所述主板上设置有DDR插槽、DB、RCD和CPU插槽，所述DDR插槽与第一DDR适配，所述DDR插槽与所述CPU插槽之间的总线协议为适配于第二DDR的总线协议；所述第一DDR设置于所述DDR插槽中，所述DDR插槽与所述DB、所述RCD连接，所述CPU插槽与所述DB、所述RCD连接，所述方法包括：
    所述RCD将来自CPU侧的第二DDR的命令转换为所述第一DDR的待执行命令；
    所述第一DDR执行所述待执行命令。
  14. 如权利要求13所述的方法，其特征在于，还包括：
    所述第一DDR输出数据至所述DB；
    所述DB输出调整时延后的数据。
PCT/CN2023/090842 2022-04-26 2023-04-26 一种主板、内存系统及数据传输方法 WO2023208039A1 (zh)

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CN108604456A (zh) * 2016-02-26 2018-09-28 英特尔公司 在存储器插槽中支持多个存储器类型
CN113971143A (zh) * 2021-10-22 2022-01-25 展讯半导体(成都)有限公司 一种内存控制器、物联网芯片及电子设备

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CN105335326A (zh) * 2015-10-10 2016-02-17 广州慧睿思通信息科技有限公司 一种基于fpga的pcie转sata接口阵列的装置
CN108604456A (zh) * 2016-02-26 2018-09-28 英特尔公司 在存储器插槽中支持多个存储器类型
CN113971143A (zh) * 2021-10-22 2022-01-25 展讯半导体(成都)有限公司 一种内存控制器、物联网芯片及电子设备

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