WO2023207806A1 - 移位寄存器、栅极驱动电路及显示装置 - Google Patents

移位寄存器、栅极驱动电路及显示装置 Download PDF

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Publication number
WO2023207806A1
WO2023207806A1 PCT/CN2023/089904 CN2023089904W WO2023207806A1 WO 2023207806 A1 WO2023207806 A1 WO 2023207806A1 CN 2023089904 W CN2023089904 W CN 2023089904W WO 2023207806 A1 WO2023207806 A1 WO 2023207806A1
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Prior art keywords
node
transistor
signal terminal
electrode
power signal
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PCT/CN2023/089904
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English (en)
French (fr)
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WO2023207806A9 (zh
Inventor
黄耀
胡明
董向丹
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京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Publication of WO2023207806A1 publication Critical patent/WO2023207806A1/zh
Publication of WO2023207806A9 publication Critical patent/WO2023207806A9/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements

Definitions

  • Embodiments of the present disclosure relate to, but are not limited to, the field of display technology, and in particular, to a shift register, a gate drive circuit, and a display device.
  • Gate Driver on Array (GOA) technology integrates Thin Film Transistor (TFT) gate switching circuits on the array substrate of the display panel to drive the display panel, thereby eliminating the need for integration
  • TFT Thin Film Transistor
  • Oxide thin film transistors have attracted more and more attention due to their transparent materials, relatively simple manufacturing process, and low process temperature.
  • new GOA circuits need to be designed to adapt to the low carrier mobility characteristics of oxide thin film transistors.
  • An embodiment of the present disclosure provides a shift register, including: a first control module, a first output module, a second output module, a second control module, a third control module, a fourth control module, a fifth control module, Six control modules and energy storage modules;
  • the first control module is connected to the first power signal terminal, the first input signal terminal and the second node, and is configured to provide the first power signal of the first power signal terminal to the first power signal terminal under the control of the first input signal of the first input signal terminal.
  • second node is connected to the first power signal terminal, the first input signal terminal and the second node, and is configured to provide the first power signal of the first power signal terminal to the first power signal terminal under the control of the first input signal of the first input signal terminal.
  • the first output module is connected to the second node, the first clock signal terminal and the first output signal terminal, and is configured to provide the first clock signal of the first clock signal terminal to the first output signal terminal under the voltage control of the second node. ;
  • the second output module is connected to the first node, the second power signal terminal and the first output signal terminal, and is configured to provide the second power signal of the second power signal terminal to the first output signal terminal under the voltage control of the first node. ;
  • the second control module is connected to the second power signal terminal, the second input signal terminal, the first clock signal terminal and the third node, and is configured to control the second power signal terminal of the second power signal terminal under the control of the second input signal of the second input signal terminal.
  • the second power signal is provided to the third node, and the second power signal of the second power signal terminal is provided to the third node under the control of the first clock signal of the first clock signal terminal;
  • the third control module is connected to the third node, the second clock signal terminal and the first node, and is configured to provide the second clock signal of the second clock signal terminal to the first node under the voltage control of the third node;
  • a fourth control module connected to the third node, the second power signal terminal and the second node, and configured to provide the second power signal of the second power signal terminal to the second node under voltage control of the third node;
  • a fifth control module connected to the first node, the second power signal terminal and the second node, and configured to provide the second power signal of the second power signal terminal to the second node under the voltage control of the first node;
  • a sixth control module connected to the second node, the second power signal terminal and the first node, and configured to provide the second power signal of the second power signal terminal to the first node under the voltage control of the second node;
  • the energy storage module includes a first capacitor, and two ends of the first capacitor are respectively connected to the third node and the second clock signal end.
  • Embodiments of the present disclosure also provide a gate drive circuit, including N cascaded shift registers SR(i); the first output signal terminal of the kth shift register SR(k) is connected to the k+1th The first input signal terminal of the shift register SR(k+1) is connected; 1 ⁇ k ⁇ N-1, N>1; at least one shift register SR(i) among the N shift registers adopts the above shift register; 1 ⁇ i ⁇ N.
  • An embodiment of the present disclosure also provides a display device, including the above gate driving circuit.
  • Figure 1 is a schematic structural diagram of a shift register provided by an embodiment of the present disclosure
  • Figure 2 is a schematic diagram of an equivalent circuit of a shift register provided by an embodiment of the present disclosure
  • Figure 3 is a schematic equivalent circuit diagram of another shift register (including a second capacitor and a third capacitor) provided by an embodiment of the present disclosure
  • Figure 4 is a schematic equivalent circuit diagram of another shift register (including a tenth transistor) provided by an embodiment of the present disclosure
  • Figure 5 is a schematic equivalent circuit diagram of another shift register provided by an embodiment of the present disclosure (including a second output signal terminal);
  • Figure 6 is a signal timing diagram of a shift register provided by an embodiment of the present disclosure.
  • Figure 7 is a signal timing diagram of another shift register provided by an embodiment of the present disclosure.
  • Figure 8 is a schematic diagram of a cascade structure of a gate drive circuit provided by an embodiment of the present disclosure.
  • Figure 9 is a schematic diagram of a cascade structure of a gate drive circuit provided by an embodiment of the present disclosure (the first input signal and the second input signal are the same);
  • FIG. 10 is a schematic diagram of a cascade structure of a gate driving circuit provided by an embodiment of the present disclosure (the first input signal and the second input signal are different).
  • connection should be understood in a broad sense.
  • it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, an indirect connection through an intermediate piece, or an internal connection between two elements.
  • connection should be understood in a broad sense.
  • it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, an indirect connection through an intermediate piece, or an internal connection between two elements.
  • a transistor refers to an element including at least three terminals: a gate, a drain, and a source.
  • the source and drain of a transistor are symmetrical.
  • the functions of "source” and “drain” may be interchanged.
  • one of the source electrode and the drain electrode is called a first electrode
  • the other of the source electrode and the drain electrode is called a second electrode
  • the gate electrode is called a control electrode.
  • electrical connection includes a case where constituent elements are connected together through an element having some electrical effect.
  • component having some electrical function There is no particular limitation on the “component having some electrical function” as long as it can transmit and receive electrical signals between the connected components.
  • elements having some electrical function include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.
  • the driving transistor is an N-type thin film transistor
  • other transistors are of the same or different types as the driving transistor depending on the circuit design.
  • the driving transistor may also be shown as a P-type thin film transistor.
  • the technology of the present disclosure can also be implemented by changing the types of other transistors accordingly and inverting the respective driving signals and level signals (and/or making other additional adaptive modifications). plan.
  • the shift register provided by an embodiment of the present disclosure includes: a first control module 10, a first output module 20, and a second output module. 30.
  • the first control module is connected to the first power signal terminal VGH, the first input signal terminal IN1 and the second node N2, and is configured to control the first power supply of the first power signal terminal under the control of the first input signal of the first input signal terminal.
  • the signal is provided to the second node;
  • the first output module is connected to the second node N2, the first clock signal terminal CK1 and the first output signal terminal OUT1, and is configured to provide the first clock signal of the first clock signal terminal to the first clock signal under the voltage control of the second node.
  • the second output module is connected to the first node N1, the second power signal terminal VGL and the first output signal terminal OUT1, and is configured to provide the second power signal of the second power signal terminal to the first power supply under the voltage control of the first node.
  • the second control module is connected to the second power signal terminal VGL, the second input signal terminal IN2, the first clock signal terminal CK1 and the third node N3, and is configured to control the second power supply signal terminal VGL under the control of the second input signal of the second input signal terminal.
  • the second power signal at the power signal terminal is provided to the third node, and the second power signal at the second power signal terminal is provided to the third node under the control of the first clock signal at the first clock signal terminal;
  • the third control module is connected to the third node N3, the second clock signal terminal CK2 and the first node N1, and is configured to provide the second clock signal of the second clock signal terminal to the first node under the voltage control of the third node;
  • the fourth control module is connected to the third node N3, the second power signal terminal VGL and the second node N2, and is configured to provide the second power signal of the second power signal terminal to the second node under the voltage control of the third node;
  • the fifth control module is connected to the first node N1, the second power signal terminal VGL and the second node N2, and is configured to provide the second power signal of the second power signal terminal to the second node under the voltage control of the first node;
  • the sixth control module is connected to the second node N2, the second power signal terminal VGL and the first node N1, and is configured to provide the second power signal of the second power signal terminal to the first node under the voltage control of the second node;
  • the energy storage module includes a first capacitor C1, and two ends of the first capacitor are respectively connected to the third node and the second clock signal terminal CK2.
  • the shift register provided in the above embodiment includes a first output module, a second output module, a first control module, a second control module, a third control module, a fourth control module, a fifth control module, a sixth control module and a storage module.
  • energy module provides the first clock signal of the first clock signal terminal to the first output signal terminal under the voltage control of the second node, and the second output module supplies the second power signal of the first clock signal terminal under the voltage control of the first node.
  • the second power signal of the terminal is provided to the first output signal terminal, the third control module and the sixth control module control the voltage of the first node, the first control module, the fourth control module and the fifth control module control the voltage of the second node,
  • the second control module controls the voltage of the third node.
  • the cooperation of the six control modules and the energy storage module can make the node potential jump in time, shorten the rising edge and falling edge time of the output pulse signal, and make the output waveform meet the requirements.
  • Figure 2 provides an equivalent circuit diagram of a shift register.
  • the first control module includes a first transistor T1, the control electrode of the first transistor is connected to the first input signal terminal, and the first The first terminal is connected to the first power signal terminal, and the second terminal of the first transistor is connected to the second node.
  • the first output module includes a second transistor T2, the control electrode of the second transistor is connected to the second node, and the first electrode of the second transistor is connected to The first clock signal terminal, the second pole of the second transistor is connected to the first output signal terminal.
  • the second output module includes a third transistor T3, the control electrode of the third transistor is connected to the first node, and the first electrode of the third transistor is connected to The second power signal terminal, the second pole of the third transistor is connected to the first output signal terminal.
  • the second control module includes a fourth transistor and a fifth transistor.
  • the control electrode of the fourth transistor is connected to the first clock signal terminal.
  • the fourth transistor The first pole of the fourth transistor is connected to the second power signal terminal, the second pole of the fourth transistor is connected to the third node, the control pole of the fifth transistor is connected to the second input signal terminal, and the first pole of the fifth transistor is connected to The second power signal terminal, the second pole of the fifth transistor is connected to the third node.
  • the third control module includes a sixth transistor T6, the control electrode of the sixth transistor is connected to the third node, and the first The second pole of the sixth transistor is connected to the second clock signal terminal, and the second pole of the sixth transistor is connected to the first node.
  • the fourth control module includes a seventh transistor T7, the control electrode of the seventh transistor is connected to the third node, and the first electrode of the seventh transistor is connected to The second power signal terminal, the second pole of the seventh transistor is connected to the second node.
  • the fifth control module includes an eighth transistor T8, the control electrode of the eighth transistor is connected to the first node, and the first electrode of the eighth transistor is connected to The second power signal terminal, the second pole of the eighth transistor is connected to the second node.
  • the sixth control module includes a ninth transistor T9, the control electrode of the ninth transistor is connected to the second node, and the first electrode of the ninth transistor is connected to The second power signal terminal, the second pole of the ninth transistor is connected to the first node.
  • Figure 3 provides an equivalent circuit diagram of an alternative shift register.
  • the first output module further includes a second capacitor C2.
  • One end of the second capacitor is connected to the control electrode of the second transistor. The other end is connected to the second pole of the second transistor.
  • the second capacitor is connected between the control electrode of the second transistor and the second electrode, and can stabilize the potential of the control electrode of the second transistor.
  • the second output module further includes a third capacitor C3.
  • One end of the third capacitor is connected to the control electrode of the third transistor. The other end is connected to the first pole of the third transistor.
  • the third capacitor is connected between the control electrode of the third transistor and the first electrode, and can stabilize the potential of the control electrode of the third transistor.
  • Figure 4 provides an equivalent circuit diagram of an alternative shift register.
  • the first output module further includes a tenth transistor T10, the control electrode of the tenth transistor is connected to the first power signal terminal, and the tenth transistor has a control electrode connected to the first power signal terminal.
  • One pole is connected to the second node, and the second pole of the tenth transistor is connected to the control pole of the second transistor. Providing the tenth transistor between the second node and the control electrode of the second transistor can stabilize the potential of the control electrode of the second transistor.
  • Figure 5 provides an equivalent circuit diagram of an alternative shift register.
  • the second node N2 is also connected to the second output signal terminal OUT2.
  • the second output signal terminal outputs a second output signal.
  • all transistors in the shift register are N-type transistors.
  • one working cycle of the shift register includes the following multiple periods: a first period, a second period, a third period. time period, fourth time period and multiple alternating fifth and sixth time periods;
  • the first power signal and the second power signal are DC signals, the first power signal is a high level signal, the second power signal is a low level signal, the first input signal and the second input signal are pulse signals, and the first clock signal and the second clock signal are periodic pulse signals; the first input signal and the second input signal are high-level signals in the first period and low-level signals in other periods; the first clock signal is in the first period and the third period. period and the fifth period are low-level signals, and are high-level signals during the second, fourth, and sixth periods; the second clock signal is a high-level signal during the first, third, and fifth periods. , it is a low-level signal in the second period, the fourth period and the sixth period.
  • one working cycle of the shift register includes the following multiple periods: a first period, a second period, a third period. time period, fourth time period and multiple alternating fifth and sixth time periods;
  • the first power signal and the second power signal are DC signals, the first power signal is a high level signal, the second power signal is a low level signal, the first input signal and the second input signal are pulse signals, and the first clock signal and the second clock signal is a periodic pulse signal;
  • the first input signal is a high-level signal in the first period and is a low-level signal in other periods;
  • the second input signal is high-level in the first period and the second period. signal, it is a low-level signal in other periods;
  • the first clock signal is a low-level signal in the first period, the third period and the fifth period, and it is a high-level signal in the second period, the fourth period and the sixth period.
  • the second clock signal is a high-level signal in the first period, the third period and the fifth period, and is a low-level signal in the second period, the fourth period and the sixth period.
  • all transistors in the shift register are oxide thin film transistors.
  • the carrier mobility of the oxide thin film transistor is low.
  • the cooperation of the six control modules and the energy storage module can make the node potential jump in time, shorten the rising edge and falling edge time of the output pulse signal, and make the output waveform meet the requirements. Require.
  • Figure 6 provides a signal timing diagram of the shift register.
  • the shift register adopts any structure from Figure 2 to Figure 5. All transistors are N-type transistors.
  • the first power signal terminal provides the first power signal
  • the second power signal terminal provides the second power signal
  • the first clock signal The first clock signal terminal provides the first clock signal
  • the second clock signal terminal provides the second clock signal
  • the first input signal terminal provides the first input signal
  • the second input signal terminal provides the second input signal
  • the first output signal terminal outputs the first output signal
  • the second output signal terminal outputs the second output signal (for Figure 5).
  • the first power signal and the second power signal are DC signals
  • the first input signal and the second input signal are pulse signals
  • the first input signal and the second input signal are the same
  • the first clock signal and the second clock signal are periodic pulses. signals, the first clock signal and the second clock signal have opposite phases.
  • the transistor gate when the voltage of the transistor gate (control electrode) is higher than the turn-on voltage, the transistor is turned on. When the voltage of the transistor gate is lower than the turn-on voltage, the transistor is in the off state.
  • a high-level signal is a signal higher than the turn-on voltage of the transistor, and a low-level signal is a signal lower than the turn-on voltage of the transistor.
  • the first power signal is a high-level signal, and the second power signal is a low-level signal.
  • a working cycle of the shift register may include multiple periods: a first period (t1), a second period (t2), a third period (t3), a fourth period (t4) and a fifth period (t4) that appears alternately multiple times. t5) and the sixth period (t6).
  • the first input signal and the second input signal are high-level signals
  • the first clock signal is a low-level signal
  • the second clock signal is a high-level signal
  • the first clock signal is a low-level signal
  • the fourth transistor is turned off
  • the second input signal is a high-level signal
  • the fifth transistor is turned on
  • the second power signal is provided to the third node.
  • the second power supply signal is a low-level signal, so the potential of the third node is low-level.
  • the potential of the third node is low level, and the sixth transistor and the seventh transistor are turned off.
  • the second clock signal is a high-level signal, and the second clock signal charges the first capacitor.
  • the first input signal is a high level signal, the first transistor is turned on, and the first power signal is provided to the second node.
  • the first power signal is a high-level signal, so the potential of the second node is high-level.
  • the potential of the second node is high level, the ninth transistor is turned on, and the second power signal is provided to the first node.
  • the second power supply signal is a low level signal, so the potential of the first node is low level.
  • the potential of the first node is low level, and the third transistor and the eighth transistor are turned off.
  • the potential of the second node is high level, the second transistor is turned on, and the first clock signal is provided to the first output signal terminal.
  • the first clock signal is a low-level signal, so the first output signal output from the first output signal terminal is a low-level signal.
  • the second output signal output by the second output signal terminal is a high-level signal.
  • the first input signal and the second input signal are low-level signals
  • the first clock signal is a high-level signal
  • the second clock signal is a low-level signal
  • the second input signal is a low-level signal
  • the fifth transistor is turned off
  • the first clock signal is a high-level signal
  • the fourth transistor is turned on
  • the second power signal is provided to the third node.
  • the second power supply signal is a low-level signal, so the potential of the third node is low-level.
  • the potential of the third node is low level, and the sixth transistor and the seventh transistor are turned off.
  • the first input signal is a low-level signal
  • the first transistor is turned off
  • the second node maintains the potential of the previous period (t1), and the potential of the previous period is high level.
  • the potential of the second node is high level, the ninth transistor is turned on, and the second power signal is provided to the first node.
  • the second power supply signal is a low level signal, so the potential of the first node is low level.
  • the potential of the first node is low level, and the third transistor and the eighth transistor are turned off.
  • the potential of the second node is high level, the second transistor is turned on, and the first clock signal is provided to the first output signal terminal.
  • the first clock signal is a high-level signal, so the first output signal output from the first output signal terminal jumps from a low-level signal to a high-level signal. Since the second transistor is always in the on state during the second period, it can quickly follow the transition of the first clock signal, thereby shortening the rising edge time of the first output signal.
  • the second output signal output by the second output signal terminal is a high-level signal.
  • the first input signal and the second input signal are high-level signals
  • the first clock signal is a low-level signal
  • the second clock signal is a high-level signal
  • the first clock signal is a low-level signal, and the fourth transistor is turned off.
  • the second input signal is a low-level signal, and the fifth transistor is turned off.
  • the second clock signal jumps from a low level signal to a high level signal, and the third node also jumps from a low level to a high level under the action of the third capacitor.
  • the sixth transistor and the seventh transistor are turned on, the second clock signal is provided to the first node, and the second power signal is provided to the second node.
  • the second clock signal is a high-level signal, and the potential of the first node jumps from low level to high level.
  • the first input signal is a low level signal, and the first transistor is turned off.
  • the second power supply signal is a low level signal, and the potential of the second node changes from high level to low level.
  • the potential of the second node is low level, and the ninth transistor and the second transistor are turned off.
  • the potential of the first node is high level, and the eighth transistor and the third transistor are turned on.
  • the second power signal is provided to the second node, the second power signal is a low level signal, and the potential of the second node is low level.
  • the second power signal is provided to the first output signal terminal, the second power signal is a low-level signal, and the first output signal output by the first output signal terminal transitions from a high-level signal to a low-level signal.
  • the potential of the second node and the first node are controlled to jump at the same time, so that the second transistor is turned off and the third transistor is turned on at the same time, and the first output signal jumps from high level to low level. flat, shortening the falling edge time of the first output signal.
  • the second output signal output by the second output signal terminal is a low level signal.
  • the first input signal and the second input signal are low-level signals
  • the first clock signal is a high-level signal
  • the second clock signal is a low-level signal
  • the second input signal is a low-level signal
  • the fifth transistor is turned off
  • the first clock signal is a high-level signal
  • the fourth transistor is turned on
  • the second power signal is provided to the third node.
  • the second power supply signal is a low-level signal, so the potential of the third node changes from high level to low level.
  • the potential of the third node is low level, and the sixth transistor and the seventh transistor are turned off.
  • the first input signal is a low level signal
  • the first transistor is turned off
  • the second node maintains the potential of the previous period (t3), and the potential of the previous period is low level.
  • the potential of the second node is low level, and the ninth transistor and the second transistor are turned off.
  • the sixth transistor and the ninth transistor are turned off, the first node maintains the potential of the previous period (t3), and the potential of the previous period is high level.
  • the potential of the first node is high level, and the eighth transistor and the third transistor continue to remain on.
  • the potential of the second node continues to maintain a low level, and the first output signal continues to maintain a low level signal.
  • the third capacitor maintains the high level of the control electrode of the third transistor.
  • the second output signal output by the second output signal terminal is a low level signal.
  • the fifth period and the sixth period alternately appear multiple times until the end of this work cycle.
  • the first input signal and the second input signal are low-level signals
  • the first clock signal is a low-level signal
  • the second clock signal is a high-level signal
  • the first clock signal is a low-level signal, and the fourth transistor is turned off.
  • the second input signal is a low-level signal, and the fifth transistor is turned off.
  • the second clock signal jumps from a low level signal to a high level signal, and the third node also jumps from a low level to a high level under the action of the third capacitor.
  • the sixth transistor and the seventh transistor are turned on, the second clock signal is provided to the first node, and the second power signal is provided to the second node.
  • the second clock signal is a high-level signal, and the potential of the first node continues to maintain a high level.
  • the first input signal is a low level signal, and the first transistor is turned off.
  • the second power supply signal is a low level signal, and the potential of the second node continues to maintain a low level.
  • the potential of the second node is low level, and the ninth transistor and the second transistor are turned off.
  • the potential of the first node is high level, and the eighth transistor and the third transistor continue to remain on.
  • the potential of the second node continues to maintain a low level, and the first output signal continues to maintain a low level signal.
  • the third capacitor is connected across the control electrode of the third transistor and the first electrode, the first node charges the third capacitor.
  • the second output signal output by the second output signal terminal is a low level signal.
  • the first input signal and the second input signal are low-level signals
  • the first clock signal is a high-level signal
  • the second clock signal is a low-level signal
  • the second input signal is a low-level signal
  • the fifth transistor is turned off
  • the first clock signal is a high-level signal
  • the fourth transistor is turned on
  • the second power signal is provided to the third node.
  • the second power supply signal is a low-level signal, so the potential of the third node changes from high level to low level.
  • the potential of the third node is low level, and the sixth transistor and the seventh transistor are turned off.
  • the first input signal is a low level signal
  • the first transistor is turned off
  • the second node maintains the potential of the previous period (t5), and the potential of the previous period is low level.
  • the potential of the second node is low level, and the ninth transistor and the second transistor are turned off.
  • the sixth transistor and the ninth transistor are turned off, the first node maintains the potential of the previous period (t5), and the potential of the previous period is high level.
  • the potential of the first node is high level, and the eighth transistor and the third transistor continue to remain on.
  • the potential of the second node continues to maintain a low level, and the first output signal continues to maintain a low level signal.
  • the third capacitor maintains the high level of the control electrode of the third transistor.
  • the second output signal output by the second output signal terminal is a low level signal.
  • Figure 7 provides an alternative signal timing diagram for the shift register.
  • the shift register adopts any structure from Figure 2 to Figure 5.
  • All transistors are N-type transistors.
  • the first power signal terminal provides the first power signal
  • the second power signal terminal provides the second power signal
  • the first clock signal The first clock signal terminal provides the first clock signal
  • the second clock signal terminal provides the second clock signal
  • the first input signal terminal provides the first input signal
  • the second input signal terminal provides the second input signal
  • the first output signal terminal outputs the first output signal
  • the second output signal terminal outputs the second output signal (for Figure 5).
  • the first power signal and the second power signal are DC signals
  • the first input signal and the second input signal are pulse signals
  • the first input signal and the second input signal are different
  • a working cycle of the shift register can include multiple periods: the first period (t1), the second period The period (t2), the third period (t3), the fourth period (t4) and the fifth period (t5) and the sixth period (t6) appear alternately multiple times.
  • the first input signal in Figure 6 has the same waveform as the first input signal in Figure 7, and the second input signal in Figure 6 has a different waveform from the second input signal in Figure 7.
  • the difference is that the second input signal in Figure 6 has a second waveform. period is low level, and the second input signal of FIG. 7 is high level during the second period.
  • the embodiment of the present disclosure also provides a gate drive circuit, including N cascaded shift registers SR(i); the first output signal terminal of the kth shift register SR(k) Connected to the first input signal terminal of the k+1th shift register SR(k+1); 1 ⁇ k ⁇ N-1, N>1; at least one shift register SR(i) among the N shift registers
  • the shift register in the above embodiment is used; 1 ⁇ i ⁇ N.
  • the first output signal terminal of the k-th shift register SR(k) is also connected to the second output signal terminal of the k+1-th shift register SR(k+1). Input signal terminal connection.
  • the signals input to the first input signal terminal and the second input signal terminal of the shift register are the same.
  • the gate drive circuit also includes N other cascaded shift registers R(i), the k+1th shift register SR(k+1 ) is connected to the output signal terminal GOUT of the kth other shift register R(k); 1 ⁇ k ⁇ N-1, N>1;1 ⁇ i ⁇ N; the kth other shift register
  • the output signal output from the output signal terminal of R(k) meets the requirements of the second input signal of the k+1th shift register SR(k+1). In this case, the signals input to the first input signal terminal and the second input signal terminal of the shift register are different.
  • the above-mentioned gate driving circuit can be connected to the pixel driving circuit of the display panel, and is used to provide various control signals to the pixel driving circuit, such as row scanning signals, reset signals, etc.
  • the display panel includes an organic light-emitting diode (OLED) display panel.
  • OLED organic light-emitting diode
  • An embodiment of the present disclosure also provides a display device, including the above gate driving circuit.
  • the display device may be: a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, or any other product or component with a display function.
  • Other essential components of the display device are understood by those of ordinary skill in the art, and will not be described in detail here, nor should they be used to limit the present invention.

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Abstract

一种移位寄存器、栅极驱动电路及显示装置，移位寄存器包括第一控制模块（10）、第一输出模块（20）、第二输出模块（30）、第二控制模块（40）、第三控制模块（50）、第四控制模块（60）、第五控制模块（70）、第六控制模块（80）和储能模块（90）；第一输出模块（20）在第二节点（N2）的电压控制下将第一电源信号端（VGH）的第一电源信号提供给第一输出信号端（OUT1），第二输出模块（30）在第一节点（N1）的电压控制下将第二电源信号端（VGL）的第二电源信号提供给第一输出信号端（OUT1）。第一控制模块（10）、第二控制模块（40）、第三控制模块（50）、第四控制模块（60）、第五控制模块（70）、第六控制模块（80）和储能模块（90）互相配合控制第一节点（N1）、第二节点（N2）和第三节点（N3）的电位。

Description

移位寄存器、栅极驱动电路及显示装置
本申请要求于2022年4月24日提交中国专利局、申请号为202210455783.7、发明名称为“移位寄存器、栅极驱动电路及显示装置”的中国专利申请的优先权，其内容应理解为通过引用的方式并入本申请中。
技术领域
本公开实施例涉及但不限于显示技术领域，尤其涉及一种移位寄存器、栅极驱动电路及显示装置。
背景技术
阵列基板行驱动(Gate Driver on Array，简称GOA)技术将薄膜晶体管(Thin Film Transistor，简称TFT)栅极开关电路集成在显示面板的阵列基板上以形成对显示面板的驱动，从而可以省去集成电路(Integrated Circuit，简称IC)的绑定(Bonding)区域以及扇出(Fan-out)区域的布线空间，从而实现窄边框。
氧化物薄膜晶体管由于材料透明以及制作工艺相对简单、工艺温度低受到越来越多的关注。针对氧化物薄膜晶体管，需要设计新的GOA电路以适应氧化物薄膜晶体管载流子迁移率较低的特点。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开实施例提供了一种移位寄存器，包括：第一控制模块、第一输出模块、第二输出模块、第二控制模块、第三控制模块、第四控制模块、第五控制模块、第六控制模块和储能模块；
第一控制模块，与第一电源信号端、第一输入信号端和第二节点连接，设置为在第一输入信号端的第一输入信号的控制下将第一电源信号端的第一电源信号提供给第二节点；
第一输出模块，与第二节点、第一时钟信号端和第一输出信号端连接，设置为在第二节点的电压控制下将第一时钟信号端的第一时钟信号提供给第一输出信号端；
第二输出模块，与第一节点、第二电源信号端和第一输出信号端连接，设置为在第一节点的电压控制下将第二电源信号端的第二电源信号提供给第一输出信号端；
第二控制模块，与第二电源信号端、第二输入信号端、第一时钟信号端和第三节点连接，设置为在第二输入信号端的第二输入信号控制下将第二电源信号端的第二电源信号提供给第三节点，在第一时钟信号端的第一时钟信号的控制下将第二电源信号端的第二电源信号提供给第三节点；
第三控制模块，与第三节点、第二时钟信号端和第一节点连接，设置为在第三节点的电压控制下将第二时钟信号端的第二时钟信号提供给第一节点；
第四控制模块，与第三节点、第二电源信号端和第二节点连接，设置为在第三节点的电压控制下将第二电源信号端的第二电源信号提供给第二节点；
第五控制模块，与第一节点、第二电源信号端和第二节点连接，设置为在第一节点的电压控制下将第二电源信号端的第二电源信号提供给第二节点；
第六控制模块，与第二节点、第二电源信号端和第一节点连接，设置为在第二节点的电压控制下将第二电源信号端的第二电源信号提供给第一节点；
储能模块，包括第一电容，所述第一电容的两端分别与第三节点和第二时钟信号端连接。
本公开实施例还提供了一种栅极驱动电路，包括N个级联的移位寄存器SR(i)；第k个移位寄存器SR(k)的第一输出信号端与第k+1个移位寄存器SR(k+1)的第一输入信号端连接；1≤k≤N-1，N>1；N个移位寄存器中至少一个移位寄存器SR(i)采用上述移位寄存器；1≤i≤N。
本公开实施例还提供了一种显示装置，包括上述栅极驱动电路。
在阅读并理解了附图和详细描述后，可以明白其它方面。
附图说明
附图用来提供对本公开技术方案的理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开技术方案的限制。
图1为本公开实施例提供的一种移位寄存器的结构示意图；
图2为本公开实施例提供的一种移位寄存器的等效电路示意图；
图3为本公开实施例提供的另一种移位寄存器的等效电路示意图(包括第二电容和第三电容)；
图4为本公开实施例提供的另一种移位寄存器的等效电路示意图(包括第十晶体管)；
图5为本公开实施例提供的另一种移位寄存器的等效电路示意图(包括第二输出信号端)；
图6为本公开实施例提供的一种移位寄存器的信号时序图；
图7为本公开实施例提供的另一种移位寄存器的信号时序图；
图8为本公开实施例提供的一种栅极驱动电路的级联结构示意图；
图9为本公开实施例提供的一种栅极驱动电路的级联结构示意图(第一输入信号和第二输入信号相同)；
图10为本公开实施例提供的一种栅极驱动电路的级联结构示意图(第一输入信号和第二输入信号不同)。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚明白，下文中将结合附图对本公开的实施例进行详细说明。注意，实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为各种各样的形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
在附图中，有时为了明确起见，夸大表示了各构成要素的大小、层的厚 度或区域。因此，本公开的一个方式并不一定限定于该尺寸，附图中各部件的形状和大小不反映真实比例。此外，附图示意性地示出了理想的例子，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本公开中的具体含义。
在本说明书中，晶体管是指至少包括栅极、漏极以及源极这三个端子的元件。晶体管的源极、漏极是对称的，在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源极”及“漏极”的功能有时互相调换。在本公开实施例中，将源极和漏极中的一个称为第一极，将源极和漏极中的另一个称为第二极，栅极称为控制极。
在本说明书中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有各种功能的元件等。
在以下示例中以驱动晶体管为N型薄膜晶体管的情况进行描述，其他晶体管根据电路设计与驱动晶体管具有相同或不同的类型。类似地，在其他实施例中，驱动晶体管也可以被示为P型薄膜晶体管。本领域技术人员能够理解的是，通过将其他晶体管的类型相应地改变并将各驱动信号和电平信号进行反相(和/或进行其他附加的适应性修改)，同样能够实现本公开的技术方案。
本公开实施例提供了一种移位寄存器，如图1所示，本公开实施例提供的移位寄存器，包括：第一控制模块10、第一输出模块20、第二输出模块 30、第二控制模块40、第三控制模块50、第四控制模块60、第五控制模块70、第六控制模块80和储能模块90；
第一控制模块，与第一电源信号端VGH、第一输入信号端IN1和第二节点N2连接，设置为在第一输入信号端的第一输入信号的控制下将第一电源信号端的第一电源信号提供给第二节点；
第一输出模块，与第二节点N2、第一时钟信号端CK1和第一输出信号端OUT1连接，设置为在第二节点的电压控制下将第一时钟信号端的第一时钟信号提供给第一输出信号端；
第二输出模块，与第一节点N1、第二电源信号端VGL和第一输出信号端OUT1连接，设置为在第一节点的电压控制下将第二电源信号端的第二电源信号提供给第一输出信号端；
第二控制模块，与第二电源信号端VGL、第二输入信号端IN2、第一时钟信号端CK1和第三节点N3连接，设置为在第二输入信号端的第二输入信号控制下将第二电源信号端的第二电源信号提供给第三节点，在第一时钟信号端的第一时钟信号的控制下将第二电源信号端的第二电源信号提供给第三节点；
第三控制模块，与第三节点N3、第二时钟信号端CK2和第一节点N1连接，设置为在第三节点的电压控制下将第二时钟信号端的第二时钟信号提供给第一节点；
第四控制模块，与第三节点N3、第二电源信号端VGL和第二节点N2连接，设置为在第三节点的电压控制下将第二电源信号端的第二电源信号提供给第二节点；
第五控制模块，与第一节点N1、第二电源信号端VGL和第二节点N2连接，设置为在第一节点的电压控制下将第二电源信号端的第二电源信号提供给第二节点；
第六控制模块，与第二节点N2、第二电源信号端VGL和第一节点N1连接，设置为在第二节点的电压控制下将第二电源信号端的第二电源信号提供给第一节点；
储能模块，包括第一电容C1，所述第一电容的两端分别与第三节点和第二时钟信号端CK2连接。
上述实施例提供的移位寄存器包括第一输出模块、第二输出模块、第一控制模块、第二控制模块、第三控制模块、第四控制模块、第五控制模块、第六控制模块和储能模块；第一输出模块在第二节点的电压控制下将第一时钟信号端的第一时钟信号提供给第一输出信号端，第二输出模块在第一节点的电压控制下将第二电源信号端的第二电源信号提供给第一输出信号端，第三控制模块和第六控制模块控制第一节点的电压，第一控制模块、第四控制模块和第五控制模块控制第二节点的电压，第二控制模块控制第三节点的电压，通过六个控制模块和储能模块的配合能够使得节点电位及时跳变，缩短输出的脉冲信号的上升沿和下降沿的时间，使得输出波形满足要求。
图2提供了一种移位寄存器的等效电路图。
如图2所示，在一些示例性的实施方式中，所述第一控制模块包括第一晶体管T1，所述第一晶体管的控制极连接第一输入信号端，所述第一晶体管的第一极连接第一电源信号端，所述第一晶体管的第二极连接第二节点。
如图2所示，在一些示例性的实施方式中，所述第一输出模块包括第二晶体管T2，所述第二晶体管的控制极连接第二节点，所述第二晶体管的第一极连接第一时钟信号端，所述第二晶体管的第二极连接第一输出信号端。
如图2所示，在一些示例性的实施方式中，所述第二输出模块包括第三晶体管T3，所述第三晶体管的控制极连接第一节点，所述第三晶体管的第一极连接第二电源信号端，所述第三晶体管的第二极连接第一输出信号端。
如图2所示，在一些示例性的实施方式中，所述第二控制模块包括第四晶体管和第五晶体管，所述第四晶体管的控制极连接第一时钟信号端，所述第四晶体管的第一极连接第二电源信号端，所述第四晶体管的第二极连接第三节点，所述第五晶体管的控制极连接第二输入信号端，所述第五晶体管的第一极连接第二电源信号端，所述第五晶体管的第二极连接第三节点。
如图2所示，在一些示例性的实施方式中，所述第三控制模块包括第六晶体管T6，所述第六晶体管的控制极连接第三节点，所述第六晶体管的第一 极连接第二时钟信号端，所述第六晶体管的第二极连接第一节点。
如图2所示，在一些示例性的实施方式中，所述第四控制模块包括第七晶体管T7，所述第七晶体管的控制极连接第三节点，所述第七晶体管的第一极连接第二电源信号端，所述第七晶体管的第二极连接第二节点。
如图2所示，在一些示例性的实施方式中，所述第五控制模块包括第八晶体管T8，所述第八晶体管的控制极连接第一节点，所述第八晶体管的第一极连接第二电源信号端，所述第八晶体管的第二极连接第二节点。
如图2所示，在一些示例性的实施方式中，所述第六控制模块包括第九晶体管T9，所述第九晶体管的控制极连接第二节点，所述第九晶体管的第一极连接第二电源信号端，所述第九晶体管的第二极连接第一节点。
图3提供了另一种移位寄存器的等效电路图。
如图3所示，在一些示例性的实施方式中，所述第一输出模块还包括第二电容C2，所述第二电容的一端与第二晶体管的控制极连接，所述第二电容的另一端与第二晶体管的第二极连接。第二电容跨接在第二晶体管的控制极和第二极之间，能够稳定第二晶体管的控制极的电位。
如图3所示，在一些示例性的实施方式中，所述第二输出模块还包括第三电容C3，所述第三电容的一端与第三晶体管的控制极连接，所述第三电容的另一端与第三晶体管的第一极连接。第三电容跨接在第三晶体管的控制极和第一极之间，能够稳定第三晶体管的控制极的电位。
图4提供了另一种移位寄存器的等效电路图。
如图4所示，在一些示例性的实施方式中，所述第一输出模块还包括第十晶体管T10，所述第十晶体管的控制极连接第一电源信号端，所述第十晶体管的第一极连接第二节点，所述第十晶体管的第二极连接第二晶体管的控制极。在第二节点和第二晶体管的控制极之间设置第十晶体管，能够稳定第二晶体管的控制极的电位。
图5提供了另一种移位寄存器的等效电路图。
如图5所示，在一些示例性的实施方式中，所述第二节点N2还连接第二输出信号端OUT2。第二输出信号端输出第二输出信号。
在一些示例性的实施方式中，所述移位寄存器中所有的晶体管为N型晶体管。
在一些示例性的实施方式中，当所述移位寄存器中所有的晶体管为N型晶体管时，所述移位寄存器的一个工作周期包括以下多个时段：第一时段、第二时段、第三时段、第四时段和多次交替出现的第五时段和第六时段；
第一电源信号和第二电源信号为直流信号，第一电源信号为高电平信号，第二电源信号为低电平信号，第一输入信号和第二输入信号为脉冲信号，第一时钟信号和第二时钟信号为周期性脉冲信号；第一输入信号和第二输入信号在第一时段为高电平信号，在其他时段为低电平信号；第一时钟信号在第一时段、第三时段和第五时段为低电平信号，在第二时段、第四时段和第六时段为高电平信号；第二时钟信号在第一时段、第三时段和第五时段为高电平信号，在第二时段、第四时段和第六时段为低电平信号。
在一些示例性的实施方式中，当所述移位寄存器中所有的晶体管为N型晶体管时，所述移位寄存器的一个工作周期包括以下多个时段：第一时段、第二时段、第三时段、第四时段和多次交替出现的第五时段和第六时段；
第一电源信号和第二电源信号为直流信号，第一电源信号为高电平信号，第二电源信号为低电平信号，第一输入信号和第二输入信号为脉冲信号，第一时钟信号和第二时钟信号为周期性脉冲信号；第一输入信号在第一时段为高电平信号，在其他时段为低电平信号；第二输入信号在第一时段和第二时段为高电平信号，在其他时段为低电平信号；第一时钟信号在第一时段、第三时段和第五时段为低电平信号，在第二时段、第四时段和第六时段为高电平信号；第二时钟信号在第一时段、第三时段和第五时段为高电平信号，在第二时段、第四时段和第六时段为低电平信号。
在一些示例性的实施方式中，所述移位寄存器中所有的晶体管为氧化物薄膜晶体管。氧化物薄膜晶体管的载流子迁移率较低，通过六个控制模块和储能模块的配合能够使得节点电位及时跳变，缩短输出的脉冲信号的上升沿和下降沿的时间，使得输出波形满足要求。
下面结合信号时序图对移位寄存器的工作过程进行说明。
图6提供了移位寄存器的一种信号时序图。移位寄存器采用图2至图5中任意一种结构，所有的晶体管都是N型晶体管，第一电源信号端提供第一电源信号，第二电源信号端提供第二电源信号，第一时钟信号端提供第一时钟信号，第二时钟信号端提供第二时钟信号，第一输入信号端提供第一输入信号，第二输入信号端提供第二输入信号，第一输出信号端输出第一输出信号，第二输出信号端输出第二输出信号(针对图5)。第一电源信号和第二电源信号为直流信号，第一输入信号和第二输入信号为脉冲信号，第一输入信号和第二输入信号相同，第一时钟信号和第二时钟信号为周期性脉冲信号，第一时钟信号和第二时钟信号相位相反。
对于N型晶体管，当晶体管栅极(控制极)的电压高于开启电压时，晶体管导通，当晶体管栅极的电压低于开启电压时，晶体管处于截止状态。高电平信号为高于晶体管开启电压的信号，低电平信号为低于晶体管开启电压的信号。第一电源信号为高电平信号，第二电源信号为低电平信号。
移位寄存器的一个工作周期可以包括多个时段：第一时段(t1)、第二时段(t2)、第三时段(t3)、第四时段(t4)和多次交替出现的第五时段(t5)与第六时段(t6)。
(一)第一时段(t1时段)
第一输入信号和第二输入信号为高电平信号，第一时钟信号为低电平信号，第二时钟信号为高电平信号。
第一时钟信号为低电平信号，第四晶体管截止，第二输入信号为高电平信号，第五晶体管导通，第二电源信号提供给第三节点。第二电源信号为低电平信号，所以第三节点的电位为低电平。
第三节点的电位为低电平，第六晶体管和第七晶体管截止。第二时钟信号为高电平信号，第二时钟信号给第一电容充电。
第一输入信号为高电平信号，第一晶体管导通，第一电源信号提供给第二节点。第一电源信号为高电平信号，所以第二节点的电位为高电平。
第二节点的电位为高电平，第九晶体管导通，第二电源信号提供给第一 节点。第二电源信号为低电平信号，所以第一节点的电位为低电平。
第一节点的电位为低电平，第三晶体管和第八晶体管截止。第二节点的电位为高电平，第二晶体管导通，第一时钟信号提供给第一输出信号端。第一时钟信号为低电平信号，所以第一输出信号端输出的第一输出信号为低电平信号。当第二电容跨接在第二晶体管的控制极和第二极之间时，第二节点给第二电容充电。
当第二节点还连接第二输出信号端时，第二输出信号端输出的第二输出信号为高电平信号。
(二)第二时段(t2时段)
第一输入信号和第二输入信号为低电平信号，第一时钟信号为高电平信号，第二时钟信号为低电平信号。
第二输入信号为低电平信号，第五晶体管截止，第一时钟信号为高电平信号，第四晶体管导通，第二电源信号提供给第三节点。第二电源信号为低电平信号，所以第三节点的电位为低电平。
第三节点的电位为低电平，第六晶体管和第七晶体管截止。
第一输入信号为低电平信号，第一晶体管截止，第二节点保持上一个时段(t1)的电位，上一个时段的电位为高电平。
第二节点的电位为高电平，第九晶体管导通，第二电源信号提供给第一节点。第二电源信号为低电平信号，所以第一节点的电位为低电平。
第一节点的电位为低电平，第三晶体管和第八晶体管截止。第二节点的电位为高电平，第二晶体管导通，第一时钟信号提供给第一输出信号端。第一时钟信号为高电平信号，所以第一输出信号端输出的第一输出信号从低电平信号跳变为高电平信号。由于第二晶体管在第二时段一直处于导通状态，所以能够快速跟随第一时钟信号的跳变而跳变，缩短了第一输出信号的上升沿时间。
当第二节点还连接第二输出信号端时，第二输出信号端输出的第二输出信号为高电平信号。
(三)第三时段(t3时段)
第一输入信号和第二输入信号为高电平信号，第一时钟信号为低电平信号，第二时钟信号为高电平信号。
第一时钟信号为低电平信号，第四晶体管截止，第二输入信号为低电平信号，第五晶体管截止。
第二时钟信号由低电平信号跳变为高电平信号，第三节点在第三电容的作用下也由低电平跳变为高电平。第三节点跳变为高电平后，第六晶体管和第七晶体管导通，第二时钟信号提供给第一节点，第二电源信号提供给第二节点。第二时钟信号为高电平信号，第一节点的电位由低电平跳变为高电平。第一输入信号为低电平信号，第一晶体管截止。第二电源信号为低电平信号，第二节点的电位由高电平变为低电平。
第二节点的电位为低电平，第九晶体管和第二晶体管截止。
第一节点的电位为高电平，第八晶体管和第三晶体管导通。第二电源信号提供给第二节点，第二电源信号为低电平信号，第二节点的电位为低电平。第二电源信号提供给第一输出信号端，第二电源信号为低电平信号，第一输出信号端输出的第一输出信号由高电平信号跳变为低电平信号。当第三电容跨接在第三晶体管的控制极和第一极之间时，第一节点给第三电容充电。
第三节点的电位跳变后同时控制第二节点和第一节点的电位发生跳变，使得第二晶体管截止和第三晶体管导通同时发生，第一输出信号由高电平跳变为低电平，缩短了第一输出信号的下降沿的时间。
当第二节点还连接第二输出信号端时，第二输出信号端输出的第二输出信号为低电平信号。
(四)第四时段(t4时段)
第一输入信号和第二输入信号为低电平信号，第一时钟信号为高电平信号，第二时钟信号为低电平信号。
第二输入信号为低电平信号，第五晶体管截止，第一时钟信号为高电平信号，第四晶体管导通，第二电源信号提供给第三节点。第二电源信号为低电平信号，所以第三节点的电位由高电平变为低电平。
第三节点的电位为低电平，第六晶体管和第七晶体管截止。
第一输入信号为低电平信号，第一晶体管截止，第二节点保持上一个时段(t3)的电位，上一个时段的电位为低电平。
第二节点的电位为低电平，第九晶体管和第二晶体管截止。
第六晶体管和第九晶体管截止，第一节点保持上一个时段(t3)的电位，上一个时段的电位为高电平。
第一节点的电位为高电平，第八晶体管和第三晶体管继续保持导通。第二节点的电位继续保持低电平，第一输出信号继续保持低电平信号。第三电容保持第三晶体管控制极的高电平。
当第二节点还连接第二输出信号端时，第二输出信号端输出的第二输出信号为低电平信号。
第四时段之后，第五时段和第六时段多次交替出现直至本工作周期结束。
(五)第五时段(t5时段)
第一输入信号和第二输入信号为低电平信号，第一时钟信号为低电平信号，第二时钟信号为高电平信号。
第一时钟信号为低电平信号，第四晶体管截止，第二输入信号为低电平信号，第五晶体管截止。
第二时钟信号由低电平信号跳变为高电平信号，第三节点在第三电容的作用下也由低电平跳变为高电平。第三节点跳变为高电平后，第六晶体管和第七晶体管导通，第二时钟信号提供给第一节点，第二电源信号提供给第二节点。第二时钟信号为高电平信号，第一节点的电位继续保持高电平。第一输入信号为低电平信号，第一晶体管截止。第二电源信号为低电平信号，第二节点的电位继续保持低电平。
第二节点的电位为低电平，第九晶体管和第二晶体管截止。
第一节点的电位为高电平，第八晶体管和第三晶体管继续保持导通。第二节点的电位继续保持低电平，第一输出信号继续保持低电平信号。当第三电容跨接在第三晶体管的控制极和第一极之间时，第一节点给第三电容充电。
当第二节点还连接第二输出信号端时，第二输出信号端输出的第二输出信号为低电平信号。
(六)第六时段(t6时段)
第一输入信号和第二输入信号为低电平信号，第一时钟信号为高电平信号，第二时钟信号为低电平信号。
第二输入信号为低电平信号，第五晶体管截止，第一时钟信号为高电平信号，第四晶体管导通，第二电源信号提供给第三节点。第二电源信号为低电平信号，所以第三节点的电位由高电平变为低电平。
第三节点的电位为低电平，第六晶体管和第七晶体管截止。
第一输入信号为低电平信号，第一晶体管截止，第二节点保持上一个时段(t5)的电位，上一个时段的电位为低电平。
第二节点的电位为低电平，第九晶体管和第二晶体管截止。
第六晶体管和第九晶体管截止，第一节点保持上一个时段(t5)的电位，上一个时段的电位为高电平。
第一节点的电位为高电平，第八晶体管和第三晶体管继续保持导通。第二节点的电位继续保持低电平，第一输出信号继续保持低电平信号。第三电容保持第三晶体管控制极的高电平。
当第二节点还连接第二输出信号端时，第二输出信号端输出的第二输出信号为低电平信号。
图7提供了移位寄存器的另一种信号时序图。移位寄存器采用图2至图5中任意一种结构，所有的晶体管都是N型晶体管，第一电源信号端提供第一电源信号，第二电源信号端提供第二电源信号，第一时钟信号端提供第一时钟信号，第二时钟信号端提供第二时钟信号，第一输入信号端提供第一输入信号，第二输入信号端提供第二输入信号，第一输出信号端输出第一输出信号，第二输出信号端输出第二输出信号(针对图5)。第一电源信号和第二电源信号为直流信号，第一输入信号和第二输入信号为脉冲信号，第一输入信号和第二输入信号不同，第一时钟信号和第二时钟信号为周期性脉冲信号，第一时钟信号和第二时钟信号相位相反。
移位寄存器的一个工作周期可以包括多个时段：第一时段(t1)、第二 时段(t2)、第三时段(t3)、第四时段(t4)和多次交替出现的第五时段(t5)与第六时段(t6)。
图6的第一输入信号和图7的第一输入信号波形相同，图6的第二输入信号和图7的第二输入信号的波形不同，区别在于：图6的第二输入信号在第二时段是低电平，图7的第二输入信号在第二时段是高电平。
在第二时段，根据图7可知第五晶体管导通，根据图6可知第五晶体管截止，但是，无论第五晶体管是导通还是截止，由于第一时钟信号是高电平，因此第四晶体管导通，所以第二电源信号总会提供给第三节点，使得第三节点的电位成为低电平。
因此，图7和图6中的第二输入信号虽然有不同，但是移位寄存器的所有节点(第一节点、第二节点、第三节点)在一个工作周期内的电位变化相同，第一输出信号、第二输出信号的波形也完全相同。
如图8所示，本公开实施例还提供了一种栅极驱动电路，包括N个级联的移位寄存器SR(i)；第k个移位寄存器SR(k)的第一输出信号端与第k+1个移位寄存器SR(k+1)的第一输入信号端连接；1≤k≤N-1，N>1；N个移位寄存器中至少一个移位寄存器SR(i)采用上述实施例中的移位寄存器；1≤i≤N。
如图9所示，在一些示例性的实施方式中，第k个移位寄存器SR(k)的第一输出信号端还与第k+1个移位寄存器SR(k+1)的第二输入信号端连接。这种情况下，移位寄存器的第一输入信号端和第二输入信号端输入的信号相同。
如图10所示，在一些示例性的实施方式中，所述栅极驱动电路还包括N个级联的其他移位寄存器R(i)，第k+1个移位寄存器SR(k+1)的第二输入信号端连接第k个其他移位寄存器R(k)的输出信号端GOUT；1≤k≤N-1，N>1；1≤i≤N；第k个其他移位寄存器R(k)的输出信号端输出的输出信号满足第k+1个移位寄存器SR(k+1)的第二输入信号的要求。这种情况下，移位寄存器的第一输入信号端和第二输入信号端输入的信号不同。
上述栅极驱动电路可以和显示面板的像素驱动电路连接，用于向像素驱动电路提供各种控制信号，比如：行扫描信号、复位信号等。
所述显示面板包括：有机发光二极管(Organic Light-Emitting Diode，简称：OLED)显示面板。
本公开实施例还提供了一种显示装置，包括上述栅极驱动电路。
所述显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。对于该显示装置的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本发明的限制。
虽然本申请所揭露的实施方式如上，但所述的内容仅为便于理解本申请而采用的实施方式，并非用以限定本发明。任何本发明所属领域内的技术人员，在不脱离本发明所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本发明的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (13)

  1. 一种移位寄存器，包括：第一控制模块、第一输出模块、第二输出模块、第二控制模块、第三控制模块、第四控制模块、第五控制模块、第六控制模块和储能模块；
    第一控制模块，与第一电源信号端、第一输入信号端和第二节点连接，设置为在第一输入信号端的第一输入信号的控制下将第一电源信号端的第一电源信号提供给第二节点；
    第一输出模块，与第二节点、第一时钟信号端和第一输出信号端连接，设置为在第二节点的电压控制下将第一时钟信号端的第一时钟信号提供给第一输出信号端；
    第二输出模块，与第一节点、第二电源信号端和第一输出信号端连接，设置为在第一节点的电压控制下将第二电源信号端的第二电源信号提供给第一输出信号端；
    第二控制模块，与第二电源信号端、第二输入信号端、第一时钟信号端和第三节点连接，设置为在第二输入信号端的第二输入信号控制下将第二电源信号端的第二电源信号提供给第三节点，在第一时钟信号端的第一时钟信号的控制下将第二电源信号端的第二电源信号提供给第三节点；
    第三控制模块，与第三节点、第二时钟信号端和第一节点连接，设置为在第三节点的电压控制下将第二时钟信号端的第二时钟信号提供给第一节点；
    第四控制模块，与第三节点、第二电源信号端和第二节点连接，设置为在第三节点的电压控制下将第二电源信号端的第二电源信号提供给第二节点；
    第五控制模块，与第一节点、第二电源信号端和第二节点连接，设置为在第一节点的电压控制下将第二电源信号端的第二电源信号提供给第二节点；
    第六控制模块，与第二节点、第二电源信号端和第一节点连接，设置为在第二节点的电压控制下将第二电源信号端的第二电源信号提供给第一节点；
    储能模块，包括第一电容，所述第一电容的两端分别与第三节点和第二时钟信号端连接。
  2. 根据权利要求1所述的移位寄存器，其中：
    所述第一输出模块包括第二晶体管，所述第二晶体管的控制极连接第二节点，所述第二晶体管的第一极连接第一时钟信号端，所述第二晶体管的第二极连接第一输出信号端；
    所述第二输出模块包括第三晶体管，所述第三晶体管的控制极连接第一节点，所述第三晶体管的第一极连接第二电源信号端，所述第三晶体管的第二极连接第一输出信号端。
  3. 根据权利要求1所述的移位寄存器，其中：
    所述第一控制模块包括第一晶体管，所述第一晶体管的控制极连接第一输入信号端，所述第一晶体管的第一极连接第一电源信号端，所述第一晶体管的第二极连接第二节点；
    所述第四控制模块包括第七晶体管，所述第七晶体管的控制极连接第三节点，所述第七晶体管的第一极连接第二电源信号端，所述第七晶体管的第二极连接第二节点；
    所述第五控制模块包括第八晶体管，所述第八晶体管的控制极连接第一节点，所述第八晶体管的第一极连接第二电源信号端，所述第八晶体管的第二极连接第二节点。
  4. 根据权利要求1所述的移位寄存器，其中：
    所述第三控制模块包括第六晶体管，所述第六晶体管的控制极连接第三节点，所述第六晶体管的第一极连接第二时钟信号端，所述第六晶体管的第二极连接第一节点；
    所述第六控制模块包括第九晶体管，所述第九晶体管的控制极连接第二节点，所述第九晶体管的第一极连接第二电源信号端，所述第九晶体管的第二极连接第一节点。
  5. 根据权利要求1所述的移位寄存器，其中：
    所述第二控制模块包括第四晶体管和第五晶体管，所述第四晶体管的控制极连接第一时钟信号端，所述第四晶体管的第一极连接第二电源信号端，所述第四晶体管的第二极连接第三节点，所述第五晶体管的控制极连接第二输入信号端，所述第五晶体管的第一极连接第二电源信号端，所述第五晶体 管的第二极连接第三节点。
  6. 根据权利要求2所述的移位寄存器，其中：
    所述第一输出模块还包括第二电容，所述第二电容的一端与第二晶体管的控制极连接，所述第二电容的另一端与第二晶体管的第二极连接；
    所述第二输出模块还包括第三电容，所述第三电容的一端与第三晶体管的控制极连接，所述第三电容的另一端与第三晶体管的第一极连接。
  7. 根据权利要求2所述的移位寄存器，其中：
    所述第一输出模块还包括第十晶体管，所述第十晶体管的控制极连接第一电源信号端，所述第十晶体管的第一极连接第二节点，所述第十晶体管的第二极连接第二晶体管的控制极。
  8. 根据权利要求1所述的移位寄存器，其中：
    所述第二节点还连接第二输出信号端，所述第二输出信号端输出第二输出信号。
  9. 根据权利要求2-8中任一项所述的移位寄存器，其中：
    所述移位寄存器包括的所有晶体管为氧化物薄膜晶体管。
  10. 根据权利要求2-8中任一项所述的移位寄存器，其中：
    当所述移位寄存器中所有的晶体管为N型晶体管时，所述移位寄存器的一个工作周期包括以下多个时段：第一时段、第二时段、第三时段、第四时段和多次交替出现的第五时段和第六时段；
    第一电源信号和第二电源信号为直流信号，第一电源信号为高电平信号，第二电源信号为低电平信号，第一输入信号和第二输入信号为脉冲信号，第一时钟信号和第二时钟信号为周期性脉冲信号；第一输入信号和第二输入信号在第一时段为高电平信号，在其他时段为低电平信号；第一时钟信号在第一时段、第三时段和第五时段为低电平信号，在第二时段、第四时段和第六时段为高电平信号；第二时钟信号在第一时段、第三时段和第五时段为高电平信号，在第二时段、第四时段和第六时段为低电平信号。
  11. 一种栅极驱动电路，包括：包括N个级联的移位寄存器SR(i)；第k 个移位寄存器SR(k)的第一输出信号端与第k+1个移位寄存器SR(k+1)的第一输入信号端连接；1≤k≤N-1，N>1；N个移位寄存器中至少一个移位寄存器SR(i)采用上述权利要求1-10中任一项所述的移位寄存器；1≤i≤N。
  12. 根据权利要求11所述的栅极驱动电路，其中：
    第k个移位寄存器SR(k)的第一输出信号端还与第k+1个移位寄存器SR(k+1)的第二输入信号端连接。
  13. 一种显示装置，包括：权利要求11或12所述的栅极驱动电路。
PCT/CN2023/089904 2022-04-24 2023-04-21 移位寄存器、栅极驱动电路及显示装置 WO2023207806A1 (zh)

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