WO2023206282A1 - 图像显示方法及系统、计算机可读存储介质及电子设备 - Google Patents

图像显示方法及系统、计算机可读存储介质及电子设备 Download PDF

Info

Publication number
WO2023206282A1
WO2023206282A1 PCT/CN2022/090044 CN2022090044W WO2023206282A1 WO 2023206282 A1 WO2023206282 A1 WO 2023206282A1 CN 2022090044 W CN2022090044 W CN 2022090044W WO 2023206282 A1 WO2023206282 A1 WO 2023206282A1
Authority
WO
WIPO (PCT)
Prior art keywords
image
displayed
pixel
viewpoint
viewpoints
Prior art date
Application number
PCT/CN2022/090044
Other languages
English (en)
French (fr)
Inventor
谷朝芸
Original Assignee
京东方科技集团股份有限公司
北京京东方显示技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 北京京东方显示技术有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202280001015.2A priority Critical patent/CN117581532A/zh
Priority to PCT/CN2022/090044 priority patent/WO2023206282A1/zh
Publication of WO2023206282A1 publication Critical patent/WO2023206282A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N13/00—Stereoscopic video systems; Multi-view video systems; Details thereof
    • H04N13/30—Image reproducers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N13/00—Stereoscopic video systems; Multi-view video systems; Details thereof
    • H04N13/30—Image reproducers
    • H04N13/366—Image reproducers using viewer tracking
    • H04N13/383—Image reproducers using viewer tracking for tracking with gaze detection, i.e. detecting the lines of sight of the viewer's eyes

Definitions

  • Embodiments of the present disclosure relate to the technical field of image display in light field 3D, and specifically, to an image display method, an image display system, a computer-readable storage medium, and an electronic device.
  • the purpose of the present disclosure is to provide an image display method, an image system, a computer-readable storage medium and an electronic device, thereby overcoming, at least to a certain extent, the problem of low image processing efficiency due to limitations and defects in related technologies.
  • an image display method including:
  • the second execution body controls the display panel to display the first image to be displayed.
  • the first execution body includes a processor disposed in a host
  • the second execution body includes a field programmable gate array disposed in a display device.
  • the first execution body includes an IC provided in the display device
  • the second execution body includes the IC or a field programmable gate array provided in the display device.
  • the original viewpoint image is processed to obtain a first image to be displayed, including:
  • the original viewpoint map in the pixel island is tiled to obtain a viewpoint tile map
  • the image display method further includes:
  • the image display method further includes:
  • converting the viewpoint tile from the original image architecture to the pixel island architecture includes:
  • the viewpoint tile is converted from the original horizontal RGB image architecture into a vertical RGB pixel island architecture.
  • calculating the second number of pixel rows of virtual pixel rows that need to be inserted in the pixel island architecture according to the first number of pixel rows in the line of sight area and the clock cycle includes: :
  • the second number of pixel rows of virtual pixel rows to be inserted in the pixel island architecture is zero;
  • the second pixel row number of the virtual pixel row is calculated according to the first pixel row number and the clock cycle.
  • determining whether the first number of pixel rows in the line of sight area and the clock cycle satisfy a second preset number relationship includes:
  • the sight area includes the human eye gaze area and/ or areas not viewed by the human eye;
  • the opening method of the GOA timing includes the first opening method or the second opening method. Opening method; when the sight area is a non-human eye gaze area, the opening method of the GOA timing includes the second opening method or the third opening method;
  • the first opening method is to open GOA row by row
  • the second opening mode is to open two rows of GOA at the same time
  • the third opening mode is to open four rows of GOA at the same time.
  • performing format conversion on the target image data to obtain a first image to be displayed includes:
  • the opening mode of the GOA timing of the line of sight area perform format conversion on the target image data to obtain the first image to be displayed;
  • the opening mode when the opening mode is the first opening mode, converting the target image data into a first to-be-displayed image having a first preset data format;
  • the opening mode is the second opening mode, convert the target image data into a first to-be-displayed image having a second preset data format;
  • the target image data is converted into a first to-be-displayed image having a third preset data format.
  • the image display method after performing format conversion on the target image data to obtain the first image to be displayed, the image display method further includes:
  • grayscale reverse processing is performed on the first to-be-displayed image to obtain a second to-be-displayed image.
  • grayscale reverse processing is performed on the first image to be displayed to obtain a second image to be displayed, including:
  • the idle channel When it is determined that the idle channel is included, insert a virtual pixel column into the first to-be-displayed image, and perform grayscale reverse processing on the first to-be-displayed image after inserting the virtual pixel column to obtain a second to-be-displayed image;
  • the insertion position of the virtual pixel column in the first image to be displayed corresponds to the position of the idle channel in the source driver chip;
  • grayscale reverse processing is performed on the first image to be displayed to obtain a second image to be displayed.
  • the image display method further includes:
  • the source driving chip required to drive the display panel is calculated. quantity;
  • the total number of channels of the display panel is calculated, and based on the total number of channels and the lateral resolution, the required number of channels in the source driver chip is calculated.
  • An insertion rule is set for the idle channel, so that the idle channel is inserted into the corresponding source driver chip according to the insertion rule.
  • the insertion rules include at least one of the following rules:
  • Each source driver chip inserted into an idle channel is placed in the first preset placement mode
  • the idle channel is placed in the source driver chip in a second preset placement manner
  • Each source driver chip inserted into an idle channel is placed in a corresponding position on the display panel in a third preset manner.
  • the image display method further includes:
  • an image display system including:
  • the first execution subject is used to obtain the original viewpoint map, process the original viewpoint map, and obtain the first image to be displayed; and send the first image to be displayed to the second execution subject;
  • the second execution subject is communicatively connected with the first execution subject and is used to control the display panel to display the first image to be displayed.
  • the first execution body includes a processor disposed in a host
  • the second execution body includes a field programmable gate array disposed in a display device.
  • the first execution body includes an IC provided in the display device
  • the second execution body includes the IC or a field programmable gate array provided in the display device.
  • the first execution subject may be further configured to: when it is determined that the number of viewpoints of the current viewpoint included in the same pixel island satisfies the preset condition, the original viewpoint in the pixel island The image is tiled to obtain a viewpoint tile; convert the viewpoint tile from the original image architecture to a pixel island architecture, and determine the sight area of the viewpoint tile; according to the first The number of pixel rows and the clock cycle are used to calculate the second number of pixel rows of virtual pixel rows that need to be inserted in the pixel island architecture; insert virtual pixel rows corresponding to the second number of pixel rows in the pixel island architecture, Obtain target image data, and perform format conversion on the target image data to obtain a first image to be displayed.
  • the first execution subject may be further configured to: calculate the number of viewpoints of the current viewpoint included in the same pixel island, and determine the difference between the number of viewpoints and the data included in the pixel island. Whether the number of time-division multiplexed paths satisfies the first preset quantity relationship; if the number of viewpoints and the number of paths satisfy the first preset quantity relationship, it is determined that the number of viewpoints of the current viewpoint satisfies the preset quantity relationship.
  • Condition If the number of viewpoints and the number of paths do not satisfy the first preset quantitative relationship, it is determined that the number of viewpoints of the current viewpoint does not satisfy the preset condition.
  • the first execution subject may be further configured to: if the number of viewpoints and the number of pathways do not satisfy the first preset quantitative relationship, quantity, calculate the number of virtual viewpoints that need to be added; add virtual viewpoints equal to the number of virtual viewpoints in the current viewpoint until the increased number of viewpoints and the number of pathways satisfy the first preset quantity relationship.
  • the first execution subject may be further configured to convert the viewpoint tile from an original horizontal RGB image architecture to a vertical RGB pixel island architecture.
  • the first execution subject may be further configured to: determine whether the first number of pixel rows in the line of sight area and the clock cycle satisfy a second preset number relationship; If the second preset quantity relationship is met, the second pixel row number of the virtual pixel rows to be inserted in the pixel island architecture is zero; if the second preset quantity relationship is not met, then according to the The first pixel row number and the clock cycle are used to calculate the second pixel row number of the virtual pixel row.
  • the first execution subject may be further configured to: determine the opening mode of the GOA timing of the line of sight area, and determine the opening mode of the GOA timing of the line of sight area according to the opening mode.
  • the first pixel row number and the clock cycle wherein the line of sight area includes the human eye gaze area and/or the non-human eye gaze area; determine whether the first pixel row number and the clock cycle satisfy the second preset number relationship; wherein, when the line of sight area is a human eye gaze area, the opening method of the GOA timing includes a first opening method or a second opening method; when the line of sight area is a non-human eye gaze area, the GOA timing sequence
  • the opening method includes the second opening method or the third opening method; wherein, the first opening method is GOA row-by-row opening, the second opening method is GOA two rows opening at the same time, and the third opening method is GOA four-row opening. Open together.
  • the first execution subject may also be configured to: perform format conversion on the target image data according to the opening mode of the GOA timing of the line of sight area to obtain the first An image to be displayed; wherein, when the opening mode is the first opening mode, the target image data is converted into a first image to be displayed with a first preset data format; when the opening mode is the second opening mode when the target image data is converted into a first to-be-displayed image with a second preset data format; when the opening mode is a third opening mode, the target image data is converted into a first to-be-displayed image having a third preset data format The format of the first image to be displayed.
  • the first execution subject may be further configured to: determine whether the first transistor type including the first thin film field effect transistor in the source driver chip in the display panel is the same as that in the display panel.
  • the first transistor type of the second thin film field effect transistor is consistent; if the first transistor type is inconsistent with the second transistor type, then perform grayscale reverse processing on the first to-be-displayed image to obtain a second to-be-displayed image .
  • the first execution subject may be further configured to: determine whether an idle channel is included in the source driver chip; when it is determined that the idle channel is included, in the first image to be displayed Insert a virtual pixel column into the first to-be-displayed image, and perform grayscale reverse processing on the first to-be-displayed image after inserting the virtual pixel column to obtain a second to-be-displayed image; wherein, the virtual pixel column is in the first to-be-displayed image.
  • the insertion position corresponds to the position of the idle channel in the source driver chip; when it is determined that the idle channel is not included, grayscale reverse processing is performed on the first image to be displayed to obtain the second image to be displayed.
  • the first execution subject may be further configured to: according to the number of pixel islands included in the display panel and the number of viewpoints of the current viewpoint included in each pixel island. As well as the lateral resolution of the display panel, calculate the number of source driver chips required to drive the display panel; calculate the total channels of the display panel based on the number of chip channels of the source driver chip and the number of source driver chips. number, and calculate the number of idle channels that need to be inserted in the source driver chip according to the total number of channels and the lateral resolution; set insertion rules for the idle channels so that all the idle channels are added according to the insertion rules. The idle channel is inserted into the corresponding source driver chip.
  • the insertion rules include at least one of the following rules:
  • Each source driver chip inserted into an idle channel is placed in the first preset placement mode
  • the idle channel is placed in the source driver chip in a second preset placement manner
  • Each source driver chip inserted into an idle channel is placed in a corresponding position on the display panel in a third preset manner.
  • the first execution subject may be further configured to: add an information line to the first to-be-displayed image or the second to-be-displayed image; wherein the information line is used to Characterizes the location of the HD area.
  • a computer-readable storage medium is provided, a computer program is stored thereon, and when the computer program is executed by a processor, the image display method described in any of the above exemplary embodiments is implemented.
  • an electronic device including:
  • the processor is configured to perform the image display method described in any example embodiment via executing the executable instructions.
  • FIG. 1 schematically illustrates a flowchart of an image display method according to an example embodiment of the present disclosure.
  • FIG. 2 schematically illustrates a block diagram of an image display system according to an example embodiment of the present disclosure.
  • FIG. 3 schematically shows an example diagram of an original viewpoint diagram according to an example embodiment of the present disclosure.
  • FIG. 4 schematically shows an example diagram of an original viewpoint map after adding a virtual viewpoint according to an exemplary embodiment of the present disclosure.
  • FIG. 5 schematically illustrates an example diagram of a vertical RGB pixel island architecture according to an example embodiment of the present disclosure.
  • FIG. 6 schematically shows an example diagram of a second pixel row number of virtual pixel rows inserted by a different GOA timing partition according to an example embodiment of the present disclosure.
  • FIG. 7 schematically illustrates an example diagram of a pixel island architecture after inserting Dummy row data (virtual pixel rows) according to an exemplary embodiment of the present disclosure.
  • FIG. 8 schematically illustrates an example diagram of a first to-be-displayed image having a first preset data format (RRRRGGGGBBBB) according to an example embodiment of the present disclosure.
  • FIG. 9 schematically shows a flowchart of a method for processing a first image to be displayed to obtain a second image to be displayed according to an example embodiment of the present disclosure.
  • FIG. 10 schematically illustrates an example diagram of placing a source driver chip inserted into an idle channel to one side of a display panel according to an example embodiment of the present disclosure.
  • FIG. 11 schematically illustrates an example diagram of placing a source driver chip inserted into an idle channel to the left and right sides of a display panel according to an example embodiment of the present disclosure.
  • FIG. 12 schematically illustrates a specific example diagram of assigning a floating channel to a virtual pixel column according to an exemplary embodiment of the present disclosure.
  • FIG. 13 schematically illustrates a flowchart of another image display method according to an example embodiment of the present disclosure.
  • FIG. 14 schematically shows a block diagram of an image display device according to an example embodiment of the present disclosure.
  • FIG. 15 schematically illustrates an electronic device for implementing the above image display method according to an example embodiment of the present disclosure.
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments may, however, be embodied in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concepts of the example embodiments. To those skilled in the art.
  • the described features, structures or characteristics may be combined in any suitable manner in one or more embodiments.
  • the resolutions of existing display panels are all standard resolutions, such as FHD (Full High Definition) display panels, 4K display panels, and 8K display panels; among them, before the FPGA controls the display panel to display the image, It is also necessary to perform GOA timing and Data mapping processing on the image to be displayed through FPGA.
  • FHD Full Definition
  • 4K display panels 4K display panels
  • 8K display panels 8K display panels
  • the above scheme has the following shortcomings: on the one hand, it does not involve how to process non-standard resolution image data; on the other hand, FPGA programming, especially debugging, takes too long. For the complex GOA timing and Data mapping of light field projects, It takes more time, which affects the product output time, that is, the image processing efficiency is low.
  • this example implementation first provides an image display method, which can be run on a host, a display device, a server, a server cluster, a cloud server, etc.; of course, those skilled in the art can also run it on other platforms according to needs
  • the method of the present disclosure is not particularly limited in this exemplary embodiment.
  • the image display method may include the following steps:
  • Step S110 Obtain the original viewpoint map through the first execution subject, and process the original viewpoint map to obtain the first image to be displayed;
  • the original viewpoint map is obtained, and when it is determined that the number of viewpoints of the current viewpoint included in the same pixel island meets the preset conditions, the original viewpoint map in the pixel island is tiled to obtain the viewpoint flattened tiling; secondly, convert the viewpoint tile from the original image architecture to the pixel island architecture, and determine the line of sight area of the viewpoint tile; then, according to the first number of pixel rows in the line of sight area and clock cycle, calculate the second number of pixel rows of virtual pixel rows that need to be inserted in the pixel island architecture; further, insert virtual pixel rows corresponding to the second number of pixel rows in the pixel island architecture, and obtain target image data, and performs format conversion on the target image data to obtain a first image to be displayed.
  • the number of virtual second pixel rows that need to be inserted in the pixel island architecture can be calculated based on the number of first pixel rows in the line of sight area and the clock cycle; finally, the number of virtual second pixel rows is inserted in the pixel island architecture.
  • the corresponding virtual pixel row is used to obtain the target image data, and the format conversion of the target image data is performed to obtain the first image to be displayed, and then the first image to be displayed can be displayed through the FPGA control display panel. After the area display is completed, you can directly enter the pixel row corresponding to the next line of sight area, thereby improving the smoothness of image display.
  • Step S120 Send the first image to be displayed to the second execution subject through the first execution subject;
  • Step S130 Use the second execution subject to control the display panel to display the first image to be displayed.
  • the processing task of the original viewpoint image and the display task of controlling the display of the first image to be displayed can be placed on different execution subjects, the first execution subject and the second execution subject can be reduced. task burden, thereby improving image processing efficiency.
  • FPGA Full name Field-Programmable Gate Array, that is, field programmable gate array
  • TCON Timing Control, logic control board
  • X-Zone can be used to indicate that in a smart viewing scenario, the display panel is divided into a human eye gaze area and a human eye non-gaze area; among them, the screen resolution or pixels of the human eye gaze area and the human eye non-gaze area The frame rate is different.
  • a pixel island architecture needs to be used for setup; in specific applications, the sub-pixel size and panel size determine the number of pixel islands that can be included in the display panel, resulting in the horizontal distortion of the display panel.
  • the resolutions are mostly non-standard resolutions; in order to solve the problem in the existing technology that images with non-standard resolutions cannot be processed, the present disclosure proposes an image display method that can perform corresponding processing in hardware and software, thereby solving the problem of non-standard resolutions. Standard resolution issue.
  • the exemplary embodiment of the present disclosure proposes The image display is implemented through the host, which can greatly save FPGA programming and debugging time and speed up product output; moreover, the image display method proposed in this disclosure can include a variety of timing layout rules: GOA line by line, GOA two Simultaneous opening of rows, simultaneous opening of four GOA rows, and X-Zone can meet a variety of application scenarios.
  • the display system may include a host 210 and a display 220 , where the host 210 and the display 220 may be connected for communication through a preset data interface.
  • a first execution subject may be provided in the host, and a first execution subject and/or a second execution subject may be provided in the display device; and, the first execution subject includes a processor provided in the host, and the second execution subject may be provided in the display device.
  • the execution subject includes a field programmable gate array provided in the display device; at the same time, the first execution subject may also include an IC provided in the display device, and the second execution subject includes the IC or a field programmable gate array provided in the display device. Programmable gate array. Further, when the first execution subject is an IC provided in the display device, the IC can simultaneously realize the task of image processing (processing the original viewpoint map to obtain the first image to be displayed) and the task of controlling the first image to be displayed; Image processing and image display can be implemented in the IC at the same time.
  • the image display system can execute the image in the following manner Processing and image display tasks:
  • the display 220 may include a display panel 221 and a field programmable gate array 222.
  • the host is connected to the field programmable gate array through a preset data interface; the field programmable gate array It is used to receive the first image to be displayed or the second image to be displayed sent by the host through the preset data interface, and to control the display panel to display the first image to be displayed or the second image to be displayed.
  • the preset data interface can be DisplayPort (DP, display interface), or of course it can also be other interfaces that can transmit videos or images. This example does not impose special restrictions on this.
  • the host 210 may include an image acquisition device 211 and a processor (such as a CPU and/or GPU) 212.
  • the image acquisition device may be used to capture the human eye image of the current user, and the processor may be used to capture the human eye image according to the captured image.
  • the eye image is used to determine the human eye gaze area and the non-human eye gaze area of the current user on the display panel.
  • the processor can also be used to perform the image processing tasks recorded in the exemplary embodiments of the present disclosure.
  • the viewpoint map tiling process needs to be performed. Specifically, it can be implemented in the following manner: when it is determined that the number of viewpoints of the current viewpoint included in the same pixel island meets the preset conditions, the original viewpoint map in the pixel island is tiled to obtain a viewpoint tile map.
  • the original viewpoint map is obtained, where the original viewpoint map is the picture corresponding to each current viewpoint (View).
  • the system does not perform any processing on the original viewpoint map; and each current viewpoint can correspond to An original viewpoint map, for example, the original viewpoint map can be shown in Figure 3(a); wherein, Figure 3 includes 11 original viewpoint maps, and the corresponding current viewpoints can be, for example, View 1, View 2, and View 3 ,..., View 11.
  • the specific judgment process of whether the preset conditions are met can be realized in the following way: first, calculate the number of viewpoints of the current viewpoint included in the same pixel island, and determine the number of viewpoints and the time-sharing multiplexing of the data included in the pixel island Whether the number of paths satisfies the first preset quantity relationship; secondly, if the number of viewpoints and the number of paths satisfy the first preset quantity relationship, it is determined that the number of viewpoints of the current viewpoint satisfies the preset condition; Further, if the number of viewpoints and the number of paths do not satisfy the first preset quantitative relationship, it is determined that the number of viewpoints of the current viewpoint does not satisfy the preset condition.
  • the number of viewpoints and the number of pathways do not satisfy the first preset quantity relationship, calculate the number of virtual viewpoints that need to be added based on the number of viewpoints and the number of pathways; and then in the current viewpoint Add virtual viewpoints equal to the number of virtual viewpoints until the increased number of viewpoints and the number of paths satisfy the first preset quantity relationship.
  • the number of current viewpoint Views contained in a pixel island is an integer multiple of the number of MUX (multiplexer, data time-division multiplexing) channels: If it is not an integer multiple, as shown in Figure 3, you need to add Dummy View (virtual viewpoint), so that the sum of the number of viewpoints of the current viewpoint and the number of viewpoints of the virtual viewpoint included in the pixel island is an integer multiple of the number of MUX channels; for example, the number of MUX channels included in a certain pixel island is 6, and the pixel The number of viewpoints of the current viewpoint included in the island is 11, then it is confirmed that a virtual viewpoint needs to be added to the pixel island; where, the original viewpoint map after adding the virtual viewpoint can be shown in Figure 3(b), for example; where, in Figure 4 includes 11 original viewpoint pictures, and the corresponding current viewpoints can be, for example, View 1, View 2, View 3, ..., View 11, and View 12.
  • MUX multiplexer, data time-division multiplexing
  • the number of MUX channels included in the pixel island can be set according to actual needs. This example does not impose special restrictions on this; at the same time, in the process of increasing the virtual viewpoint, the number of virtual channels that need to be added
  • the number of viewpoints can be calculated based on the difference between the number of viewpoints of the current viewpoint and an integer multiple of the number of paths in the MUX.
  • the pixel information included in the virtual viewpoint may be irrelevant or relevant to the information included in View 1, View 2, View 3,..., View 11.
  • the added virtual viewpoint is only used in the process of processing the original viewpoint map to obtain the first image to be displayed, the newly added virtual viewpoint is not displayed; therefore, no matter whether the pixel information in the virtual viewpoint is consistent with View 1, View 2, View 3,..., View 11 are related and will not affect the final display result, thus enabling accurate display of images.
  • the original viewpoint map in the pixel island can be tiled to obtain a viewpoint tile map.
  • the tiling can be performed sequentially according to the viewpoint coding of the current viewpoint and/or the virtual viewpoint corresponding to the original viewpoint map and/or the virtual viewpoint map, Tiling can also be done in other ways, and this example has no special restrictions on this.
  • image architecture conversion processing in the process of processing the original viewpoint map, secondly, image architecture conversion processing also needs to be performed. Specifically, this can be achieved in the following manner: converting the viewpoint tile from the original image architecture to a pixel island architecture, and determining the line of sight area of the viewpoint tile.
  • the virtual pixel rows that need to be inserted it is further necessary to calculate the virtual pixel rows that need to be inserted. Specifically, it can be implemented in the following manner: calculating the second number of pixel rows of virtual pixel rows that need to be inserted in the pixel island architecture according to the first number of pixel rows in the line of sight area and the clock cycle.
  • first it is determined whether the second preset quantity relationship is satisfied between the first pixel row number of the line of sight area and the clock cycle; secondly, if the second preset quantity relationship is satisfied, then The second number of pixel rows of the virtual pixel rows that need to be inserted in the pixel island architecture is zero; then, if the second preset quantity relationship is not satisfied, calculate according to the first number of pixel rows and the clock cycle. The second pixel row number of the virtual pixel row.
  • the process can be performed in the following manner: first, determine the number of rows of first pixels in the line of sight area.
  • the opening method of the GOA timing sequence and determine the first pixel row number and clock cycle of the line of sight area according to the opening method; wherein the line of sight area includes a human eye gaze area and/or a non-human eye gaze area; Secondly, determine whether the first pixel row number and the clock cycle satisfy a second preset quantity relationship; wherein, when the line of sight area is the human eye gaze area, the opening method of the GOA timing includes the first opening method or The second opening method; when the line of sight area is a non-human eye gaze area, the opening method of the GOA timing includes the second opening method or the third opening method; wherein, the first opening method is GOA line-by-line opening, The second opening method is to open two rows of GOA at the same time, and the third opening mode is
  • the display panel needs to be divided into a human eye gaze area and a human eye non-gaze area; and the screen resolution or pixel frame rate of the human eye gaze area and the human eye non-gaze area is Differently, that is, the human eye gaze area needs to have a higher screen resolution and pixel frame rate, and the non-human eye gaze area can have a lower screen resolution and pixel frame rate; therefore, the X-Zone design will display the panel Panel Divide it into several partitions, and determine whether the number of CLK opens in each partition is an integer multiple of the CLK cycle (clock cycle): If it is not an integer multiple, in order to facilitate CLK connection between partitions, Dummy row data (virtual pixel row) needs to be inserted to make it If it is an integer multiple, the virtual pixel rows that need to be inserted are zero, that is, there is no need to insert virtual pixel rows.
  • the number of times CLK is turned on in this partition is consistent with the number of first pixel rows in this partition. That is, when CLK is turned on once, it controls one row of pixels for display; therefore, in specific During the application process, it can also be implemented by judging whether the number of CLK opens of the partition is an integral multiple of the CLK period.
  • the display panel can be
  • the entire screen has 1620 lines in the V direction, which can be divided into 6 partitions (the sum of the human eye's gaze area and the human eye's non-glance area is 6, among which the proportion of the human eye's gaze area and the human eye's non-glance area is , which can be set according to actual needs during the application process. This example does not impose special restrictions on this).
  • Each partition has 270 rows.
  • the specific calculation method for the number of second pixel rows of virtual pixel rows that need to be inserted in each interval is as follows. for example:
  • the CLK period is 12, and each partition CLK is opened 135 times. 135 cannot be divided evenly by 24.
  • the area can be included in the current clock cycle. All pixel rows are turned on to avoid failure due to too many second pixel rows that cannot be fully turned on during the clock cycle in this area or because there are too few second pixel rows that need to occupy the second pixel rows in the next area.
  • the problem of smooth display is realized in the process of displaying the first image to be displayed through the FPGA control display panel. When the display of the previous line of sight area is completed, the pixel row corresponding to the next line of sight area can be directly entered, thereby improving The smoothness of image display.
  • the determination of the human eye gaze area and/or the human eye non-glance area can be achieved in the following manner: capturing the human eye image of the current user through an image acquisition device, and based on the captured current human eye image.
  • the user's human eye image determines the position and azimuth angle of the current user's eyes relative to the display panel. Based on the position and azimuth angle, the user's human eye gaze area on the display panel is determined, and the display panel excludes the human eye gaze area.
  • the area is regarded as the non-human eye gaze area.
  • image data format conversion in the process of processing the original viewpoint map, finally, image data format conversion also needs to be performed. Specifically, it can be implemented in the following manner: inserting virtual pixel rows corresponding to the second pixel row number in the pixel island architecture to obtain target image data, and performing format conversion on the target image data to obtain the first to-be-received image data. Display image.
  • first, virtual pixel rows corresponding to pixel cursive script are inserted into the pixel island architecture, and then the target image data can be obtained; the obtained target image data can be specifically shown in FIG. 7 .
  • second, after obtaining the target image data it is also necessary to perform format conversion on the target data to obtain the first image to be displayed; wherein, the data format conversion can be achieved in the following ways: according to the GOA timing opening method of the line of sight area, Perform format conversion on the target image data to obtain a first to-be-displayed image; wherein, when the opening mode is the first opening mode, the target image data is converted into a first to-be-displayed image having a first preset data format.
  • the gate opening sequence is row 1 (R) ⁇ row 4 (R) ⁇ row 7 (R) ⁇ row 10 (R) ⁇ row 2 (G) ⁇ row 5 (G) ⁇ Row 8 (G) ⁇ Row 11 (G) ⁇ Row 3 (B) ⁇ Row 6 (B) ⁇ Row 9 (B) ⁇ Row 12 (B)..., so GOA
  • the data transmission during line-by-line start should be converted to 4R4G4B (RRRRGGGGBBBB), that is, the first to-be-displayed image with the first preset data format can be, for example, 4R4G4B, as shown in Figure 8 for details; secondly, because the two lines of Gate are at the same time Opening only gives one group of the same data.
  • the data when considering whether to use 2R2G2B mode for output in the high-definition area or low-definition area, the data can be output according to the display panel It is determined by the charging speed of the corresponding area; if the charging speed is fast, the 2R2G2B mode output can be selected in the low-definition area; if the charging speed is slow, the 2R2G2B mode output can be selected in the high-definition area; this example does not impose special restrictions on this.
  • FIG. 9 schematically shows a flowchart of a method for processing a first image to be displayed to obtain a second image to be displayed according to an example embodiment of the present disclosure. Specifically, as shown in Figure 9, the following steps may be included:
  • Step S910 determine whether the first transistor type including the first thin film field effect transistor in the source driver chip in the display panel is consistent with the first transistor type of the second thin film field effect transistor in the display panel.
  • Step S920 If the first transistor type and the second transistor type are inconsistent, perform grayscale reverse processing on the first to-be-displayed image to obtain a second to-be-displayed image.
  • the first to-be-displayed image is subjected to grayscale reverse processing to obtain the second to-be-displayed image, which can be achieved in the following manner: first, determine whether the source driver chip includes an idle channel; secondly, after determining that the source driver chip includes the When the channel is idle, insert a virtual pixel column into the first image to be displayed, and perform grayscale reverse processing on the first image to be displayed after inserting the virtual pixel column to obtain a second image to be displayed; wherein, the virtual The insertion position of the pixel column in the first image to be displayed corresponds to the position of the idle channel in the source driver chip; further, when it is determined that the idle channel is not included, the first image to be displayed is The displayed image undergoes grayscale reverse processing to obtain a second image to be displayed.
  • the insertion rules include at least one of the following rules: each source driver chip inserted into an idle channel is placed in a first preset placement manner; the idle channel is placed in a second preset placement manner. Each source driver chip inserted into the idle channel is placed in the corresponding position of the display panel in a third preset manner.
  • Step S910 to S920 determine whether the first transistor type of the first thin film field effect transistor TFT included in the Source Driver IC (source driver chip) is consistent with the second transistor type of the second thin film field effect transistor TFT used in the display panel Panel; if They are not of the same type (inconsistent).
  • the Source Driver IC is suitable for NMOS, and the gray scale is proportional to the voltage, while the Panel is PMOS TFT, and the gray scale is inversely proportional to the voltage.
  • the gray scale in the picture needs to be reversely processed; among them, the gray scale is
  • the grayscale value in the image can be displayed by the grayscale value obtained from the L255 grayscale - the grayscale that needs to be displayed.
  • the specific calculation formula can be shown as the following formula (1):
  • the insertion rules of the virtual pixel column can be as follows: First, determine whether the Source IC (source driver chip) has a floating channel (idle channel): If so, you need to give the floating channel to Dummy data, so it needs to be in the picture Insert the Dummy column data (virtual pixel column), where the insertion position of the Dummy column data corresponds to the floating channel; if there is no idle channel, grayscale processing can be performed directly.
  • the specific judgment process of transistor type and the specific judgment process of idle channel are not strictly limited in the actual implementation process. The corresponding processing flow can be set according to actual needs. This example No special restrictions are imposed.
  • the pixel island architecture is designed to meet both the pixel size and the display panel Panel size, and the resolution is mostly non-standard.
  • the image quality is poor; for specific placement diagrams, please refer to Figure 10 and Figure 11; and, when the source driver chip COF is set with some idle channels floating channels, the number of channels included in the source driver chip will be the same as Other source driver chips that do not have idle channels have different channel numbers, and it is difficult to synchronize with other COFs during data processing; therefore, when designing the FPGA or TCON included in the display device, it is necessary to design according to the standard resolution and Just give the floating channel to the virtual pixel column; for the specific implementation of giving the floating channel to the virtual pixel column, please refer to Figure 12. Through this method, the problem that non-standard resolution cannot be solved in the existing technology can be solved.
  • the specific image display process of the original viewpoint map in the host computer has been completed. Further, in order to display the processed image on the display panel, the following steps need to be performed: first, add an information line to the first to-be-displayed image or the second to-be-displayed image; wherein, the information line is to characterize the position of the high-definition area; then, based on the preset data interface, send the first to-be-displayed image or the second to-be-displayed image to the field-programmable gate array in the display, so that the field-programmable gate array drives The display panel in the display displays the first image to be displayed or the second image to be displayed.
  • X-Zone timing that is, whether it is an intelligent viewing scene. If it is X-Zone timing, because the GOA timing of the high-definition area and low-definition area is different, the high-definition area needs to be The position is passed to the FPGA through the picture information line in order to call the appropriate timing. Therefore, a line can be added to the first line of the first image to be displayed or the second image to be displayed as an information line to facilitate the FPGA in the process of driving the display panel for display. , the display panel is controlled to perform high-definition display (displayed in RRRRGGGGBBBB, or RRGGBB) according to the information line; if the entire screen timing is the same, there is no need to add an information line.
  • the reason why the first image to be displayed or the second image to be displayed is mentioned here is because there is a situation: when there is no floating channel and the Source Driver IC (source driver chip)
  • the first to-be-displayed image can be directly sent to the FPGA, or Add an information line to the first image to be displayed and send it to the FPGA; of course, when there is a floating channel, or the first transistor type of the first thin film field effect transistor TFT included in the Source Driver IC (source driver chip), whether it is consistent with the display
  • a virtual pixel column can be added to the first image to be displayed and/or grayscale reverse processing can be performed to obtain a second image to be displayed, and then the second image to be displayed can be obtained.
  • the second image to be displayed is sent to the FPGA or an information line is added to the second image to be displayed and then sent to the FPGA.
  • the first image to be displayed or the second image to be displayed to the FPGA only the first image to be displayed or the second image to be displayed is sent each time, and the first image to be displayed and the second image to be displayed are not sent at the same time. Display image.
  • the FPGA controlling the display panel to display the first image to be displayed or the second image to be displayed, it can be implemented in the following manner: determining when each pixel row in the display panel is in the human eye gaze area is sequentially scanned.
  • the first scanning sequence of each first pixel located in the human eye gaze area determines the first opening sequence of the first switch for controlling each first pixel according to the pixel island to which each first pixel belongs and the first scanning sequence.
  • An opening sequence sequentially turns on the first switch in each pixel island; and/or determines to sequentially target each pixel group in the non-human eye gaze area in the display panel, and scan all pixel rows in the pixel group at the same time.
  • the second scanning sequence of the second pixels in the attention area according to the pixel island to which each second pixel belongs and the second scanning sequence, determine the second opening sequence of the second switch for controlling each second pixel, in sequence according to the second opening sequence Turn on the second switch in each pixel island.
  • the image display method described in the exemplary embodiment of the present disclosure will be further explained and described with reference to FIG. 13 .
  • the image display method may include the following steps:
  • Step S1301 obtain the original viewpoint map
  • Step S1302 determine whether the number of Views is an integer multiple of the MUX channels: that is, determine whether the number of viewpoints of the current viewpoint included in the same pixel island is an integer multiple of the number of MUX channels; if so, jump to step S1303, if not, Jump to step S1304;
  • Step S1303 add Dummy View: that is, calculate the number of virtual viewpoints that need to be added based on the number of viewpoints and the number of pathways; add virtual viewpoints equal to the number of virtual viewpoints in the current viewpoint until the increased number of viewpoints is equal to the number of pathways The quantity satisfies the first preset quantity relationship;
  • Step S1304 pixel island conversion: that is, tile the original viewpoint map to obtain a viewpoint tile map, and convert the viewpoint tile map from horizontal RGB to column RGB;
  • Step S1305 determine whether the number of rows in each partition is an integer multiple of the CLK period: that is, determine whether the number of first pixel rows in the partition is an integer multiple of the CLK period; if not, jump to step S1306; if so , then jump to step S1307;
  • Step S1307 perform format conversion on the target image data to obtain the first image to be displayed: that is, when GOA is opened line by line, the data transmission should be converted to 4R4G4B (RRRRGGGGBBBB); when two lines of GOA are opened at the same time, it needs to be output in the RRGGBB or 2R2G2B mode. , which is one-half of the data amount of line-by-line opening; when four lines of GOA are opened at the same time, it needs to be output in RGB mode, which is one-quarter of the data amount of line-by-line opening;
  • Step S1308 determine whether the SD Channel has floating: that is, determine whether the Source IC (source driver chip) has a floating channel (idle channel), if so, jump to step S1309; if not, jump to step S1310;
  • Step S1309 give the floating channel to the Dummy data: that is, insert the Dummy column data (virtual pixel column) into the first picture to be displayed, and give the floating channel to the Dummy column data, and the insertion position of the Dummy column data corresponds to the floating channel ;
  • Step S1310 determine whether the SD and panel TFT are of the same type: that is, determine whether the first transistor type of the first thin film field effect transistor TFT included in the Source Driver IC (source driver chip) is the same as the second thin film used in the display panel Panel. Whether the second transistor type of the field effect transistor TFT is consistent; if not, jump to step S1311; if not, jump to step S1312;
  • Step S1311, gray scale inversion that is, perform gray scale inversion on the first to-be-displayed image with virtual column data added to obtain the second to-be-processed image;
  • Step S1312 determine whether it is X-Zone timing; if yes, jump to step S1313; if not, jump to step S1313;
  • Step S1313 Add information lines to the second image to be processed
  • Step S1314 Send the second image to be processed to the FPGA.
  • the image display method recorded in the exemplary embodiments of the present disclosure adopts a software and hardware design that can solve the problem of non-standard resolution of the pixel island architecture; on the other hand, it designs a pixel island Architect a plan to process data through mapping; on the other hand, different mapping rules for different GOA timings are designed.
  • the different layout rules for different GOA timings can be shown in Table 1 below:
  • an image display device configured on a host.
  • the image display device may include an original viewpoint image processing module 1410 , a first image to be displayed sending module 1420 , and a first image to be displayed display module 1430 . in:
  • the original viewpoint map processing module 1410 can be used to obtain the original viewpoint map through the first execution subject, and process the original viewpoint map to obtain the first image to be displayed;
  • the first to-be-displayed image sending module 1420 may be used to send the first to-be-displayed image to the second execution subject through the first execution subject;
  • the first to-be-displayed image display module 1430 may be used to display the first to-be-displayed image through the second execution body controlling the display panel.
  • the first execution body includes a processor provided in the host, and the second execution body includes a field programmable gate array provided in the display device.
  • the first execution body includes an IC provided in the display device
  • the second execution body includes the IC or a field programmable gate array provided in the display device.
  • the original viewpoint map is processed to obtain a first image to be displayed, including:
  • the original viewpoint map in the pixel island is tiled to obtain a viewpoint tile map
  • the image display device further includes:
  • the first judgment module can be used to calculate the number of viewpoints of the current viewpoint included in the same pixel island, and determine whether the number of viewpoints and the number of time-division multiplexed channels of data included in the pixel island satisfy the first preset quantity relationship. ;
  • the first determination module may be configured to determine that the number of viewpoints of the current viewpoint satisfies the preset condition if the number of viewpoints and the number of pathways satisfy the first preset quantitative relationship;
  • the second determination module may be configured to determine that the number of viewpoints of the current viewpoint does not satisfy the preset condition if the number of viewpoints and the number of pathways do not satisfy the first preset quantitative relationship.
  • the image display device further includes:
  • the virtual viewpoint quantity calculation module may be used to calculate the number of virtual viewpoints that need to be added based on the number of viewpoints and the number of pathways if the number of viewpoints and the number of pathways do not satisfy the first preset quantity relationship;
  • the virtual viewpoint adding module may be used to add virtual viewpoints equal to the number of virtual viewpoints in the current viewpoint until the increased number of viewpoints and the number of pathways satisfy the first preset quantity relationship.
  • converting the viewpoint tile from the original image architecture to the pixel island architecture includes:
  • the viewpoint tile is converted from the original horizontal RGB image architecture into a vertical RGB pixel island architecture.
  • the second number of pixel rows of virtual pixel rows that need to be inserted in the pixel island architecture is calculated according to the first number of pixel rows in the line of sight area and the clock cycle, include:
  • the second number of pixel rows of virtual pixel rows to be inserted in the pixel island architecture is zero;
  • the second pixel row number of the virtual pixel row is calculated according to the first pixel row number and the clock cycle.
  • determining whether the first number of pixel rows in the line of sight area and the clock cycle satisfy a second preset number relationship includes:
  • the sight area includes the human eye gaze area and/ or areas not viewed by the human eye;
  • the opening method of the GOA timing includes the first opening method or the second opening method. Opening method; when the line of sight area is a non-human eye gaze area, the opening method of the GOA timing sequence includes the second opening method or the third opening method.
  • the first opening method is to open GOA row by row
  • the second opening method is to open two rows of GOA at the same time
  • the third opening method is to open four rows of GOA at the same time.
  • performing format conversion on the target image data to obtain a first image to be displayed includes:
  • the opening mode of the GOA timing of the line of sight area perform format conversion on the target image data to obtain the first image to be displayed;
  • the opening mode when the opening mode is the first opening mode, converting the target image data into a first to-be-displayed image having a first preset data format;
  • the opening mode is the second opening mode, convert the target image data into a first to-be-displayed image having a second preset data format;
  • the target image data is converted into a first to-be-displayed image having a third preset data format.
  • the image display device further includes:
  • the second determination module may be used to determine whether the first transistor type including the first thin film field effect transistor in the source driver chip in the display panel is consistent with the first transistor type of the second thin film field effect transistor in the display panel;
  • the grayscale reverse processing module may be used to perform grayscale reverse processing on the first to-be-displayed image to obtain a second to-be-displayed image if the first transistor type and the second transistor type are inconsistent.
  • grayscale reverse processing is performed on the first image to be displayed to obtain a second image to be displayed, including:
  • the idle channel When it is determined that the idle channel is included, insert a virtual pixel column into the first to-be-displayed image, and perform grayscale reverse processing on the first to-be-displayed image after inserting the virtual pixel column to obtain a second to-be-displayed image;
  • the insertion position of the virtual pixel column in the first image to be displayed corresponds to the position of the idle channel in the source driver chip;
  • grayscale reverse processing is performed on the first image to be displayed to obtain a second image to be displayed.
  • the insertion rules include at least one of the following rules:
  • Each source driver chip inserted into an idle channel is placed in the first preset placement mode
  • the idle channel is placed in the source driver chip in a second preset placement manner
  • Each source driver chip inserted into an idle channel is placed in a corresponding position on the display panel in a third preset manner.
  • the image display device further includes:
  • the information line adding module can be used to add an information line in the first to-be-displayed image or the second to-be-displayed image; wherein the information line is used to characterize the position of the high-definition area.
  • an electronic device capable of implementing the above method is also provided.
  • FIG. 15 An electronic device 1500 according to this embodiment of the present disclosure is described below with reference to FIG. 15 .
  • the electronic device 1500 shown in FIG. 15 is only an example and should not bring any limitations to the functions and usage scope of the embodiments of the present disclosure.
  • electronic device 1500 is embodied in the form of a general computing device.
  • the components of the electronic device 1500 may include, but are not limited to: the above-mentioned at least one processing unit 1510, the above-mentioned at least one storage unit 1520, a bus 1530 connecting different system components (including the storage unit 1520 and the processing unit 1510), and the display unit 1540.
  • the storage unit stores program code, and the program code can be executed by the processing unit 1510, so that the processing unit 1510 performs various exemplary methods according to the present disclosure described in the "Example Method" section of this specification.
  • the processing unit 1510 can perform step S110 shown in Figure 1: obtain the original viewpoint map through the first execution subject, and process the original viewpoint map to obtain the first image to be displayed; step S120: obtain the first image to be displayed through the first execution subject. The first execution subject sends the first image to be displayed to the second execution subject; step S130: control the display panel to display the first image to be displayed through the second execution subject.
  • the storage unit 1520 may include a readable medium in the form of a volatile storage unit, such as a random access storage unit (RAM) 15201 and/or a cache storage unit 15202, and may further include a read-only storage unit (ROM) 15203.
  • RAM random access storage unit
  • ROM read-only storage unit
  • Storage unit 1520 may also include a program/utility 15204 having a set of (at least one) program modules 15205 including, but not limited to: an operating system, one or more application programs, other program modules, and program data, Each of these examples, or some combination, may include the implementation of a network environment.
  • program/utility 15204 having a set of (at least one) program modules 15205 including, but not limited to: an operating system, one or more application programs, other program modules, and program data, Each of these examples, or some combination, may include the implementation of a network environment.
  • Bus 1530 may be a local area representing one or more of several types of bus structures, including a memory unit bus or memory unit controller, a peripheral bus, a graphics acceleration port, a processing unit, or using any of a variety of bus structures. bus.
  • Electronic device 1500 may also communicate with one or more external devices 1600 (e.g., keyboard, pointing device, Bluetooth device, etc.), may also communicate with one or more devices that enable a user to interact with electronic device 1500, and/or with Any device that enables the electronic device 1500 to communicate with one or more other computing devices (eg, router, modem, etc.). This communication may occur through input/output (I/O) interface 1550.
  • the electronic device 1500 may also communicate with one or more networks (eg, a local area network (LAN), a wide area network (WAN), and/or a public network, such as the Internet) through the network adapter 1560. As shown, network adapter 1560 communicates with other modules of electronic device 1500 via bus 1530.
  • network adapter 1560 communicates with other modules of electronic device 1500 via bus 1530.
  • the example embodiments described here can be implemented by software, or can be implemented by software combined with necessary hardware. Therefore, the technical solution according to the embodiment of the present disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (which can be a CD-ROM, U disk, mobile hard disk, etc.) or on the network , including several instructions to cause a computing device (which may be a personal computer, a server, a terminal device, a network device, etc.) to execute a method according to an embodiment of the present disclosure.
  • a computing device which may be a personal computer, a server, a terminal device, a network device, etc.
  • a computer-readable storage medium is also provided, on which a program product capable of implementing the method described above in this specification is stored.
  • various aspects of the present disclosure can also be implemented in the form of a program product, which includes program code.
  • the program product is run on a terminal device, the program code is used to cause the The terminal device performs the steps according to various exemplary embodiments of the present disclosure described in the above "Example Method" section of this specification.
  • the program product for implementing the above method according to an embodiment of the present disclosure may adopt a portable compact disk read-only memory (CD-ROM) and include program code, and may be run on a terminal device, such as a personal computer.
  • a readable storage medium may be any tangible medium containing or storing a program that may be used by or in conjunction with an instruction execution system, apparatus, or device.
  • the program product may take the form of any combination of one or more readable media.
  • the readable medium may be a readable signal medium or a readable storage medium.
  • the readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination thereof. More specific examples (non-exhaustive list) of readable storage media include: electrical connection with one or more conductors, portable disk, hard disk, random access memory (RAM), read only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination of the above.
  • a computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave carrying readable program code therein. Such propagated data signals may take many forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above.
  • a readable signal medium may also be any readable medium other than a readable storage medium that can send, propagate, or transport the program for use by or in connection with an instruction execution system, apparatus, or device.
  • Program code embodied on a readable medium may be transmitted using any suitable medium, including but not limited to wireless, wireline, optical cable, RF, etc., or any suitable combination of the foregoing.
  • Program code for performing operations of the present disclosure may be written in any combination of one or more programming languages, including object-oriented programming languages such as Java, C++, etc., as well as conventional procedural Programming language—such as "C" or a similar programming language.
  • the program code may execute entirely on the user's computing device, partly on the user's device, as a stand-alone software package, partly on the user's computing device and partly on a remote computing device, or entirely on the remote computing device or server execute on.
  • the remote computing device may be connected to the user computing device through any kind of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computing device, such as provided by an Internet service. (business comes via Internet connection).
  • LAN local area network
  • WAN wide area network

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Testing, Inspecting, Measuring Of Stereoscopic Televisions And Televisions (AREA)

Abstract

本公开是关于一种图像显示方法及系统、计算机可读存储介质、电子设备，涉及光场3D中的图像显示技术领域，该方法包括：通过第一执行主体获取原始视点图，并对所述原始视点图进行处理，得到第一待显示图像；通过所述第一执行主体将所述第一待显示图像发送至第二执行主体；通过所述第二执行主体控制显示面板对所述第一待显示图像进行显示。本公开提高了图像处理效率。 (图1)

Description

图像显示方法及系统、计算机可读存储介质及电子设备 技术领域
本公开实施例涉及光场3D中的图像显示技术领域，具体而言，涉及一种图像显示方法、图像显示系统、计算机可读存储介质以及电子设备。
背景技术
现有的图像显示方法中，对数据的处理全都依赖于同一执行主体进行实现；但是，当图像显示数据较大时，会使得该执行主体的负担较重，进而使得图像处理的效率较低。
发明内容
本公开的目的在于提供一种图像显示方法、图像系统、计算机可读存储介质以及电子设备，进而至少在一定程度上克服由于相关技术的限制和缺陷而导致的图像处理效率较低的问题。
根据本公开示例实施例的一个方面，提供一种图像显示方法，包括：
通过第一执行主体获取原始视点图，并对所述原始视点图进行处理，得到第一待显示图像；
通过所述第一执行主体将所述第一待显示图像发送至第二执行主体；
通过所述第二执行主体控制显示面板对所述第一待显示图像进行显示。
在本公开的一种示例实施例中，所述第一执行主体包括设置在主机中的处理器，所述第二执行主体包括设置在显示装置中的现场可编程门阵列。
在本公开的一种示例实施例中，所述第一执行主体包括设置在显示装置中的IC，所述第二执行主体包括所述IC或者设置在显示装置中的现场可编程门阵列。
在本公开的一种示例实施例中，对所述原始视点图进行处理，得到第一待显示图像，包括：
在确定同一像素岛中包括的当前视点的视点数量满足预设条件时，对该像素岛中的原始视点图进行平铺，得到视点平铺图；
将所述视点平铺图由原始图像架构转换为像素岛架构，并确定所述视点平铺图的视线区域；
根据所述视线区域所具有的第一像素行数以及时钟周期，计算所述像素岛架构中所需插入的虚拟像素行的第二像素行数；
在所述像素岛架构中插入与所述第二像素行数对应的虚拟像素行，得到目标图像数据，并对所述目标图像数据进行格式转换得到第一待显示图像。
在本公开的一种示例实施例中，所述图像显示方法还包括：
计算同一像素岛内包括的当前视点的视点数量，并判断所述视点数量与该像素岛内包括的数据分时复用的通路数量是否满足第一预设数量关系；
若所述视点数量与所述通路数量满足所述第一预设数量关系，则确定所述当前视点的视点数量满足所述预设条件；
若所述视点数量与所述通路数量不满足所述第一预设数量关系，则确定所述当前视点的视点数量不满足所述预设条件。
在本公开的一种示例实施例中，所述图像显示方法还包括：
若所述视点数量与所述通路数量不满足所述第一预设数量关系，则根据视点数量以及通路数量，计算所需增加的虚拟视点的数量；
在所述当前视点中增加与虚拟视点的数量相等的虚拟视点，直至增加后的视点数量与所述通路数量满足所述第一预设数量关系。
在本公开的一种示例实施例中，将所述视点平铺图由原始图像架构转换为像素岛架构，包括：
将所述视点平铺图由原始的横向RGB图像架构转换为纵向RGB的像素岛架构。
在本公开的一种示例实施例中，根据所述视线区域所具有的第一像素行数以及时钟周期，计算所述像素岛架构中所需插入的虚拟像素行的第二像素行数，包括：
判断所述视线区域所具有的第一像素行数以及时钟周期之间是否满足第二预设数量关系；
若满足所述第二预设数量关系，则所述像素岛架构中所需插入的虚拟像素行的第二像素行数为零；
若不满足所述第二预设数量关系，则根据所述第一像素行数以及时钟周期，计算所述虚拟像素行的第二像素行数。
在本公开的一种示例实施例中，判断所述视线区域所具有的第一像素行数以及时钟周期之间是否满足第二预设数量关系，包括：
确定所述视线区域所具有的GOA时序的开启方式，并根据所述开启方式确定所述视线区域所具有的第一像素行数以及时钟周期；其中，所述视线区域包括人眼注视区域和/或非人眼注视区域；
判断所述第一像素行数以及时钟周期之间是否满足第二预设数量关系；其中，当所述视线区域为人眼注视区域时，所述GOA时序的开启方式包括第一开启方式或第二开启方式；当所述视线区域为非人眼注视区域时，所述GOA时序的开启方式包括第二开启方式或第三开启方式；
其中，所述第一开启方式为GOA逐行开，所述第二开启方式为GOA两行同开，所述第三开启方式为GOA四行同开。
在本公开的一种示例实施例中，对所述目标图像数据进行格式转换得到第一待显示图 像，包括：
根据所述视线区域所具有的GOA时序的开启方式，对所述目标图像数据进行格式转换，得到第一待显示图像；
其中，当所述开启方式为第一开启方式时，将所述目标图像数据转换为具有第一预设数据格式的第一待显示图像；
当所述开启方式为第二开启方式时，将所述目标图像数据转换为具有第二预设数据格式的第一待显示图像；
当所述开启方式为第三开启方式时，将所述目标图像数据转换为具有第三预设数据格式的第一待显示图像。
在本公开的一种示例实施例中，在对所述目标图像数据进行格式转换得到第一待显示图像之后，所述图像显示方法还包括：
判断显示面板中的源驱动芯片中包括第一薄膜场效应晶体管的第一晶体管类型，是否与显示面板中的第二薄膜场效应晶体管的第一晶体管类型一致；
若所述第一晶体管类型与第二晶体管类型不一致，则对所述第一待显示图像进行灰阶反向处理，得到第二待显示图像。
在本公开的一种示例实施例中，对所述第一待显示图像进行灰阶反向处理，得到第二待显示图像，包括：
判断源驱动芯片中是否包括闲置通道；
在确定包括所述闲置通道时，在所述第一待显示图像中插入虚拟像素列，并对插入虚拟像素列以后的第一待显示图像进行灰阶反向处理，得到第二待显示图像；其中，所述虚拟像素列在所述第一待显示图像中的插入位置，与所述闲置通道在所述源驱动芯片中的位置对应；
在确定不包括所述闲置通道时，对所述第一待显示图像进行灰阶反向处理，得到第二待显示图像。
在本公开的一种示例实施例中，所述图像显示方法还包括：
根据所述显示面板的所包括的像素岛的数量、每一个像素岛中所包括的当前视点的视点数量以及所述显示面板的横向分辨率，计算驱动所述显示面板所需要的源驱动芯片的数量；
根据所述源驱动芯片的芯片通道数量以及源驱动芯片的数量，计算所述显示面板的总通道数，并根据所述总通道数以及所述横向分辨率，计算需要在所述源驱动芯片中插入的闲置通道的数量；
为所述闲置通道设置插入规则，以使得根据所述插入规则将所述闲置通道插入至对应的源驱动芯片中。
在本公开的一种示例实施例中，所述插入规则包括以下规则中的至少一项：
每一颗被插入闲置通道的源驱动芯片，是以第一预设放置方式进行放置的；
所述闲置通道是以第二预设放置方式放置在所述源驱动芯片中的；
每一颗被插入闲置通道的源驱动芯片，是以第三预设方式放置在显示面板的对应位置中的。
在本公开的一种示例实施例中，所述图像显示方法还包括：
在所述第一待显示图像或第二待显示图像中添加信息行；其中，所述信息行用于表征高清区位置。
根据本公开示例实施例的一个方面，提供一种图像显示系统，包括：
第一执行主体，用于获取原始视点图，并对所述原始视点图进行处理，得到第一待显示图像；以及将所述第一待显示图像发送至第二执行主体；
第二执行主体，与所述第一执行主体通信连接，用于控制显示面板对所述第一待显示图像进行显示。
在本公开的一种示例实施例中，所述第一执行主体包括设置在主机中的处理器，所述第二执行主体包括设置在显示装置中的现场可编程门阵列。
在本公开的一种示例实施例中，所述第一执行主体包括设置在显示装置中的IC，所述第二执行主体包括所述IC或者设置在显示装置中的现场可编程门阵列。
在本公开的一种示例实施例中，所述第一执行主体还可以被配置为：在确定同一像素岛中包括的当前视点的视点数量满足预设条件时，对该像素岛中的原始视点图进行平铺，得到视点平铺图；将所述视点平铺图由原始图像架构转换为像素岛架构，并确定所述视点平铺图的视线区域；根据所述视线区域所具有的第一像素行数以及时钟周期，计算所述像素岛架构中所需插入的虚拟像素行的第二像素行数；在所述像素岛架构中插入与所述第二像素行数对应的虚拟像素行，得到目标图像数据，并对所述目标图像数据进行格式转换得到第一待显示图像。
在本公开的一种示例实施例中，所述第一执行主体还可以被配置为：计算同一像素岛内包括的当前视点的视点数量，并判断所述视点数量与该像素岛内包括的数据分时复用的通路数量是否满足第一预设数量关系；若所述视点数量与所述通路数量满足所述第一预设数量关系，则确定所述当前视点的视点数量满足所述预设条件；若所述视点数量与所述通路数量不满足所述第一预设数量关系，则确定所述当前视点的视点数量不满足所述预设条件。
在本公开的一种示例实施例中，所述第一执行主体还可以被配置为：若所述视点数量与所述通路数量不满足所述第一预设数量关系，则根据视点数量以及通路数量，计算所需增加的虚拟视点的数量；在所述当前视点中增加与虚拟视点的数量相等的虚拟视点，直至增加后的视点数量与所述通路数量满足所述第一预设数量关系。
在本公开的一种示例实施例中，所述第一执行主体还可以被配置为：将所述视点平铺图由原始的横向RGB图像架构转换为纵向RGB的像素岛架构。
在本公开的一种示例实施例中，所述第一执行主体还可以被配置为：判断所述视线区 域所具有的第一像素行数以及时钟周期之间是否满足第二预设数量关系；若满足所述第二预设数量关系，则所述像素岛架构中所需插入的虚拟像素行的第二像素行数为零；若不满足所述第二预设数量关系，则根据所述第一像素行数以及时钟周期，计算所述虚拟像素行的第二像素行数。
在本公开的一种示例实施例中，所述第一执行主体还可以被配置为：确定所述视线区域所具有的GOA时序的开启方式，并根据所述开启方式确定所述视线区域所具有的第一像素行数以及时钟周期；其中，所述视线区域包括人眼注视区域和/或非人眼注视区域；判断所述第一像素行数以及时钟周期之间是否满足第二预设数量关系；其中，当所述视线区域为人眼注视区域时，所述GOA时序的开启方式包括第一开启方式或第二开启方式；当所述视线区域为非人眼注视区域时，所述GOA时序的开启方式包括第二开启方式或第三开启方式；其中，所述第一开启方式为GOA逐行开，所述第二开启方式为GOA两行同开，所述第三开启方式为GOA四行同开。
在本公开的一种示例实施例中，所述第一执行主体还可以被配置为：根据所述视线区域所具有的GOA时序的开启方式，对所述目标图像数据进行格式转换，得到第一待显示图像；其中，当所述开启方式为第一开启方式时，将所述目标图像数据转换为具有第一预设数据格式的第一待显示图像；当所述开启方式为第二开启方式时，将所述目标图像数据转换为具有第二预设数据格式的第一待显示图像；当所述开启方式为第三开启方式时，将所述目标图像数据转换为具有第三预设数据格式的第一待显示图像。
在本公开的一种示例实施例中，所述第一执行主体还可以被配置为：判断显示面板中的源驱动芯片中包括第一薄膜场效应晶体管的第一晶体管类型，是否与显示面板中的第二薄膜场效应晶体管的第一晶体管类型一致；若所述第一晶体管类型与第二晶体管类型不一致，则对所述第一待显示图像进行灰阶反向处理，得到第二待显示图像。
在本公开的一种示例实施例中，所述第一执行主体还可以被配置为：判断源驱动芯片中是否包括闲置通道；在确定包括所述闲置通道时，在所述第一待显示图像中插入虚拟像素列，并对插入虚拟像素列以后的第一待显示图像进行灰阶反向处理，得到第二待显示图像；其中，所述虚拟像素列在所述第一待显示图像中的插入位置，与所述闲置通道在所述源驱动芯片中的位置对应；在确定不包括所述闲置通道时，对所述第一待显示图像进行灰阶反向处理，得到第二待显示图像。
在本公开的一种示例实施例中，所述第一执行主体还可以被配置为：根据所述显示面板的所包括的像素岛的数量、每一个像素岛中所包括的当前视点的视点数量以及所述显示面板的横向分辨率，计算驱动所述显示面板所需要的源驱动芯片的数量；根据所述源驱动芯片的芯片通道数量以及源驱动芯片的数量，计算所述显示面板的总通道数，并根据所述总通道数以及所述横向分辨率，计算需要在所述源驱动芯片中插入的闲置通道的数量；为所述闲置通道设置插入规则，以使得根据所述插入规则将所述闲置通道插入至对应的源驱动芯片中。
在本公开的一种示例实施例中，所述插入规则包括以下规则中的至少一项：
每一颗被插入闲置通道的源驱动芯片，是以第一预设放置方式进行放置的；
所述闲置通道是以第二预设放置方式放置在所述源驱动芯片中的；
每一颗被插入闲置通道的源驱动芯片，是以第三预设方式放置在显示面板的对应位置中的。
在本公开的一种示例实施例中，所述第一执行主体还可以被配置为：在所述第一待显示图像或第二待显示图像中添加信息行；其中，所述信息行用于表征高清区位置。
根据本公开示例实施例的一个方面，提供一种计算机可读存储介质，其上存储有计算机程序，所述计算机程序被处理器执行时实现上述任一项示例实施例所述的图像显示方法。
根据本公开示例实施例的一个方面，提供一种电子设备，包括：
处理器；以及
存储器，用于存储所述处理器的可执行指令；
其中，所述处理器配置为经由执行所述可执行指令来执行任一项示例实施例所述的图像显示方法。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。在附图中：
图1示意性示出根据本公开示例实施例的一种图像显示方法的流程图。
图2示意性示出根据本公开示例实施例的一种图像显示系统的框图。
图3示意性示出根据本公开示例实施例的一种原始视点图的示例图。
图4示意性示出根据本公开示例实施例的一种添加了虚拟视点以后的原始视点图的示例图。
图5示意性示出根据本公开示例实施例的一种纵向RGB的像素岛架构的示例图。
图6示意性示出根据本公开示例实施例的一种不同GOA时序分区插入的虚拟像素行的第二像素行数的示例图。
图7示意性示出根据本公开示例实施例的一种插入Dummy行数据(虚拟像素行)之后的像素岛架构的示例图。
图8示意性示出根据本公开示例实施例的一种具有第一预设数据格式 (RRRRGGGGBBBB)的第一待显示图像的示例图。
图9示意性示出根据本公开示例实施例的一种对第一待显示图像进行处理得到第二待显示图像的方法流程图。
图10示意性示出根据本公开示例实施例的一种将被插入闲置通道的源驱动芯片放置至显示面板的一侧的示例图。
图11示意性示出根据本公开示例实施例的一种将被插入闲置通道的源驱动芯片放置至显示面板的左右两侧的示例图。
图12示意性示出根据本公开示例实施例的一种将floating channel给虚拟像素列的具体示例图。
图13示意性示出根据本公开示例实施例的另一种图像显示方法的流程图。
图14示意性示出根据本公开示例实施例的一种图像显示装置的框图。
图15示意性示出根据本公开示例实施例的一种用于实现上述图像显示方法的电子设备。
具体实施方式
现在将参照附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的范例；相反，提供这些实施方式使得本公开将更加全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。所描述的特征、结构或特性可以以任何合适的方式结合在一个或更多实施方式中。
此外，附图仅为本公开的示意性图解，并非一定是按比例绘制。图中相同的附图标记表示相同或类似的部分，因而将省略对它们的重复描述。附图中所示的一些方框图是功能实体，不一定必须与物理或逻辑上独立的实体相对应。可以采用软件形式来实现这些功能实体，或在一个或多个硬件模块或集成电路中实现这些功能实体，或在不同网络和/或处理器装置和/或微控制器装置中实现这些功能实体。
现有的显示面板(Panel)的分辨率均为标准分辨率，如FHD(Full High Definition)显示面板、4K显示面板以及8K显示面板等；其中，在通过FPGA控制显示面板对图像进行显示之前，还需要通过FPGA对待显示图像进行GOA时序以及Data mapping等处理。
但是，上述方案存在如下缺陷：一方面，未涉及到如何对非标准分辨率的图像数据进行处理；另一方面，FPGA编程尤其调试时间太长，针对光场项目复杂的GOA时序和Data mapping则需要花费更多时间，影响产品产出时间，也即图像处理效率较低。
基于此，本示例实施方式中首先提供了一种图像显示方法，该方法可以运行于主机、显示装置、服务器、服务器集群或云服务器等；当然，本领域技术人员也可以根据需求在其他平台运行本公开的方法，本示例性实施例中对此不做特殊限定。参考图1所示，该图像显示方法可以包括以下步骤：
步骤S110.通过第一执行主体获取原始视点图，并对所述原始视点图进行处理，得到第一待显示图像；
在本示例实施例中，首先，获取原始视点图，并在确定同一像素岛中包括的当前视点的视点数量满足预设条件时，对该像素岛中的原始视点图进行平铺，得到视点平铺图；其次，将所述视点平铺图由原始图像架构转换为像素岛架构，并确定所述视点平铺图的视线区域；然后，根据所述视线区域所具有的第一像素行数以及时钟周期，计算所述像素岛架构中所需插入的虚拟像素行的第二像素行数；进一步的，在所述像素岛架构中插入与所述第二像素行数对应的虚拟像素行，得到目标图像数据，并对所述目标图像数据进行格式转换得到第一待显示图像。
具体的，由于可以根据视线区域所具有的第一像素行数以及时钟周期，计算像素岛架构中所需插入的虚拟第二像素行数；最后在像素岛架构中插入与虚拟第二像素行数对应的虚拟像素行，得到目标图像数据，并对目标图像数据进行格式转换得到第一待显示图像，进而可以在通过FPGA控制显示面板对第一待显示图像进行显示的过程中，当上一个视线区域显示完成后，可以直接进入下一个视线区域对应的像素行，进而提高了图像显示的流畅性。
步骤S120.通过所述第一执行主体将所述第一待显示图像发送至第二执行主体；
步骤S130.通过所述第二执行主体控制显示面板对所述第一待显示图像进行显示。
在上述图像显示方法中，由于可以将对原始视点图的处理任务以及控制第一待显示图像进行显示的显示任务分别放置到不同的执行主体上，进而可以减少第一执行主体以及第二执行主体的任务负担，进而提高图像处理效率。
以下，将结合附图对本公开示例实施例图像显示方法进行详细的解释以及说明。
首先，对本公开示例实施例中所涉及到的名词进行解释：
FPGA：全称Field-Programmable Gate Array，即现场可编程门阵列；
TCON：Timing Control，逻辑控制板；
X-Zone：可以用于表示在智能观看的场景下，将显示面板划分为人眼注视区域以及人眼非注视区域；其中，人眼注视区域以及人眼非注视区域所具有的屏幕分辨率或者像素帧率是不同的。
其次，对本公开示例实施例的发明目的进行解释以及说明。具体的，在一些光场3D项目中需要采用像素岛架构进行设置；在具体的应用中，子像素尺寸和面板尺寸决定该显示面板中可以包括的像素岛个数，从而导致该显示面板的横向分辨率多为非标准分辨率；为了解决现有技术中无法对非标准分辨率的图像进行处理的问题，本公开提出一种图像显示方法，可以在硬件和软件进行相应的处理，进而解决非标准分辨率问题。
同时，光场3D相关项目因具有复杂的GOA(Gatedriver On Array，阵列基板行驱动)时序、Data Mapping及庞大的数据处理需求，目前暂无可用的TCON方案满足需求；因此，可以通过FPGA进行替代，FPGA可编程特性使得该器件具有独特的灵活性；但是，太多 的需求也会占用大量的编程和调试时间，进而使得图像显示效率较低；为了解决该问题，本公开示例实施例提出将图像显示通过主机来进行实现，进而可以大大节省FPGA编程和调试时间，加快产品产出；并且，本公开所提出的图像显示方法，可以包含多种时序排图规则：GOA逐行开、GOA两行同开、GOA四行同开、X-Zone，进而可以满足多种应用场景。
以下，将对本公开示例实施例所涉及到的图像显示系统进行解释以及说明。具体的，参考图2所示，该显示系统可以包括主机210以及显示器220，其中，主机210以及显示器220可以通过预设的数据接口进行通信连接。具体的，主机中可以设置有第一执行主体，显示装置中可以设置有第一执行主体和/或第二执行主体；并且，第一执行主体包括设置在主机中的处理器，所述第二执行主体包括设置在显示装置中的现场可编程门阵列；同时，第一执行主体也可以包括设置在显示装置中的IC，所述第二执行主体包括所述IC或者设置在显示装置中的现场可编程门阵列。进一步的，当第一执行主体为设置在显示装置中的IC时，该IC可以同时实现图像处理任务(对原始视点图进行处理得到第一待显示图像)以及控制第一待显示图像的任务；图像处理以及图像显示可以同时在IC中进行实现。
在一种示例实施例中，当第一执行主体为设置在主机中的处理器，第二执行主体为设置在显示装置中的现场可编程门阵列时，该图像显示系统可以通过如下方式执行图像处理以及图像显示任务：具体的，显示器220可以包括显示面板221以及现场可编程门阵列222，所述主机通过预设的数据接口与所述现场可编程门阵列连接；所述现场可编程门阵列用于通过所述预设的数据接口接收主机发送的第一待显示图像或第二待显示图像，并控制所述显示面板对所述第一待显示图像或第二待显示图像进行显示。其中，该预设的数据接口可以是DisplayPort(DP，显示接口)，当然也可以是其他可以进行视频或者图像传输的接口，本示例对此不做特殊限制。同时，该主机210中可以包括图像采集设备211以及处理器(例如CPU和/或GPU)212，该图像采集设备可以用于拍摄当前用户的人眼图像，处理器可以用于根据拍摄到的人眼图像，确定该当前用户在显示面板上的人眼注视区域以及非人眼注视区域，该处理器还可以用于执行本公开示例实施例所记载的图像处理任务。
在本公开提供的一种示例实施例中，在对原始视点图进行处理的过程中，首先，需要进行视点图平铺处理。具体的，可以通过如下方式实现：在确定同一像素岛中包括的当前视点的视点数量满足预设条件时，对该像素岛中的原始视点图进行平铺，得到视点平铺图。
具体的，首先，获取原始视点图，其中，该原始视点图即为每个当前视点(View)对应的图片，系统端未对该原始视点图进行任何的处理；并且，每一个当前视点可以对应一张原始视点图，该原始视点图例如可以参考图3(a)所示；其中，在图3中，包括11张原始视点图，对应的当前视点例如可以是View 1、View 2、View 3、……、View 11。
其次，当获取到该原始视点图以后，需要判断同一像素岛中包括的当前视点的视点数量是否满足预设条件。其中，是否满足预设条件的具体判断过程可以通过如下方式实现：首先，计算同一像素岛内包括的当前视点的视点数量，并判断所述视点数量与该像素岛内 包括的数据分时复用的通路数量是否满足第一预设数量关系；其次，若所述视点数量与所述通路数量满足所述第一预设数量关系，则确定所述当前视点的视点数量满足所述预设条件；进一步的，若所述视点数量与所述通路数量不满足所述第一预设数量关系，则确定所述当前视点的视点数量不满足所述预设条件。更进一步的，若所述视点数量与所述通路数量不满足所述第一预设数量关系，则根据视点数量以及通路数量，计算所需增加的虚拟视点的数量；然后在所述当前视点中增加与虚拟视点的数量相等的虚拟视点，直至增加后的视点数量与所述通路数量满足所述第一预设数量关系。
举例来说，首先，判断通一个像素岛内包含的当前视点View数是否为MUX(multiplexer，数据分时复用)通路数量的整数倍：如果不是整数倍，如图三需要增加Dummy View(虚拟视点)，使得该像素岛中包括的当前视点的视点数量与虚拟视点的视点数量的总和，是MUX的通路数量的整数倍；例如，某一个像素岛中包括的MUX通路数量为6，该像素岛中所包括的当前视点的视点数量为11，则确认需要在该像素岛中添加一个虚拟视点；其中，添加虚拟视点以后的原始视点图例如可以参考图3(b)所示；其中，在图4中，包括11张原始视点图，对应的当前视点例如可以是View 1、View 2、View 3、……、View 11、View 12。此处需要补充说明的是，像素岛中所包括的MUX的通路数量，可以根据实际需要进行设置，本示例对此不做特殊限制；同时，在增加虚拟视点的过程中，所需增加的虚拟视点的视点数量，可以根据当前视点的视点数量以及与MUX的通路数量的某一整数倍之间的差值进行计算得到。通过该方法，可以在进行2D显示时保证同一个像素岛内所包括的显示内容相同的，进而可以进一步的提高图像显示的精确度；并且，通过将同一个像素岛中设置的视点数量设置为MUX的通路数量的整数倍，进而可以使得在通过MUX开关对该像素岛中包括的当前视点和/或虚拟视点进行控制时，可以均衡的将当前视点和/或虚拟视点分配给每一个MUX开关，进而可以起到负载均衡的目的。
此处需要进一步补充说明的是，虚拟视点中包括的像素信息，与View 1、View 2、View 3、……、View 11中包括的信息可以是不相关的，也可以是相关的，本示例对此不做特殊限制。并且，由于增加的虚拟视点，仅在对原始视点图进行处理得到第一待显示图像的过程中用到，新增的虚拟视点并不进行显示；因此，无论该虚拟视点中的像素信息是否与View 1、View 2、View 3、……、View 11相关，均不会影响最终的显示结果，进而可以实现对图像的精确显示。
进一步的，在确定同一像素岛中包括的当前视点的视点数量满足预设条件时，即可对该像素岛中的原始视点图进行平铺，得到视点平铺图。其中，在对原始视点图和/或虚拟视点图进行平铺的过程中，可以按照与原始视点图和/或虚拟视点图对应的当前视点和/或虚拟视点的视点编码，进行依次平铺，也可以根据其他方式进行平铺，本示例对此不做特殊限制。
在本公开提供的一种示例实施例中，在对原始视点图进行处理的过程中，其次，还需要进行图像架构转换处理。具体的，可以通过如下方式实现：将所述视点平铺图由原始图 像架构转换为像素岛架构，并确定所述视点平铺图的视线区域。
具体的，在架构转换的过程中，可以通过如下方式实现：将所述视点平铺图由原始的横向RGB图像架构转换为纵向RGB的像素岛架构；其中，所得到的纵向RGB的像素岛架构具体可以如图4所示。
在本公开提供的一种示例实施例中，在对原始视点图进行处理的过程中，进一步的，还需要计算需要插入的虚拟像素行。具体的，可以通过如下方式实现：根据所述视线区域所具有的第一像素行数以及时钟周期，计算所述像素岛架构中所需插入的虚拟像素行的第二像素行数。
在本示例实施例中，首先，判断所述视线区域所具有的第一像素行数以及时钟周期之间是否满足第二预设数量关系；其次，若满足所述第二预设数量关系，则所述像素岛架构中所需插入的虚拟像素行的第二像素行数为零；然后，若不满足所述第二预设数量关系，则根据所述第一像素行数以及时钟周期，计算所述虚拟像素行的第二像素行数。
其中，在具体的对视线区域所具有的第一像素行数以及时钟周期之间是否满足第二预设数量关系进行判断的过程中，可以通过如下方式进行：首先，确定所述视线区域所具有的GOA时序的开启方式，并根据所述开启方式确定所述视线区域所具有的第一像素行数以及时钟周期；其中，所述视线区域包括人眼注视区域和/或非人眼注视区域；其次，判断所述第一像素行数以及时钟周期之间是否满足第二预设数量关系；其中，当所述视线区域为人眼注视区域时，所述GOA时序的开启方式包括第一开启方式或第二开启方式；当所述视线区域为非人眼注视区域时，所述GOA时序的开启方式包括第二开启方式或第三开启方式；其中，所述第一开启方式为GOA逐行开，所述第二开启方式为GOA两行同开，所述第三开启方式为GOA四行同开。
具体的，由于在智能观看的场景下，需要将显示面板划分为人眼注视区域以及人眼非注视区域；并且，人眼注视区域以及人眼非注视区域所具有的屏幕分辨率或者像素帧率是不同的，即人眼注视区域需要具有较高的屏幕分辨率以及像素帧率，非人眼注视区域可以有较低的屏幕分辨率以及像素帧率；因此，X-Zone设计会将显示面板Panel分为若干个分区，并判断每个分区CLK打开次数是否为CLK周期(时钟周期)的整数倍：如果不是整数倍，为方便分区间CLK衔接，需要插入Dummy行数据(虚拟像素行)使之成整数倍，如果是整数倍，则需要插入的虚拟像素行为零，也即无需插入虚拟像素行。此处需要补充说明的，该分区所具有的CLK的打开次数，与该分区所具有的第一像素行数是一致的，也即，CLK开启一次，即控制一行像素进行显示；因此，在具体的应用过程中，也可以判断该分区的CLK打开次数与CLK周期是否成整数倍来进行实现。
进一步的，由于不同GOA时序在某些节点有差异，不同的区间所需要插入的虚拟像素行的第二像素行数是不同的，需要输出的数据格式也是不同的；因此，可以以显示面板的整屏V向为1620行，可以将其分为6个分区(人眼注视区域以及人眼非注视区域的总和为6，其中，人眼注视区域以及人眼非注视区域在其中所占的比例，在应用过程中可以 根据实际需要进行设置，本示例对此不做特殊限制)，每个分区270行为例，对各区间需要插入的虚拟像素行的第二像素行数的具体计算方法进行如下举例说明：
一方面，对于通过GOA逐行开的方式进行开启的人眼注视区域：CLK周期为24，每个分区CLK打开270次，270不能被24整除，每个分区需插入的虚拟像素行的Dummy行数＝([270/24]+1)*24-270＝18行，每个分区共288行；
另一方面，对于通过GOA两行同开的方式进行开启的人眼注视区域和/或非人眼注视区域：CLK周期为12，每个分区CLK打开135次，135不能被24整除，每个分区需插入Dummy行数＝([135/12]+1)*12-135＝9行，每个分区共144行；
再一方面，对于通过GOA四行同开的方式进行开启的非人眼注视区域：CLK周期为6，每个分区CLK打开69次，69不能被6整除，每个分区需插入Dummy行数＝([69/6]+1)*6-69＝3行，每个分区共72行。其中，不同GOA时序分区插入的虚拟像素行的第二像素行数具体可以参考图6所示。
此处需要补充说明的是，通过将人眼注视区域和/或非人眼注视区域中包括的第二像素行数设置为时钟周期的整数倍，进而可以是现在时钟周期内将该区域内包括的像素行进行全部开启，避免由于在该区域内的时钟周期内第二像素行数过多无法完全开启或者第二像素行数过少需要占用下一区域的第二像素行数导致的无法进行流畅的显示的问题，实现了在通过FPGA控制显示面板对第一待显示图像进行显示的过程中，当上一个视线区域显示完成后，可以直接进入下一个视线区域对应的像素行，进而提高了图像显示的流畅性。此处需要进一步补充说明的是，关于人眼注视区域和/或人眼非注视区域的确定，可以通过如下方式进行实现：通过图像采集设备拍摄当前用户的人眼图像，并根据拍摄到的当前用户的人眼图像，确定当前用户的眼睛相对于显示面板的位置以及方位角，根据位置以及方位角，确定用户在显示面板上的人眼注视区域，并将显示面板上除开人眼注视区域以外的区域作为非人眼注视区域。
在本公开提供的一种示例实施例中，在对原始视点图进行处理的过程中，最后，还需要进行图像数据格式转换。具体的，可以通过如下方式实现：在所述像素岛架构中插入与所述第二像素行数对应的虚拟像素行，得到目标图像数据，并对所述目标图像数据进行格式转换得到第一待显示图像。
在本示例实施例中，首先，在像素岛架构中插入与像素行书对应的虚拟像素行，进而可以得到目标图像数据；其中，所得到的目标图像数据具体可以参考图7所示。其次，当得到目标图像数据以后，还需要对目标数据进行格式转换得到第一待显示图像；其中，数据格式转换具体可以通过如下方式实现：根据所述视线区域所具有的GOA时序的开启方式，对所述目标图像数据进行格式转换，得到第一待显示图像；其中，当所述开启方式为第一开启方式时，将所述目标图像数据转换为具有第一预设数据格式的第一待显示图像；当所述开启方式为第二开启方式时，将所述目标图像数据转换为具有第二预设数据格式的第一待显示图像；当所述开启方式为第三开启方式时，将所述目标图像数据转换为具有第 三预设数据格式的第一待显示图像。
具体的，首先，因GOA设计Gate打开顺序为第1行(R)→第4行(R)→第7行(R)→第10行(R)→第2行(G)→第5行(G)→第8行(G)→第11行(G)→第3行(B)→第6行(B)→第9行(B)→第12行(B)……，因此GOA逐行开时数据传输应转为4R4G4B(RRRRGGGGBBBB)，也即，具有第一预设数据格式的第一待显示图像例如可以是4R4G4B，具体可以参考图8所示；其次，因为两行Gate同时打开只给一组相同数据，因此，GOA两行同开时，需要按照RRGGBB即2R2G2B方式输出，是逐行开数据量的二分之一；进一步的，因为四行Gate同时打开只给一组相同数据，因此，GOA四行同开时，需要按照RGB方式输出即可，是逐行开数据量的四分之一；同时，对于X-Zone来说，例如高清区逐行开、低清区四行同开，每个高清区按照4R4G4B，每个低清区按照RGB方式输出数据；在某一些情况下，高清区或者低清区在考虑是否选用2R2G2B方式输出时，可以根据显示面板的对应区域的充电速度来决定；若充电速度快，则可以在低清区选用2R2G2B方式输出；若充电速度慢，则可以在高清区选用2R2G2B方式输出；本示例对此不做特殊限制。
图9示意性示出根据本公开示例实施例的一种对第一待显示图像进行处理得到第二待显示图像的方法流程图。具体的，参考图9所示，可以包括以下步骤：
步骤S910，判断显示面板中的源驱动芯片中包括第一薄膜场效应晶体管的第一晶体管类型，是否与显示面板中的第二薄膜场效应晶体管的第一晶体管类型一致。
步骤S920，若所述第一晶体管类型与第二晶体管类型不一致，则对所述第一待显示图像进行灰阶反向处理，得到第二待显示图像。
其中，对所述第一待显示图像进行灰阶反向处理，得到第二待显示图像，具体可以通过如下方式实现：首先，判断源驱动芯片中是否包括闲置通道；其次，在确定包括所述闲置通道时，在所述第一待显示图像中插入虚拟像素列，并对插入虚拟像素列以后的第一待显示图像进行灰阶反向处理，得到第二待显示图像；其中，所述虚拟像素列在所述第一待显示图像中的插入位置，与所述闲置通道在所述源驱动芯片中的位置对应；进一步的，在确定不包括所述闲置通道时，对所述第一待显示图像进行灰阶反向处理，得到第二待显示图像。其中，所述插入规则包括以下规则中的至少一项：每一颗被插入闲置通道的源驱动芯片，是以第一预设放置方式进行放置的；所述闲置通道是以第二预设放置方式放置在所述源驱动芯片中的；每一颗被插入闲置通道的源驱动芯片，是以第三预设方式放置在显示面板的对应位置中的。
以下，将对步骤S910-步骤S920进行解释以及说明。首先，判断Source Driver IC(源驱动芯片)中包括的第一薄膜场效应晶体管TFT的第一晶体管类型，是否与显示面板Panel所用的第二薄膜场效应晶体管TFT的第二晶体管类型是否一致；如果不是同类型(不一致)，如Source Driver IC适用于NMOS，灰阶与电压成正比，而Panel为PMOS TFT，灰阶与电压成反比，则需要将图片中进行灰阶反向处理；其中，灰阶反向的具体处理方式为：图片(第一待显示图像)中的灰阶＝L255灰阶-需要显示的灰阶，如需要显示L0时，图片 需为L255；也即，第一待显示图像中的灰阶值可以通过L255灰阶-需要显示的灰阶所得到的灰阶值进行显示。其中，具体的计算公式可以如下公式(1)所示：
L排图＝L255-L显示；公式(1)
进一步的，在实际应用过程中，还需要在第一待显示图像中插入虚拟像素列。具体的，虚拟像素列的插入规则可以如下所示：首先，判断Source IC(源驱动芯片)是否有floating channel(闲置通道)：如果有，则需要将floating channel给Dummy数据，因此需要在图片中插入Dummy列数据(虚拟像素列)，其中，Dummy列数据插入位置与floating channel对应；如果没有闲置通道，则可以直接进行灰阶处理。此处需要补充说明的是，对晶体管类型的具体判断过程以及对闲置通道的具体判断过程，在实际的实现过程中并没有严格的限制，可以根据实际需要设置对应的处理流程，本示例对此不做特殊限制。
进一步的，为了可以将虚拟像素列给到闲置通道，还需要在源驱动芯片中设置闲置通道。具体的，像素岛架构为同时满足像素Pixel尺寸和显示面板Panel尺寸，分辨率多为非标准，比如每个像素岛12View，共1880个像素岛，横向分辨率为1880*12/3＝7520*RGB。假设一颗COF channel数为1440，所需COF数量＝7520*3/1440＝15.67≈16；因此，在具体的在COF中设计闲置通道时，可以遵循如下设计规则：
16颗COF总Channel数＝16*1440＝23040，23040-7520*RGB＝480，即Source IC的Channel数比实际需求的Channel多480；因此，硬件设计可以将这480个Channel设置为floating(闲置)，该闲置通道不连接panel，floating的原则有三个：一方面，每颗被插入了闲置通道的源驱动芯片，位置需左右对称；另一方面，为保证源驱动芯片的正常工作，floating channel需固定在该源驱动芯片的两端；再一方面，每一颗被插入闲置通道的源驱动芯片，需要放置到显示面板Panel的最左或/和最右，尽可能减少跟其他Source IC的画质差；其中，具体的放置图可以参考图10以及图11所示；并且，当源驱动芯片COF被设置了某些闲置通道floating channel后，该源驱动芯片中所包括的通道数量会与其他没有设置闲置通道的源驱动芯片的通道数量不同，数据处理时难以与其他COF保持同步；因此，在对显示装置中包括的FPGA或TCON进行设计时，需要按照标准分辨率进行设计，并将floating channel给虚拟像素列即可；其中，将floating channel给虚拟像素列的具体实现方式，可以参考图12所示。通过该方法，可以解决现有技术中无法解决非标准分辨率的问题。
至此，在主机中对原始视点图的具体图像显示过程已经全部完成。进一步的，为了可以在显示面板对处理完成的图像进行显示，还需要执行如下步骤：首先，在所述第一待显示图像或第二待显示图像中添加信息行；其中，所述信息行用于表征高清区位置；然后，基于预设的数据接口，将所述第一待显示图像或第二待显示图像发送至显示器中的现场可编程门阵列，以使得所述现场可编程门阵列驱动所述显示器中的显示面板对所述第一待显示图像或第二待显示图像进行显示。也即，在具体的处理过程中，可以判断是否为X-Zone时序(也即是否为智能观看场景)，如果是X-Zone时序，因高清区和低清区GOA时序不 同，需将高清区位置通过图片信息行传递给FPGA，以便调用适合的时序，因此可以在第一待显示图像或第二待显示图像的首行增加一行作为信息行，以便于FPGA在驱动显示面板进行显示的过程中，根据该信息行控制显示面板进行高清显示(以RRRRGGGGBBBB的方式显示，或者以RRGGBB的方式显示)；如果整屏时序相同，无需添加信息行。
此处需要补充说明的是，此处之所以提到了第一待显示图像或第二待显示图像，是因为存在的一种情况是：当不存在floating channel且Source Driver IC(源驱动芯片)中包括的第一薄膜场效应晶体管TFT的第一晶体管类型，是否与显示面板Panel所用的第二薄膜场效应晶体管TFT的第二晶体管类型一致时，可以直接将第一待显示图像发送至FPGA，或者在第一待显示图像中增加信息行后发送至FPGA；当然，当存在floating channel，或者Source Driver IC(源驱动芯片)中包括的第一薄膜场效应晶体管TFT的第一晶体管类型，是否与显示面板Panel所用的第二薄膜场效应晶体管TFT的第二晶体管类型不一致时，可以在第一待显示图像中增加虚拟像素列和/或进行灰阶反向处理得到第二待显示图像，再将第二待显示图像发送至FPGA或者在第二待显示图像中增加信息行以后发送至FPGA。当然，在将第一待显示图像或者第二待显示图像发送至FPGA时，每次仅发送第一待显示图像或者第二待显示图像，不会存在同时发送第一待显示图像以及第二待显示图像的情况。
进一步的，在FPGA控制显示面板对第一待显示图像或第二待显示图像进行显示的过程中，可以通过如下方式进行实现：确定依次扫描显示面板中每个处于人眼注视区域的像素行时位于人眼注视区域的各第一像素的第一扫描顺序，根据各第一像素所属像素岛和第一扫描顺序，确定用于控制各第一像素的第一开关的第一开启顺序，按照第一开启顺序依次开启各像素岛内的第一开关；和/或确定依次针对显示面板中每个处于非人眼注视区域的像素组，同时扫描像素组中的所有像素行时各处于非人眼注视区域的第二像素的第二扫描顺序；根据各第二像素所属像素岛和第二扫描顺序，确定用于控制各第二像素的第二开关的第二开启顺序，按照第二开启顺序依次开启各像素岛内的第二开关。
以下，将结合图13对本公开示例实施例所记载的图像显示方法进行进一步的解释以及说明。具体的，参考图13所示，该图像显示方法可以包括以下步骤：
步骤S1301，获取原始视点图；
步骤S1302，判断View数是否为MUX通路的整数倍：也即，判断同一像素岛中包括的当前视点的视点数量是否为MUX的通路数量的整数倍；若是，跳转至步骤S1303，若否，跳转至步骤S1304；
步骤S1303，增加Dummy View：也即，根据视点数量以及通路数量，计算所需增加的虚拟视点的数量；在当前视点中增加与虚拟视点的数量相等的虚拟视点，直至增加后的视点数量与通路数量满足所述第一预设数量关系；
步骤S1304，像素岛转换：也即，对原始视点图进行平铺，得到视点平铺图，并将视点平铺图由横向RGB转换为列项RGB；
步骤S1305，判断每个分区行数是否为CLK周期的整数倍：也即，判断该分区所具 有的第一像素行数是否为CLK周期的整数倍；若否，则跳转至步骤S1306；若是，则跳转至步骤S1307；
步骤S1306，分区间插入Dummy行，得到目标图像数据：也即，对于通过GOA逐行开的方式进行开启的人眼注视区域：CLK周期为24，每个分区CLK打开270次，270不能被24整除，每个分区需插入的虚拟像素行的Dummy行数＝([270/24]+1)*24-270＝18行，每个分区共288行；对于通过GOA两行同开的方式进行开启的人眼注视区域和/或非人眼注视区域：CLK周期为12，每个分区CLK打开135次，135不能被24整除，每个分区需插入Dummy行数＝([135/12]+1)*12-135＝9行，每个分区共144行；对于通过GOA四行同开的方式进行开启的非人眼注视区域：CLK周期为6，每个分区CLK打开69次，69不能被6整除，每个分区需插入Dummy行数＝([69/6]+1)*6-69＝3行，每个分区共72行；
步骤S1307，对目标图像数据进行格式转换，得到第一待显示图像：也即，GOA逐行开时数据传输应转为4R4G4B(RRRRGGGGBBBB)；GOA两行同开时，需要按照RRGGBB即2R2G2B方式输出，是逐行开数据量的二分之一；GOA四行同开时，需要按照RGB方式输出即可，是逐行开数据量的四分之一；
步骤S1308，判断SD Channel是否有floating：也即，判断Source IC(源驱动芯片)是否有floating channel(闲置通道)，若是，则跳转至步骤S1309；若否，则跳转至步骤S1310；
步骤S1309，将floating Channel给Dummy数据：也即，在第一待显示图片中插入Dummy列数据(虚拟像素列)，并将floating channel给Dummy列数据，并且，Dummy列数据插入位置与floating channel对应；
步骤S1310，判断SD与panel TFT是否同类型：也即，判断Source Driver IC(源驱动芯片)中包括的第一薄膜场效应晶体管TFT的第一晶体管类型，是否与显示面板Panel所用的第二薄膜场效应晶体管TFT的第二晶体管类型是否一致；若否，则跳转至步骤S1311；若否，则跳转至步骤S1312；
步骤S1311，灰阶反向：也即，对加入了虚拟列数据的第一待显示图像进行灰阶反向，得到第二待处理图像；
步骤S1312，判断是否为X-Zone时序；若是，则跳转至步骤S1313；若否，则跳转至步骤S1313；
步骤S1313，则在第二待处理图像中添加信息行；
步骤S1314，将第二待处理图像图像发送至FPGA。
至此，可以毫无疑问的得出，本公开示例实施例所记载的图像显示方法，一方面，采用了可以解决像素岛架构非标准分辨率问题的软硬件设计；另一方面，设计了像素岛架构通过排图处理数据的方案；再一方面，设计了不同GOA时序不同排图规则。其中，不同GOA时序的不同排图规则具体可以如下表1所示：
表1不同GOA时序的不同排图规则
Figure PCTCN2022090044-appb-000001
下述为本公开装置实施例，可以用于执行本公开方法实施例。对于本公开装置实施例中未披露的细节，请参照本公开方法实施例。
根据本公开的一个方面，提供一种图像显示装置，配置于主机。参考图14所示，该图像显示装置可以包括原始视点图处理模块1410、第一待显示图像发送模块1420、第一待显示图像显示模块1430。其中：
原始视点图处理模块1410，可以用于通过第一执行主体获取原始视点图，并对所述原始视点图进行处理，得到第一待显示图像；
第一待显示图像发送模块1420，可以用于通过所述第一执行主体将所述第一待显示图像发送至第二执行主体；
第一待显示图像显示模块1430，可以用于通过所述第二执行主体控制显示面板对所述第一待显示图像进行显示。
在本公开的一种示例性实施例中，所述第一执行主体包括设置在主机中的处理器，所述第二执行主体包括设置在显示装置中的现场可编程门阵列。
在本公开的一种示例性实施例中，所述第一执行主体包括设置在显示装置中的IC， 所述第二执行主体包括所述IC或者设置在显示装置中的现场可编程门阵列。
在本公开的一种示例性实施例中，，对所述原始视点图进行处理，得到第一待显示图像，包括：
在确定同一像素岛中包括的当前视点的视点数量满足预设条件时，对该像素岛中的原始视点图进行平铺，得到视点平铺图；
将所述视点平铺图由原始图像架构转换为像素岛架构，并确定所述视点平铺图的视线区域；
根据所述视线区域所具有的第一像素行数以及时钟周期，计算所述像素岛架构中所需插入的虚拟像素行的第二像素行数；
在所述像素岛架构中插入与所述第二像素行数对应的虚拟像素行，得到目标图像数据，并对所述目标图像数据进行格式转换得到第一待显示图像。
在本公开的一种示例性实施例中，所述图像显示装置还包括：
第一判断模块，可以用于计算同一像素岛内包括的当前视点的视点数量，并判断所述视点数量与该像素岛内包括的数据分时复用的通路数量是否满足第一预设数量关系；
第一确定模块，可以用于若所述视点数量与所述通路数量满足所述第一预设数量关系，则确定所述当前视点的视点数量满足所述预设条件；
第二确定模块，可以用于若所述视点数量与所述通路数量不满足所述第一预设数量关系，则确定所述当前视点的视点数量不满足所述预设条件。
在本公开的一种示例性实施例中，所述图像显示装置还包括：
虚拟视点数量计算模块，可以用于若所述视点数量与所述通路数量不满足所述第一预设数量关系，则根据视点数量以及通路数量，计算所需增加的虚拟视点的数量；
虚拟视点增加模块，可以用于在所述当前视点中增加与虚拟视点的数量相等的虚拟视点，直至增加后的视点数量与所述通路数量满足所述第一预设数量关系。
在本公开的一种示例性实施例中，将所述视点平铺图由原始图像架构转换为像素岛架构，包括：
将所述视点平铺图由原始的横向RGB图像架构转换为纵向RGB的像素岛架构。
在本公开的一种示例性实施例中，根据所述视线区域所具有的第一像素行数以及时钟周期，计算所述像素岛架构中所需插入的虚拟像素行的第二像素行数，包括：
判断所述视线区域所具有的第一像素行数以及时钟周期之间是否满足第二预设数量关系；
若满足所述第二预设数量关系，则所述像素岛架构中所需插入的虚拟像素行的第二像素行数为零；
若不满足所述第二预设数量关系，则根据所述第一像素行数以及时钟周期，计算所述虚拟像素行的第二像素行数。
在本公开的一种示例性实施例中，判断所述视线区域所具有的第一像素行数以及时钟 周期之间是否满足第二预设数量关系，包括：
确定所述视线区域所具有的GOA时序的开启方式，并根据所述开启方式确定所述视线区域所具有的第一像素行数以及时钟周期；其中，所述视线区域包括人眼注视区域和/或非人眼注视区域；
判断所述第一像素行数以及时钟周期之间是否满足第二预设数量关系；其中，当所述视线区域为人眼注视区域时，所述GOA时序的开启方式包括第一开启方式或第二开启方式；当所述视线区域为非人眼注视区域时，所述GOA时序的开启方式包括第二开启方式或第三开启方式。
在本公开的一种示例性实施例中，所述第一开启方式为GOA逐行开，所述第二开启方式为GOA两行同开，所述第三开启方式为GOA四行同开。
在本公开的一种示例性实施例中，对所述目标图像数据进行格式转换得到第一待显示图像，包括：
根据所述视线区域所具有的GOA时序的开启方式，对所述目标图像数据进行格式转换，得到第一待显示图像；
其中，当所述开启方式为第一开启方式时，将所述目标图像数据转换为具有第一预设数据格式的第一待显示图像；
当所述开启方式为第二开启方式时，将所述目标图像数据转换为具有第二预设数据格式的第一待显示图像；
当所述开启方式为第三开启方式时，将所述目标图像数据转换为具有第三预设数据格式的第一待显示图像。
在本公开的一种示例性实施例中，所述图像显示装置还包括：
第二判断模块，可以用于判断显示面板中的源驱动芯片中包括第一薄膜场效应晶体管的第一晶体管类型，是否与显示面板中的第二薄膜场效应晶体管的第一晶体管类型一致；
灰阶反向处理模块，可以用于若所述第一晶体管类型与第二晶体管类型不一致，则对所述第一待显示图像进行灰阶反向处理，得到第二待显示图像。
在本公开的一种示例性实施例中，对所述第一待显示图像进行灰阶反向处理，得到第二待显示图像，包括：
判断源驱动芯片中是否包括闲置通道；
在确定包括所述闲置通道时，在所述第一待显示图像中插入虚拟像素列，并对插入虚拟像素列以后的第一待显示图像进行灰阶反向处理，得到第二待显示图像；其中，所述虚拟像素列在所述第一待显示图像中的插入位置，与所述闲置通道在所述源驱动芯片中的位置对应；
在确定不包括所述闲置通道时，对所述第一待显示图像进行灰阶反向处理，得到第二待显示图像。
在本公开的一种示例性实施例中，所述插入规则包括以下规则中的至少一项：
每一颗被插入闲置通道的源驱动芯片，是以第一预设放置方式进行放置的；
所述闲置通道是以第二预设放置方式放置在所述源驱动芯片中的；
每一颗被插入闲置通道的源驱动芯片，是以第三预设方式放置在显示面板的对应位置中的。
在本公开的一种示例性实施例中，所述图像显示装置还包括：
信息行添加模块，可以用于在所述第一待显示图像或第二待显示图像中添加信息行；其中，所述信息行用于表征高清区位置。
上述图像显示装置中各模块的具体细节已经在对应的图像显示方法中进行了详细的描述，因此此处不再赘述。
应当注意，尽管在上文详细描述中提及了用于动作执行的设备的若干模块或者单元，但是这种划分并非强制性的。实际上，根据本公开的实施方式，上文描述的两个或更多模块或者单元的特征和功能可以在一个模块或者单元中具体化。反之，上文描述的一个模块或者单元的特征和功能可以进一步划分为由多个模块或者单元来具体化。
此外，尽管在附图中以特定顺序描述了本公开中方法的各个步骤，但是，这并非要求或者暗示必须按照该特定顺序来执行这些步骤，或是必须执行全部所示的步骤才能实现期望的结果。附加的或备选的，可以省略某些步骤，将多个步骤合并为一个步骤执行，以及/或者将一个步骤分解为多个步骤执行等。
在本公开的示例性实施例中，还提供了一种能够实现上述方法的电子设备。
所属技术领域的技术人员能够理解，本公开的各个方面可以实现为系统、方法或程序产品。因此，本公开的各个方面可以具体实现为以下形式，即：完全的硬件实施方式、完全的软件实施方式(包括固件、微代码等)，或硬件和软件方面结合的实施方式，这里可以统称为“电路”、“模块”或“系统”。
下面参照图15来描述根据本公开的这种实施方式的电子设备1500。图15显示的电子设备1500仅仅是一个示例，不应对本公开实施例的功能和使用范围带来任何限制。
如图15所示，电子设备1500以通用计算设备的形式表现。电子设备1500的组件可以包括但不限于：上述至少一个处理单元1510、上述至少一个存储单元1520、连接不同系统组件(包括存储单元1520和处理单元1510)的总线1530以及显示单元1540。
其中，所述存储单元存储有程序代码，所述程序代码可以被所述处理单元1510执行，使得所述处理单元1510执行本说明书上述“示例性方法”部分中描述的根据本公开各种示例性实施方式的步骤。例如，所述处理单元1510可以执行图1中所示的步骤S110：通过第一执行主体获取原始视点图，并对所述原始视点图进行处理，得到第一待显示图像；步骤S120：通过所述第一执行主体将所述第一待显示图像发送至第二执行主体；步骤S130：通过所述第二执行主体控制显示面板对所述第一待显示图像进行显示。
存储单元1520可以包括易失性存储单元形式的可读介质，例如随机存取存储单元 (RAM)15201和/或高速缓存存储单元15202，还可以进一步包括只读存储单元(ROM)15203。
存储单元1520还可以包括具有一组(至少一个)程序模块15205的程序/实用工具15204，这样的程序模块15205包括但不限于：操作系统、一个或者多个应用程序、其它程序模块以及程序数据，这些示例中的每一个或某种组合中可能包括网络环境的实现。
总线1530可以为表示几类总线结构中的一种或多种，包括存储单元总线或者存储单元控制器、外围总线、图形加速端口、处理单元或者使用多种总线结构中的任意总线结构的局域总线。
电子设备1500也可以与一个或多个外部设备1600(例如键盘、指向设备、蓝牙设备等)通信，还可与一个或者多个使得用户能与该电子设备1500交互的设备通信，和/或与使得该电子设备1500能与一个或多个其它计算设备进行通信的任何设备(例如路由器、调制解调器等等)通信。这种通信可以通过输入/输出(I/O)接口1550进行。并且，电子设备1500还可以通过网络适配器1560与一个或者多个网络(例如局域网(LAN)，广域网(WAN)和/或公共网络，例如因特网)通信。如图所示，网络适配器1560通过总线1530与电子设备1500的其它模块通信。应当明白，尽管图中未示出，可以结合电子设备1500使用其它硬件和/或软件模块，包括但不限于：微代码、设备驱动器、冗余处理单元、外部磁盘驱动阵列、RAID系统、磁带驱动器以及数据备份存储系统等。
通过以上的实施方式的描述，本领域的技术人员易于理解，这里描述的示例实施方式可以通过软件实现，也可以通过软件结合必要的硬件的方式来实现。因此，根据本公开实施方式的技术方案可以以软件产品的形式体现出来，该软件产品可以存储在一个非易失性存储介质(可以是CD-ROM，U盘，移动硬盘等)中或网络上，包括若干指令以使得一台计算设备(可以是个人计算机、服务器、终端装置、或者网络设备等)执行根据本公开实施方式的方法。
在本公开的示例性实施例中，还提供了一种计算机可读存储介质，其上存储有能够实现本说明书上述方法的程序产品。在一些可能的实施方式中，本公开的各个方面还可以实现为一种程序产品的形式，其包括程序代码，当所述程序产品在终端设备上运行时，所述程序代码用于使所述终端设备执行本说明书上述“示例性方法”部分中描述的根据本公开各种示例性实施方式的步骤。
根据本公开的实施方式的用于实现上述方法的程序产品，其可以采用便携式紧凑盘只读存储器(CD-ROM)并包括程序代码，并可以在终端设备，例如个人电脑上运行。然而，本公开的程序产品不限于此，在本文件中，可读存储介质可以是任何包含或存储程序的有形介质，该程序可以被指令执行系统、装置或者器件使用或者与其结合使用。
所述程序产品可以采用一个或多个可读介质的任意组合。可读介质可以是可读信号介质或者可读存储介质。可读存储介质例如可以为但不限于电、磁、光、电磁、红外线、或半导体的系统、装置或器件，或者任意以上的组合。可读存储介质的更具体的例子(非 穷举的列表)包括：具有一个或多个导线的电连接、便携式盘、硬盘、随机存取存储器(RAM)、只读存储器(ROM)、可擦式可编程只读存储器(EPROM或闪存)、光纤、便携式紧凑盘只读存储器(CD-ROM)、光存储器件、磁存储器件、或者上述的任意合适的组合。
计算机可读信号介质可以包括在基带中或者作为载波一部分传播的数据信号，其中承载了可读程序代码。这种传播的数据信号可以采用多种形式，包括但不限于电磁信号、光信号或上述的任意合适的组合。可读信号介质还可以是可读存储介质以外的任何可读介质，该可读介质可以发送、传播或者传输用于由指令执行系统、装置或者器件使用或者与其结合使用的程序。
可读介质上包含的程序代码可以用任何适当的介质传输，包括但不限于无线、有线、光缆、RF等等，或者上述的任意合适的组合。
可以以一种或多种程序设计语言的任意组合来编写用于执行本公开操作的程序代码，所述程序设计语言包括面向对象的程序设计语言—诸如Java、C++等，还包括常规的过程式程序设计语言—诸如“C”语言或类似的程序设计语言。程序代码可以完全地在用户计算设备上执行、部分地在用户设备上执行、作为一个独立的软件包执行、部分在用户计算设备上部分在远程计算设备上执行、或者完全在远程计算设备或服务器上执行。在涉及远程计算设备的情形中，远程计算设备可以通过任意种类的网络，包括局域网(LAN)或广域网(WAN)，连接到用户计算设备，或者，可以连接到外部计算设备(例如利用因特网服务提供商来通过因特网连接)。
此外，上述附图仅是根据本公开示例性实施例的方法所包括的处理的示意性说明，而不是限制目的。易于理解，上述附图所示的处理并不表明或限制这些处理的时间顺序。另外，也易于理解，这些处理可以是例如在多个模块中同步或异步执行的。
本领域技术人员在考虑说明书及实践这里发明的发明后，将容易想到本公开的其他实施例。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未发明的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由权利要求指出。

Claims (18)

  1. 一种图像显示方法，其特征在于，包括：
    通过第一执行主体获取原始视点图，并对所述原始视点图进行处理，得到第一待显示图像；
    通过所述第一执行主体将所述第一待显示图像发送至第二执行主体；
    通过所述第二执行主体控制显示面板对所述第一待显示图像进行显示。
  2. 根据权利要求1所述的图像显示方法，其特征在于，所述第一执行主体包括设置在主机中的处理器，所述第二执行主体包括设置在显示装置中的现场可编程门阵列。
  3. 根据权利要求1所述的图像显示方法，其特征在于，所述第一执行主体包括设置在显示装置中的IC，所述第二执行主体包括所述IC或者设置在显示装置中的现场可编程门阵列。
  4. 根据权利要求1所述的图像显示方法，其特征在于，对所述原始视点图进行处理，得到第一待显示图像，包括：
    在确定同一像素岛中包括的当前视点的视点数量满足预设条件时，对该像素岛中的原始视点图进行平铺，得到视点平铺图；
    将所述视点平铺图由原始图像架构转换为像素岛架构，并确定所述视点平铺图的视线区域；
    根据所述视线区域所具有的第一像素行数以及时钟周期，计算所述像素岛架构中所需插入的虚拟像素行的第二像素行数；
    在所述像素岛架构中插入与所述第二像素行数对应的虚拟像素行，得到目标图像数据，并对所述目标图像数据进行格式转换得到第一待显示图像。
  5. 根据权利要求4所述的图像显示方法，其特征在于，所述图像显示方法还包括：
    计算同一像素岛内包括的当前视点的视点数量，并判断所述视点数量与该像素岛内包括的数据分时复用的通路数量是否满足第一预设数量关系；
    若所述视点数量与所述通路数量满足所述第一预设数量关系，则确定所述当前视点的视点数量满足所述预设条件；
    若所述视点数量与所述通路数量不满足所述第一预设数量关系，则确定所述当前视点的视点数量不满足所述预设条件。
  6. 根据权利要求5所述的图像显示方法，其特征在于，所述图像显示方法还包括：
    若所述视点数量与所述通路数量不满足所述第一预设数量关系，则根据视点数量以及通路数量，计算所需增加的虚拟视点的数量；
    在所述当前视点中增加与虚拟视点的数量相等的虚拟视点，直至增加后的视点数量与所述通路数量满足所述第一预设数量关系。
  7. 根据权利要求4所述的图像显示方法，其特征在于，将所述视点平铺图由原始图 像架构转换为像素岛架构，包括：
    将所述视点平铺图由原始的横向RGB图像架构转换为纵向RGB的像素岛架构。
  8. 根据权利要求4所述的图像显示方法，其特征在于，根据所述视线区域所具有的第一像素行数以及时钟周期，计算所述像素岛架构中所需插入的虚拟像素行的第二像素行数，包括：
    判断所述视线区域所具有的第一像素行数以及时钟周期之间是否满足第二预设数量关系；
    若满足所述第二预设数量关系，则所述像素岛架构中所需插入的虚拟像素行的第二像素行数为零；
    若不满足所述第二预设数量关系，则根据所述第一像素行数以及时钟周期，计算所述虚拟像素行的第二像素行数。
  9. 根据权利要求8所述的图像显示方法，其特征在于，判断所述视线区域所具有的第一像素行数以及时钟周期之间是否满足第二预设数量关系，包括：
    确定所述视线区域所具有的GOA时序的开启方式，并根据所述开启方式确定所述视线区域所具有的第一像素行数以及时钟周期；其中，所述视线区域包括人眼注视区域和/或非人眼注视区域；
    判断所述第一像素行数以及时钟周期之间是否满足第二预设数量关系；其中，当所述视线区域为人眼注视区域时，所述GOA时序的开启方式包括第一开启方式或第二开启方式；当所述视线区域为非人眼注视区域时，所述GOA时序的开启方式包括第二开启方式或第三开启方式；
    其中，所述第一开启方式为GOA逐行开，所述第二开启方式为GOA两行同开，所述第三开启方式为GOA四行同开。
  10. 根据权利要求8所述的图像显示方法，其特征在于，对所述目标图像数据进行格式转换得到第一待显示图像，包括：
    根据所述视线区域所具有的GOA时序的开启方式，对所述目标图像数据进行格式转换，得到第一待显示图像；
    其中，当所述开启方式为第一开启方式时，将所述目标图像数据转换为具有第一预设数据格式的第一待显示图像；
    当所述开启方式为第二开启方式时，将所述目标图像数据转换为具有第二预设数据格式的第一待显示图像；
    当所述开启方式为第三开启方式时，将所述目标图像数据转换为具有第三预设数据格式的第一待显示图像。
  11. 根据权利要求4所述的图像显示方法，其特征在于，在对所述目标图像数据进行格式转换得到第一待显示图像之后，所述图像显示方法还包括：
    判断显示面板中的源驱动芯片中包括第一薄膜场效应晶体管的第一晶体管类型，是否 与显示面板中的第二薄膜场效应晶体管的第一晶体管类型一致；
    若所述第一晶体管类型与第二晶体管类型不一致，则对所述第一待显示图像进行灰阶反向处理，得到第二待显示图像。
  12. 根据权利要求11所述的图像显示方法，其特征在于，对所述第一待显示图像进行灰阶反向处理，得到第二待显示图像，包括：
    判断源驱动芯片中是否包括闲置通道；
    在确定包括所述闲置通道时，在所述第一待显示图像中插入虚拟像素列，并对插入虚拟像素列以后的第一待显示图像进行灰阶反向处理，得到第二待显示图像；其中，所述虚拟像素列在所述第一待显示图像中的插入位置，与所述闲置通道在所述源驱动芯片中的位置对应；
    在确定不包括所述闲置通道时，对所述第一待显示图像进行灰阶反向处理，得到第二待显示图像。
  13. 根据权利要求12所述的图像显示方法，其特征在，所述图像显示方法还包括：
    根据所述显示面板的所包括的像素岛的数量、每一个像素岛中所包括的当前视点的视点数量以及所述显示面板的横向分辨率，计算驱动所述显示面板所需要的源驱动芯片的数量；
    根据所述源驱动芯片的芯片通道数量以及源驱动芯片的数量，计算所述显示面板的总通道数，并根据所述总通道数以及所述横向分辨率，计算需要在所述源驱动芯片中插入的闲置通道的数量；
    为所述闲置通道设置插入规则，以使得根据所述插入规则将所述闲置通道插入至对应的源驱动芯片中。
  14. 根据权利要求13所述图像显示方法，其特征在于，所述插入规则包括以下规则中的至少一项：
    每一颗被插入闲置通道的源驱动芯片，是以第一预设放置方式进行放置的；
    所述闲置通道是以第二预设放置方式放置在所述源驱动芯片中的；
    每一颗被插入闲置通道的源驱动芯片，是以第三预设方式放置在显示面板的对应位置中的。
  15. 根据权利要求12所述的图像显示方法，其特征在于，所述图像显示方法还包括：
    在所述第一待显示图像或第二待显示图像中添加信息行；其中，所述信息行用于表征高清区位置。
  16. 一种图像显示系统，其特征在，包括：
    第一执行主体，用于获取原始视点图，并对所述原始视点图进行处理，得到第一待显示图像；以及将所述第一待显示图像发送至第二执行主体；
    第二执行主体，与所述第一执行主体通信连接，用于控制显示面板对所述第一待显示图像进行显示。
  17. 一种计算机可读存储介质，其上存储有计算机程序，其特征在于，所述计算机程序被处理器执行时实现权利要求1-15任一项所述的图像显示方法。
  18. 一种电子设备，其特征在于，包括：
    处理器；以及
    存储器，用于存储所述处理器的可执行指令；
    其中，所述处理器配置为经由执行所述可执行指令来执行权利要求1-15任一项所述的图像显示方法。
PCT/CN2022/090044 2022-04-28 2022-04-28 图像显示方法及系统、计算机可读存储介质及电子设备 WO2023206282A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN202280001015.2A CN117581532A (zh) 2022-04-28 2022-04-28 图像显示方法及系统、计算机可读存储介质及电子设备
PCT/CN2022/090044 WO2023206282A1 (zh) 2022-04-28 2022-04-28 图像显示方法及系统、计算机可读存储介质及电子设备

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2022/090044 WO2023206282A1 (zh) 2022-04-28 2022-04-28 图像显示方法及系统、计算机可读存储介质及电子设备

Publications (1)

Publication Number Publication Date
WO2023206282A1 true WO2023206282A1 (zh) 2023-11-02

Family

ID=88516816

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/090044 WO2023206282A1 (zh) 2022-04-28 2022-04-28 图像显示方法及系统、计算机可读存储介质及电子设备

Country Status (2)

Country Link
CN (1) CN117581532A (zh)
WO (1) WO2023206282A1 (zh)

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106851240A (zh) * 2016-12-26 2017-06-13 网易（杭州）网络有限公司 图像数据处理的方法及装置
CN108833893A (zh) * 2018-05-31 2018-11-16 北京邮电大学 一种基于光场显示的3d图像校正方法
CN109769063A (zh) * 2018-12-25 2019-05-17 努比亚技术有限公司 一种屏幕显示方法、设备及计算机可读存储介质
CN110740309A (zh) * 2019-09-27 2020-01-31 北京字节跳动网络技术有限公司 一种图像显示方法、装置、电子设备及存储介质
CN112584124A (zh) * 2019-09-30 2021-03-30 北京芯海视界三维科技有限公司 实现3d显示的方法及装置、3d显示终端
CN113438418A (zh) * 2021-06-25 2021-09-24 Oppo广东移动通信有限公司 图像处理方法、装置、设备及计算机可读存储介质
US20210364988A1 (en) * 2020-05-21 2021-11-25 Looking Glass Factory, Inc. System and method for holographic image display

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106851240A (zh) * 2016-12-26 2017-06-13 网易（杭州）网络有限公司 图像数据处理的方法及装置
CN108833893A (zh) * 2018-05-31 2018-11-16 北京邮电大学 一种基于光场显示的3d图像校正方法
CN109769063A (zh) * 2018-12-25 2019-05-17 努比亚技术有限公司 一种屏幕显示方法、设备及计算机可读存储介质
CN110740309A (zh) * 2019-09-27 2020-01-31 北京字节跳动网络技术有限公司 一种图像显示方法、装置、电子设备及存储介质
CN112584124A (zh) * 2019-09-30 2021-03-30 北京芯海视界三维科技有限公司 实现3d显示的方法及装置、3d显示终端
US20210364988A1 (en) * 2020-05-21 2021-11-25 Looking Glass Factory, Inc. System and method for holographic image display
CN113438418A (zh) * 2021-06-25 2021-09-24 Oppo广东移动通信有限公司 图像处理方法、装置、设备及计算机可读存储介质

Also Published As

Publication number Publication date
CN117581532A (zh) 2024-02-20

Similar Documents

Publication Publication Date Title
US9786255B2 (en) Dynamic frame repetition in a variable refresh rate system
KR101713177B1 (ko) 가상 디스플레이들에 대한 시스템 및 방법
TWI341978B (en) Connecting graphics adapters for scalable performance
EP3134804B1 (en) Multiple display pipelines driving a divided display
CN107633824B (zh) 显示装置及其控制方法
US10957024B2 (en) Real time tone mapping of high dynamic range image data at time of playback on a lower dynamic range display
WO2016091082A1 (zh) 多屏拼接显示处理方法和设备
US20200145607A1 (en) Image processing system, image display method, display device and storage medium
KR20130138143A (ko) 디스플레이 미러링을 위한 시스템 및 방법
CN112965678A (zh) 一种基于电子墨水屏的显示器、装置、存储介质及方法
KR20130040251A (ko) 디스플레이 활동을 제어하기 위한 기법들
CN112740278B (zh) 用于图形处理的方法及设备
CN105704407A (zh) 一种显示处理装置、设备及方法
US8194065B1 (en) Hardware system and method for changing a display refresh rate
US9087473B1 (en) System, method, and computer program product for changing a display refresh rate in an active period
US10068549B2 (en) Cursor handling in a variable refresh rate environment
WO2023206282A1 (zh) 图像显示方法及系统、计算机可读存储介质及电子设备
US20120169745A1 (en) Method and System for Selecting Data for Display in a Plurality of Displays
CN110347391B (zh) 用于汽车全液晶仪表的图像叠加显示方法
WO2022022093A1 (zh) 数据处理方法、数据处理装置、显示装置
CN111768732B (zh) 一种显示驱动装置、显示装置和显示驱动方法
US20210286461A1 (en) Method and device for adjusting display of multimedia blackboard, medium and electronic device
KR102315969B1 (ko) 영상 처리 방법 및 이를 이용한 표시장치
US6943783B1 (en) LCD controller which supports a no-scaling image without a frame buffer
CN101714072B (zh) 用于处理表示可视信息的像素平面的方法和装置

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 202280001015.2

Country of ref document: CN

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22939132

Country of ref document: EP

Kind code of ref document: A1