WO2023206101A1 - 信号处理方法、显示装置、电子设备和可读存储介质 - Google Patents

信号处理方法、显示装置、电子设备和可读存储介质 Download PDF

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Publication number
WO2023206101A1
WO2023206101A1 PCT/CN2022/089394 CN2022089394W WO2023206101A1 WO 2023206101 A1 WO2023206101 A1 WO 2023206101A1 CN 2022089394 W CN2022089394 W CN 2022089394W WO 2023206101 A1 WO2023206101 A1 WO 2023206101A1
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Prior art keywords
data
row
signal
column
pixel
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PCT/CN2022/089394
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English (en)
French (fr)
Inventor
刘冬
廖燕平
邵喜斌
陈东川
李承珉
苏国火
张银龙
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京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Application filed by 京东方科技集团股份有限公司, 北京京东方显示技术有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202280000905.1A priority Critical patent/CN117337461A/zh
Priority to PCT/CN2022/089394 priority patent/WO2023206101A1/zh
Publication of WO2023206101A1 publication Critical patent/WO2023206101A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems

Definitions

  • Embodiments of the present disclosure relate to a signal processing method, a display device, an electronic device, and a computer-readable storage medium.
  • display devices with display panels as display ports have been increasingly integrated into people's work and life.
  • Commonly used display devices include liquid crystal display devices and OLED (Organic Light-Emitting Diode) display devices. wait.
  • the display device includes a display substrate.
  • the display substrate includes M rows and N columns of pixel units arranged in an array.
  • the signal processing method includes: obtaining Display data of a frame of image to be displayed, wherein the display data includes pixel data of P rows and Q columns arranged in an array; corresponding to the P rows of pixel data, P row gate scanning signals are generated; when P is less than M , based on the P row gate scan signal, an M-P row supplementary gate scan signal is generated, wherein the P row gate scan signal and the M-P row supplementary gate scan signal form an M row gate scan signal; respectively, using The M rows of gate scanning signals drive the M rows of pixel units; where P, Q, M and N are all positive integers.
  • generating M-P row supplementary gate scan signals based on the P row gate scan signals includes: in the The A-1 row supplementary gate scan signal is generated between every two adjacent rows of P row gate scan signals; the A-1 row gate scan signal is generated on at least one side of the P row gate scan signal.
  • Polar scan signal where A is an integer greater than 1.
  • the P row gate scan signal includes the adjacent i-th row gate scan signal and the i+1-th row gate scan signal; based on the P row gate scan signals, generating M-P row supplementary gate scan signals, including: based on the timing of the i-th row gate scan signal and the i+1-th row gate scan signal, generating a gate scan signal located in the i-th row
  • the supplementary gate scan signal of row B between the polar scan signal and the gate scan signal of the i+1th row; wherein, the rising edges of the supplementary gate scan signal of row B are all located at the i-th row in time sequence.
  • the falling edges of the B row supplementary gate scan signal are all located in the i-th row gate scan signal in timing.
  • i is a positive integer less than P
  • B is a positive integer less than or equal to M-P.
  • the rising edge of the i-th row gate scan signal, the rising edge of the B-row supplementary gate scan signal and the i+1-th row gate scan signal is sequentially delayed in time sequence; the falling edge of the i-th row gate scan signal, the falling edge of the B-row supplementary gate scan signal and the i+1-th row gate scan signal The falling edges are delayed in sequence.
  • a signal located on the i-th row gate scan signal is generated.
  • the supplementary gate scan signal of line B between the scan signal and the gate scan signal of the i+1th row includes: comparing the phase of the gate scan signal of the i+1th row and the gate scan signal of the i+1th row.
  • the phase of the scanning signal is interpolated to obtain the phase of the B row supplementary gate scanning signal.
  • the time difference between the rising edge and the falling edge of each row of supplementary gate scanning signals in the B rows is different from the i-th row.
  • the time difference between the rising and falling edges of the gate scan signal is the same.
  • each pixel unit includes S sub-pixels, and the S sub-pixels located in the same pixel unit are arranged along the row direction, and the N column pixel units include N*S column sub-pixels. Pixel; sub-pixels located in the same column have the same polarity during the display time of one frame of the image to be displayed, where S is a positive integer.
  • the signal processing method provided by at least one embodiment of the present disclosure further includes: when P is equal to M, using the P rows of gate scanning signals to drive the M rows of pixel units respectively.
  • the display device further includes N data signal lines respectively connected to the N columns of pixel units; the signal processing method further includes: based on the P rows of pixel data generate P rows of analog data signals, wherein the P rows of analog data signals include the i-th row of analog data signals, and the i-th row of analog data signals include Q analog data signals; from using the i-th row of analog data signals In the period from when the row gate scan signal drives the data write switch of the corresponding row pixel unit to turn on to when the i+1th row gate scan signal is used to drive the data write switch of the corresponding row pixel unit to turn on, the The Q analog data signals of the i-th row of analog data signals are respectively input to the Q data signal lines among the N data signal lines.
  • each of the pixel units includes S sub-pixels, the N columns of pixel units include N*S columns of sub-pixels, and the N data signal lines include N*S sub-data signal lines connected to the N*S columns of sub-pixels; each of the analog data signals includes S sub-analog data signals, and the Q analog data signals include Q*S sub-analog data signals;
  • the Q analog data signals of the i-th row of analog data signals are respectively input into the Q data signal lines among the N data signal lines, including: inputting the Q*S sub-analog data signals into the N*S sub-data respectively.
  • the Q*S strip data signal line in the signal line is
  • the signal processing method provided in at least one embodiment of the present disclosure further includes: when Q is less than N, perform a data supplement operation, wherein the data supplement operation includes: based on the Q column pixel data, generate N-Q columns Supplementing pixel data, the Q column pixel data and the N-Q column supplementary pixel data form N columns of pixel data; based on the N columns of pixel data, generate N columns of analog data signals; input the N columns of analog data signals to each Describe N columns of pixel units.
  • generating N-Q column supplementary pixel data based on the Q column pixel data includes: in the Q column pixel data Between each two adjacent columns of pixel data in , C-1 column of supplementary pixel data is generated; C-1 column of supplementary pixel data is generated on at least one side of the Q column of pixel data; where C is an integer greater than 1.
  • the Q column pixel data includes adjacent j-th column pixel data and j+1-th column pixel data; based on the Q column pixel data, N-Q Column supplementary pixel data includes: performing an interpolation operation on the j-th column pixel data and the j+1-th column pixel data to generate a column between the j-th column pixel data and the j+1-th column pixel data
  • the D column of Supplements the pixel data where j is a positive integer less than Q, and D is a positive integer less than or equal to N-Q.
  • the signal processing method provided by at least one embodiment of the present disclosure further includes: when Q is equal to N, based on the Q column pixel data, respectively generate Q column analog data signals, wherein the Q column analog data signals are respectively Used to input the N columns of pixel units.
  • the signal processing method provided by at least one embodiment of the present disclosure also includes: determining whether the display data of multiple consecutive frames of images to be displayed conforms to the alternating display law, wherein the Q column pixel data of the display data conforming to the alternating display law is in g Cycle among pixel values, and the g pixel values respectively correspond to g brightness characteristics; if so, divide the multiple frames of images to be displayed into multiple image groups, each image group including adjacent g frames of images to be displayed.
  • At least one embodiment of the present disclosure also provides a display device, including a display substrate and a timing controller.
  • the display substrate includes M rows and N columns of pixel units arranged in an array;
  • the timing controller includes a data receiving module and a gate signal generating module; data
  • the receiving module is configured to obtain display data of a frame of an image to be displayed, where the display data includes pixel data of P rows and Q columns arranged in an array.
  • the gate signal generation module is configured to: corresponding to P rows of pixel data, generate P rows of gate scan signals; when P is less than M, perform a gate signal supplement operation, where the gate signal supplement operation includes: based on P rows of gate pole scan signal to generate an M-P row supplementary gate scan signal, wherein the P row gate scan signal and the M-P row supplementary gate scan signal form an M-row gate scan signal, so as to respectively drive M rows using the M-row gate scan signal.
  • Row pixel unit; P, Q, M and N are all positive integers.
  • the display device further includes a source driver chip.
  • the source driver chip communicates with M rows and N columns of pixels through a plurality of data signal lines extending in a second direction that intersects the first direction.
  • the units are connected to provide analog data signals to the M rows and N columns of pixel units, where the source driver chip is configured to: perform a data supplement operation when Q is less than N, where the data supplement operation includes: based on the Q column pixel data, Generate N-Q columns of supplementary pixel data, Q column pixel data and N-Q columns of supplementary pixel data to form N columns of pixel data; generate N columns of analog data signals based on the formed N columns of pixel data; input the N columns of analog data signals to N columns of pixel units respectively .
  • the source driver chip includes a cache module, a plurality of operation modules and a plurality of digital-to-analog conversion modules.
  • the cache module is configured to cache display data; the plurality of operation modules are configured to execute data.
  • a supplementary operation is performed to obtain N-Q columns of supplementary pixel data; multiple digital-to-analog conversion modules are configured to convert the N columns of pixel data into N columns of analog data signals.
  • the timing controller further includes a mode control module.
  • the mode control module is configured to receive a mode instruction and send a signal to the gate signal generation module and/or the source driver chip based on the mode instruction.
  • a control signal to control whether the gate signal generation module performs a gate signal supplement operation and/or to control whether the source driver chip performs a data supplement operation.
  • the source driver chip also includes a plurality of two-way switches and a mode switching module.
  • Each two-way switch includes an input terminal and two output terminals, and the input terminal is connected to the cache module. , used to receive a column of pixel data, wherein one output terminal is connected to at least one of a plurality of digital-to-analog conversion modules, and the other output terminal is connected to at least one of a plurality of operation modules; the mode switching module is configured to be based on the control sent by the mode control module The signal controls the two-pass switch to output a column of pixel data to one of two outputs.
  • the timing controller further includes an image recognition module, and the image recognition module is configured to: identify whether the display data of multiple consecutive frames of images to be displayed conforms to the alternating display rule, wherein: conforming to the alternating display
  • the Q column pixel data showing regular display data circulates between g pixel values, and the g pixel values correspond to g brightness characteristics respectively; if so, the multi-frame image to be displayed is divided into multiple picture groups, each picture group includes The adjacent g frames of images to be displayed are executed for each picture group: if the current frame of the image to be displayed is the k-th frame of the picture group to be displayed, the Q column pixel data of the k-th frame of the image to be displayed are transformed into The k-th pixel value among the g pixel values; output the transformed Q column pixel data to the source driver chip; the source driver chip is also configured to: perform a data supplement operation for the transformed Q column pixel data; based on the data supplement The pixel
  • a brightness characteristic wherein, when k is a positive integer greater than 1, the remaining column pixel units except the k+n*gth column pixel unit are displayed as the previous frame of the k-th frame image to be displayed.
  • Corresponding brightness characteristics when k is equal to 1, the pixel units in the remaining columns except the k+n*g column pixel unit are not displayed, where n takes all integers from 0 to [Q/g-1], g is an integer greater than 1 and less than Q, and k is an integer less than or equal to g.
  • At least one embodiment of the present disclosure provides an electronic device, including the display device provided by any embodiment of the present disclosure.
  • At least one embodiment of the present disclosure provides an electronic device including a processor; a memory including one or more computer program modules; wherein the one or more computer program modules are stored in the memory and configured to The processor executes, and the one or more computer program modules include instructions for implementing the signal processing method provided by any embodiment of the present disclosure.
  • At least one embodiment of the present disclosure provides a computer-readable storage medium for storing non-transitory computer-readable instructions.
  • the non-transitory computer-readable instructions are executed by a computer, the methods provided by any embodiment of the present disclosure can be implemented. Signal processing methods.
  • Figure 1 is a schematic diagram of a display device provided by at least one embodiment of the present disclosure
  • Figure 2 is a schematic diagram of the arrangement of sub-pixels provided by at least one embodiment of the present disclosure
  • Figure 3 is a schematic diagram of a timing controller provided by at least one embodiment of the present disclosure.
  • Figure 4 is a schematic diagram of another display device provided by at least one embodiment of the present disclosure.
  • Figure 5 is a schematic diagram of a signal processing method provided by at least one embodiment of the present disclosure.
  • Figure 6 is a timing diagram of a gate scan signal provided by at least one embodiment of the present disclosure.
  • Figure 7 is a schematic diagram of a display process provided by at least one embodiment of the present disclosure.
  • Figure 8 is a schematic diagram of another display process provided by at least one embodiment of the present disclosure.
  • Figure 9 is a schematic diagram of a gray scale change provided by at least one embodiment of the present disclosure.
  • Figure 10 is a schematic diagram of another display process provided by at least one embodiment of the present disclosure.
  • Figure 11 is a schematic diagram of a source driver provided by at least one embodiment of the present disclosure.
  • Figure 12 is a schematic diagram of input pixel data and output pixel data in a source driver provided by at least one embodiment of the present disclosure
  • Figure 13 is a schematic diagram of a resolution control module provided by at least one embodiment of the present disclosure.
  • Figure 14 is a schematic diagram of a gray scale change provided by at least one embodiment of the present disclosure.
  • Figure 15 is a schematic diagram of input pixel data and output pixel data in another source driver provided by at least one embodiment of the present disclosure
  • Figure 16 is a schematic diagram of input pixel data and output pixel data in another source driver provided by at least one embodiment of the present disclosure
  • FIG. 17 is a schematic diagram of another timing controller provided by at least one embodiment of the present disclosure.
  • Figure 18 is a schematic diagram of another source driver chip provided by at least one embodiment of the present disclosure.
  • Figure 19 is a schematic diagram of another resolution conversion module provided by at least one embodiment of the present disclosure.
  • Figure 20 is a schematic diagram of an image to be displayed that conforms to the alternating display rule provided by at least one embodiment of the present disclosure
  • Figure 21 is a schematic diagram of another display device provided by at least one embodiment of the present disclosure.
  • Figure 22 is a schematic diagram of another resolution conversion module provided by at least one embodiment of the present disclosure.
  • Figure 23 is a schematic diagram of a display screen provided by at least one embodiment of the present disclosure.
  • Figure 24 is a schematic diagram of another display screen provided by at least one embodiment of the present disclosure.
  • Figure 25 is a schematic block diagram of an electronic device provided by some embodiments of the present disclosure.
  • Figure 26 is a schematic block diagram of another electronic device provided by some embodiments of the present disclosure.
  • Figure 27 is a schematic diagram of a storage medium provided by some embodiments of the present disclosure.
  • FIG. 1 is a schematic diagram of a display device provided by at least one embodiment of the present disclosure. As shown in FIG. 1 , the display device includes a display panel 110 , a timing controller 120 , a gate driver 130 and a source driver 140 .
  • the display panel 110 includes multiple rows and columns of sub-pixels Pxij arranged in an array.
  • the display substrate 110 includes M rows and N columns of pixel units arranged in an array.
  • the pixel unit is the smallest complete display unit of the display panel and may be composed of several sub-pixels Pxij.
  • each pixel unit includes S sub-pixels (S is a positive integer), and the S sub-pixels located in the same pixel unit can be arranged along the row direction.
  • the N columns of pixel units include N*S columns of sub-pixels.
  • FIG. 2 is a schematic diagram of the arrangement of sub-pixels provided by at least one embodiment of the present disclosure.
  • each pixel unit includes, for example, three sub-pixels arranged along the row direction, namely sub-pixel 1, sub-pixel 2 and sub-pixel 3. These three sub-pixels are, for example, R (red), G (green). ), B (blue), the display panel includes M rows and 3N columns of sub-pixels. Three consecutive sub-pixels in each row form a pixel unit. For example, the three sub-pixels connected to DL1 ⁇ DL3 in the first row form pixel unit 1, and the three sub-pixels connected to DL4 ⁇ DL6 in the first row form pixel unit 2.
  • Three connected sub-pixels form a pixel unit N.
  • the number and arrangement of sub-pixels included in a pixel unit can also be adopted in other ways.
  • a pixel unit including three sub-pixels and the three sub-pixels in the same pixel unit being arranged along the row direction are taken as an example for illustration.
  • the display panel further includes a plurality of gate scanning signal lines (GL1 ⁇ GLM) extending in a first direction and a plurality of data signal lines (GL1 ⁇ GLM) extending in a second direction crossing the first direction.
  • DL1 ⁇ DLN*S for example, the first direction is the row direction, the second direction is the column direction, and the first direction is perpendicular to the second direction.
  • Multiple gate scan signal lines (GL1 ⁇ GLM) are connected to M rows of pixel units respectively.
  • One gate scan signal line can be connected to each sub-pixel in a row.
  • the gate scan signal transmitted by the gate scan signal line is used to drive the corresponding The switching devices of all sub-pixels in the row are turned on.
  • Multiple data signal lines are connected to N*S columns of sub-pixels respectively.
  • One data signal line is connected to each sub-pixel in a column.
  • the switching device of the sub-pixel When the switching device of the sub-pixel is turned on, the data transmitted by the data signal line
  • the signal can be written into the sub-pixels, and the data signal is a signal for adjusting the gray scale displayed by the sub-pixel, so that each sub-pixel of the display panel displays different gray scales.
  • GL1 ⁇ GLM are used to represent both the gate scanning signal lines and the gate scanning signals transmitted on the corresponding gate scanning signal lines
  • DL1 ⁇ DLN*S are used to represent both the data signal lines and the gate scanning signals transmitted on the corresponding gate scanning signal lines. Used to represent the data signal transmitted on the corresponding data signal line.
  • Each sub-pixel is connected to a gate scanning signal line and a data signal line, and is controlled by the gate scanning signal line and data signal line to achieve gray scale changes.
  • one row of sub-pixels in the display panel can be turned on at a time, and the data driver 140 writes the data signal of the corresponding row into the turned-on sub-pixels of the row, so that the row of sub-pixels presents the corresponding brightness. Opening and writing line by line in this way allows the display panel to present the image to be displayed according to the corresponding display brightness.
  • the timing controller 120 is a board card that implements timing conversion functions. It may be an independent component or may be included in a front-end video and other signal processing system.
  • FIG. 3 is a schematic diagram of a timing controller provided by at least one embodiment of the present disclosure. As shown in FIG. 3 , the timing controller 120 includes a data receiving module 121 , a gate signal generating module 122 and a data signal transmitting module 123 .
  • the data receiving module 121 is used to receive the display data of the image to be displayed.
  • the gate signal generating module 122 generates a one-to-one corresponding gate scanning signal according to the vertical resolution of the display data (ie, the number of rows of the display data) and sends it to the gate.
  • the gate driver 130 is configured to transmit the gate scanning signal to the display panel through a plurality of cascaded shift register units in the gate driver 130 .
  • the data signal sending module 123 sends the display data to the source driver.
  • the received and sent pixel data are in one-to-one correspondence, which is called Point to Point (P to P), that is, the number of columns for receiving data is the same as the number of columns for sending data. , the number of rows of received data is the same as the number of rows of sent data.
  • the source driver processes the data signal and sends it to the display panel.
  • the timing controller is also called a timing control board.
  • the gate signal generation module also becomes the gate line signal generation module, and the gate scanning signal is also called a gate line signal.
  • the source driver 140 may include a source driver IC (Integrated Circuit Chip), which is responsible for converting the received digital data signal into an analog data signal that can drive the pixel display, and its output channels correspond to the columns of the display panel one-to-one.
  • the digital data signal refers to the data signal that the timing control board divides the pixel data signal of each row equally and sends it to the source driver IC through the data signal sending module. It is a binary digital signal; the analog data signal is the source driver IC that sends the digital data to the source driver IC.
  • the signal is converted by combining the analog voltage and sent to each data line of the display panel, which is an analog voltage signal.
  • the source driver 140 is also referred to as a source driver IC or a source driver chip for short.
  • FIG. 4 is a schematic diagram of another display device provided by at least one embodiment of the present disclosure.
  • the gate driver can be integrated into the display panel, and the gate scan signal sent by the timing controller can be sent to the display panel through the source driver. Row driven sub-pixels.
  • the display data signal sent by the timing controller is sent to the source driver, which processes the display data signal and sends it to each column of sub-pixels through the data signal line.
  • the data volume of 4K2K240Hz is one percent higher than that of 4K2K 120Hz. times, the data volume of 8K4K 120Hz is four times higher than that of 4K2K 120Hz.
  • the significantly increased data volume puts forward higher requirements on the processing speed of the system chip that generates display signals.
  • the display panel includes M rows and N columns of display units, and the physical resolution is N*M. There are N pixels in each row, which is called horizontal resolution; there are M pixels in each column, which is called vertical resolution.
  • the resolution of the image to be displayed needs to match the physical resolution of the display panel, that is, the number of rows and the number of columns correspond one to one.
  • the display signal resolution does not match the physical resolution of the display panel, for example, the horizontal resolution is only half of the panel resolution, the display panel will be unable to display or the display effect will be poor.
  • At least one embodiment of the present disclosure provides a signal processing method, a display device, an electronic device, and a computer-readable storage medium.
  • the signal processing method is used in a display device.
  • the display device includes a display substrate.
  • the display substrate includes M rows and N columns of pixel units arranged in an array.
  • the signal processing method includes: acquiring display data of a frame of an image to be displayed, wherein the display data includes The pixel data of P rows and Q columns arranged in the array; corresponding to the P row pixel data, the P row gate scan signal is generated; when P is less than M, based on the P row gate scan signal, the M-P row supplementary gate scan signal is generated, Among them, P row gate scan signals and M-P row supplementary gate scan signals form M row gate scan signals; the formed M row gate scan signals are used to drive M rows of pixel units respectively, and P, Q, M and N are all positive integer.
  • the signal processing method of the embodiment of the present disclosure expands the total number of rows of the gate scanning signal to The display panel has the same number of rows of pixel units. Based on this method, when the vertical resolution of the image to be displayed is smaller than the vertical resolution of the display panel, all rows of pixel units of the display panel can be displayed, thereby expanding the vertical resolution and improving the display effect.
  • FIG. 5 is a schematic diagram of a signal processing method provided by at least one embodiment of the present disclosure. This signal processing method is used, for example, in the above-mentioned display device. As shown in FIG. 5 , the signal processing method includes steps S210 to S240.
  • Step S210 Obtain display data of a frame of the image to be displayed.
  • the display data includes pixel data of P rows and Q columns arranged in an array.
  • Step S220 Corresponding to P rows of pixel data, generate P rows of gate scanning signals.
  • Step S230 When P is less than M, generate M-P row supplementary gate scan signals based on P-row gate scan signals, and the P-row gate scan signals and M-P row supplementary gate scan signals form M-row gate scan signals.
  • Step S240 Use the formed M rows of gate scanning signals to drive M rows of pixel units respectively.
  • P, Q, M and N are all positive integers, P is less than or equal to M, and Q is less than or equal to N.
  • the display panel includes M rows and N columns of pixel units, each pixel unit includes S sub-pixels (S is a positive integer) arranged along the row direction, and the N column pixel units include N *S columns of sub-pixels, that is, the display panel includes M rows and N*S columns of sub-pixels.
  • the M rows of pixel units in the following content can also be understood as M rows of sub-pixels.
  • sub-pixels located in the same column have the same polarity during the display time of one frame of the image to be displayed, either positive or negative.
  • the polarity of the sub-pixel here refers to the polarity of the data signal applied to the sub-pixel.
  • the gate signal generation module generates gate scanning signals corresponding to the number of rows P according to the number of rows of the image to be displayed.
  • step S230 it can be determined whether the number of rows P of the image to be displayed is less than the number M of rows of pixel units in the display panel (ie, the number of rows of sub-pixels M). If the number of rows P of the image to be displayed is smaller than the number of rows of pixel units M, number M, then M-P row supplementary gate scan signals are generated according to the generated P row gate scan signals to supplement the M row gate scan signals.
  • 900 rows of gate scanning signals are first generated based on 900 rows of pixel data, and then 900 rows of gate scanning signals are generated based on the 900 rows of pixel data.
  • the scan signal generates 300 lines of supplementary gate scan signals to supplement the 1200 lines of gate scan signals.
  • at least part of the M-P row supplementary gate scan signals can be interspersed between the P row gate scan signals. That is to say, certain two adjacent rows of the P row gate scan signals can be interspersed.
  • the supplementary gate scan signal may be generated between only part of the rows in the P row gate scan signal; in another manner, the supplementary gate scan signal may also be generated between each phase in the P row gate scan signal.
  • the supplementary gate scan signal is generated between two adjacent rows; in another way, the supplementary gate scan signal can also be generated on one or both sides of the P row gate scan signal; or it can be any of the above three ways. combination.
  • the signal processing method of the embodiment of the present disclosure expands the total number of rows of the gate scanning signal to The display panel has the same number of rows of pixel units. Based on this method, when the vertical resolution of the image to be displayed is smaller than the vertical resolution of the display panel, all rows of pixel units of the display panel can be displayed, thereby expanding the vertical resolution and improving the display effect.
  • the turn-on period in the timing of the supplementary gate scan signal for each row overlaps with the turn-on period in the timing of at least one row of gate scan signals in the P rows of gate scan signals.
  • the turn-on period of the supplementary gate scan signal of each row may overlap with the turn-on period of the nearest row of gate scan signals among the P rows of gate scan signals.
  • FIG. 6 is a timing diagram of a gate scanning signal provided by at least one embodiment of the present disclosure.
  • the P row gate scanning signal includes two adjacent rows of gate scanning signals GL1' and GL2'.
  • the turn-on levels of GL1' and GL2' are high level, and the turn-on levels of GL1' and GL2 are high.
  • the turn-on periods of ' are respectively T10 and T20.
  • the gate scanning signal can drive the switching device of the pixel unit of the corresponding row to be in an open state.
  • the row numbers are adjusted (for example, renumbered in sequence), and GL1' and GL2' can be used as the adjusted GL1 and GL3.
  • M rows of gate scanning signals are generated, M rows of pixel units can be turned on row by row.
  • the P row gate scan signal drives the corresponding P row pixel unit (i.e., P row sub-pixel) to turn on, the source driver will transmit the data signal corresponding to the corresponding row to the display panel, so that the P row pixel unit displays.
  • M-P row supplementary gate scan signal since there is an overlap in the turn-on period of the M-P row supplementary gate scan signal and the P-row gate scan signal, during the time period when the P-row gate scan signal drives the corresponding P-row pixel unit to turn on, M-P
  • the row supplementary gate scan signal will drive the remaining M-P row pixel units (ie, M-P row sub-pixels) to be turned on for a period of time. Therefore, the data signal will also be written into the M-P row pixel unit, causing the M-P row pixel unit to display. Therefore, after M rows of pixel units are scanned row by row, all M rows of pixel units can be displayed.
  • the P row gate scan signal includes the adjacent i-th row gate scan signal and the i+1-th row gate scan signal.
  • step S230 includes: based on the timing of the i-th row gate scan signal and the i+1-th row gate scan signal, generate a signal located at the i-th row.
  • the B row supplementary gate scan signal between the row gate scan signal and the i+1th row gate scan signal; the rising edges of the B row supplementary gate scan signal are all located at the i-th row gate scan signal in timing.
  • the falling edge of the B-row supplementary gate scan signal is located between the falling edge of the i-th row gate scan signal and the i+1-th row gate scan signal in timing sequence.
  • i is a positive integer less than P
  • B is a positive integer less than or equal to M-P.
  • the i-th row and i+1-th row refer to signal rows, that is, gate scanning signal rows, which are different from the physical pixel rows of the display panel.
  • the i-th row gate scan signal may also be called the i-th gate scan signal row, and the i+1-th row gate scan signal may also be called the i+1-th gate scan signal row.
  • the "rows" in rows P, M, and B are all gate scan signal rows.
  • the gate scan signals of P rows can also be called P gate scan signal rows, and the gate scan signals of M rows can also be called They are called M gate scanning signal rows, and the B rows of supplementary gate scanning signals may also be called B supplementary gate scanning signals.
  • B is less than or equal to 4, that is, the number of supplementary gate scan signal lines generated between any two adjacent gate scan signal lines in the P rows of gate scan signals is less than or equal to 4.
  • the i-th row gate scan signal is, for example, GL1, and the i+1-th row gate scan signal, for example, is GL3.
  • a supplementary gate scan signal GL2 is generated between GL1 and GL3.
  • the rising edge of GL1 is located between the rising edge of GL1 and the rising edge of GL3, and the falling edge of GL2 is located between the rising edge of GL1 and the falling edge of GL3. That is to say, the turn-on period of GL2 is located on both sides of GL1 and GL3. between opening periods.
  • the second row of pixel units corresponding to GL2 is also in the open state. Therefore, during the time period T11, the display data corresponding to the first row of pixel units It will also be written to the second row of pixel units and displayed as the brightness characteristics corresponding to the first row of pixel units. Moreover, during the first half of the period T21 when the third row of pixel units corresponding to GL3 is in the open state, the second row of pixel units corresponding to GL2 is also in the open state.
  • the third row of pixel units correspond to The display data will also be written to the second row of pixel units and displayed as the corresponding brightness characteristics of the third row of pixel units. Therefore, the second row of pixel units corresponding to GL2 mixes the brightness characteristics of the first row of pixel units and the third row of pixel units, so that the second row of pixel units can be called the gap between the first row of pixel units and the third row of pixel units. Color transition.
  • the rising edge of the i-th row gate scan signal, the rising edge of the B-row supplementary gate scan signal, and the i+1-th row gate scan signal are sequentially delayed in time sequence.
  • the falling edge of the i-th row gate scan signal, the falling edge of the B-row supplementary gate scan signal, and the i+1-th row gate scan signal are sequentially delayed in timing.
  • the rising edge of GL1, the rising edge of GL2 and the rising edge of GL3 are delayed in sequence; the falling edge of GL1, the falling edge of GL2 and the falling edge of GL3 are delayed in sequence. Based on this method, the transition can be made more natural and the pixel colors can be guaranteed to transition evenly.
  • an interpolation operation can be performed on the phase of the i-th row gate scanning signal and the phase of the i+1-th row gate scanning signal to obtain the phase of the B-row supplementary gate scanning signal. For example, interpolate the phases of GL1 and GL3 to obtain the phase of GL2, so that the turn-on period of GL2 is in the middle of the turn-on periods of GL1 and GL3, the time period T11 is half of T10, and the time period T21 is half of T20, so that The transition between the first row of pixel units, the second row of pixel units, and the third row of pixel units is more natural.
  • the above description only takes the generation of a row of supplementary gate scan signals between the i-th row gate scan signal and the i+1-th row gate scan signal as an example.
  • the disclosure is not limited thereto.
  • the phase of the supplementary gate scanning signal can also be obtained by interpolation operation.
  • the time difference between the rising edge and the falling edge of the supplementary gate scanning signal of each row in the B row supplementary gate scanning signal is the same as the time difference between the rising edge and the falling edge of the i-th row gate scanning signal.
  • the time difference T10 between the rising edge and falling edge of GL1 the time difference T11+T21 between the rising edge and falling edge of GL2, and the time difference T20 between the rising edge and falling edge of GL3 are all the same.
  • FIG. 7 is a schematic diagram of a display process provided by at least one embodiment of the present disclosure.
  • FIG. 8 is a schematic diagram of another display process provided by at least one embodiment of the present disclosure.
  • Figure 7 shows the situation where the vertical resolution M of the display panel is the same as the vertical resolution P of the display data of the image to be displayed.
  • Figure 8 shows that the vertical resolution M of the display panel is the vertical resolution P of the display data of the image to be displayed. twice the situation.
  • the embodiments of the present disclosure will be further described in detail below with reference to FIGS. 7 and 8 .
  • P rows of gate scanning signals can be used to drive M rows of pixel units respectively.
  • GL1' ⁇ GLP' are P row gate scanning signals generated based on P rows of display data
  • the analog data signals 1 to M are respectively used to write into pixel units in each row, representing the brightness characteristics (eg gray scale) displayed by the data units in each row. For example, the first row of pixel units corresponds to the analog data signal 1.
  • the analog data signal 1 is written into the first row of pixel units, causing the first row of pixels to The unit has a brightness characteristic of 1.
  • the analog data signals 2 ⁇ M are written row by row into the second row of pixel units to the M-th row of pixel units, so that the second row of pixel units to the M-th row of pixel units are opened row by row.
  • the row pixel unit to the Mth row pixel unit have brightness characteristics 2 to M, respectively.
  • step S230 includes: generating A-1 row supplementary gate scan signals between every two adjacent rows of gate scan signals in P rows of gate scan signals; At least one side of the row gate scan signal generates the A-1 row gate scan signal, where A is an integer greater than 1. For example, if the number of rows M of the pixel unit is twice the number of rows P of display data, then one row of supplementary gate scanning signals is generated between every two adjacent rows of the P row gate scanning signal, and the P row gate scanning signal is A line of supplementary gate scan signals is generated on one side of the polar scan signal, for example, a line of supplementary gate scan signals is generated on the upper or lower side.
  • the supplementary gate scanning signal may be generated using the interpolation operation described above.
  • GL1' ⁇ GL(M/2)' are the M/2 row gate scanning signals generated based on the M/2 row display data
  • GL1 ⁇ GLM are the timing controller outputs.
  • the gate scanning signals to the display panel, GL1 to GLM include GL1' to GL(M/2)' and the supplementary gate scanning signals generated according to GL1' to GL(M/2)'.
  • GL1' ⁇ GL(M/2)' can be used as odd lines GL1, GL3, GL5,..., GL(M-1) in the output signal, respectively, and then generate intermediate even numbers between each two adjacent odd lines. rows of supplementary gate scanning signals GL2, GL4, GL6, ..., GL(M-2), and generate one row of supplementary gate scanning signals GLM on the last even-numbered row.
  • the number of rows M of the pixel unit is three times the number P of rows of display data, then two supplementary gate scanning signal rows are generated between every two adjacent rows of P rows of gate scanning signals, and in P Two supplementary gate scan signal lines are generated on one side (upper or lower side) of the row gate scan signal, or one supplementary gate scan signal line can be generated on both sides of the P row gate scan signal.
  • the display device further includes N data signal lines respectively connected to N columns of pixel units.
  • P rows of analog data signals can be generated based on P rows of pixel data respectively.
  • Analog data signals 1 to P are used to write 1 to M rows of pixel units.
  • the analog data signals 1 to P are arranged in the row direction in the figure, but this does not mean that the analog data signals 1 to P are located in one row.
  • the analog data signals 1 to P correspond to pixel units in different rows.
  • P rows of analog data signals include the i-th row of analog data signals (for example, the first row of analog data signals), and the i-th row of analog data signals includes Q analog data signals (each row of analog data signals may include multiple signals, so that corresponding to multiple columns respectively).
  • the multiple analog data signals included in the first row of analog signals are all analog data signals 1.
  • the The Q analog data signals of the i-th row of analog data signals are respectively input to the Q data signal lines among the N data signal lines.
  • Q signals in the first row of analog data signals are respectively input into Q pixel units in the first row, where Q is a positive integer less than or equal to N.
  • each analog data signal includes S sub-analog data signals
  • Q analog data signals include Q*S sub-analog data signals.
  • the Q*S sub-analog data signals can be respectively input to the Q* in the N*S sub-data signal lines.
  • the Q pixel units in the first row include Q*S sub-pixels
  • the Q signals in the first row of analog data signals also include Q*S sub-signals. Therefore, the Q signals in the first row of analog data signals can be The *S sub-signals are respectively written into the Q*S sub-pixels in the first row.
  • the analog data signal 1 is written into the first row of pixel units, so that the first row of pixel units has a brightness characteristic of 1 .
  • the analog data signal 1 can also be written into the pixel units of the second row.
  • the analog data signal 2 is written into the third row pixel unit, so that the third row pixel unit has the brightness characteristic 1.
  • the pixel units of the second row are also turned on. Therefore, the analog data signal 2 can also be written into the pixel units of the second row. As a result, the second row of pixel units can display an alternation of brightness feature 1 and brightness feature 2, presenting a uniform transition.
  • the analog data signals corresponding to the gate lines of the odd rows of the display panel are the data of each row output by the source driver IC in turn.
  • the analog data signals corresponding to the gate lines of the even rows are the superposition of the data of the upper and lower rows for a period of time. That is, the actual charging process of the pixel unit in this row is to first charge the pixel data of the previous row for a period of time, and then charge the pixel data of the next row for a period of time. Therefore, the display is a transition of the pixel data of the upper and lower rows.
  • the display effect is shown in Figure 9.
  • the analog data signal corresponding to line M is the analog data signal of line M-1, which lasts for a period of time and is displayed close to line M-1.
  • FIG. 9 is a schematic diagram of a gray scale change provided by at least one embodiment of the present disclosure.
  • the P row gate scan signals (for example, GL1' ⁇ GL8') are used as the odd row gate scan signals (for example, GL1, GL3,..., GL15) and the even row supplementary gate scan signals ( Examples such as GL2, GL4, ..., GL16).
  • the left column of gray scales for example, represents the brightness characteristics of the 8 rows of pixel units corresponding to GL1' to GL8' before the gate scanning signal is expanded
  • the right column of gray scales for example, represents the GL1 to GL1 after the gate scanning signal is expanded.
  • the brightness characteristics of the 16 rows of pixel units corresponding to GL16 are used as the odd row gate scan signals (for example, GL1, GL3,..., GL15)
  • the even row supplementary gate scan signals Examples such as GL2, GL4, ..., GL16.
  • the left column of gray scales for example, represents the brightness
  • the phase of the even-numbered rows' raster line scanning signal is the interpolation of the phases of the two upper and lower adjacent odd-numbered rows' raster line scanning signals, so that the gray level of the even-numbered row pixel unit is the transition of the gray level of the adjacent odd-numbered row pixel unit, which will not cause color mess.
  • the phase of GL2 is the interpolation of the phases of GL1' (that is, GL1) and GL2' (that is, GL3).
  • the gray level of a row of pixel units corresponding to GL2 is the interpolation of the gray levels of the upper and lower rows of pixel units, which can form a natural and uniform transition. The same applies to other rows, so that the entire expanded display screen presents a better display effect.
  • FIG. 10 is a schematic diagram of another display process provided by at least one embodiment of the present disclosure.
  • the gate scan signal GL1 is generated, and the supplementary gate scan signals GL3, GL5, ..., GL(M-1) of the intermediate odd-numbered rows are generated between every two adjacent even-numbered rows.
  • A-1 row of supplementary gate scan signals can also be generated on both sides of the P row gate scan signal, for example, one row of supplementary gate scan signals can be generated on both sides.
  • the above describes the processing method in which the vertical resolution of the image to be displayed is smaller than the vertical resolution of the display panel.
  • the following describes the processing method in which the horizontal resolution of the image to be displayed is smaller than the horizontal resolution of the display panel.
  • a data supplement operation is performed.
  • the data supplement operation includes: based on the Q column pixel data, generate N-Q column supplementary pixel data, Q column pixel data and N-Q columns Supplement the pixel data to form N columns of pixel data; generate N columns of analog data signals based on the formed N columns of pixel data; input the N columns of analog data signals into N columns of pixel units respectively.
  • the data signal can be supplemented, so that data signals are written to each column of pixel units, thereby improving the horizontal resolution.
  • the pixel signal, the data signal and the pixel data signal all represent signals of pixel data.
  • each pixel unit includes S sub-pixel units arranged along the row direction.
  • Each pixel data can also be understood as a collection of S sub-pixel data.
  • the process of writing one pixel data into a pixel unit can be understood as writing the S sub-pixels.
  • the S sub-pixel data contained in two adjacent columns of pixel data may also be separately interpolated to obtain S sub-pixel data of the supplementary pixel data.
  • At least part of the N-Q columns of supplementary pixel data can be interspersed between the Q columns of pixel data. That is to say, at least one column of supplementary pixel data can be interspersed between two adjacent columns of the Q column of pixel data. .
  • Some columns in the N-Q column supplementary pixel data may also be located on both sides of the Q column pixel data.
  • the supplementary pixel data can be generated between only some columns in the Q column pixel data; in another way, it can also be generated between every two adjacent columns in the Q column pixel data.
  • Supplementary pixel data is generated; in another way, supplementary pixel data can also be generated on one or both sides of the Q column pixel data; or it can be a combination of the above three ways.
  • FIG. 11 is a schematic diagram of a source driver provided by at least one embodiment of the present disclosure.
  • the source driver includes a serial-to-parallel conversion module 141 , a buffer module 142 , a power amplification module 143 , a digital-to-analog conversion module 144 , an analog voltage module 145 and a power amplification module 146 .
  • the serial-to-parallel conversion module 141 is responsible for converting the serial digital data signal sent by the timing control board into a parallel digital data signal and sending it to the buffer module 142 .
  • the buffer module 142 is responsible for storing the parallel digital data signals sent by the serial-to-parallel converter and outputting them to the resolution conversion module 143. Each sub-pixel data corresponds to an output channel.
  • the resolution conversion module 143 is located between the buffer module 142 and the digital-to-analog conversion module 144. Its function is to adjust the ratio of the number of input and output signals, for example, generate supplementary sub-pixel data based on existing sub-pixel data. The conversion action is performed when the signal enters.
  • the digital-to-analog conversion module 144 is completed before, and the resolution conversion module 143 includes, for example, a plurality of operation modules (operators) and related connection lines.
  • the resolution conversion module 143 sends the supplemented pixel data to the digital-to-analog conversion module 144 .
  • the signal sent by the resolution conversion module 143 to the digital-to-analog conversion module 144 is a digital data signal.
  • the digital-to-analog conversion module 144 is responsible for converting the digital data signal combined with the analog voltage sent by the analog voltage module into an analog data signal, and outputs the analog data signal to Power amplifier module 146.
  • the source driver may include multiple digital-to-analog conversion modules. Each sub-pixel data corresponds to a digital-to-analog conversion module, and its input and output channels correspond to the output channels of the buffer module and the input channels of the power amplification module respectively.
  • the power amplification module 146 is responsible for amplifying the output capability of each channel, and its output channels are connected to the display panel data signal lines one by one.
  • the polarity of the analog data signal output by the digital-to-analog conversion module 144 is controlled by a polarity control signal (ie, the polarity control signal in the figure). For example, for a certain frame of image to be displayed, a polarity control signal is provided to enable digital-to-analog conversion.
  • the output voltage of the odd-numbered channels of the module is positive and the output voltage of the even-numbered channels is negative, then the sub-pixels in the odd-numbered columns of the display panel are driven by the positive line voltage, and the even-numbered columns are driven by the negative polarity voltage; in the next frame, the positive and negative polarities of the odd and even columns are carried out. switch.
  • the Q column pixel data includes adjacent j-th column pixel data and j+1-th column pixel data.
  • the interpolation operation can be performed on the pixel data of the jth column and the pixel data of the j+1th column to generate the supplementary pixel data of column D between the pixel data of the jth column and the pixel data of the j+1th column.
  • j is a positive integer less than Q.
  • D is a positive integer less than or equal to N-Q.
  • FIG. 12 is a schematic diagram of input signals and output signals of a resolution conversion module provided by at least one embodiment of the present disclosure.
  • the j-th column pixel data and the j+1-th column pixel data are, for example, the first column of pixel data (for example, represented by the identifier P_1') and the second column of pixel data (for example, in the Q column of pixel data).
  • the identifier P_2' an interpolation operation is performed between P_1' and P_2' to form a column of supplementary pixel data (such as represented by the identifier P_2).
  • P_1' is, for example, P_1
  • P_2' is, for example, P_3.
  • the supplementary pixel data column P_2 is located between P_1 and P_3. Since the pixel data of P_2 is obtained by interpolating P_1 and P_3, the brightness characteristics of the second column of pixel units corresponding to P_2 are the transition between the adjacent first and third column of pixel units, making the picture transition smoother. for nature.
  • the j-th column and the j+1-th column refer to signal columns, that is, pixel data signal columns, which are different from the physical pixel columns of the display panel.
  • the jth column of pixel data can also be called the jth pixel data signal column (or jth pixel data column), and the j+1th column of pixel data can also be called the j+1th pixel data signal column (or jth +1 pixel data column).
  • the "columns" in columns Q, N, and D are all pixel data signal columns.
  • the Q column pixel data can also be called Q pixel data columns
  • the N columns of pixel data can also be called N pixel data columns.
  • D columns of supplementary pixel data may also be called D supplementary pixel data columns.
  • D is less than or equal to 4, that is, the number of supplementary pixel data columns generated between any two adjacent pixel data columns in the Q column of pixel data is less than or equal to 4.
  • the C-1 column of supplementary pixel data is generated, and the C-1 column of supplementary pixel data can be generated on one side or both sides of the Q column of pixel data to supplement the N columns of pixel data, where C is an integer greater than 1.
  • the number of columns N of the pixel unit is twice the number of columns Q of the display data
  • one column of supplementary pixel data can be generated between each two adjacent columns of the Q column pixel data
  • one column of supplementary pixel data can be generated on one side of the Q column pixel data. (e.g. left or right) generates a column of supplementary pixel data.
  • P_1', P_2', ..., P_3Y' respectively represent the Q column pixel data
  • ln1, ln2 and ln3 included in P_1' respectively represent the three sub-pixel data included in P_1'.
  • P_1, P_2, ..., P_6Y respectively represent the supplemented N columns of pixel data, which are used as the output signals of the resolution conversion module.
  • P_1' ⁇ P_3Y' can be used as the odd columns P_1, P_3, P_5, ..., P_(6Y-1) in the output signal respectively, and the supplementary data signal P_2 of the intermediate even column is generated between each two adjacent odd columns.
  • P_4, P_6, ..., P_(6Y-2), and the supplementary data signal P_6Y can be generated in the last even column.
  • the number of columns N of the pixel unit is three times the number of columns Q of the display data, then two supplementary pixel data columns are generated between every two adjacent columns of the Q column pixel data, and between the Q column pixel data and Two supplementary pixel data columns are generated on one side (left or right side), or one supplementary pixel data column can be generated on both sides of the Q column pixel data.
  • Figure 13 is a schematic diagram of a resolution conversion module provided by at least one embodiment of the present disclosure.
  • the resolution conversion module includes multiple operators, which can implement interpolation operations.
  • Each column of pixel signals at the input end can be used as an odd-numbered column at the output end.
  • the even-numbered columns at the output end use two adjacent columns of odd-numbered column pixels.
  • the data is processed by the operator and then output.
  • the last column of even column pixel data can copy the previous column of odd column pixel data.
  • P_1 ⁇ P_3 as an example, in the process of generating P_2, the sub-pixel data of the corresponding color sub-pixels in P_1 ⁇ P_3 can be interpolated to obtain the sub-pixel data of the corresponding color sub-pixel in P_2.
  • ln1, ln2 and ln3 respectively represent the sub-pixel data of the R pixel, the sub-pixel data of the G pixel and the sub-pixel data of the B pixel, and ln4, ln5 and ln6 respectively represent the sub-pixel data of the R pixel and the sub-pixel data of the G pixel.
  • the operator may be, for example, an average operator.
  • FIG. 14 is a schematic diagram of a gray scale change provided by at least one embodiment of the present disclosure.
  • the Q column pixel data (for example, P_1' ⁇ P_6') is used as the odd column pixel data signal (for example, P_1, P_3, ..., P_11) and the even column supplementary pixel data signal (for example, P_2, P_4) is generated ,..., GL12).
  • the upper row of gray scales represents, for example, the brightness characteristics of the six columns of pixel units corresponding to P_1' to P_6' before pixel data expansion
  • the lower row of gray scales for example, represents the brightness characteristics of P_1 to P_12 respectively corresponding to the pixel data after expansion.
  • Luminance characteristics of 12-column pixel units The value of the pixel data in the even columns is the interpolation (for example, the mean) of the pixel data in the two adjacent odd columns on the left and right, so that the gray level of the pixel unit in the even column is the transition of the gray scale of the pixel unit in the adjacent odd column, which will not cause color distortion.
  • Chaos makes the entire expanded display screen present a better display effect.
  • FIG. 15 is a schematic diagram of input signals and output signals of another resolution conversion module provided by at least one embodiment of the present disclosure.
  • P_1' ⁇ P_3Y' can be used as the even columns P_2, P_4, P_6, ..., P_6Y in the output signal respectively, and supplementary pixel data is generated in the first column P_1.
  • Column P_1 can copy the pixel data of the second column P_2, and supplementary data signals P_1, P_3, P_5, ..., P_(6Y-1) of the intermediate odd-numbered columns are generated between every two adjacent even-numbered columns.
  • FIG. 16 is a schematic diagram of input pixel data and output pixel data in another source driver provided by at least one embodiment of the present disclosure.
  • Q-column analog data signals can be respectively generated based on Q-column pixel data, where the Q-column analog data signals are respectively used to input N-column pixel units. In this case, no interpolation is required.
  • FIG. 17 is a schematic diagram of another timing controller provided by at least one embodiment of the present disclosure.
  • the timing controller may further include a mode control module, the mode control module is configured to receive a mode instruction, and send a control signal to the gate line signal generation module and/or the source driver chip based on the mode instruction to control the gate Whether the gate signal generation module performs the gate signal supplement operation and/or whether the control source driver chip performs the data supplement operation.
  • the mode instruction can be obtained by automatically detecting the resolution of the image to be displayed and comparing it with the physical resolution of the display panel, or by user input.
  • FIG. 18 is a schematic diagram of another source driver chip provided by at least one embodiment of the present disclosure.
  • the control signal (mode control signal) sent by the timing controller to the source driver chip can act on the resolution conversion module to control the resolution conversion module to perform or not perform a data supplement operation.
  • a mode control module is added to the timing control board, which is responsible for receiving and sending mode instructions.
  • a mode switching command can be sent to the gate line signal generation module to choose whether to use the interpolation operation function; on the other hand, a mode switching command can be sent to the source driver IC to adjust the ratio of the number of input and output signals of the source driver IC.
  • the interpolation function can be turned on and off by adding a switching device to its front end.
  • Figure 19 is a schematic diagram of another resolution conversion module provided by at least one embodiment of the present disclosure.
  • the resolution conversion module also includes a plurality of two-pass switches and a mode switching module (not shown in the figure).
  • Each dual-pass switch includes an input terminal and two output terminals. The input terminal of the dual-pass switch is connected to the buffer module for receiving a column of pixel data.
  • One of the output terminals is connected to at least one of the plurality of digital-to-analog conversion modules, and the other The output terminal is connected to at least one of the plurality of operation modules.
  • the mode switching module is configured to control the two-pass switch to output a column of pixel data to one of the two output terminals based on a control signal sent by the mode control module.
  • the working modes of the display device include normal mode and resolution extended mode.
  • the two-pass switch In the normal mode, the two-pass switch directly outputs the signal to the digital-to-analog conversion module without interpolation operation; in the resolution extended mode, the two-pass switch outputs the signal directly to the digital-to-analog conversion module.
  • the signal is output to the arithmetic unit, and then input into the digital-to-analog conversion module after interpolation operation.
  • the mode instruction is normal mode.
  • the timing control board sends normal mode control instructions to the gate signal generator, the interpolation operation function of the gate signal generator is turned off, and the output gate scanning signal corresponds one-to-one to the gate lines of the display panel. , as shown in Figure 7.
  • the timing control board sends normal mode control instructions to the source driver IC.
  • the input path of the two-way switch in the resolution conversion module and the output path of the two-way switch are the same numbered input and output, and the output signal does not pass through the arithmetic unit. , the arithmetic unit of the source driver IC does not work, as shown in Figure 16.
  • the mode instruction is the resolution-extended mode.
  • the timing control board when the vertical resolution of the display signal is half of the vertical resolution of the display panel and the horizontal resolution is the same, the timing control board sends a vertical resolution extension mode control instruction to the gate line signal generator to start Interpolation operation function, as shown in Figure 12 or Figure 15.
  • the timing control board sends normal mode control instructions to the source driver IC to make its inputs and outputs correspond one to one.
  • the timing control board when the horizontal resolution of the display signal is half of the horizontal resolution of the display panel and the vertical resolution is the same, the timing control board sends a normal mode control instruction to the gate line signal generator, and the interpolation operation function is turned off , the output gate line signals correspond to the gate lines of the display panel one-to-one.
  • the timing control board sends horizontal resolution extended mode control instructions to the source driver IC. At this time, the two-way switch in the source driver IC directs the input signal to the arithmetic unit.
  • the input channels In_1, In_2, and In_3 correspond to the first three output channels O_1 , O_2, O_3;
  • Operator 1 outputs the interpolation operation results of In_1 and In_4, corresponding to output channel O_4;
  • Operator 2 outputs the interpolation operation results of In_2 and In_5, corresponding to output channel O_5;
  • Operator 3 outputs the interpolation operation results of In_3 and In_6 , corresponding to output channel O_6;
  • selector switch 1 outputs In_4, corresponding to output channel O_7;
  • selector switch 2 outputs In_5, corresponding to output channel O_8;
  • selector switch 3 outputs In_6, corresponding to output channel O_9; and so on,
  • the input columns are used as the odd columns of the output.
  • the operation result of the even-numbered column and the adjacent odd-numbered column changes the ratio of the digital data signal received by the source driver IC to the output analog data signal to 1:2.
  • the timing control board when the horizontal resolution of the display signal is half of the horizontal resolution of the display panel and the vertical resolution of the display signal is also half of the vertical resolution of the display panel, the timing control board sends the vertical resolution
  • the extended mode control command is given to the grid signal generator, the interpolation operation function is turned on, and the ratio of the output grid signal to the panel grid is 1:1.
  • the timing control board sends horizontal resolution extended mode control instructions to the source driver IC, and the input to output ratio is 1:2.
  • Figure 20 is a schematic diagram of an image to be displayed provided by at least one embodiment of the present disclosure.
  • multiple consecutive images to be displayed have images in which two brightness features are alternately displayed in different columns, for example, images showing the brightest feature 301 and the darkest feature 302 are alternately displayed in different columns. .
  • more than two brightness features may be displayed alternately in different columns, for example, three or four brightness features may be displayed alternately.
  • the supplementary pixel data is obtained by interpolating the pixel data of adjacent columns, then brightness features that are not originally present in the picture will appear. For example, interpolation of the brightest feature 301 and the darkest feature 302 will appear.
  • a grayscale feature located between the brightest and the darkest causes picture distortion. In order to avoid this problem, it can be processed in the following way.
  • the Q column pixel data of the display data conforming to the alternating display rule circulates between g pixel values, and the g pixel values correspond to g kinds of brightness respectively.
  • Features (such as two or more brightness features).
  • each image group includes adjacent g frames of images to be displayed, and perform the following operations for each image group: If the current frame of the image to be displayed is the image in the image group In the k-frame image to be displayed, the Q-column pixel data of the k-th frame to-be-displayed image is transformed into the k-th pixel value among the g pixel values; for the transformed Q-column pixel data, a data supplement operation is performed; based on data supplement The pixel data of the k+n*gth column after the operation generates analog data signals and is input to the pixel unit of the k+n*gth column respectively, so that the pixel unit of the k+n*gth column is displayed as the kth of the g brightness characteristics.
  • a brightness characteristic wherein, when k is a positive integer greater than 1, the remaining column pixel units except the k+n*gth column pixel unit are displayed as the previous frame of the k-th frame image to be displayed.
  • Corresponding brightness characteristics when k is equal to 1, the pixel units in the remaining columns except the k+n*g column pixel unit are not displayed, n takes all integers from 0 to [Q/g-1], and g is An integer greater than 1 and less than Q, k is an integer less than or equal to g.
  • the timing control panel can add an image recognition function to identify a special display screen that has at least two brightness characteristics and is displayed alternately.
  • FIG 20 is a schematic diagram of another display device provided by at least one embodiment of the present disclosure. As shown in Figure 21, the timing control board outputs control signals to the source driver IC to control the opening and closing of the output channels, thereby controlling the corresponding columns. Whether sub-pixels are displayed.
  • Figure 22 is a schematic diagram of another resolution conversion module provided by at least one embodiment of the present disclosure. As shown in Figure 22, the resolution conversion module adds a switch module, and the switch module can turn off or turn on the digital-to-analog conversion function of the corresponding column.
  • the timing control board outputs the screen normally, and the output control signal control source driver IC turns on all output channels and outputs normally. Interpolation operations can be performed when the horizontal resolution is insufficient. If the timing control board detects a special display screen (for example, a screen in which two brightness features are displayed alternately in different columns) and the horizontal resolution is insufficient, the timing control board can split it according to the brightness features and form a full-area screen for each feature. , output alternately in sequence; at the same time, when any feature screen is displayed, the source driver IC output channels corresponding to other features are closed by outputting control signals. Take the situation where two brightness characteristics are displayed alternately as an example.
  • a special display screen for example, a screen in which two brightness features are displayed alternately in different columns
  • the timing control board can split it according to the brightness features and form a full-area screen for each feature. , output alternately in sequence; at the same time, when any feature screen is displayed, the source driver IC output channels corresponding to other features are closed by outputting control signals
  • the timing control board outputs the brightest (first characteristic) display picture in the entire area of the source driver IC. , that is, the input data of the odd-numbered columns is the brightest, and the calculation result of the even-numbered columns is also the brightest; at the same time, the output control signal is sent to the source driver IC to close the digital-to-analog conversion module of the even-numbered pixel column corresponding to the darkest (second feature), that is, 4 /5/6, 10/11/12... are turned off.
  • the odd-numbered columns are displayed as the brightest with the input signal
  • the even-numbered columns are displayed as the picture of the previous frame (the E-1th frame), assuming a certain gray scale.
  • the darkest (feature two) display screen in the entire area of the source driver IC is output to the source driver IC, that is, each column is the darkest.
  • the output control signal is sent to the source driver IC to turn off
  • the digital-to-analog conversion module for the odd-numbered pixel columns corresponding to the brightest (feature 1), that is, 1/2/3, 7/8/9... is turned off.
  • the even-numbered columns are the darkest because the odd-numbered columns input is the darkest, and the operation result is also the darkest. , that is, the output display is the darkest, and the odd-numbered column displays the picture of the previous frame, which is the brightest.
  • multiple frames of images to be displayed can be grouped according to the number of brightness features, and the number of images to be displayed in each group is equal to the number of brightness features.
  • the 12 frames of images can be divided into 4 groups, each group containing 3 frames of images. .
  • the first frame image in each group the first frame image is transformed into the first feature displayed in the entire area. After interpolation operation, the 1st, 4th (i.e. 1+3), and 7th (i.e.
  • the second frame image in each group is transformed into a full-area display second feature, and after interpolation operation, the 2nd, 5th (i.e., 2+3), and 8th (i.e., 2+2*3) , 11 (i.e.
  • 2+3*3) columns perform digital-to-analog conversion so that the pixel units of these columns present the second feature, and the remaining columns are the features of the corresponding columns in the previous frame, that is, the 1st, 4th, 7th and 10 still shows the first characteristics.
  • the third frame of image in each group the third frame of image is transformed into the entire area to display the third feature.
  • the 3rd, 6th (that is, 3+3), and 9th (that is, 3+2*3) , 12 (i.e. 3+3*3) columns perform digital-to-analog conversion so that the pixel units of these columns present the third feature.
  • the remaining columns are the pictures of the previous frame, that is, the 1st, 4th, 7th and 10th still present the third feature.
  • a feature, and columns 2, 5, 8, and 11 still present the second feature.
  • every three columns of pixel units present the first feature, the second feature, and the third feature in turn.
  • the above method is still used to achieve a picture in which the first feature, the second feature and the third feature are alternately displayed in each frame, realizing the display of this special picture.
  • the timing control board interpolates the gate line signal, the row signal frequency is doubled, and the data line signal output is not Change, that is, the data time of the row before the interpolation operation corresponds to the time of the two rows after the interpolation; if the first row or the last row does not have two adjacent rows, the interpolation is performed in advance or delayed with reference to the phase difference after interpolation of other rows.
  • the resolution conversion module of the source driver IC sequentially uses the pixel data signal of each column of the input end as an odd number of output columns or even columns, the other half of the output is calculated from its two adjacent columns; if the first or last column at the output does not have two adjacent columns, the first or last column following the data at the input is used; resolution
  • the conversion module is between the buffer and the digital-to-analog conversion module. The conversion action is completed before the signal enters the digital-to-analog conversion module.
  • the conversion action of the resolution conversion module is performed by the corresponding sub-pixels respectively, and no conversion is performed between different sub-pixels. , calculation; the operators between adjacent columns are analog circuit operation devices.
  • vertical resolution expansion and horizontal resolution expansion are relatively independent functions and do not interfere with each other.
  • the architecture of a display panel that matches the signal processing method of embodiments of the present disclosure is: gate lines are arranged in the horizontal direction, and data lines are arranged in the vertical direction; one pixel unit includes several sub-pixels, and the gate lines are arranged along the gate lines. Arranged in the line direction; the sub-pixels in the same column are the same sub-pixels and have the same polarity within one frame.
  • a mode control function is provided, corresponding to the situation where the vertical resolution of the display signal is half the physical resolution of the display panel and the horizontal resolution is the same, and the horizontal resolution of the display signal is half the physical resolution of the display panel and the vertical resolution is the same. Corresponding processing is performed when the ratio is the same, when the vertical and horizontal resolutions of the display signal are both half of the physical resolution of the display panel, and when the vertical and horizontal resolutions of the display signal are consistent with the physical resolution of the display panel.
  • the timing control board receives mode instructions; the timing control board sends mode instructions to the gate line signal generation module to adjust the number of output row signals; the timing control board sends mode instructions to the source driver IC to make the input signal match the The ratio of the output is switched between 1:1 and 1:2, for example.
  • the gate line signal generation module adjusts the number of output row signals by adding a control switch before the interpolation operation function.
  • the switch is turned on, the interpolation operation function is enabled, and the interpolation line is output after the operation.
  • Gate line signal otherwise the switch is turned off and the number of output signals remains unchanged.
  • the number of input channels of the source driver IC is the same as the number of output channels.
  • the channel connection method for ratio switching between the input and output signals of the source driver IC is: for the first half of the input channel of the source driver IC, after connecting the switching device Connect to the first half of the output channel one by one in turn. After connecting the switching device, connect to the odd or even columns of the output one by one. After connecting the switching device, the two perform operations on each other.
  • the output port of the arithmetic unit is connected to the even number of the output in turn.
  • Channels or odd-numbered channels are connected; for the second half of the input channel, connect the switching device to the second half of the output channel one by one.
  • the switching device is controlled by the mode command.
  • the horizontal resolution of the display signal is half of the display panel
  • the second half of the input channel is closed through the switch
  • the first half of the input channel is opened through the switch
  • the odd-numbered column or even-numbered column is output to the output end
  • the operation when the horizontal resolution of the display signal is consistent with the display panel turn on the second half of the input channel through the switch; turn on the first half of the input channel through the switch, and output to the first half of the output channel.
  • the timing control board has a picture recognition function, which can identify special pictures, adjust the output graphics according to the characteristics of the special pictures, send corresponding output control instructions to the source driver IC for time-sharing display, and finally superimpose the Create the desired screen.
  • the special screen has at least two brightness characteristics, and the columns are displayed alternately.
  • the timing control panel splits the recognized special pictures according to the number of features, and forms a full-area picture for each feature, which is output alternately in sequence.
  • the timing control board outputs the full-area picture of a certain feature, it outputs the control signal to the source driver IC and closes the output channels corresponding to other features.
  • the output control signal control source drives the output mode of each channel of the IC, which can be used to control the opening and closing of each digital-to-analog conversion module, or it can also be used to control the opening and closing of each channel of the power amplifier module.
  • the display system when the vertical resolution and/or horizontal resolution of the display signal does not match the vertical resolution and/or horizontal resolution of the display signal (for example, the vertical resolution and/or horizontal resolution of the display signal is When the physical resolution of the display panel is half), the display system can display normally.
  • the signal processing methods of some embodiments of the present disclosure realize that the physical resolution of the display panel is greater than the resolution of the display signal, and the display effect is close to the display effect corresponding to the physical resolution of the display panel.
  • the signal processing methods of some embodiments of the present disclosure can reduce the requirements for the display signal resolution, the system chip that outputs the display signal, the data transmission rate between the system board and the timing control board, and the timing control.
  • the data transmission rate requirements between the board and the source driver chip reduce the requirements for the timing control chip and the source driver chip, thereby greatly reducing the cost.
  • the signal processing methods of some embodiments of the present disclosure can also output normally when the resolution of the display signal is consistent with the resolution of the display panel, thereby improving flexibility.
  • the source driver IC has universal applicability and avoids an increase in usage costs.
  • the signal processing methods of some embodiments of the present disclosure solve the problem that special pictures such as vertically separated columns cannot be displayed normally, and improve the display quality.
  • the signal processing methods of some embodiments of the present disclosure increase the charging rate by doubling the pixel charging time, reduce image quality problems caused by insufficient charging, and improve the image quality.
  • the display device includes a display substrate and a timing controller.
  • the display substrate includes M rows and N columns of pixel units arranged in an array;
  • the timing controller includes a data receiving module and a gate signal generating module.
  • the data receiving module is configured to obtain display data of a frame of an image to be displayed, where the display data includes pixel data of P rows and Q columns arranged in an array.
  • the gate signal generation module is configured to: corresponding to P rows of pixel data, generate P rows of gate scan signals; when P is less than M, perform a gate signal supplement operation, where the gate signal supplement operation includes: based on P rows of gate polar scan signal to generate an M-P row supplementary gate scan signal, where the P-row gate scan signal and the M-P row supplementary gate scan signal form an M-row gate scan signal, so that the M-row gate scan signal is used to drive M rows respectively.
  • Pixel unit; P, Q, M and N are all positive integers.
  • the display device further includes a source driver chip.
  • the source driver chip is connected to the M rows and N columns of pixel units through a plurality of data signal lines extending in a second direction crossing the first direction to provide analog to the M rows and N columns of pixel units.
  • data signal wherein the source driver chip is configured to: when Q is less than N, perform a data supplement operation, wherein the data supplement operation includes: based on the Q column pixel data, generate N-Q column supplementary pixel data, Q column pixel data and N-Q
  • the columns of supplementary pixel data form N columns of pixel data; based on the N columns of pixel data, N columns of analog data signals are generated; the N columns of analog data signals are respectively input to N columns of pixel units.
  • the source driver chip includes a cache module, multiple operation modules and multiple digital-to-analog conversion modules.
  • the cache module is configured to cache display data; the multiple operation modules are configured to perform data supplement operations to obtain N-Q column supplementary pixel data; multiple data
  • the analog conversion module is configured to convert the N columns of pixel data into N columns of analog data signals.
  • the timing controller further includes a mode control module.
  • the mode control module is configured to receive a mode instruction and send a control signal to the gate signal generation module and/or the source driver chip based on the mode instruction to control whether the gate signal generation module performs gate operation.
  • the pole signal supplement operation and/or controls whether the source driver chip performs the data supplement operation.
  • the source driver chip also includes multiple two-way switches and mode switching modules.
  • Each two-way switch includes an input terminal and two output terminals. The input terminal is connected to the cache module for receiving a column of pixel data, and one of the output terminals is connected to to at least one of the plurality of digital-to-analog conversion modules, and the other output terminal is connected to at least one of the plurality of operation modules; the mode switching module is configured to control the two-pass switch based on the control signal sent by the mode control module to output one column of pixel data to two one of the output terminals.
  • the timing controller also includes an image recognition module.
  • the image recognition module is configured to: identify whether the display data of multiple consecutive frames of images to be displayed conforms to the alternating display rule, where the Q column pixel data of the display data conforming to the alternating display rule is in g Cycle between pixel values, and g pixel values correspond to g brightness characteristics respectively; if so, divide the multi-frame images to be displayed into multiple picture groups, each group includes adjacent g frames of images to be displayed, and for each Picture group execution: If the current frame image to be displayed is the k-th frame image to be displayed in the picture group, transform the Q column pixel data of the k-th frame image to be displayed into the k-th pixel value among the g pixel values; The transformed Q column pixel data is output to the source driver chip;
  • the source driver chip is also configured to: perform a data supplement operation on the transformed Q column pixel data; generate an analog data signal based on the k+n*g column pixel data after the data supplement operation and input it into the k+n*g column respectively.
  • Pixel unit so that the pixel unit of the k+n*gth column is displayed as the kth brightness feature among the g brightness features, where, when k is a positive integer greater than 1, except for the k+n*gth column
  • the pixel units in the remaining columns other than the pixel unit are displayed as the brightness characteristics corresponding to the image to be displayed in the previous frame of the k-th frame image to be displayed; when k is equal to 1, the pixel units in the remaining columns except the k+n*g-th column
  • the remaining column pixel units are not displayed, where n takes all integers from 0 to [Q/g-1], g is an integer greater than 1 and less than Q, and k is an integer less than or equal to g.
  • At least one embodiment of the present disclosure provides an electronic device, including the display device provided by any embodiment of the present disclosure.
  • the electronic device may include a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, or any other electronic product with a display function.
  • FIG. 25 is a schematic block diagram of another electronic device provided by some embodiments of the present disclosure.
  • the electronic device 400 includes a processor 410 and a memory 420 .
  • Memory 420 is used to store non-transitory computer-readable instructions (eg, one or more computer program modules).
  • the processor 410 is configured to execute non-transitory computer readable instructions. When the non-transitory computer readable instructions are executed by the processor 410, they may perform one or more steps in the signal processing method described above.
  • Memory 420 and processor 410 may be interconnected by a bus system and/or other forms of connection mechanisms (not shown).
  • the processor 410 may be a central processing unit (CPU), a graphics processing unit (GPU), or other forms of processing units with data processing capabilities and/or program execution capabilities.
  • the central processing unit (CPU) may be of X86 or ARM architecture.
  • the processor 410 may be a general-purpose processor or a special-purpose processor that may control other components in the electronic device 400 to perform desired functions.
  • memory 420 may include any combination of one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and/or non-volatile memory.
  • Volatile memory may include, for example, random access memory (RAM) and/or cache memory (cache), etc.
  • Non-volatile memory may include, for example, read-only memory (ROM), hard disk, erasable programmable read-only memory (EPROM), portable compact disk read-only memory (CD-ROM), USB memory, flash memory, and the like.
  • One or more computer program modules may be stored on the computer-readable storage medium, and the processor 410 may run the one or more computer program modules to implement various functions of the electronic device 400 .
  • Various application programs and various data, as well as various data used and/or generated by the application programs, etc. can also be stored in the computer-readable storage medium.
  • FIG. 26 is a schematic block diagram of another electronic device provided by some embodiments of the present disclosure.
  • the electronic device 500 is, for example, suitable for implementing the signal processing method provided by the embodiment of the present disclosure.
  • the electronic device 500 may be a terminal device or the like. It should be noted that the electronic device 500 shown in FIG. 26 is only an example, which does not bring any limitations to the functions and scope of use of the embodiments of the present disclosure.
  • the electronic device 500 may include a processing device (eg, central processing unit, graphics processor, etc.) 510, which may be loaded into a random access device according to a program stored in a read-only memory (ROM) 520 or from a storage device 580.
  • the program in the memory (RAM) 530 executes various appropriate actions and processes.
  • various programs and data required for the operation of the electronic device 500 are also stored.
  • the processing device 510, ROM 520 and RAM 530 are connected to each other through a bus 540.
  • An input/output (I/O) interface 550 is also connected to bus 540.
  • the following devices may be connected to the I/O interface 550: input devices 560 including, for example, a touch screen, touch pad, keyboard, mouse, camera, microphone, accelerometer, gyroscope, etc.; including, for example, a liquid crystal display (LCD), speakers, vibration An output device 570 such as a computer; a storage device 580 including a magnetic tape, a hard disk, etc.; and a communication device 590.
  • the communication device 590 may allow the electronic device 500 to communicate wirelessly or wiredly with other electronic devices to exchange data.
  • FIG. 26 illustrates the electronic device 500 having various means, it should be understood that implementation or provision of all illustrated means is not required and the electronic device 500 may alternatively implement or be provided with more or fewer means.
  • the above-described signal processing method may be implemented as a computer software program.
  • embodiments of the present disclosure include a computer program product including a computer program carried on a non-transitory computer-readable medium, the computer program including program code for executing the above-described signal processing method.
  • the computer program may be downloaded and installed from the network through the communication device 590, or installed from the storage device 580, or installed from the ROM 520.
  • the processing device 510 When the computer program is executed by the processing device 510, the functions defined in the signal processing method provided by the embodiments of the present disclosure can be implemented.
  • At least one embodiment of the present disclosure also provides a computer-readable storage medium for storing non-transitory computer-readable instructions, which can implement the above when the non-transitory computer-readable instructions are executed by a computer. signal processing methods.
  • Figure 27 is a schematic diagram of a storage medium provided by some embodiments of the present disclosure. As shown in FIG. 27, storage medium 600 is used to store non-transitory computer-readable instructions 610. For example, the non-transitory computer readable instructions 610 when executed by a computer may perform one or more steps in the signal processing method described above.
  • the storage medium 600 can be applied to the above-mentioned electronic device 400.
  • the storage medium 600 may be the memory 420 in the electronic device 400 shown in FIG. 25 .
  • the relevant description of the storage medium 600 may refer to the corresponding description of the memory 420 in the electronic device 400 shown in FIG. 25 , which will not be described again here.

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Abstract

一种信号处理方法、显示装置、电子设备和计算机可读存储介质（600）。信号处理方法用于显示装置，显示装置包括显示基板（110），显示基板（110）包括阵列排布的M行N列像素单元，信号处理方法包括：获取一帧待显示图像的显示数据，其中，显示数据包括阵列排布的P行Q列像素数据；对应P行像素数据，生成P行栅极扫描信号；在P小于M的情况下，基于P行栅极扫描信号，生成M-P行补充栅极扫描信号，其中，P行栅极扫描信号和M-P行补充栅极扫描信号形成M行栅极扫描信号；分别利用该M行栅极扫描信号驱动M行像素单元，P、Q、M和N均为正整数。

Description

信号处理方法、显示装置、电子设备和可读存储介质 技术领域
本公开的实施例涉及一种信号处理方法、显示装置、电子设备和计算机可读存储介质。
背景技术
随着显示行业的发展，以显示面板为显示端口的显示装置已经越来越多的融入到人们的工作和生活中，常用的显示装置包括液晶显示装置和OLED(Organic Light-Emitting Diode)显示装置等。
发明内容
本公开至少一实施例提供一种信号处理方法，用于显示装置，所述显示装置包括显示基板，所述显示基板包括阵列排布的M行N列像素单元，所述信号处理方法包括：获取一帧待显示图像的显示数据，其中，所述显示数据包括阵列排布的P行Q列像素数据；对应所述P行像素数据，生成P行栅极扫描信号；在P小于M的情况下，基于所述P行栅极扫描信号，生成M-P行补充栅极扫描信号，其中，所述P行栅极扫描信号和所述M-P行补充栅极扫描信号形成M行栅极扫描信号；分别利用所述M行栅极扫描信号驱动所述M行像素单元；其中，P、Q、M和N均为正整数。
例如，在本公开至少一实施例提供的信号处理方法中，在M＝A*P的情况下，基于所述P行栅极扫描信号，生成M-P行补充栅极扫描信号，包括：在所述P行栅极扫描信号中的每相邻两行栅极扫描信号之间，生成A-1行补充栅极扫描信号；在所述P行栅极扫描信号的至少一侧生成A-1行栅极扫描信号；其中，A为大于1的整数。
例如，在本公开至少一实施例提供的信号处理方法中，所述P行栅极扫描信号包括相邻的第i行栅极扫描信号和第i+1行栅极扫描信号；基于所述P行栅极扫描信号，生成M-P行补充栅极扫描信号，包括：基于所述第i行栅极扫描信号和所述第i+1行栅极扫描信号的时序，生成位于所述第i行栅极扫描信号和所述第i+1行栅极扫描信号的之间的B行补充栅极扫描信号；其中，所述B行补充栅极扫描信号的上升沿在时序上均位于所述第i行栅极 扫描信号的上升沿和第i+1行栅极扫描信号的上升沿之间，所述B行补充栅极扫描信号的下降沿在时序上均位于所述第i行栅极扫描信号的下降沿和第i+1行栅极扫描信号的下降沿之间，其中，i为小于P的正整数，B为小于等于M-P的正整数。
例如，在本公开至少一实施例提供的信号处理方法中，所述第i行栅极扫描信号的上升沿、所述B行补充栅极扫描信号的上升沿和所述第i+1行栅极扫描信号的上升沿在时序上依次顺延；所述第i行栅极扫描信号的下降沿、所述B行补充栅极扫描信号的下降沿和所述第i+1行栅极扫描信号的下降沿在时序上依次顺延。
例如，在本公开至少一实施例提供的信号处理方法中，基于所述第i行栅极扫描信号和所述第i+1行栅极扫描信号的时序，生成位于所述第i行栅极扫描信号和所述第i+1行栅极扫描信号的之间的B行补充栅极扫描信号，包括：对所述第i行栅极扫描信号的相位和所述第i+1行栅极扫描信号的相位进行插值运算，得到所述B行补充栅极扫描信号的相位。
例如，在本公开至少一实施例提供的信号处理方法中，所述B行补充栅极扫描信号中的每行补充栅极扫描信号的上升沿和下降沿之间的时间差与所述第i行栅极扫描信号的上升沿和下降沿之间的时间差相同。
例如，在本公开至少一实施例提供的信号处理方法中，每个像素单元包括S个子像素，位于同一像素单元的S个子像素沿行方向排布，所述N列像素单元包括N*S列子像素；位于同一列的子像素在一帧待显示图像的显示时间内极性相同，其中，S为正整数。
例如，本公开至少一实施例提供的信号处理方法，还包括：在P等于M的情况下，分别利用所述P行栅极扫描信号驱动所述M行像素单元。
例如，在本公开至少一实施例提供的信号处理方法中，所述显示装置还包括与所述N列像素单元分别连接的N条数据信号线；所述信号处理方法还包括：分别基于所述P行像素数据，生成P行模拟数据信号，其中，所述P行模拟数据信号包括第i行模拟数据信号，所述第i行模拟数据信号包括Q个模拟数据信号；从利用所述第i行栅极扫描信号驱动对应行像素单元的数据写入开关打开开始至利用所述第i+1行栅极扫描信号驱动对应行像素单元的数据写入开关打开之前的时间段内，将所述第i行模拟数据信号的Q个模拟数据信号分别输入所述N条数据信号线中的Q条数据信号线。
例如，在本公开至少一实施例提供的信号处理方法中，每个所述像素单元包括S个子像素，所述N列像素单元包括N*S列子像素，所述N条数据信号线包括分别与所述N*S列子像素连接的N*S条子数据信号线；每个所述模拟数据信号包括S个子模拟数据信号，所述Q个模拟数据信号包括Q*S个子模拟数据信号；将所述第i行模拟数据信号的Q个模拟数据信号分别输入所述N条数据信号线中的Q条数据信号线，包括：将所述Q*S个子模拟数据信号分别输入所述N*S条子数据信号线中的Q*S条子数据信号线。
例如，在本公开至少一实施例提供的信号处理方法还包括：在Q小于N的情况下，执行数据补充操作，其中，所述数据补充操作包括：基于所述Q列像素数据，生成N-Q列补充像素数据，所述Q列像素数据和所述N-Q列补充像素数据形成N列像素数据；基于所述N列像素数据，生成N列模拟数据信号；将所述N列模拟数据信号分别输入所述N列像素单元。
例如，在本公开至少一实施例提供的信号处理方法中，在N＝C*Q的情况下，基于所述Q列像素数据，生成N-Q列补充像素数据，包括：在所述Q列像素数据中的每相邻两列像素数据之间，生成C-1列补充像素数据；在所述Q列像素数据的至少一侧生成C-1列补充像素数据；其中，C为大于1的整数。
例如，在本公开至少一实施例提供的信号处理方法中，所述Q列像素数据包括相邻的第j列像素数据和第j+1列像素数据；基于所述Q列像素数据，生成N-Q列补充像素数据，包括：对所述第j列像素数据和所述第j+1列像素数据进行插值运算，生成位于所述第j列像素数据和所述第j+1列像素数据之间的D列补充像素数据；其中，j为小于Q的正整数，D为小于等于N-Q的正整数。
例如，本公开至少一实施例提供的信号处理方法还包括：在Q等于N的情况下，基于所述Q列像素数据，分别生成Q列模拟数据信号，其中，所述Q列模拟数据信号分别用于输入所述N列像素单元。
例如，本公开至少一实施例提供的信号处理方法还包括：确定连续多帧待显示图像的显示数据是否符合交替显示规律，其中，符合所述交替显示规律的显示数据的Q列像素数据在g个像素值之间循环，所述g个像素值分别对应g种亮度特征；若是，将所述多帧待显示图像分为多个图组，每个图组包括相邻的g帧待显示图像，针对每个图组执行以下操作：若当前帧待显示 图像为所述图组中的第k帧待显示图像，将所述第k帧待显示图像的Q列像素数据均变换为所述g个像素值中的第k个像素值；对于变换后的Q列像素数据，执行所述数据补充操作；基于所述数据补充操作后的第k+n*g列像素数据生成模拟数据信号并分别输入第k+n*g列像素单元，以使所述第k+n*g列像素单元显示为所述g种亮度特征中的第k种亮度特征，其中，在k为大于1的正整数的情况下，除所述第k+n*g列像素单元之外的其余列像素单元显示为所述第k帧待显示图像的上一帧待显示图像对应的亮度特征；在k等于1的情况下，除所述第k+n*g列像素单元之外的其余列像素单元不显示，其中，n取0至[Q/g-1]的全部整数，g为大于1且小于Q的整数，k为小于等于g的整数。
本公开至少一实施例还提供一种显示装置，包括显示基板和时序控制器，显示基板包括阵列排布的M行N列像素单元；时序控制器包括数据接收模块和栅极信号生成模块；数据接收模块配置为获取一帧待显示图像的显示数据，其中，显示数据包括阵列排布的P行Q列像素数据。栅极信号生成模块配置为：对应P行像素数据，生成P行栅极扫描信号；在P小于M的情况下，执行栅极信号补充操作，其中，栅极信号补充操作包括：基于P行栅极扫描信号，生成M-P行补充栅极扫描信号，其中，P行栅极扫描信号和M-P行补充栅极扫描信号形成M行栅极扫描信号，以分别利用所述M行栅极扫描信号驱动M行像素单元；P、Q、M和N均为正整数。
例如，在本公开至少一实施例提供的显示装置中，显示装置还包括源驱动芯片，源驱动芯片通过多条沿与第一方向交叉的第二方向延伸的数据信号线与M行N列像素单元连接，以向M行N列像素单元提供模拟数据信号，其中，源驱动芯片配置为：在Q小于N的情况下，执行数据补充操作，其中，数据补充操作包括：基于Q列像素数据，生成N-Q列补充像素数据，Q列像素数据和N-Q列补充像素数据形成N列像素数据；基于形成的N列像素数据，生成N列模拟数据信号；将N列模拟数据信号分别输入N列像素单元。
例如，在本公开至少一实施例提供的显示装置中，源驱动芯片包括缓存模块、多个运算模块和多个数模转换模块，缓存模块配置为缓存显示数据；多个运算模块配置为执行数据补充操作，得到N-Q列补充像素数据；多个数模转换模块配置为将该N列像素数据转换为N列模拟数据信号。
例如，在本公开至少一实施例提供的显示装置中，时序控制器还包括模式控制模块，模式控制模块配置为接收模式指令，并基于模式指令向栅极信号生成模块和/或源驱动芯片发送控制信号，以控制栅极信号生成模块是否执行栅极信号补充操作和/或控制源驱动芯片是否执行数据补充操作。
例如，在本公开至少一实施例提供的显示装置中，源驱动芯片还包括多个双通开关和模式切换模块，每个双通开关包括一个输入端和两个输出端，输入端连接缓存模块，用于接收一列像素数据，其中一个输出端连接至多个数模转换模块中的至少一个，另一个输出端连接至多个运算模块中的至少一个；模式切换模块配置为基于模式控制模块发送的控制信号控制双通开关将一列像素数据输出至两个输出端中的一个。
例如，在本公开至少一实施例提供的显示装置中，时序控制器还包括图像识别模块，图像识别模块配置为：识别连续多帧待显示图像的显示数据是否符合交替显示规律，其中，符合交替显示规律的显示数据的Q列像素数据在g个像素值之间循环，g个像素值分别对应g种亮度特征；若是，将多帧待显示图像分为多个图组，每个图组包括相邻的g帧待显示图像，并针对每个图组执行：若当前帧待显示图像为图组中的第k帧待显示图像，将第k帧待显示图像的Q列像素数据均变换为g个像素值中的第k个像素值；将变换后的Q列像素数据输出至源驱动芯片；源驱动芯片还配置为：对于变换后的Q列像素数据，执行数据补充操作；基于数据补充操作后的第k+n*g列像素数据生成模拟数据信号并分别输入第k+n*g列像素单元，以使第k+n*g列像素单元显示为g种亮度特征中的第k种亮度特征，其中，在k为大于1的正整数的情况下，除第k+n*g列像素单元之外的其余列像素单元显示为第k帧待显示图像的上一帧待显示图像对应的亮度特征；在k等于1的情况下，除第k+n*g列像素单元之外的其余列像素单元不显示，其中，n取0至[Q/g-1]的全部整数，g为大于1且小于Q的整数，k为小于等于g的整数。
本公开至少一个实施例提供一种电子设备，包括本公开任一实施例提供的显示装置。
本公开至少一个实施例提供一种电子设备，包括处理器；存储器，包括一个或多个计算机程序模块；其中，所述一个或多个计算机程序模块被存储在所述存储器中并被配置为由所述处理器执行，所述一个或多个计算机程序模块包括用于实现本公开任一实施例提供的信号处理方法的指令。
本公开至少一个实施例提供一种计算机可读存储介质，用于存储非暂时性计算机可读指令，当所述非暂时性计算机可读指令由计算机执行时可以实现本公开任一实施例提供的信号处理方法。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例，而非对本发明的限制。
图1为本公开至少一实施例提供的一种显示装置的示意图；
图2为本公开至少一实施例提供的一种子像素的排布示意图；
图3为本公开至少一实施例提供的一种时序控制器的示意图；
图4为本公开至少一实施例提供的另一种显示装置的示意图；
图5为本公开至少一实施例提供的一种信号处理方法的示意图；
图6为本公开至少一实施例提供的栅极扫描信号的时序示意图；
图7为本公开至少一实施例提供的一种显示过程的示意图；
图8为本公开至少一实施例提供的另一种显示过程的示意图；
图9为本公开至少一实施例提供的一种灰阶变化的示意图；
图10为本公开至少一实施例提供的另一种显示过程的示意图；
图11为本公开至少一实施例提供的一种源极驱动器的示意图；
图12为本公开至少一实施例提供的一种源极驱动器中输入像素数据和输出像素数据的示意图；
图13为本公开至少一实施例提供的一种分辨率控制模块的示意图；
图14为本公开至少一实施例提供的一种灰阶变化的示意图；
图15为本公开至少一实施例提供的另一种源极驱动器中输入像素数据和输出像素数据的示意图；
图16为本公开至少一实施例提供的另一种源极驱动器中输入像素数据和输出像素数据的示意图；
图17为本公开至少一实施例提供的另一种时序控制器的示意图；
图18为本公开至少一实施例提供的另一种源驱动芯片的示意图；
图19为本公开至少一实施例提供的另一种分辨率转换模块的示意图；
图20为本公开至少一实施例提供的符合交替显示规律的待显示图像的 示意图；
图21为本公开至少一实施例提供的另一种显示装置的示意图；
图22为本公开至少一实施例提供的另一种分辨率转换模块的示意图；
图23为本公开至少一实施例提供的一种显示画面的示意图；
图24为本公开至少一实施例提供的另一种显示画面的示意图；
图25为本公开一些实施例提供的一种电子设备的示意框图；
图26为本公开一些实施例提供的另一种电子设备的示意框图；
图27为本公开一些实施例提供的一种存储介质的示意图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例的附图，对本发明实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于所描述的本发明的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
图1为本公开至少一实施例提供的一种显示装置的示意图。如图1所示，显示装置包括显示面板110、时序控制器120、栅极驱动器130和源极驱动器140。
显示面板110包括阵列排布的多行多列子像素Pxij。例如，显示基板110包括阵列排布的M行N列像素单元，像素单元为显示面板的最小完整显示单位，可以由若干个子像素Pxij组成。例如，每个像素单元包括S个子像素 (S为正整数)，位于同一像素单元的S个子像素可以沿行方向排布，这种情况下，N列像素单元包括N*S列子像素。
图2为本公开至少一实施例提供的一种子像素的排布示意图。如图2所示，每个像素单元例如包括沿行方向排布的三个子像素，分别为子像素1、子像素2和子像素3，这三种子像素例如分别为R(红色)、G(绿色)、B(蓝色)，则显示面板包括M行3N列子像素。每行中连续的三个子像素组成一个像素单元，例如，第一行中与DL1～DL3连接的三个子像素组成像素单元1，第一行中与DL4～DL6连接的三个子像素组成像素单元2，…，第一行中与DL(3x-2)～DL3x连接的三个子像素组成像素单元x，其中1<＝x<＝N，…，第一行中与DL(3N-2)～DL3N连接的三个子像素组成像素单元N。此外，像素单元包含的子像素的个数和排布还可以采用其他方式，本公开实施例以像素单元包含3个子像素并且同一像素单元中的3个子像素沿行方向排布为例进行说明。
如图1和图2所示，显示面板还包括沿第一方向延伸的多条栅极扫描信号线(GL1～GLM)和沿与第一方向交叉的第二方向延伸的多条数据信号线(DL1～DLN*S)，例如，第一方向为行方向，第二方向为列方向，第一方向与第二方向垂直。多条栅极扫描信号线(GL1～GLM)分别连接M行像素单元，一条栅极扫描信号线可以连接至一行中的每个子像素，栅极扫描信号线传输的栅极扫描信号用于驱动相应行中全部子像素的开关器件打开。多条数据信号线(DL1～DLN*S)分别连接N*S列子像素，一条数据信号线连接至一列中的每个子像素，在子像素的开关器件打开的情况下，数据信号线传输的数据信号可以被写入子像素中，数据信号为调整子像素显示灰阶的信号，使显示面板各子像素显示不同的灰阶。在以下的实施例中，GL1～GLM既用来表示栅极扫描信号线又用于表示相应栅极扫描信号线上传输的栅极扫描信号，DL1～DLN*S既用来表示数据信号线又用于表示相应数据信号线上传输的数据信号。
每个子像素均与一根栅极扫描信号线和一根数据信号线相连，通过栅极扫描信号线和数据信号线控制，实现灰阶变化。在呈现待显示图像的过程中，可以每次打开显示面板中的一行子像素，并且数据驱动器140将相应行的数据信号写入导通的该行子像素中，使该行子像素呈现相应的亮度。以此方式进行逐行打开和写入，即可使显示面板按照对应的显示亮度呈现待显示图 像。
时序控制器120为实现时序转换功能的板卡，其可以是独立的部件，也可以包括在前端视频等信号的处理系统中。图3为本公开至少一实施例提供的一种时序控制器的示意图。如图3所示，时序控制器120包括数据接收模块121、栅极信号生成模块122和数据信号发送模块123。数据接收模块121用于接收待显示图像的显示数据，栅极信号生成模块122根据显示数据的垂直分辨率(即显示数据的行数)，生成一一对应的栅极扫描信号，并发送给栅极驱动器130，以通过栅极驱动器130中级联的多个移位寄存器单元将栅极扫描信号发送至显示面板。数据信号发送模块123将显示数据发送至源极驱动器，接收与发送的像素数据是一一对应的，称为Point to Point(P to P)，即接收数据的列数与发送数据的列数相同，接收数据的行数与发送数据的行数相同。源极驱动器对数据信号进行处理后发送至显示面板。在以下的一些实施例中，时序控制器也称为时序控制板。在以下的一些实施例中，栅极信号生成模块也成为了栅线信号生成模块，栅极扫描信号也称为栅线信号。
源极驱动器140可以包括源驱动IC(Integrated Circuit Chip)，负责将接收到的数字数据信号转换为能驱动像素显示的模拟数据信号，其输出通道与显示面板的列一一对应。数字数据信号是指时序控制板将每一行的像素数据信号均分，经由数据信号发送模块分别发送至源驱动IC的数据信号，其为二进制的数字信号；模拟数据信号是源驱动IC将数字数据信号结合模拟电压转换而来，并发送至显示面板各数据线，其为模拟电压信号。在以下的一些实施例中，源极驱动器140也简称为源驱动IC或源驱动芯片。
图4为本公开至少一实施例提供的另一种显示装置的示意图。如图4所示，栅极驱动器可以集成于显示面板中，时序控制器发出的栅极扫描信号可以通过源极驱动器发送至显示面板，通过显示面板集成的栅极驱动器和栅极扫描信号线逐行驱动子像素。时序控制器发出的显示数据信号发送至源极驱动器，利用源极驱动器对显示数据信号进行处理并通过数据信号线发送至各列子像素。
为满足人们对于高清晰度和高流畅度的需求，超高分辨率和超高刷新率的面板已经开发问世，导致对显示信号数据量的需求大幅增加，如4K2K240Hz较4K2K 120Hz的数据量提升一倍，8K4K 120Hz较4K2K 120Hz的数据量提升四倍，大幅增加的数据量对产生显示信号的系统芯片的处理速度提 出了更高的要求，更高速率的信号传输要求传输路径(设计、工艺、材质等)更加优化，同时显示系统自身的时序控制芯片、源驱动芯片也要与之匹配，使得成本大幅上升，严重影响了超高分辨率和超高刷新率面板的普及，成为了人们对于美好生活的拦路虎。
显示面板包括M行N列显示单元，则物理分辨率为N*M。每行有N个像素，称之为水平分辨率；每列有M个像素，称之为垂直分辨率。待显示图像的分辨率需与显示面板的物理分辨率匹配，即行数和列数一一对应。在显示信号分辨率与显示面板的物理分辨率不匹配时，例如水平分辨率仅有面板分辨率的一半，会造成显示面板无法进行显示或者显示效果不佳。
本公开至少一实施例提供一种信号处理方法、显示装置、电子设备和计算机可读存储介质。该信号处理方法用于显示装置，显示装置包括显示基板，显示基板包括阵列排布的M行N列像素单元，该信号处理方法包括：获取一帧待显示图像的显示数据，其中，显示数据包括阵列排布的P行Q列像素数据；对应P行像素数据，生成P行栅极扫描信号；在P小于M的情况下，基于P行栅极扫描信号，生成M-P行补充栅极扫描信号，其中，P行栅极扫描信号和M-P行补充栅极扫描信号形成M行栅极扫描信号；分别利用形成的M行栅极扫描信号驱动M行像素单元，P、Q、M和N均为正整数。
本公开实施例的信号处理方法，通过基于显示数据的行数生成对应行数的栅极扫描信号并基于栅极扫描信号生成补充栅极扫描信号，以将栅极扫描信号的总行数扩充至与显示面板的像素单元的行数相同。基于这一方式，在待显示图像的垂直分辨率小于显示面板的垂直分辨率的情况下能够使显示面板的各行像素单元均显示，实现了垂直分辨率的扩充，提升显示效果。
下面结合附图对本公开的实施例及其一些示例进行详细说明。
图5为本公开至少一实施例提供的一种信号处理方法的示意图。该信号处理方法例如用于上述的显示装置，如图5所示，信号处理方法包括步骤S210-步骤S240。
步骤S210：获取一帧待显示图像的显示数据，显示数据包括阵列排布的P行Q列像素数据。
步骤S220：对应P行像素数据，生成P行栅极扫描信号。
步骤S230：在P小于M的情况下，基于P行栅极扫描信号，生成M-P行补充栅极扫描信号，P行栅极扫描信号和M-P行补充栅极扫描信号形成M行栅极扫描信号。
步骤S240：分别利用形成的M行栅极扫描信号驱动M行像素单元。
例如，P、Q、M和N均为正整数，P小于等于M，Q小于等于N。
例如，以图1所示的显示装置为例，显示面板包括M行N列像素单元，每个像素单元包括沿行方向排布的S个子像素(S为正整数)，N列像素单元包括N*S列子像素，即显示面板包括M行N*S列子像素。以下内容中的M行像素单元也可以理解为M行子像素。
例如，位于同一列的子像素在一帧待显示图像的显示时间内极性相同，同为正或同为负。例如，这里的子像素的极性是指施加到子像素上的数据信号的极性。
例如，在步骤S220中，栅极信号生成模块根据待显示图像的行数P生成对应行数的栅极扫描信号。
例如，在步骤S230中，可以判断待显示图像的行数P是否小于显示面板中像素单元的行数M(即子像素的行数M)，若待显示图像的行数P小于像素单元的行数M，则根据已生成的P行栅极扫描信号生成M-P行补充栅极扫描信号，以补足M行栅极扫描信号。例如，显示面板的物理分辨率为1920×1200，即显示面板包含的像素单元的行数为M＝1200。而待显示图像的图像分辨率为1440×900，即显示数据的行数为P＝900，这种情况下，先根据900行像素数据生成900行栅极扫描信号，再根据该900行栅极扫描信号生成300行补充栅极扫描信号，以补足1200行栅极扫描信号。例如，该M-P行补充栅极扫描信号中的至少部分行可以穿插在该P行栅极扫描信号之间，也就是说，该P行栅极扫描信号中的某相邻两行之间可以穿插有至少一行补充栅极扫描信号。M-P行补充栅极扫描信号中的部分行也可以位于P行栅极扫描信号的两侧。例如，在一种方式中，可以在P行栅极扫描信号中的仅部分行之间生成补充栅极扫描信号；在另一种方式中，也可以在P行栅极扫描信号中的每相邻两行之间均生成补充栅极扫描信号；在另一种方式中，也可以在P行栅极扫描信号的一侧或两侧生成补充栅极扫描信号；或者可以是以上三种方式的组合。
本公开实施例的信号处理方法，通过基于显示数据的行数生成对应行数 的栅极扫描信号并基于栅极扫描信号生成补充栅极扫描信号，以将栅极扫描信号的总行数扩充至与显示面板的像素单元的行数相同。基于这一方式，在待显示图像的垂直分辨率小于显示面板的垂直分辨率的情况下能够使显示面板的各行像素单元均显示，实现了垂直分辨率的扩充，提升显示效果。
例如，每行补充栅极扫描信号的时序中的开启时段与该P行栅极扫描信号中的至少一行栅极扫描信号的时序中的开启时段存在重叠部分。例如，每行补充栅极扫描信号的开启时段可以与该P行栅极扫描信号中距离最近的一行栅极扫描信号的开启时段存在重叠部分。
图6为本公开至少一实施例提供的栅极扫描信号的时序示意图。如图6所示，例如，P行栅极扫描信号包括相邻的两行栅极扫描信号GL1’和GL2’，例如，GL1’和GL2’的开启电平为高电平，GL1’和GL2’的开启时段分别为T10和T20，在开启时段内，栅极扫描信号可以驱动相应行的像素单元的开关器件处于打开状态。例如，在GL1’和GL2’之间生成了一行补充栅极扫描信号GL2(即B＝1)，补充栅极扫描信号GL2的开启时段与GL1和GL3中至少一者的开启时段有重叠部分。为了便于描述，在栅极扫描信号补充后，对行号进行了调整(例如按顺序重新编号)，GL1’和GL2’可以作为调整后的GL1和GL3。
例如，在显示的过程中，由于生成了M行栅极扫描信号，因此可以逐行打开M行像素单元。在P行栅极扫描信号驱动相应的P行像素单元(即P行子像素)打开的过程中，源极驱动器会向显示面板输送相应行对应的数据信号，使P行像素单元显示。在此过程中，由于M-P行补充栅极扫描信号与P行栅极扫描信号的开启时段存在重叠部分，因此，在P行栅极扫描信号驱动相应的P行像素单元打开的时间段内，M-P行补充栅极扫描信号会驱动其余的M-P行像素单元(即M-P行子像素)打开一段时间，因而，数据信号也会被写入该M-P行像素单元中，使该M-P行像素单元显示。因此，在逐行扫描完M行像素单元后，M行像素单元均可以显示。
例如，P行栅极扫描信号包括相邻的第i行栅极扫描信号和第i+1行栅极扫描信号。以第i行栅极扫描信号和第i+1行栅极扫描信号为例，步骤S230包括：基于第i行栅极扫描信号和第i+1行栅极扫描信号的时序，生成位于第i行栅极扫描信号和第i+1行栅极扫描信号的之间的B行补充栅极扫描信号；B行补充栅极扫描信号的上升沿在时序上均位于第i行栅极扫描信号的 上升沿和第i+1行栅极扫描信号的上升沿之间，B行补充栅极扫描信号的下降沿在时序上均位于第i行栅极扫描信号的下降沿和第i+1行栅极扫描信号的下降沿之间，i为小于P的正整数，B为小于等于M-P的正整数。
需要说明的是，该第i行和第i+1行是指信号行，即栅极扫描信号行，不同于显示面板的物理像素行。第i行栅极扫描信号也可称为第i个栅极扫描信号行，第i+1行栅极扫描信号也可称为第i+1个栅极扫描信号行。同样地，P行、M行和B行中的“行”均是栅极扫描信号行，P行栅极扫描信号也可以称为P个栅极扫描信号行，M行栅极扫描信号也可以称为M个栅极扫描信号行，B行补充栅极扫描信号也可以称为B个补充栅极扫描信号。
例如，在一些实施例中，B小于等于4，即在P行栅极扫描信号中的任意相邻两个栅极扫描信号行之间生成的补充栅极扫描信号行的行数小于等于4。基于这一方式，对于分辨率为4K或8K的显示面板，在基于补充后的栅极扫描信号进行图像展示的过程中，对于人眼不会产生明显的画面异常，可以达到良好的视觉效果。
例如，如图6所示，第i行栅极扫描信号例如为GL1，第i+1行栅极扫描信号例如为GL3，在时序上，在GL1和GL3之间的生成补充栅极扫描信号GL2的上升沿位于GL1的上升沿和GL3的上升沿之间，GL2的下降沿位于GL1的上升沿和GL3的下降沿之间，也就是说，GL2的开启时段位于其两侧的GL1和GL3的开启时段之间。在GL1对应的第一行像素单元处于打开状态的后半段时间T11内，GL2对应的第二行像素单元也处于打开状态，因此，在时间段T11内，第一行像素单元对应的显示数据也会被写入第二行像素单元，显示为第一行像素单元对应的亮度特征。并且，在GL3对应的第三行像素单元处于打开状态的前半段时间T21内，GL2对应的第二行像素单元也处于打开状态，因此，在这一时间段T21内，第三行像素单元对应的显示数据也会被写入第二行像素单元，显示为第三行像素单元对应的亮度特征。因此，GL2对应的第二行像素单元混合了第一行像素单元和第三行像素单元的亮度特征，可以使第二行像素单元称为第一行像素单元和第三行像素单元之间的颜色过渡。
例如，第i行栅极扫描信号的上升沿、B行补充栅极扫描信号的上升沿和第i+1行栅极扫描信号的上升沿在时序上依次顺延。第i行栅极扫描信号的下降沿、B行补充栅极扫描信号的下降沿和第i+1行栅极扫描信号的下降 沿在时序上依次顺延。例如，GL1的上升沿、GL2上升沿和GL3的上升沿依次顺延；GL1的下降沿、GL2下降沿和GL3的下降沿依次顺延。基于这一方式，可以使过渡更自然，保证像素颜色均匀过渡。
例如，在一些实施例中，可以对第i行栅极扫描信号的相位和第i+1行栅极扫描信号的相位进行插值运算，得到B行补充栅极扫描信号的相位。例如，对GL1和GL3的相位进行插值运算得到GL2的相位，使得GL2的开启时段位于GL1和GL3的开启时段的中间，时间段T11为T10的一半，时间段T21为T20的一半，这样可以使第一行像素单元、第二行像素单元和第三行像素单元的过渡更为自然。例如，以上仅以第i行栅极扫描信号和第i+1行栅极扫描信号之间生成一行补充栅极扫描信号为例进行说明，但是本公开不限于此，在第i行栅极扫描信号和第i+1行栅极扫描信号之间形成多行补充栅极扫描信号的情况下，同样可以采用插值运算的方式得到补充栅极扫描信号的相位。
例如，B行补充栅极扫描信号中的每行补充栅极扫描信号的上升沿和下降沿之间的时间差与第i行栅极扫描信号的上升沿和下降沿之间的时间差相同。例如，GL1的上升沿与下降沿之间的时间差T10、GL2的上升沿与下降沿之间的时间差T11+T21和GL3的上升沿与下降沿之间的时间差T20均相同。
图7为本公开至少一实施例提供的一种显示过程的示意图。图8为本公开至少一实施例提供的另一种显示过程的示意图。图7所示为显示面板的垂直分辨率M与待显示图像的显示数据的垂直分辨率P相同的情形，图8为显示面板的垂直分辨率M为待显示图像的显示数据的垂直分辨率P的两倍的情形。以下结合图7和图8对本公开实施例进行进一步地详细说明。
如图7所示，在M＝P的情况下，可以分别利用P行栅极扫描信号驱动M行像素单元。例如，GL1’～GLP’分别为根据P行显示数据生成的P行栅极扫描信号，GL1～GLM为时序控制器输出至显示面板的栅极扫描信号，由于M＝P，因而基于显示数据生成的多行栅极扫描信号可以一一对应输出。模拟数据信号1～M分别用于写入各行像素单元，表示各行数据单元显示的亮度特征(例如灰阶)。例如，第一行像素单元对应模拟数据信号1，在第一行栅极扫描信号GL1打开第一行像素单元的时间段内，模拟数据信号1写入第一行像素单元，使第一行像素单元具有亮度特征1。同理，在GL2～GLM逐 行打开第二行像素单元至第M行像素单元的过程中，模拟数据信号2～M逐行写入第二行像素单元至第M行像素单元，使第二行像素单元至第M行像素单元分别具有亮度特征2～亮度特征M。
例如，在M＝A*P的情况下，步骤S230包括：在P行栅极扫描信号中的每相邻两行栅极扫描信号之间，生成A-1行补充栅极扫描信号；在P行栅极扫描信号的至少一侧生成A-1行栅极扫描信号，A为大于1的整数。例如，若像素单元的行数M为显示数据的行数P的2倍，则在P行栅极扫描信号的每相邻两行之间分别生成一行补充栅极扫描信号，并在P行栅极扫描信号的一侧生成一行补充栅极扫描信号，例如在上侧或者下侧生成一个补充栅极扫描信号行。例如，可以采用如上描述的插值运算的方式生成补充栅极扫描信号。
如图8所示，P＝M/2，GL1’～GL(M/2)’分别为根据M/2行显示数据生成的M/2行栅极扫描信号，GL1～GLM为时序控制器输出至显示面板的栅极扫描信号，GL1～GLM包括GL1’～GL(M/2)’以及根据GL1’～GL(M/2)’生成的补充栅极扫描信号。例如，GL1’～GL(M/2)’可以分别作为输出信号中的奇数行GL1、GL3、GL5、…、GL(M-1)，然后在每两个相邻奇数行之间生成中间偶数行的补充栅极扫描信号GL2、GL4、GL6、…、GL(M-2)，并在最后一个偶数行生成一行补充栅极扫描信号GLM。
例如，若像素单元的行数M为显示数据的行数P的3倍，则在P行栅极扫描信号的每相邻两行之间分别生成两个补充栅极扫描信号行，并在P行栅极扫描信号的一侧(上侧或者下侧)生成两个补充栅极扫描信号行，或者可以分别在P行栅极扫描信号的两侧分别生成一个补充栅极扫描信号行。
例如，显示装置还包括与N列像素单元分别连接的N条数据信号线。如图8所示，可以分别基于P行像素数据，生成P行模拟数据信号。模拟数据信号1～P用于写入1～M行像素单元。为了便于描述，图中将模拟数据信号1～P以行方向排列，但是不代表模拟数据信号1～P位于一行中，模拟数据信号1～P对应不同行的像素单元。
例如，P行模拟数据信号包括第i行模拟数据信号(例如为第一行模拟数据信号)，第i行模拟数据信号包括Q个模拟数据信号(每行模拟数据信号可以包括多个信号，以分别对应多列)，在图8所示的示例中，第一行模拟信号包含的多个模拟数据信号均为模拟数据信号1。从利用第i行栅极扫 描信号驱动对应行像素单元的数据写入开关打开开始至利用第i+1行栅极扫描信号驱动对应行像素单元的数据写入开关打开之前的时间段内，将第i行模拟数据信号的Q个模拟数据信号分别输入N条数据信号线中的Q条数据信号线。例如，将第一行模拟数据信号中的Q个信号分别输入第一行中的Q个像素单元中，Q为小于等于N的正整数。
例如，每个模拟数据信号包括S个子模拟数据信号，Q个模拟数据信号包括Q*S个子模拟数据信号，可以将Q*S个子模拟数据信号分别输入N*S条子数据信号线中的Q*S条子数据信号线。例如，第一行的Q个像素单元包括Q*S个子像素，将第一行模拟数据信号中的Q个信号同样包括Q*S个子信号，因而，可以将第一行模拟数据信号中的Q*S个子信号分别写入第一行的Q*S个子像素中。
例如，如图8所示，在第一行栅极扫描信号GL1打开第一行像素单元的时间段内，模拟数据信号1写入第一行像素单元，使第一行像素单元具有亮度特征1。并且，在第一行像素单元打开的后半时间段内第二行像素单元也处于打开状态，因而，模拟数据信号1也可以写入第二行像素单元。在第三行栅极扫描信号GL3打开第三行像素单元的时间段内，模拟数据信号2写入第三行像素单元，使第三行像素单元具有亮度特征1。并且，在第三行像素单元打开的前半时间段内第二行像素单元也处于打开状态，因而，模拟数据信号2也可以写入第二行像素单元。由此，第二行像素单元可以显示为亮度特征1和亮度特征2的交替，呈现均匀地过渡。
显示面板奇数行栅线对应的模拟数据信号依次为源驱动IC输出的各行数据，偶数行(第M行除外)栅线对应的模拟数据信号均为其上下两行数据各持续一段时间的叠加，即本行像素单元实际充电过程为，先充上一行的像素数据一段时间，再充下一行的像素数据一段时间，故显示为上下两行像素数据的过渡，显示效果如图9所示。并且每行像素单元的实际充电时间为两行时间，进而提升了充电率，减少了因充电不足导致的画质不良。第M行对应的模拟数据信号为第M-1行模拟数据信号持续一段时间，显示为接近第M-1行。通过栅线信号插值加倍，实现了垂直分辨率的扩展。
图9为本公开至少一实施例提供的一种灰阶变化的示意图。如图9所示，沿用上述将P行栅极扫描信号(例如GL1’～GL8’)作为奇数行栅极扫描信号(例如GL1、GL3、…、GL15)并生成偶数行补充栅极扫描信号(例如GL2、 GL4、…、GL16)的示例。左侧的一列灰阶例如表示在栅极扫描信号扩充前的GL1’～GL8’分别对应的8行像素单元的亮度特征，右侧的一列灰阶例如表示在栅极扫描信号扩充后的GL1～GL16分别对应的16行像素单元的亮度特征。偶数行栅线扫描信号的相位为上下相邻两个奇数行栅线扫描信号的相位的插值，使得偶数行像素单元的灰阶为相邻的奇数行像素单元灰阶的过渡，不会引起色彩的混乱。例如，GL2的相位为GL1’(即GL1)和GL2’(即GL3)的相位的插值，GL2对应的一行像素单元的灰阶为上下两行像素单元的灰阶的插值，可以形成自然均匀的过渡。其他行同理，使得扩充后的整个显示画面呈现较好的显示效果。
图10为本公开至少一实施例提供的另一种显示过程的示意图。如图10所示，P＝M/2，GL1’～GL(M/2)’可以分别作为输出信号中的偶数行GL2、GL4、GL6、…、GLM，在第一个奇数行生成一行补充栅极扫描信号GL1，并且在每两个相邻偶数行之间生成中间奇数行的补充栅极扫描信号GL3、GL5、…、GL(M-1)。
例如，以上图8和图10均以A-1等于1为例进行了描述，在其他实施例中，若A-1大于1，A-1例如为2，除了在每相邻两行之间生成两行补充栅极扫描信号之外，还可以在P行栅极扫描信号的两侧共生成A-1行补充栅极扫描信号，例如在两侧各生成一行补充栅极扫描信号。
例如，以上介绍了待显示图像的垂直分辨率小于显示面板的垂直分辨率的处理方式，以下介绍待显示图像的水平分辨率小于显示面板的水平分辨率的处理方式。
例如，在显示数据的列数Q小于像素单元的列数N的情况下，执行数据补充操作，数据补充操作包括：基于Q列像素数据，生成N-Q列补充像素数据，Q列像素数据和N-Q列补充像素数据形成N列像素数据；基于形成的N列像素数据，生成N列模拟数据信号；将N列模拟数据信号分别输入N列像素单元。基于这一方式，可以补足数据信号，使得每列像素单元均有数据信号写入，提高水平分辨率。在以下的一些实施例中，像素信号、数据信号和像素数据信号均表示像素数据的信号。
例如，每个像素单元包括沿行方向排列的S个子像素单元，每个像素数据也可以理解为是S个子像素数据的集合，一个像素数据写入一个像素单元的过程可以理解为将S个子像素数据写入S个子像素的过程。在生成补充像 素数据的过程中，也可以是对相邻两列像素数据包含的S子像素数据分别进行插值运算，得到补充像素数据的S个子像素数据。
例如，该N-Q列补充像素数据中的至少部分列可以穿插在该Q列像素数据之间，也就是说，该Q列像素数据中的某相邻两列之间可以穿插有至少一列补充像素数据。N-Q列补充像素数据中的部分列也可以位于Q列像素数据的两侧。例如，在一种方式中，可以在Q列像素数据中的仅部分列之间生成补充像素数据；在另一种方式中，也可以在Q列像素数据中的每相邻两列之间均生成补充像素数据；在另一种方式中，也可以在Q列像素数据的一侧或两侧生成补充像素数据；或者可以是以上三种方式的组合。
数据补充操作例如可以由源极驱动器执行。图11为本公开至少一实施例提供的一种源极驱动器的示意图。如图11所示，源极驱动器包括串并转换模块141、缓存器模块142、功率放大模块143、数模转换模块144、模拟电压模块145和功率放大模块146。例如，串并转换模块141负责将时序控制板发送的串行数字数据信号转换为并行数字数据信号，并发送至缓存器模块142。缓存器模块142负责存储串并转换器发出的并行数字数据信号，并输出至分辨率转换模块143，每个子像素数据对应一个输出通道。分辨率转换模块143位于缓存器模块142和数模转换模块144之间，其作用为调整输入与输出信号数量的比例，例如根据已有的子像素数据生成补充子像素数据，转换动作在信号进入数模转换模块144之前完成，分辨率转换模块143例如包括多个运算模块(运算器)和相关连接走线。分辨率转换模块143将补充后的像素数据发送至数模转换模块144。分辨率转换模块143发送至数模转换模块144的信号为数字数据信号，数模转换模块144负责将数字数据信号结合模拟电压模块发送的模拟电压转换为模拟数据信号，并将模拟数据信号输出至功率放大模块146。源极驱动器可以包括多个数模转换模块，每个子像素数据对应一个数模转换模块，其输入和输出通道分别与缓存器模块的输出通道和功率放大模块的输入通道一一对应。
例如，功率放大模块146负责对每个通道进行输出能力的放大，其输出通道与显示面板数据信号线一一相连。数模转换模块144输出的模拟数据信号的极性由极性控制信号(即图示的极性control信号)控制，如对于某一帧待显示图像，提供一个极性控制信号，使得数模转换模块奇数通道输出电压为正极性，偶数通道输出电压为负极性，则显示面板奇数列子像素为正极 线电压驱动，偶数列为负极性电压驱动；下一帧时，进行奇偶列的正负极性切换。
例如，该Q列像素数据包括相邻的第j列像素数据和第j+1列像素数据。可以对第j列像素数据和第j+1列像素数据进行插值运算，生成位于第j列像素数据和第j+1列像素数据之间的D列补充像素数据，j为小于Q的正整数，D为小于等于N-Q的正整数。
图12为本公开至少一实施例提供的一种分辨率转换模块的输入信号和输出信号的示意图。如图12所示，例如，第j列像素数据和第j+1列像素数据例如分别为Q列像素数据中的第一列像素数据(例如以标识P_1’表示)和第二列像素数据(例如以标识P_2’表示)，在P_1’和P_2’之间例如插值运算形成一列补充像素数据(例如以标识P_2表示)，对列号重新调整后，P_1’例如为P_1，P_2’例如为P_3，补充像素数据列P_2位于P_1和P_3之间。由于P_2的像素数据为对P_1和P_3插值运算得到，因而，P_2对应的第二列像素单元的亮度特征为前后相邻的第一列像素单元和第三列像素单元的过渡，使画面过渡更为自然。
需要说明的是，该第j列和第j+1列是指信号列，即像素数据信号列，不同于显示面板的物理像素列。第j列像素数据也可称为第j个像素数据信号列(或第j个像素数据列)，第j+1列像素数据也可称为第j+1个像素数据信号列(或第j+1个像素数据列)。同样地，Q列、N列和D列中的“列”均是像素数据信号列，Q列像素数据也可以称为Q个像素数据列，N列像素数据也可以称为N个像素数据列，D列补充像素数据也可以称为D个补充像素数据列。
例如，在一些实施例中，D小于等于4，即在Q列像素数据中的任意相邻两个像素数据列之间生成的补充像素数据列的列数小于等于4。基于这一方式，对于分辨率为4K或8K的显示面板，在基于补充后的像素数据进行图像展示的过程中，对于人眼不会产生明显的画面异常，可以达到良好的视觉效果。
例如，在N＝C*Q的情况(即显示面板的水平分辨率为待显示图像的水平分辨率的整数倍的情况)下，可以在Q列像素数据中的每相邻两列像素数据之间，生成C-1列补充像素数据，并且可以在Q列像素数据的一侧或两侧共生成C-1列补充像素数据，以补足N列像素数据，C为大于1的整数。例 如，像素单元的列数N为显示数据的列数Q的2倍，则可以在Q列像素数据的每相邻两列之间分别生成一列补充像素数据，并在Q列像素数据的一侧(例如左侧或右侧)生成一列补充像素数据。
如图12所示，以N＝2Q为例，P_1’、P_2’、…、P_3Y’例如分别表示Q列像素数据，P_1’包含的ln1、ln2和ln3分别表示P_1’包含的三个子像素数据，其他像素数据同理。P_1、P_2、…、P_6Y例如分别表示补充后的N列像素数据，作为分辨率转换模块的输出信号。例如，P_1’～P_3Y’可以分别作为输出信号中的奇数列P_1、P_3、P_5、…、P_(6Y-1)，在每两个相邻奇数列之间生成中间偶数列的补充数据信号P_2、P_4、P_6、…、P_(6Y-2)，并且可以在最后一个偶数列生成补充数据信号P_6Y。
例如，若像素单元的列数N为显示数据的列数Q的3倍，则在Q列像素数据的每相邻两列之间分别生成两个补充像素数据列，并在Q列像素数据的一侧(左侧或者右侧)生成两个补充像素数据列，或者可以分别在Q列像素数据的两侧分别生成一个补充像素数据列。
图13为本公开至少一实施例提供的一种分辨率转换模块的示意图。如图13所示，分辨率转换模块包括多个运算器，可以通过运算器实现插值运算，输入端的每列像素信号可以依次作为输出端的奇数列，输出端的偶数列采用相邻两列奇数列像素数据通过运算器进行运算后输出，最后一列偶数列像素数据可以复制其前面一列奇数列像素数据。以P_1～P_3为例，在生成P_2的过程中，可以将P_1～P_3中相应颜色子像素的子像素数据进行插值运算，得到P_2中相应颜色子像素的子像素数据。例如，ln1、ln2和ln3分别代表R像素的子像素数据、G像素的子像素数据和B像素的子像素数据，ln4、ln5和ln6分别代表R像素的子像素数据、G像素的子像素数据和B像素的子像素数据，对ln1和ln4进行插值运算，得到P_2中R子像素的子像素数据O_4；对ln2和ln5进行插值运算，得到P_2中G子像素的子像素数据O_5；对ln3和ln6进行插值运算，得到P_2中B子像素的子像素数据O_6。运算器例如可以采用均值运算器。
图14为本公开至少一实施例提供的一种灰阶变化的示意图。如图14所示，沿用上述将Q列像素数据(例如P_1’～P_6’)作为奇数列像素数据信号(例如P_1、P_3、…、P_11)并生成偶数列补充像素数据信号(例如P_2、P_4、…、GL12)的示例。上侧的一行灰阶例如表示在像素数据扩充前的P_1’～ P_6’分别对应的6列像素单元的亮度特征，下侧的一行灰阶例如表示在像素数据扩充后的P_1～P_12分别对应的12列像素单元的亮度特征。偶数列像素数据的数值为左右相邻两个奇数列像素数据的插值(例如为均值)，使得偶数列像素单元的灰阶为相邻的奇数列像素单元灰阶的过渡，不会引起色彩的混乱，使得扩充后的整个显示画面呈现较好的显示效果。
图15为本公开至少一实施例提供的另一种分辨率转换模块的输入信号和输出信号的示意图。如图15所示，同样以N＝2Q为例，P_1’～P_3Y’可以分别作为输出信号中的偶数列P_2、P_4、P_6、…、P_6Y，在第一列P_1生成补充像素数据，第一列P_1可以复制第二列P_2的像素数据，并且每两个相邻偶数列之间生成中间奇数列的补充数据信号P_1、P_3、P_5、…、P_(6Y-1)。
图16为本公开至少一实施例提供的另一种源极驱动器中输入像素数据和输出像素数据的示意图。如图16所示，例如，在Q等于N的情况下，可以基于Q列像素数据，分别生成Q列模拟数据信号，其中，Q列模拟数据信号分别用于输入N列像素单元。这种情况下，无需进行插值运算。
图17为本公开至少一实施例提供的另一种时序控制器的示意图。如图17所示，例如，时序控制器还可以包括模式控制模块，模式控制模块配置为接收模式指令，并基于模式指令向栅线信号生成模块和/或源驱动芯片发送控制信号，以控制栅极信号生成模块是否执行栅极信号补充操作和/或控制源驱动芯片是否执行数据补充操作。模式指令可以通过自动检测待显示图像的分辨率并将其与显示面板的物理分辨率进行比较得到，也可以通过用户输入得到。
图18为本公开至少一实施例提供的另一种源驱动芯片的示意图。如图18所示，例如，时序控制器发送至源驱动芯片的控制信号(模式控制信号)可以作用于分辨率转换模块，以控制分辨率转换模块执行或不执行数据补充操作。
例如，时序控制板增加一模式控制模块，负责模式指令的接收与发送。一方面，可以发送模式切换指令给栅线信号生成模块，来选择是否使用插值运算功能；另一方面，可以发送模式切换指令给源驱动IC，调整源驱动IC输入和输出信号数量的比例。插值运算功能的开启和关闭，可以通过在其前端加一开关器件实现。
图19为本公开至少一实施例提供的另一种分辨率转换模块的示意图。如图19所示，分辨率转换模块还包括多个双通开关和模式切换模块(图中未示出)。每个双通开关包括一个输入端和两个输出端，双通开关的输入端连接缓存模块，用于接收一列像素数据，其中一个输出端连接至多个数模转换模块中的至少一个，另一个输出端连接至多个运算模块中的至少一个。模式切换模块配置为基于模式控制模块发送的控制信号控制双通开关将一列像素数据输出至两个输出端中的一个。例如，显示装置的工作模式包括普通模式和分辨率扩展模式，在普通模式下，双通开关将信号直接输出至数模转换模块，无需进行插值运算；在分辨率扩展模式下，双通开关将信号输出至运算器，进行插值运算后在输入数模转换模块。
例如，当检测到显示信号分辨率与显示面板的物理分辨率匹配时，模式指令为普通模式。在普通模式下，一方面，时序控制板发送普通模式控制指令给栅极信号生成器，栅极信号生成器的插值运算功能关闭，输出的栅极扫描信号即与显示面板的栅线一一对应，如图7所示。另一方面，时序控制板发送普通模式控制指令给源驱动IC，分辨率转换模块中的双通开关的输入通路与双通开关的输出通路是相同编号的输入与输出，输出信号不经过运算器，源驱动IC的运算器不起作用，如图16所示。
例如，当时序控制板接收到的显示信号分辨率与显示面板的物理分辨率不匹配时，模式指令为以分辨率扩展模式。
例如，在一些实施例中，当显示信号的垂直分辨率为显示面板的垂直分辨率的一半并且水平分辨率相同时，时序控制板发送垂直分辨率扩展模式控制指令给栅线信号生成器，启动插值运算功能，如图12或图15所示。时序控制板发送普通模式控制指令给源驱动IC，使其输入与输出一一对应。
例如，在另一些实施例中，当显示信号水平分辨率为显示面板的水平分辨率的一半并且垂直分辨率相同时，时序控制板发送普通模式控制指令给栅线信号生成器，插值运算功能关闭，输出栅线信号同显示面板的栅线一一对应。时序控制板发送水平分辨率扩展模式控制指令给源驱动IC，此时，源驱动IC中的双通开关将输入信号导向运算器，例如，输入通道In_1，In_2，In_3对应前三个输出通道O_1，O_2，O_3；运算器1输出In_1和In_4的插值运算结果，对应输出通道O_4；运算器2输出In_2和In_5的插值运算结果，对应输出通道O_5；运算器3输出In_3和In_6的插值运算结果，对应输出 通道O_6；选择开关1输出In_4，对应输出通道O_7；选择开关2输出In_5，对应输出通道O_8；选择开关3输出In_6，对应输出通道O_9；依次类推，输入列依次作为输出的奇数列，偶数列为相邻奇数列的运算结果，将源驱动IC接收的数字数据信号和输出的模拟数据信号比例变为1:2。
例如，在另一些实施例中，当显示信号水平分辨率为显示面板的水平分辨率的一半并且显示信号的垂直分辨率也为显示面板的垂直分辨率的一半时，时序控制板发送垂直分辨率扩展模式控制指令给栅线信号生成器，插值运算功能开启，输出栅线信号与面板栅线比例为1:1。时序控制板发送水平分辨率扩展模式控制指令给源驱动IC，输入与输出比例为1:2。
图20为本公开至少一实施例提供的一种待显示图像的示意图。如图20所示，在一些情况下，连续多张待显示图像均具有两种亮度特征在不同列交替显示的画面，例如，呈现最亮特征301和最暗特征302在不同列交替显示的画面。或者，多于两种亮度特征在不同列交替显示，例如三种或四种亮度特征交替显示。对于这一类画面，若采用相邻列的像素数据进行插值的方式得到补充像素数据，那么会出现画面中原本没有的亮度特征，例如，对最亮特征301和最暗特征302进行插值会出现一个位于最亮和最暗之间的灰度特征，造成画面失真，为了避免这一问题，可以采用如下的方式进行处理。
例如，可以先确定连续多帧待显示图像的显示数据是否符合交替显示规律，符合交替显示规律的显示数据的Q列像素数据在g个像素值之间循环，g个像素值分别对应g种亮度特征(例如两种或更多种亮度特征)。若是，将多帧待显示图像分为多个图组，每个图组包括相邻的g帧待显示图像，针对每个图组执行以下操作：若当前帧待显示图像为图组中的第k帧待显示图像，将第k帧待显示图像的Q列像素数据均变换为g个像素值中的第k个像素值；对于变换后的Q列像素数据，执行数据补充操作；基于数据补充操作后的第k+n*g列像素数据生成模拟数据信号并分别输入第k+n*g列像素单元，以使第k+n*g列像素单元显示为g种亮度特征中的第k种亮度特征，其中，在k为大于1的正整数的情况下，除第k+n*g列像素单元之外的其余列像素单元显示为第k帧待显示图像的上一帧待显示图像对应的亮度特征；在k等于1的情况下，除第k+n*g列像素单元之外的其余列像素单元不显示，n取0至[Q/g-1]的全部整数，g为大于1且小于Q的整数，k为小于等于g的整数。
例如，时序控制板可以增加图像识别功能，以识别特殊显示画面，该特 殊画面具备至少两个亮度特征，且为列别交替显示。
如图20所示，以两种亮度特征在各列中交替显示，即在两个像素值之间循环显示为例，例如在最亮和最暗之间交替显示。图21为本公开至少一实施例提供的另一种显示装置的示意图，如图21所示，时序控制板输出控制信号到源驱动IC，控制输出通道的开启与关闭，进而控制对应的各列像子像素是否显示。图22为本公开至少一实施例提供的另一种分辨率转换模块的示意图。如图22所示，分辨率转换模块增加开关模块，开关模块可以关闭或开启相应列的数模转换功能。
例如，若未检测到符合要求的显示画面时，时序控制板正常输出画面，输出控制信号控制源驱动IC所有输出通道开启，正常输出，在水平分辨率不足时可以进行插值运算。若时序控制板检测到特殊显示画面(例如两种亮度特征在不同列交替显示的画面)并且水平分辨率不足时，时序控制板可以根据亮度特征进行拆分，并形成每个特征的全区域画面，依次交替输出；同时，在显示任意一特征画面时，通过输出控制信号关闭其他特征对应的源驱动IC输出通道。以两种亮度特征交替显示的情况为例，如图23所示，对于第E帧(E为正整数)画面，时序控制板输出给源驱动IC全区域的最亮(第一特征)显示画面，即奇数列输入数据为最亮，偶数列计算结果也为最亮；同时，发送输出控制信号给源驱动IC，关闭最暗(第二特征)对应的偶数像素列数模转换模块，即4/5/6，10/11/12…关闭，此时奇数列同输入信号显示为最亮，偶数列显示为上一帧(第E-1帧)的画面，假设为某一灰阶。如图24所示，第E+1帧时，输出给源驱动IC全区域的最暗(特征二)显示画面，即每列均为最暗，同时，发送输出控制信号给源驱动IC，关闭最亮(特征一)对应的奇数像素列数模转换模块，即1/2/3，7/8/9…关闭，此时偶数列因奇数列输入的是最暗，运算结果也为最暗，即输出显示为最暗，此时奇数列显示为上一帧的画面，为最亮。
重复第E帧和第E+1帧的动作，画面始终保持为图24，即实现了特殊画面的显示。
例如，对于两种以上亮度特征交替显示的情况同理。为了便于描述，可以将多帧待显示图像根据亮度特征的数量分组，每组包含的待显示图像的数量与亮度特征的数量相等。以连续12帧待显示图像均呈现三种颜色特征(第一特征、第二特征和第三特征)在不同列交替显示为例，可以将12帧图像 分为4组，每组包含3帧图像。对于每组中的第一帧图像，将该第一帧图像变换为全区域显示第一特征，插值运算后，使第1、4(即1+3)、7(即1+2*3)和10(即1+3*3)列执行数模转换，以使这些列的像素单元呈现第一特征，其余列(2-3、5-6、8-9和11-12)均呈现为上一帧画面中相应列的特征，若没有上一帧则这些列不显示。对于每组中的第二帧图像，将该第二帧图像变换为全区域显示第二特征，插值运算后，使第2、5(即2+3)、8(即2+2*3)、11(即2+3*3)列执行数模转换，以使这些列的像素单元呈现第二特征，其余列均为上一帧画面中相应列的特征，即第1、4、7和10仍呈现第一特征。对于每组中的第三帧图像，将该第三帧图像变换为全区域显示第三特征，插值运算后，使第3、6(即3+3)、9(即3+2*3)、12(即3+3*3)列执行数模转换，以使这些列的像素单元呈现第三特征，其余列均为上一帧的画面，即第1、4、7和10仍呈现第一特征、以及第2、5、8和11列仍呈现第二特征，至此，每三列像素单元依次呈现第一特征、第二特征和第三特征。对于下一组图像，仍采用上述方式，可以实现每帧均呈现第一特征、第二特征和第三特征交替显示的画面，实现了这种特殊画面的显示。
基于以上方式，对于水平分辨率不足并且列别交替显示特定数量的亮度特征的画面，不仅可以实现扩增水平分辨率的目的，并且可以避免插值出现不需要的亮度特征，保证画面显示效果。
例如，在一些实施例中，显示信号垂直分辨率为显示面板物理分辨率一半时，进行垂直分辨率扩展：时序控制板对栅线信号进行插值，行信号频率提升一倍，数据线信号输出不变，即插值运算前一行的数据时间对应插值后两行的时间；第一行或最后一行无相邻两行的，则参照其它行插值后的相位差进行提前或延后插入。
例如，在一些实施例中，显示信号水平分辨率为显示面板物理分辨率一半时，进行水平分辨率扩展：通过源驱动IC的分辨率转换模块依次将输入端每列像素数据信号作为输出的奇数列或偶数列，输出的另一半由其相邻两列计算而来；输出端第一列或最后一列无相邻两列的，则采用跟随输入端数据的第一列或最后一列；分辨率转换模块介于缓存器和数模转换模块之间，转换动作在信号进入数模转换模块之前完成；分辨率转换模块的转换动作是由对应的子像素分别进行的，不同子像素间不进行转换、计算；相邻列间的运算器为模拟电路运算器件。
例如，在一些实施例中，垂直分辨率扩展和水平分辨率扩展，两个功能相对独立，互不干扰。
例如，在一些实施例中，匹配本公开实施例的信号处理方法的显示面板架构为：栅线沿水平向排布，数据线沿垂直方向排布；一个像素单元包含若干个子像素，且沿栅线方向排布；同一列子像素均为同一子像素，且在一帧时间内极性相同。
例如，在一些实施例中，具备模式控制功能，分别对应显示信号垂直分辨率为显示面板物理分辨率一半并且水平分辨率相同的情况、显示信号水平分辨率为显示面板物理分辨率一半并且垂直分辨率相同的情况、显示信号垂直和水平分辨率均为显示面板物理分辨率一半的情况、显示信号垂直和水平分辨率均与显示面板物理分辨率一致的情况进行对应的处理。
例如，在一些实施例中，时序控制板接收模式指令；时序控制板发送模式指令给栅线信号生成模块来调整输出行信号的数量；时序控制板发送模式指令给源驱动IC，使输入信号与输出的比例例如在1:1和1:2之间切换。
例如，在一些实施例中，栅线信号生成模块调整输出行信号数量的方式：插值运算功能前增加控制开关，垂直分辨率为面板一半时，开关打开，启用插值运算功能，运算后输出插值行栅线信号，否则关闭开关，输出信号数量不变。
例如，在一些实施例中，源驱动IC输入通道数量与输出通道是一致，源驱动IC输入与输出信号比例切换的通道连接方式为：对于源驱动IC输入通道的前一半通道，连接开关器件后依次与输出通道的前一半一一相连，连接开关器件后依次与输出端的奇数列或偶数列一一相连，以及连接开关器件后，两两之间相互运算，运算器输出口依次与输出端的偶数通道或奇数通道相连；对于输入通道的后一半通道，连接开关器件后依次与输出端的后一半通道一一相连。开关器件由模式指令控制，显示信号水平分辨率为显示面板的一半时，通过开关关闭输入通道的后一半，通过开关开启输入通道的前一半，且输出至输出端的奇数列或偶数列，及运算器；显示信号水平分辨率与显示面板一致时，通过开关开启输入通道的后一半；通过开关开启输入通道的前一半，且输出至输出通道的前一半。
例如，在一些实施例中，时序控制板具备画面识别功能，可以识别特殊画面，并根据特殊画面的特征调整输出图形，发送对应的输出控制指令给源 驱动IC，进行分时显示，最终叠加后行成所需画面。特殊画面至少具备两个亮度特征，且为列别交替显示。时序控制板对识别到的特殊画面按特征数量进行拆分，并形成每个特征的全区域画面，依次交替输出。在时序控制板输出某一特征的全区域画面时，输出控制信号至源驱动IC，关闭其它特征对应的输出通道。输出控制信号控制源驱动IC各通道的输出方式，可以为控制各数模转换模块的开启与关闭，也可以为控制功率放大模块各通道的开启与关闭。
本公开一些实施例的信号处理方法，在显示信号垂直分辨率和/或水平分辨率与显示信号垂直分辨率和/或水平分辨率不匹配(例如显示信号垂直分辨率和/或水平分辨率为显示面板物理分辨率一半)的情况下，显示系统可以进行正常显示。
本公开一些实施例的信号处理方法，实现了显示面板的物理分辨率大于显示信号的分辨率，显示效果与显示面板物理分辨率对应的显示效果接近。
本公开一些实施例的信号处理方法，可以通过降低对显示信号分辨率的要求，降低对输出显示信号的系统芯片的要求，降低系统板与时序控制板之间数据传输速率的需求，降低时序控制板与源驱动芯片之间数据传输速率的要求，降低对时序控制芯片和源驱动芯片的要求，进而极大降低成本，在面对超高分辨率、超高刷新率面板的需求时，使得更容易实现，成本更低。
本公开一些实施例的信号处理方法，在显示信号分辨率与显示面板分辨率一致时也可以正常输出，提升了灵活性。
本公开一些实施例的信号处理方法，源驱动IC具备普适性，避免了使用成本的提高。
本公开一些实施例的信号处理方法，解决了垂直隔列显示等特殊画面无法正常显示的问题，提升了显示画质。
本公开一些实施例的信号处理方法，通过像素充电时间加倍提升了充电率，减少充电不足导致的画质问题，提升了画质。
本公开实施例还提供一种显示装置。如图1或图4所示，该显示装置包括显示基板和时序控制器，显示基板包括阵列排布的M行N列像素单元；时序控制器包括数据接收模块和栅极信号生成模块。
数据接收模块配置为获取一帧待显示图像的显示数据，其中，显示数据包括阵列排布的P行Q列像素数据。栅极信号生成模块配置为：对应P行 像素数据，生成P行栅极扫描信号；在P小于M的情况下，执行栅极信号补充操作，其中，栅极信号补充操作包括：基于P行栅极扫描信号，生成M-P行补充栅极扫描信号，其中，P行栅极扫描信号和M-P行补充栅极扫描信号形成M行栅极扫描信号，以分别利用该M行栅极扫描信号驱动M行像素单元；P、Q、M和N均为正整数。
例如，显示装置还包括源驱动芯片，源驱动芯片通过多条沿与第一方向交叉的第二方向延伸的数据信号线与M行N列像素单元连接，以向M行N列像素单元提供模拟数据信号，其中，源驱动芯片配置为：在Q小于N的情况下，执行数据补充操作，其中，数据补充操作包括：基于Q列像素数据，生成N-Q列补充像素数据，Q列像素数据和N-Q列补充像素数据形成N列像素数据；基于该N列像素数据，生成N列模拟数据信号；将N列模拟数据信号分别输入N列像素单元。
例如，源驱动芯片包括缓存模块、多个运算模块和多个数模转换模块，缓存模块配置为缓存显示数据；多个运算模块配置为执行数据补充操作，得到N-Q列补充像素数据；多个数模转换模块配置为将该N列像素数据转换为N列模拟数据信号。
例如，时序控制器还包括模式控制模块，模式控制模块配置为接收模式指令，并基于模式指令向栅极信号生成模块和/或源驱动芯片发送控制信号，以控制栅极信号生成模块是否执行栅极信号补充操作和/或控制源驱动芯片是否执行数据补充操作。
例如，源驱动芯片还包括多个双通开关和模式切换模块，每个双通开关包括一个输入端和两个输出端，输入端连接缓存模块，用于接收一列像素数据，其中一个输出端连接至多个数模转换模块中的至少一个，另一个输出端连接至多个运算模块中的至少一个；模式切换模块配置为基于模式控制模块发送的控制信号控制双通开关将一列像素数据输出至两个输出端中的一个。
例如，时序控制器还包括图像识别模块，图像识别模块配置为：识别连续多帧待显示图像的显示数据是否符合交替显示规律，其中，符合交替显示规律的显示数据的Q列像素数据在g个像素值之间循环，g个像素值分别对应g种亮度特征；若是，将多帧待显示图像分为多个图组，每个图组包括相邻的g帧待显示图像，并针对每个图组执行：若当前帧待显示图像为图组中 的第k帧待显示图像，将第k帧待显示图像的Q列像素数据均变换为g个像素值中的第k个像素值；将变换后的Q列像素数据输出至源驱动芯片；
源驱动芯片还配置为：对于变换后的Q列像素数据，执行数据补充操作；基于数据补充操作后的第k+n*g列像素数据生成模拟数据信号并分别输入第k+n*g列像素单元，以使第k+n*g列像素单元显示为g种亮度特征中的第k种亮度特征，其中，在k为大于1的正整数的情况下，除第k+n*g列像素单元之外的其余列像素单元显示为第k帧待显示图像的上一帧待显示图像对应的亮度特征；在k等于1的情况下，除第k+n*g列像素单元之外的其余列像素单元不显示，其中，n取0至[Q/g-1]的全部整数，g为大于1且小于Q的整数，k为小于等于g的整数。
本公开至少一个实施例提供一种电子设备，包括本公开任一实施例提供的显示装置。例如，该电子设备可以包括手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的电子产品中。
图25为本公开一些实施例提供的另一种电子设备的示意框图。如图25所示，该电子设备400包括处理器410和存储器420。存储器420用于存储非暂时性计算机可读指令(例如一个或多个计算机程序模块)。处理器410用于运行非暂时性计算机可读指令，非暂时性计算机可读指令被处理器410运行时可以执行上文所述的信号处理方法中的一个或多个步骤。存储器420和处理器410可以通过总线系统和/或其它形式的连接机构(未示出)互连。
例如，处理器410可以是中央处理单元(CPU)、图形处理单元(GPU)或者具有数据处理能力和/或程序执行能力的其它形式的处理单元。例如，中央处理单元(CPU)可以为X86或ARM架构等。处理器410可以为通用处理器或专用处理器，可以控制电子设备400中的其它组件以执行期望的功能。
例如，存储器420可以包括一个或多个计算机程序产品的任意组合，计算机程序产品可以包括各种形式的计算机可读存储介质，例如易失性存储器和/或非易失性存储器。易失性存储器例如可以包括随机存取存储器(RAM)和/或高速缓冲存储器(cache)等。非易失性存储器例如可以包括只读存储器(ROM)、硬盘、可擦除可编程只读存储器(EPROM)、便携式紧致盘只读存储器(CD-ROM)、USB存储器、闪存等。在计算机可读存储介质上可以存储一个或多个计算机程序模块，处理器410可以运行一个或多个计算机程序模块，以实现电子设备400的各种功能。在计算机可读存储介质中还可 以存储各种应用程序和各种数据以及应用程序使用和/或产生的各种数据等。
需要说明的是，本公开的实施例中，电子设备400的具体功能和技术效果可以参考上文中关于信号处理方法的描述，此处不再赘述。
图26为本公开一些实施例提供的另一种电子设备的示意框图。该电子设备500例如适于用来实施本公开实施例提供的信号处理方法。电子设备500可以是终端设备等。需要注意的是，图26示出的电子设备500仅仅是一个示例，其不会对本公开实施例的功能和使用范围带来任何限制。
如图26所示，电子设备500可以包括处理装置(例如中央处理器、图形处理器等)510，其可以根据存储在只读存储器(ROM)520中的程序或者从存储装置580加载到随机访问存储器(RAM)530中的程序而执行各种适当的动作和处理。在RAM 530中，还存储有电子设备500操作所需的各种程序和数据。处理装置510、ROM 520以及RAM530通过总线540彼此相连。输入/输出(I/O)接口550也连接至总线540。
通常，以下装置可以连接至I/O接口550：包括例如触摸屏、触摸板、键盘、鼠标、摄像头、麦克风、加速度计、陀螺仪等的输入装置560；包括例如液晶显示器(LCD)、扬声器、振动器等的输出装置570；包括例如磁带、硬盘等的存储装置580；以及通信装置590。通信装置590可以允许电子设备500与其他电子设备进行无线或有线通信以交换数据。虽然图26示出了具有各种装置的电子设备500，但应理解的是，并不要求实施或具备所有示出的装置，电子设备500可以替代地实施或具备更多或更少的装置。
例如，根据本公开的实施例，上述信号处理方法可以被实现为计算机软件程序。例如，本公开的实施例包括一种计算机程序产品，其包括承载在非暂态计算机可读介质上的计算机程序，该计算机程序包括用于执行上述信号处理方法的程序代码。在这样的实施例中，该计算机程序可以通过通信装置590从网络上被下载和安装，或者从存储装置580安装，或者从ROM 520安装。在该计算机程序被处理装置510执行时，可以实现本公开实施例提供的信号处理方法中限定的功能。
本公开的至少一个实施例还提供了一种计算机可读存储介质，该计算机可读存储介质用于存储非暂时性计算机可读指令，当非暂时性计算机可读指令由计算机执行时可以实现上述的信号处理方法。
图27为本公开一些实施例提供的一种存储介质的示意图。如图27所示， 存储介质600用于存储非暂时性计算机可读指令610。例如，当非暂时性计算机可读指令610由计算机执行时可以执行根据上文所述的信号处理方法中的一个或多个步骤。
例如，该存储介质600可以应用于上述电子设备400中。例如，存储介质600可以为图25所示的电子设备400中的存储器420。例如，关于存储介质600的相关说明可以参考图25所示的电子设备400中的存储器420的相应描述，此处不再赘述。
有以下几点需要说明：
(1)本公开实施例附图只涉及到本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (24)

  1. 一种信号处理方法，用于显示装置，所述显示装置包括显示基板，所述显示基板包括阵列排布的M行N列像素单元，所述信号处理方法包括：
    获取一帧待显示图像的显示数据，其中，所述显示数据包括阵列排布的P行Q列像素数据；
    对应所述P行像素数据，生成P行栅极扫描信号；
    在P小于M的情况下，基于所述P行栅极扫描信号，生成M-P行补充栅极扫描信号，其中，所述P行栅极扫描信号和所述M-P行补充栅极扫描信号形成M行栅极扫描信号；
    分别利用所述M行栅极扫描信号驱动所述M行像素单元；
    其中，P、Q、M和N均为正整数。
  2. 根据权利要求1所述的信号处理方法，其中，在M＝A*P的情况下，基于所述P行栅极扫描信号，生成M-P行补充栅极扫描信号，包括：
    在所述P行栅极扫描信号中的每相邻两行栅极扫描信号之间，生成A-1行补充栅极扫描信号；
    在所述P行栅极扫描信号的至少一侧生成A-1行栅极扫描信号；
    其中，A为大于1的整数。
  3. 根据权利要求1所述的信号处理方法，其中，所述P行栅极扫描信号包括相邻的第i行栅极扫描信号和第i+1行栅极扫描信号；
    基于所述P行栅极扫描信号，生成M-P行补充栅极扫描信号，包括：
    基于所述第i行栅极扫描信号和所述第i+1行栅极扫描信号的时序，生成位于所述第i行栅极扫描信号和所述第i+1行栅极扫描信号的之间的B行补充栅极扫描信号；
    其中，所述B行补充栅极扫描信号的上升沿在时序上均位于所述第i行栅极扫描信号的上升沿和第i+1行栅极扫描信号的上升沿之间，所述B行补充栅极扫描信号的下降沿在时序上均位于所述第i行栅极扫描信号的下降沿和第i+1行栅极扫描信号的下降沿之间，
    其中，i为小于P的正整数，B为小于等于M-P的正整数。
  4. 根据权利要求3所述的信号处理方法，其中，所述第i行栅极扫描信号的上升沿、所述B行补充栅极扫描信号的上升沿和所述第i+1行栅极扫描信号的上升沿在时序上依次顺延；
    所述第i行栅极扫描信号的下降沿、所述B行补充栅极扫描信号的下降沿和所述第i+1行栅极扫描信号的下降沿在时序上依次顺延。
  5. 根据权利要求3所述的信号处理方法，其中，基于所述第i行栅极扫描信号和所述第i+1行栅极扫描信号的时序，生成位于所述第i行栅极扫描信号和所述第i+1行栅极扫描信号的之间的B行补充栅极扫描信号，包括：
    对所述第i行栅极扫描信号的相位和所述第i+1行栅极扫描信号的相位进行插值运算，得到所述B行补充栅极扫描信号的相位。
  6. 根据权利要求3所述的信号处理方法，其中，所述B行补充栅极扫描信号中的每行补充栅极扫描信号的上升沿和下降沿之间的时间差与所述第i行栅极扫描信号的上升沿和下降沿之间的时间差相同。
  7. 根据权利要求1所述的信号处理方法，其中，每个像素单元包括S个子像素，位于同一像素单元的S个子像素沿行方向排布，所述N列像素单元包括N*S列子像素；
    位于同一列的子像素在一帧待显示图像的显示时间内极性相同，
    其中，S为正整数。
  8. 根据权利要求1所述的信号处理方法，还包括：
    在P等于M的情况下，分别利用所述P行栅极扫描信号驱动所述M行像素单元。
  9. 根据权利要求3所述的信号处理方法，其中，所述显示装置还包括与所述N列像素单元分别连接的N条数据信号线；
    所述信号处理方法还包括：
    分别基于所述P行像素数据，生成P行模拟数据信号，其中，所述P行模拟数据信号包括第i行模拟数据信号，所述第i行模拟数据信号包括Q个模拟数据信号；
    从利用所述第i行栅极扫描信号驱动对应行像素单元的数据写入开关打开开始至利用所述第i+1行栅极扫描信号驱动对应行像素单元的数据写入开关打开之前的时间段内，将所述第i行模拟数据信号的Q个模拟数据信号分别输入所述N条数据信号线中的Q条数据信号线。
  10. 根据权利要求9所述的信号处理方法，其中，每个所述像素单元包括S个子像素，所述N列像素单元包括N*S列子像素，所述N条数据信号线包括分别与所述N*S列子像素连接的N*S条子数据信号线；
    每个所述模拟数据信号包括S个子模拟数据信号，所述Q个模拟数据信号包括Q*S个子模拟数据信号；
    将所述第i行模拟数据信号的Q个模拟数据信号分别输入所述N条数据信号线中的Q条数据信号线，包括：
    将所述Q*S个子模拟数据信号分别输入所述N*S条子数据信号线中的Q*S条子数据信号线。
  11. 根据权利要求1至10任一项所述的信号处理方法，还包括：
    在Q小于N的情况下，执行数据补充操作，其中，所述数据补充操作包括：基于所述Q列像素数据，生成N-Q列补充像素数据，所述Q列像素数据和所述N-Q列补充像素数据形成N列像素数据；
    基于所述N列像素数据，生成N列模拟数据信号；
    将所述N列模拟数据信号分别输入所述N列像素单元。
  12. 根据权利要求11所述的信号处理方法，其中，在N＝C*Q的情况下，基于所述Q列像素数据，生成N-Q列补充像素数据，包括：
    在所述Q列像素数据中的每相邻两列像素数据之间，生成C-1列补充像素数据；
    在所述Q列像素数据的至少一侧生成C-1列补充像素数据；
    其中，C为大于1的整数。
  13. 根据权利要求11所述的信号处理方法，其中，所述Q列像素数据包括相邻的第j列像素数据和第j+1列像素数据；
    基于所述Q列像素数据，生成N-Q列补充像素数据，包括：
    对所述第j列像素数据和所述第j+1列像素数据进行插值运算，生成位于所述第j列像素数据和所述第j+1列像素数据之间的D列补充像素数据；
    其中，j为小于Q的正整数，D为小于等于N-Q的正整数。
  14. 根据权利要求11所述的信号处理方法，还包括：
    在Q等于N的情况下，基于所述Q列像素数据，分别生成Q列模拟数据信号，其中，所述Q列模拟数据信号分别用于输入所述N列像素单元。
  15. 根据权利要求13所述的信号处理方法，还包括：
    确定连续多帧待显示图像的显示数据是否符合交替显示规律，其中，符合所述交替显示规律的显示数据的Q列像素数据在g个像素值之间循环，所述g个像素值分别对应g种亮度特征；
    若是，将所述多帧待显示图像分为多个图组，每个图组包括相邻的g帧待显示图像，针对每个图组执行以下操作：
    若当前帧待显示图像为所述图组中的第k帧待显示图像，将所述第k帧待显示图像的Q列像素数据均变换为所述g个像素值中的第k个像素值；
    对于变换后的Q列像素数据，执行所述数据补充操作；
    基于所述数据补充操作后的第k+n*g列像素数据生成模拟数据信号并分别输入第k+n*g列像素单元，以使所述第k+n*g列像素单元显示为所述g种亮度特征中的第k种亮度特征，
    其中，在k为大于1的正整数的情况下，除所述第k+n*g列像素单元之外的其余列像素单元显示为所述第k帧待显示图像的上一帧待显示图像对应的亮度特征；在k等于1的情况下，除所述第k+n*g列像素单元之外的其余列像素单元不显示，
    其中，n取0至[Q/g-1]的全部整数，g为大于1且小于Q的整数，k为小于等于g的整数。
  16. 一种显示装置，包括：
    显示基板，包括阵列排布的M行N列像素单元；
    时序控制器，包括数据接收模块和栅极信号生成模块；
    其中，所述数据接收模块配置为获取一帧待显示图像的显示数据，其中，所述显示数据包括阵列排布的P行Q列像素数据；
    所述栅极信号生成模块配置为：
    对应所述P行像素数据，生成P行栅极扫描信号；
    在P小于M的情况下，执行栅极信号补充操作，其中，所述栅极信号补充操作包括：基于所述P行栅极扫描信号，生成M-P行补充栅极扫描信号，其中，所述P行栅极扫描信号和所述M-P行补充栅极扫描信号形成M行栅极扫描信号，以分别利用所述M行栅极扫描信号驱动所述M行像素单元；
    其中，P、Q、M和N均为正整数。
  17. 根据权利要求16所述的显示装置，还包括：
    源驱动芯片，通过多条沿与所述第一方向交叉的第二方向延伸的数据信号线与所述M行N列像素单元连接，以向所述M行N列像素单元提供模拟数据信号，其中，所述源驱动芯片配置为：
    在Q小于N的情况下，执行数据补充操作，其中，所述数据补充操作包括：基于所述Q列像素数据，生成N-Q列补充像素数据，所述Q列像素数据和所述N-Q列补充像素数据形成N列像素数据；
    基于所述N列像素数据，生成N列模拟数据信号；
    将所述N列模拟数据信号分别输入所述N列像素单元。
  18. 根据权利要求17所述的显示装置，其中，所述源驱动芯片包括：
    缓存模块，配置为缓存所述显示数据；
    多个运算模块，配置为执行所述数据补充操作，得到所述N-Q列补充像素数据；
    多个数模转换模块，配置为将所述N列像素数据转换为所述N列模拟数据信号。
  19. 根据权利要求18所述的显示装置，其中，所述时序控制器还包括：
    模式控制模块，配置为接收模式指令，并基于所述模式指令向所述栅极信号生成模块和/或所述源驱动芯片发送控制信号，以控制所述栅极信号生成模块是否执行所述栅极信号补充操作和/或控制所述源驱动芯片是否执行所述数据补充操作。
  20. 根据权利要求19所述的显示装置，其中，所述源驱动芯片还包括：
    多个双通开关，其中，每个所述双通开关包括一个输入端和两个输出端，所述输入端连接所述缓存模块，用于接收一列像素数据，其中一个输出端连接至所述多个数模转换模块中的至少一个，另一个输出端连接至所述多个运算模块中的至少一个；
    模式切换模块，配置为基于所述模式控制模块发送的控制信号控制所述双通开关将所述一列像素数据输出至所述两个输出端中的一个。
  21. 根据权利要求17所述的显示装置，其中，
    所述时序控制器还包括图像识别模块，所述图像识别模块配置为：
    识别连续多帧待显示图像的显示数据是否符合交替显示规律，其中，符合所述交替显示规律的显示数据的Q列像素数据在g个像素值之间循环，所述g个像素值分别对应g种亮度特征；
    若是，将所述多帧待显示图像分为多个图组，每个图组包括相邻的g帧待显示图像，并针对每个图组执行：若当前帧待显示图像为所述图组中的第k帧待显示图像，将所述第k帧待显示图像的Q列像素数据均变换为所述g个像素值中的第k个像素值；将变换后的Q列像素数据输出至所述源驱动芯片；
    其中，所述源驱动芯片还配置为：
    对于所述变换后的Q列像素数据，执行所述数据补充操作；
    基于所述数据补充操作后的第k+n*g列像素数据生成模拟数据信号并分别输入第k+n*g列像素单元，以使所述第k+n*g列像素单元显示为所述g种亮度特征中的第k种亮度特征，
    其中，在k为大于1的正整数的情况下，除所述第k+n*g列像素单元之外的其余列像素单元显示为所述第k帧待显示图像的上一帧待显示图像对应的亮度特征；在k等于1的情况下，除所述第k+n*g列像素单元之外的其余列像素单元不显示，
    其中，n取0至[Q/g-1]的全部整数，g为大于1且小于Q的整数，k为小于等于g的整数。
  22. 一种电子设备，包括：如权利要求16-21任一项所述的显示装置。
  23. 一种电子设备，包括：
    处理器；
    存储器，包括一个或多个计算机程序模块；
    其中，所述一个或多个计算机程序模块被存储在所述存储器中并被配置为由所述处理器执行，所述一个或多个计算机程序模块包括用于实现权利要求1-15任一项所述的信号处理方法的指令。
  24. 一种计算机可读存储介质，存储有非暂时性计算机可读指令，当所述非暂时性计算机可读指令由计算机执行时实现权利要求1-15任一项所述的信号处理方法。
PCT/CN2022/089394 2022-04-26 2022-04-26 信号处理方法、显示装置、电子设备和可读存储介质 WO2023206101A1 (zh)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10253939A (ja) * 1997-03-14 1998-09-25 Nec Corp 液晶表示装置
CN105487313A (zh) * 2016-01-04 2016-04-13 京东方科技集团股份有限公司 阵列基板、显示面板、显示装置及其驱动方法
CN105575309A (zh) * 2014-11-03 2016-05-11 三星显示有限公司 可伸展显示装置及可伸展显示装置的显示控制方法和装置
US20200051211A1 (en) * 2017-04-21 2020-02-13 Semiconductor Energy Laboratory Co., Ltd. Image processing method and image receiving apparatus
CN112634836A (zh) * 2019-10-08 2021-04-09 拉碧斯半导体株式会社 显示驱动器和显示装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10253939A (ja) * 1997-03-14 1998-09-25 Nec Corp 液晶表示装置
CN105575309A (zh) * 2014-11-03 2016-05-11 三星显示有限公司 可伸展显示装置及可伸展显示装置的显示控制方法和装置
CN105487313A (zh) * 2016-01-04 2016-04-13 京东方科技集团股份有限公司 阵列基板、显示面板、显示装置及其驱动方法
US20200051211A1 (en) * 2017-04-21 2020-02-13 Semiconductor Energy Laboratory Co., Ltd. Image processing method and image receiving apparatus
CN112634836A (zh) * 2019-10-08 2021-04-09 拉碧斯半导体株式会社 显示驱动器和显示装置

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