WO2023202889A1

WO2023202889A1 - Bioelectrical impedance analysis circuit, test system, analysis system and method of determining a bioelectrical impedance

Info

Publication number: WO2023202889A1
Application number: PCT/EP2023/059099
Authority: WO
Inventors: Hoa Vu
Original assignee: ams Sensors Germany GmbH
Priority date: 2022-04-19
Filing date: 2023-04-06
Publication date: 2023-10-26

Abstract

A bioelectrical impedance analysis circuit (BC), comprises input terminals (IN1, IN2, IN3, IN4) and an internal resistor (RINT). A switching network (SWN) is electrically coupled to the input terminals (IN1, IN2, IN3, IN4), a measurement unit (MU) and to the internal resistor (RINT) and addressable according to a switching sequence. The measurement unit (MU) is operable to, in a first switching state of the switching sequence, generate a first output signal as a measure of an external resistance of an external resistor (REXT) to be connected to the input terminals (IN1, IN4), and further operable to, in a second switching state switching sequence, generate a second output signal as a measure of an internal resistance of the internal resistor (RINT).

Description

BIOELECTRICAL IMPEDANCE ANALYS IS CIRCUIT , TEST SYSTEM, ANALYS IS SYSTEM AND METHOD OF DETERMINING A BIOELECTRICAL IMPEDANCE

This disclosure relates to a bioelectrical impedance analysis system, a TEST SYSTEM, analysis system and to a method of determining a bioimpedance , for example by means of a BIA system .

BACKGROUND OF THE DISCLOSURE

Bioimpedance relates to electrical properties of biomaterials such as a human body . Bioelectrical impedance analysis , or BIA for short , can be used to determine biological parameters of a tissue or a human body . Such parameters include a body fat percentage or another biological parameter related to an impedance of the body . Bioimpedance is measured by applying an electric current to biomaterial , e . g . via two excitation electrodes and picking up the resulting voltage with another pair of sensing electrodes . The lower the measured voltage the lower the tissue impedance for a given current . Tissue can be thought of cells and membranes . The membranes are thin but , in an electrical sense , have high resistivity and, thus , behave as small capacitors . By using rather high measuring frequencies current passes through these capacitors . The result depends on tissue and liquids both inside and outside the cells , for example . At low frequencies , however, the membranes impede current flow, and the results are dependent only on liquids outside the cells . It is therefore an obj ect to provide an improved concept for performing BIA with an improved measurement accuracy .

This obj ect is achieved by the subj ect-matter of the independent claims . Further implementations and embodiments are the subj ect-matter of the dependent claims .

SUMMARY OF THE DISCLOSURE

The following relates to an improved concept in the field of bioimpedance measurements . One aspect suggests to use an internal reference resistor . An impedance scale may be generated from a relative internal resistor measurement , i . e . relative to an external resistor standard . The bioimpedance can be extracted from the impedance scale which generated from the internal resistor measurement and system calibration . An internal resistor, such as polysilicon resistor, can vary up to 25% . During production final test , this error can be corrected by measuring it against a precise external resistor . The term "bioelectrical impedance" will be denoted bioimpedance for short . The term "bioelectrical impedance analysis" may be abbreviated as BIA, e . g . BIA circuit or BIA system .

In at least one embodiment , a bioelectrical impedance analysis circuit comprises input terminals and an internal resistor . A switching network is electrically coupled to the input terminals , a measurement unit and to the internal resistor . Furthermore , the switching network is addressable according to a switching sequence .

In a first switching state of the switching sequence , the device conducts a first measurement and measures the resistance of an external resistor to be connected to the input terminals. In this respect, the measurement unit generates a first output signal. In a second switching state of the switching sequence, the device conducts a second measurement and measures the resistance of the internal resistor. In this respect, the measurement unit generates a second output signal. The output signals correspond to the resistance of an external resistor and the resistance of the internal resistor.

Based on the two measurements, the internal reference resistor error can be calculated and stored in a memory, e.g. an one time programmable fuses. During normal mode of operation, the internal reference resistor error is read from the fuses to extract its exact value. Thus, in contrast to prior art solutions there is no need of precise external resistors which need to be connected to bioelectrical impedance analysis circuit via dedicated pins. The proposed concept allows for improved measurement accuracy and reduce the pin counts and cost.

In at least one embodiment, the measurement unit comprises an amplifier and an analog-to-digital converter. The amplifier is operable to sense a signal, e.g. a voltage or current, over the internal resistor and at the input terminals, e.g. depending on the switching state of the switching network. The analog-to-digital converter is operable to convert the sensed signal into digital output signals. For example, the converter is a delta-sigma analog-to-digital converter. The output signals may be provided in digital form for easier further processing, e.g. a calibration procedure, such as an impedance scale. In at least one embodiment , the bioelectrical impedance analysis circuit further comprises a test current source to provide a test current and a test voltage source to provide a common mode voltage . The test current source provides an excitation current which runs through the resistors ( external or internal , depending on the switching state of the switching network) . The test voltage source provides a common mode voltage , for example .

In at least one embodiment , in the first switching state , the switching network is switched such that the test current is applied to a first input terminal . The test current can be received at a fourth input terminal , e . g . in case the external resistor is connected . The switching network is switched such that a second and third input terminal are electrically connected to a first and second input terminal of the ampli fier .

In the second switching state , the switching network is switched such that the internal resistor is electrically connected in parallel to the first and second input terminal of the ampli fier and switched such that the test current source and the test voltage source are electrically connected via the internal resistor .

The switching network establishes di f ferent electrical conductive connections , or paths , to sense either the first or second output signals , i . e . measure the resistance of the external or internal resistor . This way, the output signals can be recorded as measures of the resistances and be used to calibrate the internal resistor . In at least one embodiment , the bioelectrical impedance analysis circuit is integrated as an integrated circuit . For example , the circuit is integrated using CMOS technology .

In at least one embodiment , a test system comprises a bioelectrical impedance analysis circuit according to one of the aforementioned aspects . Furthermore , a test circuit comprising the external resistor is connected to the input terminals .

In at least one embodiment , the test system further comprises a memory and a processing unit . The processing unit is operable to receive the first and second output signals and to derive a calibration value indicative of the resistance of the internal resistor . The processing unit is further operable to save the calibration value in the memory for access during a normal mode of operation .

The saved calibration value ( e . g . , a percentage error or calibrated resistance value ) can be used to calibrate output signals , which can be generated during a normal mode of operation, e . g . when the bioelectrical impedance analysis circuit is used to conduct bioimpedance measurements using a set of electrodes connected to the input terminals rather than the test circuit . The calibration value provides a reference to the bioimpedance measurements and allows to achieve high accuracy .

In at least one embodiment , the memory and/or the processing unit are integrated into the bioelectrical impedance analysis circuit . In at least one embodiment , the processing unit is operable to issue the switching sequence to operate the switching network according to the first and second switching states .

In at least one embodiment , the processing unit is operable to issue the switching sequence to operate the switching network according to a third switching state , which shorts the input terminals of the ampli fier . The measurement unit is operable to , in the third switching state , generate a third output signal indicative of an of fset of the ampli fier .

In at least one embodiment , the test system further comprises a temperature sensor which is operable to provide a temperature signal indicative of a temperature of the bioelectrical impedance analysis circuit . The calibration value may be recorded at a temperature which is di f ferent to a normal mode of operation condition . The temperature signal allows to account also for temperature and, thus , improve accuracy further .

In at least one embodiment , the processing unit is operable to calculate an impedance scale as a function of the first and second output signals . In addition, or alternatively, the processing unit is operable to calculate an impedance scale as a function the calibration value , of fset and temperature signal .

The impedance scale can be used to derive bioimpedance values , which are calibrated against the internal resistor as reference . As the resistance of the internal resistor is determined to a high degree of accuracy, the bioimpedance values share high accuracy as well . In at least one embodiment , a bioelectrical impedance analysis system comprises a bioelectrical impedance analysis circuit according to according to one of the aforementioned aspects . Furthermore , the BIA system comprises an electronic host device , and electrodes which are connected to the input terminals , respectively . The BIA circuit is built into and connected to the electronic host device . Examples of electronic host devices include mobile devices , smartphones , smartwatches , portable computers , wrist bands , chest bands , and the like .

Furthermore , a method is suggested of determining a bioelectrical impedance using a bioelectrical impedance analysis circuit comprising an internal resistor . The bioelectrical impedance analysis circuit may be a BIA circuit according to according to one of the aforementioned aspects .

The method involves generating of a first output signal as a measure of an external resistance of an external resistor . Then, a second output signal is generated as a measure of an internal resistance of the internal resistor . A calibration value is derived as a function of the first and second output signals and indicative of the resistance of the internal resistor .

In at least one embodiment , the calibration value is derived as a percentage error value .

Further embodiments of the method become apparent to the skilled reader from the aforementioned embodiments of the BIA circuit , test system and/or BIA system, and vice-versa .

BRIEF DESCRIPTION OF THE DRAWINGS The following description of figures may further illustrate and explain aspects of the sel f-mixing interferometry sensor module , wearable electronic device and the method of detecting movements . Components and parts of the sel f-mixing interferometry sensor that are functionally identical or have an identical ef fect are denoted by identical reference symbols . Identical or ef fectively identical components and parts might be described only with respect to the figures where they occur first . Their description is not necessarily repeated in successive figures .

In the figures :

Figure 1 shows an example embodiment of a BIA TEST SYSTEM,

Figure 2 shows an example embodiment of a BIA TEST SYSTEM in a first test state ,

Figure 3 shows an example embodiment of a BIA TEST SYSTEM in a second test state ,

Figure 4 shows an example of fset calibration,

Figure 5 shows an example of fset and reference calibration,

Figure 6 shows an example embodiment of a BIA system, and

Figure 7 shows an example calculation of a bioimpedance .

DETAILED DESCRIPTION Figure 1 shows an example embodiment of a BIA system. The system comprises a test circuit TC and BIA circuit BC . For example, the BIA circuit is an integrated circuit.

The test circuit TC comprises an external resistor REXT. The external resistor constitutes a precise measurement probe, i.e. its resistance is known to a high degree. For example, the resistance is known to a degree of ±0.01 %. Consider as an illustrative example that the resistance of the external resistor REXT is 2 kQ ±0.01 %. In addition, a temperature dependence may be known as well, so that the resistance value is known to a similar high degree also for different temperatures .

The test circuit TC further comprises four switches SI, S2, S3, and S4 which allow the test circuit to be connected to respective input terminal INI, IN2, INS, and IN4 of the BIA circuit BC . A first switch SI is coupled to a first input terminal INI. A second switch S2 is coupled to a second input terminal IN2. A third switch S3 is coupled to a third input terminal INS. A fourth switch S4 is coupled to a fourth input terminal IN4. Switching states of said four switches can be controlled by means of a switching sequence, e.g. to be provided by the BIA circuit. A switching sequence may determine a test mode of operation. Depending on the switching states an electrical connection is established between the external resistor REXT and the terminals.

The test circuit TC further comprises resistors RSC1, RSC2, RSC3, and RSC4 which represent the contact resistances at the respective input terminal INI, IN2, IN3, and IN4 of the BIA circuit BC . These resistors may be implemented as relay, socket, pin, needle, bump, etc. The BIA circuit BC comprises a test current source TCS, which provides a test current ITEST. Furthermore, the BIA circuit comprises a test voltage source TVS, which provides a test voltage, e.g. a common mode voltage VCM. Furthermore, the BIA circuit BC comprises the four input terminals INI, IN2, IN3, and IN4.

Furthermore, the BIA circuit BC comprises an internal resistor RINT . The internal resistor has a resistance value which may not be known, or not known with a higher percentage error (e.g., can be up to 25%) . The internal resistor RINT is an internal component in the sense that it provides a reference for bioimpedance measurement during operation of the BIA circuit. For example, the internal resistor RINT is integrated in the integrated circuit.

The BIA circuit BC comprises a measurement unit MU. The measurement unit further comprises an amplifier AMP having a positive input IN+ and negative input IN- terminals. Via its output side the amplifier is further connected to an analog- to-digital converter ADC. For example, the analog-to-digital converter is implemented as a voltage input delta-sigma analog-to-digital converter. The analog-to-digital converter comprises an output terminal OUT to provide a digital output signal of the BIA circuit.

A switching network SWN is coupled between the four terminals INI, IN2, IN3, and IN4, the test current source TCS, the test voltage source TVS, the internal resistor RINT and the measurement unit MU (e.g. via the positive input IN+ and negative input IN- terminals of the amplifier AMP) . The switching network comprises further switches S5 to S12, whose respective switching states can be controlled by said switching sequence (see above) . Details of the switching sequence will be discussed further below. Basically, the switching network provides switchable connections depending on the switching sequence. The switching sequence provides electrical connections such that in one switching state the external resistor REXT is provided with the test current ITEST and a voltage dropping over the external resistor REXT is provided to the BIA circuit BC, e.g., via the second and third input terminals IN2, IN3 to the measurement unit MU (e.g., to the positive input IN+ and negative input IN- terminals) . In another switching state the external resistor REXT is disconnected from the BIA circuit. Instead, the internal resistor RINT is provided with the test current ITEST and a voltage dropping over the internal resistor RINT is provided to the measurement unit MU (e.g., to the positive input IN+ and negative input IN- terminals) .

In more detail, the switching network SWN provides the following electrical connections, which can be either switched on (i.e., electrical conductive) or switched off (i.e., electrical non-conductive ) depending on the switching sequence. A first connection runs from the test current source TCS via switch S7 to the first input terminal INI. A second connection runs from the test current source TCS via switch S12 to the internal resistor RINT . A third connection runs from the positive input terminal IN+ via switch S6 to the second input terminal IN2. A fourth connection runs from the positive input terminal IN+ via switch Sil to the internal resistor RINT. A fifth connection runs from the negative input terminal IN- via switch S10 to the internal resistor RINT. A sixth connection runs from the negative input terminal IN- via switch S6 to the third input terminal IN3. A seventh connection runs from the test voltage source TVS via switch S9 to the internal resistor RINT . Finally, eighth connection runs from the test voltage source TVS via switch S8 to the fourth input terminal IN4.

In the circuit layout of Figure 1 further characteristic resistances RESD1, RESD2, RESD3, and RESD4 are depicted. These relate to electrostatic discharge protection of current received via respective input terminal INI, IN2, IN3, and IN4 of the BIA circuit BC .

It may be noted that SI, S2, S3, S4, REXT are external components. S5 to S12, RINT, TCS, TVS, AMP and ADC are internal components, which may all be integrated into the integrated circuit.

Figure 2 shows an example embodiment of a BIA TEST SYSTEM in a first test state. The drawing shows the TEST SYSTEM of Figure 1 in a defined first switching state which is set to measure the external resistor. In a first step, the BIA circuit BC is set into a test mode of operation. In this mode of operation, the test circuit is electrically connected to the input terminals INI, IN2, INS, and IN4 of the BIA circuit BC . This way the BIA TEST SYSTEM is essentially configured as a f our-terminal sensing setup, or Kelvin sensing configuration .

As a next step, the switches are switched according to switching sequence. As a result, the switches are in the first switching state. The first switching state allows to measure the precise external resistor REXT and record its value . The first switching state is defined as follows: switches SI, S2, S3, S4, S5, S6, S7, and S8 are closed, while switches S9, S10, Sil, and S12 are opened (see definition of switches above and the circuit layout of Figure 1, for example) . As a consequence, the test current ITEST flows from the test current source TCS through switch S7, resistor RESD1, input terminal INI, resistor RSC1, switch SI, external resistor REXT, switch S3, resistor RSC3, fourth input terminal IN4, resistor RESD4, and switch S8 to the test voltage source TVS.

A characteristic voltage VREXT drops over the external resistor REXT as the test current ITEST runs through the resistor. This voltage is applied to the measurement unit MU and sensed between the positive and negative input terminals IN+ and IN-. In more detail, switches S2 and S6 provide the electrical connection from the external resistor REXT to the positive input terminal IN+ via resistor RSC2, second input terminal IN2, and resistor RESD2. Switches S4 and S5 provide the electrical connection from the external resistor REXT to the negative input terminal IN- via resistor RSC4, third input terminal IN3, and resistor RESD3.

The characteristic voltage VREXT is then measured by the amplifier AMP and an intermediate signal is provided to the analog-to-digital converter ADC. The intermediate signal is converted into a digital output signal and provided at the output terminal OUT. Note that the path via switches S2, S4, S5, S6 path are high impedance paths, so voltage drops on resistors RSC2, RSC4, RESD2, RESD3, and switches S2, S4, S5, and S6 are negligible. The next step, the digital output signal is saved as a reference to conduct a calibration of the internal resistor RINT to be used during normal mode of operation. The reference may only be saved temporarily as it is used to calibrate the internal resistor as the reference for bioimpedance measurements using the BIA circuit BC .

Figure 3 shows an example embodiment of a BIA TEST SYSTEM in a first test state. The drawing shows the TEST SYSTEM of Figure 1 in a defined second switching state. As a next step, the switches are switched according to switching sequence again. As a result, the switches are in the second switching state. The first switching state allows to measure the internal resistor RINT and record its value, e.g. in terms of an error percentage in a memory, such as an OTP.

The second switching state is defined as follows: switches SI, S2, S3, S4, S5, S6, S7, and S8 are opened, while switches S9, S10, Sil, and S12 are closed (see definition of switches above and the circuit layout of Figure 1, for example) . As a consequence, the test current ITEST flows from the test current source TCS through switch S12, internal resistor RINT, and switch S9 to the test voltage source TVS.

A characteristic voltage VRINT drops over the internal resistor RINT as the test current ITEST runs through the resistor. This voltage is applied to the measurement unit MU and sensed between the positive and negative input terminals IN+ and IN-. In more detail, switches Sil and S10 provide the electrical connection from the internal resistor RINT to the positive input terminal IN+ and the negative input terminal IN- .

The characteristic voltage VRINT is then measured by the amplifier AMP and an intermediate signal is provided to the analog-to-digital converter ADC. The intermediate signal is converted into a digital output signal and provided at the output terminal OUT .

The digital output signal associated with the external resistor REXT and the internal resistor RINT can be used to calculate the internal resistor percentage error . This procedure can be performed on-chip, e . g . by means of a processing unit PU (not shown) , which may also be integrated into the same integrated circuit as other components of the BIA circuit BC . However, the procedure can also be performed of f-chip, e . g . by means of a processing unit PU (not shown) external to the BIA circuit . Such a unit may be part of an electronic host device , for example . Example embodiments of processing units comprise a micro-controller, AS IC, central processing unit , and the like .

The internal resistor percentage error is calculated as a function of the digital output signal associated with the external resistor REXT and the digital output signal associated with the internal resistor RINT , and results in a percentage error signal . For example , the percentage error signal is 10 bits . 1 bit can assigned to a sign, 5 bits can be assigned for an integer number, e . g . with 1 % per code so the range can be ±31 % , and another 4 bits for a decimal number with 0 . 06 % per code . Theoretically, this way the resistor value of the internal resistor RINR can be measured to 0 . 03 % .

The percentage error signal and/or derived highly accurate value of the internal resistor RINT can be saved into a memory, e . g . integrated into the BIA circuit BC or an electronic host device . The memory can be read during normal mode of operation of the BIA circuit BC and the stored values be used to determine a highly accurate bioimpedance .

Figure 4 shows an example of fset calibration . The test mode of operation can be complemented with an of fset calibration . During the of fset calibration, the switches are switched according to the switching sequence . As a result , the switches are in a third switching state , which shorts the input terminals IN+ and IN- of the ampli fier AMP . The drawing on the left of Figure 4 illustrates the third switching states and shows the conducting electrical connections , while omitted the rest for easier representation .

The third switching state allows to measure a zero impedance without any excitation current . The resulting digital output signal generated in the third switching state determines an of fset magnitude Mo ( or ADC code magnitude ) . The of fset magnitude Mo is determined by phases I and Q and yields :

M₀ = 7I² + Q² .

Examples of of fset magnitude Mo are illustrated in the drawing as data points MO I , M02 , and M03 . In the graph on the left of Figure 4 the data points show on the ADC code magnitude axis at zero impedance of the impedance axis .

Figure 5 shows an example of fset and reference calibration . The switching network SWN can be implemented by means of multiplexers . The drawings shows a multiplexer which is connected to a current digital-to-analog converter IDAC which serves as a current source to provide excitations currents IBIOZp and IBIOZn to the internal resistor RINT . The digital- to-analog converter IDAC comprises current select terminal CST and a frequency select FSL terminal .

The digital-to-analog converter IDAC outputs the excitation currents , e . g . di f ferential sinewave currents for the excitation, which are switched to the internal resistor RINT for the measurement . Via the current select terminal CST and frequency select FSL terminal current amplitude and frequency are selected, respectively . These settings are the same as the bioimpedance measurement . The conditions are relative for the internal resistor RINT and bioimpedance measurements . Therefore , the measuring system is calibrated for the of fset and gain errors . The results from the of fset and the RINT measurements are used to generate an impedance scale for the bioimpedance measurement , as depicted on the right side of the drawing .

The resistance value of the internal resistor RINT is extracted by reading its error percentage from the memory . Optionally, the BIA circuit BC comprises a temperature sensor, which provides a temperature signal T indicative of a temperature of the circuit . A reference temperature TREF can be saved to the memory alongside the percentage error signal and/or resistance value of the internal resistor RINT . The reference temperature TREF indicates the temperature signal when the internal resistor RINT has been tested and stored in the memory .

In a next step, a reference phase cf>R and magnitude MR for the impedance scale are determined . The magnitude yields

MR = 7l² + Q² and the phase

4>_R = tan’¹ ( ) .

A temperature compensated resistance RT, in terms of the resistance of the internal resistor as reference denoted as RREF can be calculated from:

R_T = R_REF [1 - 0.000332

Furthermore, a magnitude slope m can be calculated and yields :

wherein c = Mo denoted the offset (see above) . The resulting impedance scale calibrated for the offset and gain error is depicted on the right side of Figure 5.

Figure 6 shows an example embodiment of a BIA system. The system comprises the BIA circuit BC and four electrodes ELI, EL2, EL3, and EL4 which are connected to the input terminals INI, IN2, IN3, and IN4, respectively. The electrodes each are characterized by a resistor Ri and capacitor Ci as depicted in the drawing (i.e., INI: Rl and Cl, IN2 : R2 and C2, IN3 : R3 and C3, IN4 : R4 and C4) . A body impedance is illustrated by body resistor RBODY representing a body resistance and body capacitor CBODY representing a body capacitance. A reference circuit is connected to a reference terminal REF to receive a reference voltage VREF. The BIA circuit BC in this embodiment is complemented and/or adapted to conduct a bioimpedance measurement relative to the resistance of the internal resistor as reference , denoted as RREF . Therefore , high accuracy can be achieved .

The switching network SWN is implemented by means of multiplexers , referenced as a first multiplexer SWN1 ( see VBIOZ SELECTION) and a second multiplexer SWN2 ( see IBIOZ SELECTION) in the drawing . Four control lines of the first and second multiplexer SWN1 , SWM2 are shared and connected to the input terminals INI , IN2 , INS , and IN4 , respectively . The first multiplexer SWM1 is connected to the measurement unit MU . The second multiplexer SMW2 is connected to a current digital-to-analog converter IDAC which serves as a current source to provide excitations currents IBIOZp and IBIOZn to the bioimpedance to be measured . The first and second multiplexer SWN1 , SWM2 can be configured to send the excitation currents to any two electrodes and measure the voltages on the other two electrodes during in normal mode of operation .

The measurement unit MU comprises the ampli fier AMP and the analog-to-digital converter ADC and is complemented with additional component for signal conditioning and preprocessing . In this respect the measurement unit MU comprises a series connection of a high pass filter HP, the ampli fier AMP, mixers MX1 , MX2 , low pass filters LP1 , LP2 and a multiplexer MUX connected to the analog-to-digital converter ADC .

In operation, or normal mode of operation, e . g, the multiplexer SWN2 provides excitation currents to the electrodes ELI , EL4 via the first and fourth terminals INI and IN4 which excite the body with the same current amplitude and frequency selections as to the internal resistance measurement of RINT in Figure 5 . At the same time , the first multiplexer SWN1 selects the voltages using the second and third electrodes EL2 , EL3 via the second and third input terminals IN2 , IN3 , to the measurement unit MU . For example , two sense voltages INAp and INAn can be measured according to two excitations currents IBIOZp and IBIOZn flowing across the body impedance represented by RBODY and CBODY .

The sense voltages INAp and INAn are processed by means of the measurement unit . The sense voltages are filtered by means of the high pass filter HP and detected by means of the ampli fier AMP ( e . g . , an instrumental ampli fier ) . A detected intermediate signal is demodulated by the mixers MX1 , MX2 , and low pass filtered LP to generate phase signals I and Q . The phase signals are multiplexed by means of multiplexer MUX and, finally, a digital output signal is generated by means of the analog-to-digital converter ADC, and provided at its output terminal OUT .

The digital output signal can be of fset calibrated and an impedance can be determined against the internal resistor as reference . For example , the procedure discussed with respect to previous Figures 4 and 5 can be employed, e . g . in dedicated processing unit PU . Said processing unit PU can be implemented in the BIA circuit BC or be an external component which is located in an electronic host device , for example . The switching sequence , according to a test or normal mode of operation may be provided and/or applied to the BIA circuit BC by means of the processing unit . In this context, the processing unit PU receives the digital output signal from the analog-to-digital converter ADC (e.g., ADC code of magnitude MB) . Using the impedance scale, the digital output signal is calibrated for the offset and gain error. In more detail, the magnitude of the digital output signal, which is a measure of the body impedance, is determined as

M_B = Vi² + Q² and phase

4>_B = tan ¹ ( ) .

The bioimpedance can be calculated from a function of magnitude slope m and offset magnitude Mo. For example, the bioimpedance yields:

and phase

Figure 7 shows an example calculation of a bioimpedance. The measured impedance typically is effected by different contributions, as indicated in the drawing. The upper drawings illustrates that Z_meas has contributions the actual bioimpedance Z^y, electrode and external network impedance

ZELEC+EXTNET and an input impedance of the BIA circuit, denotedZ_in . The drawing in the middle shows that Z_ELEC+EXT NET and Z_in can be estimated by a substitute circuit diagram with

Zest ⁼ Z_ELEC + EXT NET II Z_in .

These impedances can be measured in order to characteri ze the BIA system, i . e . BIA circuit BC and electrodes ELI to EL4 , e . g . at all involved frequencies . Assuming Z_est = Z_body II Z_est ( see drawing at the bottom) , the final bioimpedance yields :

While this speci fication contains many speci fics , these should not be construed as limitations on the scope of the invention or of what may be claimed, but rather as descriptions of features speci fic to particular embodiments of the invention . Certain features that are described in this speci fication in the context of separate embodiments can also be implemented in combination in a single embodiment . Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination . Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a sub-combination or variation of a sub-combination .

Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results . In certain circumstances , multitasking and parallel processing may be advantageous .

A number of implementations have been described .

Nevertheless , various modi fications may be made without departing from the spirit and scope of the invention . Accordingly, other implementations are within the scope of the claims .

This patent application claims the priority of US patent application 63/ 332 , 670 , the disclosure content of which is hereby incorporated by reference .

References

ADC analog-to-digital converter

AMP ampli fier

BC BIA circuit

CBODY body capacitor

CSL current select terminal

FSL frequency select terminal

HP high pass filter

INI input terminal

IN2 input terminal

IN3 input terminal

IN4 input terminal

ITEST test current

LP1 low pass filter

LP2 low pass filter

MU measurement unit

MUX multiplexer

MX1 mixer

MX2 mixer

OUT output terminal

RBODY body resistor

REXT external resistor

REF reference terminal

RINT internal resistor

51 switch

52 switch

53 switch

54 switch

55 switch

56 switch

57 switch

58 switch S 9 switch

510 switch

511 switch

S 12 switch SWN switching network

SWN1 f irst multiplexer

SWM2 second multiplexer

TC test circuit

TCS test current source TVS test voltage source

VCM common mode voltage

Claims

1. A bioelectrical impedance analysis circuit (BC) , comprising :

- input terminals (INI, IN2, IN3, IN4) and an internal resistor (RINT) ,

- a switching network (SWN) electrically coupled to the input terminals (INI, IN2, IN3, IN4) , a measurement unit (MU) and to the internal resistor (RINT) and addressable according to a switching sequence; wherein the measurement unit (MU) is operable to:

- in a first switching state of the switching sequence, generate a first output signal as a measure of an external resistance of an external resistor (REXT) to be connected to the input terminals (INI, IN4) , and

- in a second switching state of the switching sequence, generate a second output signal as a measure of an internal resistance of the internal resistor (RINT) .

2. The circuit according to claim 1, wherein the measurement unit (MU) comprises:

- an amplifier (AMP) to sense a voltage over the internal resistor (RINT) and at the input terminals (IN2, IN3) , and

- an analog-to-digital converter (ADC) to convert the sensed voltages into digital output signals.

3. The circuit according to claim 1 or 2, further comprising a test current source (TCS) to provide a test current (ITEST) and a test voltage source (TVS) to provide a common mode voltage (VCM) .

4. The circuit according to claim 3, wherein: - in the first switching state, the switching network (SWN) is switched such that the test current (ITEST) is applied to a first input terminal (INI) and to be received at a fourth input terminal (IN4) , and switched such that a second and third input terminal (IN2, IN3) are electrically connected to a first and second input terminal (IN+, IN-) of the amplifier (AMP) , and

- in the second switching state, the switching network (SWN) is switched such that the internal resistor (RINT) is electrically connected in parallel to the first and second input terminal (IN+, IN-) of the amplifier (AMP) and switched such that the test current source (TCS) and the test voltage source (TVS) are electrically connected via the internal resistor (RINT) .

5. The circuit according to one of claims 1 to 4, wherein the bioelectrical impedance analysis circuit (BC) is integrated as an integrated circuit.

6. A test system, comprising:

- a bioelectrical impedance analysis circuit (BC) according to one of claims 1 to 5, and

- a test circuit (TC) comprising the external resistor (REXT) and connected to the input terminals (INI, IN2, IN3, IN4) .

7. The system according to claim 6, further comprising a memory and a processing unit (PU) , wherein:

- the processing unit (PU) is operable to receive the first and second output signals and to derive a calibration value indicative of the resistance of the internal resistor (RINT) , and the processing unit (PU) is further operable to save the calibration value in the memory for access during a normal mode of operation.

8. The test system according to claim 7, wherein the memory and/or the processing unit (PU) are integrated into the bioelectrical impedance analysis circuit (BC) .

9. The system according to one of claims 6 to 8, wherein the processing unit (PU) is operable to issue the switching sequence to operate the switching network (SWN) according to the first and second switching states.

10. The system according to one of claims 6 to 9, wherein

- the processing unit (PU) is operable to issue the switching sequence to operate the switching network (SWN) according to a third switching state, which shorts the input terminals (IN+, IN-) of the amplifier (AMP) , and

- the measurement unit (MU) is operable to, in the third switching state, generate a third output signal indicative of an offset of the amplifier (AMP) .

11. The system according to one of claims 6 to 10, further comprising a temperature sensor which is operable to provide a temperature signal indicative of a temperature of the bioelectrical impedance analysis circuit (BC) .

12. The system according to one of claims 6 to 11, wherein

- the processing unit (PU) is operable to calculate an impedance scale as a function of the first and second output signals, or - the processing unit (PU) is operable to calculate an impedance scale as a function the calibration value, offset and temperature signal.

13. A bioelectrical impedance analysis system comprising:

- a bioelectrical impedance analysis circuit (BC) according to one of claims 1 to 5,

- an electronic host device, and

- electrodes (ELI, EL2, EL3, and EL4) connected to the input terminals (INI, IN2, IN3, and IN4) .

14. A method of determining a bioelectrical impedance, using a bioelectrical impedance analysis circuit comprising an internal resistor (RINT) , comprising the steps of:

- generate a first output signal as a measure of an external resistance of an external resistor (REXT) ,

- generate a second output signal as a measure of an internal resistance of the internal resistor (RINT) ,

- derive a calibration value indicative of the resistance of the internal resistor (RINT) as a function of the first and second output signals.

15. The method according to claim 14, wherein the calibration value is derived as a percentage error value.