WO2023202507A1 - 栅极驱动控制方法及其系统、显示驱动系统、显示装置 - Google Patents

栅极驱动控制方法及其系统、显示驱动系统、显示装置 Download PDF

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Publication number
WO2023202507A1
WO2023202507A1 PCT/CN2023/088589 CN2023088589W WO2023202507A1 WO 2023202507 A1 WO2023202507 A1 WO 2023202507A1 CN 2023088589 W CN2023088589 W CN 2023088589W WO 2023202507 A1 WO2023202507 A1 WO 2023202507A1
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WIPO (PCT)
Prior art keywords
display
clock signal
gate drive
partition
control signal
Prior art date
Application number
PCT/CN2023/088589
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English (en)
French (fr)
Inventor
袁靖超
赵敬鹏
段欣
朱文涛
周志恒
潘宏鑫
Original Assignee
京东方科技集团股份有限公司
重庆京东方光电科技有限公司
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Publication of WO2023202507A1 publication Critical patent/WO2023202507A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits

Definitions

  • the present invention relates to the field of display, and in particular to a gate drive control method and system, a display drive system, a display device, electronic equipment and a computer-readable medium.
  • the present invention aims to solve at least one of the technical problems existing in the prior art, and proposes a gate drive control method and its system, a display drive system, a display device, an electronic device and a computer-readable medium.
  • embodiments of the present disclosure provide a gate drive control method for controlling a drive operation of a gate drive circuit for driving a display panel, the display panel including Distributing at least two display partitions, the gate drive circuit includes: at least two gate drive modules that correspond to the display partitions one-to-one and are independent of each other, and the gate drive circuit is configured with multiple clock signal terminals and There are at least two start control signal terminals corresponding to the gate drive modules one-to-one, and each of the gate drive modules is connected to the plurality of clock signal terminals and the corresponding start control signal terminal; Gate drive control methods, including:
  • the display mode information includes: the display mode of each of the display partitions, the display mode includes a high-definition mode or a low-definition mode;
  • the multiple clock signals are sent according to the display mode of the display partition.
  • the number terminal outputs a clock signal corresponding to the display mode;
  • clock signals corresponding to the high-definition mode are output to the plurality of clock signal terminals to control the gate driving module corresponding to the display partition to Each row of sub-pixels in the above-mentioned display partition is driven by progressive scanning;
  • clock signals corresponding to the low-definition mode are output to the plurality of clock signal terminals to control the gate driving module corresponding to the display partition to Each row of sub-pixels in the above-mentioned display partition is scanned and driven by N rows at the same time, N is an integer and N ⁇ 2.
  • the display mode information further includes: the driving duration of each display partition;
  • the gate drive control method also includes:
  • a start control signal is output to the start control signal terminal corresponding to the display partition to control
  • the gate driving module corresponding to the display partition performs scan driving on each row of sub-pixels in the display partition within the driving time period.
  • the waveform parameters of the initial control signal include: the duration of the initial control signal and the duration of the initial control signal in an active level state.
  • the start control signal provided to the start control signal terminal corresponding to the display partition whose display mode is high-definition mode is a preset first start control signal
  • the start control signal provided to the start control signal terminal corresponding to the display partition whose display mode is low-definition mode is a preset second start control signal
  • the duration during which the first initial control signal is in the active level state is greater than or equal to the duration during which the second initial control signal is in the active level state.
  • the step of outputting a clock signal corresponding to the display mode to the plurality of clock signal terminals according to the display mode of the display partition includes:
  • the clock signal waveform parameters include: cycle length of the clock signal, time The number of cycles of the clock signal, the duration of the clock signal in a single cycle, and the duration of the clock signal in the active level state in a single cycle.
  • the clock signal corresponding to the high-definition mode output to the plurality of clock signal terminals is a preset first clock signal
  • the clock signal corresponding to the high-definition mode output to the plurality of clock signal terminals is a preset second clock signal
  • the duration during which the first clock signal is in an active level state within a single cycle is less than or equal to the duration during which the second clock signal is at an active level state within a single cycle.
  • embodiments of the present disclosure provide a gate drive control system for controlling a drive operation of a gate drive circuit for driving a display panel, the display panel including Distributing at least two display partitions, the gate drive circuit includes: at least two gate drive modules that correspond to the display partitions one-to-one and are independent of each other, and the gate drive circuit is configured with multiple clock signal terminals and There are at least two start control signal terminals corresponding to the gate drive modules one-to-one, and each of the gate drive modules is connected to the plurality of clock signal terminals and the corresponding start control signal terminal; Gate drive control system, including:
  • the first acquisition module is configured to acquire the display mode information of the picture to be displayed.
  • the display mode information includes: the display mode of each of the display partitions, and the display mode includes a high-definition mode or a low-definition mode;
  • a first processing module configured to, for any of the display partitions, output a clock signal corresponding to the display mode to the plurality of clock signal terminals according to the display mode of the display partition;
  • clock signals corresponding to the high-definition mode are output to the plurality of clock signal terminals to control the gate driving module corresponding to the display partition to Each row of sub-pixels in the above-mentioned display partition is driven by progressive scanning;
  • clock signals corresponding to the low-definition mode are output to the plurality of clock signal terminals to control the gate driving module corresponding to the display partition to Each row of sub-pixels in the above-mentioned display partition is scanned and driven by N rows at the same time, N is an integer and N ⁇ 2.
  • the display mode information further includes: the driving duration of each display partition;
  • the gate drive control system also includes:
  • the second processing module is configured to, for any of the display partitions, output to the start control signal terminal corresponding to the display partition according to the driving duration of the display partition and the preset start control signal waveform parameters.
  • a control signal is started to control the gate driving module corresponding to the display partition to scan and drive each row of sub-pixels in the display partition within the driving time period.
  • the waveform parameters of the initial control signal include: the duration of the initial control signal and the duration of the initial control signal in an active level state.
  • the start control signal provided to the start control signal terminal corresponding to the display partition whose display mode is high-definition mode is a preset first start control signal
  • the start control signal provided to the start control signal terminal corresponding to the display partition whose display mode is low-definition mode is a preset second start control signal
  • the duration during which the first initial control signal is in the active level state is greater than or equal to the duration during which the second initial control signal is in the active level state.
  • the first processing module includes:
  • a first determination unit configured to determine, according to the display mode of the display partition, the clock signal waveform parameters corresponding to the display mode
  • the first output unit is configured to output corresponding clock signals to the plurality of clock signal terminals according to the clock signal waveform parameters.
  • the clock signal waveform parameters include: the cycle length of the clock signal, the number of cycles of the clock signal, the duration of the clock signal in a single cycle, and the duration of the clock signal in an active level state in a single cycle. duration.
  • the clock signal corresponding to the high-definition mode output to the plurality of clock signal terminals is a preset first clock signal
  • the clock signal corresponding to the high-definition mode output to the plurality of clock signal terminals is a preset second clock signal
  • the duration during which the first clock signal is in an active level state within a single cycle is less than or equal to the duration during which the second clock signal is at an active level state within a single cycle.
  • embodiments of the present disclosure also provide a display driving system, including: as described in the second The gate drive control system provided in aspects.
  • it also includes:
  • the source driving circuit is configured to receive display data information of the picture to be displayed, and provide corresponding data voltages to each sub-pixel according to the display data of each sub-pixel recorded in the display data information;
  • the gate drive circuit includes at least two of the gate drive modules
  • the gate driving module is configured to control each row in the corresponding display partition in response to the control of a starting control signal provided by the starting control signal terminal and a clock signal provided by the plurality of clock signal terminals.
  • Sub-pixel scan drive is configured to control each row in the corresponding display partition in response to the control of a starting control signal provided by the starting control signal terminal and a clock signal provided by the plurality of clock signal terminals.
  • the interface through which the first acquisition module obtains the display mode information and the interface through which the source driver circuit obtains the display data information are the same interface;
  • the display mode information is obtained before the display data information.
  • an embodiment of the present disclosure further provides a display device, which is characterized in that it includes: a display panel and the display driving system provided in the second aspect.
  • embodiments of the present disclosure also provide an electronic device, which includes:
  • processors one or more processors
  • Memory used to store one or more programs
  • the one or more processors When the one or more programs are executed by the one or more processors, the one or more processors are caused to implement the gate drive control method as provided in the first aspect.
  • the processor includes a field programmable gate array.
  • embodiments of the present disclosure further provide a computer-readable medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the gate driving as provided in the first aspect Control the steps in the method.
  • Figure 1A is a systematic structural block diagram of a display device involved in the technical solution of the present disclosure
  • Figure 1B is a specific structural block diagram of the display device shown in Figure 1A;
  • Figure 2 is a schematic circuit structure diagram of a sub-pixel in an embodiment of the present disclosure
  • Figure 3 is a schematic circuit structure diagram of a sub-pixel in an embodiment of the present disclosure.
  • Figure 4 is a schematic diagram of a principle for determining a display mode of a display partition in an embodiment of the present disclosure
  • Figure 5 is a flow chart of a gate drive control method provided by an embodiment of the present disclosure.
  • Figure 6 is a schematic diagram of the clock signal received by the gate drive module corresponding to the display partition DS2 and the display partition DS3 in Figure 4 and the scan drive signal output;
  • Figure 7 is another schematic diagram of the clock signal received by the gate drive module corresponding to the display partition DS2 and the display partition DS3 in Figure 4 and the scan drive signal output;
  • Figure 8 is a flow chart of another gate drive control method provided by an embodiment of the present disclosure.
  • Figure 9 is a flow chart of an optional implementation of step S2 in the embodiment of the present disclosure.
  • Figure 10 is a schematic diagram of the clock signal received by the gate drive module corresponding to the display partition DS2 and the display partition DS3 in Figure 4 and the scan drive signal output;
  • Figure 11A is a structural block diagram of a gate drive control system provided by an embodiment of the present disclosure.
  • Figure 11B is a structural block diagram of the first processing module provided by an embodiment of the present disclosure.
  • Figure 12 is a structural block diagram of a display driving system provided by an embodiment of the present disclosure.
  • FIG. 13 is a schematic structural diagram of an electronic device according to an embodiment of the present disclosure.
  • Figure 1A is a systematic structural block diagram of a display device involved in the technical solution of the present disclosure.
  • the display device includes: a display panel 1, an image acquisition module 2, a processing system 3 and a display driving system 4.
  • the display panel 1 can be a 2D display panel or a 3D display panel; according to the light emitting type, the display panel 1 can be a liquid crystal display panel (LCD) or a light emitting diode. tube (LED) display panel, organic light-emitting diode (OLED) display panel or quantum dot light-emitting diode (QLED) display panel.
  • LCD liquid crystal display panel
  • LED light emitting diode
  • OLED organic light-emitting diode
  • QLED quantum dot light-emitting diode
  • the display panel 1 includes a plurality of sub-pixels arranged in an array along the row direction and the column direction, and each sub-pixel is connected to a corresponding row gate line and a corresponding column data line.
  • FIG. 2 is a schematic circuit structure diagram of a sub-pixel in an embodiment of the present disclosure.
  • the sub-pixel is a sub-pixel in the liquid crystal display panel 1 and includes a switching transistor T0 and a pixel electrode.
  • the control of the switching transistor T0 The first electrode of the switching transistor T0 is connected to the data line DATA, and the second electrode of the switching transistor T0 is connected to the pixel electrode.
  • the switching transistor T0 When the driving signal provided by the gate line GATE is at an active level, the switching transistor T0 is turned on, and the data voltage in the data line DATA is written to the pixel electrode.
  • Figure 3 is a schematic circuit structure diagram of a sub-pixel in an embodiment of the present disclosure.
  • the sub-pixel is a sub-pixel in the LED/OLED/QLED diode display panel 1 and includes: a data writing transistor T1,
  • the driving transistor DTFT and the light-emitting element EL specifically, it can be LED, OLED or QLED
  • the control electrode of the data writing transistor T1 is connected to the corresponding row gate line GATE, and the first electrode of the data writing transistor T1 is connected to the data line DATA.
  • the second electrode of the writing transistor T1 is connected to the control electrode of the driving transistor DTFT, the first electrode of the driving transistor DTFT is connected to the power supply terminal VDD, and the second electrode of the driving transistor DTFT is connected to the light-emitting element EL.
  • the driving signal provided by the gate line GATE is at a valid level, the data writing transistor T1 is turned on, the data voltage in the data line DATA is written to the control electrode of the driving transistor DTFT, and the driving transistor DTFT outputs a corresponding driving current.
  • circuit structure of the sub-pixels in the embodiments of the present disclosure is not limited to that shown in Figures 2 and 3.
  • Other circuit structures can also be used, and no examples will be given here.
  • the display panel 1 is divided into multiple display partitions along the column direction.
  • Each display partition can be independently driven, and the display mode of each display partition can be independently controlled. set up.
  • the display mode can be high-definition mode or low-definition mode.
  • the number of sub-pixel lines included in each display partition may be the same or different.
  • the display modes of each display partition can be the same or different.
  • the image acquisition module 2 is used to acquire the human eye image of the viewing user and transmit the human eye image to the processing unit.
  • System 3 The image acquisition module 2 can be integrated on the display panel 1 or set up separately; the image acquisition module 2 can specifically be a camera.
  • the processing system 3 can be used to determine the coordinates of the human eye's gaze point on the display panel 1 based on the human eye image acquired by the image acquisition module 2, and estimate the range of the human eye's gaze area based on the gaze point coordinates, and based on the human eye's gaze point coordinates.
  • the display mode of each display partition on the display panel 1 is determined based on the gaze range.
  • FIG 4 is a schematic diagram of a principle for determining the display mode of a display partition in an embodiment of the present disclosure.
  • the display panel 1 includes six display partitions DS1 to DS6 arranged sequentially from top to bottom.
  • the human eye's gaze point determined in the image is point A.
  • the human eye gaze area range Q is estimated; optionally, the human eye gaze area range Q can be a circle with point A as the center and a preset radius. A circular area (see shown in Figure 4); alternatively, the human eye gaze area range Q may be a rectangular area centered on point A and having a preset length and a preset width (no corresponding figure is given).
  • the technical solution of this disclosure does not limit the specific algorithm of the human eye gaze area evaluation algorithm.
  • the display mode of the display partitions that overlap with the human eye gaze area range Q (for example, the display partitions DS1 to DS2 in Figure 4) is set to high-definition mode, and the display mode that overlaps with the human eye gaze area range Q is set to high-definition mode.
  • the display mode of the display partitions that do not overlap in the area range Q (for example, the display partitions DS3 to DS6 in Figure 4) is set to the low-definition mode.
  • the processing system 3 can also receive the original display data information of the picture to be displayed from an external signal terminal, specifically including the display data (for example, grayscale data) of each sub-pixel of the panel 1 to be displayed.
  • the processing system 3 After the processing system 3 obtains the display mode of each display partition, it can perform resolution reduction processing on the display image of the display partition whose display mode is the low-definition mode; specifically, the sub-pixels of the display partition whose display mode is the low-definition mode
  • the gray-scale data is compressed so that the gray-scale data of every N sub-pixels located in the same column is the same gray-scale data (every N sub-pixels in the same column are combined into one sub-pixel), where N is an integer and N ⁇ 2, the specific value of N can be pre-designed or adjusted according to actual needs.
  • the technical solution of the present disclosure does not limit the specific algorithm used in the resolution reduction process. It only needs to reduce the resolution of the final image displayed in the display partition in the low-definition mode. The images displayed in the display partition whose display mode is high-definition mode are not processed.
  • the image displayed in the display partition with the display mode in low-definition mode has been reduced in resolution.
  • the display image obtained after processing is called a low-definition display image;
  • the image displayed in the display partition whose display mode is high-definition mode is called a high-definition display image;
  • the obtained low-definition display image and the unprocessed high-definition display image are fused to obtain the final display data information of the picture to be displayed.
  • the processing system 3 sends the display mode information of the picture to be displayed (including the display mode of each display partition) and the final display data information of the picture to be displayed (including the final display data of each sub-pixel) to the display driving system 4 .
  • the display driving system 4 includes at least a gate driving control system 5 , a gate driving circuit 6 and a source driving circuit 7 .
  • the gate driving circuit 6 includes: at least two gate driving modules that correspond to the display partitions one-to-one and are independent of each other (only two gate driving modules are schematically shown in FIG. 1B , namely, the gate driving module).
  • Driving module 6-1 and gate driving module 6-2) the gate driving circuit 6 is configured with multiple clock signal terminals (only four clock signal terminals CK1-CK4 are schematically shown in FIG. 1B) and gate There are at least two start control signal terminals corresponding to the drive module one-to-one (only two start control signal terminals STV1 and STV2 are schematically shown in Figure 1B).
  • Each gate drive module corresponds to multiple clock signal terminals and The start control signal terminal is connected (as shown in Figure 1B, the gate drive module 6-1 is connected to the four clock signal terminals CK1-CK4 and the corresponding start control signal terminal STV1, the gate drive module 6-2 is connected to The four clock signal terminals CK1-CK4 are connected to the corresponding start control signal terminal STV2), and the gate drive module is configured to respond to the start control signal provided by the start control signal terminal and the clock signals provided by the plurality of clock signal terminals. Control, scan and drive each row of sub-pixels in the corresponding display partition (only two partitions, namely DS1 and DS2, are schematically shown in FIG. 1B).
  • the starting working time of the gate driving module is determined by the starting control signal provided by the starting control signal terminal, and the scanning and driving mode of the gate driving module for the sub-pixels in the corresponding display partition is determined by multiple clock signal terminals. Determined by the clock signal provided.
  • the gate drive control system 5 is connected to the gate drive circuit 6.
  • the gate drive control system 5 can be used to adjust the initial control output to each gate drive module in the gate drive circuit 6 according to the display mode information of the picture to be displayed. signals and clock signals to control the working time and scan driving mode of each gate drive module.
  • the gate drive control system 5 may be based on a field programmable gate array (Field Programmable Gate Array). Programmable Gate Array (FPGA for short) and the functional modules implemented by the corresponding programs.
  • the specific form of the gate drive circuit 6 in the embodiment of the present disclosure can be a functional module with a gate drive function implemented based on FPGA and corresponding programs, or it can be a chip with a gate drive function (generally called a Gate IC), or it can It is a circuit structure (Gate on Array, GOA for short) formed directly in the peripheral area of the display panel 1 based on the array substrate process.
  • the technical solution of the present disclosure does not limit the specific form and structure of the gate driving circuit 6 .
  • one data channel may correspond to one data line or multiple data lines (as shown in Figure 1B, data channel CH1 corresponds to one data line, and data channel CH2 corresponds to two data lines).
  • a strobe circuit Cir also called a MUX circuit
  • the MUX circuit includes multiple MUX units corresponding to the data channels one-to-one (in Figure 1B Only one MUX unit is shown schematically).
  • the MUX unit is provided with multiple switch circuits corresponding to multiple data lines. Each switch circuit is controlled to be turned on sequentially through timing (at any time, at most one switch circuit in the MUX unit is The switch circuit is in a conductive state) to write the data voltage output by the data channel into the corresponding data line.
  • FIG. 5 is a flow chart of a gate drive control method provided by an embodiment of the present disclosure.
  • the gate drive control method is applied to a gate drive control system.
  • the gate drive control system is used to control the gate.
  • the gate drive circuit is used to drive the display panel.
  • the display panel includes at least two display partitions arranged along the column direction.
  • the gate drive circuit includes: at least two display partitions that correspond one to one and are independent of each other.
  • a gate drive module, the gate drive circuit is configured with multiple clock signal terminals and at least two start control signal terminals corresponding to the gate drive module, each gate drive module is connected to multiple The clock signal terminal is connected to the corresponding start control signal terminal.
  • the gate drive control method includes:
  • Step S1 Obtain the display mode information of the screen to be displayed.
  • the display mode information includes: the display mode of each display partition, and the display mode includes a high-definition mode or a low-definition mode.
  • the processing system can generate corresponding display mode information and send the display mode information to the gate drive control system through a preset interface (for example, DP interface).
  • a preset interface for example, DP interface
  • Step S2 For any display partition, output clock signals corresponding to the display mode to multiple clock signal terminals according to the display mode of the display partition.
  • clock signals corresponding to the high-definition mode are output to multiple clock signal terminals to control the gate driving module corresponding to the display partition to perform each row of sub-pixels in the display partition one by one.
  • Line scan driver when the display mode of the display partition is low-definition mode, clock signals corresponding to the low-definition mode are output to multiple clock signal terminals to control the gate drive module corresponding to the display partition to control each row in the display partition.
  • the sub-pixels are scanned and driven for N lines simultaneously, N is an integer and N ⁇ 2.
  • clock signals corresponding to the high-definition mode are output to multiple clock signal terminals to control the gate driving module corresponding to the display partition to Each row of sub-pixels is driven by progressive scanning so that the display partition can be imaged and displayed clearly.
  • clock signals corresponding to the low-definition mode are output to multiple clock signal terminals to control the gate driving module corresponding to the display partition to perform N operation on each row of sub-pixels in the display partition.
  • Line-by-line simultaneous scanning driver compared with progressive scanning, it can speed up the refresh speed of the low-definition display partition, thereby effectively reducing the number of scan drives for the low-definition display partition.
  • the display partition includes M rows of sub-pixels.
  • the number of scan drives corresponding to the display partition is M.
  • N lines of simultaneous scan driving are used, the number of scan drives corresponding to the display partition is M. /N; Since N ⁇ 2, M>M/N. Since the number of scan drives for the display partition in low-definition mode is reduced Less, so the total number of scan drives corresponding to displaying a complete frame is also reduced.
  • the total scan drive duration for displaying a complete frame is reduced, which is beneficial to improving the display refresh rate of the display device.
  • the corresponding time of a single scan drive can be increased accordingly to ensure complete writing of the data voltage to increase the pixel charging rate.
  • Figure 6 is a schematic diagram of the clock signal received by the gate drive module corresponding to the display partition DS2 and the display partition DS3 in Figure 4 and the output scan drive signal.
  • Figure 7 is a schematic diagram of the clock signal received by the gate drive module corresponding to the display partition DS2 and the display partition DS3 in Figure 4.
  • STV2 and STV3 respectively represent the starting control signal terminals configured by the gate driving modules corresponding to the display partition DS2 and the display partition DS3.
  • Figures 6 and 7 exemplarily illustrate the scanning drive signals output by the eight signal output terminals OUT2_1 ⁇ OUT2_8 in the gate drive module corresponding to the display partition DS2, and the gate drive module corresponding to the display partition DS3.
  • the display mode of display partition DS2 is high-definition mode, and its corresponding gate drive module adopts progressive scanning drive for the sub-pixel rows in display partition DS2, and the time when the eight clock signal terminals are in the active level state is staggered in sequence.
  • the time at which the scan drive signals output by the signal output terminals OUT2_1 to OUT2_8 of the gate drive module corresponding to the display partition DS2 are in the active level state are sequentially staggered, thereby achieving progressive scan driving for the sub-pixel rows in the display partition DS2.
  • the display mode of display partition DS3 is low-definition mode.
  • the corresponding gate driver module adopts 4 lines of simultaneous scanning drive for the sub-pixel rows in display partition DS3 (that is, the aforementioned N value is 4), and the 4 clock signal terminals CK1 ⁇ CK4 is in the active level state at the same time, the four clock signal terminals CK5 ⁇ CK8 are in the active level state at the same time, and the clock signal terminals CK1 ⁇ CK4 and the clock signal terminals CK5 ⁇ CK8 are in the active level state at a staggered time .
  • the scan drive signals output by the four signal output terminals OUT3_1 ⁇ OUT3_4 of the gate drive module corresponding to the display partition DS3 are at the active level for the same time, and the scan drive signals output by the four signal output terminals OUT3_5 ⁇ OUT3_8 are active.
  • the time of the level state is the same, and the signal output terminals OUT3_1 ⁇ OUT3_4 and the signal output terminals OUT3_5 ⁇ OUT3_8 are valid
  • the time of the level state is staggered, thereby achieving 4-line simultaneous scanning driving for the sub-pixel rows in the display partition DS3.
  • the number of clock signal lines mentioned above is 8, and the case where N is 4 is only used as an example and does not limit the technical solution of the present disclosure.
  • the number of clock signal lines can also be 16, 24, etc., and the value of N can be 2, 4, 8, etc., and no examples will be described here.
  • the configured clock signal line is certain, the value of N can be designed accordingly.
  • FIG 8 is a flow chart of another gate drive control method provided by an embodiment of the present disclosure.
  • the display mode information also includes: the driving duration of each display partition, the gate drive Control methods also include:
  • Step S3 For any display partition, according to the driving duration of the display partition and the preset start control signal waveform parameters, output the start control signal to the start control signal terminal corresponding to the display partition to control the corresponding start control signal of the display partition.
  • the gate driving module scans and drives each row of sub-pixels in the display partition within the driving time period.
  • the starting time of the start control signal output to the gate drive module corresponding to the display partition and the clock signal output to the gate drive module corresponding to the display partition should remain Synchronization to ensure the normal operation of the gate drive module corresponding to the display partition.
  • the start control signal waveform parameters include: the front porch (Front Porch) duration of the start control signal, and the duration of the start control signal being in an active level state (Active).
  • the front porch duration represents the time elapsed from the starting moment of a cycle (at which the signal is in an inactive level state) to when the signal switches to an active level state.
  • FP2 refers to the length of the start control signal output to the gate drive module corresponding to the display partition DS2
  • FP3 refers to the time duration of the start control signal output to the gate drive module corresponding to the display partition DS3.
  • Duration; in Figures 6 and 7, AC2 refers to the duration during which the start control signal output to the gate drive module corresponding to the display partition DS2 is at an active level
  • AC3 refers to the start control signal output to the gate drive module corresponding to the display partition DS3.
  • the initial control signal is in the effective level state for the duration.
  • the start control signal corresponding to the display partition whose display mode is high-definition mode is The start control signal provided by the number terminal is the preset first start control signal; the start control signal provided to the start control signal terminal corresponding to the display partition in the low-definition mode is the preset first control signal.
  • the duration AC2 during which the first start control signal is in the active level state is equal to the duration AC3 during which the second start control signal is in the active level state. As shown in FIG. 7 , the duration AC2 during which the first start control signal is in the active level state is greater than the duration AC3 during which the second start control signal is at the active level state.
  • the duration of the first start control signal in the active level state must ensure that the signal output terminals OUT2_1 ⁇ OUT2_4 can complete the output of the clock signal in the active level state.
  • the duration for which the initial control signal is in the active level state must ensure that the signal output terminals OUT3_1 ⁇ OUT3_4 can complete outputting the clock signal in the active level state.
  • the duration of the active level state of the clock signal output in a single cycle is H (that is, the duration corresponding to a single scan drive is H)
  • the duration of the first start control signal in the active level state in Figures 6 and 7
  • the minimum value is 4*H
  • the minimum value of the duration of the second start control signal in the active level state is 2*H. Therefore, the duration during which the second initial control signal is in the active level state may be shorter than the duration during which the first initial control signal is at the active level.
  • the display partition in the low-definition mode can be reduced.
  • the driving time is reduced, thereby reducing the total scanning driving time for displaying a complete frame, which is beneficial to improving the display refresh rate of the display device.
  • FIG 9 is a flow chart of an optional implementation of step S2 in an embodiment of the present disclosure. As shown in Figure 9, in some embodiments, step S2 shown in Figures 5 and 8 may include:
  • Step S201 Determine clock signal waveform parameters corresponding to the display mode according to the display mode of the display partition.
  • Step S202 Output corresponding clock signals to multiple clock signal terminals according to the clock signal waveform parameters.
  • the clock signal waveform parameters include: cycle length of the clock signal, clock signal The number of cycles of the signal, the duration of the clock signal in a single cycle, and the duration of the clock signal in a valid level state in a single cycle.
  • the clock signal corresponding to the high-definition mode output to the plurality of clock signal terminals is a preset first clock signal; the clock signal corresponding to the high-definition mode output to the plurality of clock signal terminals is The preset second clock signal; the duration of the first clock signal being in the active level state within a single cycle is less than or equal to the duration that the second clock signal is in the active level state within a single cycle.
  • FIG 10 is a schematic diagram of the clock signal received by the gate drive module corresponding to the display partition DS2 and the display partition DS3 in Figure 4 and the scan drive signal output.
  • AC2' refers to The duration for which the clock signal output to the gate drive module corresponding to the display partition DS2 is in the active level state
  • AC3' refers to the duration for which the clock signal output to the gate drive module corresponding to the display partition DS3 is at the active level.
  • the duration AC2′ of the first clock signal in the active level state is equal to the duration AC3 of the second clock signal in the active level state. As shown in Figure 10, the duration AC2' of the first clock signal in the active level state is shorter than the duration AC3 of the second clock signal in the active level state.
  • the scan driver duration of the display partition can be shortened.
  • the corresponding duration of the single scan drive can be appropriately increased, and it is ensured that the scan drive duration of the display partition does not exceed the scan drive duration corresponding to the progressive scan drive.
  • FIG 11A is a structural block diagram of a gate drive control system provided by an embodiment of the present disclosure.
  • the gate drive control system can be used to implement the gate drive method in the above embodiment.
  • the gate drive control system The system is used to control the driving operation of the gate drive circuit.
  • the gate drive circuit is used to drive the display panel.
  • the display panel includes at least two display partitions arranged along the column direction.
  • the gate drive circuit includes: one-to-one correspondence with the display partitions and At least two gate drive modules that are independent of each other.
  • the gate drive control system includes: a first acquisition module 501 and a first processing module 502.
  • the first acquisition module 501 is configured to acquire the display mode information of the picture to be displayed.
  • the display mode information includes: the display mode of each display partition, and the display mode includes a high-definition mode or a low-definition mode.
  • the first processing module 502 is configured to, for any display partition, output clock signals corresponding to the display mode to multiple clock signal terminals according to the display mode of the display partition; wherein, when the display mode of the display partition is high-definition mode, A clock signal terminal outputs a clock signal corresponding to the high-definition mode to control the gate drive module corresponding to the display partition to perform progressive scan driving of each row of sub-pixels in the display partition; when the display mode of the display partition is low-definition mode , output clock signals corresponding to the low-definition mode to multiple clock signal terminals to control the gate drive module corresponding to the display partition to perform N lines of simultaneous scanning and driving of each row of sub-pixels in the display partition, N is an integer and N ⁇ 2.
  • the display mode information also includes: the driving duration of each display partition;
  • the gate drive control system also includes: a second processing module 503, the second processing module 503 is configured to, for any display partition, according to the display partition
  • the driving duration and the preset starting control signal waveform parameters are used to output the starting control signal to the starting control signal terminal corresponding to the display partition to control the gate driving module corresponding to the display partition to control the gate drive module in the display partition during the driving time.
  • Each row of sub-pixels is scan driven.
  • the start control signal waveform parameters include: the length of the front porch of the start control signal, and the duration of the start control signal being in a valid level state.
  • the start control signal provided by the second processing module to the start control signal terminal corresponding to the display partition in the high-definition mode is a preset first start control signal;
  • the start control signal provided by the start control signal terminal corresponding to the display partition in the low-definition mode is the preset second start control signal; the duration of the first start control signal in the active level state is longer than Or equal to the duration during which the second start control signal is in a valid level state.
  • the first processing module 502 includes: a first determination unit 5021 and a first output unit 5022.
  • the first determining unit 5021 is configured to determine, according to the display mode of the display partition, the The clock signal waveform parameters corresponding to the mode.
  • the first output unit 5022 is configured to output corresponding clock signals to multiple clock signal terminals according to clock signal waveform parameters.
  • the clock signal waveform parameters include: the cycle duration of the clock signal, the number of cycles of the clock signal, the duration of the clock signal in a single cycle, and the duration of the clock signal in an active level state in a single cycle.
  • the clock signal corresponding to the high-definition mode output by the first processing module 502 to the plurality of clock signal terminals is a preset first clock signal; the clock signal output by the second processing module 503 to the plurality of clock signal terminals is The clock signal corresponding to the high-definition mode is a preset second clock signal; the duration in which the first clock signal is in an active level state in a single cycle is less than or equal to the duration in which the second clock signal is in an active level state in a single cycle.
  • FIG. 12 is a structural block diagram of a display driving system provided by an embodiment of the present disclosure.
  • the display driving system includes a gate driving control system 5 .
  • the gate driving control system please refer to the content in the previous embodiments and will not be described again here.
  • the display driving system further includes: a source driving circuit 7 and a gate driving circuit 6 .
  • the source driving circuit 7 is configured to receive display data information of the picture to be displayed, and provide corresponding data voltages to each sub-pixel according to the display data of each sub-pixel recorded in the display data information.
  • the gate drive circuit 6 includes at least two gate drive modules; the gate drive module is configured to respond to a start control signal provided by a start control signal terminal and control according to clock signals provided by a plurality of clock signal terminals. Each row of sub-pixels in the corresponding display partition is scan-driven.
  • the first acquisition module in the gate drive control system 5 acquires the display mode information.
  • the interface is the same as the interface through which the source driver circuit 7 obtains display data information; the display mode information is obtained before the display data information.
  • the interface through which the processing system sends display mode information and display data information to the display driving system is the same interface (for example, DP interface).
  • This design is beneficial to reducing the number of interfaces required to be configured in the system. .
  • the processing system will first transfer a piece of empty data before using the DP interface to transfer the display data information of each frame. That is, after sending the frame start identifier, the processing system will first send a period of empty data, and then send data showing the data information.
  • the position used for transmitting null data in the related art is used to transmit the display mode information; for example, a certain number of bits (for example, 24 bit) space can be designed to transmit the display mode information before sending the display data information.
  • a separate interface can also be configured for the display mode information, that is, the display mode information is transmitted using the separately configured interface, and the display data information is transmitted using the DP interface. This situation should also fall within the protection scope of this disclosure.
  • embodiments of the present disclosure also provide a display device.
  • the display device includes a display panel and a display driving system.
  • the display driving system can adopt the display driving system provided in the previous embodiment.
  • the display driving system may also include an image acquisition module and a processing system.
  • image acquisition module and processing system please refer to the content in the previous embodiments and will not be described again here.
  • FIG 13 is a schematic structural diagram of an electronic device according to an embodiment of the present disclosure.
  • an electronic device provided by an embodiment of the present disclosure includes: one or more processors 101, a memory 102, one or more I/ O interface 103.
  • One or more programs are stored on the memory 102.
  • the one or more processors implement the display control method as in any of the above embodiments;
  • one One or more I/O interfaces 103 are connected between the processor and the memory, and are configured to realize information exchange between the processor and the memory.
  • the processor 101 is a device with data processing capabilities, including but not limited to a central processing unit (CPU), etc.
  • the memory 102 is a device with data storage capabilities, including but not limited to random access memory.
  • Access memory RAM, more specifically such as SDRAM, DDR, etc.
  • ROM read-only memory
  • EEPROM electrically erasable programmable read-only memory
  • FLASH flash memory
  • the I/O interface (read-write interface) 103 is connected to Between the processor 101 and the memory 102, information exchange between the processor 101 and the memory 102 can be realized, which includes but is not limited to a data bus (Bus), etc.
  • processor 101 memory 102, and I/O interface 103 are connected to each other and, in turn, to other components of the computing device via bus 104.
  • the one or more processors 101 include a field programmable gate array.
  • a computer-readable medium stores a computer program, wherein when the program is executed by the processor, the steps in the image display control method in any of the above embodiments are implemented.
  • embodiments of the present disclosure include a computer program product including a computer program carried on a machine-readable medium, the computer program containing program code for performing the method illustrated in the flowchart.
  • the computer program may be downloaded and installed from the network via the communications component, and/or installed from removable media.
  • CPU central processing unit
  • the computer-readable medium shown in the present disclosure may be a computer-readable signal medium or a computer-readable storage medium, or any combination of the above two.
  • the computer-readable storage medium may be, for example, but is not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus or device, or any combination thereof. More specific examples of computer readable storage media may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard drive, random access memory (RAM), read only memory (ROM), removable Programmd read-only memory (EPROM or flash memory), fiber optics, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination of the above.
  • a computer-readable storage medium may be any tangible medium that contains or stores a program for use by or in connection with an instruction execution system, apparatus, or device.
  • a computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code therein. this spread The data signals can take many forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above.
  • a computer-readable signal medium may also be any computer-readable medium other than a computer-readable storage medium that can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device .
  • Program code embodied on a computer-readable medium may be transmitted using any suitable medium, including but not limited to: wireless, wire, optical cable, RF, etc., or any suitable combination of the foregoing.
  • each block in the flowchart or block diagrams may represent a module, segment, or portion of code that contains one or more components that implement the specified logical function(s). executable instructions.
  • the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown one after another may actually execute substantially in parallel, or they may sometimes execute in the reverse order, depending on the functionality involved.
  • each block of the block diagram and/or flowchart illustration, and combinations of blocks in the block diagram and/or flowchart illustration can be implemented by special purpose hardware-based systems that perform the specified functions or operations. , or can be implemented using a combination of specialized hardware and computer instructions.
  • the circuits or sub-circuits described in the embodiments of the present disclosure may be implemented in software or hardware.
  • the described circuit or sub-circuit can also be provided in a processor.
  • a processor including: a receiving circuit and a processing circuit.
  • the processing module includes a writing sub-circuit and a reading sub-circuit.
  • the names of these circuits or sub-circuits do not constitute a limitation on the circuit or sub-circuit itself under certain circumstances.
  • a receiving circuit can also be described as "receiving video signals".

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Abstract

本公开提供了一种栅极驱动控制方法，包括：获取待显示画面的显示模式信息，显示模式信息包括：各显示分区的显示模式，显示模式包括高清模式或低清模式；针对任一显示分区，根据显示分区的显示模式向多个时钟信号端输出与显示模式相对应的时钟信号；其中，在显示分区的显示模式为高清模式时，向多个时钟信号端输出与高清模式相对应的时钟信号，以控制显示分区所对应的栅极驱动模块对显示分区内的各行亚像素进行逐行扫描驱动；在显示分区的显示模式为低清模式时，向多个时钟信号端输出与低清模式相对应的时钟信号，以控制显示分区所对应的栅极驱动模块对显示分区内的各行亚像素进行N行同时扫描驱动,N为整数且N≥2。

Description

栅极驱动控制方法及其系统、显示驱动系统、显示装置 技术领域
本发明涉及显示领域，特别涉及一种栅极驱动控制方法及其系统、显示驱动系统、显示装置、电子设备和计算机可读介质。
背景技术
目前，随着对显示分辨率及刷新率的要求越来越高，对显示面板的充电时间要求更加严苛。尤其是在虚拟现实技术(VR/AR)中，由于需要对人眼注视的区域进行实时分析，之后对人眼需要的视觉敏锐度高的高清成像区域进行渲染，因此，为了达到较好的虚拟现实显示效果，对于显示分辨率和像素充电率的要求会非常高，目前现有的显示机制是逐行扫描显示面板中的各行像素，已不能满足刷新率和像素充电率的要求。
发明内容
本发明旨在至少解决现有技术中存在的技术问题之一，提出了一种栅极驱动控制方法及其系统、显示驱动系统、显示装置、电子设备和计算机可读介质。
第一方面，本公开实施例提供了一种栅极驱动控制方法，用于控制栅极驱动电路的驱动操作，所述栅极驱动电路用于驱动显示面板，所述显示面板包括沿列方向排布的至少两个显示分区，所述栅极驱动电路包括：与所述显示分区一一对应且彼此独立的至少两个栅极驱动模块，所述栅极驱动电路配置有多个时钟信号端和与所述栅极驱动模块一一对应的至少两个起始控制信号端，各所述栅极驱动模块均与所述多个时钟信号端和对应的所述起始控制信号端相连；所述栅极驱动控制方法，包括：
获取待显示画面的显示模式信息，所述显示模式信息包括：各所述显示分区的显示模式，所述显示模式包括高清模式或低清模式；
针对任一所述显示分区，根据所述显示分区的显示模式向所述多个时钟信 号端输出与所述显示模式相对应的时钟信号；
其中，在所述显示分区的显示模式为高清模式时，向所述多个时钟信号端输出与所述高清模式相对应的时钟信号，以控制所述显示分区所对应的栅极驱动模块对所述显示分区内的各行亚像素进行逐行扫描驱动；
在所述显示分区的显示模式为低清模式时，向所述多个时钟信号端输出与所述低清模式相对应的时钟信号，以控制所述显示分区所对应的栅极驱动模块对所述显示分区内的各行亚像素进行N行同时扫描驱动,N为整数且N≥2。
在一些实施例中，所述显示模式信息还包括：各所述显示分区的驱动时长；
所述栅极驱动控制方法，还包括：
针对任一所述显示分区，根据所述显示分区的驱动时长和预设的起始控制信号波形参数，向所述显示分区所对应的所述起始控制信号端输出起始控制信号，以控制所述显示分区所对应的栅极驱动模块在所述驱动时长内对所述显示分区内的各行亚像素进行扫描驱动。
在一些实施例中，所述起始控制信号波形参数包括：所述起始控制信号的前廊时长、所述起始控制信号处于有效电平状态的持续时长。
在一些实施例中，向显示模式为高清模式的所述显示分区所对应的所述起始控制信号端所提供的起始控制信号，为预设的第一起始控制信号；
向显示模式为低清模式的所述显示分区所对应的所述起始控制信号端所提供的起始控制信号，为预设的第二起始控制信号；
所述第一起始控制信号处于有效电平状态的持续时长大于或等于所述第二起始控制信号处于有效电平状态的持续时长。
在一些实施例中，根据所述显示分区的显示模式向所述多个时钟信号端输出与所述显示模式相对应的时钟信号的步骤，包括：
根据所述显示分区的显示模式，确定出与所述显示模式相对应的时钟信号波形参数；
根据所述时钟信号波形参数向所述多个时钟信号端输出相应的时钟信号。
在一些实施例中，所述时钟信号波形参数包括：时钟信号的周期时长、时 钟信号的周期数量、时钟信号在单个周期内的前廊时长、时钟信号在单个周期内处于有效电平状态的持续时长。
在一些实施例中，向所述多个时钟信号端输出的与所述高清模式相对应的时钟信号，为预设的第一时钟信号；
向所述多个时钟信号端输出的与所述高清模式相对应的时钟信号，为预设的第二时钟信号；
所述第一时钟信号在单个周期内处于有效电平状态时长小于或等于所述第二时钟信号在单个周期内处于有效电平状态时长。
第二方面，本公开实施例提供了一种栅极驱动控制系统，用于控制栅极驱动电路的驱动操作，所述栅极驱动电路用于驱动显示面板，所述显示面板包括沿列方向排布的至少两个显示分区，所述栅极驱动电路包括：与所述显示分区一一对应且彼此独立的至少两个栅极驱动模块，所述栅极驱动电路配置有多个时钟信号端和与所述栅极驱动模块一一对应的至少两个起始控制信号端，各所述栅极驱动模块均与所述多个时钟信号端和对应的所述起始控制信号端相连；所述栅极驱动控制系统，包括：
第一获取模块，配置为获取待显示画面的显示模式信息，所述显示模式信息包括：各所述显示分区的显示模式，所述显示模式包括高清模式或低清模式；
第一处理模块，配置为针对任一所述显示分区，根据所述显示分区的显示模式向所述多个时钟信号端输出与所述显示模式相对应的时钟信号；
其中，在所述显示分区的显示模式为高清模式时，向所述多个时钟信号端输出与所述高清模式相对应的时钟信号，以控制所述显示分区所对应的栅极驱动模块对所述显示分区内的各行亚像素进行逐行扫描驱动；
在所述显示分区的显示模式为低清模式时，向所述多个时钟信号端输出与所述低清模式相对应的时钟信号，以控制所述显示分区所对应的栅极驱动模块对所述显示分区内的各行亚像素进行N行同时扫描驱动,N为整数且N≥2。
在一些实施例中，所述显示模式信息还包括：各所述显示分区的驱动时长；
所述栅极驱动控制系统还包括：
第二处理模块，配置为针对任一所述显示分区，根据所述显示分区的驱动时长和预设的起始控制信号波形参数，向所述显示分区所对应的所述起始控制信号端输出起始控制信号，以控制所述显示分区所对应的栅极驱动模块在所述驱动时长内对所述显示分区内的各行亚像素进行扫描驱动。
在一些实施例中，所述起始控制信号波形参数包括：所述起始控制信号的前廊时长、所述起始控制信号处于有效电平状态的持续时长。
在一些实施例中，向显示模式为高清模式的所述显示分区所对应的所述起始控制信号端所提供的起始控制信号，为预设的第一起始控制信号；
向显示模式为低清模式的所述显示分区所对应的所述起始控制信号端所提供的起始控制信号，为预设的第二起始控制信号；
所述第一起始控制信号处于有效电平状态的持续时长大于或等于所述第二起始控制信号处于有效电平状态的持续时长。
在一些实施例中，所述第一处理模块包括：
第一确定单元，配置为根据所述显示分区的显示模式，确定出与所述显示模式相对应的时钟信号波形参数；
第一输出单元，配置为根据所述时钟信号波形参数向所述多个时钟信号端输出相应的时钟信号。
在一些实施例中，所述时钟信号波形参数包括：时钟信号的周期时长、时钟信号的周期数量、时钟信号在单个周期内的前廊时长、时钟信号在单个周期内处于有效电平状态的持续时长。
在一些实施例中，向所述多个时钟信号端输出的与所述高清模式相对应的时钟信号，为预设的第一时钟信号；
向所述多个时钟信号端输出的与所述高清模式相对应的时钟信号，为预设的第二时钟信号；
所述第一时钟信号在单个周期内处于有效电平状态时长小于或等于所述第二时钟信号在单个周期内处于有效电平状态时长。
第三方面，本公开实施例还提供了一种显示驱动系统，包括：如上述第二 方面中提供的所述栅极驱动控制系统。
在一些实施例中，还包括：
源极驱动电路，配置为接收待显示画面的显示数据信息，并根据所述显示数据信息内记载的各亚像素的显示数据向各亚像素提供对应的数据电压；
所述栅极驱动电路，包括至少两个所述栅极驱动模块；
所述栅极驱动模块，配置为响应于所述起始控制信号端所提供起始控制信号和所述多个时钟信号端所提供的时钟信号的控制，对对应的所述显示分区内的各行亚像素进行扫描驱动。
在一些实施例中，所述第一获取模块获取所述显示模式信息的接口与所述源极驱动电路获取所述显示数据信息的接口为同一接口；
所述显示模式信息位于所述显示数据信息之前被获取。
第三方面，本公开实施例还提供了一种显示装置，其特征在于，包括：显示面板和第二方面中提供的所述显示驱动系统。
第四方面，本公开实施例还提供了一种电子设备，其包括：
一个或多个处理器；
存储器，用于存储一个或多个程序；
当所述一个或多个程序被所述一个或多个处理器执行，使得所述一个或多个处理器实现如第一方面中提供的所述栅极驱动控制方法。
在一些实施例中，所述处理器包括现场可编程门阵列。
第五方面，本公开实施例还提供了一种计算机可读介质，其上存储有计算机程序，其中，所述计算机程序在被处理器执行时实现如第一方面中提供的所述栅极驱动控制方法中的步骤。
附图说明
图1A为本公开技术方案所涉及显示装置的一种系统化结构框图；
图1B为图1A中所示显示装置的具体结构框图；
图2为本公开实施例中一个亚像素的一种电路结构示意图；
图3为本公开实施例中一个亚像素的一种电路结构示意图；
图4为本公开实施例中确定显示分区的显示模式的一种原理示意图；
图5为本公开实施例提供的一种栅极驱动控制方法的流程图；
图6为图4中显示分区DS2和显示分区DS3所对应栅极驱动模块接收到的时钟信号以及输出的扫描驱动信号的一种示意图；
图7为图4中显示分区DS2和显示分区DS3所对应栅极驱动模块接收到的时钟信号以及输出的扫描驱动信号的另一种示意图；
图8为本公开实施例提供的另一种栅极驱动控制方法的流程图；
图9为本公开实施例中步骤S2的一种可选实现方案的流程图；
图10为图4中显示分区DS2和显示分区DS3所对应栅极驱动模块接收到的时钟信号以及输出的扫描驱动信号的一种示意图；
图11A为本公开实施例提供的一种栅极驱动控制系统的结构框图；
图11B为本公开实施例提供的第一处理模块的结构框图；
图12为本公开实施例提供的一种显示驱动系统的结构框图；
图13为本公开实施例的一种电子设备的结构示意图。
具体实施方式
为使本领域的技术人员更好地理解本发明的技术方案，下面结合附图对本发明提供的一种栅极驱动控制方法及其系统、显示驱动系统、显示装置、电子设备和计算机可读介质进行详细描述。
图1A为本公开技术方案所涉及显示装置的一种系统化结构框图，如图1A所示，该显示装置包括：显示面板1、图像获取模块2、处理系统3和显示驱动系统4。
其中，按照显示维度来划分，显示面板1可以为2D显示面板或3D显示面板；按照发光类型来划分，显示面板1可以为液晶显示面板(LCD)、发光二极 管(LED)显示面板、有机发光二极管(OLED)显示面板或量子点发光二极管(QLED)显示面板。本公开的技术方案对于显示面板1的类型和结构不作限定。在本公开实施例中，显示面板1包括沿行方向和列方向呈阵列排布的多个亚像素，每个亚像素与对应行栅线和对应列数据线相连。
图2为本公开实施例中一个亚像素的一种电路结构示意图，如图2所示，该亚像素为液晶显示面板1中的亚像素，包括开关晶体管T0和像素电极，开关晶体管T0的控制极与对应行栅线GATE相连，开关晶体管T0的第一极与数据线DATA相连，开关晶体管T0的第二极与像素电极相连。在栅线GATE所提供的驱动信号处于有效电平状态时，开关晶体管T0导通，数据线DATA中的数据电压写入至像素电极。
图3为本公开实施例中一个亚像素的一种电路结构示意图，如图3所示，该亚像素为LED/OLED/QLED二极管显示面板1中的亚像素，包括：数据写入晶体管T1、驱动晶体管DTFT和发光元件EL(具体可以为LED、OLED或QLED)；数据写入晶体管T1的控制极与对应行栅线GATE相连，数据写入晶体管T1的第一极与数据线DATA相连，数据写入晶体管T1的第二极与驱动晶体管DTFT的控制极相连，驱动晶体管DTFT的第一极与电源端VDD相连，驱动晶体管DTFT的第二极与发光元件EL相连。在栅线GATE所提供的驱动信号处于有效电平状态时，数据写入晶体管T1导通，数据线DATA中的数据电压写入至驱动晶体管DTFT的控制极，驱动晶体管DTFT输出相应驱动电流。
需要说明的是，本公开实施例中亚像素的电路结构不限于图2和图3中所示，还可以采用其他电路结构，此处不再一一举例说明。
与常规的显示面板1有所不同，在本公开实施例中，将显示面板1沿列方向划分为多个显示分区，各显示分区可以独立的被驱动，各显示分区的显示模式可以独立的被设置。其中，显示模式可以为高清模式或低清模式。各显示分区所包含的亚像素行数可以相同，也可以不同。各显示分区的显示模式可以相同，也可以不同。
图像获取模块2用于获取观看用户的人眼图像，并将人眼图像传输至处理 系统3。图像获取模块2可集成在显示面板1上或单独设置；图像获取模块2具体可以为摄像头。
处理系统3可用于根据图像获取模块2所获取到的人眼图像确定出人眼在显示面板1上的注视点坐标，并基于该注视点坐标来估算出人眼注视区域范围，并根据人眼注视范围来确定出显示面板1上各显示分区的显示模式。
图4为本公开实施例中确定显示分区的显示模式的一种原理示意图，如图4所示，显示面板1包括由从上至下依次排布的6个显示分区DS1～DS6，通过人眼图像所确定出的人眼注视点为点A。首先，根据点A的坐标以及预先设置的人眼注视区域评估算法，估算出人眼注视区域范围Q；可选地，人眼注视区域范围Q可以为以点A为圆心且具有预设半径的圆形区域(参见图4中所示)；或者，人眼注视区域范围Q可以为以点A为中心且具有预设长度和预设宽度的矩形区域(未给出相应附图)。当然，本公开技术方案对于人眼注视区域评估算法的具体算法不作限定。在确定出人眼注视区域范围Q后，将与人眼注视区域范围Q存在交叠的显示分区(例如，图4中显示分区DS1～DS2)的显示模式设置为高清模式，将与人眼注视区域范围Q不存在交叠的显示分区(例如，图4中显示分区DS3～DS6)的显示模式设置为低清模式。
处理系统3还可以从外部信号端接收待显示画面的原始显示数据信息，具体包括待显示面板1的各亚像素的显示数据(例如，灰阶数据)。在处理系统3获取到各显示分区的显示模式后，可对显示模式为低清模式的显示分区的显示图像进行降分辨率处理；具体地，对显示模式为低清模式的显示分区的亚像素的灰阶数据进行压缩处理，以使得位于同一列的每N个亚像素的灰阶数据为同一灰阶数据(同一列的每N个亚像素合并为一个亚像素)，其中N为整数且N≥2，N的具体取值可以根据实际需要来进行预先设计或调整。需要说明的是，本公开的技术方案对于降分辨率处理所采用的具体算法不作限定，仅需实现将显示模式为低清模式的显示分区最终所呈现图像分辨率降低即可。对于显示模式为高清模式的显示分区所显示图像不作处理。
为方便描述，将显示模式为低清模式的显示分区所显示图像完成降分辨率 处理后得到的显示图像，称为低清显示图像；将显示模式为高清模式的显示分区所显示图像，称为高清显示图像；在对显示模式为低清模式的显示分区完成降分辨率处理后，将得到的低清显示图像与未作处理的高清显示图像进行融合处理，得到待显示画面的最终的显示数据信息。
处理系统3将待显示画面的显示模式信息(包括各显示分区的显示模式)以及待显示画面的最终的显示数据信息(包括各亚像素的最终的显示数据)，发送至显示驱动系统4。
显示驱动系统4至少包括栅极驱动控制系统5、栅极驱动电路6和源极驱动电路7。
如图1B所示，栅极驱动电路6包括：与显示分区一一对应且彼此独立的至少两个栅极驱动模块(图1B中仅示意性地示出两个栅极驱动模块，即栅极驱动模块6-1和栅极驱动模块6-2)，栅极驱动电路6配置有多个时钟信号端(图1B中仅示意性地示出四个时钟信号端CK1-CK4)和与栅极驱动模块一一对应的至少两个起始控制信号端(图1B中仅示意性地示出两个起始控制信号端STV1和STV2)，各栅极驱动模块均与多个时钟信号端和对应的起始控制信号端相连(如图1B所示出，栅极驱动模块6-1与四个时钟信号端CK1-CK4和对应的起始控制信号端STV1相连，栅极驱动模块6-2与四个时钟信号端CK1-CK4和对应的起始控制信号端STV2相连)，栅极驱动模块配置为响应于起始控制信号端所提供起始控制信号和多个时钟信号端所提供的时钟信号的控制，对对应的显示分区(图1B中仅示意性地示出两个分区，即DS1和DS2)内的各行亚像素进行扫描驱动。其中，栅极驱动模块的起始工作时间由起始控制信号端所提供起始控制信号来决定，栅极驱动模块对对应的显示分区内的亚像素的扫描驱动方式由多个时钟信号端所提供的时钟信号来决定。
栅极驱动控制系统5与栅极驱动电路6相连，栅极驱动控制系统5可用于根据待显示画面的显示模式信息，来调整输出给栅极驱动电路6内各栅极驱动模块的起始控制信号和时钟信号，从而控制各栅极驱动模块的工作时间以及扫描驱动方式。其中，栅极驱动控制系统5可以为基于现场可编程门阵列(Field  Programmable Gate Array，简称FPGA)和相应程序所实现的功能模块。
本公开实施例中栅极驱动电路6具体形式可以为基于FPGA和相应程序所实现具有栅极驱动功能的功能模块，也可以为具有栅极驱动功能的芯片(一般称为Gate IC)，也可以为基于阵列基板工艺直接形成于显示面板1的周边区域的电路结构(Gate on Array，简称为GOA)。本公开的技术方案对于栅极驱动电路6的具体形式和具体结构不作限定。
源极驱动电路7可根据接收到的显示数据信息向各亚像素提供对应的数据电压。源极驱动电路7具有多个数据通道(图1B中仅示意性地示出两个数据通道CH1和CH2)，数据通道具有将灰阶数据映射为对应像素电压并将像素电压输出给相应数据线的功能。本公开实施例中源极驱动电路7具体形式可以为基于FPGA和相应程序所实现具有源极驱动功能的功能模块，也可以为具有源极驱动功能的芯片(一般称为Source IC)。本公开的技术方案对于源极驱动电路7的具体形式和具体结构不作限定。
在一些实施例中，一个数据通道可以对应一条数据线或多条数据线(如图1B所示出，数据通道CH1对应一条数据线,数据通道CH2对应两条数据线)，在一个数据通道对应多条数据线时，在数据通道输出端与多条数据线之间设置有选通电路Cir(也称为MUX电路)，MUX电路包括与数据通道一一对应的多个MUX单元(图1B中仅示意性地示出一个MUX单元)，MUX单元中设置有与多条数据线一一对应的多个开关电路，通过时序来控制各开关电路依次导通(在任意时刻，MUX单元内至多一个开关电路处于导通状态)，以将数据通道所输出的数据电压写入至对应的数据线中。
图5为本公开实施例提供的一种栅极驱动控制方法的流程图，如图5所示，该栅极驱动控制方法应用于栅极驱动控制系统，该栅极驱动控制系统用于控制栅极驱动电路的驱动操作，栅极驱动电路用于驱动显示面板，显示面板包括沿列方向排布的至少两个显示分区，栅极驱动电路包括：与显示分区一一对应且彼此独立的至少两个栅极驱动模块，栅极驱动电路配置有多个时钟信号端和与栅极驱动模块一一对应的至少两个起始控制信号端，各栅极驱动模块均与多个 时钟信号端和对应的起始控制信号端相连。对于栅极驱动电路、显示面板的相关描述可参见前面实施例中的内容，此处不再赘述。该栅极驱动控制方法，包括：
步骤S1、获取待显示画面的显示模式信息。
其中，显示模式信息包括：各显示分区的显示模式，显示模式包括高清模式或低清模式。
处理系统在根据人眼图像确定出各显示分区的显示模式后，可生成相应的显示模式信息，并通过预设接口(例如，DP接口)将该显示模式信息发送给栅极驱动控制系统。
步骤S2、针对任一显示分区，根据显示分区的显示模式向多个时钟信号端输出与显示模式相对应的时钟信号。
其中，在显示分区的显示模式为高清模式时，向多个时钟信号端输出与高清模式相对应的时钟信号，以控制显示分区所对应的栅极驱动模块对显示分区内的各行亚像素进行逐行扫描驱动；在显示分区的显示模式为低清模式时，向多个时钟信号端输出与低清模式相对应的时钟信号，以控制显示分区所对应的栅极驱动模块对显示分区内的各行亚像素进行N行同时扫描驱动,N为整数且N≥2。
在本公开实施例中，在显示分区的显示模式为高清模式时，向多个时钟信号端输出与高清模式相对应的时钟信号，以控制显示分区所对应的栅极驱动模块对显示分区内的各行亚像素进行逐行扫描驱动，以使得该显示分区能够成像清晰显示。在显示分区的显示模式为低清模式时，向多个时钟信号端输出与低清模式相对应的时钟信号，以控制显示分区所对应的栅极驱动模块对显示分区内的各行亚像素进行N行同时扫描驱动；相对于逐行扫描，可以加快低清显示分区的刷新速度，由此有效减小该低清显示分区的扫描驱动次数。示例性地，显示分区包含M行亚像素，在采用逐行扫描驱动时该显示分区所对应的扫描驱动次数为M，在采用N行同时扫描驱动时该显示分区所对应的扫描驱动次数为M/N；由于N≥2，故M＞M/N。由于处于低清模式的显示分区的扫描驱动次数减 少，故显示完整一帧所对应的扫描驱动总次数也减少。
在单次扫描驱动所对应时长不变的情况下，显示完整一帧的扫描驱动总时长减少，有利于提升显示装置的显示刷新率。在显示完整一帧的扫描驱动总时长不变的情况下，单次扫描驱动所对应时长可以相应增长，可保证数据电压的完整写入，以提升像素充电率。
图6为图4中显示分区DS2和显示分区DS3所对应栅极驱动模块接收到的时钟信号以及输出的扫描驱动信号的一种示意图，图7为图4中显示分区DS2和显示分区DS3所对应栅极驱动模块接收到的时钟信号以及输出的扫描驱动信号的另一种示意图。如图6和图7所示，以栅极驱动电路配置有8个时钟信号端为例。其中，STV2和STV3分别表示显示分区DS2和显示分区DS3所对应的栅极驱动模块所配置的起始控制信号端。图6和图7中示例性画出了显示分区DS2所对应的栅极驱动模块内8个信号输出端OUT2_1～OUT2_8所输出扫描驱动信号的情况，以及显示分区DS3所对应的栅极驱动模块内8个信号输出端OUT3_1～OUT3_8所输出扫描驱动信号的情况。
显示分区DS2的显示模式为高清模式，其所对应的栅极驱动模块对显示分区DS2内亚像素行采用逐行扫描驱动，8个时钟信号端处于有效电平状态的时间依次错开。显示分区DS2所对应的栅极驱动模块的各信号输出端OUT2_1～OUT2_8所输出的扫描驱动信号处于有效电平状态的时间依次错开，从而实现对显示分区DS2内亚像素行采用逐行扫描驱动。
显示分区DS3的显示模式为低清模式，其所对应的栅极驱动模块对显示分区DS3内亚像素行采用4行同时扫描驱动(即前述的N取值为4)，4个时钟信号端CK1～CK4处于有效电平状态的时间相同，4个时钟信号端CK5～CK8处于有效电平状态的时间相同，且时钟信号端CK1～CK4与时钟信号端CK5～CK8处于有效电平状态的时间错开。显示分区DS3所对应的栅极驱动模块的4个信号输出端OUT3_1～OUT3_4所输出的扫描驱动信号处于有效电平状态的时间相同，4个信号输出端OUT3_5～OUT3_8所输出的扫描驱动信号处于有效电平状态的时间相同，且信号输出端OUT3_1～OUT3_4与信号输出端OUT3_5～OUT3_8处于有效 电平状态的时间错开，从而实现对显示分区DS3内亚像素行采用4行同时扫描驱动。
当然，上述时钟信号线的数量为8条，N取值为4的情况仅起到示例性作用，其不会对本公开的技术方案产生限制。例如，时钟信号线的数量还可以为16条、24条等，N的取值可以为2、4、8等，此处不再一一举例描述。本领域技术人员应该知晓的是，在所配置的时钟信号线一定的情况下，可以对N的取值进行相应设计。
图8为本公开实施例提供的另一种栅极驱动控制方法的流程图，如图8所示，在一些实施例中，显示模式信息还包括：各显示分区的驱动时长，该栅极驱动控制方法还包括：
步骤S3、针对任一显示分区，根据显示分区的驱动时长和预设的起始控制信号波形参数，向显示分区所对应的起始控制信号端输出起始控制信号，以控制显示分区所对应的栅极驱动模块在驱动时长内对显示分区内的各行亚像素进行扫描驱动。
需要说明的是，针对任一显示分区，输出给该显示分区所对应的栅极驱动模块的起始控制信号的起始时刻和输出给该显示分区所对应的栅极驱动模块的时钟信号应保持同步，以保证该显示分区所对应的栅极驱动模块的正常工作。
在一些实施例中，起始控制信号波形参数包括：起始控制信号的前廊(Front Porch)时长、起始控制信号处于有效电平状态(Active)的持续时长。其中，前廊时长表示从一个周期的起始时刻开始(在起始时刻该信号属于非有效电平状态)至该信号切换至有效电平状态所经历的时长。
图6和图7中FP2指输出给显示分区DS2所对应栅极驱动模块的起始控制信号的前廊时长，FP3指输出给显示分区DS3所对应栅极驱动模块的起始控制信号的前廊时长；图6和图7中AC2指输出给显示分区DS2所对应栅极驱动模块的起始控制信号处于有效电平状态的持续时长，AC3指输出给显示分区DS3所对应栅极驱动模块的起始控制信号处于有效电平状态的持续时长。
在一些实施例中，向显示模式为高清模式的显示分区所对应的起始控制信 号端所提供的起始控制信号，为预设的第一起始控制信号；向显示模式为低清模式的显示分区所对应的起始控制信号端所提供的起始控制信号，为预设的第二起始控制信号；第一起始控制信号处于有效电平状态的持续时长大于或等于第二起始控制信号处于有效电平状态的持续时长。
参见图6中所示，第一起始控制信号处于有效电平状态的持续时长AC2等于第二起始控制信号处于有效电平状态的持续时长AC3。参见图7中所示，第一起始控制信号处于有效电平状态的持续时长AC2大于第二起始控制信号处于有效电平状态的持续时长AC3。
以图6和图7中所示情况为例，第一起始控制信号处于有效电平状态的持续时长需保证信号输出端OUT2_1～OUT2_4均能够完成输出处于有效电平状态的时钟信号，第二起始控制信号处于有效电平状态的持续时长需保证信号输出端OUT3_1～OUT3_4均能够完成输出处于有效电平状态的时钟信号。假定，在单个周期内时钟信号输出有效电平状态的时长为H(即单次扫描驱动所对应时长为H)，则图6和图7中第一起始控制信号处于有效电平状态的持续时长的最小值为4*H，第二起始控制信号处于有效电平状态的持续时长的最小值为2*H。故，第二起始控制信号处于有效电平状态的持续时长是可以小于第一起始控制信号处于有效电平状态的持续时长。
在本公开实施例中，通过将第二起始控制信号处于有效电平状态的持续时长设计为小于第一起始控制信号处于有效电平状态的持续时长，可减少处于低清模式的显示分区的驱动时长，从而使得显示完整一帧的扫描驱动总时长减少，有利于提升显示装置的显示刷新率。
图9为本公开实施例中步骤S2的一种可选实现方案的流程图，如图9所示，在一些实施例中，图5和图8中所示步骤S2可包括：
步骤S201、根据显示分区的显示模式，确定出与显示模式相对应的时钟信号波形参数。
步骤S202、根据时钟信号波形参数向多个时钟信号端输出相应的时钟信号。
在一些实施例中，时钟信号波形参数包括：时钟信号的周期时长、时钟信 号的周期数量、时钟信号在单个周期内的前廊时长、时钟信号在单个周期内处于有效电平状态的持续时长。
在一些实施例中，向多个时钟信号端输出的与高清模式相对应的时钟信号，为预设的第一时钟信号；向多个时钟信号端输出的与高清模式相对应的时钟信号，为预设的第二时钟信号；第一时钟信号在单个周期内处于有效电平状态时长小于或等于第二时钟信号在单个周期内处于有效电平状态时长。
图10为图4中显示分区DS2和显示分区DS3所对应栅极驱动模块接收到的时钟信号以及输出的扫描驱动信号的一种示意图，如图6、图7和图10所示，AC2’指输出给显示分区DS2所对应栅极驱动模块的时钟信号处于有效电平状态的持续时长，AC3’指输出给显示分区DS3所对应栅极驱动模块的时钟信号处于有效电平状态的持续时长。
参见图6和图7中所示，第一时钟信号处于有效电平状态的持续时长AC2’等于第二时钟信号处于有效电平状态的持续时长AC3。参见图10中所示，第一时钟信号处于有效电平状态的持续时长AC2’小于第二时钟信号处于有效电平状态的持续时长AC3。
基于前面内容可见，对于处于低清模式的显示分区采用N行同时扫描驱动，且单次扫描驱动所对应时长不变的情况下，可以使得该显示分区的扫描驱动时长缩短。此时，可对单次扫描驱动所对应时长进行适当增长，并保证该显示分区的扫描驱动时长不超过采用逐行扫描驱动时所对应的扫描驱动时长。通过对处于低清模式的显示分区的单次扫描驱动时长进行适当增长，即亚像素的数据电压充电时间增长，有利于保证数据电压的完全写入。
基于同一发明构思，本公开实施例还提供了一种栅极驱动控制系统。图11A为本公开实施例提供的一种栅极驱动控制系统的结构框图，如图11A所示，该栅极驱动控制系统可用于实现上述实施例中的栅极驱动方法，该栅极驱动控制系统用于控制栅极驱动电路的驱动操作，栅极驱动电路用于驱动显示面板，显示面板包括沿列方向排布的至少两个显示分区，栅极驱动电路包括：与显示分区一一对应且彼此独立的至少两个栅极驱动模块，栅极驱动电路配置有多个时 钟信号端和与栅极驱动模块一一对应的至少两个起始控制信号端，各栅极驱动模块均与多个时钟信号端和对应的起始控制信号端相连。该栅极驱动控制系统，包括：第一获取模块501和第一处理模块502。
其中，第一获取模块501配置为获取待显示画面的显示模式信息，显示模式信息包括：各显示分区的显示模式，显示模式包括高清模式或低清模式。
第一处理模块502配置为针对任一显示分区，根据显示分区的显示模式向多个时钟信号端输出与显示模式相对应的时钟信号；其中，在显示分区的显示模式为高清模式时，向多个时钟信号端输出与高清模式相对应的时钟信号，以控制显示分区所对应的栅极驱动模块对显示分区内的各行亚像素进行逐行扫描驱动；在显示分区的显示模式为低清模式时，向多个时钟信号端输出与低清模式相对应的时钟信号，以控制显示分区所对应的栅极驱动模块对显示分区内的各行亚像素进行N行同时扫描驱动,N为整数且N≥2。
在一些实施例中，显示模式信息还包括：各显示分区的驱动时长；栅极驱动控制系统还包括：第二处理模块503，第二处理模块503配置为针对任一显示分区，根据显示分区的驱动时长和预设的起始控制信号波形参数，向显示分区所对应的起始控制信号端输出起始控制信号，以控制显示分区所对应的栅极驱动模块在驱动时长内对显示分区内的各行亚像素进行扫描驱动。
在一些实施例中，起始控制信号波形参数包括：起始控制信号的前廊时长、起始控制信号处于有效电平状态的持续时长。
在一些实施例中，第二处理模块向显示模式为高清模式的显示分区所对应的起始控制信号端所提供的起始控制信号，为预设的第一起始控制信号；第二处理模块向显示模式为低清模式的显示分区所对应的起始控制信号端所提供的起始控制信号，为预设的第二起始控制信号；第一起始控制信号处于有效电平状态的持续时长大于或等于第二起始控制信号处于有效电平状态的持续时长。
如图11B所示，在一些实施例中，第一处理模块502包括：第一确定单元5021和第一输出单元5022。
其中，第一确定单元5021配置为根据显示分区的显示模式，确定出与显示 模式相对应的时钟信号波形参数。
第一输出单元5022配置为根据时钟信号波形参数向多个时钟信号端输出相应的时钟信号。
在一些实施例中，时钟信号波形参数包括：时钟信号的周期时长、时钟信号的周期数量、时钟信号在单个周期内的前廊时长、时钟信号在单个周期内处于有效电平状态的持续时长。
在一些实施例中，第一处理模块502向多个时钟信号端输出的与高清模式相对应的时钟信号，为预设的第一时钟信号；第二处理模块503向多个时钟信号端输出的与高清模式相对应的时钟信号，为预设的第二时钟信号；第一时钟信号在单个周期内处于有效电平状态时长小于或等于第二时钟信号在单个周期内处于有效电平状态时长。
对于本实施例中各模块、单元的具体描述，可参见前面对栅极驱动控制方法中各步骤的相关描述内容，此处不再赘述。
基于同一发明构思，本公开实施例还提供了一种显示驱动系统。图12为本公开实施例提供的一种显示驱动系统的结构框图，如图12所示，该显示驱动系统包括：栅极驱动控制系统5。对应该栅极驱动控制系统的具体描述，可参见前面实施例中的内容，此处不再赘述。
在一些实施例中，该显示驱动系统还包括：源极驱动电路7和栅极驱动电路6。
其中，源极驱动电路7配置为接收待显示画面的显示数据信息，并根据显示数据信息内记载的各亚像素的显示数据向各亚像素提供对应的数据电压。
栅极驱动电路6包括至少两个栅极驱动模块；栅极驱动模块配置为响应于起始控制信号端所提供的起始控制信号和根据多个时钟信号端所提供的时钟信号的控制，对对应的显示分区内的各行亚像素进行扫描驱动。
对于源极驱动电路和栅极驱动电路的相关描述可参见前面对图1A和图1B的相关描述内容，此处不再赘述。
在一些实施例中栅极驱动控制系统5内第一获取模块获取显示模式信息的 接口与源极驱动电路7获取显示数据信息的接口为同一接口；显示模式信息位于显示数据信息之前被获取。
也就是说，在本公开实施例中，处理系统向显示驱动系统发送显示模式信息和显示数据信息的接口为同一接口(例如，DP接口)，通过该设计有利于减少系统所需配置的接口数量。
在相关技术中，处理系统在利用DP接口传递每一帧画面的显示数据信息之前，会先传递一段空数据。即，处理系统在发出帧起始标识之后，会先发送一段空数据，然后再发送显示数据信息的数据。在本公开实施例中，在相关技术中用于传递空数据的位置用来传递显示模式信息；例如，可在发送显示数据信息之前设计一定数位(例如，24bit)空间用来传递显示模式信息。
当然，在本公开实施例中，也可以为显示模式信息单独配置一个接口，即显示模式信息采用该单独配置的接口进行传递，显示数据信息采用DP接口进行传递。该情况也应属于本公开的保护范围。
基于同一发明构思，本公开实施例还提供了一种显示装置。参见图1A和图1B中所示，该显示装置包括显示面板和显示驱动系统，该显示驱动系统可采用前面实施例所提供的显示驱动系统。
在一些实施例中，该显示驱动系统还可以包括图像获取模块和处理系统。对于图像获取模块和处理系统的相关描述，可参见前面实施例中的内容，此处不再赘述。
图13为本公开实施例的一种电子设备的结构示意图，如图13所示，本公开实施例提供一种电子设备包括：一个或多个处理器101、存储器102、一个或多个I/O接口103。存储器102上存储有一个或多个程序，当该一个或多个程序被该一个或多个处理器执行，使得该一个或多个处理器实现如上述实施例中任一的显示控制方法；一个或多个I/O接口103连接在处理器与存储器之间，配置为实现处理器与存储器的信息交互。
其中，处理器101为具有数据处理能力的器件，其包括但不限于中央处理器(CPU)等；存储器102为具有数据存储能力的器件，其包括但不限于随机存 取存储器(RAM，更具体如SDRAM、DDR等)、只读存储器(ROM)、带电可擦可编程只读存储器(EEPROM)、闪存(FLASH)；I/O接口(读写接口)103连接在处理器101与存储器102间，能实现处理器101与存储器102的信息交互，其包括但不限于数据总线(Bus)等。
在一些实施例中，处理器101、存储器102和I/O接口103通过总线104相互连接，进而与计算设备的其它组件连接。
在一些实施例中，该一个或多个处理器101包括现场可编程门阵列。
根据本公开的实施例，还提供一种计算机可读介质。该计算机可读介质上存储有计算机程序，其中，该程序被处理器执行时实现如上述实施例中任一的图像显示控制方法中的步骤。
特别地，根据本公开实施例，上文参考流程图描述的过程可以被实现为计算机软件程序。例如，本公开的实施例包括一种计算机程序产品，其包括承载在机器可读介质上的计算机程序，该计算机程序包含用于执行流程图所示的方法的程序代码。在这样的实施例中，该计算机程序可以通过通信部分从网络上被下载和安装，和/或从可拆卸介质被安装。在该计算机程序被中央处理单元(CPU)执行时，执行本公开的系统中限定的上述功能。
需要说明的是，本公开所示的计算机可读介质可以是计算机可读信号介质或者计算机可读存储介质或者是上述两者的任意组合。计算机可读存储介质例如可以是——但不限于——电、磁、光、电磁、红外线、或半导体的系统、装置或器件，或者任意以上的组合。计算机可读存储介质的更具体的例子可以包括但不限于：具有一个或多个导线的电连接、便携式计算机磁盘、硬盘、随机访问存储器(RAM)、只读存储器(ROM)、可擦式可编程只读存储器(EPROM或闪存)、光纤、便携式紧凑磁盘只读存储器(CD-ROM)、光存储器件、磁存储器件、或者上述的任意合适的组合。在本公开中，计算机可读存储介质可以是任何包含或存储程序的有形介质，该程序可以被指令执行系统、装置或者器件使用或者与其结合使用。而在本公开中，计算机可读的信号介质可以包括在基带中或者作为载波一部分传播的数据信号，其中承载了计算机可读的程序代码。这种传播 的数据信号可以采用多种形式，包括但不限于电磁信号、光信号或上述的任意合适的组合。计算机可读的信号介质还可以是计算机可读存储介质以外的任何计算机可读介质，该计算机可读介质可以发送、传播或者传输用于由指令执行系统、装置或者器件使用或者与其结合使用的程序。计算机可读介质上包含的程序代码可以用任何适当的介质传输，包括但不限于：无线、电线、光缆、RF等等，或者上述的任意合适的组合。
附图中的流程图和框图，图示了按照本公开各种实施例的系统、方法和计算机程序产品的可能实现的体系架构、功能和操作。在这点上，流程图或框图中的每个方框可以代表一个模块、程序段、或代码的一部分，前述模块、程序段、或代码的一部分包含一个或多个用于实现规定的逻辑功能的可执行指令。也应当注意，在有些作为替换的实现中，方框中所标注的功能也可以以不同于附图中所标注的顺序发生。例如，两个接连地表示的方框实际上可以基本并行地执行，它们有时也可以按相反的顺序执行，这依所涉及的功能而定。也要注意的是，框图和/或流程图中的每个方框、以及框图和/或流程图中的方框的组合，可以用执行规定的功能或操作的专用的基于硬件的系统来实现，或者可以用专用硬件与计算机指令的组合来实现。
描述于本公开实施例中所涉及到的电路或子电路可以通过软件的方式实现，也可以通过硬件的方式来实现。所描述的电路或子电路也可以设置在处理器中，例如，可以描述为：一种处理器，包括：接收电路和处理电路，该处理模块包括写入子电路和读取子电路。其中，这些电路或子电路的名称在某种情况下并不构成对该电路或子电路本身的限定，例如，接收电路还可以被描述为“接收视频信号”。
可以理解的是，以上实施方式仅仅是为了说明本公开的原理而采用的示例性实施方式，然而本公开并不局限于此。对于本领域内的普通技术人员而言，在不脱离本公开的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本公开的保护范围。

Claims (21)

  1. 一种栅极驱动控制方法，其特征在于，用于控制栅极驱动电路的驱动操作，所述栅极驱动电路用于驱动显示面板，所述显示面板包括沿列方向排布的至少两个显示分区，所述栅极驱动电路包括：与所述显示分区一一对应且彼此独立的至少两个栅极驱动模块，所述栅极驱动电路配置有多个时钟信号端和与所述栅极驱动模块一一对应的至少两个起始控制信号端，各所述栅极驱动模块均与所述多个时钟信号端和对应的所述起始控制信号端相连；所述栅极驱动控制方法，包括：
    获取待显示画面的显示模式信息，所述显示模式信息包括：各所述显示分区的显示模式，所述显示模式包括高清模式或低清模式；
    针对任一所述显示分区，根据所述显示分区的显示模式向所述多个时钟信号端输出与所述显示模式相对应的时钟信号；
    其中，在所述显示分区的显示模式为高清模式时，向所述多个时钟信号端输出与所述高清模式相对应的时钟信号，以控制所述显示分区所对应的栅极驱动模块对所述显示分区内的各行亚像素进行逐行扫描驱动；
    在所述显示分区的显示模式为低清模式时，向所述多个时钟信号端输出与所述低清模式相对应的时钟信号，以控制所述显示分区所对应的栅极驱动模块对所述显示分区内的各行亚像素进行N行同时扫描驱动,N为整数且N≥2。
  2. 根据权利要求1所述的栅极驱动控制方法，其特征在于，所述显示模式信息还包括：各所述显示分区的驱动时长；
    所述栅极驱动控制方法，还包括：
    针对任一所述显示分区，根据所述显示分区的驱动时长和预设的起始控制信号波形参数，向所述显示分区所对应的所述起始控制信号端输出起始控制信号，以控制所述显示分区所对应的栅极驱动模块在所述驱动时长内对所述显示分区内的各行亚像素进行扫描驱动。
  3. 根据权利要求2所述的栅极驱动控制方法，其特征在于，所述起始控制信号波形参数包括：所述起始控制信号的前廊时长、所述起始控制信号处于有效电平状态的持续时长。
  4. 根据权利要求2所述的栅极驱动控制方法，其特征在于，向显示模式为高清模式的所述显示分区所对应的所述起始控制信号端所提供的起始控制信号，为预设的第一起始控制信号；
    向显示模式为低清模式的所述显示分区所对应的所述起始控制信号端所提供的起始控制信号，为预设的第二起始控制信号；
    所述第一起始控制信号处于有效电平状态的持续时长大于或等于所述第二起始控制信号处于有效电平状态的持续时长。
  5. 根据权利要求1所述的栅极驱动控制方法，其特征在于，根据所述显示分区的显示模式向所述多个时钟信号端输出与所述显示模式相对应的时钟信号的步骤，包括：
    根据所述显示分区的显示模式，确定出与所述显示模式相对应的时钟信号波形参数；
    根据所述时钟信号波形参数向所述多个时钟信号端输出相应的时钟信号。
  6. 根据权利要求5所述的栅极驱动控制方法，其特征在于，所述时钟信号波形参数包括：时钟信号的周期时长、时钟信号的周期数量、时钟信号在单个周期内的前廊时长、时钟信号在单个周期内处于有效电平状态的持续时长。
  7. 根据权利要求1所述的栅极驱动控制方法，其特征在于，向所述多个时钟信号端输出的与所述高清模式相对应的时钟信号，为预设的第一时钟信号；
    向所述多个时钟信号端输出的与所述高清模式相对应的时钟信号，为预设的第二时钟信号；
    所述第一时钟信号在单个周期内处于有效电平状态时长小于或等于所述第二时钟信号在单个周期内处于有效电平状态时长。
  8. 一种栅极驱动控制系统，其特征在于，用于控制栅极驱动电路的驱动操作，所述栅极驱动电路用于驱动显示面板，所述显示面板包括沿列方向排布的至少两个显示分区，所述栅极驱动电路包括：与所述显示分区一一对应且彼此独立的至少两个栅极驱动模块，所述栅极驱动电路配置有多个时钟信号端和与所述栅极驱动模块一一对应的至少两个起始控制信号端，各所述栅极驱动模块均与所述多个时钟信号端和对应的所述起始控制信号端相连；所述栅极驱动控制系统，包括：
    第一获取模块，配置为获取待显示画面的显示模式信息，所述显示模式信息包括：各所述显示分区的显示模式，所述显示模式包括高清模式或低清模式；
    第一处理模块，配置为针对任一所述显示分区，根据所述显示分区的显示模式向所述多个时钟信号端输出与所述显示模式相对应的时钟信号；
    其中，在所述显示分区的显示模式为高清模式时，向所述多个时钟信号端输出与所述高清模式相对应的时钟信号，以控制所述显示分区所对应的栅极驱动模块对所述显示分区内的各行亚像素进行逐行扫描驱动；
    在所述显示分区的显示模式为低清模式时，向所述多个时钟信号端输出与所述低清模式相对应的时钟信号，以控制所述显示分区所对应的栅极驱动模块对所述显示分区内的各行亚像素进行N行同时扫描驱动,N为整数且N≥2。
  9. 根据权利要求8所述的栅极驱动控制系统，其特征在于，所述显示模式信息还包括：各所述显示分区的驱动时长；
    所述栅极驱动控制系统还包括：
    第二处理模块，配置为针对任一所述显示分区，根据所述显示分区的驱动时长和预设的起始控制信号波形参数，向所述显示分区所对应的所述起始控制信号端输出起始控制信号，以控制所述显示分区所对应的栅极驱动模块在所述 驱动时长内对所述显示分区内的各行亚像素进行扫描驱动。
  10. 根据权利要求9所述的栅极驱动控制系统，其特征在于，所述起始控制信号波形参数包括：所述起始控制信号的前廊时长、所述起始控制信号处于有效电平状态的持续时长。
  11. 根据权利要求9所述的栅极驱动控制系统，其特征在于，向显示模式为高清模式的所述显示分区所对应的所述起始控制信号端所提供的起始控制信号，为预设的第一起始控制信号；
    向显示模式为低清模式的所述显示分区所对应的所述起始控制信号端所提供的起始控制信号，为预设的第二起始控制信号；
    所述第一起始控制信号处于有效电平状态的持续时长大于或等于所述第二起始控制信号处于有效电平状态的持续时长。
  12. 根据权利要求8所述的栅极驱动控制系统，其特征在于，所述第一处理模块包括：
    第一确定单元，配置为根据所述显示分区的显示模式，确定出与所述显示模式相对应的时钟信号波形参数；
    第一输出单元，配置为根据所述时钟信号波形参数向所述多个时钟信号端输出相应的时钟信号。
  13. 根据权利要求12所述的栅极驱动控制系统，其特征在于，所述时钟信号波形参数包括：时钟信号的周期时长、时钟信号的周期数量、时钟信号在单个周期内的前廊时长、时钟信号在单个周期内处于有效电平状态的持续时长。
  14. 根据权利要求8所述的栅极驱动控制系统，其特征在于，向所述多个 时钟信号端输出的与所述高清模式相对应的时钟信号，为预设的第一时钟信号；
    向所述多个时钟信号端输出的与所述高清模式相对应的时钟信号，为预设的第二时钟信号；
    所述第一时钟信号在单个周期内处于有效电平状态时长小于或等于所述第二时钟信号在单个周期内处于有效电平状态时长。
  15. 一种显示驱动系统，其特征在于，包括：如上述权利要求8至14中任一所述栅极驱动控制系统。
  16. 根据权利要求15所述的显示驱动系统，其特征在于，还包括：
    源极驱动电路，配置为接收待显示画面的显示数据信息，并根据所述显示数据信息内记载的各亚像素的显示数据向各亚像素提供对应的数据电压；
    所述栅极驱动电路，包括至少两个所述栅极驱动模块；
    所述栅极驱动模块，配置为响应于所述起始控制信号端所提供起始控制信号和所述多个时钟信号端所提供的时钟信号的控制，对对应的所述显示分区内的各行亚像素进行扫描驱动。
  17. 根据权利要求16所述的显示驱动系统，其特征在于，所述第一获取模块获取所述显示模式信息的接口与所述源极驱动电路获取所述显示数据信息的接口为同一接口；
    所述显示模式信息位于所述显示数据信息之前被获取。
  18. 一种显示装置，其特征在于，包括：显示面板和如上述权利要求15至17中任一所述显示驱动系统。
  19. 一种电子设备，其包括：
    一个或多个处理器；
    存储器，用于存储一个或多个程序；
    当所述一个或多个程序被所述一个或多个处理器执行，使得所述一个或多个处理器实现如权利要求1至7中任一所述栅极驱动控制方法。
  20. 根据权利要求19所述的电子设备，其中，
    所述处理器包括现场可编程门阵列。
  21. 一种计算机可读介质，其上存储有计算机程序，其中，所述计算机程序在被处理器执行时实现如权利要求1至7中任一所述栅极驱动控制方法中的步骤。
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