WO2023202305A1

WO2023202305A1 - Chip and voltage noise suppression method

Info

Publication number: WO2023202305A1
Application number: PCT/CN2023/082803
Authority: WO
Inventors: 程万娟; 刘宇; 刘臻; 刘凯
Original assignee: 华为技术有限公司
Priority date: 2022-04-18
Filing date: 2023-03-21
Publication date: 2023-10-26
Also published as: CN116954346A

Abstract

Disclosed in the present application are a chip and a voltage noise suppression method, belonging to the technical field of power management. The chip comprises a plurality of processors located in the same power domain, and a power consumption monitoring module and a power consumption regulation module, the power consumption monitoring module being used for acquiring power consumption change information of the plurality of processors, and for transmitting the power consumption change information to the power consumption regulation module, and the power consumption regulation module being used for performing, according to the power consumption change information of the plurality of processors, power consumption suppression on some or all of the plurality of processors. In the present application, for a scenario in which a plurality of processors share a power supply, power consumption suppression is performed by comprehensively considering the power consumption change information of the plurality of processors, thereby achieving more accurate and timely power consumption suppression on the processors, effectively suppressing voltage noise, and reducing performance damage to the processors.

Description

Chip and Voltage Noise Reduction Methods

Cross-references to related applications

This application claims priority to the Chinese patent application filed with the China Patent Office on April 18, 2022, with application number 202210404415. middle.

Technical field

The present application relates to the field of power management technology, and in particular to a chip and a voltage noise suppression method.

Background technique

In computing devices such as notebooks, desktops, smartphones, and autonomous driving controllers, as more and more tasks are processed and the amount of calculations increases, single-core processors cannot meet the task processing needs, so multi-core processors are commonly used. Process tasks in parallel to improve the computing performance and user experience of computing devices.

Multi-core processors can share power. When multiple processors in a multi-core processor process tasks concurrently or multiple heavy-duty tasks run, voltage droop or voltage surges (voltage droop or voltage) of different frequencies will occur due to a sharp increase in power consumption. overshoot), these voltage noises may endanger the circuit functional safety of computing equipment and cause processor performance damage.

Contents of the invention

This application provides a chip and voltage noise suppression method, which can effectively suppress voltage noise and reduce performance damage to the processor.

In a first aspect, embodiments of the present application provide a chip, which includes multiple processors in the same power supply domain, and the multiple processors are powered by the same power supply. The chip also includes a power consumption monitoring module and a power consumption adjustment module, where the power consumption monitoring module refers to a device or module used to monitor the operating status of the processor and generate power consumption change information of the processor based on the operating status of the processor; The power consumption adjustment module refers to a device or module that adjusts the power consumption of the processor. In the embodiment of the present application, the power consumption monitoring module is used to obtain the power consumption change information of multiple processors, and transmit the power consumption change information to the power consumption adjustment module. The power consumption adjustment module is used to adjust the power consumption of the multiple processors according to the power consumption change information. Consumption change information is used to suppress power consumption of some or all processors among multiple processors.

In the scenario where multiple processors share power supply, the embodiment of the present application suppresses power consumption by comprehensively considering the power consumption change information of multiple processors. Compared with suppressing power consumption by a single processor alone, it can be more accurate and more accurate. The power consumption of the processor is suppressed in a timely manner to reduce voltage drops and overshoots that occur when multiple processors process tasks concurrently or when multiple overloaded tasks are running, thereby effectively suppressing voltage noise and reducing performance damage to the processor.

In a possible implementation, the power consumption monitoring module may include a voltage monitoring module set separately for each of the multiple processors; the voltage monitoring module refers to a device or module used to monitor voltage changes of the processor . Among them, the voltage monitoring module of the first processor is used to monitor whether a voltage drop occurs in the first processor, and when the amplitude of the voltage drop exceeds a set amplitude threshold, generate power consumption change monitoring information; the first processor can be one of the above-mentioned any one of the processors. Power consumption change monitoring information is one type of power consumption change information. Power consumption change monitoring information refers to monitoring Information generated by changes in power consumption of the processor. For example, when it is detected that the processor's voltage drop exceeds a set amplitude threshold, or the processor's power consumption change slope reaches a set slope threshold, it indicates that the processor's power consumption has changed, and power consumption change monitoring information is generated. In another possible implementation, the power consumption monitoring module may include a status monitoring module set separately for each of the multiple processors; the status monitoring module refers to a module for monitoring the power consumption change slope of the processor. device or module. The status monitoring module of the first processor is configured to determine the power consumption change slope according to the operating status of the first processor, and generate power consumption change monitoring information when the power consumption change slope reaches the set slope threshold of the first processor. In another possible implementation, the power consumption monitoring module may include a voltage monitoring module and a status monitoring module respectively set for each processor in the plurality of processors.

The voltage monitoring module or status monitoring module of the first processor may be installed inside the first processor, or may be installed outside the first processor. The voltage monitoring module or status monitoring module of the first processor is used to monitor the operating status of the first processor in real time, and can generate power consumption change information of the first processor in a timely manner, thereby notifying the power consumption adjustment module of the first processor in a timely manner. Processor power consumption changes. In addition, the voltage monitoring module and the status monitoring module use different methods to monitor the power consumption changes of the processor, and can generate more comprehensive and timely power consumption change information of the processor based on the different status information of the processor.

In a possible implementation, in addition to a voltage monitoring module or a status monitoring module set separately for each processor, the power consumption monitoring module may also include a power consumption change prediction module set separately for each processor. The power consumption change prediction module refers to a device or module used to predict whether the processor will experience changes in power consumption. Among them, the power consumption change prediction module of the first processor is used to monitor the operating status of the first processor, and predict whether power consumption will occur within the set time window based on the operating status and historical status records of power consumption change events that have occurred. Change events, and generate power consumption change prediction information when it is predicted that a power consumption change event will occur. Power consumption change prediction information is also a type of power consumption change information. Power consumption change prediction information refers to information generated when an impending power consumption change event is predicted based on the operating status of the processor. Among them, the power consumption change event Refers to changes in processor power consumption.

In the above implementation method, by setting the power consumption change prediction module, it can be predicted in advance whether a power consumption change event will occur within a set time window in the future, so that the power consumption change information can be provided to the power consumption adjustment module earlier. It is beneficial for the power consumption adjustment module to determine the power consumption suppression strategy in advance and perform power consumption suppression more effectively.

In a possible implementation, in addition to a voltage monitoring module or a status monitoring module set separately for each processor, the power consumption monitoring module may also include a signal monitoring module set separately for each processor. The signal monitoring module A module refers to a device or module used to monitor signals received by the processor. The signal monitoring module of the first processor is used to monitor whether the first processor receives the set target signal, and when the first processor receives the set target signal, generate target signal indication information. Target signal indication information is also a type of power consumption change information. Target signal indication information refers to information generated when a set target signal is received.

In the above implementation, the signal monitoring module is set up to monitor whether the processor receives the set target signal. The target signal is a pre-signal that may cause drastic changes in power consumption such as package resonance. The target signal is monitored through the signal monitoring module. , can provide power consumption change information to the power consumption adjustment module in advance before the power consumption changes drastically, providing evidence for the suppression timing of high-frequency power consumption change events such as package resonance, which is conducive to the power consumption adjustment module to determine the power consumption suppression strategy in advance, improving Control drop effectiveness for more effective power consumption suppression.

In a possible implementation, the power consumption change monitoring module of the first processor may include a voltage monitoring module, a status monitoring module, a power consumption change prediction module and a signal monitoring module to more comprehensively monitor different status information from multiple aspects. Provide power consumption change information to the power consumption adjustment module.

In a possible implementation, the power consumption adjustment module includes separately setting The suppression module is installed, and the suppression module is used to suppress the power consumption of the processor. Wherein, the suppression module of the first processor is used to receive the power consumption change information of the first processor transmitted by the power consumption change monitoring module of the first processor, and receive the broadcast signal from any processor other than the first processor. The power consumption change information is transmitted in a manner, and the power consumption of the first processor is suppressed based on the received power consumption change information. The suppression module of the first processor may be arranged inside the first processor, or may be arranged outside the first processor.

In the above implementation, the suppression module is distributed for each processor. The suppression module of each processor can learn the power consumption change information of other processors at the same time, thereby providing favorable evidence for determining the timing of power consumption suppression. Each processor The suppression module combines the received power consumption change information of other processors to suppress the power consumption of this processor, thereby realizing multiple processors to coordinate power consumption suppression and improving the voltage of the multi-core processor system in large current jump scenarios. Drop and overshoot control efficiency, suppressing voltage noise more effectively.

In a possible implementation, the power consumption change monitoring module and the suppression module of the first processor are both deployed inside the first processor. Since the communication line is short, the power consumption change monitoring module of the first processor can be updated. Quickly obtain various operating status information of the first processor, and notify the suppression module of the power consumption change information in a more timely manner, which is conducive to the suppression module to suppress the power consumption of the first processor earlier and reduce the risk of power consumption suppression taking effect. Too late and the voltage noise cannot be effectively suppressed.

In a possible implementation, the suppression module of the first processor may be specifically configured to: when receiving the power consumption change information of the first processor, and the power consumption change information of the first processor includes power consumption change monitoring When the information is received, the power consumption of the first processor is suppressed according to the set suppression ratio for the power consumption change monitoring information; when the power consumption change information of the first processor is received, and the power consumption change information of the first processor includes power When the power consumption change prediction information is received, if the power consumption change information sent by at least N processors is received within the set time period, the power consumption of the first processor is performed according to the set suppression ratio for the power consumption change prediction information. Suppression; where N is the set threshold for the number of changing processors; when the power consumption change information of the first processor is received, and the power consumption change information of the first processor includes target signal indication information, if at the set time When the power consumption change information sent by at least M processors is received within the segment, the power consumption of the first processor is suppressed according to the set suppression ratio for the target signal indication information; where M is the set threshold for the number of changing processors. .

In the above implementation, the suppression module can determine the power consumption suppression strategy for the processor according to different situations, and flexibly suppress the power consumption of the processor. For example, when the suppression module of the first processor receives the power consumption change monitoring information of the first processor, it means that the power consumption has changed and power consumption needs to be suppressed immediately. The suppression module immediately follows the instructions for the power consumption change monitoring information. Set a suppression ratio to suppress power consumption of the first processor. When the suppression module of the first processor receives the power consumption change prediction information or the target signal indication information of the first processor, the suppression module can combine the power consumption change information of other processors to determine whether the first processor needs to be Power consumption suppression.

In a possible implementation, the suppression module of the first processor can be specifically configured to: when receiving the power consumption change information of the second processor, if at least K processors are received within a set time period, If the power consumption change information is sent, and the business priority of the first processor is lower than the business priority of the second processor, the power consumption of the first processor is suppressed according to the set cascade suppression ratio; where K is Set the threshold for changing the number of processors; the second processor is any processor except the first processor.

In a possible implementation, the suppression module of the first processor is also configured to: after suppressing the power consumption of the first processor, transmit the information to each processor except the first processor by broadcasting Suppression information; and receiving suppression information transmitted by any processor other than the first processor in a broadcast manner. When the suppression information of the second processor is received, if the service priority of the first processor is lower than the service priority of the second processor, the power consumption of the first processor is performed according to the suppression ratio set for the suppression information. inhibition.

In the above implementation, when multiple processors perform cascade power consumption suppression, the processor with lower business priority is given priority to suppress power consumption, which relatively ensures the normal operation of the processor with higher business priority.

In a possible implementation, the chip may also include a configuration module configured separately for each of the multiple processors; the configuration module of the first processor is configured to based on the received suppression information of any processor. , adjusting the threshold used by the first processor in the process of generating power consumption change information and/or the suppression ratio used in the process of suppressing power consumption.

In the above implementation, when multiple processors perform cascade power consumption suppression, when receiving suppression information from other processors, the threshold used by this processor in the process of generating power consumption change information or when performing power consumption change information is adjusted. The suppression ratio used in the process of power consumption suppression, so that the power consumption suppression process of this processor can better match the current power consumption situation in the power domain.

In a possible implementation, the power consumption adjustment module includes an arbitration module and a suppression execution module in the power domain; the arbitration module is used to receive the power consumption change information of multiple processors sent by the power consumption monitoring module, and adjust the power consumption according to the received Power consumption change information is sent to the suppression execution module to send a power consumption suppression instruction. The power consumption suppression instruction contains the target processor that requires power consumption suppression; the suppression execution module is used to control the target processor based on the power consumption suppression instruction sent by the arbitration module. Perform power consumption suppression.

In the above implementation, by centrally managing the power consumption suppression of each processor, the power consumption suppression actions of each processor can be coordinated based on the power consumption change information of multiple processors, and voltage noise can be suppressed more effectively.

In a possible implementation, the power consumption monitoring module includes a transient current monitoring module set in the power domain; the transient current monitoring module is used to monitor the current in the power domain and generate voltage status indication information according to changes in the current. The power consumption change information includes voltage status indication information generated by the transient current monitoring module.

In the above implementation, the voltage status indication information can be generated according to the transient current changes in the power domain. As a supplement to the power consumption change information of each processor, it can more comprehensively reflect the current power usage in the power domain.

In a second aspect, embodiments of the present application provide a method for suppressing voltage noise. The method includes: obtaining power consumption change information of multiple processors in the same power domain; based on the power consumption change information of multiple processors, Some or all of the processors perform power consumption suppression.

In a possible implementation, the above voltage noise suppression method can be executed by a first processor, which is any one of multiple processors; the first processor can obtain the voltage in the same power domain in the following manner: Power consumption change information of multiple processors: monitor the operating status of the first processor, and generate power consumption change information of the first processor based on the operating status of the first processor; receive the power consumption change information of the second processor sent by the second processor The power consumption change information of the second processor is generated according to the running status of the second processor; the second processor is any processor except the first processor.

In a possible implementation, the power consumption change information of the first processor includes at least one of the following: power consumption change monitoring information generated when a power consumption change event occurs in the first processor; The operating status and historical status records of power consumption change events that have occurred. When it is predicted that a power consumption change event will occur within the set time window, the power consumption change prediction information is generated; it is monitored that the first processor receives the set power consumption change event. When the target signal is generated, the target signal indication information is generated.

In a possible implementation, when the power consumption change monitoring information of the first processor is received, the power consumption of the first processor is suppressed according to the set suppression ratio for the power consumption change monitoring information; when the power consumption change monitoring information is received When receiving the power consumption change prediction information of the first processor, if the power consumption change information sent by at least N processors is received within the set time period, the first processor will be suppressed according to the set suppression ratio for the power consumption change prediction information. The processor performs power consumption suppression; N is the change in settings Processor number threshold; when receiving the target signal indication information of the first processor, if the power consumption change information sent by at least M processors is received within the set time period, the setting for the target signal indication information will be The suppression ratio is used to suppress the power consumption of the first processor; M is the set threshold for the number of changing processors.

In a possible implementation, when the power consumption change information of the second processor is received, if the power consumption change information sent by at least K processors is received within a set time period, and the power consumption change information of the first processor is If the service priority is lower than the service priority of the second processor, the power consumption of the first processor is suppressed according to the set cascade suppression ratio; K is the set threshold for the number of changing processors.

In a possible implementation, after power consumption is suppressed on the first processor, the suppression information may be transmitted to each processor except the first processor in a broadcast manner.

In a possible implementation, when the suppression information of the second processor is received, if the service priority of the first processor is lower than the service priority of the second processor, the suppression information is suppressed according to the setting of the suppression information. Proportional, power consumption suppression for the first processor.

In a possible implementation, the first processor can also adjust the threshold used by the first processor in the power consumption monitoring process and/or perform power consumption suppression based on the received suppression information of any processor. The suppression ratio used in the process.

In a possible implementation, the above voltage noise suppression method is executed by an arbitration module. The arbitration module can receive the power consumption change information of the first processor sent by the first processor; the first processor is one of the plurality of processors. Either; or, the arbitration module can receive the power consumption change information sent by the transient current monitoring module in the power domain; the power consumption change information is the voltage status indication information generated by the transient current monitoring module according to the current change in the power domain.

In a possible implementation, the arbitration module can determine the target processor that needs to suppress power consumption based on the received power consumption change information; and suppress the power consumption of the target processor through the suppression execution module.

In a third aspect, embodiments of the present application provide a computer-readable storage medium. Computer-executable instructions are stored in the computer-readable storage medium. The computer-executable instructions are used to cause a computer to execute any of the methods provided in the second aspect. .

In a fourth aspect, embodiments of the present application provide a computer program product that includes computer-executable instructions. The computer-executable instructions are used to cause a computer to execute any of the methods provided in the second aspect.

The technical effects that can be achieved by any one of the above-mentioned second to fourth aspects can be referred to the description of the beneficial effects in the above-mentioned first aspect, and will not be repeated here.

Description of the drawings

Figure 1 is a schematic diagram of a chip provided by an embodiment of the present application;

Figure 2 is a schematic structural diagram of a processor provided by an embodiment of the present application;

Figure 3 is a schematic structural diagram of a power consumption change monitoring module provided by an embodiment of the present application;

Figure 4 is a flow chart of a power consumption suppression process performed by a suppression module provided by an embodiment of the present application;

Figure 5 is a schematic structural diagram of another processor provided by an embodiment of the present application;

Figure 6 is a schematic structural diagram of another chip provided by an embodiment of the present application;

Figure 7 is a flow chart of an arbitration module performing a power consumption suppression process provided by an embodiment of the present application;

Figure 8 is a schematic structural diagram of another chip provided by an embodiment of the present application;

Figure 9 is a flow chart of a voltage noise suppression method provided by an embodiment of the present application.

Detailed ways

In order to make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the embodiments of the present application will be described in detail below with reference to the accompanying drawings. The terms used in the embodiments of the present application are only used to explain specific embodiments of the present application and are not intended to limit the present application. Obviously, the described embodiments are only some of the embodiments of the present application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of this application.

Before introducing the specific solutions provided by the embodiments of this application, some terms used in this application will be explained to facilitate understanding by those skilled in the art, and will not limit the terms used in this application.

(1) Processor cluster: Multiple processors in the same power domain, or multiple processors powered by the same power supply, can be called a processor cluster.

In the embodiments of this application, "plurality" means two or more. In view of this, "plurality" in the embodiments of this application can also be understood as "at least two". "At least one" can be understood as one or more, for example, one, two or more. For example, including at least one means including one, two or more, and it does not limit which ones are included. For example, if it includes at least one of A, B and C, then it can include A, B, C, A and B, A and C, B and C, or A and B and C. "And/or" describes the relationship between related objects, indicating that there can be three relationships. For example, A and/or B can mean: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/", unless otherwise specified, generally indicates that the related objects are in an "or" relationship.

Unless otherwise stated, ordinal numbers such as "first" and "second" mentioned in the embodiments of this application are used to distinguish multiple objects and are not used to limit the order, timing, priority or importance of multiple objects.

In application scenarios where multi-core processors share the same power supply, when multiple processors process tasks concurrently or multiple overloaded tasks run, power consumption increases sharply, and the power integrity (PI) problem of the multi-core processor will arise. Obviously, the main manifestation is that voltage drops and overshoots of different frequencies often occur, resulting in voltage noise. Voltage noise may endanger the circuit functional safety of computing equipment, cause performance damage to the processor, or affect the minimum operating voltage of the circuit.

Based on this, embodiments of the present application provide a chip that includes multiple processors in the same power domain. That is, the multiple processors are powered by the same power supply. The power supply used to power the multiple processors can be provided on the chip. It can also be set up outside the chip, and multiple processors are connected to the power supply.

For example, the chip can be a system on chip (SoC) or a computing chip used in computing devices, a control logic chip or a forwarding logic chip used in routers, or other chips including multi-core processors. chip. The processor can be a general-purpose processor, such as a microprocessor, a central processing unit (CPU), or other processors, such as an application processor (application processor, AP), modem processor, or tensor Processor (tensor processing unit, TPU) chip, neural network processing unit (NPU), graphics processing unit (GPU), artificial intelligence (artificial intelligence, AI) processor, image signal processing Image signal processor (ISP), controller, video codec, digital signal processor (DSP), baseband processor, etc.

In addition to multiple processors in the same power domain, the chip provided by the embodiment of the present application also includes a power consumption monitoring module and a power consumption adjustment module. The power consumption monitoring module refers to monitoring the operating status of the processor. According to The operating status of the processor is a device or module that generates information about changes in power consumption of the processor; the power consumption adjustment module refers to a device or module that adjusts the power consumption of the processor. In the embodiment of this application, the power consumption monitoring module is used to obtain the power consumption changes of multiple processors. information, and transmits the power consumption change information to the power consumption adjustment module. The power consumption adjustment module is used to suppress power consumption of some or all of the multiple processors based on the power consumption change information of the multiple processors. By combining the power consumption change information of multiple processors in the same power domain, it can be more accurately determined when the processor needs to be power-consumption suppressed and which processor needs to be power-consumption suppressed, so that the power consumption can be determined When the power consumption increases sharply or before the power consumption increases sharply, the power consumption of the processor is suppressed in time to suppress the voltage noise more effectively and reduce the performance damage to the processor.

Figure 1 exemplarily shows a schematic structural diagram of a chip provided by an embodiment of the present application. In some embodiments, as shown in FIG. 1 , the chip 100 includes a processor 0, a processor 1, and a processor N-1, a total of N processors, and the N processors are all powered by the power supply 200. N processors are powered by the same power supply and can be used as a processor cluster. The processor cluster shown in Figure 1 includes more than three processors. In other embodiments, the processor cluster may also include two processors, that is, N is an integer greater than or equal to 2. The power supply 200 shown in FIG. 1 is disposed outside the chip 100 . In other embodiments, the power supply 200 can also be disposed inside the chip 100 . When the power supply 200 is provided inside the chip 100, the power supply 200 may be provided inside the processor cluster or outside the processor cluster. In some embodiments, each processor is equipped with an on-chip low dropout linear regulator (LDO). However, in high-voltage scenarios, it still needs to be connected to the same power supply and powered by the same power supply. These processors are also among multiple processors in the same power domain.

As shown in FIG. 1 , the chip 100 includes a power consumption change monitoring module 110 and a suppression module 120 respectively provided for each of the N processors. The power consumption change monitoring module 110 is used to monitor the operating status of the corresponding processor, and generate the power consumption change information of the corresponding processor according to the operating status of the corresponding processor. That is, the power consumption change monitoring module 110 implements the function of the power consumption monitoring module. The power consumption change monitoring module 110 may be disposed inside the corresponding processor, or may be disposed outside the corresponding processor. When the power consumption change monitoring module 110 can be disposed outside the corresponding processor, the power consumption change monitoring module 110 can be disposed close to the corresponding processor, so that changes in current, power consumption or voltage of the corresponding processor can be sensed in a timely manner. The suppression module 120 is used to receive the power consumption change information of any processor, and based on the received power consumption change information, suppress the power consumption of the processor corresponding to the suppression module 120, that is, the suppression module 120 implements the function of the power consumption adjustment module . The suppression module 120 may be disposed inside the corresponding processor, or may be disposed outside the corresponding processor. The power consumption change monitoring module 110 and the suppression module 120 in Figure 1 are both arranged inside the corresponding processor.

Taking processor 0 as an example for illustration, processor 0 shown in Figure 1 is provided with a power consumption change monitoring module 110 and a suppression module 120. The power consumption change monitoring module 110 of processor 0 is used to monitor the operating status of processor 0, generate power consumption change information of processor 0 according to the operating status of processor 0, and transmit the generated power consumption change information of processor 0 To the suppression module 120 of processor 0. In addition to transmitting the power consumption change information of processor 0 to the suppression module 120 of processor 0, the power consumption change monitoring module 110 of processor 0 can also transmit the power consumption change information to the suppression modules of other processors by broadcasting. The module 120, that is, the suppression module 120 of each processor from processor 1 to processor N-1 can receive the power consumption change information of processor 0 sent by the power consumption change monitoring module 110 of processor 0. The suppression module 120 of the processor 0 is used to receive the power consumption change information of the processor 0 transmitted by the power consumption change monitoring module 110 of the processor 0, and to receive the power consumption change information of the processor 0 transmitted by any processor other than the processor 0 in a broadcast manner. Power consumption change information, and based on the received power consumption change information, performs power consumption suppression on processor 0.

FIG. 2 exemplarily shows a schematic diagram of the internal structure of a processor provided by an embodiment of the present application. As shown in Figure 2, the processor includes a power consumption change monitoring module 110 and a suppression module 120, and also includes multiple functional units for implementing computing functions and control functions, such as an instruction fetch unit 131 (IFU), Instruction dispatch unit 132, prefetch unit 133, branch predictor unit 134, int.execute unit 135, load store unit 136, floating point number and single instruction Multiple data stream (single instruction multiple data, SIMD) unit, also known as floating point and SIMD unit (float & SIMD unit) 137. The processor may also include a cache system 138, and the load storage unit 136 may temporarily store loaded program instructions or data in the cache system 138. Each functional unit and cache system 138 are connected to the power consumption change monitoring module 110, and each functional unit is connected to the suppression module 120. The suppression module 120 can suppress the power consumption of any functional unit. Processors 0 to N-1 in Figure 1 can all adopt the processor structure shown in Figure 2 .

The following uses processor 0 as an example to illustrate the internal structures of the power consumption change monitoring module 110 and the suppression module 120 . The power consumption change monitoring module of the other N-1 processors has the same structure as the power consumption change monitoring module of the processor 0, and the suppression module of the other N-1 processors has the same structure as the suppression module of the processor 0.

In some embodiments, the power consumption change monitoring module 110 of the processor 0 may include an event monitoring module. The event monitoring module is configured to generate power consumption change monitoring information when a power consumption change event is detected in the processor 0, and change the power consumption to The change monitoring information is transmitted to the suppression module 120 of processor 0 and transmitted to the suppression modules 120 of other processors except processor 0 by broadcasting. The event that the power consumption of the processor 0 changes occurs means that the processor 0 has an event that causes a voltage drop or a voltage overshoot. Power consumption change monitoring information is a type of power consumption change information. For example, the event monitoring module can be based on the high-power transition indication event of each functional unit within the processor, for example, whether all the computing units of the scalable vector engine (scalable vector extensions engine, SVE) module are fully occupied, loading and storing The status of the pipeline (load store pipeline), whether there is an abnormal flushing state, etc., or you can also use one or more critical path (critical path) modeling detection circuits to detect whether there is a state that affects the processor.

In one embodiment, the event monitoring module may include a voltage monitoring module, which is used to monitor whether a voltage drop occurs in the processor 0, and generate power consumption change monitoring information when the amplitude of the voltage drop exceeds a set amplitude threshold. In another embodiment, the event monitoring module may include a status monitoring module. The status monitoring module is configured to determine the power consumption change slope according to the operating status of the processor 0, and when the power consumption change slope reaches the set slope threshold of the processor 0 When, the power consumption change monitoring information is generated. In another embodiment, the event monitoring module may include a voltage monitoring module and a status monitoring module.

In other embodiments, in addition to the event monitoring module, the power consumption change monitoring module 110 of the processor 0 may also include a power consumption change prediction module. The power consumption change prediction module is used to monitor the operating status of the processor 0. According to The operating status of processor 0 and the historical status record of power consumption change events that have occurred, predict whether a power consumption change event will occur in processor 0 within the set time window, and when it is predicted that a power consumption change event will occur in processor 0 , generate power consumption change prediction information, transmit the power consumption change prediction information to the suppression module 120 of processor 0, and transmit it to the suppression modules 120 of other processors except processor 0 by broadcasting. Among them, the power consumption change prediction information is a type of power consumption change information.

In other embodiments, in addition to the event monitoring module, the power consumption change monitoring module 110 of the processor 0 may also include a signal monitoring module. The signal monitoring module is used to monitor whether the processor 0 receives the set target signal. And when the processor 0 receives the set target signal, it generates the target signal indication information, transmits the target signal indication information to the suppression module 120 of the processor 0, and transmits it to other devices except the processor 0 by broadcasting. Inhibition module 120 of the processor. Among them, the target signal indication information is a type of power consumption change information.

In other embodiments, in addition to the event monitoring module, the power consumption change monitoring module 110 of the processor 0 may also include a power consumption change prediction module and a signal monitoring module. It should be noted that the various modules included in the power consumption change monitoring module 110 can be selected and used in combination according to actual application scenarios, or only one module can be used to implement similar functions.

For ease of understanding, FIG. 3 exemplarily shows a schematic structural diagram of a power consumption change monitoring module provided by an embodiment of the present application. As shown in FIG. 3 , the power consumption change monitoring module 110 may include a voltage monitoring module 111 , a status monitoring module 112 , a power consumption change prediction module 113 and a signal monitoring module 114 .

The voltage monitoring module 111 may use a critical path monitor (CPM). The voltage monitoring module 111 can use an analog critical path circuit to detect whether a voltage drop occurs in the processor 0. If a voltage drop occurs in the processor 0, and the amplitude of the voltage drop exceeds the set amplitude threshold of the processor 0, a power supply is generated. Consumption change monitoring information.

The status monitoring module 112 can use a current sensor (sensor). The current sensor is used to monitor the current difference per unit time (delta current in delta time, DIDT). The current sensor can use digital logic to determine the power consumption of the processor based on the monitored current difference. Change the slope to generate power consumption change monitoring information.

In some embodiments, the status monitoring module 112 can detect the running status of the processor 0 according to the set DIDT detection cycle, including detecting events or signals of each functional unit of the processor 0, and analyzing the detected events or signals of each functional unit. High-power consumption events or key signals are weighted and averaged, and the power consumption of processor 0 is obtained by fitting. The power consumption change slope is determined based on the power consumption of processor 0 in different time periods, and when the power consumption change slope reaches the set slope threshold of processor 0, power consumption change monitoring information is generated.

In one embodiment, the power consumption change slope may adopt an absolute slope value. The status monitoring module 112 can respectively determine the power consumption of the n-th detection time window _Pn and the power consumption of the n-1th detection time window _Pn-1 according to the set window length, and calculate the power consumption of the detection time window _Pn. The difference between the power consumption of the power consumption detection time window P _n-1 and The set window duration may be based on a clock cycle of the processor. For example, the set window duration may be several or dozens of clock cycles. The detection time window _Pn and the detection time window Pn _-1 are two adjacent detection windows, and the detection time window _Pn is located after the detection time window _Pn-1 . That is to say, the status monitoring module 112 can determine the power consumption change slope according to the power consumption difference between two adjacent detection time windows.

In another embodiment, the power consumption change slope may adopt a moving average slope value. The status monitoring module 112 can respectively determine the power consumption of n adjacent detection time windows according to the set window duration. Calculate the first n-1 detection time windows, that is, the average power consumption from the detection time window P ₁ to the detection time window P _n-1 , and use the power consumption of the detection time window P _n minus the first n-1 The average of the power consumption of the detection time windows is used to obtain the moving average slope value; or, the weighted average of the power consumption of the first n-1 detection time windows is calculated. The weight of the power consumption of each detection time window can be used as follows: The method is determined: the weight of detecting power consumption in time window P _n-1 is 1/2, the weight of detecting power consumption in time window P _n-2 is 1/4, and the weight of detecting power consumption in time window P _n-3 is 1/8, and so on; the moving average slope value is obtained by subtracting the weighted average of the power consumption of the detection time window P _n from the power consumption of the previous n-1 detection time windows. That is to say, the status monitoring module 112 can determine the power consumption change slope according to the power consumption differences of n adjacent detection time windows. Through the above method, the power consumption change slope can be determined more accurately.

In some embodiments, the set slope threshold of processor 0 refers to the set maximum slope threshold, and the power consumption slope threshold of processor 0 may also include a set minimum slope threshold. If the power consumption change slope is greater than or equal to the set the maximum slope threshold, then the status monitoring module 112 sets the event identifier in the register corresponding to the power consumption change monitoring information, and generates the power consumption change monitoring information based on the change of the event identifier from scratch. If the power consumption change slope is less than or equal to the set minimum slope threshold, the status monitoring module 112 may clear the event identifier in the register corresponding to the power consumption change monitoring information.

The voltage monitoring module 111 or the status monitoring module 112 of the processor 0 generates power consumption change monitoring information, indicating that a power consumption change event has occurred in the processor 0 and requires immediate active defense. The suppression module 120 receives the power consumption change monitoring module 110. Power consumption change monitoring information immediately suppresses the power consumption of processor 0.

Since the power consumption change monitoring module 110 is a module responsible for giving an indication signal indicating a drastic change in processor power consumption, the shorter the detection delay of the power consumption change monitoring module 110, the better the power consumption suppression effect. The detection response time of the voltage monitoring module 111 and the status monitoring module 112 is both ns level or even cycle level, which can quickly generate power consumption change monitoring information and transmit it to the suppression module 120 of the processor 0, which is conducive to the suppression module 120 responding in time. , perform power consumption suppression on processor 0. The voltage monitoring module 111 and the status monitoring module 112 can be used jointly or separately in different application scenarios. The power consumption change monitoring information generated by the voltage monitoring module 111 and the status monitoring module 112 is hereinafter referred to as an S1 event, and the S1 event carries an S1 event flag (flag).

In some embodiments, the output ends of the voltage monitoring module 111 and the status monitoring module 112 can be connected to a multiplexer (MUX) 115. The multiplexer 115 can be understood as a connector that includes multiple input ports and an output port. One input port of the multiplexer 115 is connected to the output port of the voltage monitoring module 111 , the other input port is connected to the output port of the status monitoring module 112 , and the output port of the multiplexer 115 is connected to the input port of the suppression module 120 . The multiplexer 115 is used to transmit the S1 event generated by the voltage monitoring module 111 or the status monitoring module 112 to the suppression module 120 . The multiplexer 115 can be installed inside the voltage monitoring module 111 or outside the voltage monitoring module 111 .

The detection delay of the voltage monitoring module 111 and the status monitoring module 112 is very short, which can be only 1cyc, thereby ensuring that when the S1 event generated by it reaches the suppression module of other processors, there is still time to suppress the increase in power consumption, thereby generating suppressed voltage noise. Effect.

The power consumption change prediction module 113 may use a current slope-based predictor (DIDT forcaster; DIDT predictor). The power consumption change prediction module 113 is used to monitor the operating status of processor 0, and predict whether processor 0 will suffer power consumption within the W1 time window based on the operating status of processor 0 and the historical status records of power consumption change events that have occurred. Change events. Among them, the W1 time window refers to the time window starting from the current moment and the duration is the set duration W1. If it is predicted that a power consumption change event will occur in processor 0 within the W1 time window, power consumption change prediction information is generated, and the power consumption change prediction information is transmitted to the suppression module 120 of processor 0 and transmitted to the processor 0 by broadcasting. Suppression module 120 for processors other than processor 0. For example, the set duration W1 can be any duration between 10-50 cyc, or a longer duration.

For example, the power consumption change prediction module 113 can use a prediction algorithm to determine that a power consumption change event will occur in processor 0 within the W1 time window based on the operating status of processor 0 and the historical status records of power consumption change events that have occurred. probability. If the determined probability is greater than or equal to the set probability value, power consumption change prediction information is generated. Among them, the historical status record of the power consumption change event that has occurred may include the pattern of the instruction sequence executed by the processor 0 during the actual power consumption change event and the previous period of time, or the state of the occurrence pattern of the high power consumption event. Statistics records. In some embodiments, when the software of the processor 0 or the cooperative circuit of the SoC gives a hint that a high-power consumption thread may be generated, the power consumption change prediction module 113 may also generate power consumption change prediction information. In other embodiments, due to the speculative prefetch instruction of the processor, a high-power event that flushes the data fetched by the prefetch instruction will be triggered when the prediction fails. Therefore, when the speculative prefetch instruction of processor 0 When the prediction fails, the power consumption change prediction module 113 may also generate power consumption change prediction information.

The operating status of processor 0 detected by the voltage monitoring module 111 or the status monitoring module 112 when the power consumption change event occurs, such as the pattern of the instruction sequence or the occurrence pattern of the high power consumption event, can be added to the historical status record, so that the next time When a similar pattern occurs, the power consumption change prediction module 113 can predict whether a power consumption change event will occur in processor 0 in the next W1 time window based on historical status records.

In some embodiments, the power consumption change prediction module 113 generates power according to a certain pattern in the historical status record. When the power consumption change prediction information is received, the event flag is set in the register corresponding to the power consumption change prediction information. The voltage monitoring module 111 or the status monitoring module 112 detects the power consumption change event caused by the pattern as a refresh instruction to trigger the power consumption change prediction module 113. That is, when the voltage monitoring module 111 or the status monitoring module 112 detects that the power consumption change prediction information corresponds to When a power consumption change event occurs, the power consumption change prediction module 113 is triggered to clear the event identifier in the register corresponding to the power consumption change prediction information; and, at the same time, refresh the prediction probability corresponding to the pattern in the historical status record. For example, the voltage monitoring module 111 or the status monitoring module 112 detects a power consumption change event corresponding to the power consumption change prediction information, indicating that the power consumption change prediction module 113 successfully predicts the pattern, and increases the prediction success rate of the pattern, so it can Improve the prediction probability corresponding to the pattern in the historical state record.

If a power consumption change event has occurred after this pattern in history, but this time, no power consumption change event has actually occurred after this pattern, the prediction success rate of this pattern is reduced at this time, that is, in the power consumption change prediction module 113 Within the preset time period after the power consumption change prediction information is generated, if neither the voltage monitoring module 111 nor the status monitoring module 112 detects the power consumption change event corresponding to the power consumption change prediction information, the power consumption change prediction module 113 clears the power consumption change event. Change the event identifier in the register corresponding to the prediction information, and reduce the prediction probability corresponding to the pattern in the historical status record. If the predicted probability corresponding to a pattern is lower than the set probability value, the power consumption change prediction module 113 may no longer generate power consumption change prediction information based on the pattern to reduce the occurrence of false alarms.

Assume that the current time is T0 time, and the power consumption change prediction module 113 of processor 0 generates power consumption change prediction information, indicating that a power consumption change event will occur on processor 0 within the future W1 time starting from T0 time. Assuming that the delay in broadcasting the power consumption change prediction information to the suppression module 120 of other processors is tn, then the power consumption change prediction information broadcast by processor 0 received by the suppression module 120 of any processor means T0+ Starting from time tn, processor 0 will have a power consumption change event within the time window of W1-tn, that is, processor 0 will experience a rapid performance or power consumption climb. In order to prevent the power consumption suppression of power consumption change events in some specific scenarios from taking effect too late and causing active defense failure, the delay tn needs to be minimized.

The power consumption change prediction information generated by the power consumption change prediction module 113 is hereinafter referred to as an S2 event, and the S2 event carries an S2 event flag.

The signal monitoring module 114 may adopt a system change number flag (SCN Flag) monitor. The signal monitoring module 114 is used to monitor whether the processor 0 receives the set target signal, and when the processor 0 receives the set target signal, generate the target signal indication information, and transmit the target signal indication information to the processor 0 The suppression module 120 is transmitted to the suppression modules 120 of other processors except processor 0 by broadcasting. Among them, the set target signal may include but is not limited to one or more of the following signals: wait for event (WFE) signal, wait for interrupt (WFI) signal, deep flush (deep flush) ) signal, branch flush signal, cache flush signal, high power event indicator signal or high power surge indicator signal, etc. The signal monitoring module 114 can identify special scenarios that may cause power consumption change events in advance based on the above target signal, and notify the suppression module 120 earlier so that the suppression module 120 can perform peak-shift suppression or avoid package resonant frequencies. The signal monitoring module 114 needs to predict the target signal indication information in advance before the power consumption change event, and the earlier the better. For example, the WFI signal can be obtained from the IFU, or it can be obtained earlier from an external wake-up interrupt interface.

When the signal monitoring module 114 detects that the processor 0 receives any kind of target signal, it generates target signal indication information. The target signal indication information generated by the signal monitoring module 114 is hereinafter referred to as an S3 event, and the S3 event carries an S3 event flag.

The above-mentioned S1 event, S2 event and S3 event are all power consumption generated by the power consumption change monitoring module 110 of the processor 0 Change information. In addition to transmitting the generated power consumption change information to the suppression module 120 of processor 0, the power consumption change monitoring module 110 of processor 0 can also transmit the power consumption change information to the suppression modules 120 of other processors by broadcasting. . Compared with the distance between the power consumption change monitoring module 110 of processor 0 and the suppression modules 120 of other processors, the distance between the power consumption change monitoring module 110 of processor 0 and the suppression module 120 of processor 0 is closer. , therefore the suppression module 120 of processor 0 can receive the power consumption change information of processor 0 sent by the power consumption change monitoring module 110 of processor 0 earlier than the suppression modules 120 of other processors.

When the power consumption change monitoring module 110 of processor 0 transmits the power consumption change information of processor 0 to the suppression modules 120 of other processors, it can transmit different types of power consumption change information through a communication signal line, or Different types of power consumption change information can be transmitted through different communication signal lines. For example, S1 events are transmitted through the first communication signal line, S2 events are transmitted through the second communication signal line, and S3 events are transmitted through the third communication signal line. . The delay of the transmission path from processor 0 to other processors should be constrained to a reasonable range, so that each processor can generate power consumption suppression processing actions after receiving the power consumption change information of processor 0 to be able to respond to voltage drops. Produce effects as constraints. In some embodiments, in order to reduce the delay, the power consumption change information can be transmitted through high-level metal traces to ensure that the power consumption change information can reach other processors within a short delay. In other embodiments, the S1 event or S3 event may not be transmitted to other processors through physical communication signal lines, but may be transmitted to other processors through interrupts, message mailboxes, or other non-physical wiring methods.

The above is an introduction to the power consumption change monitoring module 110 of the processor 0. Next, the suppression module 120 of the processor 0 will be introduced. The suppression module 120 of the processor 0 is responsible for controlling the power consumption level of each functional unit within the processor 0 .

The suppression module 120 of the processor 0 can receive the power consumption change information of the processor 0 transmitted by the power consumption change monitoring module 110 of the processor 0, and receive the power consumption change information transmitted by any processor other than the processor 0 in a broadcast manner. Consumption change information is received, and based on the received power consumption change information, power consumption is suppressed for processor 0. Specific ways for the suppression module 120 to suppress the power consumption of the processor may include but are not limited to: adjusting the clock frequency of the processor, such as adjusting the clock frequency from 100 MHz to 70 MHz; using a clock gating method, such as controlling the clock frequency every Run for 8 beats and stop for 2 beats; suppress the pipeline bandwidth of the processor, such as reducing the bandwidth of the internal pipeline of each functional unit in the processor; suppress the peak current; suppress some functional units in the processor, such as powering off some functional units or Shut down, or only suppress functional units that generate high power consumption events; temporarily shut down some functions of the processor, etc. The suppression module 120 may use one or more of the above suppression methods to suppress the power consumption of the processor.

For example, when the suppression module 120 of processor 0 receives the power consumption change information of processor 0, and the power consumption change information includes the S1 event, it means that the power consumption change event has occurred in processor 0 and requires immediate active defense. , the suppression module 120 can suppress the power consumption of the processor 0 according to the set suppression ratio corresponding to the S1 event.

When the suppression module 120 of processor 0 receives the power consumption change information of processor 0, and the power consumption change information includes the S2 event, if the suppression module 120 of processor 0 receives at least N processors within the set time period, If the power consumption change information is sent, the suppression module 120 suppresses the power consumption of processor 0 according to the set suppression ratio corresponding to the S2 event; where N is the set threshold of the number of changed processors corresponding to the S2 event.

When the suppression module 120 of processor 0 receives the power consumption change information of processor 0, and the power consumption change information includes the S3 event, if the suppression module 120 of processor 0 receives at least M processors within the set time period, If the power consumption change information is sent, the suppression module 120 suppresses the power consumption of processor 0 according to the set suppression ratio corresponding to the S3 event; where M is the set threshold of the number of changed processors corresponding to the S2 event.

When the suppression module 120 of processor 0 receives the power consumption change information of another processor, if the suppression module 120 of processor 0 receives power consumption change information sent by at least K processors within the set time period, and Processor 0 industry If the service priority is lower than the service priority of the other processor, the power consumption of processor 0 is suppressed according to the set suppression ratio corresponding to the power consumption change information of other processors; wherein, the other processor can be other than the processor For any processor other than 0, K is the threshold value of the number of processors corresponding to the set power consumption change information of other processors. The values of K and the above-mentioned M and N may be the same or different.

In some embodiments, the mitigation module 120 of processor 0 may include a power consumption event arbitration module and a peak power consumption mitigation (maxpower mitigation, MXPM) module. The power consumption event arbitration module is used to determine whether to suppress the power consumption of processor 0 based on the received power consumption change information of each processor, and when it is determined to suppress the power consumption of processor 0, notify the peak power consumption suppression module Send a suppression command, which includes the suppression ratio and suppression duration. The peak power consumption suppression module can suppress the power consumption of processor 0 within the suppression period according to the suppression ratio in the power consumption suppression instruction.

After the suppression module 120 of processor 0 suppresses the power consumption of processor 0, it transmits the suppression information to each other processor except processor 0 by broadcasting, so that other processors can determine whether they need to cooperate to suppress power consumption. .

The suppression module 120 of processor 0 can also receive suppression information transmitted by any one of the other processors in a broadcast manner. When receiving suppression information from another processor, if the service priority of processor 0 is lower than the service priority of the other processor, the suppression module 120 performs suppression on processor 0 according to the set suppression ratio corresponding to the suppression information. Power consumption suppression, thereby suppressing voltage noise. The suppression information is referred to as an S4 event below, and the S4 event carries an S4 event flag.

As shown in FIG. 1 , the suppression module 120 of the processor 0 includes a suppression information input interface, that is, an S4 input interface 121 , and a suppression information output interface, that is, an S4 output interface 122 . The suppression module 120 of processor 0 can receive S4 events broadcast by other processors through the S4 input interface 121, and broadcast suppression information to other processors through the S4 output interface 122.

When the power consumption change monitoring module 110 includes an event monitoring module, a power consumption change prediction module and a signal monitoring module, the power consumption change information received by the suppression module 120 of the processor 0 may be any of the S1 event, the S2 event or the S3 event. A sort of. At this time, the process of power consumption suppression by the suppression module 120 of processor 0 is shown in Figure 4, which includes the following steps:

S401, event information is received.

The power consumption change information of processor 0 sent by the power consumption change monitoring module 110 of processor 0 received by the suppression module 120 of processor 0, and the power consumption change information and suppression information sent by other processors can be called event information. . The power consumption change information may be any one of the S1 event, S2 event or S3 event, and the suppression information is the S4 event.

The event information sent by any processor can carry the processor's identification information and event flag. For example, the S1 event carries the S1 event flag. The event information sent by the power consumption change monitoring module 110 of the processor 0 may also carry the identification information of the processor 0. The processor can be called a processor core (core), and the identification information of the processor can be represented by C _n , where the value of n is an integer value among 1,...N-1; for example, it will be processed below The S1 event of processor 0 is represented as C ₀ -S1, the S2 event of processor 0 is represented as C ₀ -S2, and the S1 event of processor 1 is represented as C ₁ -S1.

S402, determine whether it is the event information of processor 0; if so, execute step S403; if not, execute step S407;

S403, determine whether it is an S1 event; if yes, execute step S404; if not, execute step S405;

The suppression module 120 may determine which processor sent the event information based on the identification information of the processor carried in the event information. If it is the event information of processor 0, you can determine whether it is an S1 event based on the event flag carried in the event information.

S404: Suppress the power consumption of processor 0 according to the set suppression ratio corresponding to the S1 event.

If C ₀ -S1 is received, that is, the S1 event of the processor itself, it means that the power consumption change event of the processor itself has occurred. If active defense is required immediately, the suppression module 120 can suppress the power consumption of processor 0 within the set suppression period corresponding to the S1 event according to the set suppression ratio corresponding to the S1 event to reduce power supply noise.

S405: Determine whether power consumption change information sent by at least N processors is received; if yes, execute step S406; if not, execute step S410.

Among them, N is the set number. The value of N can be 1, 2, 3 or other integer values.

S406: Suppress the power consumption of processor 0 according to the set suppression ratio corresponding to the S2/S3 event.

If it is not the S1 event of processor 0, it means it is the S2 event or S3 event of processor 0. At this time, if the number of processors sending power consumption change information is greater than or equal to N, the power consumption of processor 0 can be suppressed within the set suppression time according to the set suppression ratio corresponding to the S2/S3 event. For example, assuming that C ₀ -S2 is currently received, the following method can be used to count the number of processors sending power consumption change information: Count how many processors have been received at the current moment and within the set time period before the current moment. Power consumption change information sent by the processor. For example, the statistical result can be: within the current time and 0.05ms before the current time, in addition to receiving the above-mentioned C ₀ -S2 event, C ₁ -S1 was also received, that is, a total of functions sent by 2 processors were received. Consumption change information.

For example, if N is 1, when it is determined that the S2 event or S3 event of processor 0 is received, the set suppression ratio corresponding to the S2/S3 event can be set. The power consumption of processor 0 is suppressed for a certain period of time. If N is 2, when it is determined that the number of processors sending power consumption change information is 2 or more, the suppression ratio corresponding to the S2/S3 event can be set according to the set suppression ratio corresponding to the S2/S3 event. The power consumption of processor 0 is suppressed within the duration; otherwise, if only the C ₀ -S2 or C ₀ -S3 event is received at the current moment and within 0.05ms before the current moment, the power consumption of processor 0 does not need to be suppressed. Suppress and continue to wait for the arrival of the next event information.

In the embodiment shown in Figure 4, the set suppression ratio corresponding to the S2 event and the set suppression ratio corresponding to the S3 event adopt the same set ratio value, and the suppression duration corresponding to the S2 event and the suppression duration corresponding to the S3 event can also be the same. .

In other embodiments, the set suppression ratio corresponding to the S2 event and the set suppression ratio corresponding to the S3 event may be different, and the suppression duration corresponding to the S2 event and the suppression duration corresponding to the S3 event may also be different. After determining that the received event information is the power consumption change information of processor 0, it can be further determined whether it is an S2 event or an S3 event based on the event flag in the event information. If C ₀ -S2 is received, when it is determined that the number of processors sending power consumption change information reaches N, processor 0 can be suppressed according to the set suppression ratio corresponding to the S2 event within the set suppression duration corresponding to the S2 event. Power consumption suppression. If C ₀ -S3 is received, when it is determined that the number of processors sending power consumption change information reaches M, processor 0 can be suppressed according to the set suppression ratio corresponding to the S3 event within the set suppression duration corresponding to the S3 event. Power consumption suppression. Among them, M is also a set quantity, and M and N can be the same or different.

In other embodiments, it can also be set to perform power consumption suppression on the processor only when S1 events of at least N1 processors, S2 events of at least N2 processors, and S3 events of at least N3 processors are received. A step of. Among them, the value of N1 can be 0, 1, 2 or other integer values, the value of N2 can be 0, 1, 2 or other integer values, and the value of N3 can be 0, 1, 2 or other integer values. For example, assuming that N1 has a value of 1, N2 has a value of 2, and N3 has a value of 0, if C ₀ -S2 is received at the current time, only C ₁ -S2 is received within 0.05ms before the current time. event, the power consumption suppression for processor 0 will not be executed and the next event information will continue to wait; if C ₀ -S2 is received at the current time, C ₁ - is received within 0.05ms before the current time. If the power consumption change information of S1 and _C3 -S2 is received, or the power consumption change information of other processors is also received, it can be processed within the set suppression time period corresponding to the S2 event according to the set suppression ratio corresponding to the S2 event. Device 0 performs power consumption suppression.

S407, determine whether power consumption change information sent by at least K processors has been received; if so, execute step S408, If not, execute step S410.

If the event information is sent by other processors, it is determined whether the power consumption change information sent by at least K processors is received. Among them, K is also a set quantity. The value of K can be the same as N, or it can be different.

S408: Determine whether the service priority of processor 0 is lower than the service priority of the processor that sends the power consumption change information; if so, execute step S409; if not, execute step S410.

S409: Suppress the power consumption of processor 0 according to the set cascade suppression ratio.

In the embodiment shown in Figure 4, if the event information is sent by other processors, and it is determined that the number of processors sending power consumption change information is greater than or equal to the current time and the set time period before the current time. K, and when the service priority of processor 0 is low, the power consumption of processor 0 can be suppressed within the set suppression time period corresponding to other processors according to the set suppression ratios corresponding to other processors.

For example, if K is 3, when receiving C ₁ -S1, if it is determined that the number of processors sending power consumption change information is 3 or more, processor 0 and processor 1 can continue to be compared. If the service priority of processor 0 is lower than the service priority of processor 1, processor 0 will be suppressed according to the set suppression ratio corresponding to other processors within the set suppression time period corresponding to other processors. Perform power consumption suppression; otherwise, you may not perform power consumption suppression on processor 0 and continue to wait for the arrival of the next event information. The set suppression ratio corresponding to other processors and the set suppression ratio corresponding to various power consumption change information of the processor itself may be different.

In other embodiments, the power consumption change information and suppression information of other processors can be distinguished and processed differently respectively. For example, after determining that the event information is sent by another processor, it can be determined according to the event flag in the event information whether it is power consumption change information or suppression information. If it is power consumption change information, the number of processors sending power consumption change information is greater than or equal to K, and the business priority of processor 0 is low, the suppression ratio can be set according to the power consumption change information of other processors. Suppress the power consumption of processor 0 within the set suppression time corresponding to the power consumption change information of other processors; if it is suppression information, and the service priority of processor 0 is lower than the service priority of the processor that sends the suppression information level, the power consumption of processor 0 can be suppressed within the set suppression time period corresponding to the suppression information of other processors according to the set suppression ratio corresponding to the suppression information of other processors. For example, if C ₁ -S4 is received and the service priority of processor 0 is lower than the service priority of processor 1, the suppression ratio corresponding to the suppression information of other processors is set to that of the other processors. The power consumption of processor 0 is suppressed within the suppression period corresponding to the suppression information.

In some embodiments, the process of the processor recovering from the power consumption suppression state to the normal operating state can be divided into multiple stages for recovery. For example, if the power consumption is suppressed through the clock frequency, the clock frequency can be increased from the suppression value first. to the middle value, and then increase from the middle value to the normal value to avoid recovering too quickly and increasing the power drop.

S410, wait to receive the next event information.

After executing the step of suppressing the power consumption of processor 0, or based on the above conditions, it is determined that there is no need to suppress the power consumption of processor 0 this time. Wait for the trigger of the next actual information, and then determine whether it is necessary to suppress the power consumption of processor 0 according to the above process. Processor 0 performs power consumption suppression.

In some embodiments, various setting thresholds are used in the above-mentioned process of generating power consumption change information, as well as various setting quantities, setting suppression ratios, and setting durations used by the suppression module when performing power consumption suppression. etc., can be preset and saved in the processor's cache system or corresponding registers.

In other embodiments, the chip 100 may further include a configuration module (Configuration Module, CFG) separately provided for each of the N processors. The configuration module can be set inside the corresponding processor or outside the corresponding processor. Figure 5 shows a schematic structural diagram of a processor with a configuration module inside. As shown in Figure 5, the configuration module 140 is connected to the power consumption change monitoring module 110 and the suppression module 120. The configuration module 140 can be used to save various set thresholds used in the process of generating power consumption change information, and the suppression module Various setting quantities, setting suppression ratios, setting duration, etc. used when performing power consumption suppression. The configuration module 140 can also adjust various setting thresholds used by the corresponding processor in the process of generating power consumption change information and/or the settings used in the process of power consumption suppression based on the received suppression information of any processor. Use various settings to suppress ratios, etc.

Although each functional unit included in the processor is not shown in FIG. 5 , the processor shown in FIG. 5 may include each functional unit shown in FIG. 2 .

The meaning of some setting parameters configured in the configuration module 140 is exemplarily explained below.

CFG.Throttle_signal(S2): Immediately suppress the trigger event, which can be the S1 event of this processor, or the S1/S2 event of this processor, or the S1/S2/S2 event of this processor; for example, if CFG.Throttle_signal is The S1 event of this processor, when the suppression module receives the S1 event of this processor, it will immediately suppress the power consumption of this processor according to the set suppression ratio; if CFG.Throttle_signal(S2) is the S1/S2/ S2 event, when the suppression module receives any power consumption change information of the processor, it will immediately suppress the power consumption of the processor according to the set suppression ratio;

CFG.Detector_time(P2): The set DIDT detection period. The status monitoring module detects the running status of processor 0 according to the DIDT detection period; for example, the set DIDT detection period can be 8cyc or 16cyc, etc.;

CFG.Forcast_time(W1): Predict the duration of the window for future power consumption change events. The power consumption change prediction module predicts whether a power consumption change event will occur within the set window duration; for example, the set window duration can be 8cyc or 16cyc, etc., or it can be 1/4 or 1/2 cycle of the resonant frequency of the processor, etc.;

CFG.Detector_threshold(L1): The maximum slope threshold of the power consumption change slope. When the status monitoring module detects that the power consumption change slope of the processor reaches the set maximum slope threshold, it generates power consumption change monitoring information;

CFG.Detector_threshold(L0): The minimum slope threshold of the power consumption change slope. When the status monitoring module detects that the power consumption change slope of the processor is less than or equal to the set minimum slope threshold, the power consumption change monitoring information is cancelled;

CFG.Throttle_m(R2): used to limit the range of functional units that the suppression module can perform power consumption suppression;

CFG.Throttle_th(L2): The set suppression ratio corresponding to this processor, that is, the S1 event, S2 event and S3 event of this processor correspond to the same set suppression ratio; the suppression module receives the S1 event, In case of S2 event or S3 event, the power consumption of this processor can be suppressed according to the set suppression ratio; for example, the set suppression ratio can be 90%, 80%, 70%, etc.; among them, 90% means that the processor will be The power consumption is reduced to 90% of the current level.

CFG.Throttle_time(T2): The set suppression time, the length of time for the suppression module to suppress the power consumption of this processor; matches the set DIDT detection period; for example, the set suppression time can be 8cyc or 16cyc, etc.;

CFG.Throttle_th(cL2): cascade suppression ratio, that is, the set suppression ratio corresponding to other processors; when the suppression module receives the power consumption change information or suppression information of other processors, it can control this processor according to the set cascade suppression ratio. The processor performs power consumption suppression; for example, the set suppression ratio can be 90%, 80%, 70%...0%; 0% means delaying the instruction fetch and stopping work from the beginning of the instruction fetch unit;

CFG.Throttle_time(cT2): cascade suppression time, that is, the set suppression time corresponding to other processors; when the suppression module receives the power consumption change information or suppression information of other processors, it can The power consumption of this processor is suppressed within the set cascade suppression time; the cascade suppression time matches the set DIDT detection period; for example, the set suppression time can be 8cyc or 16cyc, etc.;

CFG.casade_corenum(C2): The set number used by the suppression module when judging power consumption suppression. That is, when the set number of processors generate event information, the power consumption of this processor will be suppressed; for example, 0 means 1 deal with When the processor generates power consumption change information, the power consumption is suppressed. 1 means that 2 processors generate event information and the power consumption is suppressed. 2 means that 3 processors generate event information and the power consumption is suppressed. 4 means no cascading. As long as this processor When the processor generates event information, it suppresses power consumption;

CFG.casade_Mask(M2): Events that do not participate in the judgment when the suppression module performs suppression judgment; for example, S4 events do not need to participate in the judgment, and the suppression module can exclude the processing of sending S4 events when counting the number of processors that send event information. Device; 1 bit for each event.

In some embodiments, different suppression ratios can be set for different events. For example, the following parameters can also be selectively set in the configuration module:

CFG.Throttle_Casade_th_S1 (L2S1): The set suppression ratio corresponding to the S1 event. When the suppression module receives the S1 event of this processor, it can suppress the power consumption of the processor according to the set suppression ratio corresponding to the S1 event. For example, S1 The set suppression ratio corresponding to the event can be 90%, 80%, 70%...0%;

CFG.Throttle_Casade_time_S1 (T2S1): The set suppression time corresponding to the S1 event. When the suppression module receives the S1 event of the processor, it can suppress the power consumption of the processor within the set suppression time corresponding to the S1 event; with the setting Match the specified DIDT detection period; for example, the set suppression time corresponding to the S1 event can be 8cyc or 16cyc, etc.;

CFG.Throttle_Casade_th_S2 (L2S2): The set suppression ratio corresponding to the S2 event. When the suppression module receives the S2 event of the processor, it can suppress the power consumption of the processor according to the set suppression ratio corresponding to the S2 event. For example, S2 The set suppression ratio corresponding to the event can be 90%, 80%, 70%...0%;

CFG.Throttle_Casade_time_S2 (T2S2): The set suppression time corresponding to the S2 event. When the suppression module receives the S2 event of the processor, it can suppress the power consumption of the processor within the set suppression time corresponding to the S2 event; with the setting Match the specified DIDT detection period; for example, the set suppression time corresponding to the S2 event can be 8cyc or 16cyc, etc.;

CFG.Throttle_Casade_th_S3 (L2S3): The set suppression ratio corresponding to the S3 event. When the suppression module receives the S3 event of this processor, it can suppress the power consumption of the processor according to the set suppression ratio corresponding to the S3 event. For example, S3 The set suppression ratio corresponding to the event can be 90%, 80%, 70%...0%;

CFG.Throttle_Casade_time_S3 (T2S3): The set suppression time corresponding to the S3 event. When the suppression module receives the S3 event of the processor, it can suppress the power consumption of the processor within the set suppression time corresponding to the S3 event; with the setting Match the specified DIDT detection period; for example, the set suppression duration corresponding to the S3 event can be 8cyc or 16cyc, etc.;

CFG.Throttle_Casade_th_S1 (cL2S1): The cascade suppression ratio for S1 events, that is, the set suppression ratio corresponding to the S1 events of other processors; when the suppression module receives S1 events from other processors, it can follow the cascade suppression ratio for S1 events. The suppression ratio suppresses power consumption of this processor; for example, the cascade suppression ratio for S1 events can be 90%, 80%, 70%...0%;

CFG.Throttle_Casade_time_S1 (cT2S1): The cascade suppression duration for S1 events, that is, the cascade suppression duration corresponding to S1 events of other processors; when the suppression module receives S1 events from other processors, it can follow the cascade suppression duration for S1 events. The suppression duration suppresses the power consumption of this processor; for example, the cascade suppression duration for S1 events can be 8cyc or 16cyc, etc.;

CFG.Throttle_Casade_th_S2 (cL2S2): The cascade suppression ratio for S2 events, that is, the set suppression ratio corresponding to the S2 events of other processors; when the suppression module receives S2 events from other processors, it can follow the cascade suppression ratio for S2 events. The suppression ratio performs power consumption suppression on this processor; for example, the cascade suppression ratio for S2 events can It's 90%, 80%, 70%...0%;

CFG.Throttle_Casade_time_S2 (cT2S2): The cascade suppression duration for S2 events, that is, the cascade suppression duration corresponding to S2 events of other processors; when the suppression module receives S2 events from other processors, it can follow the cascade suppression duration for S2 events. The suppression duration suppresses the power consumption of this processor; for example, the cascade suppression duration for S2 events can be 8cyc or 16cyc, etc.;

CFG.Throttle_Casade_th_S3 (cL2S3): The cascade suppression ratio for S3 events, that is, the set suppression ratio corresponding to the S3 events of other processors; when the suppression module receives S3 events from other processors, it can follow the cascade suppression ratio for S3 events. The suppression ratio suppresses the power consumption of this processor; for example, the cascade suppression ratio for S3 events can be 90%, 80%, 70%...0%;

CFG.Throttle_Casade_time_S3 (cT2S3): The cascade suppression duration for S3 events, that is, the cascade suppression duration corresponding to S3 events from other processors; when the suppression module receives S3 events from other processors, it can follow the cascade suppression duration for S3 events. The suppression duration suppresses the power consumption of this processor; for example, the cascade suppression duration for S3 events can be 8cyc or 16cyc, etc.;

CFG.Throttle_Casade_th_S4 (cL2S4): The cascade suppression ratio for S4 events, that is, the set suppression ratio corresponding to the S4 events of other processors; when the suppression module receives S4 events from other processors, it can follow the cascade suppression ratio for S4 events. The suppression ratio suppresses the power consumption of this processor; for example, the cascade suppression ratio for S4 events can be 90%, 80%, 70%...0%;

CFG.Throttle_Casade_time_S4 (cT2S4): The cascade suppression duration for S4 events, that is, the cascade suppression duration corresponding to S4 events from other processors; when the suppression module receives S4 events from other processors, it can follow the cascade suppression duration for S4 events. The suppression duration suppresses the power consumption of this processor; for example, the cascade suppression duration for S4 events can be 8cyc or 16cyc, etc.;

CFG.Throttle_Casade_cfg_en(cEn): Enable the optional event cascade suppression configuration. If enabled, the cascade suppression ratio of the event will be automatically passed to cL2/cT2 according to the cascade event scenario and provided to the suppression module;

CFG.Throttle_Casade_priority(cPrn): The business priority of this processor; when one of the two processors needs to be suppressed and the other can run normally, the processor with the lower business priority suppresses power consumption;

CFG.Throttle_Casade_release(cTrn): When this processor returns from the inhibited state to the normal state, several stages of recovery need to be added. The default is 0, which is restored directly. 1 is to add a stage of recovery (it can be understood that there is a step in the middle of the current recovery to the peak value.) 2, 3 and so on, can avoid recovery too fast and increase the voltage drop.

The configuration module 140 is also responsible for adjusting various set thresholds used by the processor in the process of generating power consumption change information, and various set suppression ratios used in the process of power consumption suppression. For example, the configuration module 140 can adjust various setting thresholds used by the corresponding processor in the process of generating the power consumption change information according to the received suppression information of any processor; or, the configuration module 140 can adjust the various setting thresholds used by the corresponding processor according to the received suppression information. The suppression information of any processor received, the various set suppression ratios and the set suppression duration used in the process of power consumption suppression; alternatively, the configuration module 140 can based on the suppression information of any processor received. , adjust various set thresholds used by the corresponding processor in the process of generating power consumption change information and various set suppression ratios and set suppression durations used in the process of power consumption suppression.

For example, the suppression module 120 of processor 0 receives the S4 event of processor 2 and may transmit the S4 event of processor 2 to the configuration module 140 of processor 0. The configuration module 140 of processor 0 receives the S4 event of processor 2, indicating that processor 2 is currently in a power consumption suppression state, and can be associated with the modified power consumption change monitoring module 110 of processor 0 to detect the generation threshold of the S1 event. The processor The power consumption change monitoring module 110 of 0 performs monitoring according to the modified threshold. When no power consumption suppression action occurs on any processor, the S1 event generation threshold of the power consumption change monitoring module 110 is restored to the configured default value. The threshold can be adjusted by software or in conjunction with a hardware business classification processor.

In the chip provided by the embodiment of the present application, each processor can transmit power consumption change information to each other and cooperate to suppress power consumption. It can suppress the power consumption of the processor more accurately and timely, suppress voltage noise more effectively, and reduce Performance damage to the processor.

In some embodiments, as shown in FIG. 6 , the chip provided by the embodiment of the present application may also include an arbitration module 150 and a suppression execution module 160 provided in the power domain. Both the arbitration module 150 and the suppression execution module 160 belong to the power consumption adjustment module. Among them, the arbitration module 150 can also be called a power integrity arbitration (PI arbiter) module, which is used to receive power consumption change information of multiple processors. The power consumption change information of the processor can be the power consumption change monitoring of each processor. Module 110 sends it to the arbitration module. The arbitration module 150 can determine which processor or processors need to perform power consumption suppression based on the received power consumption change information, and send a power consumption suppression instruction to the suppression execution module 160. The power consumption suppression instruction includes the target that needs to be power consumption suppressed. processor. When the arbitration module 150 determines that power consumption of some processors needs to be suppressed, the arbitration module 150 may also first suppress the power consumption of processors with lower business priorities.

The suppression execution module 160 is configured to suppress power consumption of the target processor according to the power consumption suppression instruction sent by the arbitration module 150 . The suppression execution module 160 can also be called a fast frequency scaling (FFS) module, which can perform frequency reduction processing through a fast frequency scaling response. The suppression execution module 160 can reduce the frequency of all processors at the same time, or can only reduce the frequency of the processors. Part of the processors specified by the frequency, that is, the target processors determined by the arbitration module 150 that require power consumption suppression.

In some embodiments, the chip provided by the embodiment of the present application may also include a transient current monitor (transient current monitor, TCM) module 170 provided in the power domain. The transient current monitoring module 170 belongs to the power consumption monitoring module and is used to monitor the current in the power domain and generate voltage status indication information according to changes in the current. For example, the transient current monitoring module 170 detects that the real-time current in the power domain reaches or approaches At peak current, voltage status indication information can be generated. The transient current monitoring module 170 sends the voltage status indication information to the arbitration module 150, so that the arbitration module 150 determines the power consumption suppression strategy according to the voltage status indication information, and sends the power consumption suppression strategy to the suppression execution module 160 according to the determined power consumption suppression strategy. Suppress commands.

For example, in one embodiment, the arbitration module may determine the power consumption suppression strategy only based on the voltage status indication information sent by the transient current monitoring module 170; in another embodiment, the arbitration module may only determine the power consumption suppression strategy based on the voltage status indication information sent by each processor. The power consumption change information sent determines the power consumption suppression strategy; in another embodiment, the arbitration module can determine the power consumption suppression based on the power consumption change information sent by each processor and the voltage status indication information sent by the transient current monitoring module 170 Strategy.

Figure 7 exemplarily shows a flow chart of a process of power consumption suppression by an arbitration module. As shown in Figure 7, the process may include the following steps:

S701, receiving a trigger event.

The trigger event received by the arbitration module may be the power consumption change information sent by the power consumption change monitoring module of a certain processor, such as the above-mentioned S1 event, S2 event or S3 event; it may also be the voltage status sent by the transient current monitoring module Instructions.

S702, determine whether the trigger event is voltage status indication information; if yes, execute step S703; if not, execute step S704.

The arbitration module can determine whether the received trigger event is the voltage status indication information sent by the transient current monitoring module according to the event flag carried in the received trigger event, or according to the interface through which the trigger event is received.

S703: Generate a power consumption suppression instruction according to the power consumption suppression strategy for the voltage status indication information.

If the voltage status indication information sent by the transient current monitoring module is received, the arbitration module can generate a power consumption suppression instruction based on the set suppression ratio and set suppression time for the voltage status indication information to suppress power consumption of all processors; Alternatively, the arbitration module can generate a power consumption suppression instruction based on the set suppression ratio and set suppression duration for the voltage status indication information, as well as the business priority of each processor, to suppress power consumption of some processors.

In some embodiments, the arbitration module can also adjust the threshold used by each processor in the process of generating power consumption change information or the set suppression ratio and setting used in the power consumption suppression process based on the received voltage status indication information. Inhibition duration.

S704: Generate a power consumption suppression instruction according to the power consumption suppression strategy based on the power consumption change information.

If the received trigger event is not the voltage status indication information, but the power consumption change information sent by a certain processor, assuming it is the power consumption change information sent by processor 1, the arbitration module can set the suppression ratio based on the power consumption change information. and set the suppression duration, generate a power consumption suppression instruction, and perform power consumption suppression on processor 1; or, the arbitration module can set the suppression ratio and set the suppression duration based on the power consumption change information, generate a power consumption suppression instruction, and perform power consumption suppression on the business Processors with a lower priority than processor 1 perform power consumption suppression; alternatively, the arbitration module can set the suppression ratio and suppression duration based on the power consumption change information, generate a power consumption suppression instruction, and suppress processor 1 and business priority. Processors below processor 1 perform power suppression.

In some embodiments, when the arbitration module receives the power consumption change information sent by processor 1, it can refer to the logic of the suppression module to perform power consumption suppression judgment, and first determine whether the number of processors sending power consumption change information reaches the set number. , if the set number is reached, the suppression ratio and suppression duration set for the power consumption change information can be set, and the business priority of each processor that sends the power consumption change information can be determined to determine which processors should perform power consumption suppression. And generate a power consumption suppression instruction to suppress the power consumption of the determined target processor.

In some embodiments, the arbitration module can also adjust the threshold used by each processor in the process of generating the power consumption change information or the set suppression ratio used in the power consumption suppression process based on the received power consumption change information of the processor. and set the suppression duration.

S705: Send a power consumption suppression instruction to the suppression execution module.

The arbitration module sends the generated power consumption suppression instruction to the suppression execution module, and the suppression execution module uses frequency reduction and other methods to suppress the power consumption of the corresponding processor according to the power consumption suppression instruction.

After the arbitration module sends the power consumption suppression instruction to the suppression execution module, it can wait for the arrival of the next trigger event.

In some embodiments, when the arbitration module receives power consumption change information sent by a certain processor, it can determine whether the power consumption change information is high-frequency event information, that is, power consumption change information caused by ns-level power consumption change events; If it is high-frequency event information, ns-level power consumption can be suppressed immediately according to the power consumption suppression strategy for ns-level power consumption change events. If it is not high-frequency event information, such as power consumption change information caused by us-level power consumption change events, us-level power consumption suppression can be performed according to the power consumption suppression strategy for us-level power consumption change events.

In the above embodiment, the power consumption change information obtained by the high sampling rate power consumption change monitoring module inside the processor core, and the voltage status indication information obtained by the low sampling rate transient current monitoring module for the same power domain are centralized. The managed arbitration module performs frequency reduction strategy control, and then performs frequency reduction control and frequency recovery control for the corresponding processor core through the suppression execution module, which can supplement the suppression efficiency and suppression amplitude of the suppression module of each processor. For example, if the Significant power consumption suppression, while also providing optimal energy efficiency options in multiple scenarios.

In some embodiments, there may not be a separate suppression module for each processor in the chip. As shown in FIG. 8 , the chip 100 may include a power consumption change monitoring module 110 set for each processor in the N processors, an arbitration module 150 and a suppression execution module 160 set in the power domain, and may also include a transient current Monitoring module 170. achievement The consumption change monitoring module 110 is used to monitor the operating status of the corresponding processor, generate power consumption change information of the corresponding processor according to the operating status of the corresponding processor, and transmit the power consumption change information to the arbitration module 150 . The transient current monitoring module 170 is used to monitor the current in the power domain and generate voltage status indication information according to changes in the current. The transient current monitoring module 170 sends the voltage status indication information to the arbitration module 150 . The arbitration module 150 can determine the power consumption suppression strategy based on the power consumption change information of each processor and the voltage status indication information transmitted by the transient current monitoring module 170, and send the power consumption suppression strategy to the suppression execution module 160 according to the determined power consumption suppression strategy. Suppression instructions. The power consumption suppression instructions include the target processor that needs to be suppressed in power consumption, as well as the suppression ratio and suppression duration. The suppression execution module 160 suppresses the power consumption of the target processor within the suppression duration according to the suppression ratio in the power consumption suppression instruction.

In the above embodiment, the power consumption suppression for the target processor is not controlled within the core. Instead, the suppression execution module 160 outside the processor controls the voltage or frequency of the target processor. External frequency reduction and voltage reduction can suppress the processor current better than in-core control that reduces performance by the same proportion.

In other embodiments, the transient current monitoring module may not be included in the chip. The arbitration module 150 may determine a power consumption suppression strategy based on the power consumption change information transmitted by the power consumption change monitoring module 110 of each processor, and send a power consumption suppression instruction to the suppression execution module 160 based on the determined power consumption suppression strategy.

In other embodiments, the chip may not include a power consumption change monitoring module set separately for each processor. The arbitration module 150 may determine a power consumption suppression strategy based on the voltage status indication information transmitted by the transient current monitoring module 170 , and send a power consumption suppression instruction to the suppression execution module 160 based on the determined power consumption suppression strategy.

Based on the same inventive concept as the above embodiments, embodiments of the present application also provide a voltage noise suppression method, which is executed by the chip in the above embodiments. As shown in Figure 9, the method may include the following steps:

S901: Obtain power consumption change information of multiple processors in the same power domain;

S902: According to the power consumption change information of the multiple processors, perform power consumption suppression on some or all of the multiple processors.

In some embodiments, the above voltage noise suppression method can be executed by any processor among multiple processors in the same power domain. The following description takes processor 0 as an example.

Processor 0 can obtain the power consumption change information of multiple processors in the same power domain in the following manner: monitor the operating status of processor 0, and generate the power consumption change information of processor 0 based on the operating status of processor 0; receive The power consumption change information of the second processor is sent by the second processor; the power consumption change information of the second processor is generated based on the operating status of the second processor; the second processor is any processor other than processor 0. a processor.

Among them, the power consumption change information of processor 0 includes at least one of the following: power consumption change monitoring information generated when a power consumption change event occurs in processor 0; based on the operating status of processor 0 and the power consumption change event that has occurred Historical status records, when it is predicted that a power consumption change event will occur within the set time window, the power consumption change prediction information is generated; when it is monitored that processor 0 receives the set target signal, the target signal indication information is generated.

The power consumption change information of processor 0 may be generated by the power consumption change monitoring module of processor 0 and transmitted to the suppression module of processor 0. The suppression module of processor 0 may receive the power consumption change information of processor 0 sent by the power consumption change monitoring module of processor 0, and receive the power consumption change information of the second processor sent by the second processor.

The processor 0 can suppress the power consumption of the processor 0 based on the power consumption change information of multiple processors. For example, when the power consumption change monitoring information of processor 0 is obtained, the power consumption of processor 0 is suppressed according to the set suppression ratio for the power consumption change monitoring information; when the power consumption change of processor 0 is obtained When predicting information, if the power consumption change information sent by at least N processors is received within the set time period, the power consumption of processor 0 will be suppressed according to the set suppression ratio for the power consumption change prediction information; N is The set threshold for changing the number of processors; when the target of processor 0 is obtained When targeting signal indication information, if the power consumption change information sent by at least M processors is received within the set time period, the power consumption of processor 0 will be suppressed according to the set suppression ratio for the target signal indication information; M Set the threshold for changing the number of processors.

When receiving the power consumption change information of the second processor, if the power consumption change information sent by at least K processors is received within the set time period, and the business priority of processor 0 is lower than that of the second processor, According to the business priority, the power consumption of processor 0 is suppressed according to the set cascade suppression ratio; K is the set threshold for the number of changing processors.

After power consumption suppression is performed on processor 0, the suppression information can be transmitted to each processor except processor 0 by broadcasting. When the suppression information of the second processor is received, if the service priority of processor 0 is lower than the service priority of the second processor, the power consumption of processor 0 is suppressed according to the suppression ratio set for the suppression information. .

Optionally, processor 0 can also adjust the threshold used by processor 0 in the process of power consumption monitoring and/or the suppression used in the process of power consumption suppression based on the received suppression information of any processor. Proportion.

In other embodiments, the above voltage noise suppression method can be executed by the arbitration module in the above embodiment, and the arbitration module can receive the power consumption change information of the first processor sent by the first processor; the first processor is multiple Any one of the processors; alternatively, the arbitration module can receive the power consumption change information sent by the transient current monitoring module in the power domain; the power consumption change information is the voltage status indication information generated by the transient current monitoring module according to the current changes in the power domain. .

The arbitration module can determine the target processor that needs to suppress power consumption based on the received power consumption change information; it can suppress the power consumption of the target processor through the suppression execution module.

The method steps in the embodiments of the present application can be implemented by hardware, or by a processor executing computer programs or instructions. A computer program or instructions may constitute a computer program product. An embodiment of the present application also provides a computer program product including computer-executable instructions. In some embodiments, the computer-executable instructions are used to cause the computer to perform functions in the method embodiments shown in FIG. 4, FIG. 7, or FIG. 9.

Computer-executable instructions may be stored in a computer-readable storage medium. Embodiments of the present application further provide a computer-readable storage medium in which executable instructions are stored. In some embodiments, the computer-executable instructions are used to cause the computer to perform functions in the method embodiments shown in FIG. 4, FIG. 7, or FIG. 9.

The computer-readable storage medium provided by the embodiment of the present application can be random access memory (random access memory, RAM), flash memory, read-only memory (read-only memory, ROM), programmable read-only memory (programmableROM, PROM), Erasable programmable read-only memory (erasable PROM, EPROM), electrically erasable programmable read-only memory (electrically ePROM, EEPROM), register, hard disk, removable hard disk, CD-ROM or any other form known in the art Computer-readable storage media.

Computer-executable instructions may be stored in or transmitted from one computer-readable storage medium to another, for example, the computer program or instructions may be transmitted from a website, computer, server, or A data center transmits data via wired or wireless means to another website site, computer, server, or data center. The computer-readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server or data center that integrates one or more available media. The available media may be magnetic media, such as floppy disks, hard disks, and magnetic tapes; they may also be optical media, such as digital video discs (DVDs); they may also be semiconductor media, such as solid-state hard drives.

In the various embodiments of this application, if there is no special explanation or logical conflict, the terms and/or descriptions between different embodiments are consistent and can be referenced to each other. The technical features in different embodiments are based on their inherent Logical relationships can be combined to form new embodiments. Furthermore, the terms "including" and "having" and any variations thereof are intended to cover a non-exclusive inclusion, for example, the inclusion of a series of steps or units. Methods, systems, products or devices need not be limited to Instead of those steps or elements expressly listed, other steps or elements not expressly listed or inherent to the process, method, product or apparatus may be included.

Although the present application has been described in conjunction with specific features and embodiments thereof, it will be apparent that various modifications and combinations may be made without departing from the spirit and scope of the application. Accordingly, the specification and drawings are merely illustrative of the scheme defined by the appended claims and are deemed to cover any and all modifications, variations, combinations or equivalents within the scope of this application.

Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the scope of the present application. In this way, if these modifications and variations of the embodiments of the present application fall within the scope of the claims of this application and equivalent technologies, then this application is also intended to include these modifications and variations.

Claims

A chip, characterized in that it includes multiple processors in the same power domain, a power consumption monitoring module and a power consumption adjustment module;

The power consumption monitoring module is used to obtain the power consumption change information of the multiple processors, and transmit the power consumption change information to the power consumption adjustment module;

The power consumption adjustment module is configured to suppress power consumption of some or all of the plurality of processors based on the power consumption change information of the plurality of processors.
The chip according to claim 1, wherein the power consumption change information includes power consumption change monitoring information; the power consumption monitoring module includes a voltage set separately for each processor in the plurality of processors. Monitoring module and/or condition monitoring module;

The voltage monitoring module of the first processor is used to monitor whether a voltage drop occurs in the first processor, and when the amplitude of the voltage drop exceeds a set amplitude threshold, generate the power consumption change monitoring information; the first processor be any one of the plurality of processors;

The status monitoring module of the first processor is configured to determine the power consumption change slope according to the operating status of the first processor, and generate the power consumption change slope when the power consumption change slope reaches the set slope threshold of the first processor. Consumption change monitoring information.
The chip according to claim 2, wherein the power consumption change information also includes power consumption change prediction information; the power consumption monitoring module further includes setting settings for each processor in the plurality of processors. Power consumption change prediction module;

The power consumption change prediction module of the first processor is used to monitor the operating status of the first processor, and predict whether the power consumption change event will occur within the set time window based on the operating status and the historical status record of the power consumption change event that has occurred. A power consumption change event will occur, and when it is predicted that a power consumption change event will occur, the power consumption change prediction information is generated.
The chip according to claim 2 or 3, characterized in that the power consumption change information also includes target signal indication information; the power consumption monitoring module further includes: Set signal monitoring module;

The signal monitoring module of the first processor is used to monitor whether the first processor receives the set target signal, and when the first processor receives the set target signal, generate the target signal Instructions.
The chip according to any one of claims 2 to 4, wherein the power consumption adjustment module includes a suppression module respectively provided for each processor in the plurality of processors;

The suppression module of the first processor is configured to receive the power consumption change information of the first processor transmitted by the power consumption change monitoring module of the first processor, and receive the power consumption change information of the first processor other than the first processor. Any processor transmits power consumption change information through broadcasting, and based on the received power consumption change information, performs power consumption suppression on the first processor.
The chip according to claim 5, characterized in that the suppression module of the first processor is specifically used for:

When the power consumption change information of the first processor is received, and the power consumption change information of the first processor includes power When the power consumption change monitoring information is received, the power consumption of the first processor is suppressed according to the set suppression ratio for the power consumption change monitoring information.
The chip according to claim 5 or 6, characterized in that the suppression module of the first processor is specifically used for:

When the power consumption change information of the first processor is received, and the power consumption change information of the first processor includes power consumption change prediction information, if at least N processors are received within the set time period, power consumption change information, then suppress the power consumption of the first processor according to the set suppression ratio for the power consumption change prediction information; the N is the set threshold of the number of changing processors; or,

When the power consumption change information of the first processor is received, and the power consumption change information of the first processor includes target signal indication information, if the power consumption change information sent by at least M processors is received within the set time period, If the power consumption change information is received, the power consumption of the first processor is suppressed according to the set suppression ratio for the target signal indication information; the M is the set threshold for the number of changing processors.
The chip according to any one of claims 5 to 7, characterized in that the suppression module of the first processor is specifically used for:

When receiving the power consumption change information of the second processor, if the power consumption change information sent by at least K processors is received within the set time period, and the service priority of the first processor is lower than the According to the service priority of the second processor, the power consumption of the first processor is suppressed according to the set cascade suppression ratio; the K is the set threshold for the number of changing processors; the second processor is Any processor other than the first processor.
The chip according to any one of claims 5 to 8, characterized in that the suppression module of the first processor is also used for:

After suppressing the power consumption of the first processor, transmit the suppression information to each processor except the first processor by broadcast;

The suppression module of the first processor is also configured to receive suppression information transmitted by any processor other than the first processor in a broadcast manner.
The chip according to claim 9, characterized in that the suppression module of the first processor is also used for:

When the suppression information of the second processor is received, if the service priority of the first processor is lower than the service priority of the second processor, the suppression ratio of the first processor is set according to the suppression ratio set for the suppression information. A processor performs power consumption suppression.
The chip according to any one of claims 5 to 10, characterized in that the chip further includes a configuration module respectively provided for each processor in the plurality of processors;

The configuration module of the first processor is configured to adjust the threshold used by the first processor in the process of generating power consumption change information and/or in the process of power consumption according to the received suppression information of any processor. The suppression ratio used in the suppression process.
The chip according to any one of claims 1 to 11, wherein the power consumption adjustment module includes an arbitration module and a suppression execution module in the power domain;

The arbitration module is configured to receive the power consumption change information of multiple processors sent by the power consumption monitoring module, and send a power consumption suppression instruction to the suppression execution module according to the received power consumption change information. The power consumption suppression instruction contains the target processor that needs to be power consumption suppressed;

The suppression execution module is configured to suppress power consumption of the target processor according to the power consumption suppression instruction sent by the arbitration module.
The chip according to any one of claims 1 to 12, wherein the power consumption monitoring module includes a transient current monitoring module in the power domain;

The transient current monitoring module is used to monitor the current in the power domain and generate the power consumption change information according to changes in the current.
A voltage noise suppression method, characterized by including:

Obtain power consumption change information of multiple processors in the same power domain;

According to the power consumption change information of the plurality of processors, power consumption is suppressed for some or all of the plurality of processors.
The method according to claim 14, characterized in that the method is executed by a first processor, and the first processor is any one of the plurality of processors; and the obtaining of multiple processors in the same power domain Power consumption change information of each processor, including:

Monitor the operating status of the first processor, and generate power consumption change information of the first processor according to the operating status of the first processor; the power consumption change information of the first processor includes: monitoring the When a power consumption change event occurs on the first processor, the power consumption change monitoring information is generated;

Receive the power consumption change information of the second processor sent by the second processor; the power consumption change information of the second processor is generated according to the operating status of the second processor; the second processor be any processor except the first processor.
The method according to claim 15, characterized in that the power consumption change information of the first processor further includes at least one of the following:

Generate power consumption change prediction information when it is predicted that a power consumption change event will occur within a set time window based on the operating status of the first processor and historical status records of power consumption change events that have occurred;

Target signal indication information is generated when it is detected that the first processor receives the set target signal.
The method according to claim 16, wherein the step of suppressing power consumption of some or all of the plurality of processors according to the power consumption change information of the plurality of processors includes:

If the power consumption change monitoring information of the first processor is obtained, the power consumption of the first processor is suppressed according to the set suppression ratio for the power consumption change monitoring information; or,

If the power consumption change prediction information of the first processor is obtained, and the power consumption change information sent by at least N processors is obtained within the set time period, the suppression ratio set for the power consumption change prediction information will be , perform power consumption suppression on the first processor; the N is the set threshold for the number of changing processors; or,

If the target signal indication information of the first processor is obtained, and at least M locations are obtained within a set time period, If the power consumption change information sent by the processor is received, then the power consumption of the first processor is suppressed according to the set suppression ratio for the target signal indication information; the M is the set threshold of the number of changing processors.
The method according to claim 15 or 16, characterized in that, according to the power consumption change information of the plurality of processors, performing power consumption suppression on some or all of the plurality of processors includes: :

When receiving the power consumption change information of the second processor, if the power consumption change information sent by at least K processors is received within the set time period, and the service priority of the first processor is lower than the According to the service priority of the second processor, the power consumption of the first processor is suppressed according to the set cascade suppression ratio; the K is the set threshold for the number of changing processors.
The method according to claim 17 or 18, characterized in that after suppressing power consumption of the first processor, the method further includes:

The suppression information is transmitted to each processor except the first processor in a broadcast manner.
The method of claim 19, further comprising:

When the suppression information of the second processor is received, if the service priority of the first processor is lower than the service priority of the second processor, the suppression ratio set for the suppression information is suppressed. The first processor performs power consumption suppression.
The method according to claim 19 or 20, characterized in that the method further includes:

According to the received suppression information of any processor, the threshold value used by the first processor in the process of power consumption monitoring and/or the suppression ratio used in the process of performing power consumption suppression is adjusted.
The method according to claim 14, characterized in that the method is executed by an arbitration module, and obtaining the power consumption change information of multiple processors in the same power domain includes:

Receive the power consumption change information of the first processor sent by the first processor; the first processor is any one of the plurality of processors; or,

Receive power consumption change information sent by the transient current monitoring module in the power domain; the power consumption change information is generated by the transient current monitoring module according to the current change in the power domain.
The method according to claim 22, wherein the step of suppressing power consumption of some or all of the plurality of processors according to the power consumption change information of the plurality of processors includes:

According to the received power consumption change information, determine the target processor that needs to perform power consumption suppression;

Suppress the power consumption of the target processor by suppressing the execution module.
A computer-readable storage medium, characterized in that computer-executable instructions are stored therein, and the computer-executable instructions are used to cause a computer to execute the method according to any one of claims 14 to 23.
A computer program product, characterized in that it contains computer-executable instructions, and the computer-executable instructions are used to cause a computer to execute the method according to any one of claims 14 to 23.