CN116954346A

CN116954346A - Chip and voltage noise suppression method

Info

Publication number: CN116954346A
Application number: CN202210404415.XA
Authority: CN
Inventors: 程万娟; 刘宇; 刘臻; 刘凯
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2022-04-18
Filing date: 2022-04-18
Publication date: 2023-10-27
Also published as: WO2023202305A1

Abstract

The application discloses a chip and a voltage noise suppression method, and belongs to the technical field of power management. The chip comprises a plurality of processors in the same power domain, a power consumption monitoring module and a power consumption adjusting module, wherein the power consumption monitoring module is used for acquiring power consumption change information of the plurality of processors and transmitting the power consumption change information to the power consumption adjusting module, and the power consumption adjusting module is used for carrying out power consumption inhibition on part or all of the plurality of processors according to the power consumption change information of the plurality of processors. In the scene that a plurality of processors share a power supply, the power consumption of the processors is suppressed by comprehensively considering the power consumption change information of the plurality of processors, so that the power consumption of the processors can be suppressed more accurately and more timely, the voltage noise is effectively suppressed, and the performance damage to the processors is reduced.

Description

Chip and voltage noise suppression method

Technical Field

The application relates to the technical field of power management, in particular to a chip and a voltage noise suppression method.

Background

In computing devices such as notebooks, desktops, smartphones and autopilots, as more and more tasks are processed, the computing amount is larger and larger, and a single-core processor cannot meet the task processing requirement, so that the tasks are processed in parallel by using a multi-core processor, and the computing performance and the user experience of the computing device are improved.

The multi-core processors can share a power supply, and when a plurality of processors in the multi-core processors concurrently process tasks or a plurality of heavy-load tasks run, voltage drop upshoots (voltage droop or voltage overshoot) with different frequencies can occur due to rapid increase of power consumption, and the voltage noise can damage the circuit function safety of the computing device, so that the performance of the processors is damaged.

Disclosure of Invention

The application provides a chip and a voltage noise suppression method, which can effectively suppress voltage noise and reduce performance damage to a processor.

In a first aspect, embodiments of the present application provide a chip including a plurality of processors within a same power domain, the plurality of processors being powered by a same power source. The chip also comprises a power consumption monitoring module and a power consumption adjusting module, wherein the power consumption monitoring module is a device or a module for monitoring the running state of the processor and generating power consumption change information of the processor according to the running state of the processor; the power consumption adjusting module refers to a device or a module for adjusting the power consumption of the processor. In the embodiment of the application, the power consumption monitoring module is used for acquiring the power consumption change information of the plurality of processors and transmitting the power consumption change information to the power consumption adjusting module, and the power consumption adjusting module is used for carrying out power consumption inhibition on part or all of the plurality of processors according to the power consumption change information of the plurality of processors.

In the scene that the plurality of processors share the power supply, the embodiment of the application carries out power consumption inhibition by comprehensively considering the power consumption change information of the plurality of processors, and compared with the power consumption inhibition carried out by a single processor, the embodiment of the application can carry out power consumption inhibition on the processors more accurately and more timely, reduce the voltage drop up-rushing condition which occurs when the plurality of processors concurrently process tasks or a plurality of heavy-load tasks operate, thereby effectively inhibiting voltage noise and reducing the performance damage on the processors.

In one possible implementation, the power consumption monitoring module may include a voltage monitoring module separately provided for each of the plurality of processors; a voltage monitoring module refers to a device or module for monitoring a voltage change of a processor. The voltage monitoring module of the first processor is used for monitoring whether voltage drop occurs in the first processor or not, and generating power consumption change monitoring information when the amplitude of the voltage drop exceeds a set amplitude threshold value; the first processor may be any of the plurality of processors described above. The power consumption change monitoring information belongs to one of the power consumption change information, and the power consumption change monitoring information is information generated by monitoring that the processor generates power consumption change. For example, when the voltage drop amplitude of the processor is monitored to exceed a set amplitude threshold or the power consumption change slope of the processor reaches a set slope threshold, the processor is indicated to generate power consumption change, and power consumption change monitoring information is generated. In another possible implementation, the power consumption monitoring module may include a status monitoring module separately provided for each of the plurality of processors; the state monitoring module refers to a device or module for monitoring the slope of the power consumption change of the processor. The state monitoring module of the first processor is used for determining a power consumption change slope according to the running state of the first processor, and generating power consumption change monitoring information when the power consumption change slope reaches a set slope threshold of the first processor. In another possible implementation, the power consumption monitoring module may include a voltage monitoring module and a status monitoring module separately provided for each of the plurality of processors.

The voltage monitoring module or the state monitoring module of the first processor may be disposed inside the first processor or may be disposed outside the first processor. The voltage monitoring module or the state monitoring module of the first processor is used for monitoring the running state of the first processor in real time, and can timely generate the power consumption change information of the first processor, so that the power consumption change of the first processor is informed to the power consumption adjusting module more timely. And the voltage monitoring module and the state monitoring module monitor the power consumption change of the processor in different modes, and can generate the power consumption change information of the processor more comprehensively and timely according to different state information of the processor.

In one possible implementation, the power consumption monitoring module may further include a power consumption change prediction module separately provided for each processor, in addition to the voltage monitoring module or the state monitoring module separately provided for each processor, where the power consumption change prediction module refers to a device or a module for predicting whether a power consumption change will occur to the processor. The power consumption change prediction module of the first processor is used for monitoring the running state of the first processor, predicting whether a power consumption change event will occur in a set time window according to the running state and a historical state record of the power consumption change event, and generating power consumption change prediction information when the power consumption change event is predicted to occur. The power consumption change prediction information also belongs to one of the power consumption change information, and the power consumption change prediction information refers to information generated when an impending power consumption change event is predicted according to the running state of the processor, wherein the power consumption change event refers to the power consumption change of the processor.

In the implementation manner, by setting the power consumption change prediction module, whether the power consumption change event occurs in a future set time window can be predicted in advance, so that the power consumption change information can be provided for the power consumption adjustment module earlier, the power consumption adjustment module is facilitated to determine the power consumption inhibition strategy in advance, and the power consumption inhibition is more effectively carried out.

In one possible implementation, the power consumption monitoring module may further include a signal monitoring module separately provided for each processor, in addition to the voltage monitoring module or the state monitoring module separately provided for each processor, where the signal monitoring module refers to a device or a module for monitoring a signal received by the processor. The signal monitoring module of the first processor is used for monitoring whether the first processor receives a set target signal or not and generating target signal indication information when the first processor receives the set target signal. The target signal indication information also belongs to one of the power consumption change information, and the target signal indication information is information generated when a set target signal is received.

In the implementation manner, whether the processor receives the set target signal or not is monitored by the signal monitoring module, the target signal is a front signal which possibly causes severe power consumption change such as package resonance, and the signal monitoring module monitors the target signal, so that power consumption change information can be provided for the power consumption adjusting module in advance before the severe power consumption change, evidence is provided for restraining time of high-frequency power consumption change events such as package resonance, and the power consumption adjusting module is facilitated to determine a power consumption restraining strategy in advance, and the control drop effectiveness is improved to more effectively restrain the power consumption.

In one possible implementation, the power consumption variation monitoring module of the first processor may include a voltage monitoring module, a state monitoring module, a power consumption variation prediction module, and a signal monitoring module, which more fully provides power consumption variation information to the power consumption adjustment module according to different state information from multiple aspects.

In one possible implementation, the power consumption adjustment module includes a suppression module separately provided for each of the plurality of processors, the suppression module being configured to suppress power consumption of the processor. The suppression module of the first processor is used for receiving the power consumption change information of the first processor transmitted by the power consumption change monitoring module of the first processor, receiving the power consumption change information transmitted by any one processor except the first processor in a broadcast mode, and performing power consumption suppression on the first processor based on the received power consumption change information. The suppression module of the first processor may be disposed inside the first processor or may be disposed outside the first processor.

In the implementation manner, the suppression modules are distributed for each processor, and the suppression modules of the processors can simultaneously learn the power consumption change information of other processors, so that beneficial evidence is provided for judging the power consumption suppression time, the suppression modules of the processors are combined with the received power consumption change information of the other processors to suppress the power consumption of the processor, so that the power consumption suppression is cooperatively carried out by the processors, the voltage drop overshoot control efficiency of the multi-core processor system under a large current jump scene is improved, and the voltage noise is effectively suppressed.

In a possible implementation manner, the power consumption change monitoring module and the suppression module of the first processor are both deployed inside the first processor, and because the communication line is shorter, the power consumption change monitoring module of the first processor can acquire various running state information of the first processor more quickly, and inform the suppression module of the power consumption change information more timely, so that the suppression module is beneficial to suppressing the power consumption of the first processor earlier, and the situation that voltage noise cannot be effectively suppressed due to too late power consumption suppression effect is reduced.

In one possible implementation manner, the suppression module of the first processor may specifically be used to: when power consumption change information of the first processor is received and the power consumption change information of the first processor comprises power consumption change monitoring information, performing power consumption inhibition on the first processor according to a set inhibition proportion aiming at the power consumption change monitoring information; when power consumption change information of a first processor is received and the power consumption change information of the first processor comprises power consumption change prediction information, if the power consumption change information sent by at least N processors is received within a set time period, performing power consumption suppression on the first processor according to a set suppression proportion aiming at the power consumption change prediction information; wherein N is a set threshold value of the number of the change processors; when power consumption change information of the first processor is received and the power consumption change information of the first processor comprises target signal indication information, if the power consumption change information sent by at least M processors is received within a set time period, performing power consumption inhibition on the first processor according to a set inhibition proportion aiming at the target signal indication information; wherein M is a set threshold for the number of processors to be changed.

In the implementation manner, the suppression module can respectively determine the power consumption suppression strategies aiming at the processor according to different situations, and flexibly suppress the power consumption of the processor. For example, when the suppression module of the first processor receives the power consumption change monitoring information of the first processor, which indicates that the power consumption change has occurred and that the power consumption suppression needs to be performed immediately, the suppression module performs the power consumption suppression on the first processor immediately according to the set suppression proportion for the power consumption change monitoring information. When the suppression module of the first processor receives the power consumption change prediction information or the target signal indication information of the first processor, the suppression module can combine the power consumption change information of other processors to determine whether power consumption suppression of the first processor is needed.

In one possible implementation manner, the suppression module of the first processor may specifically be used to: when the power consumption change information of the second processor is received, if the power consumption change information sent by at least K processors is received within a set time period and the service priority of the first processor is lower than that of the second processor, performing power consumption inhibition on the first processor according to a set cascade inhibition proportion; k is a set variable processor number threshold; the second processor is any one of the processors other than the first processor.

In one possible implementation, the suppression module of the first processor is further configured to: after the power consumption of the first processor is suppressed, transmitting suppression information to each processor except the first processor in a broadcasting mode; and receiving the suppression information transmitted by any one processor except the first processor in a broadcast mode. When the suppression information of the second processor is received, if the service priority of the first processor is lower than that of the second processor, power consumption suppression is carried out on the first processor according to the set suppression proportion aiming at the suppression information.

In the implementation manner, when the processors perform cascade power consumption inhibition, the power consumption inhibition is performed on the processor with the lower service priority, so that the normal operation of the processor with the higher service priority is ensured relatively.

In one possible implementation, the chip may further include a configuration module separately provided for each of the plurality of processors; the configuration module of the first processor is used for adjusting a threshold value used by the first processor in the process of generating the power consumption change information and/or a suppression proportion used in the process of performing power consumption suppression according to the received suppression information of any one processor.

In the implementation manner, when the plurality of processors perform cascade power consumption suppression, when suppression information of other processors is received, a threshold value used by the processor in the process of generating power consumption change information or a suppression proportion used in the process of performing power consumption suppression are adjusted, so that the power consumption suppression process of the processor can be more matched with the current power consumption condition in a power domain.

In one possible implementation, the power consumption adjustment module includes an arbitration module and a suppression execution module within a power domain; the arbitration module is used for receiving the power consumption change information of the plurality of processors sent by the power consumption monitoring module, and sending a power consumption suppression instruction to the suppression execution module according to the received power consumption change information, wherein the power consumption suppression instruction comprises a target processor which needs to be subjected to power consumption suppression; the suppression execution module is used for suppressing the power consumption of the target processor according to the power consumption suppression instruction sent by the arbitration module.

In the above-described implementation, by centrally managing the power consumption suppression of each processor, the power consumption suppression operation for each processor can be coordinated according to the power consumption change information of the plurality of processors, and the voltage noise can be suppressed more effectively.

In one possible implementation, the power consumption monitoring module includes a transient current monitoring module disposed within a power domain; the transient current monitoring module is used for monitoring current in a power domain and generating voltage state indication information according to the change of the current. The power consumption change information includes voltage state indication information generated by the transient current monitoring module.

In the implementation manner, the voltage state indication information can be generated according to the transient current change condition in the power supply domain, and can be used as the supplement of the power consumption change information of each processor, so that the current power utilization condition in the power supply domain can be more comprehensively reflected.

In a second aspect, an embodiment of the present application provides a voltage noise suppression method, including: acquiring power consumption change information of a plurality of processors in the same power domain; and performing power consumption inhibition on part or all of the plurality of processors according to the power consumption change information of the plurality of processors.

In one possible implementation manner, the voltage noise suppression method may be executed by a first processor, where the first processor is any one of a plurality of processors; the first processor may acquire power consumption variation information of a plurality of processors located in the same power domain by: monitoring the running state of the first processor, and generating power consumption change information of the first processor according to the running state of the first processor; receiving power consumption change information of a second processor sent by the second processor; the power consumption change information of the second processor is generated according to the operation state of the second processor; the second processor is any one of the processors other than the first processor.

In one possible implementation, the power consumption variation information of the first processor includes at least one of: when the first processor is monitored to generate a power consumption change event, generating power consumption change monitoring information; according to the running state of the first processor and the history state record of the power consumption change event, the power consumption change prediction information generated when the power consumption change event is predicted to occur in a set time window is obtained; and when the first processor is monitored to receive the set target signal, the generated target signal indicating information is generated.

In one possible implementation manner, when the power consumption change monitoring information of the first processor is received, performing power consumption inhibition on the first processor according to a set inhibition proportion aiming at the power consumption change monitoring information; when power consumption change prediction information of a first processor is received, if power consumption change information sent by at least N processors is received within a set time period, performing power consumption suppression on the first processor according to a set suppression proportion aiming at the power consumption change prediction information; n is a set variable processor number threshold; when target signal indication information of a first processor is received, if power consumption change information sent by at least M processors is received within a set time period, power consumption of the first processor is suppressed according to a set suppression proportion aiming at the target signal indication information; m is a set variable processor number threshold.

In one possible implementation manner, when the power consumption change information of the second processor is received, if the power consumption change information sent by at least K processors is received within a set period of time and the service priority of the first processor is lower than the service priority of the second processor, performing power consumption suppression on the first processor according to a set cascade suppression proportion; k is a set threshold for the number of processors to be changed.

In one possible implementation, after power consumption suppression of the first processor, suppression information may be transmitted to each processor other than the first processor by broadcasting.

In one possible implementation, when the suppression information of the second processor is received, if the service priority of the first processor is lower than that of the second processor, power consumption suppression is performed on the first processor according to a set suppression proportion for the suppression information.

In one possible implementation, the first processor may further adjust a threshold value used by the first processor in the power consumption monitoring process and/or a suppression proportion used in the power consumption suppressing process according to the received suppression information of any one processor.

In one possible implementation manner, the voltage noise suppression method is executed by an arbitration module, and the arbitration module can receive power consumption change information of the first processor, which is sent by the first processor; the first processor is any one of a plurality of processors; alternatively, the arbitration module may receive the power consumption change information sent by the transient current monitoring module in the power domain; the power consumption change information is voltage state indication information generated by the transient current monitoring module according to current change in the power supply domain.

In one possible implementation, the arbitration module may determine, according to the received power consumption variation information, a target processor that needs to perform power consumption suppression; and performing power consumption inhibition on the target processor through the inhibition execution module.

In a third aspect, embodiments of the present application provide a computer-readable storage medium having stored therein computer-executable instructions for causing a computer to perform any one of the methods provided in the second aspect above.

In a fourth aspect, embodiments of the present application provide a computer program product comprising computer executable instructions for causing a computer to perform any of the methods provided in the second aspect above.

The technical effects achieved by any one of the second aspect to the fourth aspect may be referred to the description of the beneficial effects in the first aspect, and the detailed description is not repeated here.

Drawings

FIG. 1 is a schematic diagram of a chip according to an embodiment of the present application;

FIG. 2 is a schematic diagram of a processor according to an embodiment of the present application;

fig. 3 is a schematic structural diagram of a power consumption change monitoring module according to an embodiment of the present application;

FIG. 4 is a flowchart of a power consumption suppression process performed by a suppression module according to an embodiment of the present application;

FIG. 5 is a schematic diagram of another processor according to an embodiment of the present application;

FIG. 6 is a schematic diagram of another chip according to an embodiment of the present application;

FIG. 7 is a flowchart illustrating a power consumption suppression process performed by an arbitration module according to an embodiment of the present application;

FIG. 8 is a schematic diagram of another chip according to an embodiment of the present application;

fig. 9 is a flowchart of a voltage noise suppression method according to an embodiment of the present application.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present application more apparent, the embodiments of the present application will be described in detail below with reference to the accompanying drawings. The terminology used in the description of the embodiments of the application herein is for the purpose of describing particular embodiments of the application only and is not intended to be limiting of the application. It will be apparent that the described embodiments are merely some, but not all embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.

Before describing the embodiments of the present application, some of the words in the present application are explained in order to facilitate understanding of those skilled in the art, and the words in the present application are not limited thereto.

(1) Processor cluster (processor cluster): multiple processors within the same power domain, or multiple processors powered by the same power source, may be referred to as a processor cluster.

In the embodiments of the present application, "a plurality" refers to two or more, and in this regard, "a plurality" may be understood as "at least two" in the embodiments of the present application. "at least one" may be understood as one or more, for example as one, two or more. For example, including at least one means including one, two or more, and not limiting what is included, e.g., including at least one of A, B and C, then A, B, C, A and B, A and C, B and C, or A and B and C, may be included. "and/or", describes an association relationship of an association object, and indicates that there may be three relationships, for example, a and/or B, and may indicate: a exists alone, A and B exist together, and B exists alone. The character "/", unless otherwise specified, generally indicates that the associated object is an "or" relationship.

Unless stated to the contrary, the embodiments of the present application refer to ordinal terms such as "first," "second," etc., for distinguishing between multiple objects and not for defining a sequence, timing, priority, or importance of the multiple objects.

In an application scenario that the multi-core processor shares the same power supply, when a plurality of processors concurrently process tasks or a plurality of heavy-load tasks run, power consumption is increased sharply, and the problem of power supply integrity (power integration, PI) of the multi-core processor is obvious, and the problem is mainly represented by voltage drop overshoot with different frequencies frequently occurring, so that voltage noise is generated, the voltage noise may harm the circuit function safety of the computing device, and performance damage of the processor is caused or benefit of the minimum working voltage of the circuit is influenced.

Based on this, the embodiment of the application provides a chip, which includes a plurality of processors in the same power domain, that is, the plurality of processors are powered by the same power source, and the power source for powering the plurality of processors may be disposed in the chip or may be disposed outside the chip, where the plurality of processors are all connected by the power source.

The chip may be a system on chip (SoC) or a compute chip used in a computing device, a control logic chip or a forwarding logic chip used in a router, or other chip including a multi-core processor, for example. The processor may be a general purpose processor such as a microprocessor, a central processing unit (central processing unit, CPU), or other processors such as an application processor (application processor, AP), a modem processor, a tensor processor (tensor processing unit, TPU) chip, a neural network processor (neural-network processing unit, NPU), a graphics processor (graphic processing unit, GPU), an artificial intelligence (artificial intelligence, AI) processor, an image signal processor (image signal processor, ISP), a controller, a video codec, a digital signal processor (digital signal processor, DSP), a baseband processor, or the like.

The chip provided by the embodiment of the application comprises a plurality of processors in the same power domain, a power consumption monitoring module and a power consumption adjusting module, wherein the power consumption monitoring module is a device or a module for monitoring the running state of the processors and generating power consumption change information of the processors according to the running state of the processors; the power consumption adjusting module refers to a device or a module for adjusting the power consumption of the processor. In the embodiment of the application, the power consumption monitoring module is used for acquiring the power consumption change information of the plurality of processors and transmitting the power consumption change information to the power consumption adjusting module, and the power consumption adjusting module is used for carrying out power consumption inhibition on part or all of the plurality of processors according to the power consumption change information of the plurality of processors. By combining the power consumption change information of a plurality of processors in the same power domain, the power consumption of the processors can be accurately determined when the power consumption of the processors needs to be suppressed, and which processor needs to be suppressed, so that the power consumption of the processors can be suppressed timely when the power consumption is increased sharply or before the power consumption is increased sharply, voltage noise can be suppressed more effectively, and performance damage to the processors is reduced.

Fig. 1 schematically illustrates a structure of a chip according to an embodiment of the present application. In some embodiments, as shown in FIG. 1, the chip 100 includes N processors, processor 0, processor 1 … …, and processor N-1, each powered by a power supply 200. N processors are powered by the same power supply and can be used as a processor cluster. In other embodiments, the processor cluster shown in fig. 1 may include more than 3 processors, and in other embodiments, the processor cluster may include 2 processors, i.e., N is an integer greater than or equal to 2. The power supply 200 shown in fig. 1 is disposed outside the chip 100, and in other embodiments, the power supply 200 may be disposed inside the chip 100. When the power supply 200 is disposed inside the chip 100, the power supply 200 may be disposed inside the processor cluster or may be disposed outside the processor cluster. In some embodiments, each processor is provided with an on-chip low dropout linear regulator (low dropout regulator, LDO), but in high voltage scenarios, it is still necessary to pass through to the same power supply, powered by the same power supply, which also belongs to multiple processors within the same power domain.

As shown in fig. 1, a power consumption variation monitoring module 110 and a suppression module 120, which are respectively provided for each of N processors, are included in a chip 100. The power consumption change monitoring module 110 is configured to monitor an operation state of a corresponding processor, and generate power consumption change information of the corresponding processor according to the operation state of the corresponding processor, that is, the power consumption change monitoring module 110 implements a function of the power consumption monitoring module. The power consumption change monitoring module 110 may be provided inside the corresponding processor or may be provided outside the corresponding processor. When the power consumption variation monitoring module 110 may be disposed outside the corresponding processor, the power consumption variation monitoring module 110 may be disposed in close proximity to the corresponding processor so that a variation in current, power consumption or voltage of the corresponding processor may be perceived in time. The suppression module 120 is configured to receive power consumption variation information of any one processor, and perform power consumption suppression on the processor corresponding to the suppression module 120 based on the received power consumption variation information, that is, the suppression module 120 implements the function of the power consumption adjustment module. The suppression module 120 may be disposed inside the corresponding processor or may be disposed outside the corresponding processor. The power consumption variation monitoring module 110 and the suppressing module 120 in fig. 1 are both provided inside the corresponding processor.

Taking the processor 0 as an example for illustration, the processor 0 shown in fig. 1 is internally provided with a power consumption change monitoring module 110 and a suppression module 120. The power consumption change monitoring module 110 of the processor 0 is configured to monitor an operation state of the processor 0, generate power consumption change information of the processor 0 according to the operation state of the processor 0, and transmit the generated power consumption change information of the processor 0 to the suppression module 120 of the processor 0. The power consumption change monitoring module 110 of the processor 0 may transmit the power consumption change information of the processor 0 to the suppression module 120 of the other processor in addition to the power consumption change information of the processor 0, that is, the suppression module 120 of each of the processors 1 to N-1 may receive the power consumption change information of the processor 0 sent by the power consumption change monitoring module 110 of the processor 0. The suppression module 120 of the processor 0 is configured to receive the power consumption variation information of the processor 0 transmitted by the power consumption variation monitoring module 110 of the processor 0, and receive the power consumption variation information transmitted by any one of the processors except the processor 0 in a broadcast manner, and perform power consumption suppression on the processor 0 based on the received power consumption variation information.

Fig. 2 schematically illustrates an internal structure of a processor according to an embodiment of the present application. As shown in fig. 2, the processor includes a power consumption variation monitoring module 110 and a suppression module 120, and further includes a plurality of functional units for implementing computing functions and control functions, such as a fetch unit 131 (instruction fetch unit, IFU), an instruction dispatch (instruction dispatch) unit 132, a prefetch unit 133, a branch predictor unit 134, an integer execution unit (int.execution unit) 135, a load store unit 136, a floating point number and single instruction multiple data stream (single instruction multiple data, SIMD) unit, or a so-called floating point number and SIMD unit 137. A cache system 138 may also be included in the processor, and a load store unit 136 may store loaded program instructions or data temporarily in the cache system 138. Each of the functional units and the buffer system 138 is connected to the power consumption change monitoring module 110, and each of the functional units is connected to the suppressing module 120, and the suppressing module 120 may perform power consumption suppression on any one of the functional units. Processor 0 through processor N-1 of FIG. 1 may each employ the processor architecture shown in FIG. 2.

The internal structures of the power consumption variation monitoring module 110 and the suppressing module 120 are described below with the processor 0 as an example. The power consumption change monitoring modules of the other N-1 processors have the same structure as the power consumption change monitoring module of the processor 0, and the inhibition modules of the other N-1 processors have the same structure as the inhibition module of the processor 0.

In some embodiments, the power consumption change monitoring module 110 of the processor 0 may include an event monitoring module, where the event monitoring module is configured to generate power consumption change monitoring information when it monitors that the processor 0 has a power consumption change event, transmit the power consumption change monitoring information to the suppression module 120 of the processor 0, and transmit the power consumption change monitoring information to the suppression modules 120 of other processors except the processor 0 by broadcasting. Wherein, the occurrence of the power consumption change event by the processor 0 means that the occurrence of the voltage drop or the voltage overshoot event by the processor 0 is caused. The power consumption variation monitoring information is one type of power consumption variation information. For example, the event monitoring module may detect whether a state that affects the processor is generated according to a high power consumption jump indicating event of each functional unit in the processor, for example, whether the scalable vector engine (scalable vector extensions engine, SVE) module operation unit is full, a state of the load storage pipeline (load store pipeline), whether an abnormal flushing state occurs, or the like, or by using a mode of a modeling detection circuit of one or more critical paths.

In one embodiment, the event monitoring module may include a voltage monitoring module for monitoring whether a voltage dip has occurred in the processor 0 and generating power consumption variation monitoring information when the magnitude of the voltage dip exceeds a set magnitude threshold. In another embodiment, the event monitoring module may include a state monitoring module for determining a power consumption change slope according to an operation state of the processor 0 and generating power consumption change monitoring information when the power consumption change slope reaches a set slope threshold of the processor 0. In another embodiment, the event monitoring module may include a voltage monitoring module and a status monitoring module.

In other embodiments, the power consumption change monitoring module 110 of the processor 0 may further include a power consumption change prediction module, in addition to the event monitoring module, configured to monitor an operation state of the processor 0, predict whether the power consumption change event will occur in the processor 0 within a set time window according to the operation state of the processor 0 and a history of the power consumption change event, generate power consumption change prediction information when it is predicted that the power consumption change event will occur in the processor 0, transmit the power consumption change prediction information to the suppression module 120 of the processor 0, and transmit the power consumption change prediction information to the suppression modules 120 of other processors except the processor 0 in a broadcast manner. Wherein the power consumption variation prediction information is one of the power consumption variation information.

In other embodiments, the power consumption change monitoring module 110 of the processor 0 may further include a signal monitoring module, in addition to the event monitoring module, where the signal monitoring module is configured to monitor whether the processor 0 receives the set target signal, generate target signal indication information when the processor 0 receives the set target signal, transmit the target signal indication information to the suppression module 120 of the processor 0, and transmit the target signal indication information to the suppression modules 120 of other processors except the processor 0 by broadcasting. Wherein the target signal indication information is one of power consumption variation information.

In other embodiments, the power consumption change monitoring module 110 of the processor 0 may include a power consumption change prediction module and a signal monitoring module in addition to the event monitoring module. It should be noted that, each module included in the power consumption change monitoring module 110 may be selected and combined according to an actual application scenario, or only one module may be used to implement similar functions.

For convenience of understanding, fig. 3 schematically illustrates a structure of a power consumption change monitoring module according to an embodiment of the present application. As shown in fig. 3, the power consumption change monitoring module 110 may include a voltage monitoring module 111, a state monitoring module 112, a power consumption change prediction module 113, and a signal monitoring module 114.

The voltage monitoring module 111 may employ a critical path detector (critical path monitor, CPM). The voltage monitoring module 111 may use an analog critical path (critical path) circuit to detect whether the processor 0 experiences a voltage sag, and generate power consumption change monitoring information if the processor 0 experiences a voltage sag and the voltage sag exceeds a set amplitude threshold of the processor 0.

The state monitoring module 112 may employ a current sensor (sensor) for monitoring the current difference (delta current in delta time, DIDT) per unit time, and the current sensor may use digital logic to determine the power consumption change slope of the processor based on the monitored current difference, generating power consumption change monitoring information.

In some embodiments, the state monitoring module 112 may detect the running state of the processor 0 according to a set DIDT detection period, including detecting events or signals of each functional unit of the processor 0, and performing weighted average on the detected high power consumption events or key signals of each functional unit, and fitting to obtain the power consumption of the processor 0. And determining a power consumption change slope according to the power consumption of the processor 0 in different time periods, and generating power consumption change monitoring information when the power consumption change slope reaches a set slope threshold of the processor 0.

In one embodiment, the power consumption change slope may take the form of an absolute slope value. The state monitoring module 112 may determine the nth detection time window P according to the set window duration _n Power consumption and n-1 th detection time window P _n-1 And calculates a detection time window P _n Power consumption detection time window P of (2) _n-1 The difference between the power consumption and the power consumption of the processor 0 is taken as the power consumption change slope of the processor 0, and the difference is an absolute slope value. Wherein, is provided withThe fixed window duration may be in units of clock cycles (cycles) of the processor, for example, the set window duration may be several or several tens of clock cycles. Detection time window P _n And detection time window P _n-1 Is two adjacent detection windows and detects time window P _n And is located in the detection time window P _n-1 After that, the process is performed. That is, the state monitoring module 112 may determine the power consumption change slope based on the power consumption difference of two adjacent detection time windows.

In another embodiment, the power consumption change slope may take the form of a moving average slope value. The state monitoring module 112 may determine power consumption of n adjacent detection time windows according to the set window duration. The first n-1 detection time windows are calculated, namely, the slave detection time windows P ₁ Up to detection time window P _n-1 By using a detection time window P _n Subtracting the average value of the power consumption of the previous n-1 detection time windows from the power consumption of the previous n detection time windows to obtain a mobile average slope value; alternatively, a weighted average of the power consumption of the first n-1 detection time windows therein is calculated, and the weight of the power consumption of each detection time window may be determined as follows: detection time window P _n-1 The power consumption of (2) is 1/2, and the time window P is detected _n-2 The power consumption of (2) is 1/4, and the time window P is detected _n-3 The power consumption of (2) is 1/8, and so on; using a detection time window P _n Subtracting the weighted average of the power consumption with the power consumption of the first n-1 detection time windows to obtain a mobile average slope value. That is, the state monitoring module 112 may determine the power consumption change slope from the power consumption difference values of the adjacent n detection time windows. By the method, the power consumption change slope can be determined more accurately.

In some embodiments, the set slope threshold of the processor 0 refers to a set maximum slope threshold, the power consumption slope threshold of the processor 0 may further include a set minimum slope threshold, and if the power consumption change slope is greater than or equal to the set maximum slope threshold, the state monitoring module 112 sets an event identification in a register corresponding to the power consumption change monitoring information, and generates the power consumption change monitoring information from no to some change based on the event identification. If the power consumption change slope is less than or equal to the set minimum slope threshold, the state monitoring module 112 may clear the event identification in the register corresponding to the power consumption change monitoring information.

The voltage monitoring module 111 or the state monitoring module 112 of the processor 0 generates power consumption change monitoring information, which indicates that the processor 0 has occurred a power consumption change event, and needs to perform active defense immediately, and the suppression module 120 receives the power consumption change monitoring information sent by the power consumption change monitoring module 110 and performs power consumption suppression on the processor 0 immediately.

Since the power consumption change monitoring module 110 is a module responsible for giving an indication signal of a severe change in power consumption of the processor, the shorter the detection delay of the power consumption change monitoring module 110, the better the power consumption suppression effect. The detection response time of the voltage monitoring module 111 and the state monitoring module 112 is ns level or even cycle level, so that the power consumption change monitoring information can be quickly generated and transmitted to the suppression module 120 of the processor 0, and the suppression module 120 can respond in time to suppress the power consumption of the processor 0. The voltage monitoring module 111 and the state monitoring module 112 may be used in combination or separately in different application scenarios. The power consumption change monitoring information generated by the voltage monitoring module 111 and the state monitoring module 112 is hereinafter referred to as an S1 event, and an S1 event flag (flag) is carried in the S1 event.

In some embodiments, the outputs of the voltage monitoring module 111 and the status monitoring module 112 may be connected to a Multiplexer (MUX) 115, and the multiplexer 115 may be understood as a connector including a plurality of input ports and an output port. One input port of the multiplexer 115 is connected to the output port of the voltage monitoring module 111, the other input port is connected to the output port of the state monitoring module 112, and the output port of the multiplexer 115 is connected to the input port of the rejection module 120. The multiplexer 115 is configured to transmit the S1 event generated by the voltage monitoring module 111 or the status monitoring module 112 to the suppression module 120. The multiplexer 115 may be disposed inside the voltage monitoring module 111 or may be disposed outside the voltage monitoring module 111.

The detection delay of the voltage monitoring module 111 and the state monitoring module 112 is very short and can be only 1cyc, so that when the generated S1 event reaches the suppression module of other processors, the power consumption is still suppressed, and the effect of suppressing the voltage noise is generated.

The power consumption change prediction module 113 may employ a current slope-based predictor (DIDT predictor). The power consumption change prediction module 113 is configured to monitor an operation state of the processor 0, and predict whether the power consumption change event will occur in the processor 0 within the W1 time window according to the operation state of the processor 0 and a history of the power consumption change event. The time window W1 refers to a time window with a set time length W1 from the current time. If it is predicted that the processor 0 will generate a power consumption change event within the W1 time window, power consumption change prediction information is generated, transmitted to the suppression module 120 of the processor 0, and transmitted to the suppression modules 120 of other processors except the processor 0 by broadcasting. The set period of time W1 may be, for example, any period of time between 10-50cyc, or longer.

Illustratively, the power consumption change prediction module 113 may employ a prediction algorithm to determine a probability that the power consumption change event will occur by the processor 0 within the W1 time window according to the running state of the processor 0 and the history of the power consumption change event, and generate the power consumption change prediction information if the determined probability is greater than or equal to the set probability value. The historical state record of the power consumption change event may include a pattern (pattern) of an instruction sequence executed by the processor 0 during the period of time and before the period of time when the power consumption change event actually occurs, or a statistical record of the state of the pattern of the high power consumption event. In some embodiments, the power consumption change prediction module 113 may also generate power consumption change prediction information when the software of the processor 0 or the mating circuitry of the SoC gives a hint that a high power consumption thread may be generated. In other embodiments, the power consumption change prediction module 113 may also generate the power consumption change prediction information when the speculative prefetch instruction of the processor 0 fails, because the speculative prefetch instruction of the processor may cause a high power consumption event that flushes the data fetched by the prefetch instruction when the prediction fails.

The operation state of the processor 0, such as pattern of the instruction sequence or pattern of occurrence of the high power consumption event, detected by the voltage monitoring module 111 or the state monitoring module 112, may be added to the history state record, so that when a similar pattern occurs next time, the power consumption change prediction module 113 may predict whether the processor 0 will generate the power consumption change event in the next W1 time window according to the history state record.

In some embodiments, when generating the power consumption variation prediction information according to a pattern in the history state record, the power consumption variation prediction module 113 sets an event flag in a register corresponding to the power consumption variation prediction information. The voltage monitoring module 111 or the state monitoring module 112 detects the power consumption change event caused by the pattern as a refresh indication for triggering the power consumption change prediction module 113, that is, when the voltage monitoring module 111 or the state monitoring module 112 detects the power consumption change event corresponding to the power consumption change prediction information, the power consumption change prediction module 113 is triggered to clear the event identifier in the register corresponding to the power consumption change prediction information; and simultaneously refreshing the prediction probability corresponding to the pattern in the history state record. For example, the voltage monitoring module 111 or the state monitoring module 112 detects a power consumption change event corresponding to the power consumption change prediction information, which indicates that the power consumption change prediction module 113 successfully predicts the pattern, and increases the success rate of the prediction of the pattern, so that the prediction probability corresponding to the pattern can be increased in the history state record.

If a power consumption change event has occurred after the pattern in the history, but no power consumption change event actually occurs after the pattern, the success rate of prediction of the pattern is reduced, that is, within a preset period after the power consumption change prediction module 113 generates the power consumption change prediction information, the voltage monitoring module 111 and the state monitoring module 112 do not detect the power consumption change event corresponding to the power consumption change prediction information, the power consumption change prediction module 113 clears the event identifier in the register corresponding to the power consumption change prediction information, and reduces the prediction probability corresponding to the pattern in the history state record. If the prediction probability corresponding to a pattern is lower than the set probability value, the power consumption change prediction module 113 may not generate power consumption change prediction information according to the pattern any more, so as to reduce occurrence of false alarm.

Assuming that the current time is T0, the power consumption change prediction module 113 of the processor 0 generates power consumption change prediction information indicating that a power consumption change event will occur to the processor 0 within a future W1 time from T0. Assuming that the delay of broadcasting the power consumption variation prediction information to the suppression modules 120 of other processors is tn, the power consumption variation prediction information broadcast by the processor 0 received by the suppression module 120 of any one processor is expressed as meaning that the power consumption variation event will occur in the processor 0 within the time window of W1-tn from the time of t0+tn, that is, the phenomenon that the processor 0 quickly climbs by performance or power consumption occurs. In order to prevent the power consumption suppression of power consumption change events for some specific scenarios from taking effect too late, resulting in failure of active defense, the delay tn needs to be minimized.

The power consumption change prediction information generated by the power consumption change prediction module 113 is hereinafter referred to as an S2 event, and the S2 event carries an S2 event flag.

The signal monitoring module 114 may employ a system change value Flag (system change number Flag, SCN Flag) monitor. The signal monitoring module 114 is configured to monitor whether the processor 0 receives a set target signal, generate target signal indication information when the processor 0 receives the set target signal, transmit the target signal indication information to the suppression module 120 of the processor 0, and transmit the target signal indication information to the suppression modules 120 of other processors except the processor 0 in a broadcast manner. The set target signals may include, but are not limited to, one or more of the following: a wait for event (WFE) signal, a wait for interrupt (wait for interrupt, WFI) signal, a deep flush (deep flush) signal, a branch flush (branch flush) signal, a cache flush (cache flush) signal, a high power event (high power event) indication signal, a high power burst indication signal, or the like. The signal monitoring module 114 may identify, in advance, a special scenario that may cause a power consumption change event based on the above-mentioned target signal, and notify the suppression module 120 earlier, so that the suppression module 120 may perform peak-staggering suppression or avoid the package resonant frequency. The signal monitoring module 114 generates the target signal indication information that needs to be pre-determined in advance of the power consumption change event, the earlier the better. For example, the WFI signal may be obtained from the IFU or may be obtained earlier from an external wake-up interrupt interface.

The signal monitoring module 114 generates target signal indication information when it monitors that the processor 0 receives any one of the target signals. The target signal indication information generated by the signal monitoring module 114 is hereinafter referred to as an S3 event, and the S3 event carries an S3 event flag.

The above-mentioned S1 event, S2 event, and S3 event are all power consumption change information generated by the power consumption change monitoring module 110 of the processor 0. The power consumption variation monitoring module 110 of the processor 0 may transmit the generated power consumption variation information to the suppression module 120 of the other processor by broadcasting, in addition to transmitting the power consumption variation information to the suppression module 120 of the processor 0. The power consumption change monitoring module 110 of the processor 0 is closer to the suppression module 120 of the processor 0 than to the suppression modules 120 of other processors, so that the suppression modules 120 of the processor 0 can receive the power consumption change information of the processor 0 sent by the power consumption change monitoring module 110 of the processor 0 earlier than the suppression modules 120 of other processors.

When the power consumption change monitoring module 110 of the processor 0 transmits the power consumption change information of the processor 0 to the suppression module 120 of another processor, different kinds of power consumption change information may be transmitted through one communication signal line, or different kinds of power consumption change information may be transmitted through different communication signal lines, for example, the S1 event may be transmitted through a first communication signal line, the S2 event may be transmitted through a second communication signal line, and the S3 event may be transmitted through a third communication signal line. The time delay of the transmission path from the processor 0 to other processors should be constrained to a reasonable range so as to be capable of meeting the constraint condition that the generated power consumption inhibition processing action can act on voltage drop after each processor receives the power consumption change information of the processor 0. In some embodiments, to reduce latency, power consumption change information may be transmitted over high-level metal traces to ensure that power consumption change information can reach other processors within a short latency. In other embodiments, the S1 event or S3 event may be transmitted to other processors by way of an interrupt, message mailbox, or other non-physical trace, rather than being transmitted to other processors by way of an physical communication signal line.

The above description is of the power consumption change monitoring module 110 of the processor 0, and the suppression module 120 of the processor 0 is described below. The throttle module 120 of the processor 0 is responsible for controlling the power consumption level of the functional units within the processor 0.

The suppression module 120 of the processor 0 may receive the power consumption variation information of the processor 0 transmitted by the power consumption variation monitoring module 110 of the processor 0, and the power consumption variation information transmitted by any one of the processors except the processor 0 through broadcasting, and perform power consumption suppression on the processor 0 based on the received power consumption variation information. Specific ways in which the suppression module 120 may suppress power consumption of the processor may include, but are not limited to: adjusting the clock frequency of the processor, such as adjusting the clock frequency from 100MHz to 70MHz; a clock gating (clock gating) mode is adopted, for example, the clock is controlled to stop 2 beats when 8 beats are operated; suppressing pipeline bandwidth of a processor, such as reducing bandwidth of pipelines inside each functional unit in the processor; suppressing peak current; suppressing part of the functional units in the processor, such as powering down or turning off part of the functional units, or suppressing only the functional units that generate high power consumption events; temporarily shutting down some of the processor functions, etc. The throttling module 120 may employ one or more of the throttling modes described above to throttle power consumption of the processor.

For example, when the suppression module 120 of the processor 0 receives the power consumption change information of the processor 0, and the power consumption change information includes the S1 event, which indicates that the power consumption change event has occurred in the processor 0, the suppression module 120 may perform power consumption suppression on the processor 0 according to the set suppression proportion corresponding to the S1 event.

When the suppression module 120 of the processor 0 receives the power consumption change information of the processor 0 and the power consumption change information includes an S2 event, if the suppression module 120 of the processor 0 receives the power consumption change information sent by at least N processors in a set period of time, the suppression module 120 performs power consumption suppression on the processor 0 according to a set suppression proportion corresponding to the S2 event; n is the number threshold of the change processors corresponding to the set S2 event.

When the suppression module 120 of the processor 0 receives the power consumption change information of the processor 0 and the power consumption change information includes an S3 event, if the suppression module 120 of the processor 0 receives the power consumption change information sent by at least M processors in a set period of time, the suppression module 120 performs power consumption suppression on the processor 0 according to a set suppression proportion corresponding to the S3 event; wherein M is the threshold value of the number of the change processors corresponding to the set S2 event.

When the suppression module 120 of the processor 0 receives the power consumption change information of another processor, if the suppression module 120 of the processor 0 receives the power consumption change information sent by at least K processors within a set period of time and the service priority of the processor 0 is lower than the service priority of the other processor, performing power consumption suppression on the processor 0 according to a set suppression proportion corresponding to the power consumption change information of the other processor; the other processor may be any one processor except the processor 0, where K is a threshold value of the number of changed processors corresponding to the set power consumption change information of the other processors. K may be the same as or different from M, N.

In some embodiments, the throttling module 120 of the processor 0 may include a power consumption event arbitration module and a peak power consumption throttling (MaxPower Mitigation, MXPM) module. The power consumption event arbitration module is used for determining whether to carry out power consumption inhibition on the processor 0 according to the received power consumption change information of each processor, and sending an inhibition instruction to the peak power consumption inhibition module when determining to carry out power consumption inhibition on the processor 0, wherein the inhibition instruction comprises inhibition proportion and inhibition duration. The peak power consumption suppression module may perform power consumption suppression on the processor 0 for a suppression duration according to a suppression proportion in the power consumption suppression instruction.

After the power consumption of the processor 0 is suppressed by the suppression module 120 of the processor 0, suppression information is transmitted to other processors except the processor 0 in a broadcast manner, so that the other processors determine whether the power consumption suppression needs to be performed in a linkage manner.

The suppression module 120 of processor 0 may also receive suppression information transmitted by any one of the other processors by broadcast. When the suppression information of another processor is received, if the service priority of the processor 0 is lower than that of the other processor, the suppression module 120 suppresses the power consumption of the processor 0 according to the set suppression proportion corresponding to the suppression information, thereby suppressing the voltage noise. The suppression information is hereinafter referred to as an S4 event, and the S4 event carries an S4 event flag.

As shown in fig. 1, the suppression module 120 of the processor 0 includes a suppression information input interface, i.e., an S4 input interface 121, and a suppression information output interface, i.e., an S4 output interface 122. The suppression module 120 of processor 0 may receive S4 events broadcast by other processors via S4 input interface 121 and broadcast suppression information to other processors via S4 output interface 122.

When the power consumption change monitoring module 110 includes an event monitoring module, a power consumption change prediction module, and a signal monitoring module, the power consumption change information received by the suppression module 120 of the processor 0 may be any one of an S1 event, an S2 event, or an S3 event. At this time, the process of suppressing power consumption by the suppressing module 120 of the processor 0 is as shown in fig. 4, and includes the following steps:

S401, event information is received.

The power consumption change information of the processor 0 transmitted by the power consumption change monitoring module 110 of the processor 0 and received by the suppression module 120 of the processor 0, and the power consumption change information and the suppression information transmitted by other processors may be referred to as event information. The power consumption change information may be any one of an S1 event, an S2 event, or an S3 event, and the suppression information is an S4 event.

The event information sent by any one processor may carry the identification information of the processor and the event flag, for example, the S1 event carries the S1 event flag. Power consumption change monitoring module 110 of processor 0The transmitted event information may also carry identification information of the processor 0. The processor may be referred to as a processor core (core), and the identification information of the processor may be C _n The value of N is an integer value in 1 and … … N-1; illustratively, the S1 event for processor 0 is denoted as C hereinafter ₀ S1, S2 event of processor 0 is denoted as C ₀ S2, the S1 event of processor 1 is denoted C ₁ -S1。

S402, judging whether the event information is the event information of the processor 0; if yes, go to step S403, if no, go to step S407;

s403, judging whether the event is an S1 event; if yes, go to step S404; if not, executing step S405;

The suppression module 120 may determine which processor transmits the event information according to the identification information of the processor carried in the event information. In the event information of the processor 0, it may be determined whether it is an S1 event according to an event flag carried in the event information.

S404, performing power consumption inhibition on the processor 0 according to the set inhibition proportion corresponding to the S1 event.

If C is received ₀ S1, i.e. an S1 event of the processor itself, which indicates that the processor itself has occurred a power consumption change event, and active defense needs to be performed immediately, the suppression module 120 may perform power consumption suppression on the processor 0 in a suppression duration corresponding to the set S1 event according to a set suppression proportion corresponding to the S1 event, so as to reduce power supply noise.

S405, judging whether power consumption change information sent by at least N processors is received; if yes, step S406 is executed, and if no, step S410 is executed.

Wherein N is a set number. The value of N may be 1, 2, 3 or other integer value.

And S406, performing power consumption inhibition on the processor 0 according to the set inhibition proportion corresponding to the S2/S3 event.

If it is not an S1 event of processor 0, the description is an S2 event or an S3 event of processor 0. At this time, if the number of processors transmitting the power consumption variation information is greater than or equal to N, it may be according to S2/S3 matters And the corresponding set inhibition proportion carries out power consumption inhibition on the processor 0 within the set inhibition duration. Illustratively, assume that C is currently received ₀ S2, counting the number of processors transmitting the power consumption variation information by: and counting the power consumption change information transmitted by the processors which are received in total in the current time and the set time period before the current time. For example, the statistics may be: within 0.05ms of the current time and before the current time, except that the above C is received ₀ -also receive C before S2 event ₁ S1, i.e. power consumption change information sent by 2 processors in total is received.

For example, if N is 1, when it is determined that the S2 event or the S3 event of the processor 0 is received, the power consumption of the processor 0 may be suppressed in the suppression period corresponding to the set S2/S3 event according to the set suppression ratio corresponding to the S2/S3 event. If N is 2, when the number of processors sending the power consumption change information is determined to be 2 or more, performing power consumption inhibition on the processor 0 in the inhibition duration corresponding to the set S2/S3 event according to the set inhibition proportion corresponding to the S2/S3 event; otherwise, if only C is received within 0.05ms of the current time and before the current time ₀ -S2 or C ₀ S3 event, the power consumption of the processor 0 may not be suppressed, and the next event information may be continued to be waited for.

In the embodiment shown in fig. 4, the set suppression ratio corresponding to the S2 event and the set suppression ratio corresponding to the S3 event adopt the same set ratio value, and the suppression duration corresponding to the S2 event and the suppression duration corresponding to the S3 event may also be the same.

In other embodiments, the set suppression ratio corresponding to the S2 event and the set suppression ratio corresponding to the S3 event may be different, and the suppression duration corresponding to the S2 event and the suppression duration corresponding to the S3 event may be different. After determining that the received event information is the power consumption variation information of the processor 0, it may further determine whether it is an S2 event or an S3 event according to the event flag in the event information. If C is received ₀ S2, when it is determined that the number of processors transmitting the power consumption variation information reaches N, it may be performed as in S2And the power consumption of the processor 0 is restrained within the restraining time period corresponding to the set S2 event by the corresponding set restraining proportion. If C is received ₀ And S3, when the number of processors for transmitting the power consumption change information reaches M, performing power consumption inhibition on the processor 0 according to the set inhibition proportion corresponding to the S3 event within the set inhibition duration corresponding to the S3 event. Wherein M is also a set number, and M and N can be the same or different.

In other embodiments, it may be further configured that the step of suppressing power consumption of the processor is performed only when an S1 event of at least N1 processors, an S2 event of at least N2 processors, and an S3 event of at least N3 processors are received. Wherein, the value of N1 may be 0, 1, 2 or other integer values, the value of N2 may be 0, 1, 2 or other integer values, and the value of N3 may be 0, 1, 2 or other integer values. For example, suppose that N1 has a value of 1, N2 has a value of 2, and N3 has a value of 0, if at the current time C is received ₀ S2, within 0.05ms before the current time, only C is received ₁ -S2 event, then no power consumption throttling of processor 0 is performed, and waiting for the arrival of the next event information; if at the current time C is received ₀ S2, within 0.05ms before the current time, C is received ₁ S1 and C ₃ -S2 two power consumption change information, or power consumption change information of other processors is also received, and power consumption of processor 0 may be suppressed according to the set suppression proportion corresponding to the S2 event within the set suppression duration corresponding to the S2 event.

S407, judging whether power consumption change information sent by at least K processors is received or not; if yes, step S408 is executed, and if no, step S410 is executed.

And if the event information is the event information sent by other processors, judging whether power consumption change information sent by at least K processors is received. Where K is also a set number. The value of K can be the same as N or different from N.

S408, judging whether the service priority of the processor 0 is lower than the service priority of the processor sending the power consumption change information; if yes, step S409 is executed, and if no, step S410 is executed.

S409, performing power consumption inhibition on the processor 0 according to the set cascade inhibition proportion.

In the embodiment shown in fig. 4, if the event information is sent by another processor, and it is determined that the number of processors sending the power consumption change information is greater than or equal to K in the current time and the set time period before the current time, and the service priority of the processor 0 is low, the power consumption of the processor 0 may be suppressed in the set suppression period corresponding to the other processor according to the set suppression proportion corresponding to the other processor.

Illustratively, if K is 3, then C is received ₁ -S1, if it is determined that the number of processors transmitting the power consumption variation information is 3 or more, comparing the service priorities of processor 0 and processor 1, and if the service priority of processor 0 is lower than the service priority of processor 1, performing power consumption suppression on processor 0 in the set suppression periods corresponding to other processors according to the set suppression ratios corresponding to other processors; otherwise, the processor 0 may not be power-consumption-suppressed, and continue to wait for the arrival of the next event information. The set suppression ratio corresponding to the other processors may be different from the set suppression ratio corresponding to the various power consumption variation information of the processors themselves.

In other embodiments, the power consumption variation information of the other processors may be distinguished from the suppression information, and different processes may be performed respectively. For example, after determining whether the event information is transmitted by another processor, whether the power consumption change information or the suppression information is determined according to an event flag in the event information may be determined. If the power consumption change information is the power consumption change information, the number of processors sending the power consumption change information is larger than or equal to K, and when the service priority of the processor 0 is lower, the power consumption of the processor 0 can be restrained within the restraining time period corresponding to the power consumption change information of the other set processors according to the set restraining proportion corresponding to the power consumption change information of the other processors; if the processor 0 is the suppression information and the service priority of the processor is lower than that of the processor sending the suppression information, the device can be set according to the suppression information of other processorsAnd performing power consumption inhibition on the processor 0 in the inhibition time period corresponding to the inhibition information of the other set processors by the fixed inhibition proportion. For example, if C is received ₁ And S4, if the service priority of the processor 0 is lower than that of the processor 1, performing power consumption inhibition on the processor 0 in the inhibition duration corresponding to the inhibition information of the other processors according to the set inhibition proportion corresponding to the inhibition information of the other processors.

In some embodiments, the process of recovering the processor from the power consumption suppression state to the normal operation state may be divided into a plurality of stages for recovery, for example, if the power consumption is suppressed by the clock frequency, the clock frequency may be first increased from the suppression value to the intermediate value and then from the intermediate value to the normal value, so as to avoid that the recovery is too fast and the power supply is increased.

S410, waiting for receiving the next event information.

After executing the step of suppressing the power consumption of the processor 0, or when it is determined that the power consumption of the processor 0 is not required at this time according to the above conditions, the trigger of the next actual information is waited, and then it is determined whether the power consumption of the processor 0 is required according to the above flow.

In some embodiments, the various set thresholds used in the process of generating the power consumption variation information and the various set numbers, set suppression ratios, set durations, and the like used by the suppression module in performing power consumption suppression may be preset and stored in a cache system or a corresponding register of the processor.

In other embodiments, the chip 100 may further include a configuration module (Configuration Module, CFG) separately provided for each of the N processors. The configuration module may be disposed inside the corresponding processor or may be disposed outside the corresponding processor. Fig. 5 shows a schematic structural diagram of a processor with a configuration module disposed therein, and as shown in fig. 5, the configuration module 140 is connected to the power consumption change monitoring module 110 and the suppression module 120, where the configuration module 140 may be used to save various set thresholds used in the process of generating the power consumption change information, and various set numbers, set suppression proportions, set durations, and the like used by the suppression module when performing power consumption suppression. The configuration module 140 may also adjust various setting thresholds used by the corresponding processor in generating the power consumption change information and/or various setting suppression ratios used in performing power consumption suppression, etc. according to the received suppression information of any one processor.

Although the functional units included in the processor are not shown in fig. 5, the processor shown in fig. 5 may include the functional units shown in fig. 2.

The meaning of some of the setting parameters configured in the configuration module 140 is exemplarily described below.

Cfg. thread_signal (S2): the immediate inhibition triggering event can be an S1 event of the processor, an S1/S2 event of the processor, or an S1/S2/S2 event of the processor; for example, if cfg. Thread_signal is the S1 event of the present processor, the suppression module immediately suppresses the power consumption of the present processor according to the set suppression proportion when receiving the S1 event of the present processor; if CFG.Throttle_Signal (S2) is an S1/S2/S2 event of the processor, the suppression module immediately suppresses the power consumption of the processor according to a set suppression proportion when receiving any power consumption change information of the processor;

cfg. Detector_time (P2): the state monitoring module detects the running state of the processor 0 according to the set DIDT detection period; for example, the set DIDT detection period may be 8cyc or 16cyc, etc.;

cfg.forcast_time (W1): predicting the time length of a window generated by a future power consumption change event, and predicting whether the power consumption change event will occur within the set window time length by a power consumption change prediction module; for example, the set window duration may be 8cyc or 16cyc, or may be 1/4 or 1/2 cycle of the resonant frequency of the processor;

Cfg. Detector_threshold (L1): a maximum slope threshold of the power consumption change slope, when the state monitoring module monitors that the power consumption change slope of the processor reaches the set maximum slope threshold, power consumption change monitoring information is generated;

cfg. Detector_threshold (L0): the minimum slope threshold of the power consumption change slope, when the state monitoring module monitors that the power consumption change slope of the processor is smaller than or equal to the set minimum slope threshold, the power consumption change monitoring information is canceled;

cfg. thread_m (R2): a range of functional units for limiting the power consumption suppression that the suppression module can perform;

cfg. thread_th (L2): setting the inhibition proportion corresponding to the processor, namely setting the inhibition proportion corresponding to the S1 event, the S2 event and the S3 event of the processor to be the same; the suppression module can suppress the power consumption of the processor according to the set suppression proportion when receiving the S1 event, the S2 event or the S3 event of the processor; for example, the set inhibition ratio may be 90%,80%,70%, or the like; wherein 90% means reducing the power consumption of the present processor to the current 90%.

Cfg. thread_time (T2): the suppression module suppresses the power consumption of the processor for a set suppression duration; matching with the set DIDT detection period; for example, the set inhibition period may be 8cyc or 16cyc, or the like;

Cfg. thread_th (cL 2): cascade suppression proportion, namely setting suppression proportion corresponding to other processors; when the suppression module receives power consumption change information or suppression information of other processors, the suppression module can suppress the power consumption of the processor according to a set cascade suppression proportion; for example, the set inhibition ratio may be 90%,80%,70%. 0%;0% means deferring the fetching and stopping the operation from the fetching unit;

cfg. thread_time (cT 2): the cascade inhibition time length is the set inhibition time length corresponding to other processors; when the suppression module receives power consumption change information or suppression information of other processors, the suppression module can suppress the power consumption of the processor in the set cascade suppression duration according to the set cascade suppression proportion; the cascading inhibition duration is matched with a set DIDT detection period; for example, the set inhibition period may be 8cyc or 16cyc, or the like;

cfg. casade_corenum (C2): the suppression module suppresses the power consumption of the processor when the suppression module performs the power consumption suppression judgment, namely the processor reaching the set number generates event information; for example, 0 indicates that 1 processor generates power consumption variation information to perform power consumption suppression, 1 indicates that 2 processors generate event information to perform power consumption suppression, 2 indicates that 3 processors generate event information to perform power consumption suppression, and 4 indicates that the processors are not cascade-connected to perform power consumption suppression as long as the present processor generates event information;

Cfg. casade_mask (M2): the suppression module performs suppression judgment, and does not participate in the event of judgment; for example, the S4 event may not participate in the determination, and the suppression module may exclude the processor that sent the S4 event when counting the number of processors that send the event information; each event 1bit.

In some embodiments, different suppression ratios may be set for different events, respectively, and illustratively, the following parameters may also be selectively set in the configuration module:

cfg. thread_casade_ths1 (L2S 1): the suppression module may perform power consumption suppression on the processor according to the set suppression proportion corresponding to the S1 event when the suppression module receives the S1 event of the processor, for example, the set suppression proportion corresponding to the S1 event may be 90%,80%,70%. 0%;

cfg. thread_casade_time_s1 (T2S 1): the suppression module can suppress the power consumption of the processor in the set suppression duration corresponding to the S1 event when receiving the S1 event of the processor; matching with the set DIDT detection period; for example, the set suppression period corresponding to the S1 event may be 8cyc or 16cyc, or the like;

Cfg. thread_casade_ths2 (l2s2): the suppression module may perform power consumption suppression on the processor according to the set suppression proportion corresponding to the S2 event when receiving the S2 event of the processor, for example, the set suppression proportion corresponding to the S2 event may be 90%,80%,70%. 0%;

cfg. thread_capacitor_time_s2 (T2S 2): the suppression module can suppress the power consumption of the processor in the set suppression duration corresponding to the S2 event when receiving the S2 event of the processor; matching with the set DIDT detection period; for example, the set suppression period corresponding to the S2 event may be 8cyc or 16cyc, etc.;

cfg. thread_casade_ths3 (l2s3): the suppression module may perform power consumption suppression on the processor according to the set suppression proportion corresponding to the S3 event when receiving the S3 event of the processor, for example, the set suppression proportion corresponding to the S3 event may be 90%,80%,70%. 0%;

cfg. thread_capacitor_time_s3 (T2S 3): the suppression module can suppress the power consumption of the processor in the set suppression duration corresponding to the S3 event when receiving the S3 event of the processor; matching with the set DIDT detection period; for example, the set suppression period corresponding to the S3 event may be 8cyc or 16cyc, etc.;

Cfg. thread_casade_ths1 (cL 2S 1): the cascade suppression proportion aiming at the S1 event, namely the set suppression proportion corresponding to the S1 event of other processors; when the suppression module receives the S1 event of other processors, the suppression module can suppress the power consumption of the processor according to the cascade suppression proportion aiming at the S1 event; for example, the cascade inhibition ratio for S1 event may be 90%,80%,70%. 0%;

cfg. thread_casade_time_s1 (cT 2S 1): the cascade inhibition duration aiming at the S1 event, namely the cascade inhibition duration corresponding to the S1 event of other processors; when the suppression module receives the S1 event of other processors, the suppression module can suppress the power consumption of the processor according to the cascade suppression duration aiming at the S1 event; for example, the cascade suppression duration for the S1 event may be 8cyc or 16cyc, etc.;

cfg. thread_casade_ths2 (cL 2S 2): the cascade suppression proportion aiming at the S2 event, namely the set suppression proportion corresponding to the S2 event of other processors; when the suppression module receives the S2 event of other processors, the suppression module can suppress the power consumption of the processor according to the cascade suppression proportion aiming at the S2 event; for example, the cascade inhibition ratio for the S2 event may be 90%,80%,70%. 0%;

Cfg. thread_capacitor_time_s2 (cT 2S 2): the cascade inhibition duration aiming at the S2 event, namely the cascade inhibition duration corresponding to the S2 event of other processors; when the suppression module receives the S2 event of other processors, the suppression module can suppress the power consumption of the processor according to the cascade suppression duration aiming at the S2 event; for example, the cascade suppression duration for the S2 event may be 8cyc or 16cyc, etc.;

cfg. thread_casade_ths3 (cL 2S 3): the cascade suppression proportion aiming at the S3 event, namely the set suppression proportion corresponding to the S3 event of other processors; when the suppression module receives the S3 event of other processors, the suppression module can suppress the power consumption of the processor according to the cascade suppression proportion aiming at the S3 event; for example, the cascade inhibition ratio for the S3 event may be 90%,80%,70%. 0%;

cfg. thread_capacitor_time_s3 (cT 2S 3): the cascade inhibition duration aiming at the S3 event, namely the cascade inhibition duration corresponding to the S3 event of other processors; when the suppression module receives the S3 event of other processors, the suppression module can suppress the power consumption of the processor according to the cascade suppression duration aiming at the S3 event; for example, the cascade suppression duration for the S3 event may be 8cyc or 16cyc, etc.;

Cfg. thread_casade_ths4 (cL 2S 4): the cascade suppression proportion aiming at the S4 event, namely the set suppression proportion corresponding to the S4 event of other processors; when the suppression module receives the S4 event of other processors, the suppression module can suppress the power consumption of the processor according to the cascade suppression proportion aiming at the S4 event; for example, the cascade inhibition ratio for the S4 event may be 90%,80%,70%. 0%;

cfg. thread_casade_time_s4 (cT 2S 4): the cascade inhibition duration aiming at the S4 event, namely the cascade inhibition duration corresponding to the S4 event of other processors; when the suppression module receives the S4 event of other processors, the suppression module can suppress the power consumption of the processor according to the cascade suppression duration aiming at the S4 event; for example, the cascade suppression duration for the S4 event may be 8cyc or 16cyc, etc.;

cfg. thread_casade_cfg_en (cEn): for the enabling of selectable event cascade inhibition configuration, if the enabling is performed, automatically transmitting the cascade inhibition proportion of the event to cL2/cT2 according to a cascade event scene, and providing the cascade inhibition proportion for an inhibition module for use;

cfg. thread_casade_ priority (cPrn): service priority of the processor; when one of the two processors needs to be restrained from operating normally, the processor with low service priority carries out power consumption restraint;

Cfg. Thread_casade_release (cTrn): when the processor is recovered from the inhibited state to the normal state, a plurality of stages of recovery are required to be added. Defaulting to 0, direct recovery. 1 to add a phase recovery (it is understood that the current recovery has a step in the middle of the peak) 2,3 and so on, it is avoided that the recovery is too fast to add a voltage drop.

The configuration module 140 is also responsible for adjusting various set thresholds used by the present processor in generating power consumption change information, various set suppression ratios used in performing power consumption suppression, and the like. Illustratively, the configuration module 140 may adjust various set thresholds used by the corresponding processor in generating the power consumption change information according to the received suppression information of any one of the processors; alternatively, the configuration module 140 may set the suppression ratio and the suppression duration for each type of the power consumption suppression process according to the received suppression information of any one of the processors; alternatively, the configuration module 140 may adjust various setting thresholds used by the corresponding processor in generating the power consumption change information and various setting suppression ratios and setting suppression durations used in performing power consumption suppression according to the received suppression information of any one of the processors.

For example, the suppression module 120 of processor 0 receives the S4 event of processor 2, and may transmit the S4 event of processor 2 to the configuration module 140 of processor 0. The configuration module 140 of the processor 0 receives the S4 event of the processor 2, which indicates that the processor 2 is currently in the power consumption suppression state, and may correlate to the power consumption change monitoring module 110 of the processor 0 modifying the generation threshold of the S1 event, and the power consumption change monitoring module 110 of the processor 0 monitors according to the modified threshold. When no power consumption suppressing action occurs for all processors, the generation threshold of the S1 event of the power consumption change monitoring module 110 resumes the default value of the configuration. The adjustment of the threshold value can be adjusted by software in a matching way, and can also be adjusted by combining with a hardware service classification processor in a matching way.

The chip provided by the embodiment of the application can mutually transmit the power consumption change information among the processors, and cooperatively perform power consumption inhibition, so that the power consumption inhibition of the processors can be performed more accurately and more timely, the voltage noise can be inhibited more effectively, and the performance damage to the processors is reduced.

In some embodiments, as shown in fig. 6, the chip provided in the embodiment of the present application may further include an arbitration module 150 and a suppression execution module 160 disposed in the power domain. The arbitration module 150 and the suppression execution module 160 are both power consumption adjustment modules. The arbitration module 150 may also be referred to as a power integrity arbitration (PI arbiter) module, and is configured to receive power consumption change information of a plurality of processors, where the power consumption change information of the processors may be sent to the arbitration module by the power consumption change monitoring module 110 of each processor. The arbitration module 150 may determine which processor or processors need to perform power consumption suppression according to the received power consumption variation information, and send a power consumption suppression instruction to the suppression execution module 160, where the power consumption suppression instruction includes a target processor that needs to perform power consumption suppression. The arbitration module 150 may also perform power consumption suppression on the processor with the lower service priority first when determining that power consumption suppression is required on a part of the processors.

The suppression execution module 160 is configured to perform power consumption suppression on the target processor according to the power consumption suppression instruction sent by the arbitration module 150. The suppression execution module 160 may also be referred to as a fast frequency division response (fast frequency scaling, FFS) module, and may perform frequency-reducing processing by using a fast frequency division response method, where the suppression execution module 160 may frequency-reduce all processors at the same time, or may frequency-reduce only a designated part of the processors, that is, the target processor determined by the arbitration module 150 to need to perform power consumption suppression.

In some embodiments, the chip provided by embodiments of the present application may further include a transient current monitoring (transient current monitor, TCM) module 170 disposed within the power domain. The transient current monitoring module 170 belongs to a power consumption monitoring module, and is configured to monitor a current in a power domain and generate voltage status indication information according to a change of the current, for example, the transient current monitoring module 170 may generate the voltage status indication information when detecting that a real-time current in the power domain reaches or approaches a peak current (peak current). The transient current monitoring module 170 sends the voltage status indication information to the arbitration module 150, so that the arbitration module 150 determines a power consumption suppression policy according to the voltage status indication information, and sends a power consumption suppression instruction to the suppression execution module 160 according to the determined power consumption suppression policy.

For example, in one embodiment, the arbitration module may determine the power consumption suppression policy based solely on the voltage status indication information sent by the transient current monitoring module 170; in another embodiment, the arbitration module may determine the power consumption suppression policy based only on the power consumption variation information sent by each processor; in another embodiment, the arbitration module may determine the power consumption suppression strategy based on power consumption variation information sent by the processors and voltage status indication information sent by the transient current monitoring module 170.

Fig. 7 is a flowchart illustrating a process for power consumption reduction by the arbitration module, as shown in fig. 7, which may include the steps of:

s701, receiving a trigger event.

The triggering event received by the arbitration module may be the power consumption change information sent by the power consumption change monitoring module of a certain processor, such as the S1 event, the S2 event or the S3 event; it may also be voltage status indication information sent by the transient current monitoring module.

S702, judging whether the triggering event is voltage state indication information; if yes, go to step S703; if not, go to step S704.

The arbitration module can determine whether the received trigger event is the voltage state indication information sent by the transient current monitoring module according to the event mark carried in the received trigger event or according to the interface receiving the trigger event.

S703, generating a power consumption suppression instruction according to the power consumption suppression policy for the voltage state instruction information.

If the voltage state indication information sent by the transient current monitoring module is received, the arbitration module can generate a power consumption inhibition instruction according to the set inhibition proportion and the set inhibition duration aiming at the voltage state indication information, and power consumption inhibition is carried out on all processors; or, the arbitration module may generate a power consumption suppression instruction according to the set suppression proportion and the set suppression duration for the voltage state indication information and the service priority of each processor, so as to suppress power consumption of part of the processors.

In some embodiments, the arbitration module may also adjust a threshold value used by each processor in generating the power consumption change information or a set throttling proportion and a set throttling duration used in the power consumption throttling process according to the received voltage state indication information.

S704, generating a power consumption suppression instruction according to a power consumption suppression strategy aiming at the power consumption change information.

If the received trigger event is not the voltage state indication information, but the power consumption change information sent by a certain processor is assumed to be the power consumption change information sent by the processor 1, the arbitration module can generate a power consumption suppression instruction according to the suppression proportion and the suppression duration set for the power consumption change information, and power consumption suppression is performed on the processor 1; or the arbitration module can generate a power consumption inhibition instruction according to the inhibition proportion and the inhibition duration set for the power consumption change information, and carry out power consumption inhibition on the processor with service priority lower than that of the processor 1; alternatively, the arbitration module may generate the power consumption suppression instruction according to the suppression ratio and the suppression duration set for the power consumption variation information, and perform power consumption suppression on the processor 1 and the processor with the service priority lower than that of the processor 1.

In some embodiments, when the arbitration module receives the power consumption variation information sent by the processor 1, the arbitration module may refer to the logic for performing power consumption inhibition determination by the inhibition module, determine whether the number of processors sending the power consumption variation information reaches the set number, and if so, determine which processors are subjected to power consumption inhibition according to the inhibition proportion and the set inhibition duration set for the power consumption variation information and the service priority of each processor sending the power consumption variation information, generate a power consumption inhibition instruction, and perform power consumption inhibition on the determined target processor.

In some embodiments, the arbitration module may further adjust a threshold value used by each processor in generating the power consumption change information or a set suppression proportion and a set suppression duration used in the power consumption suppression process according to the received power consumption change information of the processor.

S705, sending a power consumption suppression instruction to the suppression execution module.

The arbitration module sends the generated power consumption suppression instruction to the suppression execution module, and the suppression execution module suppresses the power consumption of the corresponding processor in a frequency-reducing mode and the like according to the power consumption suppression instruction.

After the arbitration module sends the power consumption suppression instruction to the suppression execution module, the next trigger event can be waited.

In some embodiments, when the arbitration module receives the power consumption change information sent by a certain processor, it can determine whether the power consumption change information is high-frequency event information, that is, power consumption change information caused by a ns-level power consumption change event; in the case of high-frequency event information, ns-level power consumption suppression can be immediately performed according to a power consumption suppression policy for ns-level power consumption change events. If the high-frequency event information is not the high-frequency event information, for example, the power consumption change information caused by the power consumption change event of the us level, the power consumption of the us level can be suppressed according to the power consumption suppression policy for the power consumption change event of the us level.

In the above embodiment, the power consumption change information obtained by the power consumption change monitoring module with high sampling rate inside the processor core and the voltage state indication information obtained by the transient current monitoring module with low sampling rate for the same power domain are controlled by the centralized management arbitration module, and then the frequency reduction control and the frequency recovery control are performed on the corresponding processor core by the inhibition execution module, so that the inhibition efficiency and the inhibition amplitude of the inhibition module of each processor can be supplemented, for example, larger-amplitude power consumption inhibition can be performed, and meanwhile, the optimal selection of multi-scenario energy efficiency can be provided.

In some embodiments, the suppression module may not be separately provided for each processor in the chip. As shown in fig. 8, the chip 100 may include a power consumption variation monitoring module 110, an arbitration module 150 and a suppression execution module 160, which are respectively provided for each of the N processors, and a transient current monitoring module 170. The power consumption change monitoring module 110 is configured to monitor an operation state of the corresponding processor, generate power consumption change information of the corresponding processor according to the operation state of the corresponding processor, and transmit the power consumption change information to the arbitration module 150. The transient current monitoring module 170 is configured to monitor a current in a power domain and generate voltage status indication information according to a change in the current. The transient current monitoring module 170 sends a voltage status indication to the arbitration module 150. The arbitration module 150 may determine a power consumption suppression policy according to the power consumption variation information of each processor and the voltage state indication information transmitted by the transient current monitoring module 170, and send a power consumption suppression instruction to the suppression execution module 160 according to the determined power consumption suppression policy, where the power consumption suppression instruction includes a target processor that needs to perform power consumption suppression, and further includes a suppression proportion and a suppression duration. The suppression execution module 160 suppresses the power consumption of the target processor for a suppression period according to the suppression proportion in the power consumption suppression instruction.

In the above embodiment, the power consumption suppression for the target processor is not in-core control, but voltage or frequency control is performed on the target processor by the out-of-processor suppression execution module 160. The external frequency-reducing voltage-reducing can inhibit the current of the processor to a better degree than the nuclear control effect with equal proportion of reducing performance.

In other embodiments, the transient current monitoring module may not be included in the chip. The arbitration module 150 may determine a power consumption suppression policy according to the power consumption variation information transmitted by the power consumption variation monitoring module 110 of each processor, and send a power consumption suppression instruction to the suppression execution module 160 according to the determined power consumption suppression policy.

In other embodiments, the power consumption variation monitoring module separately provided for each processor may not be included in the chip. The arbitration module 150 may determine a power consumption suppression policy according to the voltage status indication information transmitted by the transient current monitoring module 170, and send a power consumption suppression instruction to the suppression execution module 160 according to the determined power consumption suppression policy.

The embodiment of the present application also provides a voltage noise suppression method, which is performed by the chip in the above embodiment, based on the same inventive concept as the above embodiment. As shown in fig. 9, the method may include the steps of:

S901, acquiring power consumption change information of a plurality of processors in the same power domain;

s902, performing power consumption inhibition on part or all of the plurality of processors according to the power consumption change information of the plurality of processors.

In some embodiments, the voltage noise suppression method may be performed by any one of a plurality of processors in the same power domain, and the following description will take the example of the processor 0 as an example.

Processor 0 may obtain power consumption variation information for multiple processors within the same power domain by: monitoring the running state of the processor 0, and generating power consumption change information of the processor 0 according to the running state of the processor 0; receiving power consumption change information of a second processor sent by the second processor; the power consumption change information of the second processor is generated according to the operation state of the second processor; the second processor is any one of processors other than the processor 0.

Wherein the power consumption variation information of the processor 0 includes at least one of: when the power consumption change event of the processor 0 is monitored, the generated power consumption change monitoring information is generated; according to the running state of the processor 0 and the history state record of the power consumption change event, the power consumption change prediction information generated when the power consumption change event is predicted to occur in a set time window is predicted; when the processor 0 is monitored to receive the set target signal, the generated target signal indicates information.

The power consumption variation information of the processor 0 may be generated by the power consumption variation monitoring module of the processor 0 and transmitted to the suppression module of the processor 0. The suppression module of the processor 0 may receive the power consumption variation information of the processor 0 sent by the power consumption variation monitoring module of the processor 0, and receive the power consumption variation information of the second processor sent by the second processor.

Processor 0 may perform power consumption suppression for processor 0 based on the power consumption variation information of the plurality of processors. Illustratively, when the power consumption variation monitoring information of the processor 0 is acquired, the power consumption of the processor 0 is suppressed according to a set suppression ratio for the power consumption variation monitoring information; when the power consumption change prediction information of the processor 0 is obtained, if the power consumption change information sent by at least N processors is received within a set time period, performing power consumption suppression on the processor 0 according to a set suppression proportion aiming at the power consumption change prediction information; n is a set variable processor number threshold; when target signal indication information of the processor 0 is obtained, if power consumption change information sent by at least M processors is received within a set time period, performing power consumption inhibition on the processor 0 according to a set inhibition proportion aiming at the target signal indication information; m is a set variable processor number threshold.

When the power consumption change information of the second processor is received, if the power consumption change information sent by at least K processors is received within a set time period and the service priority of the processor 0 is lower than that of the second processor, performing power consumption inhibition on the processor 0 according to a set cascade inhibition proportion; k is a set threshold for the number of processors to be changed.

After the power consumption suppression of the processor 0, the suppression information may be transmitted to each processor other than the processor 0 by broadcasting. When the suppression information of the second processor is received, if the service priority of the processor 0 is lower than that of the second processor, the power consumption of the processor 0 is suppressed according to the set suppression proportion for the suppression information.

Optionally, the processor 0 may also adjust the threshold value used by the processor 0 in the power consumption monitoring process and/or the suppression proportion used in the power consumption suppressing process according to the received suppression information of any one of the processors.

In other embodiments, the voltage noise suppression method may be performed by the arbitration module in the foregoing embodiments, where the arbitration module may receive the power consumption variation information of the first processor sent by the first processor; the first processor is any one of a plurality of processors; alternatively, the arbitration module may receive the power consumption change information sent by the transient current monitoring module in the power domain; the power consumption change information is voltage state indication information generated by the transient current monitoring module according to current change in the power supply domain.

The arbitration module can determine a target processor needing power consumption suppression according to the received power consumption change information; and performing power consumption inhibition on the target processor through the inhibition execution module.

The steps of the method in the embodiments of the present application may be implemented by means of hardware, or may be implemented by means of a processor executing a computer program or instructions. The computer program or instructions may constitute a computer program product. Embodiments of the present application also provide a computer program product comprising computer-executable instructions. In some embodiments, the computer-executable instructions are for causing a computer to perform the functions of the method embodiments shown in fig. 4, 7, or 9.

The computer executable instructions may be stored in a computer readable storage medium, and embodiments of the present application also provide a computer readable storage medium having the executable instructions stored therein. In some embodiments, the computer-executable instructions are for causing a computer to perform the functions of the method embodiments shown in fig. 4, 7, or 9.

The computer readable storage medium provided by embodiments of the present application may be a random access memory (random access memory, RAM), a flash memory, a read-only memory (ROM), a programmable read-only memory (programmableROM, PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a register, a hard disk, a removable hard disk, a CD-ROM, or any other form of computer readable storage medium known in the art.

The computer-executable instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer program or instructions may be transmitted from one website site, computer, server, or data center to another website site, computer, server, or data center by wired or wireless means. The computer readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. that integrates one or more available media. The usable medium may be a magnetic medium, e.g., floppy disk, hard disk, tape; optical media, such as digital video discs (digital video disc, DVD); but also semiconductor media such as solid state disks.

In various embodiments of the application, where no special description or logic conflict exists, terms and/or descriptions between the various embodiments are consistent and may reference each other, and features of the various embodiments may be combined to form new embodiments based on their inherent logic. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion, such as a series of steps or elements. The method, system, article, or apparatus is not necessarily limited to those explicitly listed but may include other steps or elements not explicitly listed or inherent to such process, method, article, or apparatus.

Although the application has been described in connection with specific features and embodiments thereof, it will be apparent that various modifications and combinations can be made without departing from the spirit and scope of the application. Accordingly, the specification and drawings are merely exemplary of the arrangements defined in the appended claims and are to be construed as covering any and all modifications, variations, combinations, or equivalents that are within the scope of the application.

It will be apparent to those skilled in the art that various modifications and variations can be made to the present application without departing from the scope of the application. Thus, if such modifications and variations of the embodiments of the present application fall within the scope of the claims and the equivalents thereof, the present application is also intended to include such modifications and variations.

Claims

1. The chip is characterized by comprising a plurality of processors, a power consumption monitoring module and a power consumption adjusting module which are positioned in the same power domain;

the power consumption monitoring module is used for acquiring power consumption change information of the plurality of processors and transmitting the power consumption change information to the power consumption adjusting module;

the power consumption regulating module is used for carrying out power consumption inhibition on part or all of the processors according to the power consumption change information of the processors.

2. The chip of claim 1, wherein the power consumption variation information includes power consumption variation monitoring information; the power consumption monitoring module comprises a voltage monitoring module and/or a state monitoring module which are respectively arranged for each processor in the plurality of processors;

the voltage monitoring module of the first processor is used for monitoring whether voltage drop occurs in the first processor or not, and generating the power consumption change monitoring information when the amplitude of the voltage drop exceeds a set amplitude threshold value; the first processor is any one of the plurality of processors;

the state monitoring module of the first processor is used for determining a power consumption change slope according to the running state of the first processor, and generating the power consumption change monitoring information when the power consumption change slope reaches a set slope threshold of the first processor.

3. The chip of claim 2, wherein the power consumption variation information further includes power consumption variation prediction information; the power consumption monitoring module further comprises a power consumption change prediction module respectively arranged for each processor in the plurality of processors;

the power consumption change prediction module of the first processor is used for monitoring the running state of the first processor, predicting whether a power consumption change event will occur in a set time window according to the running state and a historical state record of the power consumption change event, and generating the power consumption change prediction information when the power consumption change event is predicted to occur.

4. A chip according to claim 2 or 3, wherein the power consumption variation information further includes target signal indication information; the power consumption monitoring module further comprises a signal monitoring module respectively arranged for each processor in the plurality of processors;

the signal monitoring module of the first processor is used for monitoring whether the first processor receives a set target signal or not and generating the target signal indication information when the first processor receives the set target signal.

5. The chip of any one of claims 2 to 4, wherein the power consumption adjustment module includes a suppression module provided separately for each of the plurality of processors;

the suppression module of the first processor is configured to receive the power consumption variation information of the first processor transmitted by the power consumption variation monitoring module of the first processor, receive the power consumption variation information transmitted by any one processor except the first processor in a broadcast manner, and perform power consumption suppression on the first processor based on the received power consumption variation information.

6. The chip of claim 5, wherein the suppression module of the first processor is specifically configured to:

When the power consumption change information of the first processor is received, and the power consumption change information of the first processor comprises power consumption change monitoring information, performing power consumption inhibition on the first processor according to a set inhibition proportion aiming at the power consumption change monitoring information.

7. The chip according to claim 5 or 6, wherein the suppression module of the first processor is specifically configured to:

when power consumption change information of the first processor is received and the power consumption change information of the first processor comprises power consumption change prediction information, if the power consumption change information sent by at least N processors is received within a set time period, performing power consumption suppression on the first processor according to a set suppression proportion aiming at the power consumption change prediction information; the N is a set variable processor quantity threshold; or alternatively, the process may be performed,

when power consumption change information of the first processor is received and the power consumption change information of the first processor comprises target signal indication information, if the power consumption change information sent by at least M processors is received within a set time period, performing power consumption inhibition on the first processor according to a set inhibition proportion aiming at the target signal indication information; and M is a set threshold value of the number of the change processors.

8. The chip according to any one of claims 5 to 7, wherein the suppression module of the first processor is specifically configured to:

when power consumption change information of a second processor is received, if the power consumption change information sent by at least K processors is received within a set time period, and the service priority of the first processor is lower than that of the second processor, performing power consumption inhibition on the first processor according to a set cascade inhibition proportion; the K is a set variable processor quantity threshold; the second processor is any one of processors other than the first processor.

9. The chip of any one of claims 5 to 8, wherein the suppression module of the first processor is further configured to:

transmitting suppression information to each processor except the first processor in a broadcasting mode after performing power consumption suppression on the first processor;

the suppression module of the first processor is further configured to: and receiving the inhibition information transmitted by any one processor except the first processor in a broadcast mode.

10. The chip of claim 9, wherein the suppression module of the first processor is further configured to:

When the suppression information of the second processor is received, if the service priority of the first processor is lower than that of the second processor, performing power consumption suppression on the first processor according to the set suppression proportion aiming at the suppression information.

11. The chip according to any one of claims 5 to 10, further comprising a configuration module provided separately for each of the plurality of processors;

the configuration module of the first processor is used for adjusting a threshold value used by the first processor in the process of generating the power consumption change information and/or a suppression proportion used in the process of performing power consumption suppression according to the received suppression information of any one processor.

12. The chip of any one of claims 1 to 11, wherein the power consumption adjustment module comprises an arbitration module and a suppression execution module within the power domain;

the arbitration module is used for receiving the power consumption change information of the plurality of processors sent by the power consumption monitoring module, and sending a power consumption inhibition instruction to the inhibition execution module according to the received power consumption change information, wherein the power consumption inhibition instruction comprises a target processor needing power consumption inhibition;

The inhibition execution module is used for carrying out power consumption inhibition on the target processor according to the power consumption inhibition instruction sent by the arbitration module.

13. The chip of any one of claims 1-12, wherein the power consumption monitoring module comprises a transient current monitoring module within the power domain;

the transient current monitoring module is used for monitoring current in the power domain and generating the power consumption change information according to the change of the current.

14. A voltage noise suppression method, comprising:

acquiring power consumption change information of a plurality of processors in the same power domain;

and performing power consumption inhibition on part or all of the plurality of processors according to the power consumption change information of the plurality of processors.

15. The method of claim 14, wherein the method is performed by a first processor, the first processor being any one of the plurality of processors; the obtaining the power consumption change information of the plurality of processors in the same power domain comprises the following steps:

monitoring the running state of the first processor and generating power consumption change information of the first processor according to the running state of the first processor; the power consumption variation information of the first processor includes: when the first processor is monitored to generate a power consumption change event, generating power consumption change monitoring information;

Receiving power consumption change information of a second processor sent by the second processor; the power consumption change information of the second processor is generated according to the operation state of the second processor; the second processor is any one of processors other than the first processor.

16. The method of claim 15, wherein the power consumption variation information of the first processor further comprises at least one of:

according to the running state of the first processor and the history state record of the power consumption change event, the power consumption change prediction information generated when the power consumption change event is predicted to occur in a set time window is obtained;

and when the first processor is monitored to receive the set target signal, the generated target signal indicating information is generated.

17. The method of claim 16, wherein the performing power consumption suppression on some or all of the plurality of processors according to the power consumption variation information of the plurality of processors comprises:

if the power consumption change monitoring information of the first processor is obtained, power consumption of the first processor is restrained according to a set restraining proportion aiming at the power consumption change monitoring information; or alternatively, the process may be performed,

If the power consumption change prediction information of the first processor is obtained and the power consumption change information sent by at least N processors is obtained in a set time period, performing power consumption suppression on the first processor according to a set suppression proportion aiming at the power consumption change prediction information; the N is a set variable processor quantity threshold; or alternatively, the process may be performed,

if the target signal indication information of the first processor is acquired and the power consumption change information sent by at least M processors is acquired in a set time period, performing power consumption inhibition on the first processor according to a set inhibition proportion aiming at the target signal indication information; and M is a set threshold value of the number of the change processors.

18. The method according to claim 15 or 16, wherein the performing power consumption suppression on some or all of the plurality of processors according to the power consumption variation information of the plurality of processors includes:

when power consumption change information of a second processor is received, if the power consumption change information sent by at least K processors is received within a set time period, and the service priority of the first processor is lower than that of the second processor, performing power consumption inhibition on the first processor according to a set cascade inhibition proportion; and K is a set threshold value of the number of the change processors.

19. The method of claim 17 or 18, wherein after the power consumption suppressing of the first processor, the method further comprises:

the suppression information is transmitted to each processor except the first processor by broadcasting.

20. The method of claim 19, wherein the method further comprises:

when the suppression information of the second processor is received, if the service priority of the first processor is lower than that of the second processor, power consumption suppression is carried out on the first processor according to the set suppression proportion aiming at the suppression information.

21. The method according to claim 19 or 20, characterized in that the method further comprises:

and adjusting a threshold value used by the first processor in the power consumption monitoring process and/or a suppression proportion used in the power consumption suppression process according to the received suppression information of any one processor.

22. The method of claim 14, wherein the method is performed by an arbitration module, the obtaining power consumption variation information for a plurality of processors within a same power domain, comprising:

Receiving power consumption change information of a first processor, which is sent by the first processor; the first processor is any one of the plurality of processors; or alternatively, the process may be performed,

receiving power consumption change information sent by a transient current monitoring module in the power domain; the power consumption change information is generated by the transient current monitoring module according to current change in the power supply domain.

23. The method of claim 22, wherein the performing power consumption suppression on some or all of the plurality of processors according to the power consumption variation information of the plurality of processors comprises:

determining a target processor needing power consumption suppression according to the received power consumption change information;

and performing power consumption inhibition on the target processor through an inhibition execution module.

24. A computer-readable storage medium, characterized in that computer-executable instructions for causing a computer to perform the method of any one of claims 14-23 are stored.

25. A computer program product comprising computer executable instructions for causing a computer to perform the method of any one of claims 14 to 23.