WO2023197163A1

WO2023197163A1 - Comparator and method of comparing voltages

Info

Publication number: WO2023197163A1
Application number: PCT/CN2022/086392
Authority: WO
Inventors: Takao Ishii
Original assignee: Huawei Technologies Co., Ltd.
Priority date: 2022-04-12
Filing date: 2022-04-12
Publication date: 2023-10-19

Abstract

A comparator comprises a differential amplifier having a first port (INN), a second port (INP), and an output port outputting a comparison result signal obtained by amplifying a result of subtracting a first signal from a second signal; a first capacitance element (C ₁) connected between the INN and a system input port (PIXEL) receiving a signal that is to be converted to the first signal; a second capacitance element (C ₂) connected between the INN and a selection node (SN); and a AZ switch (SW _AZN) to switch between a connected state in which the INN and the output port are connected and a disconnected state; wherein in response to the SW _AZN switching from the connected state to the disconnected state, the comparator transitions from a first state, in which the SN receives a first voltage, to a second state, in which the SN receives a second voltage (V _bst).

Description

COMPARATOR AND METHOD OF COMPARING VOLTAGES

TECHNICAL FIELD

Embodiments described herein relate to a comparator and a method of comparing voltages.

BACKGROUND ART

It is desirably to design mobile terminals such as smartphones and tablets, to have low power consumption because of their requirements for long time operations. The low power consumption also helps to suppress the generation of thermal radiation, which may cause performance degradation such as a noise, a dark current or the like.

Since most of the mobile terminals include one or more image sensors, the image sensor, particularly an analog to digital converter (ADC) also should operate with low power consumption. More specifically, a comparator in the ADC should operate with low power consumption.

Since the power consumption is proportional to a power supply voltage, one solution to reducing the power consumption is to lower the power supply voltage and cause to operate with the lower voltage. However, when simply lowering the power supply voltage, an acceptable range of input voltage also shrinks in the ADC, particularly in the comparator.

RELATED-ART DOCUMENTS

Patent Document: United State Patent No. 9774811

SUMMARY OF THE INVENTION

An embodiment of the invention as described in the present application provides a comparator improved to extend an acceptable range of input voltages.

An embodiment of the invention as described in the present application provides an analog to digital converter including such a comparator.

An embodiment of the invention as described in the present application provides a CMOS image sensor including such an analog to digital converter.

An embodiment in one aspect described herein provides a comparator comprising:

a differential amplifier having a first port (INN) that receives a first signal, a second port (INP) that receives a second signal, and an output port that outputs a comparison result signal obtained by amplifying a result of subtracting the first signal from the second signal;

a first capacitance element (C ₁) connected between the first port (INN) and a system input port (PIXEL) receiving a signal to be converted to the first signal;

a second capacitance element (C ₂) connected between the first port (INN) and a selection node (SN) ; and

an AZ switch (SW _AZN) to switch between a connected state in which the first port (INN) and the output port are connected and a disconnected state in which they are disconnected;

wherein in response to the AZ switch (SW _AZN) switching from the connected state to the disconnected state, the comparator transitions from a first state, in which the selection node (SN) receives a first voltage, to a second state, in which the selection node (SN) receives a second voltage (V _bst) .

BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 conceptually illustrates an image sensor according to an embodiment.

Figure 2 illustrates a diagram explaining an ADC in a CMOS image sensor.

Figure 3 illustrates a diagram explaining an operation range of a differential amplifier.

Figure 4 illustrates a structure with a capacitance divider.

Figure 5 illustrates a structure which boosts of an input range.

Figure 6 illustrates a flow chart of operations according to an embodiment.

Figure 7 illustrates several kinds of signal wave forms to explain operations according to an embodiment.

Figure 8 illustrates a variation using a symmetric structure.

Figure 9 illustrates a variation which can switch capacitors.

Figure 10 illustrates the architecture of a mobile terminal according to an embodiment.

Mode for Carrying Out the Invention

Hereinafter, embodiments will be described with reference to accompanying drawings in the context of following sections. Through the drawings, the same reference number or the reference symbol is assigned to the same element. For the purpose of simple explanation, redundant explanations will be omitted.

1. System Overview

2. Basic Structure

3. Basic Operations

4. Capacitance Attenuator

5. Input Range Boosting

6. Variations

6.1 Symmetric Structure

6.2 Capacitor Switching

7. System Architecture

Partitions in the following description are not essential for the embodiments. Descriptions in two or more partitions may be combined, and descriptions in one partition may be applied to descriptions in another partition (unless contraindicated) , as appropriate.

1. System Overview

Figure 1 conceptually illustrates an image sensor 10 according to an embodiment. The image sensor 10 may be, for example, a CMOS image sensor. However, the image sensor may be any sensor array (e.g., finger print sensors) that includes an array of sensor elements, each of which converts physical quantity into an electric signal, and an element reading out their output signals. In Figure 1, a plurality of pixels 11, a row decode circuit 20, a read-out circuit 13, a power supply 14 and a processor 15 are depicted. Figure 1 illustrates elements which relate to the following description. However, actually there may exist the other elements.

Each pixel of the plurality of pixels 11 is designated by means of a scan line G _i connected to the pixel and a data line D _j connected to the pixel. “i” is an index used to designate the scan line, which is an integer equal to or more than 1 and equal to or less than M, and “j” is an index used to designate the data line, which is an integer equal to or more than 1 and equal to or less than N (the same shall apply hereafter) .

The processor 15 controls the row decode circuit to drive (activate or deactivate) the plurality of scan lines G ₁-G _M connected to the pixels 11. Since one scan line is connected to a plurality of pixels 11 (N pixels in Figure 1) , the plurality of pixels may be designated at once by designating one scan line.

The processor 15 controls the read-out circuit 13 to read data from the plurality of pixels 11 using the plurality of data lines D ₁-D _N connected to the pixels 11.

The read-out circuit 13 includes a plurality of analog to digital converters ADC ₁-ADC _N, each of which is connected to the data line D _j. The plurality of analog to digital converters ADC ₁-ADC _N operate in parallel. Each of the analog to digital converters ADC _j operates in a time division multiplexed manner with respect to the M pixels; i.e., the ADC _j repeats an analog to digital conversion M times, in which the conversion includes reading from one pixel 11 the data being an analog voltage signal, and outputting a corresponding digital signal.

The processor 15 controls the power supply 14 to supply a predetermined voltage to the plurality of pixels 11 and the plurality of analog to digital converters ADC ₁-ADC _N.

N and M may be any suitable positive integer. For example, N and M may be hundreds, thousands or the like.

2. Basic Structure

Figure 2 illustrates the analog to digital converter (ADC) in the CMOS image sensor. Figure 2 illustrates some of representative elements relating to the pixel 11 and the analog to digital converter ADC _j. In Figure 2, a pixel source follower part 21 relating to the pixel 11, a differential amplifier 22 (which may be referred to as “comparator 22” ) , and a ramp signal generator 23 are depicted.

The pixel source follower part 21 includes a photodiode PD which an anode is connected to a low power supply V _SS (for example, V _SS may be GND) ; a transfer transistor Tr1 connected between a cathode of the PD and a floating diffusion layer (FD) ; and a reset transistor Tr2 connected between the floating diffusion layer and a high power supply V _DD. Although only one PD is depicted, a plurality of PDs and Tr1 may be connected to the floating diffusion layer.

The source follower part 21 further includes an amplification transistor Tr3 forming a source follower in which a gate receiving an input voltage is connected to the floating diffusion layer; a selection transistor Tr4 which controls a connection between Tr3 and output signal lines (the data line D _j in Figure 1) ; and a bias transistor Tr5 which supplies a source follower bias current to the output signal line. Herein Tr1 to Tr4 correspond to a unit pixel 11, and plural unit pixels 11 are connected to one output signal line. Generally, one Tr5 is connected to one output signal line.

The amount of photo electrons generated by the photodiode PD is generally proportional to the amount of received light, namely product of illumination on the PD and exposure time. The transfer transistor Tr1 regulates the flow of the photo electrons to the node FD. The gate of Tr4 is connected to the scan line G _i depicted in Figure 1. The Tr4 is connected to the data line D _j depicted in Figure 1. An output port PIXEL of the pixel source follower part 21 located between Tr4 and Tr5 may be referred to as one of system input ports of the differential amplifier 22. The bias transistor Tr5 is shared among plural pixels connected to the same data line D _j.

The differential amplifier 22 includes a pair of load transistors Tr6, Tr7, the sources of which are connected to the high power supply V _DD; a pair of input transistors Tr8, Tr9; and a bias transistor Tr10, which a drain is connected to the respective sources of Tr8 and Tr9 and which supplies a bias current. The drains of Tr6 and Tr7 are connected to the drains of Tr8 and Tr9, respectively. The source of Tr10 is connected to the low power supply V _SS. The drain of Tr6 and the drain of Tr8 are connected to the output port of the differential amplifier 22. In the illustrated example, common power supplies V _DD and V _SS are used for the pixel source follower part 21 and the differential amplifier 22. However, in the another embodiment, different power supplies may be used.

The gate of Tr8 is connected to one input port INN of the differential amplifier 22. The INN is connected to the output port of the pixel source follower part 21 (or one of system input ports) PIXEL via a capacitor C _N. The gate of Tr9 is connected to the other input port of the differential amplifier 22. The INP is connected to the output port RAMP via a capacitor C _P. The RAMP may be referred to as the other of system input ports of the differential amplifier 22.

An auto zero (AZ) switch SW _AZN is located between one input port INN and the output port OUT. The SW _AZN switches between a connected state in which the INN and the output port of the differential amplifier are connected and a disconnected state in which they are disconnected. Also, an AZ switch SW _AZP is located between the other input port INP and the drain of Tr7 (the drain of Tr9) . The SW _AZP switches between a connected state in which the INP and the drain of Tr7 (and the drain of Tr9) are connected and a disconnected state in which they are disconnected. The Tr10 functions as a constant current source. For more detail on the Auto Zero Technique, please refer to:

https: //www. analog. com/jp/technical-articles/to-chop-or-auto-zero-that-is-the-question. html

The ramp signal generator 23 generates a reference signal which is used for a comparison operation which is performed in a single slope type analog to digital conversion. In other words, the ramp signal generator 23 generates a base signal which is compared with an analog voltage signal. A digital value corresponding to an analog input may be obtained by means of a counter circuit by measuring a timing at which the ramp signal level and the analog signal level cross. The ramp signal is a signal having a predetermined waveform. For example, the ramp signal may be generated by means of a digital to analog converter (DAC) which the count value of the counter circuit is used as its digital input. As an example, at least a portion of the ramp signal generator 23 may be provided in the read-out circuit 13, the power supply 14 and/or the processor 15.

The polarity combination of Tr1 to Tr9 is only one of examples, other polarity may be used in the other embodiment.

3. Basic Operations

Generally, the ADC depicted in Figure 2 receives the analog voltage signal of the pixels, amplifies the voltage between the pair of input nodes (INN, INP) , and outputs the digital signal as the comparison result, from the output port OUT.

Hereinafter, operations are described in detail.

Firstly, the AZ switches SW _AZN and SW _AZP are closed, the voltage at one input port INN is reset equal to the voltage of the drain voltage of Tr6, the voltage at the other input port INP is reset equal to the gate and drain voltage of Tr7. As a result, the drain voltage of Tr6 and the voltages of the two input ports INN and INP are reset to the voltage corresponding to the drain voltage of Tr7. At this time, the floating diffusion layer which is the input of the pixel source follower is pre-charged to a known level (e.g., V _DD) by toggling the reset transistor Tr2. “Toggling” refers OFF-ON-OFF operations, which may also be referred to as “switching” . In the situation that Tr1 and Tr2 are tuned off, Tr4 is turned on, the analog voltage signal indicative of a base level is input to one input port INN, thus the voltage of the input port INN becomes a corresponding voltage.

Then, the AZ switches SW _AZN and SW _AZP are opened, a measurement of the base level (or a baseline) of the pixel is started. The base line level is measured in advance because the pre-charge voltage may include error components such as kTC noise of the diffusion capacitance, feedthrough due to the switching of the reset transistor Tr2 or the like.

The ramp signal is input to the other input port INP. Generally, the ramp signal changes from a high level to a low level over time. The changing step width is determined by a resolution of the analog to digital conversion. It is possible to determine the voltage of the base level by measuring a timing when the voltage level of the analog voltage signal and the voltage level of the ramp signal become same.

Next, the voltage corresponding to the charge stored in the pixel is measured. Specifically, the photo electrons stored in the photodiode PD depending on an amount of light is transferred to the node FD by toggling (or switching) Tr1, and the analog voltage signal having a magnitude corresponding to the amount of light is generated according to a proportionality coefficient which is inverse of the capacitance of the node FD. This is input to one input port INN through the pixel source follower part 21, and the voltage at the input port becomes a corresponding voltage. This voltage is generated by adding the base level to the voltage corresponding to the amount of the photo electrons from the pixel. In case the electrons are signal charge like this example, usually, the voltage corresponding to the amount of photoelectron falls below the base voltage.

The ramp signal is input to the other input port INP. The ramp signal changes from a high level to a low level over time. The changing step width is determined by a resolution of the analog to digital conversion. The changing range of the ramp signal (the range between the high level and the low level) may or may not be same as the range used in the base level measurement. In any event, it is determined such that the base level and an input voltage (the voltage at the input port INN) are within their ranges of the ramp signal, respectively. It is possible to determine the pixel voltage corresponding to the state of the photodiode PD by measuring a timing when the voltage level of the analog voltage signal and the voltage level of the ramp signa become same.

In this example, the base level corresponds to a higher limit value of the ADC’s acceptable voltage, and it is assumed that the input voltage within the acceptable range is equal to or less than the base level. However, it is not essential for the embodiments. For example, in case a polarity of the signal charge is different (e.g., in case holes are stored) , magnitude relations of the voltages are all reversed, but such cases are also included in the scope of this application.

After the pixel voltage is measured for one pixel, the pixel voltage is similarly measured for another pixel that is connected to the same data line. The pixel voltages for all pixels (M pixels in Figure 1) connected to the same data line are sequentially measured.

When the differential amplifier 22 appropriately operates as an amplifier, as described above, respective transistors Tr6 –Tr10 operate in their saturation region. Thus, in order to realize such operations, some voltages are applied to the gate, source and drain of respective transistors.

Figure 3 illustrates a diagram for use in explaining an operation range of the differential amplifier 22 comprising the transistors Tr6 –Tr10. Supposing that respective threshold voltages of the transistors Tr6, Tr7 are V _th, p, respective pinch-off voltages between the source and the drain are V _dsat, p, respective threshold voltages of the transistors Tr8, Tr9 are V _th, n, respective pinch-off voltages between the source and the drain are V _dsat, n, a pinch-off voltage between the source and the drain of the transistor Tr10 is V _dsat, trail.

As described above, two input ports INN and INP (the gates of Tr8 and Tr9) are set to the drain voltage (V _DD -V _dsat, p -V _thp) (initial state) by closing the AZ switch SW _AZN, then change according to the amount of change of the gate voltages of Tr8 and Tr9, after opening the AZ switches, from the initial state. The voltage of one input port INN (an input voltage V _IN) is equal to or less than the initial voltage (the base level) . On the other hand, since Tr8, Tr9 and Tr10 are present, the input voltage is needed to be greater than (V _dsat, tail + V _dsat, n + V _th, n) . As described above, in this example it is assumed that the base level corresponds to the higher limit of the ADC’s acceptable voltage, and that the input voltage within the acceptable range is equal to or less than the base level. Thus, the input voltage V _IN at the input port INN has to satisfy the following inequality.

(V _DD -V _dsat, p -V _thp) > V _IN > (V _dsat, tail + V _dsat, n + V _th, n) ... (Formula 1)

As an example, if V _DD = 5 [V] , V _thp = V _thn = 0.5 [V] , and V _dsat, n = V _dsat, p =V _dsat, tail = 0.2 [V] , then the range of the input voltage V _IN is as follows:

4.3 [V] > V _IN > 0.9 [V] Therefore, the ADC can measure the input voltage V _IN within the range of about 3.4 [V] that satisfies this inequality.

If V _DD = 1.8 [V] due to the low voltage operation, then the range of the input voltage V _IN is as follows:

1.1 [V] > V _IN > 0.9 [V] Therefore, the ADC can measure the input voltage V _IN within the range of about only 0.2 [V] that satisfies this inequality. The ADC including a comparator according to the embodiment described below can measure the voltages in a wider range.

4. Capacitance Attenuator

Figure 4 illustrates an example in which a structure using a capacitance attenuator (capacitance divider) is added to the basic structure depicted in Figure 2. As shown by the broken line box in a pixel side (P-SIDE) , a first capacitance element (C ₁) is connected between one system input port PIXEL and the first input port INN. A second capacitance element (C ₂) is connected between the first input port INN and a selection node SN. Although it is not essential, a structure similar to that on the pixel side (P-SIDE) also may exist on the ramp signal side (R-SIDE) .

The selection node SN is connected to one system input port PIXEL or to the low power supply V _SS (e.g., GND) by means of a switch depending on a mode of operations. For example, the selection node SN may be connected to the system input port PIXEL to measure voltages in a relatively narrow range when the number of photo electrons stored in the pixel may be small due to a low illuminance environment, short exposure time or the like. For convenience, this operation mode may be referred to as a high gain operation mode or a small full scale range mode. When the number of photo electrons stored in the pixel are large, the selection node SN is connected to the low power supply V _SS to measure voltages in a relatively wide range. For convenience, this operation mode may be referred to as a low gain operation mode or a large full scale range mode. Switching of the selection node SN may be performed based on a sensitivity setting of a camera system (such as sensitivity settings of ISO100, ISO200, etc. ) , exposure time setting or the like.

In the following descriptions, we will mainly discuss operations in the low gain operation mode or the large full scale range mode. Thus, when viewed from one system input port PIXEL, it can be considered that the first capacitance element C ₁ and the second capacitance element C ₂ are connected in series. If the voltage at one system input port PIXEL is V _IN, because of the capacitance voltage divider, the voltage at the first input port INN can be expressed as follows:

C ₁/ (C ₁ + C ₂) V _IN = (1 + (C ₂/C ₁) ) ^-1 V _IN ... (Formula 2)

If C ₁ = C ₂, the voltage at the first input port INN is V _IN/2 which is smaller than the voltage V _IN at the system input port. In other words, if a higher voltage limit at the first input port INN is V _max, a higher voltage limit at one system input port PIXEL can be 2V _max.

In this way, by adding the second capacitance element C ₂, the acceptable voltage range at one system input port PIXEL can be increased by a factor (1 + (C ₂/C ₁) ) . However, it should be noted that if a noise component is present in the voltage signal, the noise component will also be increased. This is described in later.

5. Input Range Boosting

Figure 5 illustrates an example in which a structure which boosts an input range is added. In the example depicted in Figure 4, the selection node SN was always connected to the low power supply V _SS. In the example depicted in Figure 5, the selection node SN is connected to a boost voltage supplier BOOST. As an example, at least a portion of the boost voltage supplier BOOST may be provided in the read-out circuit 13, the power supply 14 and/or the processor 15 (Figure 1) . As described above, the AZ switch SW _AZN switches between the connected state in which the first input port INN and the drain of Tr8 are connected and the disconnected state in which they are disconnected.

In response to the AZ switch SW _AZN switching from the connected state to the disconnected state, the boost voltage supplier BOOST transitions from supplying a first voltage to the selection node SN to supplying a second voltage V _bst to the selection node SN. The first voltage may be, for example, the low power supply voltage V _SS. The second voltage V _bst may be a constant voltage, such as 1 [V] . The boost voltage supplier BOOST may be implemented by means of a buffer circuit.

Hereinafter, operations in the structure depicted in Figure 5 will be described with reference to Figures 6-7. Figure 6 illustrates a flow chart of operations according to the embodiment. Figure 7 illustrates several kinds of signal wave forms for use in explaining operations according to the embodiment. It should be noted that the waveforms depicted in Figure 7 are for explaining an outline of the operations, and are not intended to depict accurate voltage levels.

As described with reference to the basic structure (Figure 2) , the analog to digital converter ADC _j measures the pixel voltage for one pixel, then measures the pixel voltage for another pixel connected to the same data line, and repeats the measurements in the same manner. For convenience, the measurement period for measuring the pixel voltage for one pixel will be described separately for periods of S0-S4 as depicted in the lower part in Figure 7. The S0-S4 correspond to respective steps in Figure 6.

At step S0 in Figure 6, the AZ switches SW _AZN and SW _AZP (Figure 5) are closed and the voltage at the input port INN is reset equal to the drain voltage of Tr6. Similarly, the voltage at the input port INP is reset equal to the drain voltages of Tr7, Tr9. In Figure 7, the states of the AZ switches SW _AZN and SW _AZP are depicted in common as “AZ SW” and both operate in phase. At this time, the floating diffusion layer, which is the input of the pixel source follower, is pre-charged to a known level (e.g., V _DD) by toggling the reset transistor Tr2. In the situation that Tr1 and Tr2 are tuned off, Tr4 is turned on, the analog voltage signal indicative of a base level is input to one input port INN, thus the voltage of the input port INN becomes a corresponding voltage V _r.

At step S1 in Figure 6, the AZ switches SW _AZN and SW _AZP are opened, a measurement of the base level (or a baseline) of the pixel is started. The base line level is measured in advance because the pre-charge voltage may include error components such as kTC noise of the diffusion capacitance, feedthrough due to the switching of the reset transistor Tr2 or the like.

At the timing t = t _g, the boost voltage supplier BOOST transitions from the first state supplying the first voltage to the selection node (SN) to the second state supplying the second voltage to the selection node SN. In the illustrated example, the first voltage is the low power supply voltage V _SS and the second voltage is V _bst. As an example, the V _bst may be a constant voltage of 1 [V] , but may be a high power supply voltage V _DD such as 2.8 [V] or 1.8 [V] .

When the voltage at the selection node SN changes from the first voltage V _SS to the second voltage V _bst at the timing t = t _g, the voltage at the input port INN raises by (1 + (C ₁/C ₂) ) ^-1 V _bst. This is because when viewed from the selection node SN that is in a high potential, it can be considered that the first capacitance element C ₁ is a ground capacitance element of the C ₁-C ₂ serial circuit. Thus, the voltage at the input port INN can be written as:

V _r + (1 + (C ₁/C ₂) ) ^-1 V _bst ... (Formula 3)

When discussing the formula (Formula 2) , the selection node SN was connected to the low power supply voltage V _SS. It should be noted that when the capacitance element C ₁ and C ₂ are viewed from the system input port PIXEL, the second capacitance element C ₂ is a ground capacitance element of the C ₁-C ₂ serial circuit.

At step S1, the ramp signal is input to the other input port INP. The ramp signal generally remains a high level for a certain interval (S1) , then gradually decreases to a low level (S2) . The ramp signal maintains the high level for the time interval S1. The magnitude of the level is dependent on the object to be measured. In this example, the voltage at the input port INN increases as shown in (Formula 3) , therefore “high level” in the ramp signal needs to be a higher level than such an increased voltage.

At step S2, the ramp signal generally gradually changes from the high level to the low level over time. The changing step width is determined by a resolution of the analog to digital conversion. It is possible to determine the voltage of the increased base level (Formula 3) by measuring a timing t _r when the voltage level of the analog voltage signal and the voltage level of the ramp signal become same.

At step S3, the voltage corresponding to the charge stored in the pixel is measured. Specifically, the photo electrons stored in the photodiode PD depending on an amount of light is transferred to the node FD by toggling (or switching) Tr1, and the analog voltage signal having a magnitude corresponding to the amount of light is generated according to a proportionality coefficient which is inverse of the capacitance of the node FD. This is input to one input port INN through the pixel source follower part 21, and the voltage at the input port becomes a corresponding voltage. This voltage is generated by adding the base level to the voltage corresponding to the amount of the photo electrons from the pixel. In case electrons are signal charge like this example, usually, the voltage corresponding to the amount of photoelectron falls below the base voltage.

At the beginning of the time interval S3, the pixel waveform (PIXEL) largely and transiently changes until it stabilizes, this is because there are capacitive coupling of Tr1, Tr3 and Tr4 accompanying the photon electrons transfer. In Figure 7, a solid line waveform for “PIXEL” corresponds to a case that the photo current is minimum (MIN) while a broken line waveform corresponds to a case that the photo current is maximum (MAX) . Thus, actually, a single waveform will be drawn between the solid line and the broken line.

In steps S3 and S4, similar to the steps S1 and S2, the ramp signal that is input to the other input port INP generally remains at a high level for a certain interval (S3) , then gradually decreases to a low level over time (S4) . The ramp signal maintains the high level for the time interval S3. The magnitude of the level is dependent on the object to be measured. In this example, “high level” in the ramp signal is set similar to “high level” that is set in step S1.

At step S4, the ramp signal generally gradually changes from the high level to the low level over time. The changing step width is determined by a resolution of the analog to digital conversion. The changing range of the ramp signal (the range between the high level and the low level) may or may not be same as the range used in the base level measurement. In any way, it is determined such that the base level and the input voltage (the voltage at the input port INN) are within their ranges of the ramp signal, respectively. It is possible to determine the pixel voltage corresponding to the state of the photodiode PD by measuring a timing when the voltage level of the analog voltage signal and the voltage level of the ramp signal become same (a some timing between t _A and t _B) .

As an example, the measurement period for measuring the pixel voltage for one pixel (a time interval from the start of S0 to the end of S4) may be about 10μs, a time interval from the start of S0 to the end of S2 may be about 5μs, and a time interval from the start of S3 to the end of S4 may be about 5μs. However, these numerical values are provided merely as an example, other numerical values may be used in another embodiment.

In the embodiment, a higher limit value of the acceptable voltage corresponds to the base level, and the voltage within the acceptable range is equal to or less than the base level. Thus, the larger the base level, the wider the acceptable voltage range. In the embodiment, as described with reference to (Formula 3) , the increased base level is expressed as follows:

V _r + (1 + (C ₁/C ₂) ) ^-1 V _bst

On the other hand, as described in “4. Capacitance Attenuator” , by adding the second capacitance element C ₂, the acceptable voltage range at the system input port PIXEL can be increased by the factor (1 + (C ₂/C ₁) ) . Applying this to the increased base level described above, the acceptable voltage range can be written as:

(1 + (C ₂/C ₁) ) × (V _r + (1 + (C ₁/C ₂) ) ^-1 V _bst)

=(1 + (C ₂/C ₁) ) × V _r + (1 + (C ₂/C ₁) ) × (1 + (C ₁/C ₂) ) ^-1 V _bst

=(1 + (C ₂/C ₁) ) × V _r + (C ₂/C ₁) V _bst ... (Formula 4)

The first term of the last formula corresponds to the contribution which was explained in “4. Capacitance Attenuator” , i.e., the contribution by adding the capacitance element C ₂. The second term corresponds to a contribution caused by the boosting with the second voltage V _bst. In this way, the acceptable voltage range may be widely extended from V _r.

By the way, with regard to the ADC depicted in Figure 5, the dynamic range may be evaluated as a ratio of an acceptable voltage range to a reference noise.

Dynamic range = (Acceptable voltage range) / (Reference noise)

For example, the dynamic range in the basic structure depicted in Figure 2 may be evaluated as follows:

V _r/V _n ... (Formula 5)

where, V _r represents the base level in the basic structure (Figure 2) , and V _n represents the reference noise.

Next, we will consider the dynamic range for the structure in which the capacitance element C ₂ is added. In this case, the base level could be increased by a factor (1 + (C ₂/C ₁) ) . However, the reference noise is also increased by the same factor (1 + (C ₂/C ₁) ) . Therefore, the dynamic range is expressed as follows:

(1 + (C ₂/C ₁) ) V _r / [ (1 + (C ₂/C ₁) ) V _n] = V _r/V _n ... (Formula 6)

This results in the same formula as (Formula 5) . It is difficult to improve the dynamic range by merely adding the grounded capacitance element C ₂ to the basic structure (Figure 2) .

In this regard, according to the embodiment in which the boost voltage supplier BOOST is added, the base level may be improved as shown in (Formula 4) , so the dynamic range can be written as follows:

[ (1 + (C ₂/C ₁) ) ×V _r + (C ₂/C ₁) V _bst] / [ (1 + (C ₂/C ₁) ) V _n] = V _r/V _n + (C ₂/C ₁) (1 + (C ₂/C ₁) ) ^-1 (V _bst/V _n) ... (Formula 7)

The first term in the last formula corresponds to the dynamic range in the basic structure. The second term corresponds to an effect improved according to the embodiment.

According to the embodiment, the dynamic range can be effectively extended.

Since the first capacitance element C ₁ plays a major role in receiving the voltage from the pixel (Figures 4-5) , a large value of the capacitance C ₁ may be preferable in terms of a signal to noise ratio (SNR) . On the other hand, according to the formula (Formula 4) indicative of the acceptable voltage range and the formula (Formula 7) indicative of the dynamic range, a large value of the capacitance C ₂ may be preferable in terms of increasing the acceptable voltage level and/or the dynamic range. In an actual application, C ₁ and C ₂ may be appropriately determined while considering these trade-offs. Thus, the capacitance ratio between the first capacitance element C ₁ and the second capacitance element C ₂ may be fixed or changed depending on the situation.

With regard to the acceptable voltage range, in the basic ADC structure (Figure 2) , as described in “3. Basic operations” , the input voltage VIN at the input port INN has to satisfy the following inequality:

1.1 [V] > V _IN > 0.9 [V] The acceptable voltage range V _r was 0.2 [V] . Where, it is assumed that V _DD = 1.8 [V] , V _thp = V _thn = 0.5 [V] , V _dsat, n = V _dsat, p = V _dsat, tail = 0.2 [V] .

According to (Formula 4) in the embodiment, the acceptable voltage range is:

(1 + (C ₂/C ₁) ) ×V _r + (C ₂/C ₁) V _bst

= 2×V _r + V _bst

= 1.4 [V] Where, it is assumed that C ₁ = C ₂, V _bst = 1 [V] . Unlike the basic structure, it is possible to measure voltages in the wide range over 1 [V] .

Supposing that the input reference noise is V _n = 100 [μV] , the dynamic range in the basic structure can be calculated as follows:

20 log ₁₀ (V _r/V _n)

= 20 log ₁₀ (0.2 [V] /100 [μV] )

= 66 dB

In this regard, the improved contribution from the embodiment can be calculated as follows according to the second term in (Formula 7) :

20 log ₁₀ [ { (1+ (C ₂/C ₁) ) V _r + (C ₂/C ₁) V _bst} / (1 + (C ₂/C ₁) ) V _n) ] = 20 log ₁₀ [V _r/V _n + (1/2) (V _bst/V _n) ]

= 20 log ₁₀ [0.2 [V] /100 [uV] + (1/2) (1 [V] /100 [μV] ) ]

～ 77 dB

Where, it is assumed that C ₁ = C ₂, V _bst = 1 [V] . In this case, the dynamic range is increased to 77 dB. This means that when converted it to the Effective Number of Bits (ENOB) , it is extended by about 12 bits.

ENOB = (SINAD –1.76) /6.02

= (77 –1.76) /6.02

～ 12

Where, SINAD is a power ratio indicating the quality of the signal in dB, which is 77 in this example.

6. Variations

Next, variations of the embodiments are illustratively described.

6.1 Symmetric Structure

Figure 8 illustrates a variation using a symmetric structure. As depicted in Figure 8, the boost voltage supplier BOOST is shared between the pixel side (P-SIDE, or PIX-SIDE) and the ramp signal side (R-SIDE, Ref-SIDE) . Although not essential for R-SIDE, the P-SIDE boost voltage supplier BOOST and the R-SIDE boost voltage supplier BOOST may exist independently on both sides. When the boost voltage supplier BOOST is shared as depicted in Figure 8, it is advantageous in that the influence of the noise due to the boost voltage supplier BOOST may be cancelled.

6.2 Capacitor Switching

As described above, the capacitance ratio between the first capacitance element C ₁ and the second capacitance element C ₂ may be changed depending on the situation. For example, in addition to the first capacitance element C ₁ connected between the system input node PIXEL and the input node INN of the differential amplifier, a plurality of capacitance elements may be connected to the input node INN.

Figure 9 illustrates a variation which can switch capacitors. A first capacitance element C ₁ is connected between the input node INN and a first selection node SN ₁, a second capacitance element C ₂ is connected between the input node INN and a second selection node SN ₂, a third capacitance element C ₃ is connected between the input node INN and a third selection node SN ₃, a fourth capacitance element C ₄ is connected between the input node INN and a fourth selection node SN ₄, and the second to the fourth selection node SN ₂ to SN ₄ are connected to the boost voltage supplier BOOST through the switches, respectively. For the purpose of cancelling the noise components due to the boost voltage supplier BOOST, a similar structure may be provided in the ramp signal side (R-SIDE) as depicted in Figure 9. For example, the embodiment depicted in Figure 9 can select the capacitance to be used depending on brightness.

In the embodiments depicted in Figures 5, 8 and 9, in addition to or alternatively, the second voltage V _bst which the boost voltage supplier BOOST supplies to the selection node SN may be switched between two or more voltages, for example from the viewpoint of trimming after manufacturing. For example, the second voltage V _bst may transition not only between two states of 0 [V] and 1.0 [V] , but also among four states of 0, 0.8, 1.0, and 1.2 [V] . That is, the waveform of the second voltage V _bst may be expressed as L-value signal (L is an integer equal to or more than two) .

According to the embodiment, the acceptable voltage range and the dynamic range may be improved by switching the selection node SN to the side of the boost voltage supplier BOOST. This is preferred for comparators, analog to digital converters including the comparator, and CMOS image sensors including them. This is because the CMOS image sensor needs to adjust the full scale range depending on a lighting level of a scene and/or exposure time.

The embodiment can provide a low power consumption comparator with the large input range, an analog to digital converter including such a comparator, and a CMOS image sensor including them.

The embodiment can provide a low power consumption comparator with the improved dynamic range, an analog to digital converter including such a comparator, and a CMOS image sensor including them.

The embodiment may be used not only for a single slope type column parallel ADC in the CMOS image sensor, but also an input stage in a variety of ADCs.

7. System Architecture

The embodiments described herein may be applied to a variety of devices including mobile devices and stationary devices. An exemplary mobile terminal according to the embodiment will be described with reference to Figure 10. A mobile terminal may be a device that provides a user with an image capture function and/or data connectivity, a handheld device with a wireless connection function, or another processing device connected to a wireless modem (for example, a digital camera, a single-lens reflex camera, or a smartphone) . Alternatively, the mobile terminal may be another intelligent device with an image capture function and a display function (for example, a wearable device, a tablet computer, a PDA (Personal Digital Assistant, personal digital assistant) , a drone, or an aerial photographer) .

Figure 10 is a schematic diagram of an optional hardware structure of a terminal 100 which is an exemplary mobile terminal. Referring to Figure 10, the terminal 100 may include components such as a radio frequency unit 110, a memory 120, an input unit 130, a display unit 140, a imaging device 101, an audio circuit 160, a speaker 161, a microphone 162, an earphone jack 163, a processor 170, an external interface 180, and a power supply 190.

The radio frequency (RF) unit 110 may be configured to send and receive information or send and receive a signal in a call process. Generally, an RF unit includes but is not limited to an antenna, an amplifier, a transceiver, a coupler, a low noise amplifier (LNA) , a duplexer, and the like. In addition, the radio frequency unit 110 may communicate with a network device and another device through wireless communication. Any communications standard or protocol may be used for the wireless communication.

The memory 120 may be configured to store instructions and data. The memory 120 may mainly include an instruction storage area and a data storage area. The instruction storage area may store software such as an operating system, an application, and instructions. The data storage area may store an image which is obtained by the imaging device 10, audio data which is input or output by the audio circuit 150, an image displayed by the display unit 140, data used for an operation process performed by the processor 170, and other various transient or permanent data.

The input unit 130 may be configured to receive input digit or character information in the mobile terminal 100. Specifically, the input unit 130 may include a touchscreen 131 and other input devices 132. The touchscreen 131 may collect a touch operation of the user on or near the touchscreen, and drive a corresponding connection apparatus according to a preset program. The touchscreen 131 may detect a touch action of the user on the touchscreen, convert the touch action into a touch signal, send the touch signal to the processor 170, and receive and execute a command sent by the processor 170. Another input device 132 may include but is not limited to one or more of a physical keyboard, a function key (such as a volume control key or a power on/off key) , a trackball, a mouse, a joystick, and the like.

The display unit 140 may be configured to display information input by the user, information provided for the user, various menus of the terminal 100, or the like. In the embodiments, the display unit 140 is configured to display an image obtained by using the imaging device 101, where the image may include a preview image in some shooting modes, an image that is captured, an image that is processed by using a specific algorithm after shooting, or the like.

The imaging device 101 is configured to collect a still image or moving images and may be enabled through triggering by an application program instruction, to implement a shooting function or a video camera function. The imaging device 101 may include components such as an imaging lens, a light filter, and an image sensor. Particularly, the imaging device 101 according to the embodiment is an image sensor such as a CMOS image sensor. The image sensor may include the analog to digital converter depicted with reference to Figure 2. Light emitted or reflected by an object to be shot enters the imaging lens and is aggregated on the image sensor by passing through the light filter. The imaging lens is mainly configured to aggregate light emitted or reflected by an object to be shot, in a shooting field of view, and perform imaging. The light filter is mainly configured to filter out an extra light wave (for example, a light wave other than visible light, such as infrared light) from light. The image sensor is mainly configured to perform optical-to-electrical conversion on a received optical signal, convert the optical signal and the light intensity change into an electrical signal, and input the electrical signal to the processor 170 for subsequent processing.

The audio circuit 160, the speaker 161, the microphone 162, and an earphone jack 163 may provide an audio interface between the user and the mobile terminal 100. The audio circuit 160 may transmit, to the speaker 161, an electrical signal converted from received audio data, and the speaker 161 converts the electrical signal into a sound signal for output. Conversely, the microphone 162 is configured to collect a sound signal, and may convert the collected sound signal into an electrical signal. The audio circuit may also include an earphone jack 163, configured to provide a connection interface between the audio circuit and an earphone.

The processor 170 is a control center of the mobile terminal 100, and is connected to various parts of the mobile terminal 100 through various interfaces and signal lines. The processor 170 performs various functions of the mobile terminal 100, executes the instruction stored in the memory 120, and invokes the data stored in the memory 120, thereby processing the data. In some embodiments, the processor and the memory may be implemented on a single chip. In some embodiments, the processor and the memory may be separately implemented on independent chips.

The mobile terminal 100 further includes the external interface 180. The external interface 180 may be a standard micro-USB interface or a multi-pin connector. The external interface may be configured to connect the terminal 100 to another apparatus for communication, or may be configured to connect to a charger to charge the terminal 100.

The mobile terminal 100 further includes the power supply 190 (such as a battery) that supplies power to each component. Preferably, the power supply may be logically connected to the processor 170, so as to implement functions such as a charging function, a discharging function, and power consumption management by using the power supply management system.

Persons skilled in the art may understand that Figure 10 is merely an example of the mobile terminal, and does not constitute any limitation on the embodiments. The mobile terminal may include more or fewer components than those shown in the figure, or combine some components, or have different components.

The division into parts of elements in Figure 1, Figure 10, and so on are merely for logical function division, which prioritizes convenience of explanation. It is to be understood that some or all of the divided elements may be integrated, in actual implementation, into one physical entity, or may be physically separated. For example, each of the foregoing elements may be a separate processing element, or may be integrated on a chip of a mobile terminal. Alternatively, described processing elements may be stored in a storage element of a controller in a form of program code, and invoke and execute various functions, as appropriate. In addition, the processing elements may be integrated or may be implemented independently. The processing element may be an integrated circuit chip and has a signal processing capability. In an implementation process, steps in the foregoing methods or the foregoing elements can be implemented by using a hardware integrated logical circuit in the processing element, or by using instructions in a form of software.

Persons skilled in the art will understand that the embodiments of the present invention may be provided as a method, a device, a storage medium, or a computer program. Therefore, the present invention may use a form of hardware only embodiments, or embodiments with a combination of software and hardware.

The method, the device, the storage medium, and the computer program which relate to the embodiments of the present invention are described with reference to the flowcharts and/or block diagrams. It is to be understood that computer program instructions may be used to implement each process and/or each block in the flowcharts and/or the block diagrams. These computer program instructions may be provided for a general-purpose computer, a dedicated computer, an embedded processor, or a processor of any other programmable data processing device, so that the executed instructions generate the functions described with reference to the embodiments.

These computer program instructions may be stored in an appropriate storage medium, or may be transmitted on a transmission medium. These computer program instructions may be loaded onto a computer or another programmable data processing device, so that a series of operations are performed by the computer, thereby generating the functions described with reference to the embodiments.

Although the embodiments of the present invention are described, persons skilled in the art can make changes and modifications to these embodiments. Therefore, the following claims are intended to be construed to encompass the embodiments and all changes and modifications thereto, within the scope of the present invention.

LIST OF REFERENCE SYMBOLS

10 Image sensor

11 Pixel

12 Row decode circuit

13 Read out circuit

14 Power supplier

15 Processor

Claims

A comparator comprising:

a differential amplifier having a first port (INN) that receives a first signal, a second port (INP) that receives a second signal, and an output port that outputs a comparison result signal obtained by amplifying a result of subtracting the first signal from the second signal;

a first capacitance element (C ₁) connected between the first port (INN) and a system input port (PIXEL) receiving a signal to be converted to the first signal;

a second capacitance element (C ₂) connected between the first port (INN) and a selection node (SN) ; and

an AZ switch (SW _AZN) to switch between a connected state in which the first port (INN) and the output port are connected and a disconnected state in which they are disconnected;

wherein in response to the AZ switch (SW _AZN) switching from the connected state to the disconnected state, the comparator transitions from a first state, in which the selection node (SN) receives a first voltage, to a second state, in which the selection node (SN) receives a second voltage (V _bst) .
The comparator according to claim 1, wherein a capacitance ratio between the first capacitance element (C ₁) and the second capacitance element (C ₂) is adjustable.
The comparator according to claim 1, further comprising a third capacitance element (C ₃) connected between the first port (INN) and a selection node (SN) .
The comparator according to claim 1, further comprising:

a third capacitance element (C _1P) connected between the second port (INP) and another system input port (RAMP) receiving a signal to be converted to the second signal; and

another Auto Zero switch (SW _AZP) to switch between a connected state in which the second port (INP) and a predetermined node are connected, and a disconnected state in which they are disconnected.
An analog to digital converter comprising:

the comparator according to claim 1; and

a boost voltage supplier (BOOST) that supplies the first voltage to the selection node (SN) in a case where the AZ switch (SW _AZN) is in the connected state, and supplies the second voltage (V _bst) to the selection node (SN) in a case where the AZ switch (SW _AZN) is in the disconnected state;

wherein the signal to be converted to the first signal is an analog voltage signal from a pixel; the second signal is a reference signal to be compared with the analog voltage signal; and the analog to digital converter generates a digital signal corresponding to the analog voltage signal by means of the comparison result signal.
The analog to digital converter according to claim 5, wherein during an interval when the analog voltage signal indicates a base level of the pixel, the comparator boosts a voltage in the first port (INN) depending on the second voltage (V _bst) ; and

wherein, during an interval when the analog voltage signal indicates a voltage corresponding to electrical charge stored in the pixel, the comparator outputs an output signal from the output port, the output signal being indicative of a comparison result of the reference signal with the analog voltage signal, which is boosted depending on the second voltage (V _bst) .
An image sensor comprising:

a plurality of pixels;

a processor to control access to the plurality of pixels; and

the analog to digital converter according to claim 5, the analog to digital converter being connected to the processor.
An analog to digital converter comprising:

a differential amplifier having a first port (INN) that receives a first signal, a second port (INP) that receives a second signal, and an output port that outputs a comparison result signal obtained by amplifying a result of subtracting the first signal from the second signal;

a first PIX-side capacitance element (C _1N) connected between the first port (INN) and a first system input port (PIXEL) receiving a signal to be converted to the first signal;

a second PIX-side capacitance element (C _2N) connected between the first port (INN) and a PIX-side selection node (SN _N) ;

a PIX-side AZ switch (SW _AZN) to switch between a connected state in which the first port (INN) and the output port are connected and a disconnected state in which they are disconnected;

a first REF-side capacitance element (C _1P) connected between the second port (INP) and a second system input port (RAMP) receiving a reference signal to be compared with the first signal;

a second REF-side capacitance element (C _2P) connected between the second port (INP) and a REF-side selection node (SN _P) ;

a REF-side AZ switch (SW _AZP) to switch between a connected state, in which the second port (INP) and a predetermined node, are connected and a disconnected state, in which they are disconnected; and

a boost voltage supplier (BOOST) that supplies the first voltage to the PIX-side selection node (SN _N) and the REF-side selection node (SN _P) in a case where the PIX-side AZ switch (SW _AZN) and the REF-side AZ switch (SW _AZP) are in the connected state, and supplies the second voltage (V _bst) to the PIX-side selection node (SN _N) and the REF-side selection node (SN _P) in a case where the PIX-side AZ switch (SW _AZN) and the REF-side AZ switch (SW _AZP) switch are in the disconnected state;

wherein the signal to be converted to the first signal is an analog voltage signal from a pixel; the second signal is a reference signal to be compared with the analog voltage signal; and the analog to digital converter generates a digital signal corresponding to the analog voltage signal by means of the comparison result signal.
A method of comparing voltages in an apparatus that includes

a differential amplifier having a first port (INN) that receives a first signal, a second port (INP) that receives a second signal, and an output port that outputs an output signal;

a first capacitance element (C ₁) connected between the first port (INN) and a system input port (PIXEL) receiving a signal to be converted to the first signal;

a second capacitance element (C ₂) connected between the first port (INN) and a selection node (SN) ; and

a AZ switch (SW _AZN) to switch between a connected state, in which the first port (INN) and the output port are connected, and a disconnected state, in which they are disconnected;

wherein the signal to be converted to the first signal is an analog voltage signal from a pixel; the second signal is a reference signal to be compared with the analog voltage signal; and the output signal is a digital signal corresponding to the analog voltage signal, the method comprising:

in response to the AZ switch (SW _AZN) switching from the connected state to the disconnected state, transitioning from a first state, in which the selection node (SN) receives a first voltage, to a second state in which the selection node (SN) receives a second voltage (V _bst) ;

during an interval when the analog voltage signal indicates a base level of the pixel, boosting a voltage in the first port (INN) depending on the second voltage (V _bst) ; and

during an interval when the analog voltage signal indicates a voltage corresponding to electrical charge stored in the pixel, outputting a comparison result signal from the output port , the comparison result signal obtained by amplifying a result of subtracting the reference signal from the analog voltage signal that is boosted depending on the second voltage (V _bst) .