WO2023189052A1 - 半導体モジュール - Google Patents

半導体モジュール Download PDF

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Publication number
WO2023189052A1
WO2023189052A1 PCT/JP2023/006631 JP2023006631W WO2023189052A1 WO 2023189052 A1 WO2023189052 A1 WO 2023189052A1 JP 2023006631 W JP2023006631 W JP 2023006631W WO 2023189052 A1 WO2023189052 A1 WO 2023189052A1
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Prior art keywords
semiconductor module
chip
region
electrode
less
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PCT/JP2023/006631
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English (en)
French (fr)
Japanese (ja)
Inventor
真也 梅木
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Rohm Co Ltd
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Rohm Co Ltd
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Priority to CN202380030275.7A priority Critical patent/CN118975133A/zh
Priority to JP2024511469A priority patent/JPWO2023189052A1/ja
Publication of WO2023189052A1 publication Critical patent/WO2023189052A1/ja
Priority to US18/802,642 priority patent/US20240405016A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of AC power input into DC power output; Conversion of DC power input into AC power output
    • H02M7/42—Conversion of DC power input into AC power output without possibility of reversal
    • H02M7/44—Conversion of DC power input into AC power output without possibility of reversal by static converters
    • H02M7/48—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/12—Modifications for increasing the maximum permissible switched current
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/567—Circuits characterised by the use of more than one type of semiconductor device, e.g. BIMOS, composite devices such as IGBT
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/441—Vertical IGBTs
    • H10D12/461—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions
    • H10D12/481—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/81—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
    • H10D62/8325—Silicon carbide
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H10D8/50—PIN diodes 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/40—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00 with at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of IGFETs with BJTs
    • H10D84/401—Combinations of FETs or IGBTs with BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/10—Integrated device layouts

Definitions

  • the present invention relates to an IGBT device and a semiconductor module including a MISFET device forming a parallel circuit with the IGBT device.
  • Patent Document 1 discloses a power transistor driving device including a parallel circuit including an edge-gate bipolar transistor and a field-effect transistor.
  • the field effect transistor is controlled to be in the on state after the insulated gate bipolar transistor is controlled to be in the on state.
  • One embodiment provides a semiconductor module with improved electrical characteristics.
  • One embodiment includes an IGBT device and a MISFET device that configures a parallel circuit with the IGBT device, and generates a drain current of the MISFET device in a voltage range less than the built-in voltage of the IGBT device, and generates a drain current of the MISFET device in a voltage range that is equal to or higher than the built-in voltage.
  • a semiconductor module is provided that generates a collector current of the IGBT device and a drain current of the MISFET device in a voltage range of .
  • FIG. 1 is a circuit diagram showing the electrical structure of a semiconductor module according to one embodiment.
  • FIG. 2 is a graph showing the electrical characteristics of the semiconductor module shown in FIG.
  • FIG. 3 is a plan view showing a configuration example of an IGBT device incorporated into the semiconductor module shown in FIG. 1.
  • FIG. 4 is a schematic cross-sectional view taken along the line IV-IV shown in FIG. 3.
  • FIG. 5 is a plan view showing an example of the layout within the first chip shown in FIG.
  • FIG. 6 is a cross-sectional view showing a main part of the first active region shown in FIG.
  • FIG. 7 is a plan view showing a configuration example of a MISFET device incorporated in the semiconductor module shown in FIG. 1.
  • FIG. 1 is a circuit diagram showing the electrical structure of a semiconductor module according to one embodiment.
  • FIG. 2 is a graph showing the electrical characteristics of the semiconductor module shown in FIG.
  • FIG. 3 is a plan view showing a configuration example of an IGBT device incorporated into
  • FIG. 8 is a schematic cross-sectional view taken along the line VIII-VIII shown in FIG. 7.
  • FIG. 9 is a plan view showing an example of the layout within the second chip shown in FIG.
  • FIG. 10 is a sectional view showing a main part of the second active region shown in FIG. 7.
  • FIG. 11A is a graph showing current-voltage characteristics according to the first adjustment example of the semiconductor module shown in FIG. 1.
  • FIG. 11B is a graph showing current-voltage characteristics according to the second adjustment example of the semiconductor module shown in FIG. 1.
  • FIG. FIG. 11C is a graph showing current-voltage characteristics according to the third adjustment example of the semiconductor module shown in FIG. 1.
  • FIG. 12 is a perspective view showing an example of the configuration of a semiconductor module.
  • FIG. 13 is a plan view showing the internal structure of the semiconductor module shown in FIG. 12.
  • FIG. 14 is a plan view showing another example of the configuration of the semiconductor module.
  • FIG. 15 is a plan view showing another example of the configuration of the semiconductor module.
  • FIG. 16 is a sectional view showing another configuration example of the IGBT device.
  • FIG. 17 is a sectional view showing another configuration example of the MISFET device.
  • FIG. 18 is a sectional view showing another configuration example of the MISFET device.
  • FIG. 19 is a sectional view showing another configuration example of the MISFET device.
  • FIG. 20 is a sectional view showing another configuration example of the MISFET device.
  • this phrase includes a numerical value (form) that is equal to the numerical value (form) of the comparison target; It also includes a numerical error (form error) in the range of ⁇ 10% based on (form).
  • a numerical value that is equal to the numerical value (form) of the comparison target
  • a numerical error form error in the range of ⁇ 10% based on (form).
  • words such as “first”, “second”, “third”, etc. are used, but these are symbols attached to the name of each structure to clarify the order of explanation; It is not given for the purpose of limiting the name.
  • FIG. 1 is a circuit diagram showing the electrical structure of a semiconductor module 1 according to an embodiment.
  • a semiconductor module 1 includes an IGBT device 2 (Insulated Gate Bipolar Transistor device) and a MISFET device 3 (Metal Semiconductor Field Effect Transistor device) that constitutes a parallel switching circuit together with the IGBT device 2.
  • IGBT device 2 Insulated Gate Bipolar Transistor device
  • MISFET device 3 Metal Semiconductor Field Effect Transistor device
  • the IGBT device 2 is a bipolar type first semiconductor switching device (first semiconductor device) having an IGBT, and includes a collector C, an emitter E, and a first gate G1.
  • the MISFET device 3 is a unipolar type second semiconductor switching device (second semiconductor device) having a MISFET, and includes a drain D, a source S, and a second gate G2.
  • the drain D of the MISFET device 3 is electrically connected to the collector C of the IGBT device 2.
  • the source S of the MISFET device 3 is electrically connected to the emitter E of the IGBT device 2.
  • the second gate G2 of the MISFET device 3 is electrically connected to the first gate G1 of the IGBT device 2.
  • the first gate G1 of the IGBT device 2 and the second gate G2 of the MISFET device 3 are electrically connected to a gate drive circuit GD, and a gate signal from the gate drive circuit GD is input to the first gate G1 and the second gate G2. Ru. That is, the MISFET device 3 is controlled simultaneously with the IGBT device 2.
  • the IGBT device 2 generates a collector current Ice in response to a gate signal
  • the MISFET device 3 generates a drain current Ids in response to a gate signal.
  • the gate drive circuit GD may be a gate driver IC.
  • FIG. 1 shows a configuration in which the semiconductor module 1 is electrically connected to the gate drive circuit GD, the semiconductor module 1 may include the gate drive circuit GD as one component.
  • FIG. 2 is a graph showing the electrical characteristics of the semiconductor module 1 shown in FIG. 1.
  • the vertical axis represents collector current Ice (drain current Ids)
  • the horizontal axis represents collector voltage Vce (drain voltage Vds).
  • FIG. 2 shows the characteristics of the output current IO of the semiconductor module 1.
  • Output current IO is the sum of collector current Ice and drain current Ids.
  • semiconductor module 1 generates an output current IO consisting only of drain current Ids of MISFET device 3 in a voltage range less than built-in voltage Vbi of IGBT device 2.
  • the semiconductor module 1 generates an output current IO including the drain current Ids of the MISFET device 3 and the collector current Ice of the IGBT device 2 in a voltage range equal to or higher than the built-in voltage Vbi of the IGBT device 2.
  • the IGBT device 2 Since the IGBT device 2 is a bipolar semiconductor switching device, it has a relatively large loss in a low current region below the built-in voltage Vbi, and a relatively small loss in a high current region above the built-in voltage Vbi. .
  • the loss reduction effect in the high current region in the IGBT device 2 is due to the conductivity modulation effect.
  • the MISFET device 3 is a unipolar semiconductor switching device different from the IGBT device 2, it does not have a built-in voltage Vbi and does not exhibit a conductivity modulation effect. MISFET device 3 has relatively small loss in the low current region and relatively large loss in the high current region. Although the loss in the high current region of the MISFET device 3 can be improved by increasing the size of the MISFET device 3, problems of cost and layout changes arise.
  • the drain current Ids of the MISFET device 3 is used in the low current region, so the loss of the IGBT device 2 in the low current region is reduced. Furthermore, since the collector current Ice of the IGBT device 2 and the drain current Ids of the MISFET device 3 are used in the high current region, the loss of the MISFET device 3 in the high current region is reduced.
  • both the loss in the low current region and the loss in the high current region can be reduced without increasing the size of the MISFET device 3. Therefore, it is possible to provide a semiconductor module 1 with improved electrical characteristics.
  • an example of the configuration of the IGBT device 2 incorporated into the semiconductor module 1 and an example of the configuration of the MISFET device 3 incorporated into the semiconductor module 1 will be explained.
  • FIG. 3 is a plan view showing an example of the configuration of the IGBT device 2 incorporated into the semiconductor module 1 shown in FIG. 1.
  • FIG. 4 is a schematic cross-sectional view taken along the line IV-IV shown in FIG. 3.
  • FIG. 5 is a plan view showing an example of the layout within the first chip 10 shown in FIG.
  • FIG. 6 is a cross-sectional view showing a main part of the first active region 17 shown in FIG. 5. As shown in FIG.
  • the IGBT device 2 has a first breakdown voltage VB1.
  • the first breakdown voltage VB1 is a reverse voltage at which reverse voltage breakdown (avalanche breakdown) begins.
  • the first breakdown voltage VB1 may be greater than or equal to 500V and less than or equal to 1500V.
  • the first breakdown voltage VB1 may have a value belonging to any one of the following ranges: 500V to 750V, 750V to 1000V, 1000V to 1250V, and 1250V to 1500V.
  • the first breakdown voltage VB1 may be 500V or more and 700V or less, or 1100V or more and 1300V or less.
  • the IGBT device 2 includes a first chip 10 having a hexahedral shape (specifically, a rectangular parallelepiped shape).
  • the first chip 10 is a Si chip made of single crystal Si (silicon).
  • the IGBT device 2 is a "Si-IGBT device.”
  • the first chip 10 has a single layer structure made of a Si substrate.
  • the first chip 10 has a first chip thickness T1.
  • the first chip thickness T1 may have a thickness of 50 ⁇ m or more and 200 ⁇ m or less.
  • the first chip thickness T1 has a value belonging to any one of the following ranges: 50 ⁇ m to 75 ⁇ m, 75 ⁇ m to 100 ⁇ m, 100 ⁇ m to 125 ⁇ m, 125 ⁇ m to 150 ⁇ m, 150 ⁇ m to 175 ⁇ m, and 175 ⁇ m to 200 ⁇ m. You may do so.
  • the first chip thickness T1 may be 60 ⁇ m or more and 90 ⁇ m or less.
  • the first chip thickness T1 may be greater than or equal to 120 ⁇ m and less than or equal to 160 ⁇ m.
  • the first chip 10 has a first main surface 11 on one side, a second main surface 12 on the other side, and first to fourth side surfaces 13A to 13D connecting the first main surface 11 and the second main surface 12. have.
  • the first main surface 11 and the second main surface 12 are formed into a quadrangular shape (rectangular shape in this form) in a plan view (hereinafter simply referred to as "plan view") seen from the normal direction Z. .
  • the normal direction Z is also the thickness direction of the first chip 10.
  • the first main surface 11 and the second main surface 12 may be formed in a square shape in plan view.
  • the first side surface 13A and the second side surface 13B extend in a first direction
  • the first side surface 13A and the second side surface 13B form the long sides of the first chip 10.
  • the third side surface 13C and the fourth side surface 13D extend in the second direction Y and face the first direction X.
  • the third side surface 13C and the fourth side surface 13D form the short sides of the first chip 10.
  • the first to fourth side surfaces 13A to 13D may each have a length of 0.1 mm or more and 20 mm or less in plan view.
  • the length of the first to fourth side surfaces 13A to 13D is 0.1 mm or more and 1 mm or less, 1 mm or more and 2.5 mm or less, 2.5 mm or more and 5 mm or less, 5 mm or more and 7.5 mm or less, 7.5 mm or more and 10 mm or less, and 10 mm. It may each have a value belonging to any one of the following ranges: 12.5 mm to 15 mm, 15 mm to 17.5 mm, and 17.5 mm to 20 mm.
  • the first chip 10 has a first chip area S1 in plan view.
  • the first chip area S1 is the product of the length of the first side surface 13A and the length of the third side surface 13C (that is, the product of the length of the second side surface 13B and the length of the fourth side surface 13D).
  • the IGBT device 2 includes an n-type (first conductivity type) semiconductor region 14 formed inside the first chip 10.
  • the semiconductor region 14 is formed throughout the interior of the first chip 10 .
  • the first chip 10 is made of an n-type Si chip, and the semiconductor region 14 is formed using the Si chip.
  • the IGBT device 2 includes an n-type buffer region 15 formed in the surface layer portion of the second main surface 12.
  • the buffer region 15 is formed in a layer shape extending along the second main surface 12 over the entire second main surface 12, and is exposed from the first to fourth side surfaces 13A to 13D.
  • Buffer region 15 has a higher n-type impurity concentration than semiconductor region 14. The presence or absence of the buffer area 15 is optional, and a configuration without the buffer area 15 may be adopted.
  • the IGBT device 2 includes a p-type (second conductivity type) collector region 16 formed in the surface layer portion of the second main surface 12.
  • the collector region 16 is formed in the surface layer portion of the buffer region 15 on the second main surface 12 side.
  • the collector region 16 is formed in a layered manner extending along the second main surface 12 over the entire second main surface 12, and is exposed from the second main surface 12 and the first to fourth side surfaces 13A to 13D.
  • the IGBT device 2 includes a first active region 17 provided on the first main surface 11 of the first chip 10.
  • the first active region 17 is a region that includes an IGBT structure 18 and generates a collector current Ice.
  • the first active region 17 has a first active area SA1 in plan view.
  • the first active area SA1 is defined by the planar area of a polygonal region (see the two-dot chain line in FIG. 3) that includes the IGBT structure 18 in plan view.
  • the first active area SA1 is defined by the total planar area of the plurality of first active regions 17.
  • the first active area SA1 takes various values depending on the first chip area S1.
  • the first active area SA1 may be 30% or more and less than 100% of the first chip area S1.
  • the first active area SA1 is 30% or more and 40% or less, 40% or more and 50% or less, 50% or more and 60% or less, 60% or more and 70% or less, 70% or more and 80% or less, and 80% of the first chip area S1. It may have a value that belongs to any one of the ranges of 90% or more and 90% or more and less than 100%.
  • the IGBT structure 18 includes a p-type base region 19 formed in the surface layer of the first main surface 11 in the first active region 17 .
  • Base region 19 may also be referred to as a "channel region.”
  • the base region 19 is formed in a layered shape extending along the first main surface 11 over the entire first active region 17 .
  • the IGBT structure 18 includes a plurality of first trench structures 20 formed on the first main surface 11 in the first active region 17 .
  • a gate potential Vg is applied to the plurality of first trench structures 20.
  • the plurality of first trench structures 20 control channel inversion and non-inversion.
  • the IGBT structure 18 is of a trench gate type.
  • the first trench structure 20 may be referred to as a "first trench gate structure.”
  • the plurality of first trench structures 20 are arranged at intervals in the first direction X, and are each formed in a band shape extending in the second direction Y.
  • the plurality of first trench structures 20 are formed on the first main surface 11 so as to penetrate the base region 19 and reach the semiconductor region 14 .
  • the depth of each first trench structure 20 may be 0.5 ⁇ m or more and 10 ⁇ m or less.
  • the depth of each first trench structure 20 belongs to any one of the following ranges: 0.5 ⁇ m to 2.5 ⁇ m, 2.5 ⁇ m to 5 ⁇ m, 5 ⁇ m to 7.5 ⁇ m, and 7.5 ⁇ m to 10 ⁇ m. It may have a value.
  • the depth of each first trench structure 20 is preferably 4 ⁇ m or more and 8 ⁇ m or less.
  • Each first trench structure 20 includes a first trench 21, a first insulating film 22, and a first buried electrode 23.
  • the first trench 21 is formed in the first main surface 11 and partitions the wall surface of the first trench structure 20.
  • the first insulating film 22 covers the wall surface of the first trench 21 in the form of a film.
  • the first insulating film 22 may include a silicon oxide film.
  • the first buried electrode 23 is buried in the first trench 21 with the first insulating film 22 interposed therebetween. In this form, the first buried electrode 23 includes conductive polysilicon.
  • the IGBT structure 18 includes a plurality of n-type emitter regions 24 formed in a region along the plurality of first trench structures 20 in the surface layer portion of the base region 19 .
  • Each emitter region 24 has a higher n-type impurity concentration than the semiconductor region 14.
  • Each emitter region 24 is formed in a region between two adjacent first trench structures 20 in the surface layer portion of the base region 19 .
  • Each emitter region 24 forms a channel of the IGBT in the base region 19 together with the semiconductor region 14 .
  • the IGBT structure 18 includes a plurality of contact holes 25 formed in the first main surface 11 so as to expose a plurality of emitter regions 24.
  • Each contact hole 25 is formed in a region between two adjacent first trench structures 20.
  • Each contact hole 25 is formed at intervals from the bottom of the base region 19 toward the first main surface 11 side.
  • Each contact hole 25 may penetrate the emitter region 24 or may be formed at intervals from the bottom of the emitter region 24 toward the first main surface 11 side.
  • Each contact hole 25 is formed in a band shape extending along the first trench structure 20 in plan view.
  • the IGBT structure 18 includes a plurality of p-type first contact regions 26 formed in a region different from the emitter region 24 in the surface layer portion of the base region 19. Each first contact region 26 has a higher p-type impurity concentration than base region 19. Each first contact region 26 is formed in a region along the wall surface of the corresponding contact hole 25 . Each first contact region 26 is formed in a band shape extending along the corresponding contact hole 25 in plan view. The bottom of each first contact region 26 is formed in a region between the bottom of the base region 19 and the bottom wall of the corresponding contact hole 25 .
  • the IGBT device 2 includes a first interlayer insulating film 27 that covers the first main surface 11.
  • the first interlayer insulating film 27 includes a first lower insulating film 28 and a first upper insulating film 29.
  • the first lower insulating film 28 is connected to the first insulating film 22 and covers the first main surface 11 so as to expose the first buried electrode 23.
  • the first lower insulating film 28 may include a silicon oxide film.
  • the first upper insulating film 29 covers the first lower insulating film 28 so as to cover the plurality of first trench structures 20 .
  • the first upper insulating film 29 may include a silicon oxide film.
  • the first upper insulating film 29 is thicker than the first lower insulating film 28 .
  • the first interlayer insulating film 27 includes a plurality of emitter openings 30 that expose the plurality of emitter regions 24.
  • the plurality of emitter openings 30 are formed in one-to-one correspondence with the plurality of contact holes 25 so as to communicate with the plurality of contact holes 25 .
  • the plurality of emitter openings 30 are formed in a band shape extending along the plurality of contact holes 25 .
  • the IGBT device 2 includes a plurality of contact electrodes 31 embedded in a first interlayer insulating film 27.
  • the plurality of contact electrodes 31 are embedded in the plurality of emitter openings 30. Each contact electrode 31 enters into the contact hole 25 from the emitter opening 30 and is electrically connected to the emitter region 24 and the first contact region 26 within the contact hole 25 .
  • the IGBT device 2 includes a first gate electrode 32 disposed on a first interlayer insulating film 27.
  • a gate potential Vg is applied to the first gate electrode 32 from the outside.
  • the first gate electrode 32 is arranged in a region along the center of the third side surface 13C in plan view.
  • the first gate electrode 32 may be arranged at any location.
  • the first gate electrode 32 may be arranged in a region along a corner of the first chip 10 or in the center of the first chip 10 in plan view.
  • the first gate electrode 32 faces a region outside the first active region 17 with the first interlayer insulating film 27 in between.
  • the first gate electrode 32 may face the first active region 17 (that is, the plurality of first trench structures 20) with the first interlayer insulating film 27 in between.
  • the first gate electrode 32 is formed into a rectangular shape in plan view.
  • the first gate electrode 32 may be formed in a circular or polygonal shape in plan view.
  • the first gate electrode 32 includes a conductive material different from that of the first buried electrode 23.
  • the first gate electrode 32 may include at least one of a Ti-based metal film, an Al-based metal film, and a Cu-based metal film.
  • the Ti-based metal film may include at least one of a Ti film and a TiN film (the same applies hereinafter in this specification).
  • the Al-based metal film may include at least one of a pure Al film (an Al film with a purity of 99% or more) and an Al alloy film (the same applies hereinafter in this specification).
  • the Cu-based metal film may include at least one of a pure Cu film (a Cu film with a purity of 99% or more) and a Cu alloy film (the same applies hereinafter in this specification).
  • the Al alloy film and the Cu alloy film may include at least one of an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film (the same applies hereinafter in this specification).
  • the gate electrode has a stacked structure including a Ti-based metal film and an Al-based metal film stacked in this order from the first interlayer insulating film 27 side.
  • the first gate electrode 32 may be referred to as a "first gate metal.”
  • the IGBT device 2 includes a first gate wiring 33 disposed on the first interlayer insulating film 27.
  • the first gate wiring 33 is electrically connected to the first gate electrode 32 and the plurality of first trench structures 20 and transmits the gate potential Vg applied to the first gate electrode 32 to the plurality of first trench structures 20. .
  • the first gate wiring 33 is drawn out from the first gate electrode 32 onto the first interlayer insulating film 27 in a plan view, and intersects (specifically, The first to third side surfaces 13A to 13C extend in a band shape so as to be perpendicular to each other.
  • the first gate wiring 33 penetrates the first interlayer insulating film 27 and is electrically connected to the plurality of first trench structures 20 .
  • the first gate wiring 33 includes the same conductive material as the first gate electrode 32 .
  • the IGBT device 2 includes an emitter electrode 34 disposed on the first interlayer insulating film 27.
  • An emitter potential Ve is applied to the emitter electrode 34 from the outside.
  • the emitter electrode 34 is arranged on the first interlayer insulating film 27 in a region surrounded by the first gate electrode 32 and the first gate wiring 33 so as to cover the first active region 17 .
  • the emitter electrode 34 faces the plurality of first trench structures 20 with the first interlayer insulating film 27 in between, and penetrates the first interlayer insulating film 27 to provide electricity to the plurality of emitter regions 24 and the plurality of first contact regions 26. connected. Specifically, the emitter electrode 34 is electrically connected to the plurality of emitter regions 24 and the plurality of first contact regions 26 via the plurality of contact electrodes 31 that penetrate the first interlayer insulating film 27 .
  • the emitter electrode 34 includes the same conductive material as the first gate electrode 32. Emitter electrode 34 may also be referred to as "emitter metal.” In this form, the emitter electrode 34 includes a different conductive material than the plurality of contact electrodes 31. Of course, the emitter electrode 34 may include the same conductive material as the plurality of contact electrodes 31. In this case, portions of the emitter electrode 34 located within the plurality of emitter openings 30 may be formed as the plurality of contact electrodes 31.
  • the emitter electrode 34 has a planar shape that is substantially similar to the planar shape of the first active region 17. If the planar shape of the emitter electrode 34 is substantially similar to the planar shape of the first active region 17, the above-mentioned first active area SA1 may be defined by the planar area of the emitter electrode 34.
  • the IGBT device 2 includes a collector electrode 35 covering the second main surface 12.
  • a collector potential Vc is applied to the collector electrode 35.
  • the collector electrode 35 forms ohmic contact with the collector region 16 exposed from the second main surface 12 .
  • the collector electrode 35 may cover the entire second main surface 12 so as to be continuous with the peripheral edge (first to fourth side surfaces 13A to 13D) of the first chip 10.
  • FIG. 7 is a plan view showing an example of the configuration of the MISFET device 3 incorporated into the semiconductor module 1 shown in FIG. 1.
  • FIG. 8 is a schematic cross-sectional view taken along the line VIII-VIII shown in FIG. 7.
  • FIG. 9 is a plan view showing an example of the layout inside the second chip 40 shown in FIG.
  • FIG. 10 is a cross-sectional view showing a main part of the second active region 47 shown in FIG. 7. As shown in FIG.
  • the MISFET device 3 has a second breakdown voltage VB2.
  • the second breakdown voltage VB2 is a reverse voltage at which reverse voltage breakdown (avalanche breakdown) begins.
  • the second breakdown voltage VB2 is preferably higher than the first breakdown voltage VB1 of the IGBT device 2. It is particularly preferred that the second breakdown voltage VB2 is higher than the first breakdown voltage VB1.
  • the second breakdown voltage VB2 may be greater than or equal to 500V and less than or equal to 3000V.
  • the second breakdown voltage VB2 is 500V or more and 750V or less, 750V or more and 1000V or less, 1000V or more and 1250V or less, 1250V or more and 1500V or less, 1500V or more and 1750V or less, 1750V or more and 2000V or less, 2000V or more and 2250V or less, 2250V or more and 2500V or less, and 2500V or more. It may have a value belonging to any one of 2750V or less and 2750V or more and 3000V or less.
  • the second breakdown voltage VB2 may be 500V or more and 700V or less, or 1100V or more and 1300V or less.
  • MISFET device 3 includes a second chip 40 having a hexahedral shape (specifically, a rectangular parallelepiped shape).
  • the second chip 40 is made of a semiconductor single crystal chip different from the first chip 10.
  • the second chip 40 is a wide bandgap semiconductor chip made of a single crystal wide bandgap semiconductor.
  • the MISFET device 3 is a "wide bandgap semiconductor-MISFET device."
  • a wide bandgap semiconductor is a semiconductor that has a bandgap that exceeds that of Si.
  • GaN gallium nitride
  • SiC silicon carbide
  • C diamond
  • the second chip 40 is made of a SiC chip that includes a hexagonal SiC single crystal as an example of a wide bandgap semiconductor.
  • the MISFET device 3 is a "SiC-MISFET device.”
  • the hexagonal SiC single crystal has multiple types of polytypes including 2H (Hexagonal)-SiC single crystal, 4H-SiC single crystal, 6H-SiC single crystal, and the like.
  • the second chip 40 includes a 4H-SiC single crystal, but the second chip 40 may include other polytypes.
  • the second chip 40 has a second chip thickness T2.
  • the second chip thickness T2 may be greater than or equal to the first chip thickness T1 of the IGBT device 2.
  • the second chip thickness T2 may be less than the first chip thickness T1.
  • the second chip thickness T2 may be approximately equal to the first chip thickness T1.
  • the second chip thickness T2 may have a thickness of 25 ⁇ m or more and 200 ⁇ m or less.
  • the second chip thickness T2 is in any one of the following ranges: 25 ⁇ m to 50 ⁇ m, 50 ⁇ m to 75 ⁇ m, 75 ⁇ m to 100 ⁇ m, 100 ⁇ m to 125 ⁇ m, 125 ⁇ m to 150 ⁇ m, 150 ⁇ m to 175 ⁇ m, and 175 ⁇ m to 200 ⁇ m. may have a value belonging to .
  • the second chip thickness T2 is 25 ⁇ m or more and 50 ⁇ m or less, 50 ⁇ m or more and 75 ⁇ m or less, 75 ⁇ m or more and 100 ⁇ m or less, 100 ⁇ m or more and 125 ⁇ m or less, 125 ⁇ m or more and 150 ⁇ m or less, And, it may have a value belonging to any one range of 150 ⁇ m or more and 175 ⁇ m or less.
  • the second chip thickness T2 is 50 ⁇ m or more and 75 ⁇ m or less, 75 ⁇ m or more and 100 ⁇ m or less, 100 ⁇ m or more and 125 ⁇ m or less, 125 ⁇ m or more and 150 ⁇ m or less, and 150 ⁇ m. It may have a value belonging to any one of the ranges of 175 ⁇ m or more and 175 ⁇ m or more and 200 ⁇ m or less.
  • the second chip thickness T2 is any one of 150 ⁇ m and 160 ⁇ m, 160 ⁇ m and 170 ⁇ m, and 170 ⁇ m and 180 ⁇ m. may have values belonging to one range.
  • the second chip 40 has a first main surface 41 on one side, a second main surface 42 on the other side, and first to fourth side surfaces 43A to 43D connecting the first main surface 41 and the second main surface 42. have.
  • the first main surface 41 and the second main surface 42 are formed into a quadrangular shape (in this form, a square shape) in a plan view (hereinafter simply referred to as "plan view") when viewed from the normal direction Z. .
  • the normal direction Z is also the thickness direction of the second chip 40.
  • the first main surface 41 and the second main surface 42 may be formed in a rectangular shape in plan view.
  • the first main surface 41 and the second main surface 42 are formed by a c-plane of a SiC single crystal.
  • the first principal surface 41 is formed by the silicon plane ((0001) plane) of the SiC single crystal
  • the second principal surface 42 is formed by the carbon plane ((000-1) plane) of the SiC single crystal. It is preferable.
  • the first main surface 41 and the second main surface 42 may have an off angle that is inclined at a predetermined angle in a predetermined off direction with respect to the c-plane.
  • the off direction is preferably the a-axis direction ([11-20] direction) of the SiC single crystal.
  • the off angle may be greater than 0° and less than or equal to 10°.
  • the off angle is preferably 5° or less.
  • the first side surface 43A and the second side surface 43B extend in a first direction
  • the third side surface 43C and the fourth side surface 43D extend in the second direction Y and face the first direction X.
  • the first direction X may be the m-axis direction ([1-100] direction) of the SiC single crystal
  • the second direction Y may be the a-axis direction of the SiC single crystal.
  • the first direction X may be the a-axis direction of the SiC single crystal
  • the second direction Y may be the m-axis direction of the SiC single crystal.
  • the first to fourth side surfaces 43A to 43D may each have a length of 0.1 mm or more and 20 mm or less in plan view.
  • the length of the first to fourth side surfaces 43A to 43D is 0.1 mm or more and 1 mm or less, 1 mm or more and 2.5 mm or less, 2.5 mm or more and 5 mm or less, 5 mm or more and 7.5 mm or less, 7.5 mm or more and 10 mm or less, and 10 mm. It may each have a value belonging to any one of the following ranges: 12.5 mm to 15 mm, 15 mm to 17.5 mm, and 17.5 mm to 20 mm.
  • the second chip 40 has a second chip area S2 in plan view.
  • the second chip area S2 is the product of the length of the first side surface 43A and the length of the third side surface 43C (that is, the product of the length of the second side surface 43B and the length of the fourth side surface 43D).
  • the second chip area S2 is preferably less than the first chip area S1 of the IGBT device 2.
  • the second chip area S2 is 0.1 times or more and 0.6 times or less the first chip area S1.
  • the second chip area S2 is 0.1 times or more and 0.2 times or less, 0.2 times or more and 0.3 times or less, 0.3 times or more and 0.4 times or less, or 0. It may have a value belonging to any one of the ranges of .4 times to 0.5 times, and 0.5 times to 0.6 times.
  • the MISFET device 3 includes an n-type first semiconductor region 44 formed in a region (surface layer portion) on the first main surface 41 side within the second chip 40.
  • the first semiconductor region 44 is formed in a layered shape extending along the first main surface 41 and is exposed from the first main surface 41 and the first to fourth side surfaces 43A to 43D.
  • the first semiconductor region 44 is made of a wide bandgap semiconductor epitaxial layer (SiC epitaxial layer).
  • the first semiconductor region 44 may have a thickness of 1 ⁇ m or more and 50 ⁇ m or less.
  • the first semiconductor region 44 may have a value belonging to any one of the following ranges: 1 ⁇ m to 10 ⁇ m, 10 ⁇ m to 20 ⁇ m, 20 ⁇ m to 30 ⁇ m, 30 ⁇ m to 40 ⁇ m, and 40 ⁇ m to 50 ⁇ m.
  • the thickness of the first semiconductor region 44 is preferably 15 ⁇ m or more and 25 ⁇ m or less.
  • the MISFET device 3 includes an n-type second semiconductor region 45 formed in a region (surface layer portion) on the second main surface 42 side within the second chip 40.
  • the second semiconductor region 45 is formed in a layered manner extending along the second main surface 42 and is exposed from the second main surface 42 and the first to fourth side surfaces 43A to 43D.
  • the second semiconductor region 45 has a higher n-type impurity concentration than the first semiconductor region 44 and is electrically connected to the first semiconductor region 44 .
  • the second semiconductor region 45 is made of a wide bandgap semiconductor single crystal substrate (SiC single crystal substrate).
  • the second chip 40 has a laminated structure including a substrate and an epitaxial layer.
  • the second semiconductor region 45 may have a thickness of 1 ⁇ m or more and 200 ⁇ m or less.
  • the second semiconductor region 45 has a size of 1 ⁇ m to 25 ⁇ m, 25 ⁇ m to 50 ⁇ m, 50 ⁇ m to 75 ⁇ m, 75 ⁇ m to 100 ⁇ m, 100 ⁇ m to 125 ⁇ m, 125 ⁇ m to 150 ⁇ m, 150 ⁇ m to 175 ⁇ m, and 175 ⁇ m to 200 ⁇ m. or may have values belonging to one range.
  • the thickness of the second semiconductor region 45 may be 5 ⁇ m or more.
  • the thickness of the second semiconductor region 45 is preferably 10 ⁇ m or more.
  • the thickness of the second semiconductor region 45 may be greater than or equal to the thickness of the first semiconductor region 44.
  • the thickness of the second semiconductor region 45 may be less than the thickness of the first semiconductor region 44.
  • the thickness of the second semiconductor region 45 may be approximately equal to the thickness of the first semiconductor region 44; the thickness of the second semiconductor region 45 is greater than the thickness of the first semiconductor region 44 in this form.
  • the MISFET device 3 includes a second active region 47 provided on the first main surface 41 of the second chip 40.
  • the second active region 47 is a region that includes a MISFET structure 48 and generates a drain current Ids.
  • the second active region 47 has a second active area SA2 in plan view.
  • the second active area SA2 is defined by the planar area of the polygonal region.
  • the second active area SA2 is defined by the total planar area of the plurality of second active regions 47.
  • the second active area SA2 takes various values depending on the second chip area S2.
  • the second active area SA2 may be 30% or more and less than 100% of the second chip area S2.
  • the second active area SA2 is 30% or more and 40% or less, 40% or more and 50% or less, 50% or more and 60% or less, 60% or more and 70% or less, 70% or more and 80% or less, and 80% of the second chip area S2. It may have a value that belongs to any one of the ranges of 90% or more and 90% or more and less than 100%.
  • the second active area SA2 is preferably less than the first active area SA1 of the IGBT device 2. It is particularly preferable that the second active area SA2 is 0.1 times or more and 0.6 times or less the first active area SA1. In this case, the second active area SA2 is 0.1 times or more and 0.2 times or less, 0.2 times or more and 0.3 times or less, 0.3 times or more and 0.4 times or less, or 0. It may have a value belonging to any one of the ranges of .4 times to 0.5 times, and 0.5 times to 0.6 times.
  • the MISFET structure 48 includes a p-type body region 49 formed in the surface layer of the first main surface 41 in the second active region 47 .
  • Body region 49 may also be referred to as a "channel region.”
  • the body region 49 is formed in a layered shape extending along the first main surface 41 over the entire second active region 47 .
  • the MISFET structure 48 includes a plurality of second trench structures 50 formed on the first main surface 41 in the second active region 47 .
  • the gate potential Vg of the IGBT device 2 is applied to the plurality of second trench structures 50 .
  • the plurality of second trench structures 50 control channel inversion and non-inversion. That is, the MISFET structure 48 is of a trench gate type.
  • Second trench structure 50 may be referred to as a "second trench gate structure.”
  • the plurality of second trench structures 50 are arranged at intervals in the first direction X, and are each formed in a band shape extending in the second direction Y.
  • the plurality of second trench structures 50 penetrate the body region 49 to reach the first semiconductor region 44 and are formed at intervals from the bottom of the first semiconductor region 44 toward the first main surface 41 side.
  • the plurality of second trench structures 50 are preferably shallower than the plurality of first trench structures 20 of the IGBT device 2.
  • the depth of each second trench structure 50 may be 0.1 ⁇ m or more and 3 ⁇ m or less.
  • the depth of each second trench structure 50 is 0.1 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.5 ⁇ m or less, and 2. It may have a value belonging to any one of the ranges of 5 ⁇ m or more and 3 ⁇ m or less.
  • the depth of each first trench structure 20 is preferably 0.5 ⁇ m or more and 1.5 ⁇ m or less.
  • Each second trench structure 50 includes a second trench 51, a second insulating film 52, and a second buried electrode 53.
  • the second trench 51 is formed on the first main surface 41 and partitions the wall surface of the second trench structure 50.
  • the second insulating film 52 covers the wall surface of the second trench 51 in the form of a film.
  • the second insulating film 52 may include a silicon oxide film.
  • the second buried electrode 53 is buried in the second trench 51 with the second insulating film 52 interposed therebetween. In this form, the second buried electrode 53 includes conductive polysilicon.
  • the MISFET structure 48 includes a plurality of third trench structures 60 formed on the first main surface 41 in the second active region 47 .
  • the emitter potential Ve of the IGBT device 2 as the source potential Vs is applied to the plurality of third trench structures 60.
  • Third trench structure 60 may be referred to as a "trench source structure.”
  • the plurality of third trench structures 60 are each arranged in a region between two adjacent second trench structures 50.
  • the plurality of third trench structures 60 are arranged alternately with the plurality of second trench structures 50 in the first direction X in plan view, and are each formed in a band shape extending in the second direction Y.
  • the plurality of third trench structures 60 penetrate the body region 49 to reach the first semiconductor region 44 and are formed at intervals from the bottom of the first semiconductor region 44 toward the first main surface 41 side.
  • Each third trench structure 60 has a depth greater than or equal to the depth of each second trench structure 50.
  • Each third trench structure 60 is deeper than each second trench structure 50 in this configuration.
  • the depth of each third trench structure 60 is preferably 1.5 times or more and 3 times or less the depth of each second trench structure 50.
  • each third trench structure 60 is shallower than each first trench structure 20 of the IGBT device 2.
  • the depth of each third trench structure 60 may be 0.5 ⁇ m or more and 5 ⁇ m or less.
  • the depth of each third trench structure 60 has a value belonging to any one of the following ranges: 0.5 ⁇ m to 1 ⁇ m, 1 ⁇ m to 2 ⁇ m, 2 ⁇ m to 3 ⁇ m, 3 ⁇ m to 4 ⁇ m, and 4 ⁇ m to 5 ⁇ m. You may do so.
  • the depth of each third trench structure 60 is preferably 1 ⁇ m or more and 2.5 ⁇ m or less.
  • Each third trench structure 60 includes a third trench 61, a third insulating film 62, and a third buried electrode 63.
  • the third trench 61 is formed in the first main surface 41 and partitions the wall surface of the third trench structure 60.
  • the third insulating film 62 covers the wall surface of the third trench 61 in the form of a film.
  • the third insulating film 62 may include a silicon oxide film.
  • the third buried electrode 63 is buried in the third trench 61 with the third insulating film 62 interposed therebetween. In this form, the third buried electrode 63 includes conductive polysilicon.
  • the MISFET structure 48 includes a plurality of n-type source regions 64 formed in a region along the plurality of second trench structures 50 in the surface layer portion of the body region 49 .
  • Each source region 64 has a higher n-type impurity concentration than the first semiconductor region 44 .
  • Each source region 64 is formed in a region between adjacent second trench structure 50 and third trench structure 60 in the surface layer portion of body region 49 .
  • Each source region 64 forms a MISFET channel in the body region 49 together with the first semiconductor region 44 .
  • the MISFET structure 48 includes a plurality of p-type well regions 65 formed in regions along the plurality of third trench structures 60 within the second chip 40.
  • Well region 65 has a higher p-type impurity concentration than body region 49 in this form.
  • the p-type impurity concentration of well region 65 may be lower than that of body region 49.
  • the plurality of well regions 65 cover the wall surface of the third trench structure 60 within the second chip 40 and are electrically connected to the body region 49 in the surface layer portion of the first main surface 41.
  • the plurality of well regions 65 are formed at intervals from the bottom of the first semiconductor region 44 toward the first main surface 41 side, and face the second semiconductor region 45 with a part of the first semiconductor region 44 in between. .
  • the plurality of well regions 65 form a pn junction with the first semiconductor region 44 .
  • the MISFET structure 48 includes a plurality of p-type second contact regions 66 formed in regions along the plurality of third trench structures 60 within the plurality of well regions 65 .
  • Second contact region 66 has a higher p-type impurity concentration than body region 49 .
  • the p-type impurity concentration of the second contact region 66 is higher than that of the well region 65.
  • the plurality of second contact regions 66 cover the wall surfaces of the corresponding third trench structures 60 within the corresponding well regions 65.
  • the plurality of second contact regions 66 are drawn out from within the corresponding well region 65 to the surface layer portion of the body region 49 along the wall surface of the corresponding third trench structure 60 and exposed from the first main surface 41 .
  • the MISFET device 3 includes a second interlayer insulating film 67 covering the first main surface 41.
  • the second interlayer insulating film 67 includes a second lower insulating film 68 and a second upper insulating film 69.
  • the second lower insulating film 68 is connected to the second insulating film 52 and the third insulating film 62 and covers the first main surface 41 so as to expose the second buried electrode 53 and the third buried electrode 63. .
  • the second lower insulating film 68 may include a silicon oxide film.
  • the second upper insulating film 69 covers the second lower insulating film 68 so as to cover the plurality of second trench structures 50 and the plurality of third trench structures 60 .
  • the second upper insulating film 69 may include a silicon oxide film.
  • the second upper insulating film 69 is thicker than the second lower insulating film 68.
  • the MISFET device 3 includes a second gate electrode 72 disposed on the second interlayer insulating film 67.
  • the gate potential Vg of the IGBT device 2 is applied to the second gate electrode 72 from the outside.
  • the second gate electrode 72 is arranged in a region along the center of the third side surface 43C in plan view.
  • the second gate electrode 72 can be arranged at any location.
  • the second gate electrode 72 may be arranged in a region along the corner of the second chip 40 or in the center of the second chip 40 in plan view.
  • the second gate electrode 72 faces a region outside the second active region 47 with the second interlayer insulating film 67 in between.
  • the second gate electrode 72 may face the second active region 47 (that is, the plurality of second trench structures 50 and the plurality of third trench structures 60) with the second interlayer insulating film 67 in between.
  • the second gate electrode 72 is formed into a rectangular shape in plan view.
  • the second gate electrode 72 may be formed in a circular or polygonal shape in plan view.
  • the second gate electrode 72 includes a different conductive material from the second buried electrode 53.
  • the second gate electrode 72 may include at least one of a Ti-based metal film, an Al-based metal film, and a Cu-based metal film.
  • the second gate electrode 72 has a stacked structure including a Ti-based metal film and an Al-based metal film stacked in this order from the second interlayer insulating film 67 side.
  • the second gate electrode 72 may be referred to as a "second gate metal.”
  • the MISFET device 3 includes a second gate wiring 73 placed on the second interlayer insulating film 67.
  • the second gate wiring 73 is electrically connected to the second gate electrode 72 and the plurality of second trench structures 50 and transmits the gate potential Vg applied to the second gate electrode 72 to the plurality of second trench structures 50. .
  • the second gate wiring 73 is drawn out from the second gate electrode 72 onto the second interlayer insulating film 67 in a plan view, and intersects (specifically, It extends in a band shape along the first to third side surfaces 43A to 43C so as to be perpendicular to each other.
  • the second gate wiring 73 penetrates the second interlayer insulating film 67 and is electrically connected to the plurality of second trench structures 50 .
  • the second gate wiring 73 includes the same conductive material as the second gate electrode 72.
  • the MISFET device 3 includes a source electrode 74 placed on the second interlayer insulating film 67.
  • the emitter potential Ve of the IGBT device 2 is applied to the source electrode 74 as the source potential Vs.
  • the source electrode 74 is disposed on the second interlayer insulating film 67 in a region surrounded by the second gate electrode 72 and the second gate wiring 73 so as to cover the second active region 47 .
  • the source electrode 74 faces the plurality of second trench structures 50 with the second interlayer insulating film 67 in between, and penetrates the second interlayer insulating film 67 to form the plurality of third trench structures 60, the plurality of source regions 64, and the plurality of source regions 64. is electrically connected to the second contact region 66 of the second contact region 66 of
  • the source electrode 74 includes the same conductive material as the second gate electrode 72.
  • Source electrode 74 may be referred to as a "source metal.”
  • the source electrode 74 has a planar shape that is substantially similar to the planar shape of the second active region 47 . If the planar shape of the source electrode 74 is substantially similar to the planar shape of the second active region 47, the above-mentioned second active area SA2 may be defined by the planar area of the source electrode 74.
  • the MISFET device 3 includes a drain electrode 75 covering the second main surface 42.
  • the drain electrode 75 is applied with the collector potential Vc of the IGBT device 2 as the drain potential Vd.
  • the drain electrode 75 forms an ohmic contact with the second semiconductor region 45 exposed from the second main surface 42 .
  • the drain electrode 75 may cover the entire second main surface 42 so as to be continuous with the peripheral edge (first to fourth side surfaces 43A to 43D) of the second chip 40.
  • the output current IO of the semiconductor module 1 is adjusted by adjusting the chip area ratio S2/S1 of the second chip area S2 of the MISFET device 3 to the first chip area S1 of the IGBT device 2. That is, the output current IO is adjusted by adjusting the active area ratio SA2/SA1 of the second active area SA2 of the MISFET device 3 to the first active area SA1 of the IGBT device 2.
  • the current generation ability improves accordingly, and a high current
  • the loss of the MISFET device 3 in the region increases. For example, when a drain current Ids near the maximum rated value of the collector current Ice of the IGBT device 2 is generated in the MISFET device 3, the loss of the MISFET device 3 in the high current region becomes extremely high. In these cases, there is little benefit in connecting the MISFET device 3 in parallel to the IGBT device 2.
  • the semiconductor module 1 can be incorporated into an inverter, a DC/DC converter, or a PFC (power factor correction) circuit as one usage mode.
  • a collector current Ice of 20% to 40% of the maximum rated value is generally used.
  • a collector current Ice of 30% to 50% of the maximum rated value is generally used.
  • the MISFET device 3 Since the MISFET device 3 is assumed to be used in a low current region, it is required to efficiently generate a drain current Ids in a current range even lower than the above current range. Therefore, there is little benefit in enlarging the second chip area S2 (second active area SA2) of the MISFET device 3.
  • the second chip area S2 (second active area SA2) of the MISFET device 3 is set to be less than the first chip area S1 (first active area SA1) of the IGBT device 2. It is preferable that It is particularly preferable that the chip area ratio S2/S1 (active area ratio SA2/SA1) is 0.1 or more and 0.6 or less.
  • the MISFET device 3 is assumed to be used in a low current region, it is required to be smaller than the IGBT device 2, while the MISFET device 3 is required to be smaller than the IGBT device 2, which is assumed to be used in a high current operation. Since they are connected in parallel, a withstand voltage higher than the withstand voltage of the IGBT device 2 is required.
  • the MISFET device 3 has a second breakdown voltage VB2 that is higher than the first breakdown voltage VB1 of the IGBT device 2.
  • the MISFET device 3 having the requirements of small size and high breakdown voltage is achieved by employing the second chip 40 made of a wide bandgap semiconductor (SiC in this embodiment).
  • FIG. 11A is a graph showing current-voltage characteristics according to the first adjustment example of the semiconductor module 1 shown in FIG. 1.
  • FIG. 11B is a graph showing current-voltage characteristics according to the second adjustment example of the semiconductor module 1 shown in FIG.
  • FIG. 11C is a graph showing current-voltage characteristics according to the third adjustment example of the semiconductor module 1 shown in FIG. 1.
  • the vertical axis represents collector current Ice (drain current Ids)
  • the horizontal axis represents collector voltage Vce (drain voltage Vds).
  • a first characteristic C1, a second characteristic C2, and a third characteristic C3 are shown in FIGS. 11A to 11C, respectively.
  • the first characteristic C1 indicates the individual collector current Ice when the IGBT device 2 is used alone.
  • the second characteristic C2 indicates the individual drain current Ids when the MISFET device 3 is used alone.
  • the third characteristic C3 indicates the output current IO when a parallel switching circuit including the IGBT device 2 and the MISFET device 3 is used.
  • the output current IO is the sum of the individual collector current Ice and the individual drain current Ids.
  • FIG. 11A shows the first to third characteristics C1 to C3 when the chip area ratio S2/S1 (active area ratio SA2/SA1) is adjusted to 0.1.
  • FIG. 11B shows first to third characteristics C1 to C3 when the chip area ratio S2/S1 (active area ratio SA2/SA1) is adjusted to 0.3.
  • FIG. 11C shows the first to third characteristics C1 to C3 when the chip area ratio S2/S1 (active area ratio SA2/SA1) is adjusted to 0.6.
  • the individual drain current Ids (individual collector current Ice) at the intersection P of the first characteristic C1 and the second characteristic C2 is set to the first current value A, and when the built-in voltage Vbi is applied (specifically Specifically, the individual drain current Ids (when a drain voltage Vds equal to the built-in voltage Vbi is applied) is set to the second current value B (B ⁇ A).
  • the current ratio A/B of the first current value A to the second current value B is preferably greater than 1 and 3 or less (1 ⁇ A/B ⁇ 3).
  • the current ratio A/B is greater than 1 and less than or equal to 1.25, more than 1.25 and less than 1.5, more than 1.5 and less than 1.75, more than 1.75 and less than 2, more than 2 and less than 2.25, and 2. It may have a value belonging to any one of the ranges of 25 to 2.5, 2.5 to 2.75, and 2.75 to 3. It is particularly preferable that the current ratio A/B is 1.1 or more and 2.6 or less.
  • the difference value (AB) between the first current value A and the second current value B is preferably 0.5A or more and 30A or less.
  • the difference value (A-B) is either 0.5A or more and 1A or less, 1A or more and 5A or less, 5A or more and 10A or less, 10A or more and 15A or less, 15A or more and 20A or less, 20A or more and 25A or less, and 25A or more and 30A or less. It may have values that belong to one range.
  • the slope of the straight line connecting the first current value A and the second current value B is preferably greater than 1 and 30 or less.
  • the slope of the straight line connecting the first current value A and the second current value B is greater than 1 and less than or equal to 5, greater than or equal to 5 and less than or equal to 10, greater than or equal to 10 and less than or equal to 15, greater than or equal to 15 and less than or equal to 20, greater than or equal to 20 and less than or equal to 25, and greater than or equal to 25 and less than or equal to 30 It may have a value belonging to any one of the following ranges.
  • the first current value A is adjusted to 4.2A
  • the second current value B is adjusted to 3.3A.
  • the built-in voltage Vbi is 0.6V
  • the collector voltage Vce (drain voltage Vds) at the intersection P is 0.9V.
  • the current ratio A/B is 1.27.
  • the difference value (AB) between the first current value A and the second current value B is 0.9A.
  • the slope of the straight line connecting the first current value A and the second current value B is 3.
  • the first current value A is adjusted to 16A
  • the second current value B is adjusted to 10.7A.
  • the built-in voltage Vbi is 0.6V
  • the collector voltage Vce (drain voltage Vds) at the intersection P is 1.16V.
  • the current ratio A/B is 1.5.
  • the difference value (AB) between the first current value A and the second current value B is 5.3A.
  • the slope of the straight line connecting the first current value A and the second current value B is 9.46.
  • the first current value A is adjusted to 46A
  • the second current value B is adjusted to 22.8A.
  • the built-in voltage Vbi is 0.6V
  • the collector voltage Vce (drain voltage Vds) at the intersection P is 1.7V.
  • the current ratio A/B is 2.02.
  • the difference value (AB) between the first current value A and the second current value B is 23.2A.
  • the slope of the straight line connecting the first current value A and the second current value B is 21.1.
  • the semiconductor module 1 includes the IGBT device 2 and the MISFET device 3.
  • the MISFET device 3 and the IGBT device 2 constitute a parallel circuit.
  • the semiconductor module 1 generates the drain current Ids of the MISFET device 3 in a voltage range below the built-in voltage Vbi of the IGBT device 2, and generates the collector current Ice and A drain current Ids of the MISFET device 3 is generated.
  • the drain current Ids of the MISFET device 3 is used in the low current region, so the loss of the IGBT device 2 in the low current region is reduced. Furthermore, since the collector current Ice of the IGBT device 2 and the drain current Ids of the MISFET device 3 are used in the high current region, the loss of the MISFET device 3 in the high current region is reduced. Therefore, it is possible to provide a semiconductor module 1 with improved electrical characteristics.
  • the IGBT device 2 has a first breakdown voltage VB1
  • the MISFET device 3 has a second breakdown voltage VB2 that is higher than the first breakdown voltage VB1.
  • the MISFET device 3 which is intended to be used in a low voltage and low current environment, can be appropriately used in combination with the IGBT device 2, which is intended to be used in a high voltage and high current environment.
  • the first breakdown voltage VB1 may be greater than or equal to 500V and less than or equal to 1500V.
  • the second breakdown voltage VB2 may be greater than or equal to 500V and less than or equal to 3000V.
  • the IGBT device 2 preferably includes a first chip 10 made of Si. According to this structure, a relatively inexpensive IGBT device 2 can be used.
  • the MISFET device 3 preferably includes a second chip 40 made of a wide bandgap semiconductor. According to the wide bandgap semiconductor, it is possible to simultaneously increase the breakdown voltage and reduce the size of the second chip 40 with ease. Therefore, a high-voltage MISFET device 3 suitable for the usage environment of the IGBT device 2 can be easily realized. It is particularly preferred that the wide bandgap semiconductor is SiC.
  • the first chip 10 has a first chip area S1
  • the second chip 40 has a second chip area S2, which is smaller than the first chip area S1.
  • the current generation ability of the MISFET device 3 can be limited. Thereby, the loss of the MISFET device 3 in the low current region can be appropriately reduced.
  • the second chip area S2 is 0.1 times or more and 0.6 times or less the first chip area S1.
  • the second chip 40 may be thinner than the first chip 10.
  • the second chip 40 may be thicker than the first chip 10.
  • the individual drain at the intersection P of the first characteristic C1 and the second characteristic C2 When the current Ids (individual collector current Ice) is set to the first current value A and the individual drain current Ids when the built-in voltage Vbi is applied is set to the second current value B (B ⁇ A), the second current value B
  • the current ratio A/B of the first current value A to the first current value A is preferably greater than 1 and 3 or less (1 ⁇ A/B ⁇ 3). According to this structure, both the loss in the low current region and the loss in the high current region can be appropriately reduced.
  • the form of the semiconductor module 1 is arbitrary as long as it can configure a parallel switching circuit of the IGBT device 2 and the MISFET device 3, and is not limited to a specific form. Below, an example of the configuration of the semiconductor module 1 will be shown.
  • FIG. 12 is a perspective view showing an example of the configuration of the semiconductor module 1.
  • FIG. 13 is a plan view showing the internal structure of the semiconductor module 1 shown in FIG. 12.
  • the semiconductor module 1 has a TO-220 package form in this embodiment.
  • the semiconductor module 1 includes a resin package body 80 formed in a hexahedral shape (specifically, a rectangular parallelepiped shape).
  • the package body 80 may be made of thermosetting resin (eg, epoxy resin).
  • the package body 80 has a first surface 81 on one side, a second surface 82 on the other side, and first to fourth side walls 83A to 83D connecting the first surface 81 and the second surface 82.
  • the first surface 81 and the second surface 82 are formed into a rectangular shape when viewed from above in the normal direction Z.
  • the first side wall 83A and the second side wall 83B extend in the first direction X and face each other in the second direction Y that is orthogonal to the first direction X.
  • the third side wall 83C and the fourth side wall 83D extend in the second direction Y and face the first direction X.
  • the semiconductor module 1 includes a metal support electrode 84 disposed within the package body 80.
  • the support electrode 84 may be exposed from the second surface 82.
  • Support electrode 84 includes a support section 85 and a lead-out section 86 .
  • the support portion 85 is arranged within the package body 80.
  • the drawer portion 86 is drawn out from the support portion 85 toward the third side wall 83C, passes through the third side wall 83C, and is located outside the package body 80.
  • the drawer portion 86 has a circular through hole.
  • the semiconductor module 1 includes a plurality (three in this embodiment) of metal wiring electrodes 87 drawn out from the inside of the package body 80.
  • the plurality of wiring electrodes 87 are arranged on the fourth side wall 83D side with respect to the support electrode 84.
  • the plurality of wiring electrodes 87 are each formed in a band shape extending in a direction perpendicular to the fourth side wall 83D (that is, the first direction X).
  • the wiring electrodes 87 on both sides are spaced apart from the supporting electrode 84, and the central wiring electrode 87 is formed integrally with the supporting electrode 84.
  • the wiring electrode 87 connected to the support electrode 84 may be arranged at any location.
  • the plurality of wiring electrodes 87 include an emitter wiring electrode 87e, a gate wiring electrode 87g, and a collector wiring electrode 87c.
  • Emitter wiring electrode 87e may be referred to as a "source terminal” or “emitter source terminal.”
  • the collector wiring electrode 87c may be referred to as a "drain terminal” or a “collector drain terminal.”
  • the emitter wiring electrode 87e is arranged on the second side wall 83B side
  • the gate wiring electrode 87g is arranged on the first side wall 83A side
  • the collector wiring electrode 87c is arranged between the emitter wiring electrode 87e and the gate wiring electrode 87g. has been done.
  • the semiconductor module 1 includes the above-described IGBT device 2 arranged on the support electrode 84 (support part 85) within the package body 80.
  • the IGBT device 2 is arranged in a region on the first side wall 83A side with respect to the center portion of the support electrode 84. In other words, the IGBT device 2 is placed close to the gate wiring electrode 87g.
  • the IGBT device 2 is placed on the support electrode 84 with the collector electrode 35 facing the support electrode 84. Further, the IGBT device 2 is arranged on the support electrode 84 with the first gate electrode 32 facing the fourth side wall 83D side in plan view. Collector electrode 35 is electrically connected to support electrode 84 .
  • the IGBT device 2 is arranged at a first distance from the gate wiring electrode 87g and at a second distance, which is larger than the first distance, from the emitter wiring electrode 87e.
  • the IGBT device 2 faces the gate wiring electrode 87g in the first direction X, and does not face the emitter wiring electrode 87e in the first direction X.
  • the IGBT device 2 may face the collector wiring electrode 87c in the first direction X.
  • the semiconductor module 1 includes the above-described MISFET device 3 arranged on the support electrode 84 (support part 85) at a distance from the IGBT device 2 within the package body 80.
  • the MISFET device 3 is arranged on the second side wall 83B side with respect to the IGBT device 2, and faces the IGBT device 2 in the second direction Y. In other words, the MISFET device 3 is placed closer to the emitter wiring electrode 87e than the IGBT device 2 is.
  • the MISFET device 3 is arranged on the support electrode 84 with the drain electrode 75 facing the support electrode 84. Further, the MISFET device 3 is arranged on the support electrode 84 with the second gate electrode 72 facing the fourth side wall 83D side in plan view.
  • the drain electrode 75 is electrically connected to the collector electrode 35 of the IGBT device 2 via the support electrode 84, and is electrically connected to the collector wiring electrode 87c via the support electrode 84.
  • the MISFET device 3 is arranged at a third distance from the gate wiring electrode 87g and at a fourth distance smaller than the third distance from the emitter wiring electrode 87e. In this form, the MISFET device 3 faces the emitter wiring electrode 87e in the first direction X, and does not face the gate wiring electrode 87g in the first direction X. The MISFET device 3 may face the collector wiring electrode 87c in the first direction X.
  • the semiconductor module 1 includes a first conductive adhesive 88 interposed between the support electrode 84 (support part 85) and the collector electrode 35.
  • First conductive adhesive 88 may include solder or metal paste.
  • the solder may be lead-free solder.
  • the metal paste may contain at least one of Au, Ag, and Cu.
  • the Ag paste may consist of Ag sintered paste.
  • the Ag sintering paste consists of a paste in which nano-sized or micro-sized Ag particles are added to an organic solvent.
  • the semiconductor module 1 includes a second conductive adhesive 89 interposed between the support electrode 84 (support part 85) and the drain electrode 75.
  • the second conductive adhesive 89 may include solder or metal paste.
  • the solder may be lead-free solder.
  • the metal paste may contain at least one of Au, Ag, and Cu.
  • the Ag paste may consist of Ag sintered paste.
  • the semiconductor module 1 includes a plurality of first to fourth conductive connection members 90A to 90D arranged within the package body 80.
  • the plurality of first to fourth conductive connection members 90A to 90D are made of metal wires (that is, bonding wires).
  • the plurality of first to fourth conductive connection members 90A to 90D may include at least one of a gold wire, a copper wire, and an aluminum wire.
  • at least one or all of the plurality of first to fourth conductive connection members 90A to 90D may be made of a metal plate such as a metal clip instead of a metal wire.
  • the first conductive connection member 90A is electrically and mechanically connected to the source electrode 74 and emitter wiring electrode 87e of the MISFET device 3.
  • the second conductive connection member 90B is electrically and mechanically connected to the second gate electrode 72 and the gate wiring electrode 87g of the MISFET device 3.
  • the third conductive connection member 90C is electrically connected to the emitter electrode 34 of the IGBT device 2 and the emitter wiring electrode 87e. Specifically, the third conductive connection member 90C is electrically and mechanically connected to the first connection portion 91 that is electrically and mechanically connected to the emitter electrode 34 of the IGBT device 2 and to the source electrode 74 of the MISFET device 3. The emitter wiring electrode 87e is electrically connected to the emitter wiring electrode 87e via the first conductive connecting member 90A.
  • the second connection portion 92 of the third conductive connection member 90C is joined to the first conductive connection member 90A above the source electrode 74. That is, the third conductive connection member 90C is electrically connected to the emitter wiring electrode 87e via the first conductive connection member 90A by a stitch wire method.
  • the third conductive connection member 90C may be directly electrically and mechanically connected to the emitter electrode 34 and the emitter wiring electrode 87e.
  • the fourth conductive connection member 90D is electrically and mechanically connected to the first gate electrode 32 and the gate wiring electrode 87g of the IGBT device 2.
  • FIG. 14 is a plan view showing another example of the configuration of the semiconductor module 1.
  • FIG. 14 shows a semiconductor module 1 according to the first embodiment in which the locations of the IGBT device 2 and the MISFET device 3 are exchanged. That is, in this embodiment, the IGBT device 2 is arranged in a region on the second side wall 83B side with respect to the central portion of the support electrode 84. Further, the IGBT device 2 is arranged at a position close to the emitter wiring electrode 87e.
  • the IGBT device 2 is arranged at a first distance from the emitter wiring electrode 87e and at a second distance, which is larger than the first distance, from the gate wiring electrode 87g. In this form, the IGBT device 2 faces the emitter wiring electrode 87e in the first direction X, and does not face the gate wiring electrode 87g in the first direction X. The IGBT device 2 may face the collector wiring electrode 87c in the first direction X.
  • the MISFET device 3 is arranged on the first side wall 83A side with respect to the IGBT device 2, and faces the IGBT device 2 in the second direction Y. In other words, the MISFET device 3 is placed closer to the gate wiring electrode 87g than the IGBT device 2 is.
  • the MISFET device 3 is arranged at a third distance from the emitter wiring electrode 87e and at a fourth distance smaller than the third distance from the gate wiring electrode 87g. In this form, the MISFET device 3 faces the gate wiring electrode 87g in the first direction X, and does not face the emitter wiring electrode 87e in the first direction X. The MISFET device 3 may face the collector wiring electrode 87c in the first direction X.
  • the first conductive connection member 90A is electrically and mechanically connected to the emitter electrode 34 and the emitter wiring electrode 87e of the IGBT device 2.
  • the second conductive connection member 90B is electrically and mechanically connected to the first gate electrode 32 and the gate wiring electrode 87g of the IGBT device 2.
  • the third conductive connection member 90C is electrically connected to the source electrode 74 and emitter wiring electrode 87e of the MISFET device 3. Specifically, the third conductive connection member 90C is electrically and mechanically connected to the first connection portion 93 that is electrically and mechanically connected to the source electrode 74 of the MISFET device 3 and to the emitter electrode 34 of the IGBT device 2. The emitter wiring electrode 87e is electrically connected to the emitter wiring electrode 87e via the first conductive connecting member 90A.
  • the second connection portion 94 of the third conductive connection member 90C is joined to the first conductive connection member 90A on the emitter electrode 34. That is, the third conductive connection member 90C is electrically connected to the emitter wiring electrode 87e via the first conductive connection member 90A by a stitch wire method.
  • the third conductive connection member 90C may be directly electrically and mechanically connected to the source electrode 74 and the emitter wiring electrode 87e.
  • the fourth conductive connection member 90D is electrically and mechanically connected to the second gate electrode 72 and the gate wiring electrode 87g of the MISFET device 3.
  • the bending angle in the extending direction of the third conductive connecting member 90C with respect to the extending direction of the first conductive connecting member 90A may be changed as shown in FIG. It may become smaller (sudden) compared to the case of the semiconductor module 1 according to the above. Therefore, when considering the bending angle of the second conductive connection member 90B with respect to the first conductive connection member 90A, the IGBT device 2 and the MISFET device 3 are preferably arranged in the semiconductor module 1 according to FIG. 13.
  • FIG. 15 is a plan view showing still another configuration example of the semiconductor module 1.
  • the semiconductor module 1 includes a first semiconductor module 1A and a second semiconductor module 1B.
  • the first semiconductor module 1A includes a package body 80, a support electrode 84, a plurality of wiring electrodes 87, an IGBT device 2, a first conductive adhesive 88, a first conductive connection member 90A, and a second conductive connection member 90B.
  • the first conductive connection member 90A is electrically and mechanically connected to the emitter electrode 34 and the emitter wiring electrode 87e.
  • the second conductive connection member 90B is electrically and mechanically connected to the first gate electrode 32 and the gate wiring electrode 87g.
  • the second semiconductor module 1B includes a package body 80, a support electrode 84, a plurality of wiring electrodes 87, a MISFET device 3, a second conductive adhesive 89, a third conductive connection member 90C, and a fourth conductive connection member 90D.
  • the third conductive connection member 90C is electrically and mechanically connected to the source electrode 74 and the emitter wiring electrode 87e.
  • the fourth conductive connection member 90D is electrically and mechanically connected to the second gate electrode 72 and the gate wiring electrode 87g.
  • the emitter wiring electrode 87e of the second semiconductor module 1B is electrically connected to the emitter wiring electrode 87e of the first semiconductor module 1A.
  • the gate wiring electrode 87g of the second semiconductor module 1B is electrically connected to the gate wiring electrode 87g of the first semiconductor module 1A.
  • the collector wiring electrode 87c of the second semiconductor module 1B is electrically connected to the collector wiring electrode 87c of the first semiconductor module 1A.
  • the "package body 80," the “support electrode 84,” and the “plurality of wiring electrodes 87 (emitter wiring electrode 87e, gate wiring electrode 87g, and collector wiring electrode 87c)" related to the first semiconductor module 1A are referred to as the "first package body”. , may be referred to as a “first electrode” and “a plurality of first terminals (a first emitter terminal, a first gate terminal, and a first collector terminal)."
  • the "package body 80," the "support electrode 84,” and the “plurality of wiring electrodes 87 (emitter wiring electrode 87e, gate wiring electrode 87g, and collector wiring electrode 87c)" related to the second semiconductor module 1B are referred to as the "second package body”. , may also be referred to as a “second electrode plate” and "a plurality of second terminals (second emitter terminal, second gate terminal, and second collector terminal)."
  • FIG. 16 is a sectional view showing another configuration example of the IGBT device 2.
  • the IGBT device 2 is an RC-IGBT device (Reverse Conducting-IGBT device) that integrally includes an IGBT and a freewheeling diode (pn junction diode).
  • RC-IGBT device Reverse Conducting-IGBT device
  • freewheeling diode pn junction diode
  • the IGBT device 2 includes one or more (preferably more than one) IGBT structures 18 provided in the first active region 17 and one or more (preferably more than one) diodes provided in the first active region 17.
  • a structure 100 is included.
  • the first active area SA1 of the first active region 17 is the planar area of the polygonal region. defined by
  • the plurality of IGBT structures 18 may each be formed in a rectangular shape in plan view.
  • the plurality of diode structures 100 may each be formed in a rectangular shape in plan view.
  • the plurality of IGBT structures 18 may be arranged in a matrix or in a staggered manner at intervals in the first direction X and the second direction Y in a plan view.
  • the plurality of diode structures 100 may be arranged at intervals in the first direction X and the second direction Y so as to be adjacent to at least one IGBT structure 18.
  • the plurality of diode structures 100 may be arranged alternately with the plurality of IGBT structures 18 in the first direction X.
  • Each IGBT structure 18 includes a base region 19, a plurality of first trench structures 20, a plurality of emitter regions 24, a plurality of contact holes 25, and a plurality of first contact regions 26. Descriptions of these specific configurations are omitted because they are as described above.
  • Each diode structure 100 includes an n-type cathode region 101 formed in the surface layer portion of the second main surface 12.
  • the cathode region 101 has an n-type impurity concentration higher than the p-type impurity concentration of the collector region 16, and is a region in which the conductivity type of a portion of the collector region 16 is replaced from the p-type to the n-type.
  • the cathode region 101 has a higher n-type impurity concentration than the semiconductor region 14 (buffer region 15).
  • the cathode region 101 is formed in a layered shape extending along the second main surface 12 and is exposed from the second main surface 12 . Cathode region 101 penetrates collector region 16 so as to be electrically connected to semiconductor region 14 (buffer region 15).
  • Each diode structure 100 includes a p-type anode region 102 formed in the surface layer of the first main surface 11.
  • Anode region 102 may have approximately the same p-type impurity concentration as base region 19.
  • the p-type impurity concentration of the anode region 102 may be higher than the p-type impurity concentration of the base region 19 or lower than the p-type impurity concentration of the base region 19.
  • the anode region 102 is formed in a layer shape extending along the first main surface 11 so as to face the cathode region 101 in the thickness direction of the first chip 10, and is exposed from the first main surface 11.
  • the anode region 102 is shallower than the plurality of first trench structures 20 .
  • Anode region 102 may have approximately the same depth as base region 19.
  • the anode region 102 may be formed deeper than the base region 19.
  • the anode region 102 forms a pn junction with the semiconductor region 14.
  • a pn junction diode is formed in which the anode region 102 serves as an anode and the cathode region 101 serves as a cathode.
  • Each diode structure 100 includes a plurality of fourth trench structures 110 formed on the first main surface 11.
  • a potential (emitter potential Ve in this form) different from that of the first trench structure 20 (gate potential Vg) is applied to the fourth trench structure 110.
  • Fourth trench structure 110 may be referred to as an "emitter trench structure” or an “anode trench structure.”
  • the plurality of fourth trench structures 110 are arranged at intervals in the first direction X, and are each formed in a band shape extending in the second direction Y.
  • the plurality of fourth trench structures 110 are formed on the first main surface 11 so as to penetrate the anode region 102 and reach the semiconductor region 14 .
  • each fourth trench structure 110 has a depth approximately equal to the depth of each first trench structure 20.
  • each fourth trench structure 110 may be 0.5 ⁇ m or more and 10 ⁇ m or less.
  • the depth of each fourth trench structure 110 belongs to any one of the following ranges: 0.5 ⁇ m to 2.5 ⁇ m, 2.5 ⁇ m to 5 ⁇ m, 5 ⁇ m to 7.5 ⁇ m, and 7.5 ⁇ m to 10 ⁇ m. It may have a value.
  • the depth of each fourth trench structure 110 is preferably 4 ⁇ m or more and 8 ⁇ m or less.
  • Each fourth trench structure 110 includes a fourth trench 111, a fourth insulating film 112, and a fourth buried electrode 113.
  • the fourth trench 111 is formed in the first main surface 11 and partitions the wall surface of the fourth trench structure 110.
  • the fourth insulating film 112 covers the wall surface of the fourth trench 111 in the form of a film.
  • the fourth insulating film 112 may include a silicon oxide film.
  • the fourth buried electrode 113 is buried in the fourth trench 111 with the fourth insulating film 112 interposed therebetween. In this form, the fourth buried electrode 113 includes conductive polysilicon.
  • the first interlayer insulating film 27 described above includes diode openings 114 that expose each diode structure 100.
  • Diode openings 114 expose anode region 102 and a plurality of fourth trench structures 110 in each diode structure 100.
  • the diode opening 114 exposes all of the fourth trench structure 110.
  • the aforementioned emitter electrode 34 is electrically connected to the plurality of emitter regions 24 and the plurality of first contact regions 26 via the plurality of contact electrodes 31 on the first interlayer insulating film 27 .
  • the emitter electrode 34 enters the diode opening 114 from above the first interlayer insulating film 27 .
  • the emitter electrode 34 is electrically connected to the anode region 102 and the plurality of fourth trench structures 110 within the diode opening 114.
  • the collector electrode 35 described above forms ohmic contact with the collector region 16 and cathode region 101 exposed from the second main surface 12 .
  • FIG. 17 is a sectional view showing another configuration example of the MISFET device 3.
  • MISFET device 3 may have a third trench structure 60 having approximately the same depth as second trench structure 50.
  • FIG. 18 is a sectional view showing another example of the configuration of the MISFET device 3.
  • MISFET device 3 may not include third trench structure 60.
  • the plurality of source regions 64 are formed in a region between two adjacent second trench structures 50 in the surface layer portion of the body region 49 .
  • the well region 65 described above is not formed.
  • the plurality of second contact regions 66 described above are formed in a region between two adjacent second trench structures 50 in the surface layer portion of the body region 49.
  • the aforementioned source electrode 74 penetrates the second interlayer insulating film 67 and is electrically connected to the plurality of source regions 64 and the plurality of second contact regions 66 .
  • FIG. 19 is a sectional view showing another configuration example of the MISFET device 3.
  • MISFET device 3 may include a second semiconductor region 45 having a thickness smaller than the thickness of first semiconductor region 44 inside second chip 40. That is, the second chip 40 may include a semiconductor substrate having a thickness smaller than the thickness of the epitaxial layer.
  • FIG. 20 is a sectional view showing another configuration example of the MISFET device 3.
  • MISFET device 3 may include only first semiconductor region 44 without second semiconductor region 45 inside second chip 40.
  • the first semiconductor region 44 is exposed from the first main surface 41, the second main surface 42, and the first to fourth side surfaces 43A to 43D of the second chip 40. That is, in this form, the second chip 40 does not have a semiconductor substrate and has a single layer structure made of an epitaxial layer.
  • the embodiments described above can be implemented in other forms.
  • the first chip 10 was made of a Si chip.
  • the first chip 10 may be a wide bandgap semiconductor chip made of a single crystal wide bandgap semiconductor chip.
  • the first chip 10 may be a SiC chip made of SiC single crystal.
  • the second chip 40 is made of a wide bandgap semiconductor chip.
  • the second chip 40 may be made of a Si single crystal Si chip.
  • the trench gate type IGBT device 2 that controls channel inversion and non-inversion inside the first chip 10 was shown.
  • a planar gate type IGBT device 2 that controls channel inversion and non-inversion from above the first main surface 11 of the first chip 10 may be employed.
  • the trench gate type MISFET device 3 that controls channel inversion and non-inversion inside the second chip 40 was shown.
  • a planar gate MISFET device 3 that controls channel inversion and non-inversion from above the first main surface 41 of the second chip 40 may be employed.
  • the "first conductivity type” is “n type” and the “second conductivity type” is “p type”.
  • a configuration may be adopted in which the "first conductivity type” is “p type” and the “second conductivity type” is “n type”. The specific configuration in this case can be obtained by replacing “n type” with “p type” and simultaneously replacing “p type” with “n type” in the above description and accompanying drawings.
  • [A1] includes an IGBT device (2) and a MISFET device (3) forming a parallel circuit with the IGBT device (2), wherein the The drain current (Ids) of the MISFET device (3) is generated, and the collector current (Ice) of the IGBT device (2) and the drain current (Ids) of the MISFET device (3) are generated in a voltage range equal to or higher than the built-in voltage (Vbi). ), a semiconductor module (1) that generates a semiconductor module (1).
  • the IGBT device (2) has a first breakdown voltage (VB1), and the MISFET device (3) has a second breakdown voltage (VB2) higher than the first breakdown voltage (VB1).
  • the IGBT device (2) includes a first chip (10) made of Si, and the MISFET device (3) includes a second chip (40) made of a wide bandgap semiconductor.
  • the semiconductor module (1) according to any one of the above.
  • the first chip (10) has a first chip area (S1)
  • the second chip (40) has a second chip area (S2) smaller than the first chip area (S1).
  • the individual drain current (Ids) at the intersection (P) of the first characteristic (C1) and the second characteristic (C2) is set to a first current value A
  • the current ratio A/B of the first current value A to the second current value B is greater than 1 and less than or equal to 3. (1 ⁇ A/B ⁇ 3)
  • the semiconductor module (1) according to any one of A1 to A9.
  • the semiconductor module (1) according to any one of A1 to A13, wherein the IGBT device (2) is an RC-IGBT device that integrally includes an IGBT and a freewheeling diode.
  • the IGBT device (2) is arranged on the support electrode (84), and the MISFET device (3) is arranged on the support electrode (84).
  • the semiconductor module (1) according to any one of A1 to A14, wherein the semiconductor module (1) is electrically connected to the IGBT device (2) via the support electrode (84).
  • a wiring electrode (87) provided at a distance from the supporting electrode (84), and a first conductive connecting member () electrically connected to the MISFET device (3) and the wiring electrode (87).
  • 90A and a second conductive connection member (90C) electrically connected to the IGBT device (2) and the wiring electrode (87).
  • the first conductive connection member (90A) is mechanically and electrically connected to the MISFET device (3) and the wiring electrode (87), and the second conductive connection member (90C) is connected to the MISFET device (3) and the wiring electrode (87).
  • A16 which is mechanically and electrically connected to the device (3) and the IGBT device (2), and electrically connected to the wiring electrode (87) via the first conductive connecting member (90A).

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • General Engineering & Computer Science (AREA)
  • Electrodes Of Semiconductors (AREA)
PCT/JP2023/006631 2022-03-31 2023-02-24 半導体モジュール Ceased WO2023189052A1 (ja)

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JP2024511469A JPWO2023189052A1 (https=) 2022-03-31 2023-02-24
US18/802,642 US20240405016A1 (en) 2022-03-31 2024-08-13 Semiconductor module

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JP2022-061318 2022-03-31

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013125806A (ja) * 2011-12-14 2013-06-24 Mitsubishi Electric Corp 電力用半導体装置
JP2017108097A (ja) * 2015-11-30 2017-06-15 良孝 菅原 半導体素子
JP2017195259A (ja) * 2016-04-19 2017-10-26 株式会社デンソー 半導体モジュール、及び電力変換装置
JP6877660B1 (ja) * 2020-09-09 2021-05-26 三菱電機株式会社 電力変換装置及び電力変換装置を搭載した航空機

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013125806A (ja) * 2011-12-14 2013-06-24 Mitsubishi Electric Corp 電力用半導体装置
JP2017108097A (ja) * 2015-11-30 2017-06-15 良孝 菅原 半導体素子
JP2017195259A (ja) * 2016-04-19 2017-10-26 株式会社デンソー 半導体モジュール、及び電力変換装置
JP6877660B1 (ja) * 2020-09-09 2021-05-26 三菱電機株式会社 電力変換装置及び電力変換装置を搭載した航空機

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