WO2023188245A1 - Gate bias control circuit and gate bias control method for communication amplification transistor - Google Patents

Abstract

A gate bias control circuit (100) comprises: a wave detection unit (10) for detecting an input signal that is of a communication amplification transistor FET, that is a modulation wave signal obtained by modulation of a carrier wave, and that is inputted to a gate electrode as an input signal; and a bias voltage generation unit (20) that applies a gate bias voltage Vgt, according to input electric power of the input signal having been detected by the wave detection unit (10), to a gate bias node to which the gate electrode of the communication amplification transistor is connected.

Description

Gate bias control circuit and gate bias control method for communication amplification transistor

The present disclosure relates to a gate bias control circuit and a gate bias control method for a communication amplification transistor.

In recent years, high-output amplifiers have been desired as amplifiers used in transmitters in wireless base station systems.
As a high-output amplifier for such communication, a high electron mobility transistor (HEMT: hereinafter referred to as GaN-HEMT) using gallium nitride (GaN) is used as shown in Non-Patent Document 1. It is being considered.

The gate bias voltage applied to the gate electrode of the GaN-HEMT shown in Non-Patent Document 1 is always constant because the gate electrode is connected to the gate bias voltage via an inductor and a resistor.

In this way, in a GaN-HEMT to which a constant gate bias voltage is always applied, when a modulated wave signal obtained by modulating a carrier wave to the gate electrode is input as an input signal, amplitude distortion (AM-AM: Amplitude to Amplitude) characteristics (hereinafter referred to as AM-AM characteristics) and phase distortion (AM-PM) characteristics (hereinafter referred to as AM-PM characteristics) are distorted, and the adjacent channel power ratio (ACPR) It was found that distortion characteristics such as Channel Power Ratio (hereinafter referred to as ACPR) deteriorate.
As described above, distortion occurs in the AM-AM characteristics and AM-PM characteristics because the semiconductor material that makes up the GaN transistor contains crystal defects (hereinafter referred to as traps), and when a modulated wave signal is input as an input signal. This is thought to have occurred due to the memory effect caused by the trap.

The present disclosure has been made in view of the above-mentioned points, and when a modulated wave signal is input as an input signal to a communication amplification transistor, a memory effect occurs due to a trap in the semiconductor material constituting the communication amplification transistor. The object of the present invention is to obtain a gate bias control circuit that suppresses deterioration of distortion characteristics.

A gate bias control circuit according to the present disclosure includes a detection unit that detects an input signal of a communication amplification transistor into which a modulated wave signal obtained by modulating a carrier wave to a gate electrode is input as an input signal; and a bias voltage generating section that applies a gate bias voltage corresponding to the input power of the input signal to the gate bias node connected to the gate electrode of the communication amplification transistor.

According to the present disclosure, when a modulated wave signal is input as an input signal to a communication amplification transistor, a memory effect due to a trap in a semiconductor material constituting the communication amplification transistor is suppressed, and deterioration of distortion characteristics is suppressed.

FIG. 3 is a diagram showing the relationship between the gate bias control circuit and the communication amplification transistor according to the first embodiment. FIG. 3 is a diagram showing the relationship between the power of the input signal of the communication amplification transistor and the gate bias voltage from the gate bias control circuit according to the first embodiment. 1 is a circuit diagram showing a gate bias control circuit according to Embodiment 1. FIG. 5 is a flowchart illustrating an example of control operations performed by the gate bias control circuit according to the first embodiment. 3 is a diagram showing an output spectrum versus frequency in the gate bias control circuit according to the first embodiment. FIG. 5 is a diagram showing changes in gate bias voltage in the gate bias control circuit according to the first embodiment. FIG. 3 is a diagram showing AM-AM characteristics in the gate bias control circuit according to the first embodiment. FIG. 3 is a diagram showing AM-PM characteristics in the gate bias control circuit according to the first embodiment. FIG. FIG. 3 is a diagram showing changes in gain in the gate bias control circuit according to the first embodiment. 5 is a diagram showing a phase shift of an output signal in the gate bias control circuit according to the first embodiment. FIG. 5 is a diagram showing ACPR in the gate bias control circuit according to the first embodiment. FIG. 7 is a diagram showing a relationship between a gate bias control circuit and a communication amplification transistor according to a second embodiment. FIG. FIG. 7 is a diagram showing the relationship between the power of the input signal of the communication amplification transistor and the gate bias voltage from the gate bias control circuit according to the second embodiment. 3 is a circuit diagram showing a gate bias control circuit according to a second embodiment. FIG. 7 is a flowchart illustrating an example of control operations performed by the gate bias control circuit according to the second embodiment. 7 is a diagram showing an output spectrum versus frequency in a gate bias control circuit according to a second embodiment. FIG. FIG. 7 is a diagram showing changes in gate bias voltage in the gate bias control circuit according to the second embodiment. 7 is a diagram showing AM-AM characteristics in the gate bias control circuit according to the second embodiment. FIG. 7 is a diagram showing AM-PM characteristics in the gate bias control circuit according to the second embodiment. FIG. 7 is a diagram illustrating changes in gain in the gate bias control circuit according to the second embodiment. FIG. 7 is a diagram showing a phase shift of an output signal in a gate bias control circuit according to a second embodiment. FIG. 7 is a diagram showing ACPR in the gate bias control circuit according to the second embodiment. FIG. FIG. 7 is a diagram showing a relationship between a gate bias control circuit and a communication amplification transistor according to a third embodiment. FIG. 7 is a diagram showing the relationship between the power of the input signal of the communication amplification transistor and the gate bias voltage from the gate bias control circuit according to the third embodiment. FIG. 7 is a circuit diagram showing a gate bias control circuit according to a third embodiment. 7 is a flowchart illustrating an example of control operations performed by the gate bias control circuit according to the third embodiment. 7 is a diagram showing an output spectrum versus frequency in a gate bias control circuit according to a third embodiment. FIG. 7 is a diagram showing changes in gate bias voltage in the gate bias control circuit according to Embodiment 3. FIG. FIG. 7 is a diagram showing AM-AM characteristics in the gate bias control circuit according to the third embodiment. FIG. 7 is a diagram showing AM-PM characteristics in the gate bias control circuit according to the third embodiment. FIG. 7 is a diagram illustrating changes in gain in the gate bias control circuit according to Embodiment 3; FIG. 7 is a diagram showing a phase shift of an output signal in a gate bias control circuit according to a third embodiment. FIG. 7 is a diagram showing ACPR in the gate bias control circuit according to the third embodiment.

Embodiment 1.
A gate bias control circuit 100 for a communication amplification transistor FET according to a first embodiment will be described with reference to FIGS. 1 to 11.
The communication amplification transistor FET (hereinafter simply referred to as FET) is a field effect transistor (FET), and a GaN-HEMT is used as an example.

Note that FETs are not limited to GaN-HEMTs, but are used in communication amplifiers such as GaN transistors, and a modulated wave signal obtained by modulating a carrier wave is input to the gate electrode as an input signal, and the amplification function is performed. The gate bias control circuit 100 can be applied to any FET that has the following characteristics.
In addition, the input signal input to the FET is independent of the relationship between the modulation bandwidth BW and the electron capture time constant Tc of the trap in the semiconductor material, and the input signal input to the FET has an arbitrary modulation bandwidth BW and electron capture time constant Tc. The gate bias control circuit 100 can be applied.

In the communication amplification transistor FET, a modulated wave signal obtained by modulating a carrier wave is inputted to the gate electrode G as an input signal, and an output signal obtained by amplifying the input signal is outputted from the drain electrode D.
As shown in FIG. 1, the input power in the input signal is Pin, and the output power in the output signal is Pout. Let Pinave be the average input power in the input signal.

The gate electrode G of the FET is connected to a gate bias node via a series body of an inductor L and a resistor Rd. As shown in FIG. 1, the gate bias voltage applied to the gate bias node is Vgt.
The drain electrode D of the FET is connected to the drain node. As shown in FIG. 1, the drain bias voltage applied to the drain node is Vd.
The source electrode S of the FET is connected to a ground potential node as shown in FIG.

The gate bias control circuit 100 detects the input signal input to the FET, controls the gate bias voltage Vgt according to the level of the input power Pin in the input signal, and applies the gate bias voltage Vgt to the gate bias node.
As shown in FIG. 2, the gate bias control circuit 100 maintains the gate bias voltage Vgt at the set voltage when the input power Pin is greater than or equal to the average input power Pinave, and maintains the gate bias voltage Vgt at the set voltage when the input power Pin is less than the average input power Pinave. The lower the power Pin is, the higher the gate bias voltage Vgt is applied to the gate bias node than the set voltage.

In FIG. 2, the horizontal axis shows time, the vertical axis shows power for input power Pin and average input power Pinave, and voltage for gate bias voltage Vgt.
Further, the gate bias voltage Vgt is shown by a solid line, the input power Pin is shown by a broken line, and the average input power Pinave is shown by a chain line.

As shown in FIG. 3, the gate bias control circuit 100 includes a detection section 10 that detects an input signal, a bias voltage generation section 20 that applies a gate bias voltage Vgt to a gate bias node, and a coupler Coup that extracts an input signal. .

The detection unit 10 detects the input signal input to the FET taken out by the coupler Coup.
The detection unit 10 is a detector including a diode D1, a resistor Ra, and a capacitor C1, as shown in FIG.
The anode of the diode D1 is connected to the coupler Coup, and the cathode is connected to the output node of the detection section 10.
The resistor R3 and the capacitor C1 are connected between the output node of the detection section 10 and the ground node.

The bias voltage generation section 20 controls the gate bias voltage Vgt according to the level of the input power Pin in the input signal detected by the detection section 10, and controls the gate bias voltage Vgt when the input power Pin is equal to or higher than the average input power Pinave. When the set voltage is maintained and the input power Pin is less than the average input power Pinave, the lower the input power Pin is, the higher the gate bias voltage Vgt is applied to the gate bias node than the set voltage.

The bias voltage generation section 20 includes a voltage generation section 21, a limiter circuit 22, a first adder A1, an inverting amplifier 23, a second adder A2, a resistor R1, and a resistor R6.
The voltage generator 21 has a first voltage node that outputs a first voltage and a second voltage node that outputs a second voltage different from the first voltage.

The voltage generator 21 includes a DC power supply DC, a resistor Rb, and a resistor Rc.
The direct current power supply DC constitutes a first voltage generating section that outputs a first voltage to the + electrode. The connection point of the + electrode of the DC power supply DC is the first voltage node.
The resistor Rb and the resistor Rc are connected in series between the first voltage node and the ground potential node, and a second voltage is applied to the connection point between the resistor Rb and the resistor Rc, that is, a second voltage with respect to the first voltage. A second voltage generator is configured to output the voltage. The connection point between resistor Rb and resistor Rc is the second voltage node.

The limiter circuit 22 limits the upper limit of the voltage of the input signal appearing at the output node of the detection section 10.
The limiter circuit 22 limits the voltage that appears at one end when the input power Pin is less than the average input power Pinave to a constant voltage that is an upper limit value. .
One end of the limiter circuit 22 is connected to the output node of the detection section 10 via a resistor R1, and the other end is connected to a ground node.
The limiter circuit 22 includes a diode D2 to which an anode electrode is connected at one end, and a resistor R2 connected between the cathode of the diode D2 and a ground node.

The first adder A1 has one input terminal connected to the second voltage node of the voltage generating section 21, and the other input terminal connected to one end of the limiter circuit 22.
The output voltage from the first adder A1 is the sum of the second voltage at the second voltage node of the voltage generator 21 and the voltage at one end of the limiter circuit 22, and is the sum of the second voltage at the second voltage node of the voltage generator 21 and the voltage at one end of the limiter circuit 22. This voltage ranges up to the voltage plus a constant voltage limited by the limiter circuit 22.

That is, if the second voltage at the second voltage node is V _M , the voltage limited by the limiter circuit 22 is V _L , and the voltage at the output node of the detection section 10 is V _α , then the voltage from the first adder A1 is The output voltage V _O1 is as follows.
The output voltage V _O1 is a voltage value that changes to V _M +V _α in the range from V _M to V _M +V _L.
The second voltage _VM is a voltage for adjusting the level of the gate bias voltage Vgt.

From the second voltage V _M to the voltage (V _M +V _L ) which is the sum of the second voltage V _M and the constant voltage V _L limited by the limiter circuit 22, the second voltage V _M is adjusted according to the input power Pin. The value (V _M +V _α ) obtained by adding the voltage V _α is taken.
That is, when the input power Pin is less than the average input power Pinave, the output voltage from the first adder A1 is a voltage (V _M +V _α ) increased from the second voltage V _M according to the input power Pin. , when the input power Pin is equal to or higher than the average input power Pinave, it is maintained _{at a constant voltage (V M +} V _L ) obtained by adding a constant voltage to the second voltage VM.

The inverting amplifier 23 inverts the output from the first adder A1 and outputs an amplified voltage.
The inverting amplifier 23 includes an operational amplifier AMP and resistors R3 to R5.
A resistor R3 is connected between the output terminal of the first adder A1 and the inverting input terminal of the operational amplifier AMP.
A resistor R4 is connected between the inverting input terminal and the output terminal of the operational amplifier AMP.
Resistor R5 is connected between the non-inverting input terminal of operational amplifier AMP and the ground node.

The second adder A2 has one input terminal connected to the first voltage node of the voltage generator 21, that is, the + electrode of the DC power supply DC, and the other input terminal connected to the output of the inverting amplifier 23 via the resistor R6. The output end is connected to the gate bias node.
The output terminal of the second adder A2 is the output terminal of the gate bias control circuit 100.

The output voltage from the second adder A2 is a value obtained by adding the voltage at the output terminal of the inverting amplifier 23 to the voltage at the first voltage node of the voltage generating section 21, and is a value obtained by adding the voltage at the output terminal of the inverting amplifier 23 to the voltage at the first voltage node of the voltage generating section The voltage at the voltage node of the voltage generator 21 is subtracted from the sum of the second voltage _VM at the second voltage node of the voltage generator 21 and the voltage _VL at one end of the limiter circuit 22. 21 minus the second voltage V _M at the second voltage node of V M .
Note that although the voltage at the output terminal of the inverting amplifier 23 is an amplified value, the explanation of the amplification is omitted to avoid complication of explanation. The same applies to the following.

That is, if the voltage at the first voltage node of the voltage generator 21 is _V0 , the output voltage from the second adder A2, that is, the gate bias voltage Vgt is as follows.
The gate bias voltage Vgt is a voltage value that changes from V _O -(V _M +V _L ) to V _O -(V _M +V _α ) in the range of V _O -V _M.

The voltage [V _O −(V _M +V _L )] is a set voltage when the input power Pin of the input signal is greater than or equal to the average input power Pinave of the input signal.
Further, the voltage [V _O -(V _M +V _α )] is the voltage when the input power Pin of the input signal is less than the average input power Pinave of the input signal, and the voltage according to the input power Pin of the input signal, that is, , the lower the input power Pin of the input signal, the higher the voltage becomes than the set voltage.

A series body of an inductor L and a resistor Rd is connected between the gate electrode of the FET and the gate bias node.
Further, a capacitor C2 is connected between the gate bias node and the ground node.

Next, the operation performed by gate bias control circuit 100 according to the first embodiment will be described using FIG. 4.
First, in step ST1, the coupler Coup extracts an input signal input to the FET, and the detection section 10 detects the extracted input signal.
The step in which the detection unit 10 detects the input signal of the FET is a detection step.

When the input signal of the FET is detected, the bias voltage generating section 20 maintains the gate bias voltage Vgt at the set voltage when the input power Pin in the input signal is equal to or higher than the average input power Pinave (step ST2) (step ST3), When the input power Pin is less than the average input power Pinave (step ST2), the gate bias voltage Vgt is raised higher than the set voltage. Specifically, the lower the input power Pin is, the higher the gate bias voltage Vgt is than the set voltage. (step ST4).

Steps ST2 to ST4 are bias voltage generation steps in which a gate bias voltage Vgt corresponding to the input power Pin of the input signal detected in the detection step is applied to the gate bias node to which the gate electrode of the FET is connected.
Steps ST2 to ST4 maintain the gate bias voltage Vgt at the set voltage when the input power Pin of the input signal detected in the detection step is equal to or higher than the average input power Pinave, and input when the input power Pin is less than the average input power Pinave. The lower the power Pin is, the higher the gate bias voltage Vgt is than the set voltage in the bias voltage generation step.
Thereafter, steps ST1 to ST4 are sequentially repeated.

Regarding the gate bias control circuit 100 according to the first embodiment, verification results by simulation will be explained based on FIGS. 5 to 11.
In the verification, a model with a large signal as an input signal was used in consideration of the influence of traps in the semiconductor constituting the FET. Specifically, the modulated wave signal as the input signal was 64QAM, the modulation bandwidth BW of the input signal was 20 MHz, the frequency of the input signal was 4 GHz, the drain voltage Vd was 50 V, and the idle drain current Idq was 20 mA/mm.
For comparison, the same verification was performed with the gate bias voltage Vgt of the FET set to a constant voltage.
In FIGS. 5 to 11, dark, light black parts show examples of the first embodiment, and light black parts show comparative examples.

FIG. 5 shows an output signal that is a modulated wave signal from the FET, and shows an output spectrum with respect to frequency. The horizontal axis shows the frequency and the vertical axis shows the output spectrum.
FIG. 6 shows changes in the gate bias voltage Vgt from the gate bias control circuit 100. The horizontal axis represents time, and the vertical axis represents gate bias voltage.
FIG. 7 shows the AM-AM characteristics. The horizontal axis shows the output power of the output signal, and the vertical axis shows the gain of the FET.
FIG. 8 shows AM-PM characteristics. The horizontal axis shows the output power of the output signal, and the vertical axis shows the phase.
FIG. 9 shows the change in gain of the FET. The horizontal axis represents time, and the vertical axis represents FET gain.
FIG. 10 shows the phase shift of the output signal. The horizontal axis shows time and the vertical axis shows phase.
FIG. 11 shows ACPR.

As can be understood from FIG. 5, when the gate bias control circuit 100 according to the first embodiment is used, the power level ratio between the main channel and the adjacent channel (indicated by E1 in FIG. 5) is different from that of the comparative example. This has a large advantage compared to the power level ratio between the main channel and the adjacent channel (shown at S1 in FIG. 5).

As can be understood from FIG. 7, when the gate bias control circuit 100 according to the first embodiment is used, the dynamic AM-AM characteristic has a wider spread of FET gain with respect to the output power of the output signal than in the comparative example. is suppressed.
In particular, when using the gate bias control circuit 100 according to the first embodiment, the spread of the dynamic AM-AM characteristics at low output (shown by E2 in FIG. 7) is different from the dynamic AM-AM characteristic at low output in the comparative example. This has the advantage of being smaller than the spread of AM-AM characteristics (shown at S2 in FIG. 7).

Furthermore, as can be understood from FIG. 11, the ACPR is approximately -23.4 dBc in the comparative example, whereas it is improved to approximately -28.1 dBc when using the gate bias control circuit 100 according to the first embodiment. has been done.
That is, when using the gate bias control circuit 100 according to the first embodiment, there is an advantage that the ratio of the power levels between the main channel and the adjacent channel is larger than the ratio of the power levels between the main channel and the adjacent channel in the comparative example. be.

From these things, the following can be understood.
In the comparative example, when the input power Pin of the input signal input to the FET is greater than or equal to the average input power Pinave, electrons are charged to the trap in the FET, and when the input power Pin is less than the average input power Pinave, the instantaneous The gain of the FET has decreased, the dynamic AM-AM characteristics have deteriorated, and the distortion characteristics have deteriorated.

On the other hand, when the gate bias control circuit 100 according to the first embodiment is used, the instantaneous decrease in FET gain due to the influence of the trap explained in the comparative example can be suppressed when the input power Pin is less than the average input power Pinave. By applying a gate bias voltage Vgt higher than the set voltage to the gate electrode of the FET, the gate bias control circuit 100 has the effect of preventing a decrease in the gain of the FET, improving dynamic AM-AM characteristics, and improving distortion characteristics. suppresses deterioration.

Furthermore, as can be understood from FIGS. 8, 9, and 10, when using the gate bias control circuit 100 according to the first embodiment, the AM-PM characteristics, FET gain, and output It can be seen that the phase variation of the signal has been improved.

Note that in the gate bias control circuit 100 according to the first embodiment, the detection section 10, the bias voltage generation section 20, and the coupler Coup are configured using analog circuits as shown in FIG. The configuration may be such that the gate bias voltage Vgt is directly generated by software using a digital signal that generates a modulated wave signal according to the level of the input power Pin in the input signal.

In this case as well, the generated gate bias voltage Vgt is the set voltage when the input power Pin is equal to or higher than the average input power Pinave, similar to the gate bias voltage Vgt generated by the analog circuit shown in FIG. When the power Pin is less than the average input power Pinave, the lower the input power Pin is, the higher the voltage is than the set voltage.

Furthermore, in the gate bias control circuit 100 according to the first embodiment, the voltage to be added to the set voltage when the input power Pin is less than the average input power Pinave may be configured by a differentiating circuit.

As described above, in the gate bias control circuit 100 according to the first embodiment, the bias voltage generation section 20 generates the gate bias voltage Vgt according to the input power Pin of the input signal detected by the detection section 10 for communication. Since the voltage is applied to the gate bias node to which the gate electrode of the amplification transistor FET is connected, it is possible to suppress the influence of the memory effect due to traps in the FET, thereby suppressing deterioration of distortion characteristics.

In the gate bias control circuit 100 according to the first embodiment, when the input power Pin of the input signal detected by the detection unit 10 is equal to or higher than the average input power Pinave of the input signal, the bias voltage generation unit 20 generates a gate bias voltage of the set voltage. Vgt is applied to the gate bias node, and if the input power Pin is less than the average input power Pinave, the lower the input power Pin is, the higher the voltage than the set voltage is applied to the gate bias node, so the input power Pin is higher than the average input power Pinave. When the input power Pin is less than the average input power Pinave due to the influence of electrons being charged in the traps in the FET when Deterioration of distortion characteristics can be suppressed.

Embodiment 2.
A gate bias control circuit 200 for a communication amplification transistor FET according to a second embodiment will be described with reference to FIGS. 12 to 22.
The gate bias control circuit 200 according to the second embodiment is different from the gate bias control circuit 100 according to the first embodiment in that the set voltage is a voltage that increases with time, and other points are the same. be.
12 to 22, the same reference numerals as those shown in FIGS. 1 to 11 indicate the same or equivalent parts.

The gate bias control circuit 200 according to the second embodiment is more suitable as a gate bias control circuit applied to an FET to which a modulated wave signal transmitted by a time division duplex (TDD) method is input as an input signal. Are suitable.
The modulated wave signal by the TDD method is a modulated wave signal that repeats on and off, and the gain of the FET tends to decrease transiently due to the effect of electrons being charged in the traps in the FET, so the gate bias control circuit 200 adjusts the set voltage. The voltage is increased over time, and control is performed to transiently increase the average value of the gate bias voltage Vgt for the FET.

As shown in FIG. 13, the gate bias control circuit 200 sets the set voltage to a voltage that increases over time, and when the input power Pin is equal to or higher than the average input power Pinave, the gate bias voltage Vgt is set to the set voltage, and the input power Pin increases. When the input power Pin is less than the average input power Pinave, the lower the input power Pin is, the higher the gate bias voltage Vgt is applied to the gate bias node than the set voltage.

In FIG. 13, the horizontal axis shows time, the vertical axis shows power for input power Pin and average input power Pinave, and voltage for gate bias voltage Vgt.
Further, the gate bias voltage Vgt is shown by a solid line, the input power Pin is shown by a broken line, and the average input power Pinave is shown by a chain line.

As shown in FIG. 14, the gate bias control circuit 200 includes a detection section 10 that detects an input signal, a bias voltage generation section 20A that applies a gate bias voltage Vgt to a gate bias node, and a coupler Coup that takes out an input signal. .
Since the detection section 10 and the coupler Coup are the same as the detection section 10 and the coupler Coup in the first embodiment, their explanation will be omitted.

The bias voltage generation section 20A controls the gate bias voltage Vgt according to the level of the input power Pin in the input signal detected by the detection section 10, sets the set voltage to a voltage that increases over time, and sets the input power Pin to the average input voltage. When the input power Pin is higher than the average input power Pinave, the gate bias voltage Vgt is set to the set voltage, and when the input power Pin is less than the average input power Pinave, the lower the input power Pin is, the higher the gate bias voltage Vgt is set to the gate bias node. to be applied.

The bias voltage generator 20A includes a voltage generator 21A, a limiter circuit 22, a first adder A1, an inverting amplifier 23, a second adder A2, a resistor R1, and a resistor R6.
The other constituent features except for the voltage generation section 21A are the same as the other constituent features except for the voltage generation section 21 in Embodiment 1, so the explanation will be omitted.

The voltage generator 21 has a first voltage node that outputs a first voltage that increases with time, and a second voltage node that outputs a second voltage different from the first voltage.
The voltage generation section 21 includes a first voltage generation section that outputs a first voltage to a first voltage node, and a second voltage generation section that outputs a second voltage to a second voltage node.

The first voltage generating section has a pulsed DC power supply DC1, a resistor Rt, and a capacitor Ct.
The output end of the pulsed DC power supply DC1 is connected to the first voltage node via a resistor Rt.
Capacitor Ct is connected between the first voltage node and the ground node.
The pulsed DC power supply DC1 accumulates charge in the capacitor Ct during the on-cycle, and removes the charge accumulated in the capacitor Ct during the off-cycle, thereby controlling the voltage between the electrodes of the capacitor Ct to a first voltage. A first voltage at the node is increased over time.

The product of the resistance Rt and the capacitance Ct is set to be the same as the time constant of the decrease in FET gain due to the influence of traps during TDD operation.
Therefore, when a pulse is output from the pulsed DC power supply DC1, the gate bias voltage Vgt increases to compensate for the decrease in the gain of the FET.
The difference between the low gate bias voltage Vgt and the high gate bias voltage Vgt set by the pulsed DC power supply DC1 is set to an increase in the gate bias voltage which is the set voltage.

The pulsed direct current power supply DC1 sequentially increases the first voltage at the first voltage node from the initial voltage at each pulse period, and adjusts the on/off cycle to periodically initialize the first voltage. Return the voltage to the current state.
The second voltage generator has a direct current power supply DC2.

Let V _O be the voltage in the initial state at the first voltage node, V _β be the voltage raised from the set voltage in the initial state by the pulsed DC power supply DC1, and V _M be the second voltage.
The output voltage from the second adder A2, that is, the gate bias voltage Vgt is as follows.
The gate bias voltage Vgt is a voltage that changes from [V _O to (V _O +V _β )]-(V _M +V _α ) in the range from V _O -(V _M +V _L ) to (V _O +V _β )-V _M is the value of

The voltage [V _O −(V _M +V _L )] is the set voltage in the initial state when the input power Pin of the input signal is greater than or equal to the average input power Pinave of the input signal.
Also, when the voltage [(V _O + V _β ) - (V _M + V _L )] transiently increases the average value of the gate bias voltage Vgt, the input power Pin of the input signal is the average input power of the input signal. This is the set voltage when it is equal to or higher than Pinave.

Furthermore, when the voltage [(V _O +V _β )-(V _M +V _α )] transiently increases the average value of the gate bias voltage Vgt, the input power Pin of the input signal is equal to the average input power of the input signal. This is the voltage when the input power Pin of the input signal is lower than the set voltage [(V _O + V _β ) - (V _M + V _L )]. The voltage will be high.

Next, the operation performed by the gate bias control circuit 200 according to the second embodiment will be described using FIG. 15.
First, in step ST1, the coupler Coup extracts an input signal input to the FET, and the detection section 10 detects the extracted input signal.
The step in which the detection unit 10 detects the input signal of the FET is a detection step.

The bias voltage generator 20 sets the set voltage to a set voltage that is increased over time (steps ST5 and ST6), and when the input signal of the FET is detected, the bias voltage generator 20 sets the input power Pin of the input signal to the average input voltage. If the input power Pin is greater than or equal to the average input power Pinave (step ST2), the gate bias voltage Vgt is set to an increased set voltage (step ST3A), and if the input power Pin is less than the average input power Pinave (step ST2), the gate bias voltage Vgt is increased. The gate bias voltage Vgt is raised higher than the set voltage, specifically, the lower the input power Pin is, the higher the gate bias voltage Vgt is than the raised set voltage (step ST4A).

Steps ST2 to ST5, ST6, ST3A, and ST4A include steps of increasing the set voltage over time, and apply the gate bias voltage Vgt according to the input power Pin of the input signal detected in the detection step to the gate electrode of the FET. This is a step of generating a bias voltage to be applied to the gate bias node connected to the gate bias node.

Steps ST2 to ST5, ST6, ST3A, and ST4A include steps of increasing the set voltage over time, and when the input power Pin of the input signal detected in the detection step is equal to or higher than the average input power Pinave, the gate bias voltage Vgt This is a bias voltage generation step in which the gate bias voltage Vgt is set to an increased set voltage, and when the input power Pin is less than the average input power Pinave, the lower the input power Pin is, the higher the gate bias voltage Vgt is set to be a voltage higher than the raised set voltage.
Thereafter, steps ST1 to ST4A are sequentially repeated.

Regarding the gate bias control circuit 200 according to the second embodiment, verification results by simulation will be explained based on FIGS. 16 to 22.
In the verification, a model with a large signal as an input signal was used in consideration of the influence of traps in the semiconductor constituting the FET. Specifically, the modulated wave signal as the input signal was 64QAM, the modulation bandwidth BW of the input signal was 20 MHz, the frequency of the input signal was 4 GHz, the drain voltage Vd was 50 V, and the idle drain current Idq was 20 mA/mm.
In FIGS. 16 to 22, dark, light black parts show examples of the second embodiment, and light black parts show examples of the first embodiment.

FIG. 16 shows an output signal which is a modulated wave signal from the FET, and shows an output spectrum with respect to frequency. The horizontal axis shows the frequency and the vertical axis shows the output spectrum.
FIG. 17 shows changes in the gate bias voltage Vgt from the gate bias control circuit 100. The horizontal axis represents time, and the vertical axis represents gate bias voltage.
FIG. 18 shows AM-AM characteristics. The horizontal axis shows the output power of the output signal, and the vertical axis shows the gain of the FET.
FIG. 19 shows AM-PM characteristics. The horizontal axis shows the output power of the output signal, and the vertical axis shows the phase.
FIG. 20 shows the change in FET gain. The horizontal axis represents time, and the vertical axis represents FET gain.
FIG. 21 shows the phase shift of the output signal. The horizontal axis shows time and the vertical axis shows phase.
FIG. 22 shows ACPR.

As is clear from FIG. 16, when using the gate bias control circuit 100 according to the second embodiment, the power level ratio of the main channel and the adjacent channel is lower when using the gate bias control circuit 100 according to the first embodiment. The ratio of the power levels of the main channel and the adjacent channel is the same as in the case where the power level of the main channel and the adjacent channel are the same, and there is a large advantage over the comparative example.
As can be understood from FIG. 18, in particular, when using the gate bias control circuit 100 according to the second embodiment, the spread of the dynamic AM-AM characteristics at low output is the gate bias control according to the first embodiment. This is smaller than the spread of dynamic AM-AM characteristics at low output when the circuit 100 is used, and has a small advantage over the comparative example.

As can be understood from FIG. 20, when the gate bias control circuit 200 according to the second embodiment is used, the transient gain of the FET changes over time. It is suppressed more than when using it.
Furthermore, as can be understood from FIG. 22, ACPR is approximately -23.4 dBc in the comparative example and -28.1 dBc in the case where the gate bias control circuit 100 according to the first embodiment is used, whereas in the embodiment When the gate bias control circuit 200 according to the second embodiment is used, the improvement is approximately −29.1.
That is, when using the gate bias control circuit 100 according to the second embodiment, there is an advantage that the ratio of the power levels of the main channel and the adjacent channel is larger than the ratio of the power levels of the main channel and the adjacent channel of the comparative example. be.

When the gate bias control circuit 200 according to the second embodiment is applied to an FET into which a modulated wave signal by the TDD method is input as an input signal, the gain of the FET transiently generated due to the effect of electrons being charged in traps in the FET. By increasing the set voltage over time, and when the input power Pin is less than the average input power Pinave, the gate bias control circuit 100 applies a gate bias voltage Vgt higher than the set voltage to the gate electrode of the FET. It has the effect of preventing a decrease in FET gain and suppresses deterioration of distortion characteristics.

As described above, in the gate bias control circuit 200 according to the second embodiment, the bias voltage generation section 20 increases the set voltage over time, and increases the setting voltage according to the input power Pin of the input signal detected by the detection section 10. Since the gate bias voltage Vgt is applied to the gate bias node to which the gate electrode of the communication amplification transistor FET is connected, it is possible to suppress the influence of the memory effect due to traps in the FET and to suppress deterioration of distortion characteristics.

In the gate bias control circuit 200 according to the second embodiment, the bias voltage generation section 20 increases the set voltage over time, and the input power Pin of the input signal detected by the detection section 10 is greater than or equal to the average input power Pinave of the input signal. If the input power Pin is less than the average input power Pinave, the gate bias voltage Vgt of the set voltage is applied to the gate bias node, and the lower the input power Pin is, the higher the voltage than the set voltage is applied to the gate bias node. Due to the effect of electrons being charged in the traps in the FET, excessive gain reduction of the FET can be prevented, and deterioration of distortion characteristics can be suppressed.

Embodiment 3.
A gate bias control circuit 300 for a communication amplification transistor FET according to the third embodiment will be described with reference to FIGS. 23 to 33.
Compared to the gate bias control circuit 200 according to the second embodiment, the gate bias control circuit 300 according to the third embodiment suppresses an unnecessary increase in the gate bias voltage Vgt for the FET, and the input power Pin of the input signal is adjusted to the average input power. The difference is that the upper limit value of the gate bias voltage Vgt is limited when the power is less than Pinave, and the gain with respect to the output power in the dynamic AM-AM characteristic is made close to flat, but other points are the same.
In FIGS. 23 to 33, the same reference numerals as those shown in FIGS. 1 to 22 indicate the same or corresponding parts.

As shown in FIG. 24, the gate bias control circuit 300 sets the set voltage to a voltage that increases over time, and when the input power Pin is equal to or higher than the average input power Pinave, the gate bias voltage Vgt is set to the set voltage, and the input power Pin increases. If it is less than the average input power Pinave, the upper limit value of the gate bias voltage Vgt is limited, and the lower the input power Pin is, the higher the gate bias voltage Vgt is applied to the gate bias node than the set voltage.

In FIG. 24, the horizontal axis shows time, the vertical axis shows power for input power Pin and average input power Pinave, and voltage for gate bias voltage Vgt.
Further, the gate bias voltage Vgt is shown by a solid line, the input power Pin is shown by a broken line, the average input power Pinave is shown by a dashed-dotted line, and the upper limit of the gate bias voltage Vgt is shown by a dashed-two dotted line.

The second limiter circuit 24 is connected to the output terminal of the inverting amplifier 23 and limits the upper limit value of the voltage at the output terminal of the inverting amplifier 23.
The second limiter circuit 24 limits the voltage at the output terminal of the inverting amplifier 23 to a constant voltage that is an upper limit value.
The second limiter circuit 24 has one end connected to the output end of the inverting amplifier 23 via a resistor R6, and the other end connected to the ground node.
The second limiter circuit 24 includes a diode D3 having an anode electrode connected to one end thereof, and a resistor R7 connected between the cathode of the diode D3 and the ground node.

The voltage inputted to the other input terminal of the second adder A2 connected to the output terminal of the inverting amplifier 23 is in the range of -(V _M +V _L2 ) to _-VM ; _The output voltage V _O1 from the first adder A1 is lower than the voltage V _L2 limited by the second limiter circuit 24 .
The output voltage V _O1 is a voltage value that changes to V _M +V _α in the range from V _M to V _M +V _L1 .
Note that V _M is the second voltage, V _L1 is the voltage limited by the first limiter circuit 22, and V _α is the voltage at the output node of the detection section 10.

The output voltage from the second adder A2, that is, the gate bias voltage Vgt is as follows.
The gate bias voltage Vgt is a voltage that changes from V _O - (V _O +V _β )] - (V _M +V _α ) in the range from V _O - (V M +V _L2 ) to ( _{V O} +V _β ) - V _M is the value of
That is, the upper limit value of the gate bias voltage Vgt is limited by the voltage _VL2 limited by the second limiter circuit 24.

Note that the voltage [V _O −(V _M +V _L2 )] is the set voltage in the initial state when the input power Pin of the input signal is greater than or equal to the average input power Pinave of the input signal.
Also, when the voltage [(V _O +V _β )-(V _M +V _L2 )] transiently increases the average value of the gate bias voltage Vgt, the input power Pin of the input signal is the average input power of the input signal. This is the set voltage when it is equal to or higher than Pinave.

Furthermore, when the voltage [(V _O +V _β )-(V _M +V _α )] transiently increases the average value of the gate bias voltage Vgt, the input power Pin of the input signal is equal to the average input power of the input signal. This is the voltage when the input power Pin of the input signal is less than Pinave, and the upper limit value is limited by the voltage according to the input power Pin of the input signal, that is, the voltage _VL2 limited by the second limiter circuit 24, and the input power Pin of the input signal The lower the voltage, the higher the voltage is than the set voltage [(V _O +V _β )−(V _M +V _L2 )].

Next, the operation performed by the gate bias control circuit 300 according to the third embodiment will be described using FIG. 26.
Step ST1, step ST2, step ST3A, step ST5, and step ST6 are the same as step ST1, step ST2, step ST3A, step ST5, and step ST6 in the gate bias control circuit 200 according to the second embodiment. , the difference is that step ST4B is used instead of step ST4A.

That is, in step ST4B, when the input power Pin is less than the average input power Pinave (step ST2), the upper limit value of the gate bias voltage Vgt is limited to raise the gate bias voltage Vgt from the increased set voltage (step ST6). Specifically, the lower the input power Pin is, the higher the gate bias voltage Vgt is made to be than the increased set voltage (step ST4A).

Steps ST2 to ST5, ST6, ST3A, and ST4B include steps of increasing the set voltage over time, and limit the upper limit of the gate bias voltage Vgt according to the input power Pin of the input signal detected in the detection step. This is a bias voltage generation step in which the gate bias voltage Vgt applied to the FET is applied to the gate bias node to which the gate electrode of the FET is connected.

Steps ST2 to ST5, ST6, ST3A, and ST4B include steps of increasing the set voltage over time, and the upper limit of the gate bias voltage Vgt is limited so that the input power Pin of the input signal detected in the detection step is the average If the input power Pin is higher than the input power Pinave, the gate bias voltage Vgt is set to an increased set voltage, and if the input power Pin is less than the average input power Pinave, the lower the input power Pin is, the higher the gate bias voltage Vgt is set to be higher than the raised set voltage. This is a step of generating a bias voltage.
Thereafter, steps ST1 to ST4B are sequentially repeated.

Regarding the gate bias control circuit 300 according to the third embodiment, verification results by simulation will be explained based on FIGS. 27 to 33.
In the verification, a model with a large signal as an input signal was used in consideration of the influence of traps in the semiconductor constituting the FET. Specifically, the modulated wave signal as the input signal was 64QAM, the modulation bandwidth BW of the input signal was 20 MHz, the frequency of the input signal was 4 GHz, the drain voltage Vd was 50 V, and the idle drain current Idq was 20 mA/mm.
In FIGS. 27 to 33, dark, light black portions represent examples of the third embodiment, and light black portions represent examples of the second embodiment.

FIG. 27 shows an output signal that is a modulated wave signal from the FET, and shows an output spectrum with respect to frequency. The horizontal axis shows the frequency and the vertical axis shows the output spectrum.
FIG. 28 shows changes in the gate bias voltage Vgt from the gate bias control circuit 100. The horizontal axis represents time, and the vertical axis represents gate bias voltage.
FIG. 29 shows AM-AM characteristics. The horizontal axis shows the output power of the output signal, and the vertical axis shows the gain of the FET.
FIG. 30 shows AM-PM characteristics. The horizontal axis shows the output power of the output signal, and the vertical axis shows the phase.
FIG. 31 shows the change in FET gain. The horizontal axis represents time, and the vertical axis represents FET gain.
FIG. 32 shows the phase shift of the output signal. The horizontal axis shows time and the vertical axis shows phase.
Figure 33 shows ACPR.

As can be understood from FIG. 29, when the gate bias control circuit 300 according to the third embodiment is used, the dynamic AM-AM characteristics are such that the FET gain spreads with respect to the output power of the output signal compared to the comparative example. is suppressed, and the gain with respect to the output power in the dynamic AM-AM characteristic is flat compared to the second embodiment.

As can be understood from FIG. 31, when the gate bias control circuit 300 according to the third embodiment is used, excessive temporal fluctuations in gain of the FET are suppressed compared to the comparative example.
Furthermore, as understood from FIG. 33, ACPR (Alt) is approximately -37.4 dBc in the comparative example, and -43.6 dBc in the case where the gate bias control circuit 200 according to the second embodiment is used. When the gate bias control circuit 300 according to the third embodiment is used, the improvement is approximately -54.1.

As described above, the gate bias control circuit 300 according to the third embodiment limits the upper limit value of the gate bias voltage and controls the gate bias voltage Vgt of the communication amplification transistor FET according to the input power of the input signal. Since it is applied to the gate bias node to which the electrode is connected, the gain with respect to the output power in dynamic AM-AM characteristics can be made close to flat, and deterioration of distortion characteristics can be suppressed.

In the gate bias control circuit 300 according to the third embodiment, the bias voltage generation section 20 increases the set voltage over time, and communicates the gate bias voltage Vgt according to the input power Pin of the input signal detected by the detection section 10. Since the voltage is applied to the gate bias node to which the gate electrode of the amplifier transistor FET is connected, it is possible to suppress the influence of the memory effect due to traps in the FET and suppress the deterioration of the distortion characteristics.

In the gate bias control circuit 300 according to the third embodiment, the bias voltage generation section 20 increases the set voltage over time, and the input power Pin of the input signal detected by the detection section 10 is greater than or equal to the average input power Pinave of the input signal. If the gate bias voltage Vgt of the set voltage is applied to the gate bias node, and the input power Pin is less than the average input power Pinave, the upper limit value of the gate bias voltage is limited and the lower the input power Pin is, the higher the set voltage is. Since a high voltage is applied to the gate bias node, it is possible to prevent excessive gain reduction of the FET due to the effect of charging electrons to traps in the FET, and to make the gain close to flat with respect to the output power in dynamic AM-AM characteristics. Deterioration of distortion characteristics can be suppressed.

Note that it is possible to freely combine each embodiment, to modify any component of each embodiment, or to omit any component in each embodiment.

A gate bias control circuit according to the present disclosure uses a high-output amplifier used in a transmitter in a wireless base station system, particularly a gallium nitride transistor (GaN-Tr) or a gallium nitride transistor used as a communication amplification transistor. It is suitable as a high electron mobility transistor (GaN-HEMT) gate bias control circuit.

100, 200, 300 gate bias control circuit, 10 detection section, 20, 20A, 20B bias voltage generation section, 21, 21A voltage generation section, 22 limiter, 23 inverting amplifier, 24 second limiter, A1 first adder , A2 second adder, FET communication amplification transistor.

Claims (16)

1. a detection unit that detects an input signal of a communication amplification transistor into which a modulated wave signal obtained by modulating a carrier wave to a gate electrode is input as an input signal;
   a bias voltage generation unit that applies a gate bias voltage corresponding to the input power of the input signal detected by the detection unit to a gate bias node to which the gate electrode of the communication amplification transistor is connected;
   A gate bias control circuit for a communications amplification transistor.
2. The bias voltage generation section sets the gate bias voltage to a set voltage when the input power of the input signal is equal to or higher than the average input power in the input signal, and sets the gate bias voltage to a set voltage when the input power of the input signal is less than the average input power in the input signal. The gate bias control circuit according to claim 1, wherein the lower the input power of the input signal, the higher the voltage is set than the set voltage.
3. The bias voltage generating section includes:
   a voltage generator having a first voltage node that outputs a first voltage and a second voltage node that outputs a second voltage different from the first voltage;
   a limiter circuit that is connected to the output node of the detection section and limits an upper limit value of the voltage of the input signal appearing at the output node of the detection section;
   One input terminal is connected to a second voltage node of the voltage generator, the other input terminal is connected to one end of a limiter, and the second voltage at the second voltage node and the voltage at one end of the limiter are connected. a first adder that adds and outputs;
   an inverting amplifier that outputs a voltage obtained by inverting the output from the first adder;
   One input terminal is connected to the first voltage node of the voltage generator, the other input terminal is connected to the output terminal of the inverting amplifier, the output terminal is connected to the gate bias node, and the first voltage The gate bias control circuit according to claim 1, further comprising: a second adder that adds the first voltage at the node and the voltage at the output end of the inverting amplifier and outputs the result to the gate bias node.
4. The bias voltage generating section sets the set voltage to a voltage that increases with time, sets the gate bias voltage to the set voltage when the input power of the input signal is equal to or higher than the average input power of the input signal, and sets the gate bias voltage to the set voltage when the input power of the input signal is equal to or higher than the average input power of the input signal, and 2. The gate bias control circuit according to claim 1, wherein when the input power of the input signal is less than the average input power of the input signal, the lower the input power of the input signal, the higher the voltage is set than the set voltage.
5. The bias voltage generating section includes:
   a voltage generator having a first voltage node that outputs a first voltage that increases over time and a second voltage node that outputs a second voltage different from the first voltage;
   a limiter circuit that is connected to the output node of the detection section and limits an upper limit value of the voltage of the input signal appearing at the output node of the detection section;
   One input terminal is connected to a second voltage node of the voltage generator, the other input terminal is connected to one end of a limiter, and the second voltage at the second voltage node and the voltage at one end of the limiter are connected. a first adder that adds and outputs;
   an inverting amplifier that outputs a voltage obtained by inverting the output from the first adder;
   One input terminal is connected to the first voltage node of the voltage generator, the other input terminal is connected to the output terminal of the inverting amplifier, the output terminal is connected to the gate bias node, and the first voltage The gate bias control circuit according to claim 1, further comprising: a second adder that adds the first voltage at the node and the voltage at the output end of the inverting amplifier and outputs the result to the gate bias node.
6. The voltage generation section includes a first voltage generation section that outputs a first voltage to the first voltage node, and a second voltage generation section that outputs a second voltage to the second voltage node. Prepare,
   The first voltage generating section includes a pulsed DC power source whose output end is connected to the first voltage node, and a capacitor connected between the first voltage node and a ground node,
   the second voltage generator is a DC power supply;
   The gate bias control circuit according to claim 5.
7. The bias voltage generating section sets the set voltage to a voltage that increases with time, sets the gate bias voltage to the set voltage when the input power of the input signal is equal to or higher than the average input power of the input signal, and sets the gate bias voltage to the set voltage when the input power of the input signal is equal to or higher than the average input power of the input signal, and The gate according to claim 1, wherein the upper limit value of the gate bias voltage is limited when the input power of the input signal is less than the average input power of the input signal, and the lower the input power of the input signal, the higher the voltage is than the set voltage. Bias control circuit.
8. The bias voltage generating section includes:
   a voltage generator having a first voltage node that outputs a first voltage that increases over time and a second voltage node that outputs a second voltage different from the first voltage;
   a first limiter circuit that is connected to the output node of the detection section and limits an upper limit value of the voltage of the input signal appearing at the output node of the detection section;
   One input terminal is connected to a second voltage node of the voltage generator, the other input terminal is connected to one end of a limiter, and the second voltage at the second voltage node and the voltage at one end of the limiter are connected. a first adder that adds and outputs;
   an inverting amplifier that outputs a voltage obtained by inverting the output from the first adder;
   a second limiter circuit connected to the output end of the inverting amplifier and limiting an upper limit value of the voltage at the output end of the inverting amplifier;
   One input terminal is connected to the first voltage node of the voltage generator, the other input terminal is connected to the output terminal of the inverting amplifier, the output terminal is connected to the gate bias node, and the first voltage The gate bias control circuit according to claim 1, further comprising: a second adder that adds the first voltage at the node and the voltage at the output end of the inverting amplifier and outputs the result to the gate bias node.
9. The voltage generation section includes a first voltage generation section that outputs a first voltage to the first voltage node, and a second voltage generation section that outputs a second voltage to the second voltage node. Prepare,
   The first voltage generating section includes a pulsed DC power source whose output end is connected to the first voltage node, and a capacitor connected between the first voltage node and a ground node,
   the second voltage generator is a DC power supply;
   The gate bias control circuit according to claim 8.
10. The gate bias control circuit according to any one of claims 4 to 9, wherein the modulated wave signal as the input signal is a modulated wave signal transmitted by a time division duplex method.
11. The bias voltage generating section includes:
    a voltage generator having a first voltage node that outputs a first voltage and a second voltage node that outputs a second voltage different from the first voltage;
    a first limiter circuit that is connected to the output node of the detection section and limits an upper limit value of the voltage of the input signal appearing at the output node of the detection section;
    One input terminal is connected to a second voltage node of the voltage generator, the other input terminal is connected to one end of a limiter, and the second voltage at the second voltage node and the voltage at one end of the limiter are connected. a first adder that adds and outputs;
    an inverting amplifier that outputs a voltage obtained by inverting the output from the first adder;
    a second limiter circuit connected to the output end of the inverting amplifier and limiting an upper limit value of the voltage at the output end of the inverting amplifier;
    One input terminal is connected to the first voltage node of the voltage generator, the other input terminal is connected to the output terminal of the inverting amplifier, the output terminal is connected to the gate bias node, and the first voltage The gate bias control circuit according to claim 1, further comprising: a second adder that adds the first voltage at the node and the voltage at the output end of the inverting amplifier and outputs the result to the gate bias node.
12. A gate bias control method for controlling a gate bias voltage of a communication amplification transistor to which a modulated wave signal obtained by modulating a carrier wave to a gate electrode is input as an input signal, the method comprising:
    a detection step of detecting the input signal of the communication amplification transistor;
    a bias voltage generation step of applying a gate bias voltage corresponding to the input power of the input signal detected in the detection step to a gate bias node to which the gate electrode of the communication amplification transistor is connected;
    Gate bias control method with
13. The bias voltage generating step sets the gate bias voltage to a set voltage when the input power of the input signal is equal to or higher than the average input power in the input signal, and when the input power of the input signal is less than the average input power in the input signal. 13. The gate bias control method according to claim 12, wherein the lower the input power of the input signal, the higher the voltage is set than the set voltage.
14. The bias voltage generation step includes a step of increasing the set voltage over time, and the gate bias voltage is set to the set voltage when the input power of the input signal is equal to or higher than the average input power of the input signal, and the gate bias voltage is set to the set voltage when the input power of the input signal is equal to or higher than the average input power of the input signal, 13. The gate bias control method according to claim 12, wherein when the input power of the input signal is less than the average input power of the input signal, the lower the input power of the input signal, the higher the voltage is set than the set voltage.
15. The bias voltage generation step includes a step of increasing the set voltage over time, and the gate bias voltage is set to the set voltage when the input power of the input signal is equal to or higher than the average input power of the input signal, and the gate bias voltage is set to the set voltage when the input power of the input signal is equal to or higher than the average input power of the input signal, 13. The gate according to claim 12, wherein the upper limit value of the gate bias voltage is limited when the input power of the input signal is less than the average input power of the input signal, and the lower the input power of the input signal, the higher the voltage is than the set voltage. Bias control method.
16. The bias voltage generating step sets the gate bias voltage to the set voltage when the input power of the input signal is equal to or higher than the average input power in the input signal, and the input power of the input signal is set to the set voltage when the input power of the input signal is equal to or higher than the average input power in the input signal. 13. The gate bias control method according to claim 12, wherein the upper limit value of the gate bias voltage is limited so that the lower the input power of the input signal is, the higher the voltage is than the set voltage.

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