WO2023188116A1 - Signal generation circuit, control circuit, storage medium, and signal generation method - Google Patents

Signal generation circuit, control circuit, storage medium, and signal generation method Download PDF

Info

Publication number
WO2023188116A1
WO2023188116A1 PCT/JP2022/016017 JP2022016017W WO2023188116A1 WO 2023188116 A1 WO2023188116 A1 WO 2023188116A1 JP 2022016017 W JP2022016017 W JP 2022016017W WO 2023188116 A1 WO2023188116 A1 WO 2023188116A1
Authority
WO
WIPO (PCT)
Prior art keywords
input signal
signal
circuit
output
quantizer
Prior art date
Application number
PCT/JP2022/016017
Other languages
French (fr)
Japanese (ja)
Inventor
道也 早馬
修平 山口
Original Assignee
三菱電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to PCT/JP2022/016017 priority Critical patent/WO2023188116A1/en
Priority to JP2024501260A priority patent/JP7459409B2/en
Publication of WO2023188116A1 publication Critical patent/WO2023188116A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/02—Delta modulation, i.e. one-bit differential modulation

Definitions

  • the present disclosure relates to a signal generation circuit having a quantizer, a control circuit, a storage medium, and a signal generation method.
  • Direct digital RF uses a delta-sigma DAC (Digital Analog Converter) to directly output an RF (Radio Frequency) signal from an FPGA (Field Programmable Gate Array), has been studied.
  • Direct digital RF often uses high-speed serial output circuits built into FPGAs as output circuits, but the SNR ( Signal to Noise Ratio) deteriorates.
  • Methods to improve the SNR include increasing the filter order of the delta-sigma DAC itself, using a multi-bit quantizer in the delta-sigma DAC quantizer, and using a MASH (Multi Age noise SHAping) type delta-sigma conversion circuit.
  • MASH Multi Age noise SHAping
  • circuit scale is limited by the capacity of the FPGA.
  • number of quantization bits is limited by the number of multi-values that can be output by the built-in high-speed serial output circuit.
  • a method of increasing the filter order of the delta-sigma DAC itself is effective in reducing quantization noise, but cannot reduce the influence of phase noise.
  • the method of increasing the filter order of the delta-sigma DAC itself has problems in that the stability of the delta-sigma conversion circuit itself decreases and the circuit scale increases due to the increase in the number of multipliers.
  • a method using a MASH type delta-sigma conversion circuit is also effective in reducing quantization noise, but cannot reduce the influence of phase noise. Furthermore, since the final stage output of the MASH type delta-sigma conversion circuit is multi-valued, there are significant restrictions when implementing it with a high-speed serial output circuit built into an FPGA. For example, in a 1-1 MASH type delta-sigma conversion circuit, the number of multi-values required for a high-speed serial output circuit can be suppressed to about 3 by replacing the adder circuit immediately before the output with an analog multiplexing circuit. I can do it.
  • Patent Document 1 utilizes the characteristic that delta-sigma conversion circuits with different initial values output different signal sequences even if the input signal is the same, and uses the characteristic that delta-sigma conversion circuits with different initial values output different signal sequences. It is possible to reduce both quantization noise and phase noise by externally combining . However, there is a problem in that it is necessary to prepare a plurality of delta-sigma conversion circuits in order to obtain outputs from delta-sigma DACs of different series, resulting in an increase in circuit scale.
  • the present disclosure has been made in view of the above, and provides a signal generation circuit that can suppress signal deterioration due to quantization noise and phase noise of delta-sigma signal output while suppressing increases in the number of multi-values and circuit scale.
  • the purpose is to obtain.
  • the signal generation circuit of the present disclosure generates a difference between the output signal of the first quantizer and the first input signal to the first input signal quantization circuit.
  • a first-stage error-feedback type first input signal quantization circuit that uses the signal as an input signal to the first filter, and uses the output signal from the first filter as the input signal to the first quantizer;
  • a signal distribution unit that distributes the difference between the input signal to the first quantizer and the output signal from the first quantizer to two or more second input signal quantization circuits as a second input signal; each takes the difference between the output signal of the second quantizer and the second input signal to the second input signal quantization circuit as the input signal to the second filter, and outputs the output signal from the second filter.
  • the signal generation circuit is characterized in that it combines and outputs a first output signal from a first input signal quantization circuit and a second output signal from two or more second input signal quantization circuits. do.
  • the signal generation circuit according to the present disclosure has the effect of suppressing signal deterioration due to quantization noise and phase noise of the delta-sigma signal output while suppressing an increase in the number of multi-values and circuit scale.
  • Flowchart showing the operation of the initial value control section of the signal generation circuit according to the first embodiment is a diagram illustrating an example of the configuration of a processing circuit when the processing circuit that implements the signal generation circuit according to Embodiment 1 is implemented using a processor and memory;
  • FIG. A diagram showing an example of a processing circuit when the processing circuit realizing the signal generation circuit according to Embodiment 1 is configured with dedicated hardware.
  • FIG. 1 is a diagram showing a configuration example of a signal generation circuit 1 according to the first embodiment.
  • the signal generation circuit 1 includes a transmission signal generation section 2, input signal quantization circuits 3-1 to 3-N, a signal distribution section 5, an initial value control section 6, and an analog multiplexing circuit 7.
  • the input signal quantization circuits 3-1 to 3-N are MASH type delta-sigma conversion circuits.
  • a delta-sigma conversion circuit is also called a delta-sigma modulation circuit. Note that N is a positive integer of 3 or more.
  • the input signal quantization circuit 3-1 includes a subtracter 12-1, a loop filter 13-1, a quantizer 14-1, a high-speed serial output circuit 16-1, and a feedback path 17-1.
  • the input signal quantization circuit 3-2 includes a gain section 11-2, a subtracter 12-2, a loop filter 13-2, a quantizer 14-2, a combination filter 15-2, and a high-speed serial output circuit. 16-2, and a return path 17-2.
  • the input signal quantization circuit 3-N includes a gain section 11-N, a subtracter 12-N, a loop filter 13-N, a quantizer 14-N, and a combination filter 15-N. , a high-speed serial output circuit 16-N, and a feedback path 17-N.
  • the input signal quantization circuits 3-2 to 3-N constitute an input signal quantization circuit group 4.
  • the input signal quantization circuit 3-1 is the first stage input signal quantization circuit
  • the input signal quantization circuits 3-2 to 3-N that is, the input signal quantization circuit group 4 are This is the input signal quantization circuit in the second stage. Since N is a positive integer of 3 or more, the input signal quantization circuit group 4, which is the second stage input signal quantization circuit, has two or more input signal quantization circuits 3.
  • the input signal quantization circuit 3-1 will be referred to as a first input signal quantization circuit
  • the loop filter 13-1 will be referred to as a first filter
  • the quantizer 14-1 will be referred to as a first quantization circuit.
  • the high-speed serial output circuit 16-1 is referred to as a first high-speed serial output circuit
  • the input signal to the input signal quantization circuit 3-1 is referred to as a first input signal
  • the input signal quantization circuit 3-1 is referred to as a first input signal.
  • the output signal from 1 is sometimes referred to as the first output signal.
  • the input signal quantization circuits 3-2 to 3-N are referred to as second input signal quantization circuits
  • the loop filters 13-2 to 13-N are referred to as second filters
  • the quantizers 14-2 to 3-N are referred to as second input signal quantization circuits.
  • 14-N is referred to as a second quantizer
  • high-speed serial output circuits 16-2 to 16-N are referred to as second high-speed serial output circuits.
  • the signal may be referred to as a second input signal
  • the output signals from the input signal quantization circuits 3-2 to 3-N may be referred to as second output signals.
  • the input signal quantization circuits 3-1 to 3-N are not distinguished, they are referred to as the input signal quantization circuit 3, and when the gain sections 11-2 to 11-N are not distinguished, they are referred to as the input signal quantization circuit 3.
  • the subtracters 12-1 to 12-N are not distinguished, they are called the subtracter 12, and when the loop filters 13-1 to 13-N are not distinguished, they are called the loop filter 13, and the quantizers 14-1 to 14-N are called the loop filter 13.
  • the quantizer 14 when the combination filters 15-2 to 15-N are not distinguished, it is called the combination filter 15, and when the high-speed serial output circuits 16-1 to 16-N are not distinguished, it is called the quantizer 14.
  • the signal generation circuit 1 includes N-1 gain units 11, N subtracters 12, N loop filters 13, N quantizers 14, and N-1 combination filters. 15, N high-speed serial output circuits 16, and N feedback paths 17.
  • the transmission signal generation unit 2 generates a transmission signal x(z) and outputs it to the input signal quantization circuit 3-1.
  • the subtracter 12-1 calculates the difference between the transmission signal x(z) and the signal from the feedback path 17-1, which is the output signal from the quantizer 14-1. That is, the signal on the feedback path 17-1 is subtracted from the transmission signal x(z) and output to the loop filter 13-1.
  • the loop filter 13-1 is generally configured by a combination of an FIR (Finite Impulse Response) filter and an IIR (Infinite Impulse Response) filter as shown in FIG.
  • FIG. 2 is a diagram showing a configuration example of the loop filter 13 of the signal generation circuit 1 according to the first embodiment.
  • the loop filter 13 includes an FIR filter 131, an IIR filter 132, and a subtracter 133.
  • Loop filter 13 filters the output signal from subtracter 12 using FIR filter 131 .
  • the loop filter 13 uses a subtracter 133 to calculate the difference between the output signal from the FIR filter 131 and the output signal from the IIR filter 132 and outputs the difference. Further, the loop filter 13 filters a signal obtained by branching the output signal from the loop filter 13 using an IIR filter 132 .
  • the output signal from the loop filter 13-1 is quantized by the quantizer 14-1, outputted from the high-speed serial output circuit 16-1, and also sent to the subtracter 12-1 via the feedback path 17-1. Used to take the
  • Quantizer 14-1 outputs a value according to the magnitude of the output signal from loop filter 13-1. For example, the quantizer 14-1 outputs 1 when the value of the output signal from the loop filter 13-1 is 0 or more, and - when the value of the output signal from the loop filter 13-1 is less than 0. Outputs 1.
  • the signal output from the quantizer 14-1 is represented as y 1 (z).
  • the high-speed serial output circuit 16-1 uses an output circuit having the same number of quantization bits as the quantizer 14-1 connected to the previous stage, and outputs a signal according to the value of the output signal from the quantizer 14-1. Output the value.
  • the quantization error of the first-stage delta-sigma conversion circuit that is, the difference between the input value and the output value of the quantizer, is canceled by the second-stage delta-sigma conversion circuit and subsequent stages. This reduces quantization noise.
  • the signal generation circuit 1 of the present embodiment converts the quantization error of the first stage input signal quantization circuit 3-1, which is a MASH type delta-sigma conversion circuit, into two stages connected in parallel. The signal is distributed to input signal quantization circuits 3-2 to 3-N, which are N-1 delta-sigma conversion circuits, and outputted.
  • the signal generation circuit 1 receives an output signal from an input signal quantization circuit 3-1, which is a delta-sigma conversion circuit in the first stage, and an input signal quantization circuit, which is N-1 delta-sigma conversion circuits in the second stage. By combining the output signals from 3-2 to 3-N with an analog multiplexing circuit 7 outside the FPGA, quantization noise is reduced. As shown in FIG. 1, in the signal generation circuit 1, the configuration other than the analog multiplexing circuit 7 is assumed to be implemented by FPGA, but the configuration of the signal generation circuit 1 is similar to the example in FIG. Not limited.
  • the signal distribution section 5 includes a subtracter 51.
  • the subtracter 51 connects the output signal from the loop filter 13-1 of the input signal quantization circuit 3-1 and the feedback path 17- which is the output signal from the quantizer 14-1 of the input signal quantization circuit 3-1. 1, that is, the signal on the feedback path 17-1 is subtracted from the output signal of the loop filter 13-1.
  • the signal distribution unit 5 distributes the difference obtained by the subtracter 51 to the input signal quantization circuits 3-2 to 3-N as a quantization error of the first stage input signal quantization circuit 3-1. In this way, the signal distribution unit 5 uses the difference between the input signal to the quantizer 14-1 and the output signal from the quantizer 14-1 as a second input signal to the input signal quantization circuits 3-2 to 3-2. 3-Distribute to N.
  • the gain section 11-n calculates a gain # for the quantization error of the distributed first-stage input signal quantization circuit 3-1. Multiply by n. Note that n is a positive integer from 2 to N.
  • the subtracter 12-n calculates the difference between the output signal from the gain section 11-n and the signal from the feedback path 17-n, which is the output signal from the quantizer 14-n.
  • the signal on the feedback path 17-n is subtracted from the output signal from -n, and the result is output to the loop filter 13-n.
  • the configuration of the loop filter 13-n is similar to the configuration of the loop filter 13-1 described above.
  • the output signal from the loop filter 13-n is quantized by a quantizer 14-n, passed through a combination filter 15-n, and outputted from a high-speed serial output circuit 16-n, as well as a feedback path 17-n.
  • the subtracter 12-n uses the subtracter 12-n to calculate the difference between the signal and the output signal from the gain section 11-n.
  • the quantizer 14-n outputs a value according to the magnitude of the output signal from the loop filter 13-n. For example, the quantizer 14-n outputs 1 when the value of the output signal from the loop filter 13-n is 0 or more, and - when the value of the output signal from the loop filter 13-n is less than 0. Outputs 1.
  • the combination filter 15-n is a unique filter set to cancel the quantization error of the first-stage input signal quantization circuit 3-1, and is an FIR filter, an IIR filter, or an FIR filter and an IIR filter.
  • the combination filter 15-n performs filter processing on the output signal from the quantizer 14-n and outputs it to the high-speed serial output circuit 16-n.
  • the signals output from the coupling filters 15-2 to 15-N are expressed as y 2 (z) to y N (z).
  • the high-speed serial output circuit 16-n uses an output circuit having the same number of quantization bits as the quantizer 14-n connected before the combination filter 15-n.
  • Equation (1) corresponds to the filter characteristics of the loop filters 13-1 to 13-N
  • Equation (2) corresponds to the filter characteristics of the combined filters 15-2 to 15-N.
  • z ⁇ 1 is a coefficient used in general delay elements.
  • the initial values of the loop filters 13-2 to 13-N included in two or more input signal quantization circuits 3-2 to 3-N are set to different values for each of the loop filters 13-2 to 13-N. .
  • the gains set in the gain sections 11-2 to 11-N are set to values such that the total value of the coefficients becomes 1. It is conceivable to set it to 1/(N-1). In this way, the two or more input signal quantization circuits 3-2 to 3-N each multiply the input signal by a different coefficient, and compare the output signal of the quantizer 14 with the input signal after multiplication by the coefficient. The difference is used as an input signal to the loop filter 13. Further, the sum of two or more coefficients multiplied by the input signal by two or more input signal quantization circuits 3-2 to 3-N is set to 1.
  • FIG. 3 is a diagram showing a configuration example of the high-speed serial output circuit 16 of the signal generation circuit 1 according to the first embodiment.
  • the high-speed serial output circuit 16 includes an encoder 161, high-speed serial output circuits 162 and 163, and an analog multiplexing circuit 164.
  • the high-speed serial output circuit 16 can realize ternary output by combining the output signals of the two high-speed serial output circuits 162 and 163 with the analog multiplexing circuit 164.
  • the high-speed serial output circuits 162 and 163 simultaneously output -1.
  • the encoder 161 outputs the opposite value from the high-speed serial output circuits 162 and 163, that is, 1 is output from the high-speed serial output circuit 162, and -1 is output from the high-speed serial output circuit 163, Alternatively, control is performed so that -1 is output from the high-speed serial output circuit 162 and 1 is output from the high-speed serial output circuit 163.
  • the high-speed serial output circuit 16-1 enables multi-value output by using two or more high-speed serial output circuits.
  • each of the high-speed serial output circuits 16-2 to 16-N is capable of multi-value output by using two or more high-speed serial output circuits.
  • the analog multiplexing circuit 7 multiplexes the signals output from the high-speed serial output circuits 16-1 to 16-N in an analog manner and outputs the multiplexed signals.
  • FIG. 4 is a diagram showing a configuration example of the analog multiplexing circuit 7 of the signal generation circuit 1 according to the first embodiment.
  • the analog multiplexing circuit 7 includes power distribution circuits 71 to 77.
  • the power distribution circuits 71 to 77 are, for example, circuit elements such as resistive power combiners and Wilkinson dividers that can combine power at a fixed ratio. Note that the analog multiplexing circuit 7 may be configured to also play the role of the analog multiplexing circuit 164 included in the high-speed serial output circuit 16 with ternary output shown in FIG.
  • FIG. 5 is a flowchart showing the operation of the initial value control section 6 of the signal generation circuit 1 according to the first embodiment.
  • the initial value control unit 6 randomly sets the initial values of the FIR filter 131 and the IIR filter 132 inside the loop filters 13-2 to 13-N at the timing when the signal generation circuit 1 starts operating (step S101).
  • the signal generation circuit 1 After the setting by the initial value control unit 6, the signal generation circuit 1 outputs the transmission signal x(z) from the transmission signal generation unit 2, and starts a conversion process for the transmission signal x(z).
  • FIG. 6 is a flowchart showing the operation of the signal generation circuit 1 according to the first embodiment.
  • the first stage input signal quantization circuit 3-1 receives the transmission signal x(z) from the transmission signal generation section 2
  • the first stage input signal quantization circuit 3-1 performs a subtracter 12-1, a loop filter 13-1
  • a first quantization process is performed by the quantizer 14-1 and the high-speed serial output circuit 16-1 (step S201), and the output signal from the high-speed serial output circuit 16-1 is output to the analog multiplexing circuit 7.
  • the input signal to the quantizer 14-1 and the output signal from the quantizer 14-1 are output to the signal distribution section 5.
  • the signal distribution unit 5 calculates the difference between the input signal to the quantizer 14-1 and the output signal from the quantizer 14-1 (step S202).
  • the signal distribution unit 5 distributes the calculated difference as an input signal to the second-stage input signal quantization circuits 3-2 to 3-N (step S203).
  • the second-stage input signal quantization circuits 3-2 to 3-N each include a gain section 11, a subtracter 12, a loop filter 13, a quantizer 14,
  • a second quantization process is performed by the combination filter 15 and the high-speed serial output circuit 16 (step S204), and the output signal from the high-speed serial output circuit 16 is output to the analog multiplexing circuit 7.
  • the analog multiplexing circuit 7 synthesizes the output signals from the input signal quantization circuits 3-1 to 3-N (step S205) and outputs the synthesized signal.
  • the first stage error feedback type input signal quantization circuit 3-1 calculates the difference between the output signal of the quantizer 14-1 and the first input signal to the input signal quantization circuit 3-1. is an input signal to the loop filter 13-1, and an output signal from the loop filter 13-1 is an input signal to the quantizer 14-1.
  • the input signal quantization circuit 3-1 outputs an output signal using the high-speed serial output circuit 16-1.
  • the two or more second-stage error feedback type input signal quantization circuits 3-2 to 3-N each input the output signal of the quantizer 14 and the input signal to the input signal quantization circuit 3. The difference is used as an input signal to the loop filter 13, and the output signal from the loop filter 13 is used as an input signal to the quantizer 14.
  • Each of the two or more input signal quantization circuits 3-2 to 3-N outputs an output signal using the high-speed serial output circuit 16.
  • the analog multiplexing circuit 7 combines the output signal from the input signal quantization circuit 3-1 and the output signals from two or more input signal quantization circuits 3-2 to 3-N. Output.
  • the analog multiplexing circuit 7 is realized by an analog circuit as shown in FIG.
  • the high-speed serial output circuits 16-1 to 16-N have a circuit configuration as shown in FIG. 3, and as described above, are built in an FPGA or the like.
  • other configurations are realized by a processing circuit.
  • the processing circuit may be a processor and memory that executes a program stored in memory, or may be dedicated hardware.
  • the processing circuit is also called a control circuit.
  • FIG. 7 is a diagram illustrating a configuration example of the processing circuit 90 when the processing circuit realizing the signal generation circuit 1 according to the first embodiment is implemented by the processor 91 and the memory 92.
  • FIG. 7 includes high-speed serial output circuits 16-1 to 16-N and an analog multiplexing circuit 7.
  • a processing circuit 90 shown in FIG. 7 is a control circuit, and includes a processor 91 and a memory 92.
  • each function of the processing circuit 90 is realized by software, firmware, or a combination of software and firmware.
  • Software or firmware is written as a program and stored in memory 92.
  • each function is realized by a processor 91 reading and executing a program stored in a memory 92.
  • the processing circuit 90 includes a memory 92 for storing a program by which the processing of the signal generating circuit 1 is executed as a result.
  • This program can also be said to be a program for causing the signal generation circuit 1 to execute each function realized by the processing circuit 90.
  • This program may be provided by a storage medium in which the program is stored, or may be provided by other means such as a communication medium.
  • the first stage error feedback type input signal quantization circuit 3-1 converts the difference between the output signal of the quantizer 14-1 and the input signal to the input signal quantization circuit 3-1 into a loop filter.
  • Two or more input signal quantization circuits 3-2 to 3-N of the eye error feedback type each calculate the difference between the output signal of the quantizer 14 and the second input signal to the input signal quantization circuit 3. It can also be said that this is a program executed by the signal generation circuit 1, including a third step in which the input signal is input to the loop filter 13 and the output signal from the loop filter 13 is input to the quantizer 14.
  • the processor 91 is, for example, a CPU (Central Processing Unit), a processing device, an arithmetic device, a microprocessor, a microcomputer, or a DSP (Digital Signal Processor).
  • the memory 92 may be a nonvolatile or volatile memory such as RAM (Random Access Memory), ROM (Read Only Memory), flash memory, EPROM (Erasable Programmable ROM), or EEPROM (registered trademark) (Electrically EPROM). This includes semiconductor memory, magnetic disks, flexible disks, optical disks, compact disks, mini disks, and DVDs (Digital Versatile Discs).
  • FIG. 8 is a diagram showing an example of the processing circuit 93 in the case where the processing circuit realizing the signal generation circuit 1 according to the first embodiment is configured with dedicated hardware.
  • FIG. 8 includes high-speed serial output circuits 16-1 to 16-N and an analog multiplexing circuit 7.
  • the processing circuit 93 shown in FIG. 8 is, for example, a single circuit, a composite circuit, a programmed processor, a parallel programmed processor, an ASIC (Application Specific Integrated Circuit), an FPGA, or a combination thereof.
  • a part may be realized by dedicated hardware, and a part may be realized by software or firmware. In this way, the processing circuit can implement each of the above-mentioned functions using dedicated hardware, software, firmware, or a combination thereof.
  • the signal generation circuit 1 is a two-stage MASH type delta-sigma conversion circuit, in which the first stage is composed of the input signal quantization circuit 3-1, and the second stage is composed of the input signal quantization circuit 3-1. are configured in parallel with input signal quantization circuits 3-2 to 3-N, and by giving different initial values to the second-stage input signal quantization circuits 3-2 to 3-N, different series of delta-sigma signals can be generated.
  • the analog multiplexing circuit 7 synthesizes the output signals from the input signal quantization circuits 3-1 to 3-N.
  • the signal generation circuit 1 suppresses quantization noise more than a simple two-stage MASH-type delta-sigma conversion circuit without increasing the number of output values unlike a three-stage or more-stage MASH-type delta-sigma conversion circuit. be able to. Furthermore, since the signal generation circuit 1 parallelizes only the second stage, it is possible to reduce the circuit scale required to synthesize delta-sigma outputs of different series compared to the method described in Patent Document 1. can. The signal generation circuit 1 can suppress signal deterioration due to quantization noise and phase noise of the delta-sigma signal output while suppressing an increase in the number of multilevel values and circuit scale.
  • the signal generation circuit 1 uses the initial value control unit 6 to set initial values to the FIR filter 131 and the IIR filter 132 inside the loop filters 13-2 to 13-N.
  • the signal generation circuit does not include the initial value control section 6 will be described.
  • FIG. 9 is a diagram showing a configuration example of the signal generation circuit 1a according to the second embodiment.
  • the signal generation circuit 1a is obtained by removing the initial value control section 6 from the signal generation circuit 1 shown in FIG.
  • random values as shown in equation (3) are set in advance for the gain sections 11-2 to 11-N.
  • the input signal quantization circuits 3-2 to 3-N are delta-sigma conversion circuits, and when the base signal waveforms are the same but have different amplitudes, they output different output signal sequences with low correlation. It has the characteristics of Therefore, by utilizing the characteristics of the input signal quantization circuits 3-2 to 3-N, the signal generation circuit 1a eliminates the need for the initial value control section 6, and the signal generation circuit 1 of the first embodiment. The same effect as that obtained when the initial value is randomly set can be obtained.

Abstract

A signal generation circuit (1) includes: a first-stage error-feedback-type input signal quantization circuit (3-1) that uses a difference between an output signal of a first quantizer and a first input signal as an input signal to a first filter and uses an output signal from the first filter as an input signal to the first quantizer; a signal distribution unit (5) that uses a difference between the input signal to the first quantizer and the output signal from the first quantizer as a second input signal and distributes the second input signal to two or more input signal quantization circuits (3-2 to 3-N); and the two or more second-stage error-feedback-type input signal quantization circuits (3-2 to 3-N) each uses a difference between an output signal of a second quantizer and the second input signal as an input signal to a second filter and uses an output signal from the second filter as an input signal to the second quantizer. A first output signal from the input signal quantization circuit (3-1) and second output signals from the two or more input signal quantization circuits (3-2 to 3-N) are synthesized and output.

Description

信号発生回路、制御回路、記憶媒体および信号発生方法Signal generation circuit, control circuit, storage medium and signal generation method
　本開示は、量子化器を有する信号発生回路、制御回路、記憶媒体および信号発生方法に関する。 The present disclosure relates to a signal generation circuit having a quantizer, a control circuit, a storage medium, and a signal generation method.
　近年、デルタシグマＤＡＣ（Digital　Analog　Converter）を用いてＦＰＧＡ（Field　Programmable　Gate　Array）から直接ＲＦ（Radio　Frequency）信号を出力するダイレクトデジタルＲＦと呼ばれる手法が検討されている。ダイレクトデジタルＲＦは、出力回路としてＦＰＧＡに内蔵されている高速シリアル出力回路を多く用いるが、１ｂｉｔ量子化器から発生する量子化雑音、および高速シリアル出力回路の出力クロックに起因する位相雑音によってＳＮＲ（Signal　to　Noise　Ratio）が劣化する。ＳＮＲを改善する手法としては、デルタシグマＤＡＣ自体のフィルタ次数を上げる手法、デルタシグマＤＡＣの量子化器に多ビットの量子化器を用いる手法、ＭＡＳＨ（Multi　stAge　noise　SHaping）型のデルタシグマ変換回路を用いる手法などがある。また、ＳＮＲを改善する手法として、特許文献１には、同一入力で異なる系列のデルタシグマ出力を合成する手法が開示されている。 In recent years, a method called direct digital RF, which uses a delta-sigma DAC (Digital Analog Converter) to directly output an RF (Radio Frequency) signal from an FPGA (Field Programmable Gate Array), has been studied. Direct digital RF often uses high-speed serial output circuits built into FPGAs as output circuits, but the SNR ( Signal to Noise Ratio) deteriorates. Methods to improve the SNR include increasing the filter order of the delta-sigma DAC itself, using a multi-bit quantizer in the delta-sigma DAC quantizer, and using a MASH (Multi　Age　noise　SHAping) type delta-sigma conversion circuit. There are methods that use Further, as a method for improving the SNR, Patent Document 1 discloses a method of combining delta-sigma outputs of different series from the same input.
欧州特許出願公開第２５０６４２６号明細書European Patent Application No. 2506426
　デルタシグマＤＡＣをＦＰＧＡで実装する際の制約には、回路規模、および量子化ビット数の２つがある。回路規模は、ＦＰＧＡの容量によって制約を受ける。また、量子化ビット数は、内蔵する高速シリアル出力回路の出力可能な多値数によって制約を受ける。特に汎用のＦＰＧＡに内蔵されている高速シリアル出力回路の多値数は最大でも２ｂｉｔ程度であるため、量子化器の多ビット化によるＳＮＲの改善には限界がある。デルタシグマＤＡＣ自体のフィルタ次数を上げる方法は、量子化雑音の低減には効果があるが、位相雑音の影響を低減することはできない。また、デルタシグマＤＡＣ自体のフィルタ次数を上げる方法は、デルタシグマ変換回路自体の安定性が低下するほか、乗算器の増加による回路規模の増加が問題となる。 There are two constraints when implementing a delta-sigma DAC in FPGA: circuit scale and number of quantization bits. The circuit scale is limited by the capacity of the FPGA. Further, the number of quantization bits is limited by the number of multi-values that can be output by the built-in high-speed serial output circuit. In particular, since the number of multi-values in a high-speed serial output circuit built into a general-purpose FPGA is about 2 bits at most, there is a limit to the improvement of SNR by increasing the number of bits in a quantizer. A method of increasing the filter order of the delta-sigma DAC itself is effective in reducing quantization noise, but cannot reduce the influence of phase noise. Furthermore, the method of increasing the filter order of the delta-sigma DAC itself has problems in that the stability of the delta-sigma conversion circuit itself decreases and the circuit scale increases due to the increase in the number of multipliers.
　ＭＡＳＨ型のデルタシグマ変換回路を用いる方法も、量子化雑音の低減には効果があるが、位相雑音の影響を低減することはできない。さらに、ＭＡＳＨ型のデルタシグマ変換回路は、最終段の出力が多値化されるため、ＦＰＧＡ内蔵の高速シリアル出力回路で実装する上での制約が大きい。例えば、１－１ＭＡＳＨ型のデルタシグマ変換回路は、出力直前の加算器の回路部分をアナログ合波回路で代替することで、高速シリアル出力回路に必要とされる多値数を３程度に抑えることができる。しかしながら、１－１－１ＭＡＳＨ型のデルタシグマ変換回路は、前述のアナログ合波回路で代替する手法を用いたとしても、高速シリアル出力回路に必要とされる多値数が５となり、汎用のＦＰＧＡでの実装が困難である。 A method using a MASH type delta-sigma conversion circuit is also effective in reducing quantization noise, but cannot reduce the influence of phase noise. Furthermore, since the final stage output of the MASH type delta-sigma conversion circuit is multi-valued, there are significant restrictions when implementing it with a high-speed serial output circuit built into an FPGA. For example, in a 1-1 MASH type delta-sigma conversion circuit, the number of multi-values required for a high-speed serial output circuit can be suppressed to about 3 by replacing the adder circuit immediately before the output with an analog multiplexing circuit. I can do it. However, in the 1-1-1 MASH type delta-sigma conversion circuit, even if the above-mentioned analog multiplexing circuit is used instead, the number of multi-values required for a high-speed serial output circuit is 5, and it is difficult to use a general-purpose FPGA. It is difficult to implement in
　特許文献１に記載の手法は、初期値の異なるデルタシグマ変換回路は入力信号が同じであっても異なる信号系列を出力するという特性を利用し、異なる初期値を与えたデルタシグマ変換回路の出力を外部で合成することによって、量子化雑音および位相雑音の両方を低減することが可能である。しかしながら、異なる系列のデルタシグマＤＡＣの出力を得るためにデルタシグマ変換回路を複数用意する必要があり、回路規模が大きくなってしまう、という問題があった。 The method described in Patent Document 1 utilizes the characteristic that delta-sigma conversion circuits with different initial values output different signal sequences even if the input signal is the same, and uses the characteristic that delta-sigma conversion circuits with different initial values output different signal sequences. It is possible to reduce both quantization noise and phase noise by externally combining . However, there is a problem in that it is necessary to prepare a plurality of delta-sigma conversion circuits in order to obtain outputs from delta-sigma DACs of different series, resulting in an increase in circuit scale.
　本開示は、上記に鑑みてなされたものであって、多値数および回路規模の増加を抑制しつつ、デルタシグマ信号出力の量子化雑音および位相雑音による信号劣化を抑制可能な信号発生回路を得ることを目的とする。 The present disclosure has been made in view of the above, and provides a signal generation circuit that can suppress signal deterioration due to quantization noise and phase noise of delta-sigma signal output while suppressing increases in the number of multi-values and circuit scale. The purpose is to obtain.
　上述した課題を解決し、目的を達成するために、本開示の信号発生回路は、第１の量子化器の出力信号と第１の入力信号量子化回路への第１の入力信号との差分を第１のフィルタへの入力信号とし、第１のフィルタからの出力信号を第１の量子化器への入力信号とする１段目の誤差フィードバック型の第１の入力信号量子化回路と、第１の量子化器への入力信号と第１の量子化器からの出力信号との差分を第２の入力信号として２以上の第２の入力信号量子化回路へ分配する信号分配部と、各々が、第２の量子化器の出力信号と第２の入力信号量子化回路への第２の入力信号との差分を第２のフィルタへの入力信号とし、第２のフィルタからの出力信号を第２の量子化器への入力信号とする２段目の誤差フィードバック型の２以上の第２の入力信号量子化回路と、を備える。信号発生回路は、第１の入力信号量子化回路からの第１の出力信号と２以上の第２の入力信号量子化回路からの第２の出力信号とを合成して出力することを特徴とする。 In order to solve the above-mentioned problems and achieve the purpose, the signal generation circuit of the present disclosure generates a difference between the output signal of the first quantizer and the first input signal to the first input signal quantization circuit. a first-stage error-feedback type first input signal quantization circuit that uses the signal as an input signal to the first filter, and uses the output signal from the first filter as the input signal to the first quantizer; a signal distribution unit that distributes the difference between the input signal to the first quantizer and the output signal from the first quantizer to two or more second input signal quantization circuits as a second input signal; each takes the difference between the output signal of the second quantizer and the second input signal to the second input signal quantization circuit as the input signal to the second filter, and outputs the output signal from the second filter. and two or more second-stage error feedback type second input signal quantization circuits that input the signal to the second quantizer. The signal generation circuit is characterized in that it combines and outputs a first output signal from a first input signal quantization circuit and a second output signal from two or more second input signal quantization circuits. do.
　本開示に係る信号発生回路は、多値数および回路規模の増加を抑制しつつ、デルタシグマ信号出力の量子化雑音および位相雑音による信号劣化を抑制できる、という効果を奏する。 The signal generation circuit according to the present disclosure has the effect of suppressing signal deterioration due to quantization noise and phase noise of the delta-sigma signal output while suppressing an increase in the number of multi-values and circuit scale.
実施の形態１に係る信号発生回路の構成例を示す図A diagram showing a configuration example of a signal generation circuit according to Embodiment 1. 実施の形態１に係る信号発生回路のループフィルタの構成例を示す図A diagram showing a configuration example of a loop filter of the signal generation circuit according to Embodiment 1. 実施の形態１に係る信号発生回路の高速シリアル出力回路の構成例を示す図A diagram showing a configuration example of a high-speed serial output circuit of the signal generation circuit according to Embodiment 1. 実施の形態１に係る信号発生回路のアナログ合波回路の構成例を示す図A diagram showing a configuration example of an analog multiplexing circuit of the signal generation circuit according to Embodiment 1. 実施の形態１に係る信号発生回路の初期値制御部の動作を示すフローチャートFlowchart showing the operation of the initial value control section of the signal generation circuit according to the first embodiment 実施の形態１に係る信号発生回路の動作を示すフローチャートFlowchart showing the operation of the signal generation circuit according to the first embodiment 実施の形態１に係る信号発生回路を実現する処理回路をプロセッサおよびメモリで実現する場合の処理回路の構成例を示す図1 is a diagram illustrating an example of the configuration of a processing circuit when the processing circuit that implements the signal generation circuit according to Embodiment 1 is implemented using a processor and memory; FIG. 実施の形態１に係る信号発生回路を実現する処理回路を専用のハードウェアで構成する場合の処理回路の例を示す図A diagram showing an example of a processing circuit when the processing circuit realizing the signal generation circuit according to Embodiment 1 is configured with dedicated hardware. 実施の形態２に係る信号発生回路の構成例を示す図A diagram showing a configuration example of a signal generation circuit according to Embodiment 2
　以下に、本開示の実施の形態に係る信号発生回路、制御回路、記憶媒体および信号発生方法を図面に基づいて詳細に説明する。 Below, a signal generation circuit, a control circuit, a storage medium, and a signal generation method according to embodiments of the present disclosure will be described in detail based on the drawings.
実施の形態１．
　図１は、実施の形態１に係る信号発生回路１の構成例を示す図である。信号発生回路１は、送信信号生成部２と、入力信号量子化回路３－１～３－Ｎと、信号分配部５と、初期値制御部６と、アナログ合波回路７と、を備える。入力信号量子化回路３－１～３－Ｎは、ＭＡＳＨ型のデルタシグマ変換回路である。デルタシグマ変換回路は、デルタシグマ変調回路とも言う。なお、Ｎは３以上の正の整数とする。 Embodiment 1.
FIG. 1 is a diagram showing a configuration example of a signal generation circuit 1 according to the first embodiment. The signal generation circuit 1 includes a transmission signal generation section 2, input signal quantization circuits 3-1 to 3-N, a signal distribution section 5, an initial value control section 6, and an analog multiplexing circuit 7. The input signal quantization circuits 3-1 to 3-N are MASH type delta-sigma conversion circuits. A delta-sigma conversion circuit is also called a delta-sigma modulation circuit. Note that N is a positive integer of 3 or more.
　入力信号量子化回路３－１は、減算器１２－１と、ループフィルタ１３－１と、量子化器１４－１と、高速シリアル出力回路１６－１と、帰還経路１７－１と、を備える。入力信号量子化回路３－２は、ゲイン部１１－２と、減算器１２－２と、ループフィルタ１３－２と、量子化器１４－２と、結合フィルタ１５－２と、高速シリアル出力回路１６－２と、帰還経路１７－２と、を備える。以降も同様に、入力信号量子化回路３－Ｎは、ゲイン部１１－Ｎと、減算器１２－Ｎと、ループフィルタ１３－Ｎと、量子化器１４－Ｎと、結合フィルタ１５－Ｎと、高速シリアル出力回路１６－Ｎと、帰還経路１７－Ｎと、を備える。なお、入力信号量子化回路３－２～３－Ｎによって、入力信号量子化回路群４を構成している。信号発生回路１において、入力信号量子化回路３－１は１段目の入力信号量子化回路であり、入力信号量子化回路３－２～３－Ｎ、すなわち入力信号量子化回路群４は２段目の入力信号量子化回路である。Ｎは３以上の正の整数のため、２段目の入力信号量子化回路である入力信号量子化回路群４は、２以上の入力信号量子化回路３を有する。 The input signal quantization circuit 3-1 includes a subtracter 12-1, a loop filter 13-1, a quantizer 14-1, a high-speed serial output circuit 16-1, and a feedback path 17-1. . The input signal quantization circuit 3-2 includes a gain section 11-2, a subtracter 12-2, a loop filter 13-2, a quantizer 14-2, a combination filter 15-2, and a high-speed serial output circuit. 16-2, and a return path 17-2. Similarly, the input signal quantization circuit 3-N includes a gain section 11-N, a subtracter 12-N, a loop filter 13-N, a quantizer 14-N, and a combination filter 15-N. , a high-speed serial output circuit 16-N, and a feedback path 17-N. Note that the input signal quantization circuits 3-2 to 3-N constitute an input signal quantization circuit group 4. In the signal generation circuit 1, the input signal quantization circuit 3-1 is the first stage input signal quantization circuit, and the input signal quantization circuits 3-2 to 3-N, that is, the input signal quantization circuit group 4 are This is the input signal quantization circuit in the second stage. Since N is a positive integer of 3 or more, the input signal quantization circuit group 4, which is the second stage input signal quantization circuit, has two or more input signal quantization circuits 3.
　以降の説明において、入力信号量子化回路３－１を第１の入力信号量子化回路と称し、ループフィルタ１３－１を第１のフィルタと称し、量子化器１４－１を第１の量子化器と称し、高速シリアル出力回路１６－１を第１の高速シリアル出力回路と称し、入力信号量子化回路３－１への入力信号を第１の入力信号と称し、入力信号量子化回路３－１からの出力信号を第１の出力信号と称することがある。また、入力信号量子化回路３－２～３－Ｎを第２の入力信号量子化回路と称し、ループフィルタ１３－２～１３－Ｎを第２のフィルタと称し、量子化器１４－２～１４－Ｎを第２の量子化器と称し、高速シリアル出力回路１６－２～１６－Ｎを第２の高速シリアル出力回路と称し、入力信号量子化回路３－２～３－Ｎへの入力信号を第２の入力信号と称し、入力信号量子化回路３－２～３－Ｎからの出力信号を第２の出力信号と称することがある。 In the following description, the input signal quantization circuit 3-1 will be referred to as a first input signal quantization circuit, the loop filter 13-1 will be referred to as a first filter, and the quantizer 14-1 will be referred to as a first quantization circuit. The high-speed serial output circuit 16-1 is referred to as a first high-speed serial output circuit, the input signal to the input signal quantization circuit 3-1 is referred to as a first input signal, and the input signal quantization circuit 3-1 is referred to as a first input signal. The output signal from 1 is sometimes referred to as the first output signal. In addition, the input signal quantization circuits 3-2 to 3-N are referred to as second input signal quantization circuits, the loop filters 13-2 to 13-N are referred to as second filters, and the quantizers 14-2 to 3-N are referred to as second input signal quantization circuits. 14-N is referred to as a second quantizer, and high-speed serial output circuits 16-2 to 16-N are referred to as second high-speed serial output circuits. The signal may be referred to as a second input signal, and the output signals from the input signal quantization circuits 3-2 to 3-N may be referred to as second output signals.
　また、以降の説明において、入力信号量子化回路３－１～３－Ｎを区別しない場合は入力信号量子化回路３と称し、ゲイン部１１－２～１１－Ｎを区別しない場合はゲイン部１１と称し、減算器１２－１～１２－Ｎを区別しない場合は減算器１２と称し、ループフィルタ１３－１～１３－Ｎを区別しない場合はループフィルタ１３と称し、量子化器１４－１～１４－Ｎを区別しない場合は量子化器１４と称し、結合フィルタ１５－２～１５－Ｎを区別しない場合は結合フィルタ１５と称し、高速シリアル出力回路１６－１～１６－Ｎを区別しない場合は高速シリアル出力回路１６と称し、帰還経路１７－１～１７－Ｎを区別しない場合は帰還経路１７と称することがある。すなわち、信号発生回路１は、Ｎ－１個のゲイン部１１と、Ｎ個の減算器１２と、Ｎ個のループフィルタ１３と、Ｎ個の量子化器１４と、Ｎ－１個の結合フィルタ１５と、Ｎ個の高速シリアル出力回路１６と、Ｎ個の帰還経路１７と、を有する。 In the following explanation, when the input signal quantization circuits 3-1 to 3-N are not distinguished, they are referred to as the input signal quantization circuit 3, and when the gain sections 11-2 to 11-N are not distinguished, they are referred to as the input signal quantization circuit 3. When the subtracters 12-1 to 12-N are not distinguished, they are called the subtracter 12, and when the loop filters 13-1 to 13-N are not distinguished, they are called the loop filter 13, and the quantizers 14-1 to 14-N are called the loop filter 13. When the 14-N is not distinguished, it is called the quantizer 14, when the combination filters 15-2 to 15-N are not distinguished, it is called the combination filter 15, and when the high-speed serial output circuits 16-1 to 16-N are not distinguished, it is called the quantizer 14. is referred to as a high-speed serial output circuit 16, and may be referred to as a feedback path 17 if the feedback paths 17-1 to 17-N are not distinguished. That is, the signal generation circuit 1 includes N-1 gain units 11, N subtracters 12, N loop filters 13, N quantizers 14, and N-1 combination filters. 15, N high-speed serial output circuits 16, and N feedback paths 17.
　送信信号生成部２は、送信信号ｘ（ｚ）を生成して入力信号量子化回路３－１に出力する。 The transmission signal generation unit 2 generates a transmission signal x(z) and outputs it to the input signal quantization circuit 3-1.
　入力信号量子化回路３－１において、減算器１２－１は、送信信号ｘ（ｚ）と、量子化器１４－１からの出力信号である帰還経路１７－１からの信号との差分をとって、すなわち、送信信号ｘ（ｚ）から帰還経路１７－１の信号を減算し、ループフィルタ１３－１に出力する。 In the input signal quantization circuit 3-1, the subtracter 12-1 calculates the difference between the transmission signal x(z) and the signal from the feedback path 17-1, which is the output signal from the quantizer 14-1. That is, the signal on the feedback path 17-1 is subtracted from the transmission signal x(z) and output to the loop filter 13-1.
　ループフィルタ１３－１は、一般的には、図２に示すようなＦＩＲ（Finite　Impulse　Response）フィルタおよびＩＩＲ（Infinite　Impulse　Response）フィルタの組み合わせによって構成される。図２は、実施の形態１に係る信号発生回路１のループフィルタ１３の構成例を示す図である。ループフィルタ１３は、ＦＩＲフィルタ１３１と、ＩＩＲフィルタ１３２と、減算器１３３と、を備える。ループフィルタ１３は、ＦＩＲフィルタ１３１によって減算器１２からの出力信号をフィルタリングする。ループフィルタ１３は、減算器１３３によって、ＦＩＲフィルタ１３１からの出力信号とＩＩＲフィルタ１３２からの出力信号との差分をとって出力する。また、ループフィルタ１３は、ループフィルタ１３からの出力信号を分岐した信号を、ＩＩＲフィルタ１３２でフィルタリングする。ループフィルタ１３－１からの出力信号は、量子化器１４－１によって量子化され、高速シリアル出力回路１６－１から出力されるとともに、帰還経路１７－１を経由して減算器１２－１において入力信号との差分をとるために用いられる。 The loop filter 13-1 is generally configured by a combination of an FIR (Finite Impulse Response) filter and an IIR (Infinite Impulse Response) filter as shown in FIG. FIG. 2 is a diagram showing a configuration example of the loop filter 13 of the signal generation circuit 1 according to the first embodiment. The loop filter 13 includes an FIR filter 131, an IIR filter 132, and a subtracter 133. Loop filter 13 filters the output signal from subtracter 12 using FIR filter 131 . The loop filter 13 uses a subtracter 133 to calculate the difference between the output signal from the FIR filter 131 and the output signal from the IIR filter 132 and outputs the difference. Further, the loop filter 13 filters a signal obtained by branching the output signal from the loop filter 13 using an IIR filter 132 . The output signal from the loop filter 13-1 is quantized by the quantizer 14-1, outputted from the high-speed serial output circuit 16-1, and also sent to the subtracter 12-1 via the feedback path 17-1. Used to take the difference from the input signal.
　量子化器１４－１は、ループフィルタ１３－１からの出力信号の大きさに応じた値を出力する。例えば、量子化器１４－１は、ループフィルタ１３－１からの出力信号の値が０以上の場合は１を出力し、ループフィルタ１３－１からの出力信号の値が０未満の場合は－１を出力する。図１では、量子化器１４－１から出力される信号をｙ１（ｚ）として表している。 Quantizer 14-1 outputs a value according to the magnitude of the output signal from loop filter 13-1. For example, the quantizer 14-1 outputs 1 when the value of the output signal from the loop filter 13-1 is 0 or more, and - when the value of the output signal from the loop filter 13-1 is less than 0. Outputs 1. In FIG. 1, the signal output from the quantizer 14-1 is represented as y 1 (z).
　高速シリアル出力回路１６－１は、前段に接続されている量子化器１４－１と同じ量子化ビット数を持つ出力回路を用いて、量子化器１４－１からの出力信号の値に応じた値を出力する。 The high-speed serial output circuit 16-1 uses an output circuit having the same number of quantization bits as the quantizer 14-1 connected to the previous stage, and outputs a signal according to the value of the output signal from the quantizer 14-1. Output the value.
　一般的なＭＡＳＨ型のデルタシグマ変換回路は、１段目のデルタシグマ変換回路の量子化誤差、すなわち量子化器の入力値と出力値との差分を２段目以降のデルタシグマ変換回路によってキャンセルすることで、量子化雑音を低減している。これに対して、本実施の形態の信号発生回路１は、ＭＡＳＨ型のデルタシグマ変換回路である１段目の入力信号量子化回路３－１の量子化誤差を、並列に接続された２段目のＮ－１個のデルタシグマ変換回路である入力信号量子化回路３－２～３－Ｎに分配して出力する。信号発生回路１は、１段目のデルタシグマ変換回路である入力信号量子化回路３－１からの出力信号、および２段目のＮ－１個のデルタシグマ変換回路である入力信号量子化回路３－２～３－Ｎからの出力信号を、ＦＰＧＡ外部のアナログ合波回路７で合成することによって、量子化雑音を低減する。なお、図１に示すように、信号発生回路１において、アナログ合波回路７以外の構成についてはＦＰＧＡによって実装されることを想定しているが、信号発生回路１の構成は図１の例に限定されない。 In a general MASH type delta-sigma conversion circuit, the quantization error of the first-stage delta-sigma conversion circuit, that is, the difference between the input value and the output value of the quantizer, is canceled by the second-stage delta-sigma conversion circuit and subsequent stages. This reduces quantization noise. In contrast, the signal generation circuit 1 of the present embodiment converts the quantization error of the first stage input signal quantization circuit 3-1, which is a MASH type delta-sigma conversion circuit, into two stages connected in parallel. The signal is distributed to input signal quantization circuits 3-2 to 3-N, which are N-1 delta-sigma conversion circuits, and outputted. The signal generation circuit 1 receives an output signal from an input signal quantization circuit 3-1, which is a delta-sigma conversion circuit in the first stage, and an input signal quantization circuit, which is N-1 delta-sigma conversion circuits in the second stage. By combining the output signals from 3-2 to 3-N with an analog multiplexing circuit 7 outside the FPGA, quantization noise is reduced. As shown in FIG. 1, in the signal generation circuit 1, the configuration other than the analog multiplexing circuit 7 is assumed to be implemented by FPGA, but the configuration of the signal generation circuit 1 is similar to the example in FIG. Not limited.
　信号分配部５は、減算器５１を備える。減算器５１は、入力信号量子化回路３－１のループフィルタ１３－１からの出力信号と、入力信号量子化回路３－１の量子化器１４－１からの出力信号である帰還経路１７－１からの信号との差分をとる、すなわちループフィルタ１３－１の出力信号から帰還経路１７－１の信号を減算する。信号分配部５は、減算器５１で得られた差分を、１段目の入力信号量子化回路３－１の量子化誤差として入力信号量子化回路３－２～３－Ｎに分配する。このように、信号分配部５は、量子化器１４－１への入力信号と量子化器１４－１からの出力信号との差分を第２の入力信号として入力信号量子化回路３－２～３－Ｎへ分配する。 The signal distribution section 5 includes a subtracter 51. The subtracter 51 connects the output signal from the loop filter 13-1 of the input signal quantization circuit 3-1 and the feedback path 17- which is the output signal from the quantizer 14-1 of the input signal quantization circuit 3-1. 1, that is, the signal on the feedback path 17-1 is subtracted from the output signal of the loop filter 13-1. The signal distribution unit 5 distributes the difference obtained by the subtracter 51 to the input signal quantization circuits 3-2 to 3-N as a quantization error of the first stage input signal quantization circuit 3-1. In this way, the signal distribution unit 5 uses the difference between the input signal to the quantizer 14-1 and the output signal from the quantizer 14-1 as a second input signal to the input signal quantization circuits 3-2 to 3-2. 3-Distribute to N.
　ｎ番目のデルタシグマ変換回路である入力信号量子化回路３－ｎにおいて、ゲイン部１１－ｎは、分配された１段目の入力信号量子化回路３－１の量子化誤差に対してゲイン＃ｎを乗算する。なお、ｎは２～Ｎの正の整数とする。 In the input signal quantization circuit 3-n, which is the n-th delta-sigma conversion circuit, the gain section 11-n calculates a gain # for the quantization error of the distributed first-stage input signal quantization circuit 3-1. Multiply by n. Note that n is a positive integer from 2 to N.
　減算器１２－ｎは、ゲイン部１１－ｎからの出力信号と、量子化器１４－ｎからの出力信号である帰還経路１７－ｎからの信号との差分をとって、すなわち、ゲイン部１１－ｎからの出力信号から帰還経路１７－ｎの信号を減算し、ループフィルタ１３－ｎに出力する。 The subtracter 12-n calculates the difference between the output signal from the gain section 11-n and the signal from the feedback path 17-n, which is the output signal from the quantizer 14-n. The signal on the feedback path 17-n is subtracted from the output signal from -n, and the result is output to the loop filter 13-n.
　ループフィルタ１３－ｎの構成は、前述のループフィルタ１３－１の構成と同様である。ループフィルタ１３－ｎからの出力信号は、量子化器１４－ｎによって量子化され、結合フィルタ１５－ｎを経由して高速シリアル出力回路１６－ｎから出力されるとともに、帰還経路１７－ｎを経由して減算器１２－ｎにおいてゲイン部１１－ｎからの出力信号との差分をとるために用いられる。 The configuration of the loop filter 13-n is similar to the configuration of the loop filter 13-1 described above. The output signal from the loop filter 13-n is quantized by a quantizer 14-n, passed through a combination filter 15-n, and outputted from a high-speed serial output circuit 16-n, as well as a feedback path 17-n. The subtracter 12-n uses the subtracter 12-n to calculate the difference between the signal and the output signal from the gain section 11-n.
　量子化器１４－ｎは、ループフィルタ１３－ｎからの出力信号の大きさに応じた値を出力する。例えば、量子化器１４－ｎは、ループフィルタ１３－ｎからの出力信号の値が０以上の場合は１を出力し、ループフィルタ１３－ｎからの出力信号の値が０未満の場合は－１を出力する。 The quantizer 14-n outputs a value according to the magnitude of the output signal from the loop filter 13-n. For example, the quantizer 14-n outputs 1 when the value of the output signal from the loop filter 13-n is 0 or more, and - when the value of the output signal from the loop filter 13-n is less than 0. Outputs 1.
　結合フィルタ１５－ｎは、１段目の入力信号量子化回路３－１の量子化誤差をキャンセルするために設定される固有のフィルタであり、ＦＩＲフィルタ、またはＩＩＲフィルタ、またはＦＩＲフィルタおよびＩＩＲフィルタの組み合わせとして実装される。結合フィルタ１５－ｎは、量子化器１４－ｎからの出力信号に対してフィルタ処理を行い、高速シリアル出力回路１６－ｎに出力する。図１では、結合フィルタ１５－２～１５－Ｎから出力される信号をｙ２（ｚ）～ｙＮ（ｚ）として表している。 The combination filter 15-n is a unique filter set to cancel the quantization error of the first-stage input signal quantization circuit 3-1, and is an FIR filter, an IIR filter, or an FIR filter and an IIR filter. Implemented as a combination of The combination filter 15-n performs filter processing on the output signal from the quantizer 14-n and outputs it to the high-speed serial output circuit 16-n. In FIG. 1, the signals output from the coupling filters 15-2 to 15-N are expressed as y 2 (z) to y N (z).
　高速シリアル出力回路１６－ｎは、結合フィルタ１５－ｎの前段に接続されている量子化器１４－ｎと同じ量子化ビット数を持つ出力回路を用いる。 The high-speed serial output circuit 16-n uses an output circuit having the same number of quantization bits as the quantizer 14-n connected before the combination filter 15-n.
　なお、ループフィルタ１３－１～１３－Ｎおよび結合フィルタ１５－２～１５－Ｎに設定されるフィルタ特性の組み合わせの代表例としては、式（１）および式（２）の組み合わせが存在する。式（１）はループフィルタ１３－１～１３－Ｎのフィルタ特性に対応するものであり、式（２）は結合フィルタ１５－２～１５－Ｎのフィルタ特性に対応するものである。なお、ｚ－１は、一般的な遅延素子などで使用される係数である。 Note that, as a typical example of the combination of filter characteristics set for the loop filters 13-1 to 13-N and the combined filters 15-2 to 15-N, there is a combination of equations (1) and (2). Equation (1) corresponds to the filter characteristics of the loop filters 13-1 to 13-N, and Equation (2) corresponds to the filter characteristics of the combined filters 15-2 to 15-N. Note that z −1 is a coefficient used in general delay elements.
　ｚ－１／（１－ｚ－１）　…（１） z -1 /(1-z -1 )...(1)
　１－ｚ－１　…（２） 1-z -1 ...(2)
　このように、２以上の入力信号量子化回路３－２～３－Ｎが有するループフィルタ１３－２～１３－Ｎの初期値を、ループフィルタ１３－２～１３－Ｎごとに異なる値とする。 In this way, the initial values of the loop filters 13-2 to 13-N included in two or more input signal quantization circuits 3-2 to 3-N are set to different values for each of the loop filters 13-2 to 13-N. .
　また、ゲイン部１１－２～１１－Ｎに設定されるゲインについては、ゲイン部１１－２～１１－Ｎに設定されるゲイン、すなわち係数の合計値が１となるような値として、全てを１／（Ｎ－１）に設定することが考えられる。このように、２以上の入力信号量子化回路３－２～３－Ｎは、各々が、入力信号に異なる係数を乗算し、量子化器１４の出力信号と係数を乗算後の入力信号との差分をループフィルタ１３への入力信号とする。また、２以上の入力信号量子化回路３－２～３－Ｎで入力信号に乗算される２以上の係数の総和を１とする。 Also, regarding the gains set in the gain sections 11-2 to 11-N, all the gains set in the gain sections 11-2 to 11-N are set to values such that the total value of the coefficients becomes 1. It is conceivable to set it to 1/(N-1). In this way, the two or more input signal quantization circuits 3-2 to 3-N each multiply the input signal by a different coefficient, and compare the output signal of the quantizer 14 with the input signal after multiplication by the coefficient. The difference is used as an input signal to the loop filter 13. Further, the sum of two or more coefficients multiplied by the input signal by two or more input signal quantization circuits 3-2 to 3-N is set to 1.
　また、量子化器１４－１～１４－Ｎとして１ｂｉｔ量子化器を用い、ループフィルタ１３－１～１３－Ｎおよび結合フィルタ１５－２～１５－Ｎのフィルタ特性の組み合わせとして式（１）および式（２）の関係を用いた場合、結合フィルタ１５－２～１５－Ｎの出力は、－２，０，２の３値をとる。このため、高速シリアル出力回路１６－２～１６－Ｎは、３値の出力が可能な高速シリアル出力回路を用いる必要がある。３値の出力が可能な高速シリアル出力回路１６－２～１６－Ｎとしては、図３に示すような構成が考えられる。図３は、実施の形態１に係る信号発生回路１の高速シリアル出力回路１６の構成例を示す図である。高速シリアル出力回路１６は、エンコーダ１６１と、高速シリアル出力回路１６２，１６３と、アナログ合波回路１６４と、を備える。 In addition, a 1-bit quantizer is used as the quantizers 14-1 to 14-N, and the combination of filter characteristics of the loop filters 13-1 to 13-N and the combined filters 15-2 to 15-N is expressed by formula (1) and When using the relationship in equation (2), the outputs of the coupling filters 15-2 to 15-N take three values -2, 0, and 2. Therefore, the high-speed serial output circuits 16-2 to 16-N need to be high-speed serial output circuits capable of outputting three values. As the high-speed serial output circuits 16-2 to 16-N capable of outputting three values, a configuration as shown in FIG. 3 can be considered. FIG. 3 is a diagram showing a configuration example of the high-speed serial output circuit 16 of the signal generation circuit 1 according to the first embodiment. The high-speed serial output circuit 16 includes an encoder 161, high-speed serial output circuits 162 and 163, and an analog multiplexing circuit 164.
　高速シリアル出力回路１６は、２つの高速シリアル出力回路１６２，１６３の出力信号をアナログ合波回路１６４で合成することによって、３値の出力を実現できる。この場合、エンコーダ１６１は、入力値が２の場合、高速シリアル出力回路１６２，１６３から同時に１が出力され、入力値が－２の場合、高速シリアル出力回路１６２，１６３から同時に－１が出力されるように制御する。また、エンコーダ１６１は、入力値が０の場合、高速シリアル出力回路１６２，１６３から逆の値、すなわち高速シリアル出力回路１６２から１が出力され、かつ高速シリアル出力回路１６３から－１が出力され、または高速シリアル出力回路１６２から－１が出力され、かつ高速シリアル出力回路１６３から１が出力されるように制御する。このように、高速シリアル出力回路１６－１は、２以上の高速シリアル出力回路を用いることで多値出力を可能とする。また、高速シリアル出力回路１６－２～１６－Ｎは、各々が、２以上の高速シリアル出力回路を用いることで多値出力を可能とする。 The high-speed serial output circuit 16 can realize ternary output by combining the output signals of the two high-speed serial output circuits 162 and 163 with the analog multiplexing circuit 164. In this case, when the input value of the encoder 161 is 2, 1 is simultaneously output from the high-speed serial output circuits 162 and 163, and when the input value is -2, the high-speed serial output circuits 162 and 163 simultaneously output -1. control so that Furthermore, when the input value is 0, the encoder 161 outputs the opposite value from the high-speed serial output circuits 162 and 163, that is, 1 is output from the high-speed serial output circuit 162, and -1 is output from the high-speed serial output circuit 163, Alternatively, control is performed so that -1 is output from the high-speed serial output circuit 162 and 1 is output from the high-speed serial output circuit 163. In this way, the high-speed serial output circuit 16-1 enables multi-value output by using two or more high-speed serial output circuits. Furthermore, each of the high-speed serial output circuits 16-2 to 16-N is capable of multi-value output by using two or more high-speed serial output circuits.
　アナログ合波回路７は、高速シリアル出力回路１６－１～１６－Ｎから出力された信号を、アナログ的に合波して出力する。図４は、実施の形態１に係る信号発生回路１のアナログ合波回路７の構成例を示す図である。アナログ合波回路７は、電力分配回路７１～７７を備える。電力分配回路７１～７７は、例えば、抵抗式のパワーコンバイナ、ウィルキンソンディバイダなどの電力を一定の比率で合成可能な回路素子である。なお、アナログ合波回路７は、図３に示す３値の出力の高速シリアル出力回路１６に含まれるアナログ合波回路１６４の役割も含まれるように構成されてもよい。 The analog multiplexing circuit 7 multiplexes the signals output from the high-speed serial output circuits 16-1 to 16-N in an analog manner and outputs the multiplexed signals. FIG. 4 is a diagram showing a configuration example of the analog multiplexing circuit 7 of the signal generation circuit 1 according to the first embodiment. The analog multiplexing circuit 7 includes power distribution circuits 71 to 77. The power distribution circuits 71 to 77 are, for example, circuit elements such as resistive power combiners and Wilkinson dividers that can combine power at a fixed ratio. Note that the analog multiplexing circuit 7 may be configured to also play the role of the analog multiplexing circuit 164 included in the high-speed serial output circuit 16 with ternary output shown in FIG.
　図５は、実施の形態１に係る信号発生回路１の初期値制御部６の動作を示すフローチャートである。初期値制御部６は、信号発生回路１が動作を開始するタイミングで、ループフィルタ１３－２～１３－Ｎ内部のＦＩＲフィルタ１３１およびＩＩＲフィルタ１３２の初期値をランダムに設定する（ステップＳ１０１）。初期値制御部６による設定後、信号発生回路１は、送信信号生成部２から送信信号ｘ（ｚ）を出力し、送信信号ｘ（ｚ）に対する変換処理を開始する。 FIG. 5 is a flowchart showing the operation of the initial value control section 6 of the signal generation circuit 1 according to the first embodiment. The initial value control unit 6 randomly sets the initial values of the FIR filter 131 and the IIR filter 132 inside the loop filters 13-2 to 13-N at the timing when the signal generation circuit 1 starts operating (step S101). After the setting by the initial value control unit 6, the signal generation circuit 1 outputs the transmission signal x(z) from the transmission signal generation unit 2, and starts a conversion process for the transmission signal x(z).
　図６は、実施の形態１に係る信号発生回路１の動作を示すフローチャートである。信号発生回路１において、１段目の入力信号量子化回路３－１は、送信信号生成部２から送信信号ｘ（ｚ）が入力されると、減算器１２－１、ループフィルタ１３－１、量子化器１４－１、および高速シリアル出力回路１６－１によって第１の量子化処理を行い（ステップＳ２０１）、高速シリアル出力回路１６－１からの出力信号をアナログ合波回路７に出力するとともに、量子化器１４－１への入力信号および量子化器１４－１からの出力信号を信号分配部５に出力する。信号分配部５は、量子化器１４－１への入力信号と量子化器１４－１からの出力信号との差分を演算する（ステップＳ２０２）。信号分配部５は、演算により求めた差分を入力信号として、２段目の入力信号量子化回路３－２～３－Ｎへ分配する（ステップＳ２０３）。２段目の入力信号量子化回路３－２～３－Ｎは、各々、信号分配部５から入力信号が入力されると、ゲイン部１１、減算器１２、ループフィルタ１３、量子化器１４、結合フィルタ１５、および高速シリアル出力回路１６によって第２の量子化処理を行い（ステップＳ２０４）、高速シリアル出力回路１６からの出力信号をアナログ合波回路７に出力する。アナログ合波回路７は、入力信号量子化回路３－１～３－Ｎからの出力信号を合成して（ステップＳ２０５）、出力する。 FIG. 6 is a flowchart showing the operation of the signal generation circuit 1 according to the first embodiment. In the signal generation circuit 1, when the first stage input signal quantization circuit 3-1 receives the transmission signal x(z) from the transmission signal generation section 2, the first stage input signal quantization circuit 3-1 performs a subtracter 12-1, a loop filter 13-1, A first quantization process is performed by the quantizer 14-1 and the high-speed serial output circuit 16-1 (step S201), and the output signal from the high-speed serial output circuit 16-1 is output to the analog multiplexing circuit 7. , the input signal to the quantizer 14-1 and the output signal from the quantizer 14-1 are output to the signal distribution section 5. The signal distribution unit 5 calculates the difference between the input signal to the quantizer 14-1 and the output signal from the quantizer 14-1 (step S202). The signal distribution unit 5 distributes the calculated difference as an input signal to the second-stage input signal quantization circuits 3-2 to 3-N (step S203). When the input signal is input from the signal distribution section 5, the second-stage input signal quantization circuits 3-2 to 3-N each include a gain section 11, a subtracter 12, a loop filter 13, a quantizer 14, A second quantization process is performed by the combination filter 15 and the high-speed serial output circuit 16 (step S204), and the output signal from the high-speed serial output circuit 16 is output to the analog multiplexing circuit 7. The analog multiplexing circuit 7 synthesizes the output signals from the input signal quantization circuits 3-1 to 3-N (step S205) and outputs the synthesized signal.
　このように、１段目の誤差フィードバック型の入力信号量子化回路３－１は、量子化器１４－１の出力信号と入力信号量子化回路３－１への第１の入力信号との差分をループフィルタ１３－１への入力信号とし、ループフィルタ１３－１からの出力信号を量子化器１４－１への入力信号とする。入力信号量子化回路３－１は高速シリアル出力回路１６－１を用いて出力信号を出力する。また、２段目の誤差フィードバック型の２以上の入力信号量子化回路３－２～３－Ｎは、各々が、量子化器１４の出力信号と入力信号量子化回路３への入力信号との差分をループフィルタ１３への入力信号とし、ループフィルタ１３からの出力信号を量子化器１４への入力信号とする。２以上の入力信号量子化回路３－２～３－Ｎは、各々が、高速シリアル出力回路１６を用いて出力信号を出力する。信号発生回路１において、アナログ合波回路７は、入力信号量子化回路３－１からの出力信号と２以上の入力信号量子化回路３－２～３－Ｎからの出力信号とを合成して出力する。 In this way, the first stage error feedback type input signal quantization circuit 3-1 calculates the difference between the output signal of the quantizer 14-1 and the first input signal to the input signal quantization circuit 3-1. is an input signal to the loop filter 13-1, and an output signal from the loop filter 13-1 is an input signal to the quantizer 14-1. The input signal quantization circuit 3-1 outputs an output signal using the high-speed serial output circuit 16-1. Furthermore, the two or more second-stage error feedback type input signal quantization circuits 3-2 to 3-N each input the output signal of the quantizer 14 and the input signal to the input signal quantization circuit 3. The difference is used as an input signal to the loop filter 13, and the output signal from the loop filter 13 is used as an input signal to the quantizer 14. Each of the two or more input signal quantization circuits 3-2 to 3-N outputs an output signal using the high-speed serial output circuit 16. In the signal generation circuit 1, the analog multiplexing circuit 7 combines the output signal from the input signal quantization circuit 3-1 and the output signals from two or more input signal quantization circuits 3-2 to 3-N. Output.
　つづいて、信号発生回路１のハードウェア構成について説明する。信号発生回路１において、アナログ合波回路７は、図４に示すようなアナログ回路によって実現される。高速シリアル出力回路１６－１～１６－Ｎは、図３に示すような回路構成であり、前述のように、ＦＰＧＡなどに内蔵される構成である。信号発生回路１において、その他の構成は、処理回路により実現される。処理回路は、メモリに格納されるプログラムを実行するプロセッサおよびメモリであってもよいし、専用のハードウェアであってもよい。処理回路は制御回路とも呼ばれる。 Next, the hardware configuration of the signal generation circuit 1 will be explained. In the signal generation circuit 1, the analog multiplexing circuit 7 is realized by an analog circuit as shown in FIG. The high-speed serial output circuits 16-1 to 16-N have a circuit configuration as shown in FIG. 3, and as described above, are built in an FPGA or the like. In the signal generation circuit 1, other configurations are realized by a processing circuit. The processing circuit may be a processor and memory that executes a program stored in memory, or may be dedicated hardware. The processing circuit is also called a control circuit.
　図７は、実施の形態１に係る信号発生回路１を実現する処理回路をプロセッサ９１およびメモリ９２で実現する場合の処理回路９０の構成例を示す図である。なお、図７は、高速シリアル出力回路１６－１～１６－Ｎ、およびアナログ合波回路７を含んでいる。図７に示す処理回路９０は制御回路であり、プロセッサ９１およびメモリ９２を備える。処理回路９０がプロセッサ９１およびメモリ９２で構成される場合、処理回路９０の各機能は、ソフトウェア、ファームウェア、またはソフトウェアとファームウェアとの組み合わせにより実現される。ソフトウェアまたはファームウェアはプログラムとして記述され、メモリ９２に格納される。処理回路９０では、メモリ９２に記憶されたプログラムをプロセッサ９１が読み出して実行することにより、各機能を実現する。すなわち、処理回路９０は、信号発生回路１の処理が結果的に実行されることになるプログラムを格納するためのメモリ９２を備える。このプログラムは、処理回路９０により実現される各機能を信号発生回路１に実行させるためのプログラムであるともいえる。このプログラムは、プログラムが記憶された記憶媒体により提供されてもよいし、通信媒体など他の手段により提供されてもよい。 FIG. 7 is a diagram illustrating a configuration example of the processing circuit 90 when the processing circuit realizing the signal generation circuit 1 according to the first embodiment is implemented by the processor 91 and the memory 92. Note that FIG. 7 includes high-speed serial output circuits 16-1 to 16-N and an analog multiplexing circuit 7. A processing circuit 90 shown in FIG. 7 is a control circuit, and includes a processor 91 and a memory 92. When the processing circuit 90 includes a processor 91 and a memory 92, each function of the processing circuit 90 is realized by software, firmware, or a combination of software and firmware. Software or firmware is written as a program and stored in memory 92. In the processing circuit 90, each function is realized by a processor 91 reading and executing a program stored in a memory 92. That is, the processing circuit 90 includes a memory 92 for storing a program by which the processing of the signal generating circuit 1 is executed as a result. This program can also be said to be a program for causing the signal generation circuit 1 to execute each function realized by the processing circuit 90. This program may be provided by a storage medium in which the program is stored, or may be provided by other means such as a communication medium.
　上記プログラムは、１段目の誤差フィードバック型の入力信号量子化回路３－１が、量子化器１４－１の出力信号と入力信号量子化回路３－１への入力信号との差分をループフィルタ１３－１への入力信号とし、ループフィルタ１３－１からの出力信号を量子化器１４－１への入力信号とする第１のステップと、信号分配部５が、量子化器１４－１への入力信号と量子化器１４－２からの出力信号との差分を第２の入力信号として２以上の入力信号量子化回路３－２～３－Ｎへ分配する第２のステップと、２段目の誤差フィードバック型の２以上の入力信号量子化回路３－２～３－Ｎが、各々、量子化器１４の出力信号と入力信号量子化回路３への第２の入力信号との差分をループフィルタ１３への入力信号とし、ループフィルタ１３からの出力信号を量子化器１４への入力信号とする第３のステップと、を信号発生回路１に実行さるプログラムであるとも言える。 In the above program, the first stage error feedback type input signal quantization circuit 3-1 converts the difference between the output signal of the quantizer 14-1 and the input signal to the input signal quantization circuit 3-1 into a loop filter. A first step in which the output signal from the loop filter 13-1 is input to the quantizer 14-1, and the signal distribution unit 5 inputs the output signal to the quantizer 14-1. a second step of distributing the difference between the input signal of and the output signal from the quantizer 14-2 as a second input signal to two or more input signal quantization circuits 3-2 to 3-N; Two or more input signal quantization circuits 3-2 to 3-N of the eye error feedback type each calculate the difference between the output signal of the quantizer 14 and the second input signal to the input signal quantization circuit 3. It can also be said that this is a program executed by the signal generation circuit 1, including a third step in which the input signal is input to the loop filter 13 and the output signal from the loop filter 13 is input to the quantizer 14.
　ここで、プロセッサ９１は、例えば、ＣＰＵ（Central　Processing　Unit）、処理装置、演算装置、マイクロプロセッサ、マイクロコンピュータ、またはＤＳＰ（Digital　Signal　Processor）などである。また、メモリ９２は、例えば、ＲＡＭ（Random　Access　Memory）、ＲＯＭ（Read　Only　Memory）、フラッシュメモリ、ＥＰＲＯＭ（Erasable　Programmable　ＲＯＭ）、ＥＥＰＲＯＭ（登録商標）（Electrically　ＥＰＲＯＭ）などの、不揮発性または揮発性の半導体メモリ、磁気ディスク、フレキシブルディスク、光ディスク、コンパクトディスク、ミニディスク、またはＤＶＤ（Digital　Versatile　Disc）などが該当する。 Here, the processor 91 is, for example, a CPU (Central Processing Unit), a processing device, an arithmetic device, a microprocessor, a microcomputer, or a DSP (Digital Signal Processor). The memory 92 may be a nonvolatile or volatile memory such as RAM (Random Access Memory), ROM (Read Only Memory), flash memory, EPROM (Erasable Programmable ROM), or EEPROM (registered trademark) (Electrically EPROM). This includes semiconductor memory, magnetic disks, flexible disks, optical disks, compact disks, mini disks, and DVDs (Digital Versatile Discs).
　図８は、実施の形態１に係る信号発生回路１を実現する処理回路を専用のハードウェアで構成する場合の処理回路９３の例を示す図である。なお、図８は、図７と同様、高速シリアル出力回路１６－１～１６－Ｎ、およびアナログ合波回路７を含んでいる。図８に示す処理回路９３は、例えば、単一回路、複合回路、プログラム化したプロセッサ、並列プログラム化したプロセッサ、ＡＳＩＣ（Application　Specific　Integrated　Circuit）、ＦＰＧＡ、またはこれらを組み合わせたものが該当する。処理回路については、一部を専用のハードウェアで実現し、一部をソフトウェアまたはファームウェアで実現するようにしてもよい。このように、処理回路は、専用のハードウェア、ソフトウェア、ファームウェア、またはこれらの組み合わせによって、上述の各機能を実現することができる。 FIG. 8 is a diagram showing an example of the processing circuit 93 in the case where the processing circuit realizing the signal generation circuit 1 according to the first embodiment is configured with dedicated hardware. Note that, like FIG. 7, FIG. 8 includes high-speed serial output circuits 16-1 to 16-N and an analog multiplexing circuit 7. The processing circuit 93 shown in FIG. 8 is, for example, a single circuit, a composite circuit, a programmed processor, a parallel programmed processor, an ASIC (Application Specific Integrated Circuit), an FPGA, or a combination thereof. Regarding the processing circuit, a part may be realized by dedicated hardware, and a part may be realized by software or firmware. In this way, the processing circuit can implement each of the above-mentioned functions using dedicated hardware, software, firmware, or a combination thereof.
　以上説明したように、本実施の形態によれば、信号発生回路１は、２段ＭＡＳＨ型のデルタシグマ変換回路において、１段目を入力信号量子化回路３－１で構成し、２段目を入力信号量子化回路３－２～３－Ｎで並列にして構成し、２段目の入力信号量子化回路３－２～３－Ｎに異なる初期値を与えることで異なる系列のデルタシグマ信号出力を得て、アナログ合波回路７で入力信号量子化回路３－１～３－Ｎからの出力信号を合成することとした。これにより、信号発生回路１は、３段以上のＭＡＳＨ型デルタシグマ変換回路のように出力の多値数を増やすことなく、単純な２段ＭＡＳＨ型デルタシグマ変換回路よりも量子化雑音を抑制することができる。また、信号発生回路１は、２段目のみを並列化するため、特許文献１に記載の手法と比較して、異なる系列のデルタシグマ出力を合成するために必要な回路規模を低減することができる。信号発生回路１は、多値数および回路規模の増加を抑制しつつ、デルタシグマ信号出力の量子化雑音および位相雑音による信号劣化を抑制することができる。 As described above, according to the present embodiment, the signal generation circuit 1 is a two-stage MASH type delta-sigma conversion circuit, in which the first stage is composed of the input signal quantization circuit 3-1, and the second stage is composed of the input signal quantization circuit 3-1. are configured in parallel with input signal quantization circuits 3-2 to 3-N, and by giving different initial values to the second-stage input signal quantization circuits 3-2 to 3-N, different series of delta-sigma signals can be generated. After obtaining the outputs, the analog multiplexing circuit 7 synthesizes the output signals from the input signal quantization circuits 3-1 to 3-N. As a result, the signal generation circuit 1 suppresses quantization noise more than a simple two-stage MASH-type delta-sigma conversion circuit without increasing the number of output values unlike a three-stage or more-stage MASH-type delta-sigma conversion circuit. be able to. Furthermore, since the signal generation circuit 1 parallelizes only the second stage, it is possible to reduce the circuit scale required to synthesize delta-sigma outputs of different series compared to the method described in Patent Document 1. can. The signal generation circuit 1 can suppress signal deterioration due to quantization noise and phase noise of the delta-sigma signal output while suppressing an increase in the number of multilevel values and circuit scale.
実施の形態２．
　実施の形態１では、信号発生回路１は、初期値制御部６を用いてループフィルタ１３－２～１３－Ｎの内部のＦＩＲフィルタ１３１およびＩＩＲフィルタ１３２に初期値を設定していた。実施の形態２では、信号発生回路が初期値制御部６を備えない構成について説明する。 Embodiment 2.
In the first embodiment, the signal generation circuit 1 uses the initial value control unit 6 to set initial values to the FIR filter 131 and the IIR filter 132 inside the loop filters 13-2 to 13-N. In the second embodiment, a configuration in which the signal generation circuit does not include the initial value control section 6 will be described.
　図９は、実施の形態２に係る信号発生回路１ａの構成例を示す図である。信号発生回路１ａは、図１に示す信号発生回路１から初期値制御部６を削除したものである。実施の形態２において、信号発生回路１ａは、ゲイン部１１－２～１１－Ｎに対して予め式（３）に示すようなランダムな値が設定されているものとする。 FIG. 9 is a diagram showing a configuration example of the signal generation circuit 1a according to the second embodiment. The signal generation circuit 1a is obtained by removing the initial value control section 6 from the signal generation circuit 1 shown in FIG. In the second embodiment, it is assumed that in the signal generating circuit 1a, random values as shown in equation (3) are set in advance for the gain sections 11-2 to 11-N.
　ΣＧｉ＝１．０　…（３） ΣG i =1.0...(3)
　なお、式（３）において、Ｇｉはｉ番目のゲインの値を表す。また、式（３）では記載を省略しているが、本来「Σ」の上下に示されるｉの範囲はｉ＝２～Ｎとなる。 Note that in equation (3), G i represents the i-th gain value. Further, although the description is omitted in equation (3), the range of i shown above and below "Σ" is originally i=2 to N.
　入力信号量子化回路３－２～３－Ｎは、前述のようにデルタシグマ変換回路であり、基となる信号波形が同じであっても振幅が異なる場合、相関が低い異なる出力信号列を出力する特性を有する。そのため、信号発生回路１ａは、このような入力信号量子化回路３－２～３－Ｎの特性を利用することで、初期値制御部６を不要としつつ、実施の形態１の信号発生回路１において初期値をランダムに設定した場合の効果と同様の効果を得ることができる。 As mentioned above, the input signal quantization circuits 3-2 to 3-N are delta-sigma conversion circuits, and when the base signal waveforms are the same but have different amplitudes, they output different output signal sequences with low correlation. It has the characteristics of Therefore, by utilizing the characteristics of the input signal quantization circuits 3-2 to 3-N, the signal generation circuit 1a eliminates the need for the initial value control section 6, and the signal generation circuit 1 of the first embodiment. The same effect as that obtained when the initial value is randomly set can be obtained.
　以上の実施の形態に示した構成は、一例を示すものであり、別の公知の技術と組み合わせることも可能であるし、実施の形態同士を組み合わせることも可能であるし、要旨を逸脱しない範囲で、構成の一部を省略、変更することも可能である。 The configurations shown in the embodiments above are merely examples, and can be combined with other known techniques, or can be combined with other embodiments, within the scope of the gist. It is also possible to omit or change part of the configuration.
　１，１ａ　信号発生回路、２　送信信号生成部、３－１～３－Ｎ　入力信号量子化回路、４　入力信号量子化回路群、５　信号分配部、６　初期値制御部、７，１６４　アナログ合波回路、１１－２～１１－Ｎ　ゲイン部、１２－１～１２－Ｎ，５１，１３３　減算器、１３－１～１３－Ｎ　ループフィルタ、１４－１～１４－Ｎ　量子化器、１５－２～１５－Ｎ　結合フィルタ、１６－１～１６－Ｎ，１６２，１６３　高速シリアル出力回路、１７－１～１７－Ｎ　帰還経路、７１～７７　電力分配回路、１３１　ＦＩＲフィルタ、１３２　ＩＩＲフィルタ、１６１　エンコーダ。 1, 1a Signal generation circuit, 2 Transmission signal generation section, 3-1 to 3-N Input signal quantization circuit, 4 Input signal quantization circuit group, 5 Signal distribution section, 6 Initial value control section, 7,164 Analog signal generator Wave circuit, 11-2 to 11-N gain section, 12-1 to 12-N, 51, 133 subtracter, 13-1 to 13-N loop filter, 14-1 to 14-N quantizer, 15- 2 to 15-N coupling filter, 16-1 to 16-N, 162, 163 high-speed serial output circuit, 17-1 to 17-N feedback path, 71 to 77 power distribution circuit, 131 FIR filter, 132 IIR filter, 161 encoder.

Claims (9)

  1. 　第１の量子化器の出力信号と第１の入力信号量子化回路への第１の入力信号との差分を第１のフィルタへの入力信号とし、前記第１のフィルタからの出力信号を前記第１の量子化器への入力信号とする１段目の誤差フィードバック型の前記第１の入力信号量子化回路と、
    　前記第１の量子化器への入力信号と前記第１の量子化器からの出力信号との差分を第２の入力信号として２以上の第２の入力信号量子化回路へ分配する信号分配部と、
    　各々が、第２の量子化器の出力信号と前記第２の入力信号量子化回路への前記第２の入力信号との差分を第２のフィルタへの入力信号とし、前記第２のフィルタからの出力信号を前記第２の量子化器への入力信号とする２段目の誤差フィードバック型の２以上の前記第２の入力信号量子化回路と、
    　を備え、
    　前記第１の入力信号量子化回路からの第１の出力信号と２以上の前記第２の入力信号量子化回路からの第２の出力信号とを合成して出力することを特徴とする信号発生回路。     The difference between the output signal of the first quantizer and the first input signal to the first input signal quantization circuit is used as the input signal to the first filter, and the output signal from the first filter is used as the input signal to the first input signal quantization circuit. the first stage error feedback type first input signal quantization circuit that inputs the input signal to the first quantizer;
    a signal distribution unit that distributes the difference between the input signal to the first quantizer and the output signal from the first quantizer as a second input signal to two or more second input signal quantization circuits; and,
    each of which uses a difference between an output signal of a second quantizer and the second input signal to the second input signal quantization circuit as an input signal to a second filter; two or more of the second input signal quantization circuits of a second stage error feedback type that input the output signal of the input signal to the second quantizer;
    Equipped with
    Signal generation characterized in that a first output signal from the first input signal quantization circuit and a second output signal from two or more of the second input signal quantization circuits are combined and output. circuit.
  2. 　前記第１の入力信号量子化回路からの前記第１の出力信号と２以上の前記第２の入力信号量子化回路からの前記第２の出力信号とを合成して出力するアナログ合波回路、
    　を備えることを特徴とする請求項１に記載の信号発生回路。     an analog multiplexing circuit that combines and outputs the first output signal from the first input signal quantization circuit and the second output signal from two or more of the second input signal quantization circuits;
    2. The signal generating circuit according to claim 1, comprising: a.
  3. 　前記第１の入力信号量子化回路は、第１の高速シリアル出力回路を用いて前記第１の出力信号を出力し、
    　２以上の前記第２の入力信号量子化回路は、各々が、第２の高速シリアル出力回路を用いて前記第２の出力信号を出力する、
    　ことを特徴とする請求項１または２に記載の信号発生回路。     The first input signal quantization circuit outputs the first output signal using a first high-speed serial output circuit,
    Each of the two or more second input signal quantization circuits outputs the second output signal using a second high-speed serial output circuit.
    The signal generating circuit according to claim 1 or 2, characterized in that:
  4. 　前記第１の高速シリアル出力回路は、２以上の高速シリアル出力回路を用いることで多値出力を可能とし、
    　前記第２の高速シリアル出力回路は、各々が、２以上の高速シリアル出力回路を用いることで多値出力を可能とする、
    　ことを特徴とする請求項３に記載の信号発生回路。     The first high-speed serial output circuit enables multi-value output by using two or more high-speed serial output circuits,
    Each of the second high-speed serial output circuits enables multi-value output by using two or more high-speed serial output circuits,
    The signal generating circuit according to claim 3, characterized in that:
  5. 　２以上の前記第２の入力信号量子化回路が有する前記第２のフィルタの初期値を、前記第２のフィルタごとに異なる値とする、
    　ことを特徴とする請求項１から４のいずれか１つに記載の信号発生回路。     The initial value of the second filter included in the two or more second input signal quantization circuits is set to a different value for each second filter,
    The signal generating circuit according to any one of claims 1 to 4.
  6. 　２以上の前記第２の入力信号量子化回路は、各々が、前記第２の入力信号に異なる係数を乗算し、前記第２の量子化器の出力信号と前記係数を乗算後の前記第２の入力信号との差分を前記第２のフィルタへの入力信号とし、
    　２以上の前記第２の入力信号量子化回路で前記第２の入力信号に乗算される２以上の前記係数の総和を１とする、
    　ことを特徴とする請求項１から５のいずれか１つに記載の信号発生回路。     The two or more second input signal quantization circuits each multiply the second input signal by a different coefficient, and the second input signal after multiplying the output signal of the second quantizer by the coefficient. The difference between the input signal and the input signal is used as the input signal to the second filter,
    The sum of the two or more coefficients multiplied by the second input signal by the two or more second input signal quantization circuits is 1;
    The signal generating circuit according to any one of claims 1 to 5, characterized in that:
  7. 　信号発生回路を制御するための制御回路であって、
    　１段目の誤差フィードバック型の第１の入力信号量子化回路において、第１の量子化器の出力信号と前記第１の入力信号量子化回路への第１の入力信号との差分を第１のフィルタへの入力信号とし、前記第１のフィルタからの出力信号を前記第１の量子化器への入力信号とし、
    　前記第１の量子化器への入力信号と前記第１の量子化器からの出力信号との差分を第２の入力信号として２以上の第２の入力信号量子化回路へ分配、
    　２段目の誤差フィードバック型の２以上の前記第２の入力信号量子化回路において、各々、第２の量子化器の出力信号と前記第２の入力信号量子化回路への前記第２の入力信号との差分を第２のフィルタへの入力信号とし、前記第２のフィルタからの出力信号を前記第２の量子化器への入力信号とする、
    　ことを前記信号発生回路に実施させることを特徴とする制御回路。     A control circuit for controlling a signal generation circuit,
    In the first stage error feedback type first input signal quantization circuit, the difference between the output signal of the first quantizer and the first input signal to the first input signal quantization circuit is calculated as a first input signal quantization circuit. an input signal to the filter, an output signal from the first filter as an input signal to the first quantizer,
    distributing the difference between the input signal to the first quantizer and the output signal from the first quantizer as a second input signal to two or more second input signal quantization circuits;
    In the two or more second-stage error feedback type second input signal quantization circuits, each of the output signals of the second quantizer and the second input to the second input signal quantization circuit The difference with the signal is used as an input signal to a second filter, and the output signal from the second filter is used as an input signal to the second quantizer.
    A control circuit that causes the signal generation circuit to perform the following operations.
  8. 　信号発生回路を制御するためのプログラムが記憶された記憶媒体であって、
    　前記プログラムは、
    　１段目の誤差フィードバック型の第１の入力信号量子化回路において、第１の量子化器の出力信号と前記第１の入力信号量子化回路への第１の入力信号との差分を第１のフィルタへの入力信号とし、前記第１のフィルタからの出力信号を前記第１の量子化器への入力信号とし、
    　前記第１の量子化器への入力信号と前記第１の量子化器からの出力信号との差分を第２の入力信号として２以上の第２の入力信号量子化回路へ分配、
    　２段目の誤差フィードバック型の２以上の前記第２の入力信号量子化回路において、各々、第２の量子化器の出力信号と前記第２の入力信号量子化回路への前記第２の入力信号との差分を第２のフィルタへの入力信号とし、前記第２のフィルタからの出力信号を前記第２の量子化器への入力信号とする、
    　ことを前記信号発生回路に実施させることを特徴とする記憶媒体。     A storage medium storing a program for controlling a signal generation circuit,
    The program is
    In the first stage error feedback type first input signal quantization circuit, the difference between the output signal of the first quantizer and the first input signal to the first input signal quantization circuit is calculated as a first input signal quantization circuit. an input signal to the filter, an output signal from the first filter as an input signal to the first quantizer,
    distributing the difference between the input signal to the first quantizer and the output signal from the first quantizer as a second input signal to two or more second input signal quantization circuits;
    In the two or more second-stage error feedback type second input signal quantization circuits, each of the output signals of the second quantizer and the second input to the second input signal quantization circuit The difference with the signal is used as an input signal to a second filter, and the output signal from the second filter is used as an input signal to the second quantizer.
    A storage medium characterized in that the signal generation circuit performs the following operations.
  9. 　信号発生回路の信号発生方法であって、
    　１段目の誤差フィードバック型の第１の入力信号量子化回路が、第１の量子化器の出力信号と前記第１の入力信号量子化回路への第１の入力信号との差分を第１のフィルタへの入力信号とし、前記第１のフィルタからの出力信号を前記第１の量子化器への入力信号とする第１のステップと、
    　信号分配部が、前記第１の量子化器への入力信号と前記第１の量子化器からの出力信号との差分を第２の入力信号として２以上の第２の入力信号量子化回路へ分配する第２のステップと、
    　２段目の誤差フィードバック型の２以上の前記第２の入力信号量子化回路が、各々、第２の量子化器の出力信号と前記第２の入力信号量子化回路への前記第２の入力信号との差分を第２のフィルタへの入力信号とし、前記第２のフィルタからの出力信号を前記第２の量子化器への入力信号とする第３のステップと、
    　を含むことを特徴とする信号発生方法。     A signal generation method for a signal generation circuit, the method comprising:
    A first input signal quantization circuit of error feedback type in the first stage converts the difference between the output signal of the first quantizer and the first input signal to the first input signal quantization circuit into a first input signal quantization circuit. a first step in which the output signal from the first filter is an input signal to the first quantizer;
    A signal distribution unit supplies the difference between the input signal to the first quantizer and the output signal from the first quantizer as a second input signal to two or more second input signal quantization circuits. a second step of distributing;
    The two or more second-stage error feedback type second input signal quantization circuits each input the output signal of the second quantizer and the second input to the second input signal quantization circuit. a third step in which the difference from the signal is used as an input signal to a second filter, and the output signal from the second filter is used as an input signal to the second quantizer;
    A signal generation method characterized by comprising:
PCT/JP2022/016017 2022-03-30 2022-03-30 Signal generation circuit, control circuit, storage medium, and signal generation method WO2023188116A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/JP2022/016017 WO2023188116A1 (en) 2022-03-30 2022-03-30 Signal generation circuit, control circuit, storage medium, and signal generation method
JP2024501260A JP7459409B2 (en) 2022-03-30 2022-03-30 Signal generation circuit, control circuit, storage medium and signal generation method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2022/016017 WO2023188116A1 (en) 2022-03-30 2022-03-30 Signal generation circuit, control circuit, storage medium, and signal generation method

Publications (1)

Publication Number Publication Date
WO2023188116A1 true WO2023188116A1 (en) 2023-10-05

Family

ID=88200301

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2022/016017 WO2023188116A1 (en) 2022-03-30 2022-03-30 Signal generation circuit, control circuit, storage medium, and signal generation method

Country Status (2)

Country Link
JP (1) JP7459409B2 (en)
WO (1) WO2023188116A1 (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05152967A (en) * 1990-04-26 1993-06-18 Hughes Aircraft Co Sigma delta analogue/ digital converter
JP2017529023A (en) * 2014-11-10 2017-09-28 三菱電機株式会社 System and method for generating multi-band signals
WO2022054200A1 (en) * 2020-09-10 2022-03-17 三菱電機株式会社 Output signal generation device, control circuit, recording medium, and phase correction method

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5152967B2 (en) 2007-10-12 2013-02-27 パナソニック株式会社 COMMUNICATION METHOD, COMMUNICATION DEVICE, AND COMMUNICATION SYSTEM,

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05152967A (en) * 1990-04-26 1993-06-18 Hughes Aircraft Co Sigma delta analogue/ digital converter
JP2017529023A (en) * 2014-11-10 2017-09-28 三菱電機株式会社 System and method for generating multi-band signals
WO2022054200A1 (en) * 2020-09-10 2022-03-17 三菱電機株式会社 Output signal generation device, control circuit, recording medium, and phase correction method

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
MCCUE JAMIN J.; DUPAIX BRIAN; DUNCAN LUCAS; PATEL VIPUL J.; QUACH TONY; KHALIL WALEED: "A time-interleaved multi-mode ΔΣ RF-DAC for direct digital-to-RF synthesis", 2015 IEEE RADIO FREQUENCY INTEGRATED CIRCUITS SYMPOSIUM (RFIC), IEEE, 17 May 2015 (2015-05-17), pages 103 - 106, XP032818592, DOI: 10.1109/RFIC.2015.7337715 *

Also Published As

Publication number Publication date
JPWO2023188116A1 (en) 2023-10-05
JP7459409B2 (en) 2024-04-01

Similar Documents

Publication Publication Date Title
JP5883181B2 (en) Data converter
KR100979075B1 (en) Method and apparatus for generating a pulse width modulated signal
JP4014598B2 (en) Noise shaping circuit and method using feedback steering for overload compensation, and system using the same
US7116721B1 (en) Delta-sigma modulators with integral digital low-pass filtering
EP1081863B1 (en) Delta-sigma modulator with two-step quantization, and method for using two-step quantization in delta-sigma modulation
CN100514858C (en) Word length reduction circuit
JP4660778B2 (en) PWM signal generator, PWM signal generator, and digital amplifier
CN114301464A (en) Sigma-Delta analog-to-digital converter with aliasing suppression function
JP7459409B2 (en) Signal generation circuit, control circuit, storage medium and signal generation method
US7015843B2 (en) Sigma-delta converter with noise suppression
JPWO2007094255A1 (en) D / A converter
JP4952239B2 (en) Class D amplifier
US20050122244A1 (en) Digital signal processing device and audio signal reproduction device
US7417573B2 (en) Sigma-delta circuit and related method with time sharing architecture
US9218816B2 (en) DAC device and audio system
JP2012044500A (en) Σδ converter
JP2018506900A (en) System and method for signal data transformation using noise shaping
JP7088785B2 (en) Digital microphone
JP3558911B2 (en) D / A converter
JP2001345703A (en) Digital-to-analog converter and digital-to-analog converting method
KR101463034B1 (en) Parallel processing sigma delta modulator and design method thereof

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22935262

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 2024501260

Country of ref document: JP