WO2023186119A1

WO2023186119A1 - Superconducting silicon wafer and preparation method therefor

Info

Publication number: WO2023186119A1
Application number: PCT/CN2023/085556
Authority: WO
Inventors: 徐望胜; 沈龙; 马亮亮; 尤兵; 王念慈; 白城镇; 张辉
Original assignee: 本源量子计算科技（合肥）股份有限公司
Priority date: 2022-04-02
Filing date: 2023-03-31
Publication date: 2023-10-05

Abstract

Disclosed are a superconducting silicon wafer and a preparation method therefor. The preparation method comprises: providing a silicon wafer having through vias, the silicon wafer comprising a first surface and a second surface which are oppositely provided; depositing a superconducting material from the first surface of the silicon wafer at a first temperature, so as to plate a first layer of superconducting film on the first surface of the silicon wafer and hole walls of the through vias; and depositing the superconducting material from the second surface of the silicon wafer at a second temperature higher than the first temperature, so as to plate, on the second surface of the silicon wafer, a second layer of superconducting film connected to the first layer of superconducting film. The superconducting silicon wafer is obtained by adopting the preparation method. By means of the method, a superconducting film can be prevented from being damaged, and reliable superconducting connection is formed on the two surfaces of the silicon wafer.

Description

Superconducting silicon wafer and preparation method thereof

Cross-references to related applications

This patent application requires a Chinese patent application with the invention title "Preparation method of semiconductor structure, semiconductor structure and superconducting quantum device" and application number CN202210354267.5 submitted on April 2, 2022; on April 14, 2022 A Chinese patent application with the invention name "Superconducting interconnect structure and preparation method thereof" and application number CN202210392617.7 submitted on June 16, 2022; the invention name "Superconducting silicon wafer and its preparation method" was submitted on June 16, 2022. Chinese patent application with application number CN202210685143.5; submitted on August 12, 2022, with the invention name "Preparation method of superconducting interconnection structure and preparation method of superconducting quantum circuit" and application number The priority of the Chinese patent application CN202210972234.7, which is fully incorporated herein by reference.

Technical field

The present invention relates to the technical field of superconducting circuits, and in particular to a superconducting silicon wafer and a preparation method thereof.

Background technique

In order to achieve high-density connections, semiconductor devices often create circuits on the front and back of the substrate. Conductive vias are formed by drilling holes in the substrate and filling them with conductive materials, so that the electrical connections between the front circuit and the back circuit pass through the substrate in the shortest possible time. Interconnection is achieved over a distance, which is an integration technology based on Through Silicon Via (TSV).

Through silicon via technology achieves direct interconnection between chips by creating vertical vias between chips and wafers. At present, the through-silicon via interconnection structure generally uses the Bosh process to etch the substrate to form the through-hole. Then, PVD, CVD, ALD, etc. are used to deposit a coating on the wall of the through silicon hole. This process generally takes a long time. For example, when thermal evaporation coating is used, the deposition rate is only The thickness of the through hole is several hundred microns.

Superconducting quantum chips widely use through-silicon via technology due to their high power consumption requirements. In order to realize superconducting connection between the upper and lower sides of the silicon wafer, in the existing manufacturing process, the silicon wafer is placed on a stage, and a superconducting material is deposited on the upper surface of the silicon wafer to form a superconducting film. Since the lower surface of the silicon wafer is attached to the carrier, the precursor can only grow near the through holes on the lower surface of the silicon wafer. Therefore, the superconducting film on the lower surface of the silicon wafer is incomplete, discontinuous and damaged. As shown in Figure 1, it is a light microscope image of the lower surface of the silicon wafer in the existing manufacturing process. A black edge appears on the periphery of the through hole array, which is caused by damage to the superconducting film. Figure 2 shows the SEM characterization image of the lower surface of the silicon wafer in the existing manufacturing process. As can be seen from Figure 2, the superconducting film is damaged in many places on the lower surface of the silicon wafer (circled by the dotted line in the figure). Therefore, it is difficult to form a superconducting connection by only depositing superconducting material once in the existing manufacturing process.

Conventional through silicon via structures are generally formed on semiconductor substrates with a standard thickness of 100 microns to 300 microns. Usually, the position of the through silicon hole is directly defined on the back surface of the crystal, and then the silicon is removed through the plasma etching Bosh process to obtain the through hole. However, the sidewalls of the obtained through holes are relatively steep, and steep through holes, especially deep and straight through holes (for example, through holes formed on semiconductor substrates with a standard thickness of more than 400 microns), are extremely inconvenient for electroplating Subsequent processes such as filling and growing materials on the sidewalls further affect the reliability of the interconnection.

In the existing technology, it is difficult to form a superconducting connection, and the superconducting film is prone to damage.

Contents of the invention

An object of an embodiment of the present disclosure is to provide a superconducting silicon wafer and a preparation method thereof, so that two surfaces of the silicon wafer can form reliable superconducting connections.

In a first aspect, a method for preparing a superconducting silicon wafer is provided, including: providing a silicon wafer with a through hole, the silicon wafer including a first surface and a second surface arranged oppositely; at a first temperature, from the Deposit superconducting material on the first surface of the silicon wafer to plate a first layer of superconducting film on the first surface of the silicon wafer and the hole wall of the through hole; at a second temperature higher than the first temperature A superconducting material is deposited from the second surface of the silicon wafer under a certain temperature to coat the second surface of the silicon wafer with a second layer of superconducting film connected to the first layer of superconducting film.

In the second aspect, generally, in the through-silicon via integration technology, the obtained through-hole sidewalls are relatively steep and are not convenient for subsequent processes such as electroplating and filling.

Here, a method for preparing a semiconductor structure is provided, including: forming a first mask on a surface of a substrate, the surface including an opposing first surface and a second surface; patterning the first mask to obtain a first window and a second window, and the first window is located on the first surface, and the second window is located on the second surface; and etching through the first window and the second window using potassium hydroxide solution The substrate obtains a through hole, the through hole includes a connected first partial through hole and a second partial through hole, and the first partial through hole is formed on the first surface, and the second partial through hole is formed on the first surface. the second surface.

Optionally, the first mask includes one of the following: SiO ₂ , SiN _x , or ITO.

Optionally, the aspect ratio of the first part of the through hole and the second part of the through hole is ≥20:1.

Optionally, the angle between the side wall of the first part of the through hole and the first surface and the angle between the side wall of the second part of the through hole and the second surface are both between 52° and 54°.

Optionally, the preparation method further includes: forming a superconducting material on the sidewall of the first part of the through hole; and forming a superconducting material on the sidewall of the second part of the through hole, and forming a superconducting material on the sidewall of the second part of the through hole. Through hole The superconducting material on the sidewalls is interconnected with the superconducting material on the sidewalls of the first portion of the through hole.

Optionally, the superconducting material is indium or titanium nitride.

In a third aspect, a semiconductor structure is provided, including: a substrate including an opposing first surface and a second surface; and a through hole including a first portion of the through hole and a second portion of the through hole that are connected, and the first portion A through hole is formed on the first surface, and the second partial through hole is formed on the second surface.

Optionally, the sidewalls of the first portion of the through-hole and the sidewalls of the second portion of the through-hole are formed with interconnected superconducting material.

Optionally, the superconducting material is indium or titanium nitride.

According to a fourth aspect, a superconducting silicon wafer obtained according to any of the above preparation methods is also provided.

In a fifth aspect, a superconducting quantum device is provided, including: the semiconductor structure according to the embodiment; a first superconducting circuit formed on the first surface; and a second superconducting circuit formed on the second surface. A conductive circuit, and the second superconducting circuit and the first superconducting circuit are electrically connected through the superconducting material.

Optionally, the first superconducting circuit is a qubit, the second superconducting circuit is a reading resonant cavity, and the qubits and the reading resonant cavity correspond one to one.

Optionally, the qubit includes a capacitor and a superconducting quantum interferer connected in parallel with the capacitor.

In one embodiment, compatibility between twice deposited superconducting films may be improved. The first layer of superconducting film and the second layer of superconducting film can be integrated to prevent damage to the superconducting film and form a reliable superconducting connection between the two surfaces of the silicon wafer.

Alternatively, potassium hydroxide solution wet etching has the characteristics of anisotropy and a fixed etching inclination angle. Therefore, in another embodiment, the side walls of the first part of the through hole and the side walls of the second part of the through hole are inclined at a certain angle relative to the surface where they are located, so as to prevent the formed through hole from having a deep and steep shape. This in turn facilitates the process of growing material on the sidewalls to achieve interconnection.

Generally, the preparation process of through-silicon via interconnect structures takes a long time. In a sixth aspect, a method for preparing a superconducting interconnect structure is provided, including filling molten superconducting material into a first hole for forming a through-silicon via to form a superconducting element.

In one embodiment, the first hole is a through-hole through the substrate, and filling the molten superconducting material into the first hole for forming the through-silicon via to form the superconducting element includes: forming a through-hole through the substrate ; Filling the powder of superconducting material into the through hole; and melting the powder to obtain a superconducting connecting element filling the through hole.

Optionally, the step of filling the powder of superconducting material into the through hole and melting the powder is performed in a vacuum environment.

Optionally, the step of filling the powder of superconducting material into the through hole and melting the powder is performed in a reducing atmosphere.

Optionally, the reducing atmosphere is formed using one of H ₂ , CO, and formic acid vapor.

Optionally, the step of filling the powder of superconducting material into the through hole and melting the powder includes: first blocking and heating one side of the through hole, and then filling the powder of superconducting material into the through hole. The powder is melted into the through hole, wherein the particle size of the powder is smaller than the diameter of the through hole.

Optionally, the superconducting material includes at least one of indium, titanium nitride, niobium, niobium nitride, and tantalum.

In a seventh aspect, a superconducting interconnect structure is provided, including: a through hole penetrating a substrate; and a superconducting connection element formed in the through hole, the superconducting connection element completely filling the through hole .

Optionally, the superconducting connecting element has no voids inside.

Optionally, there is no oxide impurity inside the superconducting connection element.

Optionally, the superconducting connection element is at least one of indium, titanium nitride, niobium, niobium nitride, and tantalum.

Optionally, the diameter of the through hole is ≥50 microns.

Optionally, a first superconducting circuit is formed on the first surface of the substrate, a second superconducting circuit is formed on the second surface of the substrate, and the through hole penetrates the first surface and the third superconducting circuit. two surfaces, and the first superconducting circuit and the second superconducting circuit are connected through the superconducting connecting element. The first superconducting circuit is a qubit, the second superconducting circuit is a reading resonant cavity, and the qubits and the reading resonant cavity correspond one to one. The qubit includes a capacitor and a superconducting quantum interference device in parallel with the capacitor.

Optionally, according to one embodiment, the method of powder filling and melting is short-time consuming and highly efficient, which helps to achieve rapid preparation of TSV-based interconnect structures.

In another embodiment, the first hole is a blind hole, and filling the molten superconducting material into the first hole for forming the through silicon via to form the superconducting element includes: forming a blind hole on the substrate; Superconducting material is filled into the blind hole to form a superconducting element; and on one side of the bottom of the blind hole, the substrate is thinned to form a through hole penetrating the substrate.

Optionally, before filling the molten superconducting material into the blind hole, the method further includes: forming an adhesive wetting layer on the inner wall of the blind hole.

Optionally, the adhesive wetting layer includes: a first material layer adhering to the inner wall; and a second material layer adhering to the first material layer.

Optionally, the first material layer includes titanium Ti or nickel Ni, and the second material layer includes gold Au or copper Cu.

Optionally, at the same time as filling the molten superconducting material into the blind hole, it also includes: heating the substrate to above the melting point of the superconducting material.

Optionally, the step of filling the molten superconducting material into the blind hole includes: forming the superconducting material into particles; and melting the particles separately to form droplets and filling the blind hole.

Optionally, molten superconducting material is filled into the blind holes in an oxidation resistant environment.

Optionally, the anti-oxidation environment is a vacuum environment.

Optionally, the anti-oxidation environment is an environment of non-oxidizing gas.

Optionally, the non-oxidizing gas includes one of nitrogen N ₂ , hydrogen H ₂ , carbon monoxide CO, and formic acid vapor.

Optionally, the superconducting material includes at least one of indium In, tin Sn, lead Pt, and indium tin alloy.

In a ninth aspect, a method for preparing a superconducting quantum circuit is provided, including: a superconducting interconnect structure prepared according to the above preparation method; and forming a first superconducting quantum circuit at one end of the through hole. The surface of the substrate, and the first superconducting quantum circuit is connected to one end of the superconducting element; and a second superconducting quantum circuit is formed on the surface of the substrate at the other end of the through hole, and the third superconducting quantum circuit is connected to one end of the superconducting element. Two superconducting quantum circuits are connected to the other end of the superconducting element.

Optionally, the first superconducting quantum circuit, the superconducting element and the second superconducting quantum circuit form one of the following structures: a pulse control signal line, a magnetic flux control signal line, a read signal line, and a read signal line. Take the resonant cavity.

Optionally, according to one embodiment, the method of filling the blind holes and then thinning the molten superconducting material is short and efficient, which is helpful for rapid preparation of TSV-based superconducting interconnect structures.

Description of drawings

Figure 1 is a light microscope diagram of the lower surface of a silicon wafer in the existing manufacturing process.

Figure 2 is an SEM characterization picture of the lower surface of the silicon wafer in the existing manufacturing process.

FIG. 3 is a schematic flow chart of a method for preparing a superconducting silicon wafer according to an embodiment of the present invention.

Figure 4 is a schematic structural diagram of a silicon wafer with through holes.

Figure 5 is a schematic diagram of the preparation process of the superconducting film.

Figure 6 is a low-magnification optical microscope image of the second surface of the superconducting silicon wafer obtained by the preparation method provided by the embodiment of the present invention.

Figure 7 is a high-magnification optical microscope image of the second surface of the superconducting silicon wafer obtained by the preparation method provided by the embodiment of the present invention.

Figure 8 is a step flow chart of a method for preparing a semiconductor structure provided by an embodiment of the present application;

9A to 9C are schematic flow diagrams of a method for manufacturing a semiconductor structure provided by embodiments of the present application;

Figure 10 is a schematic diagram of a semiconductor structure provided by an embodiment of the present application;

Figure 11 is a schematic structural diagram of a superconducting quantum device provided by an embodiment of the present application.

Figure 12 is a step flow chart of a method for preparing a superconducting interconnect structure provided by an embodiment of the present application;

Figure 13 is a schematic diagram of powder filling through holes and melting according to the embodiment of the present application;

Figure 14 is a schematic diagram of a superconducting interconnection structure provided by an embodiment of the present application.

Figure 15 is a step flow chart of a method for preparing a superconducting interconnect structure provided by an embodiment of the present application;

Figure 16 is a schematic diagram of blind holes filled with molten superconducting material according to an embodiment of the present application;

Figure 17a is a schematic diagram of the substrate before thinning provided by the embodiment of the present application;

Figure 17b is a schematic diagram of the substrate after thinning according to the embodiment of the present application;

Figure 18 is a schematic diagram of an adhesive wetting layer formed on the inner wall of a blind hole provided by an embodiment of the present application;

Figure 19 is a schematic diagram of substrate heating provided by an embodiment of the present application;

Figure 20 is a schematic structural diagram of a superconducting quantum circuit provided by an embodiment of the present application.

Explanation of reference symbols:
1-substrate, 11-first surface, 12-second surface,
2-first mask, 21-first window, 22-second window,
3-through hole, 31-first part through hole, 32-second part through hole,
41-First quantum circuit, 42-Second quantum circuit,
51-first superconducting material layer, 52-second superconducting material layer.
1C-heating platform, 2C-substrate, 21C-first surface, 22C-second surface, 3C-through hole, 4v-
Indium powder, 5C-superconducting connecting element.
1D-substrate, 11D-first surface, 12D-second surface, 13D-blind hole, 14v-third surface,
21D-molten droplets, 22D-superconducting elements,
3D-adhesive wetting layer, 31D-first material layer, 32D-second material layer,
4D-heating plate, 5D-first superconducting quantum circuit, 6D-second superconducting quantum circuit.

Detailed ways

Specific embodiments of the present invention will be described in more detail below with reference to the schematic diagrams. The advantages and features of the invention will become more apparent from the following description and claims. It should be noted that the drawings are in a very simplified form and use imprecise proportions, and are only used to conveniently and clearly assist in explaining the embodiments of the present invention.

In the description of the present invention, it should be understood that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", etc. is based on the orientation or positional relationship shown in the drawings. , is only for the convenience of describing the present invention and simplifying the description, but does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be construed as a limitation of the present invention.

In addition, the terms “first” and “second” are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of indicated technical features. Therefore, features defined as "first" and "second" may explicitly or implicitly include one or more of these features. In the description of the present invention, "plurality" means at least two, such as two, three, etc., unless otherwise expressly and specifically limited.

Please refer to Figure 3, which provides a method for preparing a superconducting silicon wafer. The preparation method includes the following steps.

S11: Provide a silicon wafer with a through hole, and the silicon wafer includes a first surface and a second surface arranged oppositely.

Through silicon via technology enables the circuits on the upper surface of the silicon chip to be directly interconnected with the circuits on the lower surface, greatly shortening the wiring length and reducing signal delay and loss.

Silicon wafers usually have a considerable thickness. The standard thickness of silicon wafers for through-holes is between 100 microns and 300 microns. However, for special needs, the thickness of some silicon wafers usually needs to be greater than 400 microns. Through holes on silicon wafers can be prepared using the Bosch process.

As shown in Figure 4, it is a silicon wafer with through holes. The silicon chip 1 has through holes A2 arranged in an array. The surface facing upward in the figure is the first surface of the silicon wafer 1 , and the surface facing downward in the figure is the second surface of the silicon wafer 1 . The present invention does not limit the shape of the hole wall of the through hole A2. In this embodiment, the hole wall of the through hole A2 may be vertical or inclined relative to the first surface.

It should be noted that the first surface and the second surface are relative. You can choose any side of the silicon wafer to be the first surface, and the other side to be the second surface.

S12: Deposit a superconducting material from the first surface of the silicon wafer at a first temperature to plate a first layer of superconducting film on the first surface of the silicon wafer and the hole wall of the through hole.

When the superconducting material is deposited on the first surface of the silicon wafer, the superconducting material will be deposited on the first surface of the silicon wafer and the hole wall of the through hole, and finally coated with a film on the first surface of the silicon wafer and the hole wall of the through hole, and at the same time , inevitably, due to the conformality during coating, the superconducting material will also grow near the through holes on the second surface of the silicon wafer, so a part of the first layer will also be plated near the through holes on the second surface of the silicon wafer. superconducting film.

S13: Deposit a superconducting material from the second surface of the silicon wafer at a second temperature higher than the first temperature, so as to coat the second surface of the silicon wafer with a second layer of superconducting film connected to the first layer of superconducting film. membrane.

When depositing superconducting material on the second surface of the silicon wafer, since there is already a first layer of superconducting film near the through hole, the superconducting material will only be deposited on the second surface of the silicon wafer due to the influence of the first layer of superconducting film. And because the superconducting material is deposited at a second temperature higher than the first temperature, the deposited superconducting material has strong compatibility with the first layer of superconducting film. Finally, the second layer is plated on the second surface of the silicon wafer. The superconducting film is connected to the first layer of superconducting film, that is, the two are integrated into one.

In order to ensure that the superconducting films formed twice are continuous and have the same thickness, in this embodiment, the thickness of the first superconducting film and the second superconducting film are the same. The thickness of the first superconducting film and the second superconducting film can be made the same by adjusting the process parameters of depositing the superconducting material twice.

For example, in this embodiment, the first layer of superconducting film is obtained by atomic layer deposition or chemical vapor deposition.

As shown in Figure 5(a), it is a schematic cross-sectional view along the AA direction shown in Figure 4. Before depositing the superconducting material, the silicon wafer 1 is placed on the stage with the first surface 1A of the silicon wafer 1 facing upward. Figure 5(b) is a schematic diagram of the silicon wafer shown in Figure 5(a) being coated with the first layer of superconducting film. At the first temperature, using the atomic layer deposition method Or when depositing superconducting material by chemical vapor deposition, the superconducting material will be deposited on the first surface 1A of the silicon wafer 1 and the hole wall of the through hole A2, and grow near the through hole 2 on the second surface 1B of the silicon wafer 1 , and finally the first layer of superconducting film is plated on the first surface 1A of the silicon wafer 1, the hole wall of the through hole A2, and the vicinity of the through hole A2 on the second surface 1B of the silicon wafer 1.

Further, in this embodiment, the second layer of superconducting film is obtained by magnetron sputtering or electron beam evaporation. For example, the first temperature is lower than 50°C, and the second temperature is 300 to 800°C.

When depositing superconducting materials using magnetron sputtering or electron beam evaporation, the silicon wafer 1 needs to be turned over first. Figure 5(c) is a schematic diagram of the silicon wafer shown in Figure 5(b) after being flipped. The flipped silicon wafer 1 is placed on the stage, with the second surface 1B of the silicon wafer 1 facing upward. Figure 5(d) is a schematic diagram of the silicon wafer shown in Figure 5(c) being coated with a second layer of superconducting film. Superconducting material is sputtered on the second surface 1B of the silicon wafer 1 at the second temperature. The superconducting material will grow on the second surface 1B of the silicon wafer 1 and fuse with the first layer of superconducting film. Finally, the superconducting material will grow on the second surface 1B of the silicon wafer 1. The second surface 1B of the sheet 1 is coated with a second layer of superconducting film connected to the first layer of superconducting film.

In some application scenarios, since the surface of the superconducting film is easily oxidized after it is formed, an oxide layer is easily generated on the surface of the first superconducting film. This oxide layer will hinder the interaction between the second superconducting film and the first superconducting film. Fusion. In this embodiment, before the step of depositing the superconducting material from the second surface of the silicon wafer at the second temperature, that is, step S13, the preparation method also includes: S131: removing the first layer located on the second surface of the silicon wafer. oxide layer on the surface of the superconducting film.

Since the second layer of superconducting film is only formed on the second surface of the silicon wafer, it is only necessary to remove the oxide layer on the surface of the first layer of superconducting film on the second surface of the silicon wafer. The oxide layer can be removed using ion beam etching (IBE).

In some embodiments, the superconducting material is a material that exhibits superconducting properties at or below a critical temperature, including at least one of aluminum, titanium nitride, indium, niobium, niobium nitride, and tantalum, but the present invention does not This is limited to other materials that exhibit superconducting properties at or below the critical temperature.

Compared with the prior art of only depositing superconducting material once, the above method can improve the compatibility between the superconducting films deposited twice. The first layer of superconducting film and the second layer of superconducting film can be integrated to prevent damage to the superconducting film and form a reliable superconducting connection between the two surfaces of the silicon wafer.

A superconducting silicon wafer is also provided. The superconducting silicon wafer is obtained by using the method for preparing the superconducting silicon wafer in the aforementioned embodiment.

The second surface of the superconducting silicon wafer in this embodiment was inspected with an optical microscope. The inspection results are shown in Figures 6 and 7. The optical microscope magnification of Figure 6 is x30.0. It can be seen that there is no black color on the periphery of the through hole array. On the other hand, the optical microscope magnification of Figure 7 is x200.0. It can be seen that the superconducting film on the second surface of the superconducting silicon wafer is complete and continuous, and there is no damage to the superconducting film. Therefore, reliable superconducting connection can be achieved on both surfaces of the superconducting silicon wafer in this embodiment.

Integration technology based on Through Silicon Via (TSV) allows the circuits on the front side of the substrate and the circuits on the back side to be directly interconnected, greatly shortening the wiring length and reducing signal delay and loss.

Semiconductor substrates usually have considerable thickness, and in related technologies, plasma etching Bosch process is used to form through holes. The Bosh process can form vertical vias with a relatively high aspect ratio, and the side walls of the vias formed are steep. Steep through-holes, especially deep and steep through-holes formed on thicker substrates, make the subsequent process of growing material on the sidewalls of the through-hole quite difficult. The conformal coverage of the growth material is low, which can easily lead to the failure of the sidewall material layer, thereby affecting the interconnection characteristics of the entire TSV. Generally, the standard thickness of the semiconductor substrate for through-holes is between 100 microns and 300 microns. For special needs, the thickness of some semiconductor substrates usually needs to be greater than 400 microns. How to avoid deep and steep through holes from affecting subsequent processes such as electroplating and filling, and how to ensure that the morphology of the sidewalls is conducive to growing materials for interconnection, needs to be solved urgently.

FIG. 8 is a step flow chart of a method for manufacturing a semiconductor structure provided by an embodiment of the present application. 9A to 9C are schematic flow diagrams of a method for manufacturing a semiconductor structure provided by embodiments of the present application.

As shown in FIG. 8 and FIG. 9 , a method for preparing a semiconductor structure is provided, including step S101 to step S103.

Step S101: Form the first mask 2 on the surface of the substrate 1. The surfaces include opposite first surfaces 11 and second surfaces 12, and the substrate 1 may be silicon.

Step S102: Pattern the first mask 2 to obtain the first window 21 and the second window 22. The first window 21 is located on the first surface 11 and exposes a portion of the first surface 11 . The second window 22 is located on the second surface 12 and exposes a portion of the second surface 12 . The distribution of the first window 21 and the second window 22 is symmetrical to facilitate the formation of through holes.

Step S103: Use potassium hydroxide solution to etch the substrate 1 through the first window 21 and the second window 22 to obtain a through hole 3. The through hole 3 includes a first partial through hole 31 and a second partial through hole 32 that are connected. The first partial through hole 31 is formed on the first surface 11 . The second partial through hole 32 is formed on the second surface 12 . It can be understood that the first partial through hole 31 is formed by etching the exposed area of the first window 21 , and the second partial through hole 32 is formed by etching the exposed area of the second window 22 .

Here, the potassium hydroxide solution wet etching has anisotropy and the etched sidewalls are inclined, thereby ensuring that the sidewalls of the first part of the through hole 31 and the sidewall of the second part of the through hole 32 have relative characteristics relative to the surface where they are located. The fixed inclination angle prevents the formed through hole from having a deep and steep shape, which in turn facilitates the process of growing material on the sidewall to achieve interconnection.

In some embodiments, the first mask 2 includes one of the following: SiO ₂ , SiN _x , and ITO. For example, LPCVD is used to grow SiNx on the silicon substrate 1 as the first mask 2 and achieve full surface coverage of the substrate 1 . Then, photoresist is coated on the first mask 2 and the first surface 11 and the second surface 12 of the substrate 1 are mask patterned using the photoresist. The potassium hydroxide solution is then used to complete the etching of the substrate 1 . During specific implementation, the etching cutoff position can be controlled by adjusting the line width, etching time, etc. on the surface of the first mask 2 . As an example, SPR955 photoresist can be used in combination with a stepper photolithography tool Double-sided pattern exposure is performed, and the mask can be patterned after development. It is not limited to this, other methods may also be used to form SiO ₂ or ITO as the first mask 2 on the surface of the substrate 1 .

In other embodiments, the aspect ratio of the first part of the through hole 31 and the second part of the through hole 32 is ≥20:1. For example, the maximum diameter of the through hole formed on a silicon substrate with a standard thickness of 400 microns does not exceed 20 microns. As the thickness of the substrate 1 increases, the advantages of this solution become more obvious. Wet etching using potassium hydroxide solution from the opposite first surface 11 and the second surface 12 not only has a higher rate (Si concentration is 30%) And the etching rate in KOH solution with a temperature of 70°C is 35.7-37.4μm/H). Wet etching with potassium hydroxide solution can ensure a fixed etching angle, and the sidewall shape obtained by etching two surfaces at the same time. The appearance can avoid deep, steep and straight situations.

In some embodiments, the angle between the side wall of the first part of the through hole 31 and the first surface 11 and the angle between the side wall of the second part of the through hole 32 and the second surface 12 are both 52° to 54°. For example, the included angle may be 52°, 52.5°, 53°, 53.2°, 53.5°, 53.8°, or 54°.

In one embodiment, the preparation method further includes: evaporating in a direction perpendicular to the first surface 11 to form a superconducting material on the sidewall of the first part of the through hole 31 to obtain the first superconducting material layer 51; And, evaporate along the direction perpendicular to the second surface 12 to form a superconducting material on the side wall of the second partial through hole 32 to obtain a second superconducting material layer 52 located in the second partial through hole 32 The superconducting material on the sidewall is interconnected with the superconducting material on the sidewall of the first partial through hole 31 , that is, the first superconducting material layer 51 and the second superconducting material layer 52 are interconnected. E-Beam, ALD or other optical coating methods can be used during evaporation.

In one embodiment, the superconducting material is indium or titanium nitride, and may also be aluminum or niobium. The specific implementation is not limited to these materials. It is a material that exhibits superconducting properties at a temperature equal to or lower than the critical temperature. Both are available.

In one embodiment, the substrate 1 is wet etched with KOH through the first window 21 and the second window 22 to obtain a through hole, and the self-stopping property of the (111) crystal plane of KOH wet etching is utilized. When forming a TSV through hole 3, the existence of the inherent angle between the (111) crystal plane and the (100) crystal plane helps to obtain a through hole 3 with a relatively fixed angle between the side wall and the surface. The embodiment of the present application uses KOH wet etching to synchronously etch from the first surface 11 and the second surface 12 to form the first partial through hole 31 and the second partial through hole 32 respectively. The etching in two directions avoids sidewall retention. An angle throughout helps avoid the appearance of steep side walls. For example, due to the anisotropy of KOH corroding Si, and the corrosion angle is fixed, the embodiment of this application can use etching in 30% concentration KOH and a constant temperature of 70°C. The etching rate of Si in this solution is 35.7-37.4 μm/H, the line width can be controlled according to the angle, thereby controlling the surface opening size. Moreover, the first partial through hole 31 formed on the first surface 11 and the second partial through hole 32 formed on the second surface 12 may be symmetrical, for example, a symmetrical structure formed by simultaneous etching with a KOH solution. . In the embodiment of the present application, the diameter of the first part of the through hole 31 and the diameter of the second part of the through hole 32 both reach the maximum at the surface opening of the substrate 1 .

FIG. 10 is a schematic diagram of a semiconductor structure provided by an embodiment of the present application.

Referring to FIG. 10 , in combination with FIG. 8 and FIGS. 9A to 9C , another embodiment of the present application provides a semiconductor structure, which includes: a substrate 1 including an opposite first surface 11 and a second Surface 12, the substrate 1 may be silicon; and the through hole 3 includes a connected first part of the through hole 31 and a second part of the through hole 32, and the first part of the through hole 31 is formed on the first surface 11, the The second partial through hole 32 is formed on the second surface 12 .

The sidewall morphology in the embodiment of the present application facilitates the process of growing material on the sidewall to achieve interconnection. It should be noted that the semiconductor structure of the embodiment of the present application can be prepared by the above-mentioned embodiment of the preparation method of the semiconductor structure. In the embodiment of the present application, the diameter of the first part of the through hole 31 and the diameter of the second part of the through hole 32 both reach the maximum at the surface opening of the substrate 1 .

In some embodiments of the present application, the aspect ratio of the first part of the through hole 31 and the second part of the through hole 32 is ≥20:1. For example, they are formed on a silicon substrate with a standard thickness of 400 microns. Through hole 3, the maximum diameter of hole 3 does not exceed 20 microns.

In other embodiments of the present application, the angle between the side wall of the first partial through hole 31 and the first surface 11 and the angle between the side wall of the second partial through hole 32 and the second surface 12 The included angles are all between 52° and 54°. For example, the included angles may be 52°, 52.5°, 53°, 53.2°, 53.5°, 53.8°, or 54°. It should be noted that the steep through hole 3 is not convenient for growing material on the side wall, but controlling the angle between 52° and 54° facilitates the use of E-Beam, ALD or other optical coating methods to grow material on the side wall. . For a thicker substrate 1, the through hole 3 is adopted to include a connected first partial through hole 31 and a second partial through hole 32, wherein the first partial through hole 31 is formed on the first surface 11, so The second partial through hole 32 is formed on the second surface 12 . This structural form avoids the steep topography of the side wall and is conducive to growing material on the side wall to realize the interconnection of the electrical structures on both sides of the through hole 3 .

In some embodiments of the present application, sidewalls of the first through hole 31 and the second through hole 32 are formed with interconnected superconducting material, for example, formed on the first through hole. The first superconducting material layer 51 on the sidewall of 31 is interconnected with the second superconducting material layer 52 formed on the sidewall of the second partial through hole 32 . In one embodiment of the present application, the superconducting material is indium or titanium nitride, and may also be aluminum or niobium. The specific implementation is not limited to these types. It exhibits superconducting at a temperature equal to or lower than the critical temperature. Materials with special characteristics are available.

Referring to FIG. 11 , combined with FIG. 8 , FIG. 9A to FIG. 9C and FIG. 10 , the third embodiment of the present application provides a superconducting quantum device. The superconducting quantum device includes: the above semiconductor structure The semiconductor structure described in the embodiment; the first superconducting circuit 41 formed on the first surface 11; and the second superconducting circuit 42 formed on the second surface 12, and the second superconducting circuit 42 is formed on the second surface 12. The circuit 42 is electrically connected to the first superconducting circuit 41 through the superconducting material. The expansion and integration of qubits is achieved through the through holes in the semiconductor structure provided by this embodiment, which can support dense qubits and alleviate interconnection congestion. What needs to be pointed out here is that the embodiment of the superconducting quantum device has the same characteristics as the above-mentioned semiconductor The structural embodiments have the same beneficial effects, so no further description is given.

In some embodiments of the present application, the first superconducting circuit 41 is a qubit, the second superconducting circuit 42 is a read resonant cavity, and the qubit 41 and the read resonant cavity 42 are the same. One corresponds to coupling.

In some embodiments of the present application, the qubit 41 includes a capacitor and a superconducting quantum interferometer (Squid) connected in parallel with the capacitor.

Compared with the prior art, this application first forms the first mask 2 on the surface of the substrate 1 , the surface includes the opposite first surface 11 and the second surface 12 , and then patterns the first mask 1 A first window 21 and a second window 22 are obtained, and the first window 21 is located on the first surface 11 and the second window 22 is located on the second surface 12, and then a potassium hydroxide solution is used to pass through the The first window 21 and the second window 22 are etched into the substrate 1 to obtain a through hole 3. The through hole 3 includes a connected first partial through hole 31 and a second partial through hole 32, and the first partial through hole 31 is connected to the first partial through hole 31 and the second partial through hole 32. The hole 31 is formed on the first surface 11 , and the second partial through hole 32 is formed on the second surface 12 . In this application, after patterning the first mask 2 on both the opposing first surface 11 and the second surface 12, potassium hydroxide solution is used to synchronously etch from the first surface 11 and the second surface 12 to respectively form the first mask 2. For a part of the through hole 31 and the second part of the through hole 32, the potassium hydroxide solution wet etching is anisotropic and the etching angle is fixed, thereby ensuring that the side walls of the first part of the through hole 31 and the side walls of the second part of the through hole 32 are The walls are inclined at a certain angle relative to the surface where they are located, such as 52° or 53° relative to the surface where they are located, to avoid deep and steep morphology of the formed through holes, thereby helping to achieve mutual interaction between the growing materials on the side walls. Even the craftsmanship. It should be noted that etching from two directions prevents the sidewalls from penetrating at an angle, which helps improve the situation where it is difficult for materials to grow on the sidewalls of deep holes.

The existing method of forming an interconnection structure based on through-silicon vias mainly uses plasma etching Bosch process to prepare through-silicon vias, and then through any appropriate process (for example, chemical vapor deposition (CVD)). ) or plasma enhanced chemical vapor deposition (PECVD) or atomic layer deposition (ALD) is attached to the wall of the through silicon hole to form a layer for electrical connection. For example, in the related art, copper electroplating principles are used to form a layer in the through silicon hole. Depositing copper realizes the electrical connection between electronic components of different chips. Depositing copper in a through silicon hole usually requires first adhering a seed layer to the wall of the through silicon hole, and then electroplating copper on the seed layer. This implementation process It is more complex and slow, and as the aspect ratio of the through silicon hole increases, the copper diffusion barrier layer and the copper seed layer may not completely cover the inner surface of the through silicon hole, causing the layer formed after electroplating filling. The generation of void defects leads to a decrease in the reliability of interconnect structures based on through-silicon vias, and even circuit breakage problems. Non-superconducting materials such as copper are not suitable for the transmission of superconducting signals in quantum computing.

In addition, when chemical vapor deposition (CVD) or plasma enhanced chemical vapor deposition (PECVD) or atomic layer deposition (ALD) are used to fill through silicon holes, or other methods are used, such as molecular beam deposition, atomic vapor deposition, sputtering When filling through-silicon vias such as injection molding, etc., it is necessary to first obtain a through-silicon via shape that is conducive to growing material. appearance, otherwise the process of growing materials on the sidewalls of the through-silicon vias would be quite difficult. Specifically, the sidewall morphology of the through silicon via in the current related technology affects the conformal coverage of the growth material, which can easily lead to the failure of the sidewall material layer, thereby affecting the interconnection characteristics of the entire structure.

FIG. 12 is a step flow chart of a method for preparing a superconducting interconnect structure according to an embodiment. 13 is a schematic diagram of powder filling through holes and melting according to an embodiment.

As shown in Figure 12 and Figure 13, a method for preparing a superconducting interconnection structure includes step S101C to step S102C, wherein:

Step S101C: Provide a substrate 2C having an opposing first surface 21C and a second surface 22C. A through hole 3C penetrating the first surface 21C and the second surface 22C is formed on the substrate 2C. The substrate 2C may be made of undoped single crystal silicon, impurity-doped single crystal silicon, silicon on insulator (SOI), etc. As an example, in this embodiment, the substrate 2C is made of single crystal silicon material. In this embodiment, the through hole 3C is formed by etching the substrate 2C. The substrate 2C can be dry etched or wet etched to obtain the through hole 3C, such as using reactive ion etching (RIE), inductively coupled plasma etching (Inductively Coupled Plasma, ICP), high-density Plasma etching (High Density Plasma Etch, HDPE), deep reactive ion etching (Deep Reactive Ion Etching, DRIE) or chemical solution wet etching, etc.

Step S102C: Fill the powder of superconducting material into the through hole 3C and melt the powder to obtain the superconducting connection element 5C that completely fills the through hole 3C. For example, the second surface 22C can be placed on the heating platform 1C to ensure that the heating platform 1C can heat the space area within the through hole 3C. Then, the powder of superconducting material is used to plant balls on the first surface of the substrate 2C. Then, the powder is filled into the through hole 3C by pressing, adsorbing or blowing, and the powder is melted.

Compared with the prior art method of first etching the substrate 2C to form a through hole, and then using PVD, CVD, ALD, etc. to fill the through hole 3C to prepare an interconnection structure, the embodiment provided in this application uses superconducting materials. The powder is filled into the through hole 3C and the powder is melted. After solidification, the superconducting connection element 5C that completely fills the through hole 3C can be formed, thereby obtaining a superconducting interconnection structure. Compared with related technologies, this application improves the filling efficiency of through holes 3C and helps to achieve rapid preparation of TSV-based interconnect structures. In this embodiment, the requirements for the sidewall shape of the through hole 3C are relatively low, that is, any sidewall shape that is steep, inclined, or arc-shaped is applicable.

In some embodiments, the powder of the superconducting material is filled into the through hole 3C and the powder is melted in a vacuum environment to avoid oxidation during the heating and melting of the powder and affecting the filling effect. For example, superconducting material powder can be filled into the through hole 3C in a closed reaction chamber with a certain degree of vacuum and the powder can be melted. For example, the vacuum degree in the reaction chamber is greater than 10 ^-5 Pa and less than 10 ^-3 Pa. In other embodiments, powder of superconducting material is filled into the through hole 3C and the powder is melted in a reducing atmosphere. In one embodiment, the reducing atmosphere is formed using one of H ₂ , CO, and formic acid vapor. In one embodiment, the powder of superconducting material is indium powder. For example, hydrogen gas can be introduced to add Heat to above 300°C, or add CO and heat to above 750°C, or add formic acid gas to first heat and maintain at 150°C to 200°C, and then heat to above 200°C. In one example, formic acid gas is introduced to first heat and maintain the temperature at 160°C and then heat to 220°C. The filling effect of through hole 3C is directly related to the reliability and yield of TSV integration technology. Due to the presence of an oxide layer on the surface of the indium powder, its melting point is higher than that of indium and is difficult to melt, causing voids to form in the superconducting connection element 5C and thus affecting the reliability and yield of the superconducting interconnection structure. Control the heating temperature in a reducing atmosphere such as H ₂ , CO, formic acid vapor, etc. to melt indium and fill it into the hole. Repeat this many times to completely fill the through hole 3C, avoiding the presence of indium oxide and helping to avoid the formation of voids. It should be noted that indium oxide (In ₂ O ₃ ) reacts with formic acid at 150°C to 200°C to generate In(COOH) ₃ , and In(COOH) ₃ reacts with formic acid at a temperature above 200°C to generate indium (In).

In some embodiments, the step of filling the powder of superconducting material into the through hole 3C and melting the powder includes: first blocking one side of the through hole 3C and heating the inside of the through hole 3C; Then, the powder of superconducting material is filled into the through hole 3C, and the powder is heated and melted, wherein the particle size of the powder is smaller than the diameter of the through hole 3C. For example, when the diameter of the through hole 3C is 50 microns, indium powder with a diameter of 23 microns can be used to fill the through hole 3C.

In some embodiments, the superconducting material is a material that exhibits superconducting properties at a temperature equal to or lower than the critical temperature, including indium in the above examples, and aluminum, niobium, titanium nitride, niobium nitride, and tantalum. wait. For example, one of the above and a combination thereof may be used. The specific implementation is not limited to these types, and any material that exhibits superconducting properties at a temperature equal to or lower than the critical temperature can be used.

Referring to FIG. 14 , in combination with FIGS. 12 and 13 , a superconducting interconnect structure is provided, including: a through hole 3C penetrating the opposing first surface 21C and the second surface 22C on the substrate 2C; and The superconducting connection element 4C is formed in the through hole 3C, and the superconducting connection element 4 completely fills the through hole 3C.

It should be noted that the superconducting interconnection structure in the embodiment of the present application can be prepared by the above-mentioned embodiment of the preparation method of the superconducting interconnection structure. In the embodiment of the present application, the superconducting connection element 5C that completely fills the through hole 3C is less likely to produce void defects, which helps to improve the reliability and yield of the superconducting interconnection structure.

In some embodiments, there are no void defects such as voids inside the superconducting connection element 5C. In other embodiments, there is no oxide impurity inside the superconducting connection element 5C. In one embodiment, the diameter of the through hole 3C is ≥50 microns.

In some embodiments, the superconducting connection element 5C is a material that exhibits superconducting properties at a temperature equal to or lower than the critical temperature, such as aluminum, niobium, indium, and the like. The specific implementation is not limited to these types, and any material that exhibits superconducting properties at a temperature equal to or lower than the critical temperature can be used.

In some embodiments, a first superconducting circuit is formed on the first surface 21C of the substrate 2C, a second superconducting circuit is formed on the second surface 22C of the substrate, and the through hole 3C penetrates the first superconducting circuit. a table surface 21C and the second surface 22C, and the first superconducting circuit and the second superconducting circuit are connected through the superconducting connection element 5C. In one embodiment, the first superconducting circuit is a qubit, the second superconducting circuit is a read resonant cavity, and the qubit and the read resonant cavity correspond one to one. Exemplarily, the qubit includes a capacitor and a superconducting quantum interference device connected in parallel with the capacitor.

A superconducting quantum interferometer consists of Josephson junctions connected in parallel. A Josephson junction connected in parallel can be composed of two Josephson structures connected in parallel, that is, a superconducting ring formed by a Josephson junction. The Josephson junction is a tunnel junction, point contact, or other structure exhibiting the Josephson effect. In some embodiments, each Josephson junction is a stacked structure of a superconducting layer-insulating layer-superconducting layer, and a first layer of superconducting material may be deposited to form the first superconducting layer of the Josephson junction, and then the first layer Partial areas of the superconducting layer are oxidized to form an insulating layer, and a second layer of superconducting material is deposited to form the second superconducting layer of the Josephson junction, thereby obtaining a stacked structure of superconducting layer-insulating layer-superconducting layer.

The fabrication of a superconducting interconnect structure provided by embodiments of the present application may require deposition of one or more materials, such as superconducting materials, dielectrics and/or metals. Depending on the materials selected, these materials may be deposited using deposition processes such as chemical vapor deposition, physical vapor deposition (eg, evaporation or sputtering), or epitaxial techniques, as well as other deposition processes. The fabrication process of a superconducting interconnect structure described in embodiments of the present application may require the removal of one or more materials from the device during the manufacturing process. Depending on the material to be removed, the removal process may include, for example, wet etching techniques, dry etching techniques, or lift-off processes. Materials forming circuit elements described herein may be patterned using known lithographic techniques (eg, photolithography or electron beam exposure).

Figure 15 is a flow chart of steps of a method for preparing a superconducting interconnect structure according to an embodiment. 16 is a schematic diagram of blind holes filled with molten superconducting material according to an embodiment. Figure 17a is a schematic diagram before substrate thinning according to an embodiment. Figure 17b is a schematic diagram of the substrate after thinning according to an embodiment.

As shown in Figure 15, Figure 16, Figure 17a and Figure 17b, a method for preparing a superconducting interconnect structure includes steps S101D to S103D, wherein:

Step S101D: Form a blind hole 13D on the substrate 1D. The substrate 1 may be made of undoped single crystal silicon, impurity-doped single crystal silicon, high-resistance silicon, etc. As an example, the substrate 1D is made of single crystal silicon material. In this embodiment, the blind hole 13D is formed by etching the substrate 1D. The substrate 1D can have a first surface 11D and a second surface 12D, and the first surface 11D can be dry etched or wet etched to obtain the blind hole 13D, such as using reactive ion etching (RIE), Inductively coupled plasma etching (Inductively Coupled Plasma, ICP), high density plasma etching (High Density Plasma Etch, HDPE), deep reactive ion etching (Deep Reactive Ion Etching, DRIE) and other methods. The mask involved in the etching process can be a soft mask, such as a mask formed by AZ4620, AZ9260, etc., or a hard mask, such as a mask formed by Si compounds such as SiO ₂ , SiNx, amorphous silicon, or It is a mask formed by metals and other solid compounds.

Step S102D: Fill the molten superconducting material into the blind hole 13D to form a superconducting element 22D. The heated and melted superconducting material forms molten droplets 21D. The molten droplets 21D can be filled into the blind hole 13D through a needle or the like to form a superconducting element 22D defined by the shape of the blind hole 13D. For example, the molten droplets 21D can be filled into the blind hole 13D at a speed of 150 drops to 200 drops per second.

Step S103D: The substrate 1D is thinned by chemical mechanical grinding and polishing on one side of the bottom of the blind hole 13D. The thinned substrate 1D forms a through hole penetrating the substrate 1D.

This application first forms a blind hole 13D on the substrate 1D, then fills the molten superconducting material into the blind hole 13D to form a superconducting element 22D, and then thins the liner on one side of the bottom of the blind hole 13D. The bottom 1D is formed so that the blind hole 13D forms a through hole penetrating the substrate 1D, thereby obtaining a superconducting interconnection structure penetrating the substrate 1D. Based on the superconducting interconnection structure, the surfaces of the substrate 1D at both ends of the through hole can be circuit interconnections. According to one embodiment, the method of filling the blind hole 13D with molten superconducting material and then thinning it is short, time-consuming and highly efficient, which is helpful for rapid preparation of TSV-based superconducting interconnection structures.

As will be understood by those skilled in the art, although in portions of this application, including the accompanying drawings, blind via 13D is depicted as being on the top surface of substrate ID, the thinned surface is on the bottom surface of substrate ID surface, but the top and bottom surface selections are relative and can be adjusted as needed.

Figure 18 is a schematic diagram of an adhesive wetting layer formed on the inner wall of a blind hole provided by an embodiment of the present application.

Referring to FIG. 18 , combined with FIG. 15 , FIG. 16 , FIG. 17 a and FIG. 17 b , in some embodiments, before the step of filling the molten superconducting material into the blind hole 13D, it also includes: An adhesive wetting layer 3D is formed on the inner wall of the blind hole 13D to enhance the adhesive adhesion of the molten superconducting material to the hole wall. This ensures good adhesion of the superconducting material to the sidewalls, thus avoiding void defects. Optionally, this can also act as a barrier to diffusion and infiltration. The adhesive wetting layer 3D can be made of a material that forms good contact with the substrate 1D and can block the diffusion of the superconducting material. In some examples, when the superconducting material is indium In, the adhesion wetting layer 3D includes: a first material layer 31D adhering to the inner wall; and a second material layer adhering to the first material layer 31D. 32D. The constituent materials of the first material layer 31D and the substrate 1D have good adhesion properties. The second material layer 32D forms infiltration with the superconducting material indium In and effectively blocks the diffusion of indium In. The two material layers help improve the adhesion of the superconducting material to the side walls and block the diffusion of the superconducting material. For example, the first material layer 31D includes titanium Ti or nickel Ni, and the second material layer 32D includes gold Au or copper Cu.

Figure 19 is a schematic diagram of substrate heating provided by an embodiment of the present application.

Referring to Figure 19 and combined with Figure 16, in some embodiments, when filling the molten superconducting material into the blind hole 13D, it also includes: heating the substrate 1D to the superconducting above the melting point of the conductive material. For example, the substrate 1D can be placed on a heating plate 4D and heated to above the melting point of the superconducting material, so that the molten droplets 21D filled by multiple injections can fuse with each other, eliminate pores, and achieve a good filling effect;

In some embodiments, the step of filling the molten superconducting material into the blind hole 13D includes: forming the superconducting material into particles; separately melting the particles to form molten droplets 21D and filling them in The blind hole 13D. For example, as shown in FIG. 16 and FIG. 19 , the spherical superconducting material is heated and sprayed particle by particle by the filling device. For example, spherical superconducting material is transported to the injection channel port one by one. Then, a heat source such as a laser can be used to heat and melt the spherical superconducting material located at the mouth of the injection channel to form molten droplets 21D. The molten droplets 21D can pass through the injection channel opening and be filled into the blind hole 13D. The diameter of the particle spherical shape is larger than the diameter of the injection channel opening. Therefore, the particle spherical superconducting material cannot pass through the injection channel opening before being heated and melted. For example, in the embodiment of the present application, each particle of spherical superconducting material can be heated, melted, and filled in the blind holes 13D in sequence at a certain speed. In the embodiment of the present application, the granular spherical superconducting material is heated by the laser to form molten droplets 21D when it is about to be filled into the blind hole 13D, which reduces the duration of being melted and helps prevent oxidation, adhesion and carrying of impurities. wait. The diameter of the spherical particles ranges from 40um to 100um. During implementation, the diameter may be smaller than the diameter of the blind hole 13D. The superconducting material is a material that exhibits superconducting properties at a temperature equal to or lower than the critical temperature, including indium In, tin Sn, lead Pt, indium tin alloy, etc. For example, one of the above and a combination thereof may be used. The specific implementation is not limited to these types, and any material that exhibits superconducting properties at a temperature equal to or lower than the critical temperature can be used.

In some embodiments, the blind hole 13D is filled with molten superconducting material in an oxidation resistant environment.

In one embodiment, the molten superconducting material is filled into the blind hole 13D in a vacuum environment to avoid oxidation during the heating and melting process of the superconducting material and affecting the filling effect. For example, molten superconducting material can be filled into the blind hole 13D in a closed reaction chamber with a certain degree of vacuum. For example, the vacuum degree in the reaction chamber is greater than 10 ^-5 Pa and less than 10 ^-3 Pa.

In another embodiment, the blind hole 13D is filled with molten superconducting material in a non-oxidizing gas environment. For example, the non-oxidizing gas includes one of nitrogen N ₂ , hydrogen H ₂ , carbon monoxide CO, and formic acid vapor. The filling effect of blind hole 13D is directly related to the reliability and yield of TSV integration technology. For example, due to the presence of an oxide layer on the surface of the indium ball particles, the melting point is higher than the melting point of indium and is difficult to melt, resulting in the formation of voids in the superconducting element 22D and thus affecting the reliability and yield of the superconducting interconnect structure. Control the heating temperature in a reducing atmosphere such as H ₂ , CO, formic acid vapor, etc. to melt indium into droplets and fill them in the holes, avoiding the presence of indium oxide and helping to avoid the formation of cavities.

Referring to what is shown in Figure 20, combined with what is shown in Figures 15, 16, 17a, 17b, 18 and 19, another aspect of the present application provides a method for preparing a superconducting quantum circuit, including: according to the above The superconducting interconnection structure prepared by the preparation method of the superconducting interconnection structure; a first superconducting quantum circuit 5D is formed on the first surface 11D of the substrate 1D at one end of the through hole, and the first superconducting quantum circuit 5D is formed on the first surface 11D of the substrate 1D at one end of the through hole. The conductive subcircuit 5D is connected to one end of the superconducting element 22D; and a second superconducting quantum circuit 6D is formed on the third surface 14D of the substrate 1D at the other end of the through hole. The quantum circuit 6D is connected to the other end of the superconducting element 22D.

In some embodiments, the first superconducting quantum circuit 5D, the superconducting element 22D and the second superconducting quantum circuit 6D form one of the following structures: pulse control signal line, magnetic flux control signal Line, read signal line, read resonant cavity. The superconducting interconnection structure based on TSV can realize the cross-surface structure formation of pulse control signal lines, magnetic flux control signal lines, read signal lines, read resonant cavities and other structures. For example, pulse control signal lines, magnetic A part of any circuit structure among the pass control signal line, the read signal line, and the read resonant cavity is formed on the first surface 11D, and the other part is formed on the third surface 14D. Based on the circuit structure penetrating the first surface 11D and the third surface 14D, The superconducting interconnect structure connects the two parts to obtain a cross-surface structure.

In the description of this specification, reference to the terms "one embodiment," "some embodiments," "examples," or "specific examples" or the like means that a particular feature, structure, material, or characteristic is described in connection with the embodiment or example. Included in at least one embodiment or example of the invention. In this specification, the schematic expressions of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the specific features, structures, materials or characteristics described may be combined in any suitable manner in any one or more embodiments. Furthermore, those skilled in the art may join and combine the different embodiments or examples described in this specification.

The above are only preferred embodiments of the present invention and do not limit the present invention in any way. Any person skilled in the technical field who makes any form of equivalent substitution or modification to the technical solutions and technical contents disclosed in the present invention shall not deviate from the technical solutions of the present invention. The contents still fall within the protection scope of the present invention.

Claims

A method for preparing superconducting silicon wafers, which is characterized by including:

providing a silicon wafer having a through hole, the silicon wafer including a first surface and a second surface disposed oppositely;

Depositing a superconducting material from the first surface of the silicon wafer at a first temperature to plate a first layer of superconducting film on the first surface of the silicon wafer and the hole wall of the through hole;

Depositing a superconducting material from the second surface of the silicon wafer at a second temperature higher than the first temperature to plate a second layer of superconducting film on the second surface of the silicon wafer to be connected to the first layer of superconducting film The second layer of superconducting film.
The preparation method according to claim 1, wherein the first layer of superconducting film and the thickness of the second layer of superconducting film are the same.
The preparation method according to claim 1 or 2, characterized in that the first layer of superconducting film is obtained by atomic layer deposition or chemical vapor deposition.
The preparation method according to claim 3, characterized in that the second layer of superconducting film is obtained by magnetron sputtering or electron beam evaporation.
The preparation method according to claim 4, characterized in that the first temperature is lower than 50°C, and the second temperature is 300˜800°C.
The preparation method according to claim 3, characterized in that, before the step of depositing superconducting material from the second surface of the silicon wafer at the second temperature, the preparation method further includes:

Remove the oxide layer on the surface of the first layer of superconducting film located on the second surface of the silicon wafer.
The preparation method according to claim 6, characterized in that the oxide layer is removed by ion beam etching.
The preparation method according to claim 1, wherein the superconducting material includes at least one of aluminum, titanium nitride, indium, niobium, niobium nitride, and tantalum.
The preparation method according to claim 1, characterized in that the hole wall of the through hole is perpendicular or inclined relative to the first surface.
The preparation method according to claim 1, wherein providing the silicon wafer with through holes further includes:

Forming a first mask on the first surface and the second surface of the silicon wafer;

Patterning the first mask to obtain a first window and a second window, the first window is located on the first surface, and the second window is located on the second surface; and

Potassium hydroxide solution is used to etch the silicon wafer through the first window and the second window to obtain A through hole is obtained, the through hole includes a first partial through hole and a second partial through hole that are connected, and the first partial through hole is formed on the first surface, and the second partial through hole is formed on the second partial through hole. surface.
The preparation method according to claim 10, characterized in that the aspect ratio of the first part of the through hole and the second part of the through hole is ≥20:1.
The preparation method according to claim 10 or 11, characterized in that the angle between the side wall of the first partial through hole and the first surface and the angle between the side wall of the second partial through hole and the second The included angles on the surfaces are all between 52° and 54°.
A superconducting silicon wafer obtained according to the preparation method according to any one of claims 1 to 12.
A superconducting quantum device, characterized by comprising: the superconducting silicon wafer according to claim 13.