CN217182176U - Semiconductor structure and superconducting quantum device - Google Patents
Semiconductor structure and superconducting quantum device Download PDFInfo
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- CN217182176U CN217182176U CN202220774990.4U CN202220774990U CN217182176U CN 217182176 U CN217182176 U CN 217182176U CN 202220774990 U CN202220774990 U CN 202220774990U CN 217182176 U CN217182176 U CN 217182176U
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 42
- 239000000463 material Substances 0.000 claims abstract description 44
- 239000000758 substrate Substances 0.000 claims abstract description 43
- 239000002096 quantum dot Substances 0.000 claims description 7
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 5
- 229910052738 indium Inorganic materials 0.000 claims description 5
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 5
- 239000003990 capacitor Substances 0.000 claims description 4
- KWYUFKZDYYNOTN-UHFFFAOYSA-M Potassium hydroxide Chemical compound [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 abstract description 35
- 238000000034 method Methods 0.000 abstract description 23
- 238000005530 etching Methods 0.000 abstract description 22
- 238000002360 preparation method Methods 0.000 abstract description 8
- 238000000059 patterning Methods 0.000 abstract description 6
- 229910052710 silicon Inorganic materials 0.000 description 10
- 239000010703 silicon Substances 0.000 description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 238000001039 wet etching Methods 0.000 description 7
- 230000009286 beneficial effect Effects 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000009623 Bosch process Methods 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000009713 electroplating Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000001704 evaporation Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 229910052758 niobium Inorganic materials 0.000 description 2
- 239000010955 niobium Substances 0.000 description 2
- GUCVJGMIXFAOAE-UHFFFAOYSA-N niobium atom Chemical compound [Nb] GUCVJGMIXFAOAE-UHFFFAOYSA-N 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
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- 238000004080 punching Methods 0.000 description 1
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Abstract
The application discloses a preparation method of a semiconductor structure, the semiconductor structure and a superconducting quantum device, and belongs to the field of quantum information. The preparation method comprises the steps of firstly forming a first mask on the surface of a substrate, wherein the surface comprises a first surface and a second surface which are opposite, then patterning the first mask to obtain a first window and a second window, wherein the first window is positioned on the first surface, the second window is positioned on the second surface, and then etching the substrate through the first window and the second window by utilizing a potassium hydroxide solution to obtain through holes, wherein the through holes comprise a first part of through holes and a second part of through holes which are communicated, the first part of through holes are formed on the first surface, and the second part of through holes are formed on the second surface. In the through hole obtained by the application, the side wall of the first part of the through hole and the side wall of the second part of the through hole are inclined, so that the process of growing materials on the side walls to realize interconnection is facilitated.
Description
Technical Field
The present application relates to the field of quantum information, and in particular, to a method for manufacturing a semiconductor structure, and a superconducting quantum device.
Background
In order to achieve high-density connection, in a semiconductor device, circuits are often fabricated on the front and back surfaces of a substrate, and conductive Through holes are formed by punching and filling conductive materials on the substrate, so that the electrical connection between the front and back circuits can be interconnected in the shortest distance Through the substrate, which is an integrated technology based on Through Silicon Vias (TSV).
Conventional through-silicon-via structures are typically formed on semiconductor substrates having a standard thickness of 100 to 300 microns, typically by defining the through-silicon-via locations directly on the back surface of the wafer, and then removing the silicon by a plasma etch bosch process to obtain the through-silicon vias. However, the obtained through hole has steep side walls, and the steep through holes, especially deep steep through holes (for example, through holes formed on a semiconductor substrate with a standard thickness of more than 400 microns), are not convenient for subsequent processes of growing materials on the side walls, such as electroplating filling, and the like, thereby affecting the reliability of interconnection.
SUMMERY OF THE UTILITY MODEL
The application provides a preparation method of a semiconductor structure, the semiconductor structure and a superconducting quantum device, aiming at the problem that in the integration technology of Through Silicon Vias (TSV), the obtained side wall of the Through hole is steep and inconvenient for electroplating filling and other subsequent processes.
One embodiment of the present application provides a method of fabricating a semiconductor structure, the method comprising:
forming a first mask on a surface of a substrate, the surface comprising opposing first and second surfaces;
patterning the first mask to obtain a first window and a second window, wherein the first window is located on the first surface, and the second window is located on the second surface; and
and etching the substrate through the first window and the second window by using a potassium hydroxide solution to obtain through holes, wherein the through holes comprise a first part of through holes and a second part of through holes which are communicated, the first part of through holes are formed on the first surface, and the second part of through holes are formed on the second surface.
In the above manufacturing method, the first mask includes one of: SiO 2 2 、SiN x 、ITO。
According to the preparation method, the depth-to-width ratio of the first part of through holes and the second part of through holes is more than or equal to 20: 1.
According to the preparation method, the included angle between the side wall of the first part of through holes and the first surface and the included angle between the side wall of the second part of through holes and the second surface are both 52-54 degrees.
The preparation method as described above, further comprising: forming a superconducting material on the side wall of the first partial through hole; and forming a superconducting material on the side wall of the second part of through hole, wherein the superconducting material on the side wall of the second part of through hole is connected with the superconducting material on the side wall of the first part of through hole.
In the above method, the superconducting material is indium or titanium nitride.
Another embodiment of the present application provides a semiconductor structure, comprising:
a substrate comprising opposing first and second surfaces; and
and the through holes comprise a first part of through holes and a second part of through holes which are communicated, the first part of through holes are formed on the first surface, and the second part of through holes are formed on the second surface.
In the semiconductor structure, the aspect ratio of the first partial through hole and the second partial through hole is more than or equal to 20: 1.
In the semiconductor structure, an included angle between the sidewall of the first portion of through holes and the first surface and an included angle between the sidewall of the second portion of through holes and the second surface are both 52 ° to 54 °.
In the semiconductor structure, the sidewall of the first partial via and the sidewall of the second partial via are formed with the superconducting material interconnected.
In the semiconductor structure, the superconducting material is indium or titanium nitride.
A third embodiment of the present application provides a superconducting quantum device, including:
the semiconductor structure as described above; a first superconducting circuit formed on the first surface; and a second superconducting circuit formed on the second surface, and electrically connected to the first superconducting circuit through the superconducting material.
In the above superconducting quantum device, the first superconducting circuit is a qubit, the second superconducting circuit is a read resonant cavity, and the qubits correspond to the read resonant cavity one to one.
The superconducting quantum device as described above, the qubit comprising a capacitor and a superconducting quantum interferometer in parallel with the capacitor.
Compared with the prior art, this application is through forming first mask in the surface of substrate earlier, the surface includes relative first surface and second surface, and is graphical again first mask obtains first window and second window, just first window is located the first surface, the second window is located the second surface, then utilize potassium hydroxide solution to pass through first window with the etching of second window the substrate obtains the through-hole, the through-hole is including the first part through-hole and the second part through-hole of intercommunication, just first part through-hole is formed in the first surface, the second part through-hole is formed in the second surface. Because the wet etching of the potassium hydroxide solution has the characteristics of anisotropy and fixed etching inclination angle, after the patterning of the first mask is carried out on the relative first surface and the second surface, the potassium hydroxide solution is utilized to synchronously etch from the first surface and the second surface to form the first part through hole and the second part through hole respectively and realize penetration, the side wall of the first part through hole and the side wall of the second part through hole are ensured to be inclined at a certain angle relative to the surface where the side wall of the first part through hole and the side wall of the second part through hole are positioned, the formed through holes are prevented from appearing in a deep and steep shape, and the interconnection process of the side wall growth materials is facilitated.
Compared with the prior art, the substrate in the semiconductor structure provided by the application has the opposite first surface and second surface, the through holes comprise the first partial through holes and the second partial through holes which are communicated, the first partial through holes are formed in the first surface of the substrate, and the second partial through holes are formed in the second surface of the substrate. The semiconductor structure provided by the application has the advantages that the side wall of the first part of through hole and the side wall of the second part of through hole formed from two surfaces do not penetrate along an angle, but have a fixed inclination angle relative to the surface, and the side wall morphology is beneficial to realizing interconnection in the process of growing materials on the side wall.
Drawings
Fig. 1 is a flowchart illustrating steps of a method for fabricating a semiconductor structure according to an embodiment of the present disclosure;
fig. 2A to fig. 2C are schematic flow charts illustrating a method for fabricating a semiconductor structure according to an embodiment of the present disclosure;
fig. 3 is a schematic diagram of a semiconductor structure according to an embodiment of the present disclosure;
fig. 4 is a schematic structural diagram of a superconducting quantum device according to an embodiment of the present application.
Description of reference numerals:
1-a substrate, 11-a first surface, 12-a second surface,
2-first mask, 21-first window, 22-second window,
3-through hole, 31-first partial through hole, 32-second partial through hole,
41-a first quantum circuit, 42-a second quantum circuit,
51-a first layer of superconducting material, 52-a second layer of superconducting material.
Detailed Description
The embodiments described below with reference to the drawings are exemplary only for the purpose of explaining the present application and are not to be construed as limiting the present application.
The integrated technology based on Through Silicon Vias (TSV) enables the circuits on the front side and the back side of the substrate to be directly interconnected, greatly shortens the routing length, and reduces signal delay and loss.
Semiconductor substrates typically have a substantial thickness and, in the related art, vias are formed using a plasma etch Bosch process (Bosch process) which is capable of forming vertical vias having a relatively high aspect ratio. However, the via sidewalls are formed steep. Steep vias, especially deep steep vias formed on substrates with large thicknesses, make the subsequent process of growing material on the sidewalls of the vias quite difficult. In particular, the conformal coverage of the grown material, in turn, can easily lead to failure of the sidewall material layer, thereby affecting the interconnect characteristics of the overall TSV. Generally, the standard thickness of the semiconductor substrate for forming the through hole is between 100 micrometers and 300 micrometers, but for special requirements, the thickness of some semiconductor substrates generally needs to be more than 400 micrometers, so that how to avoid the influence of deep and steep through holes on subsequent processes such as electroplating filling and the like, and how to ensure the morphology of the side wall is beneficial to realizing interconnection of growth materials, and the like are urgently needed to be solved.
Fig. 1 is a flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of the present disclosure.
Fig. 2A to fig. 2C are schematic flow charts illustrating a method for fabricating a semiconductor structure according to an embodiment of the present disclosure.
As shown in fig. 1 and fig. 2, an embodiment of the present application provides a method for manufacturing a semiconductor structure, the method including steps S101 to S103, wherein:
step S101, forming a first mask 2 on a surface of a substrate 1, where the surface includes a first surface 11 and a second surface 12 opposite to each other, and the substrate 1 may be silicon.
Step S102, patterning the first mask 2 to obtain a first window 21 and a second window 22, where the first window 21 is located on the first surface 11 and exposes a partial region of the first surface 11, the second window 22 is located on the second surface 12 and exposes a partial region of the second surface 12, and the first window 21 and the second window 22 are symmetrically distributed to facilitate forming a through hole.
Step S103, etching the substrate 1 through the first window 21 and the second window 22 by using a potassium hydroxide solution to obtain a through hole 3, where the through hole 3 includes a first portion of through holes 31 and a second portion of through holes 32 that are communicated with each other, the first portion of through holes 31 is formed on the first surface 11, and the second portion of through holes 32 is formed on the second surface 12, it can be understood that the first portion of through holes 31 is formed by etching an exposed area of the first window 21, and the second portion of through holes 32 is formed by etching an exposed area of the second window 22.
Compared with the prior art, after the patterning of the first mask 2 is carried out on the first surface 11 and the second surface 12 which are opposite, the embodiment provided by the application utilizes the potassium hydroxide solution to synchronously etch the substrate 1 from the first surface 11 and the second surface 12 to form the first partial through hole 31 and the second partial through hole 32 respectively, and the potassium hydroxide solution wet etching has anisotropy and etched side wall inclination, so that the side wall of the first partial through hole 31 and the side wall of the second partial through hole 32 have fixed inclination angles relative to the surfaces where the side walls are located, the formed through holes are prevented from having deep and steep appearances, and the process of realizing interconnection on the side wall growth materials is facilitated.
In some embodiments of the present application, the first mask 2 comprises one of: SiO 2 2 、SiN x And ITO. Illustratively, SiNx is grown on a silicon substrate 1 by LPCVD to form a first mask 2, the whole surface of the substrate 1 is covered, photoresist is coated on the first mask 2, the first surface 11 and the second surface 12 of the substrate 1 are subjected to mask patterning by the photoresist, and etching of the substrate 1 is completed by potassium hydroxide solution, wherein in the specific implementation, the etching stop position can be controlled by adjusting the line width, the etching time and the like of the surface of the first mask 2. Illustratively, the mask may be patterned after development by using SPR955 photoresist in combination with a stepper tool to perform double-sided pattern exposure. Not limited thereto, SiO may be formed on the surface of the substrate 1 by other means 2 Or ITO as the first mask 2.
In other embodiments of the present application, the aspect ratio of the first partial through hole 31 to the second partial through hole 32 is greater than or equal to 20: 1. Illustratively, the maximum diameter of the through-holes formed in a silicon substrate having a standard thickness of 400 microns does not exceed 20 microns. With the increase of the thickness of the substrate 1, the advantage of the scheme is more obvious, the first surface 11 and the second surface 12 which are opposite to each other are etched by the potassium hydroxide solution in a wet method, the rate is high (the etching rate of Si in KOH solution with the concentration of 30% and the temperature of 70 ℃ is 35.7-37.4 mu m/H), the fixed etching angle can be ensured by the potassium hydroxide solution in the wet etching, and the side wall appearance obtained by simultaneously etching the two surfaces can avoid the condition of steep depth.
In some embodiments of the present application, an angle between a sidewall of the first partial through hole 31 and the first surface 11 and an angle between a sidewall of the second partial through hole 32 and the second surface 12 are both 52 ° to 54 °, and exemplarily, the included angle may be 52 °, 52.5 °, 53 °, 53.2 °, 53.5 °, 53.8 °, and 54 °.
In an embodiment of the present application, the preparation method further includes: evaporating along a direction perpendicular to the first surface 11, and forming a superconducting material on the sidewall of the first partial through hole 31 to obtain a first superconducting material layer 51; and evaporating along a direction perpendicular to the second surface 12, forming a superconducting material on the sidewall of the second partial through hole 32 to obtain a second superconducting material layer 52, and interconnecting the superconducting material on the sidewall of the second partial through hole 32 and the superconducting material on the sidewall of the first partial through hole 31, namely interconnecting the first superconducting material layer 51 and the second superconducting material layer 52. And E-Beam, ALD or other optical coating modes can be adopted during evaporation.
In an embodiment of the present application, the superconducting material is indium or titanium nitride, and may also be aluminum or niobium, and the implementation is not limited to these, and any material that exhibits superconducting characteristics at a temperature equal to or lower than the critical temperature may be used.
In an embodiment of the present application, a through hole is obtained by using a KOH wet etching method to etch the substrate 1 through the first window 21 and the second window 22, and the TSV through hole 3 is formed by using an automatic stop characteristic of a KOH wet etching (111) crystal plane, and the existence of the inherent included angle between the (111) crystal plane and the (100) crystal plane is helpful for obtaining the through hole 3 with a relatively fixed included angle between the sidewall and the surface. According to the embodiment of the application, the first part of through holes 31 and the second part of through holes 32 are formed by synchronously etching the first surface 11 and the second surface 12 through KOH wet etching, and the side walls are prevented from being penetrated at an angle by etching in two directions, so that the appearance of steep side wall morphology is avoided. Illustratively, because KOH etches Si with anisotropy and the etching angle is fixed, the embodiment of the application can adopt the etching in 30 percent KOH and a constant temperature of 70 ℃, the etching rate of Si in the solution is 35.7-37.4 mu m/H, and the line width can be controlled according to the angle, thereby controlling the size of the surface opening. The first partial through hole 31 formed on the first surface 11 and the second partial through hole 32 formed on the second surface 12 may be symmetrical, for example, symmetrical structures formed by simultaneous etching with KOH solution. In the embodiment of the present application, the diameter of the first partial through hole 31 and the diameter of the second partial through hole 32 are both maximized at the surface opening of the substrate 1.
Fig. 3 is a schematic view of a semiconductor structure according to an embodiment of the present disclosure.
Referring to fig. 3, and in conjunction with fig. 1 and 2A-2C, another embodiment of the present application provides a semiconductor structure comprising:
a substrate 1 comprising opposing first and second surfaces 11, 12, the substrate 1 may be silicon; and
and the through hole 3 comprises a first part of through hole 31 and a second part of through hole 32 which are communicated, the first part of through hole 31 is formed on the first surface 11, and the second part of through hole 32 is formed on the second surface 12.
In the embodiment of the present application, the first partial through hole 31 formed on the first surface 11 and the second partial through hole 32 formed on the second surface 12 may be symmetrical, for example, symmetrical structures formed simultaneously in the same process. In the through hole 3 formed on the substrate 1, the sidewall of the first partial through hole 31 and the sidewall of the second partial through hole 32 have a fixed inclination angle relative to the surface on which the sidewalls are located, and the sidewall morphology is helpful for realizing interconnection in a process of growing materials on the sidewalls. The semiconductor structure of the embodiment of the present application can be prepared by the above-mentioned semiconductor structure preparation method embodiment. In the embodiment of the present application, the diameter of the first partial through hole 31 and the diameter of the second partial through hole 32 are both maximized at the surface opening of the substrate 1.
In some embodiments of the present application, the aspect ratio of the first partial through hole 31 and the second partial through hole 32 is ≧ 20: 1, and for example, the maximum diameter of the through hole 3 is no more than 20 microns when the through hole 3 is formed on a silicon substrate with a standard thickness of 400 microns.
In other embodiments of the present application, an included angle between the sidewall of the first partial through hole 31 and the first surface 11 and an included angle between the sidewall of the second partial through hole 32 and the second surface 12 are both 52 ° to 54 °, and exemplarily, the included angle may be 52 °, 52.5 °, 53 °, 53.2 °, 53.5 °, 53.8 °, and 54 °. It should be noted that the steep through holes 3 are inconvenient for growing materials on the sidewall, and the included angle is controlled to be 52-54 degrees, so that materials can be grown on the sidewall by using E-Beam, ALD or other optical coating methods. For the substrate 1 with thicker thickness, the through hole 3 comprises a first partial through hole 31 and a second partial through hole 32 which are communicated, wherein the first partial through hole 31 is formed on the first surface 11, and the second partial through hole 32 is formed on the second surface 12, and the structural form avoids the steep morphology of the side wall, and is beneficial to growing materials on the side wall to realize the interconnection of the electrical structures on two sides of the through hole 3.
In some embodiments of the present application, the sidewalls of the first partial via 31 and the sidewalls of the second partial via 32 are formed with an interconnection of superconducting materials, for example, the first superconducting material layer 51 formed on the sidewalls of the first partial via 31 and the second superconducting material layer 52 formed on the sidewalls of the second partial via 32 are interconnected. In an embodiment of the present application, the superconducting material is indium or titanium nitride, and may also be aluminum or niobium, and the implementation is not limited to these, and any material that exhibits superconducting characteristics at a temperature equal to or lower than the critical temperature may be used.
Fig. 4 is a schematic structural diagram of a superconducting quantum device according to an embodiment of the present application.
Referring to fig. 4, in combination with fig. 1, 2A to 2C, and 3, a third embodiment of the present application provides a superconducting quantum device including: the semiconductor structure as described in the upper semiconductor structure embodiment; a first superconducting circuit 41 formed on the first surface 11; and a second superconducting circuit 42 formed on the second surface 12, and the second superconducting circuit 42 and the first superconducting circuit 41 are electrically connected by the superconducting material. The through holes in the semiconductor structure provided by the embodiment realize the extension and integration of the qubits, can support dense qubits, and relieve the congestion of interconnection. Here, it should be noted that: the embodiments of the superconducting quantum device have the same beneficial effects as the embodiments of the semiconductor structure, and therefore, the details are not repeated.
In some embodiments of the present application, the first superconducting circuit 41 is a qubit, the second superconducting circuit 42 is a read resonator, and the qubits 41 and the read resonators 42 are coupled in a one-to-one correspondence.
In some embodiments of the present application, the qubit 41 comprises a capacitance and a superconducting quantum interferometer (Squid) in parallel with the capacitance.
Compared with the prior art, the first mask 2 is formed on the surface of the substrate 1 firstly, the surface comprises the first surface 11 and the second surface 12 which are opposite to each other, the first mask 1 is patterned to obtain the first window 21 and the second window 22, the first window 21 is located on the first surface 11, the second window 22 is located on the second surface 12, the first window 21 and the second window 22 are etched by utilizing a potassium hydroxide solution, the substrate 1 is provided with the through hole 3, the through hole 3 comprises a first part through hole 31 and a second part through hole 32 which are communicated with each other, the first part through hole 31 is formed on the first surface 11, and the second part through hole 32 is formed on the second surface 12. According to the method, after the first mask 2 is patterned on the first surface 11 and the second surface 12 which are opposite to each other, the potassium hydroxide solution is used for synchronously etching the first surface 11 and the second surface 12 to form the first part of through holes 31 and the second part of through holes 32 respectively, the potassium hydroxide solution wet etching is anisotropic, and the etching angle is fixed, so that the side walls of the first part of through holes 31 and the second part of through holes 32 are inclined at a certain angle relative to the surface where the side walls are located, for example, the side walls are 52 degrees or 53 degrees relative to the surface where the side walls are located, the formed through holes are prevented from being in a deep and steep shape, and the process of realizing interconnection of growth materials on the side walls is facilitated. It should be noted that the etching from two directions avoids the sidewall from penetrating at an angle, which is helpful to improve the situation that the sidewall of the deep hole is not easy to grow material.
The construction, features and functions of the present application are described in detail in the embodiments illustrated in the drawings, which are only preferred embodiments of the present application, but the present application is not limited by the drawings, and all equivalent embodiments that can be modified or changed according to the idea of the present application are within the scope of the present application without departing from the spirit of the present application.
Claims (8)
1. A semiconductor structure, comprising:
a substrate comprising opposing first and second surfaces; and
and the through holes comprise a first part of through holes and a second part of through holes which are communicated, the first part of through holes are formed on the first surface, and the second part of through holes are formed on the second surface.
2. The semiconductor structure of claim 1, wherein an aspect ratio of the first partial via and the second partial via is greater than or equal to 20: 1.
3. The semiconductor structure of claim 1 or 2, wherein an included angle between the sidewall of the first portion of the via hole and the first surface and an included angle between the sidewall of the second portion of the via hole and the second surface are both 52 ° to 54 °.
4. The semiconductor structure of claim 3, wherein sidewalls of the first portion of the via and sidewalls of the second portion of the via are formed with an interconnecting superconducting material.
5. The semiconductor structure of claim 4, wherein the superconducting material is indium or titanium nitride.
6. A superconducting quantum device, comprising:
the semiconductor structure of any one of claims 4 or 5;
a first superconducting circuit formed on the first surface; and
a second superconducting circuit formed on the second surface, and the second superconducting circuit and the first superconducting circuit are electrically connected through the superconducting material.
7. The superconducting quantum device of claim 6, wherein the first superconducting circuit is a qubit, the second superconducting circuit is a read resonator, and the qubit and the read resonator are in one-to-one correspondence.
8. The superconducting quantum device of claim 7, wherein the qubit comprises a capacitor and a superconducting quantum interferometer in parallel with the capacitor.
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| CN115440653A (en) * | 2022-04-02 | 2022-12-06 | 合肥本源量子计算科技有限责任公司 | Preparation method of semiconductor structure, semiconductor structure and superconducting quantum device |
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| CN115440653A (en) * | 2022-04-02 | 2022-12-06 | 合肥本源量子计算科技有限责任公司 | Preparation method of semiconductor structure, semiconductor structure and superconducting quantum device |
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