WO2023185263A1 - 调制信号处理装置、方法、微控制器及电子设备 - Google Patents

调制信号处理装置、方法、微控制器及电子设备 Download PDF

Info

Publication number
WO2023185263A1
WO2023185263A1 PCT/CN2023/075170 CN2023075170W WO2023185263A1 WO 2023185263 A1 WO2023185263 A1 WO 2023185263A1 CN 2023075170 W CN2023075170 W CN 2023075170W WO 2023185263 A1 WO2023185263 A1 WO 2023185263A1
Authority
WO
WIPO (PCT)
Prior art keywords
value
register
data
modulation
bit
Prior art date
Application number
PCT/CN2023/075170
Other languages
English (en)
French (fr)
Inventor
邵旭东
虞少平
杨淞
熊建蓝
Original Assignee
浙江地芯引力科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from CN202210322921.4A external-priority patent/CN114500204B/zh
Priority claimed from CN202210338142.3A external-priority patent/CN114500201B/zh
Application filed by 浙江地芯引力科技有限公司 filed Critical 浙江地芯引力科技有限公司
Publication of WO2023185263A1 publication Critical patent/WO2023185263A1/zh

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B14/00—Transmission systems not characterised by the medium used for transmission
    • H04B14/02—Transmission systems not characterised by the medium used for transmission characterised by the use of pulse modulation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/02—Amplitude-modulated carrier systems, e.g. using on-off keying; Single sideband or vestigial sideband modulation
    • H04L27/06—Demodulator circuits; Receiver circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/10—Frequency-modulated carrier systems, i.e. using frequency-shift keying
    • H04L27/12—Modulator circuits; Transmitter circuits

Definitions

  • This application belongs to the field of electrical digital technology, and specifically relates to a modulated signal processing device, method, microcontroller and electronic equipment.
  • the Qi protocol is a "wireless charging" standard launched by the Wireless Power Consortium and is a general specification in the field of wireless charging.
  • data is transmitted from the power receiver to the power transmitter (RX to TX) using ASK (modulation) data
  • data is transmitted from the power transmitter to the power receiver (TX to RX) using FSK modulation) data.
  • RX can be electronic devices such as mobile phones, watches, tablets, etc.
  • TX can be electronic devices such as mobile power supplies and chargers.
  • the data processing of ASK data or FSK data on the above-mentioned TX device is controlled by MCU (MoneyWise Credit Union, microcontroller).
  • the PWM wave is generally controlled by the MCU and the signal carrier is output through the H-bridge circuit.
  • the FSK data is actually implemented by the MCU controlling the frequency of the PWM.
  • This application proposes a modulation signal processing device, method, microcontroller and electronic equipment.
  • the modulation signal processing device is integrated into a whole and can directly operate the PWM output timer and analog-to-digital converter of the microcontroller and has high compatibility. , high precision and easy implementation.
  • the first embodiment of the present application proposes a modulated signal processing device, applied to a microcontroller, including a first signal processing module and/or a second signal processing module, wherein:
  • the first signal processing module is connected to the analog-to-digital converter of the microcontroller, and is used to: receive the completion flag output by the analog-to-digital converter, and collect the conversion value output by the analog-to-digital converter, And generate corresponding bit data based on the total number of samples and the preset half-cycle value;
  • the second signal processing module is connected to the PWM output timer of the microcontroller, and is used for: converting the bit data into a modulated data packet that complies with the Qi protocol, and processing the data according to the modulated data packet and the preset Modulation configuration parameters, respectively calculate the reload value and the corresponding frequency modulation parameter of the PWM output timer, so that the PWM output timer outputs the corresponding pulse width modulation signal.
  • the first signal processing module includes a data sampling module and a data decoding module
  • the data sampling module receives the completion flag output by the analog-to-digital converter, collects the conversion value output by the analog-to-digital converter, and outputs the total number of recorded samples and the first interrupt flag;
  • the data decoding module receives the first interrupt flag and generates corresponding bit data according to the total number of received samples and the preset half-cycle value.
  • the data sampling module includes a logic circuit and a counter, and the counter is used to record the total number of samplings;
  • the logic circuit is used to generate a logic value according to the conversion value and a preset comparison value.
  • the logic value performs an edge jump, it triggers the output of the total number of sampling times, clears the total number of sampling times, and sends out the total number of sampling times. Describe the first interrupt flag.
  • the preset comparison value includes a reference value and a hysteresis value
  • the logic circuit includes a first logic circuit and a second logic circuit
  • the first logic circuit inputs the reference value, the hysteresis value and the logic value, and outputs an actual comparison value according to a preset logic condition;
  • the second logic circuit inputs the actual comparison value and the conversion value , and output the logical value;
  • the preset logical conditions include:
  • the actual comparison value is equal to the difference between the reference value and the hysteresis value; if the logic value is 0, the actual comparison value is equal to the reference value and the hysteresis value.
  • the data sampling module also includes a reference value register, a hysteresis value register, a count value output register, a logic value register and a first interrupt flag register, and stores the reference value and the hysteresis value respectively. , the total sampling times, the logic value and the first interrupt flag.
  • the data decoding module includes a computing unit, and the computing unit is based on Determine the number of captured half-cycles based on the total number of samplings, and calculate the corresponding bit data based on the number of half-cycles based on preset calculation rules;
  • the preset calculation rules include:
  • the number of half cycles is 3, it is determined that the corresponding number of bits when captured for the first time is a 0 and a 1, and the corresponding number of bits when captured next time is 0;
  • the data decoding module further includes a bit receiving state machine, and the computing unit sends the calculated bit data to the bit receiving state machine;
  • the bit receiving state machine performs format verification on the received bit data, stores the successfully verified bit data in the data cache register, and sets the validity flag and the second interrupt flag after the verification, and the When an error is detected, the validity flag is cleared, the second interrupt flag is set, and the bit reception state machine is reset.
  • the bit receiving state machine sequentially verifies each bit of data written, and sequentially verifies the starting bit, 8 bit values, parity value, and stop bit of the data packet. .
  • the data decoding module also includes a half-cycle value register, a count value receiving register, a validity flag register and a second interrupt flag register, respectively used to store the half-cycle value, the count value Receive, the validity flag and the second interrupt flag.
  • the second signal processing module includes a data packet construction module and a parameter calculation module, where:
  • the data packet constituting module converts the bit data to be sent into a modulated data packet that conforms to the Qi protocol, and sends the modulated data packet to the parameter calculation module;
  • the parameter calculation module calculates the reload value of the PWM output timer and the corresponding frequency modulation parameter respectively according to the modulation data packet and the preset modulation configuration parameter, so that the PWM output timer outputs the corresponding pulse width modulated signal.
  • the data packet construction module includes a data cache register, an interrupt register and a control register, where,
  • the data cache register stores data to be sent written by the microcontroller
  • the interrupt register stores the interrupt data written by the microcontroller and is used to mark the modulation data Completion of a single byte in a packet;
  • the control register stores control data written by the microcontroller and is used to control the opening and closing of the data packet constituting module, the transmission of bit data, and the format of the modulated data packet.
  • control register includes a startup enable register and a transmission enable register;
  • startup enable register stores the startup enable status value written by the microcontroller for controlling the data Opening and closing of package components;
  • the transmission enable register stores the transmission enable status value written by the microcontroller and is used to control the transmission of bit data.
  • the modulation data includes a boot preamble and at least one byte of bit data
  • the control register also includes a preamble number register
  • the preamble number register is in the sending enable state value.
  • each byte of bit data includes a start bit, a data body bit, a parity bit and a stop bit;
  • the control register also includes a parity control register, which stores the parity written by the microcontroller when the transmission enable status value is high and the data to be sent in the data cache register is empty.
  • the initial value of the parity check bit is used to control the initial value of the parity check bit.
  • the modulation data packet also includes padding data located at the end of the data packet, and the control register further includes a padding control register.
  • the transmission enable state value of the padding control register is When the level is low, the padding flag data written by the microcontroller is stored, which is used to mark whether to perform end padding.
  • the parameter calculation module includes a trigger period counter and a calculation sub-module
  • the frequency modulation parameters include a load setting value of the trigger period counter
  • the trigger period counter is based on the load setting. The value is counted, and if the count overflows, the calculation sub-module is triggered to perform calculation;
  • the calculation sub-module After the calculation sub-module is triggered, it calculates the reload value and the corresponding load setting value of the PWM output timer according to the modulation data packet and the preset modulation configuration parameters, and calculates the load setting value. is sent to the trigger cycle counter, and the reload value is sent to the PWM output timer.
  • the calculation sub-module includes a configuration register and a calculation unit.
  • the configuration register includes a period number register, a period difference register, a base frequency register, a modulation degree register and a polarity selection register;
  • the modulation configuration parameters include the number of modulation cycles, the modulation cycle difference, and the set fundamental frequency respectively stored in the cycle number register, the cycle difference register, the fundamental frequency register, the modulation degree register, and the polarity selection register. , modulation degree and modulation polarity.
  • the calculation sub-module also includes an intermediate variable register.
  • the calculation unit calculates the logic value corresponding to the bit data to be sent based on the modulation polarity, and writes the logic value into the
  • the intermediate variable register records the logic level of the output frequency
  • the reload value and the load setting value corresponding to the logic value under the corresponding modulation polarity are calculated.
  • An embodiment of the second aspect of the present application provides a modulated signal processing method, which method includes:
  • Receive the completion flag output by the analog-to-digital converter collect the conversion value output by the analog-to-digital converter, and generate corresponding bit data based on the total number of samples and the preset half-cycle value; and/or,
  • the embodiment of the third aspect of the present application provides a microcontroller, on which the modulation signal processing device described in the first aspect is integrated.
  • the embodiment of the fourth aspect of the present application provides an electronic device, including a memory, a processor, and a computer program stored on the memory and executable on the processor, and further includes a digital logic circuit, the digital logic circuit
  • the circuit includes a modulated signal processing device as described in the first aspect.
  • the modulated signal processing device is applied to a microcontroller and includes a first signal processing module and/or a second signal processing module.
  • the first signal processing module is connected to the analog-to-digital converter of the microcontroller, Used for: receiving the completion flag output by the analog-to-digital converter, collecting the conversion value output by the analog-to-digital converter, and generating corresponding bit data according to the total number of samples and the preset half-cycle value.
  • the second signal processing module is connected to the PWM output timer of the microcontroller, and is used to: convert the bit data into a modulation data packet that complies with the Qi protocol, and configure the modulation parameters according to the modulation data packet and the preset modulation configuration parameters.
  • the module parameters can be configured to adapt to the modulation signal processing of most protocols on the market.
  • the modulated signal processing device is a hardware peripheral, and its sending and receiving timing is not affected by the software interrupt time. The processing of numbers will be more efficient, accurate and convenient.
  • the hardware circuit design of the device is relatively simple and easy to design and implement (can be realized by directly operating the PWM output timer and analog-to-digital converter of the microcontroller); when applying the software, only some simple operations are needed to complete the data transmission. , saving MCU computing resources.
  • this device can take into account the advantages of software and hardware, and can send data more efficiently, accurately and conveniently while ensuring its flexibility.
  • Figure 1 shows a schematic framework structure diagram of a modulated signal processing device provided by an embodiment of the present application.
  • Figure 2 shows a schematic framework structure diagram of the first signal processing module provided by the embodiment of the present application
  • Figure 3 shows a schematic diagram of bit "0" and bit “1" output in the embodiment of the present application
  • Figure 4 shows a schematic diagram of the time difference in the prior art
  • Figure 5 shows a schematic diagram of the execution logic of the data collection module provided by the embodiment of the present application.
  • Figure 6 shows a schematic diagram of the corresponding relationship between the reference value, the hysteresis value and the count value
  • Figure 7 shows a schematic diagram of the data structure of the Qi protocol in the embodiment of the present application.
  • Figure 8 shows a schematic diagram of the correspondence between bit data and the number of half cycles
  • Figure 9 shows a schematic execution logic diagram of the data decoding module provided by the embodiment of the present application.
  • Figure 10 shows a schematic diagram of the working process of the bit state machine
  • Figure 11 shows a schematic diagram of the frame structure of the second signal processing module provided by the embodiment of the present application.
  • Figure 12 shows a schematic diagram of the application of the second signal processing module in the PWM output timer provided by the embodiment of the present application
  • Figure 13 shows a schematic data structure diagram of the FSK data of the Qi protocol in the embodiment of the present application
  • Figure 14 shows a schematic execution logic diagram of the second signal processing module provided by the embodiment of the present application.
  • Figure 15 shows a schematic diagram of the corresponding relationship between the execution logic and the data structure of the second signal processing module provided by the embodiment of the present application;
  • Figure 16 shows a schematic structural diagram of the parameter calculation module provided by the embodiment of the present application.
  • Figure 17 shows a schematic diagram of bit "0" and bit "1" output in the embodiment of the present application.
  • Figure 18 shows a schematic flowchart of the modulated signal processing method provided by the embodiment of the present application.
  • Comparator scheme first convert the ASK signal into an envelope signal through the envelope detection circuit, then convert the envelope signal into a logic signal through the filter circuit and comparator, and count the duration through edge interrupt and timer, and then through The MCU software decodes the data based on the duration count, and then receives the decoded data packet through the software.
  • the voltage sampling scheme is similar to the above comparator scheme, but the difference is that a filter amplification circuit is used to generate a logic signal.
  • the current sampling scheme is similar to the above comparator scheme. The difference is that a coil is used for current sampling and a differential amplifier circuit is used to generate a logic signal.
  • ADC Analog to Digital Converter
  • the comparator solution has low demand for MCU computing resources and requires the MCU to have built-in comparator peripherals, and the parameters of the comparator are difficult to adjust through software configuration; the voltage and current sampling solutions have low demand for MCU computing resources and require operational amplifiers. Or a dedicated highly integrated power management chip.
  • the ADC sampling scheme is directly implemented by software. It does not require peripheral circuits to convert "logical signals" or other chips. It is easy to adjust parameters through software.
  • this part of the high-frequency trigger operation requires a lot of program time to execute, which requires MCU computing resources. Extremely high.
  • the data decoding part in each solution is the same and can be used as a general module to reduce the occupation of MCU computing resources.
  • the software receiving part requires programs based on different wireless protocols. Execution, it cannot be made into a general module.
  • this embodiment provides a modulated signal processing device, method, microcontroller and electronic equipment, wherein the modulated signal processing device is applied to the microcontroller and can be used to receive analog-to-digital conversion from the microcontroller.
  • the completion flag of the converter output and collects the conversion value output by the analog-to-digital converter, and generates corresponding bit data based on the total number of samples and the preset half-cycle value; and/or is used to convert the bit data into modulation that complies with the Qi protocol data packet, and calculate the reload value and corresponding frequency modulation parameter of the PWM output timer respectively according to the modulation data packet and the preset modulation configuration parameters, so that the PWM output timer outputs the corresponding pulse width modulation signal.
  • the module parameters can be configured to adapt to the modulation signal processing of most protocols on the market.
  • the modulation signal processing device serves as a hardware peripheral, and its transmission and reception timing is not affected by software interruption time. Signal processing will be more efficient, accurate and convenient.
  • the hardware circuit design of the device is relatively simple and easy to design and implement (can be realized by directly operating the PWM output timer and analog-to-digital converter of the microcontroller); when applying the software, only some simple operations are needed to complete the data transmission. , saving MCU computing resources.
  • this device can take into account the advantages of software and hardware, and can send data more efficiently, accurately and conveniently while ensuring its flexibility.
  • the half-cycle value can be understood as a sampling value that can represent the half-cycle duration.
  • the preset half-cycle value in this embodiment can be any value. Those skilled in the art can make specific settings according to the actual situation. This embodiment does not make specific settings. limited.
  • Modulation configuration parameters can include any parameters that need to be configured in the signal modulation process, including but not limited to the number of modulation cycles, modulation cycle difference, and settings stored in the cycle number register, cycle difference register, fundamental frequency register, modulation degree register, and polarity selection register respectively.
  • the fundamental frequency, modulation degree, modulation polarity, etc. can be pre-calculated through the MCU and configured into registers.
  • the preset modulation configuration parameters in this embodiment The configuration parameters can be any of the above, and those skilled in the art can make specific settings according to actual conditions, and are not specifically limited in this embodiment.
  • the modulated signal processing device can realize the above-mentioned “receiving the completion flag of the analog-to-digital converter output of the microcontroller, and collecting the conversion value of the analog-to-digital converter output, and based on the total number of samples and the preset half cycle Value generation corresponding bit data” function, and the above-mentioned “convert bit data into modulation data packets that comply with the Qi protocol, and calculate the reload value and the PWM output timer respectively according to the modulation data packets and preset modulation configuration parameters.
  • “Corresponding frequency modulation parameters, so that the PWM output timer outputs the corresponding pulse width modulation signal” function can also be used to implement the above two functions, and this embodiment does not specifically limit this.
  • Figure 1 is a schematic diagram of the structure and application principle of a modulated signal processing device provided by an embodiment of the present application.
  • the modulated signal processing device is applied to a microcontroller and may include a first signal processing module and/or a third signal processing module. 2.
  • Signal processing module is connected to the analog-to-digital converter of the microcontroller, and is used for: receiving the completion flag output by the analog-to-digital converter, and collecting the conversion value output by the analog-to-digital converter, and based on the total number of samples and the predetermined value. Assume that the half-cycle value generates corresponding bit data.
  • the second signal processing module is connected to the PWM output timer of the microcontroller and is used to: convert bit data into modulation data packets that comply with the Qi protocol, and calculate the PWM output timing respectively based on the modulation data packets and preset modulation configuration parameters. The reload value of the device and the corresponding frequency modulation parameter, so that the PWM output timer outputs the corresponding pulse width modulation signal.
  • the first signal processing module can be used as an independent hardware peripheral of the analog-to-digital converter, integrated in the MCU, and used in the ASK data decoding process, so that the ASK data decoding process is changed from software implementation to hardware implementation.
  • the ASK data The decoding device can collect the conversion value output by the analog-to-digital converter after receiving the completion flag output by the analog-to-digital converter, and generate corresponding bit data based on the total number of samples and the preset half-cycle value to implement ASK data decoding. And compared with software implementation solutions, the sending and receiving timing of this hardware peripheral is not affected by software interrupt time, and the decoding process will be more efficient, accurate and convenient.
  • the logic of the device is simple, and the design of the required hardware circuits is usually relatively simple. It can be implemented by directly operating the registers of the ADC peripherals; when used in software applications, only some simple operations are needed to complete the ASK data decoding, thus freeing up the memory in the MCU. A large amount of software computing resources are occupied.
  • the second signal processing module can be used for the control process of FSK data transmission and can be used as an independent hardware peripheral of the PWM output timer. Functionally, it is a data communication interface module integrated into the MCU, thereby releasing a large amount of software computing resources in the MCU. Occupied, the bit data to be sent can be converted into Qi-compliant The modulation data packet of the protocol, and calculate the reload value of the PWM output timer and the corresponding frequency modulation parameter respectively according to the modulation data packet and the preset modulation configuration parameters, so that the PWM output timer outputs the corresponding pulse width modulation signal, In this way, the module parameters can be configured to adapt to the FSK transmission control of most protocols on the market.
  • the sending and receiving timing of this hardware peripheral is not affected by software interrupt time, and the control will be more accurate.
  • the logic of the device is simple, and the design of the required digital logic circuits is usually relatively simple and easy to design and implement.
  • Figure 2 is a schematic structural diagram of a first signal processing module provided by an embodiment of the present application.
  • the first signal processing module is applied to a microcontroller and is connected to an analog-to-digital converter of the microcontroller.
  • data sampling module if receiving the completion flag output by the analog-to-digital converter (i.e., ADC interrupt flag), collects the conversion value output by the analog-to-digital converter, and outputs the total number of recorded samples and the first interrupt flag
  • data The decoding module if receiving the first interrupt flag, generates corresponding bit data according to the total number of samples received and the preset half-cycle value.
  • the first signal processing module is used as an independent hardware peripheral, and the implementation method is similar to the receiving part of the I2C peripheral, that is, the MCU writes the register through the bus, configures the sending parameters, writes the data cache, and responds to interrupts Request, etc., the ASK hardware peripheral module directly operates the register of the ADC peripheral.
  • the data sampling module is mainly responsible for converting the analog voltage signal on the coil into logic level data (ie, demodulation).
  • the data decoding module is mainly responsible for receiving the logic level duration parameter (which can be output by the data sampling module of this embodiment, or obtained by the software in other ways), decoding the bytes, and outputting them to the software.
  • the MCU receives the edge interrupt of the logic signal and then obtains the time difference through the counter. For example, setting the timer counting frequency to 1MHz means The period is 1us (the first parameter). If the read " ⁇ Count" value is 250 (the second parameter), as shown in Figure 4, the time difference of 250us (the third parameter) is calculated. No. The three parameters are equal to the first parameter multiplied by the second parameter. The first parameter is selected by the timer in combination with the usage scenario; the third parameter is determined by the actual communication protocol and is affected by fluctuations in wireless reception communication quality.
  • the data sampling module can receive After reaching the completion mark of the analog-to-digital converter output, collect the conversion value of the analog-to-digital converter output, and record the total number of sampling times. Combined with the frequency of the ADC trigger conversion, the corresponding logic level duration data can be determined. For example, the frequency of the logic signal is 4KHz (changes 4,000 times in one second), and the conversion value sampling frequency is set to 8 times the frequency of the logic signal, that is, 32KHz (sampling 32,000 times in one second).
  • the ADC can sample 8 times. That is to say, in theory, the ADC can continuously sample a voltage higher than Vref 8 times, and then continuously sample a voltage lower than Vref 8 times.
  • the number of sampling times (Count value) is used to record the number of times the same voltage is continuously sampled. Based on the sampling frequency, the length of time for the voltage change of this section of the envelope signal line can be calculated (equal to the third parameter mentioned above).
  • the data sampling module includes a logic circuit and a counter, and the counter is used to record the total number of sampling times.
  • the logic circuit is used to generate a logic value based on the conversion value and the preset comparison value.
  • the logic value performs an edge jump, it triggers the output of the total number of sampling times, clears the total number of sampling times, and issues the first interrupt flag.
  • the function implementation of the data sampling module takes the "conversion value” and "completion flag (ie, timer interrupt)" output by the ADC peripheral as inputs. Once the timer interrupts, the data sampling module is triggered to run once. After the total number of sampling times is output, clear the total number of sampling times to prepare for the next sampling record. Issuing the first interrupt flag can trigger the above-mentioned data decoding module to perform data decoding.
  • the output of the total number of samples is triggered when the logic value makes an edge jump. It can be the output of the total number of samples triggered by the logic value on the rising edge, or the output of the total number of samples triggered by the logic value on the falling edge. As long as the same operation is performed each time It can only be triggered when the edge of the direction jumps.
  • the preset comparison value may include a reference value and a hysteresis value.
  • the logic circuit includes a first logic circuit and a second logic circuit; the first logic circuit inputs a reference value, a hysteresis value and a logic value, and outputs an actual comparison value according to a preset logic condition; the second logic circuit inputs an actual comparison value. Compares and converts values, and outputs logical values.
  • the above-mentioned preset logic conditions include: if the logic value is 1, the actual comparison value is equal to the difference between the reference value and the hysteresis value; if the logic value is 0, the actual comparison value is equal to the sum of the reference value and the hysteresis value.
  • the first logic circuit can be any circuit that can realize the above logical conditions, and this embodiment does not specifically limit its specific circuit structure.
  • the second logic circuit can be a comparator circuit, the positive input of which is the above-mentioned switching Change the value, the negative input is the above actual comparison value, and the output is the above logical value.
  • the middle one is the base voltage, that is, the reference value.
  • the upper and lower horizontal lines are used to define the hysteresis interval.
  • the hysteresis value that is, the middle base voltage, corresponds to the upper and lower horizontal lines respectively.
  • the absolute value of the difference in voltage That is, the reference value Vref is the center value of comparison, and the hysteresis value delt is the positive and negative difference, both configured by the MCU software.
  • the data sampling module also includes a reference value register, a hysteresis value register, a count value output register, a logic value register, a first interrupt flag register, a module enable register, etc., and stores the reference value, hysteresis value, and total sampling times respectively. , logic value, first interrupt flag and enable status value (usually a logic value of 0 or 1).
  • the data sampling module takes the "conversion value” and "completion flag” output by the ADC peripheral as input. Each time it receives the completion flag, it changes the value of the module enable register to the enable state value, triggering the module to run once. Each time sampling is performed, the "count value” of the counter is automatically increased by 1.
  • the above reference value and hysteresis value can generate an actual comparison value after passing through the first logic circuit, which is used to compare with the conversion value. Based on the comparison result and the comparison circuit, the logic value logic can be generated and written into the logic value register to reflect the "logic "Signal" transition, this logic value logic can affect the positive and negative hysteresis value delt to react on the actual comparison value.
  • the "count value” of the counter can be output to the count value output register, and then the count value is cleared to zero and the interrupt is set (the first interrupt flag is set)
  • the register value is written as 1).
  • the subsequent data decoding module reads the total number of samples in the count value output register, it clears the count value output register, that is, writes the value of the count value output register as 0.
  • the data decoding module includes a calculation unit that determines the number of captured half-cycles based on the total number of samples, and calculates corresponding bit data based on the number of half-cycles based on preset calculation rules.
  • each data packet usually includes a starting preamble, N bytes and a padding bit 1 at the end.
  • Further analysis according to the rules of the Qi protocol shows: when the data bit is "1", the edge changes twice in one cycle, and the edge direction does not change at the end of the cycle; when the data bit is "0”, the edge changes once in one cycle, and the cycle The edge direction changes at the end. When the second data bit is "0", the edge direction changes back.
  • This embodiment uses half-cycle as the unit and uses single-edge counting judgment, which is more efficient and saves resources compared with double-edge counting judgment.
  • the captured half-cycle value possibilities include the following situations:
  • the above-mentioned preset calculation rules include: if the number of half-cycles is 2, determine the corresponding number of bits to be 1; if the number of half-cycles is 3, determine the number of corresponding bits when first captured to be a 0 and a 1. 1. The corresponding number of bits when captured next time is 0; if the number of half-cycles is 4, determine the corresponding number of bits to be two 0s; if the number of half-cycles is greater than 4, determine a timeout, packet transmission error, or Finish.
  • the data decoding module also includes a bit receiving state machine, and the calculation unit sends the calculated bit data to the bit receiving state machine; the bit receiving state machine performs format verification on the received bit data, and The bit data that is successfully verified is stored in the data cache register, and the validity flag and the second interrupt flag are set after the verification is completed. When the verification is incorrect, the validity flag is cleared, the second interrupt flag is set, and the reset bit is set. Receive state machine.
  • the data decoding module also includes a half-cycle value register, a count value receiving register, a validity flag register, and a second interrupt flag register, which are respectively used to store the half-cycle value, count value reception, validity flag, and second interrupt flag.
  • the "first interrupt flag" of the data sampling module can trigger the data decoding module (if the module is used independently and written directly by the software) to decode the data. Each time it is triggered, the module runs once. Then, according to the "half-cycle value” configured by the software (the configuration requires the period value to be an even number), based on the above-mentioned preset calculation rules, the total number of input samples (Count) can be calculated corresponding to the number of captured half-cycles, and the corresponding Write the corresponding bit data "0" or bit data "1” to the bit receiving state machine (specifically as shown in Figure 8 shown).
  • the bit receiving state machine can verify each bit of data written, and sequentially verify the starting bit, 8 bit values and parity check value of the data packet, and the termination bit. Then, the bit receiving state machine writes the successfully verified bit data into the data cache register (Buff), and sets (writes 1 in the register) the validity flag register and the second interrupt flag register.
  • the second signal processing module is applied to the PWM output timer of the microcontroller and may include data.
  • Packet composition module and parameter calculation module among which: the data packet composition module converts the bit data to be sent into modulation data packets that comply with the Qi protocol, and sends the modulation data packet to the parameter calculation module; the parameter calculation module, according to the modulation data packet and the preset modulation configuration parameters, respectively calculate the reload value of the PWM output timer and the corresponding frequency modulation parameters, so that the PWM output timer outputs the corresponding pulse width modulation signal.
  • the second signal processing module can be set on the PWM output timer at the position shown in Figure 12. It is functionally equivalent to a data communication interface module and its implementation is similar to the I2C peripheral.
  • the MCU can write to the register of the second signal processing module through the bus, configure sending parameters, write data cache, respond to interrupt requests, etc.
  • the second signal processing module can directly operate the register of the timer.
  • the data packet composition module is mainly responsible for the protocol layer control of FSK communication, responsible for converting the data packets that the software needs to send into control parameters that comply with the Qi protocol, and transmitting the output results to the parameter calculation module.
  • the parameter calculation module is mainly responsible for the physical layer control of FSK communication.
  • the second signal processing module includes a data packet composition module and a parameter calculation module.
  • the data packet composition module can convert the bit data to be sent into a modulated data packet that complies with the Qi protocol, and send the modulated data packet to the parameter Compute module.
  • the parameter calculation module can calculate the reload value of the PWM output timer and the corresponding frequency modulation parameters respectively according to the modulation data packet and the preset modulation configuration parameters, so that the PWM output timer outputs the corresponding pulse width modulation signal. In this way, it can By configuring module parameters, it can adapt to the modulation signal processing of most protocols on the market. And compared with software implementation solutions, the sending and receiving timing of this hardware peripheral is not affected by software interrupt time, and the control will be more accurate.
  • the hardware circuit design of the device is usually relatively simple and easy to design and implement; when applying the software, only a few simple operations are needed to complete the data transmission, saving MCU computing resources.
  • this device can take into account the advantages of software and hardware, and can send data more efficiently, accurately and conveniently while ensuring its flexibility.
  • the data packet construction module may include a data cache register, an interrupt register, and a control register.
  • the data cache register stores the data to be sent written by the microcontroller;
  • the interrupt register stores the data written by the microcontroller.
  • Interrupt data is used to mark the completion of a single byte in the modulated data packet;
  • the control register stores the control data written by the microcontroller and is used to control the opening and closing of the data packet constituting modules, the transmission of bit data, and the format of the modulated data packet. .
  • This embodiment separates the data caching function from other MCU hardware by setting the above register.
  • the data caching register is used to cache the bit data to be sent, and the MCU only needs to perform a simple operation of sending data. , thereby saving the MCU needed to constitute the data packet It saves time and avoids blockage in program running, which can effectively reduce the occupation of MCU resources and facilitate the MCU to perform other functions, thus greatly improving its work efficiency.
  • the control register includes the start enable register and the send enable register (Send); the start enable register is used to store the start enable status value written by the microcontroller to control the opening and closing of the data packet module; the send enable register is used It is used to store the transmission enable status value written by the microcontroller to control the transmission of bit data.
  • the status value is usually a logical value of 1 or 0.
  • 1 is a high level, indicating that the control is on, that is, the data packet constituting module is turned on or can send data;
  • 0 is a low level, indicating that the control is off, that is, the data packet is formed.
  • the module is shut down or unable to send data.
  • the MCU When the data packet constituting module composes the data packet, the MCU first changes the enable state of the start enable register through the bus, starts the data packet constituting module, and then writes one byte of data to be sent to the data cache register (Buff) , and then set the send enable register (Send) so that the register value is equal to 1, and receive the bit data sent by the first signal processing module. Then the MCU continues to write to the control register through the bus, and can control the specific format of the data packet according to the preset data packet format.
  • the preset format data packet to be generated can be sent to the parameter calculation module bit by bit, and then the MCU continues to send interrupt data to the interrupt register (IT) through the bus, sets the interrupt flag to complete the interrupt IT, triggers the interrupt, and clears the enable status under hardware control value (clearing can be understood as making the register value equal to 0 and the control state is closed). If the data packet has not been sent completely, continue to write "Buff" and set it (setting it can be understood as making the register value equal to 1 and the control state is on) control register. If the sending is completed, it will not be executed.
  • the modulated data may include a boot preamble and at least one byte of bit data.
  • the control register also includes a preamble number register.
  • the status value of the preamble number register in the transmit enable register is rising. edge, and the data to be sent in the data cache register is empty, the preamble control data written by the microcontroller is stored, which is used to control the number of boot preamble bits to achieve flexible configuration of the boot preamble number, further improving the Flexibility and versatility of the second signal processing module.
  • the above-mentioned bit data of each byte includes a start bit, data body bit, parity bit and stop bit;
  • the control register also includes a parity control register.
  • the parity control register stores the initial parity value written by the microcontroller and is used to control the parity bit. The initial value is then configured to configure the data packet format, further improving the flexibility and versatility of the second signal processing module.
  • the modulated data packet also includes padding data located at the end of the data packet.
  • the control register also includes a padding control register. When the status value of the transmit enable register is low, the padding control register stores the padding flag written by the microcontroller. Data used to mark whether to perform end padding. In this way, writing the complement flag data when the status value of the transmission enable register is low level does not affect the transmission of bit data, and can further ensure the accuracy of the FSK data sent by the second signal processing module.
  • the bit filling flag data can also be a logic value of 1 or 0. 1 is a high level, indicating that bit filling is required; 0 is a low level, indicating that bit filling is not required.
  • this embodiment sets the above preamble numbers respectively.
  • the number register, the parity control register and the padding control register are configured so that the number of boot prologues, the initial value of the parity check, and whether to pad the bit "1" at the end can be configured, which can further improve the versatility of the second signal processing module.
  • the MCU writes a byte to be sent to the data cache register (Buff) through the bus, and then sets the send enable register so that the register value is equal to 1. Since data is not being sent at this time (the beginning of the data packet), you can add several bits “1” according to the configuration value, calculate the parity value and generate an "11bit" data packet, which is sent bit by bit; after sending 8 bits, Hardware control clears “Send” (clears even if the register value is equal to 0), and sets the interrupt flag "Complete Interrupt IT" to trigger the interrupt, and the software processes the interrupt function (the software clears the "IT" flag); if the data packet has not been sent yet , continue to write "Buff” and set "Send".
  • the hardware continues to send the parity bit and the stop bit. After the stop bit is sent, if "Send” is 1, jump to step 2 ;If "Send” is 0, jump to the following step of adding "1”; the step of adding "1” is: according to the configuration, when the bit “1” needs to be padded at the end, pad the bit, pad “1", and send , after completion, clear the module's complement "1" flag, and concurrently clear the module's transmit enable status.
  • the parameter calculation module includes a trigger period Counter and calculation sub-module
  • the frequency modulation parameters include the load setting value of the trigger period counter, the trigger period counter counts based on the load setting value, and if the count overflows, the calculation sub-module is triggered to calculate; after the calculation sub-module is triggered, it is calculated according to the modulation data Package and preset modulation configuration parameters, respectively calculate the reload value and corresponding load setting value of the PWM output timer, send the loading setting value to the trigger cycle counter, and send the reloading value to the PWM output timer.
  • the "modulation period" of a certain FSK signal is 500us (corresponding to a frequency of 2KHz). Since in most cases, the frequency needs to be adjusted twice within a “modulation period", the frequency switching control should be based on "half a modulation period”.
  • the unit is 250us (that is, the first parameter, corresponding to the frequency 4KHz).
  • the PWM frequency is 100KHz, that is, the period is 10us (second parameter), that is, the "timer overflow frequency” is 100KHz (period 10us), and the "trigger period counter” is triggered to decrement, which is equal to 0
  • the initial value is set, that is, the number of modulation cycles is 25 (the third parameter)
  • the next "modulation half cycle" can be set to 250us.
  • the parameter calculation module provided in this embodiment will trigger a "timer overflow trigger” every interval of one PWM cycle (second parameter).
  • the The module can perform the following two tasks within a fixed period of every "half modulation cycle" (first parameter): 1) Set the "auto-reload value” of the PWM output timer based on the bit data to be sent (this value is directly related to (in the second parameter) to switch the output frequency of the PWM output timer; 2) Reset the value of the "trigger cycle counter” inside the module to set the third parameter according to the second parameter, so that when the FSK data is output, it can be fixed The modulation period (first parameter) switches the output frequency of the PWM output timer.
  • the values of the above three parameters are determined by the actual communication protocol, and this case is compatible with all communication protocols.
  • the third parameter is equal to the first parameter divided by the second parameter. Since the essence of FSK communication is to modulate the carrier frequency, the period (second parameter) will change as the frequency changes. The value of the first parameter is relatively fixed, so the third parameter needs to change as the value of the first parameter changes.
  • the calculation sub-module includes a configuration register and a calculation unit.
  • the configuration register includes a period number register, a period difference register, a base frequency register, a modulation degree register and a polarity register. Select the register; the modulation configuration parameters include the period number register, the period difference register, the fundamental frequency register, the modulation degree register and the polarity selection register respectively store the modulation period number, modulation period difference, set fundamental frequency, modulation degree and modulation polarity, etc.
  • the modulation configuration parameters that need to be configured by the parameter calculation module include carrier reference frequency (related to the second parameter), modulation period length (related to the first parameter), polarity selection (related to the second parameter), etc., It can be pre-calculated by the MCU and configured into the above-mentioned corresponding registers, so that the parameter calculation module can calculate the above-mentioned frequency modulation parameters.
  • the principle by which the parameter calculation module calculates the above frequency modulation parameters includes:
  • Polarity options include “+”, “-”, “+-” and “-+”;
  • Auto-reload value set base frequency + 1 ⁇ modulation degree
  • Cycle counter (positive) modulation cycle number - positive modulation cycle difference
  • Cycle counter (negative) number of modulation cycles + negative modulation cycle difference.
  • the second signal processing module can be compatible with the usage requirements of all QI protocols. For example, when the PWM output timer frequency of a certain MCU is 48MHz, the relationship between the values configured in each register and the actual output FSK parameters can be shown in Table 2 and Table 3 below respectively.
  • the calculation sub-module may also include an intermediate variable register, and the calculation unit calculates based on the modulation polarity. Calculate the logic value corresponding to the bit data to be sent, and write the logic value into the intermediate variable register to record the logic level of the output frequency; according to the preset modulation configuration parameters, calculate the reload value corresponding to the logic value under the corresponding modulation polarity and Load settings.
  • the MCU can first preset the values of some registers, as shown in Table 4 below:
  • "Polarity Selection” can be set to "+”, "-” and " ⁇ ".
  • the input of this module includes: the upper level trigger signal, "bit data to be sent”; the output of this module includes: the value “TR1" output to the "trigger cycle counter", the reload value output to the PWM timer " TR2".
  • the timer frequency divided by TR2 is equal to the PWM output frequency
  • TR1 divided by the PWM output frequency is equal to the half-cycle duration
  • each embodiment of the first signal processing module described above can be applied to a modulated signal processing device that includes a first signal processing module but does not include a second processing module, or can also be applied to a modulated signal processing device that also includes a first signal processing module. and a modulated signal processing device of the second processing module.
  • the above-mentioned embodiments of the second signal processing module can also be applied to modulated signal processing devices that include the second signal processing module but do not include the first processing module, or can also be applied to modulated signal processing devices that include both the first signal processing module and the first processing module. Modulated signal processing device of the second processing module.
  • Modulated signal processing device of the second processing module For specific implementation methods, reference may be made to the above description, and they will not be listed one by one here.
  • this embodiment also provides a modulated signal processing method, as shown in Figure 18.
  • the method includes at least one of the following steps S1 and S2, wherein:
  • Step S1 Receive the completion flag output by the analog-to-digital converter, collect the conversion value output by the analog-to-digital converter, and generate corresponding bit data based on the total number of samples and the preset half-cycle value;
  • Step S2 convert the bit data into a modulation data packet that complies with the Qi protocol, and calculate the reload value of the PWM output timer and the corresponding frequency adjustment according to the modulation data packet and the preset modulation configuration parameters. Control parameters to make the PWM output timer output the corresponding pulse width modulation signal;
  • the modulation signal processing method provided in this embodiment is based on the same concept as the above-mentioned modulation signal processing device, so it can at least achieve the beneficial effects that the above-mentioned modulation signal processing device can achieve, which will not be described again here.
  • this embodiment also provides a microcontroller, on which the modulated signal processing device as in any of the above embodiments is integrated.
  • the microcontroller provided in this embodiment is based on the same concept as the above modulated signal processing device, so it can at least achieve the beneficial effects that the above modulated signal processing device can achieve, which will not be described again here.
  • this embodiment also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, and also includes a digital logic circuit, and the digital logic circuit
  • the circuit includes the modulated signal processing device as described above.
  • the electronic device may be a chip formed with the microcontroller, and the above-mentioned wireless charging system, motor control system (or only the control device of the system) using the chip, etc.
  • the electronic equipment provided by the embodiments of the present application and the modulated signal processing device provided by the embodiments of the present application are based on the same inventive concept, and have the same beneficial effects as the methods adopted, operated or implemented.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)

Abstract

本申请提出一种调制信号处理装置、方法、微控制器及电子设备，该调制信号处理装置应用于微控制器，包括：第一信号处理模块，与微控制器的模拟数字转换器连接，用于：接收到模拟数字转换器输出的完成标志，并采集模拟数字转换器输出的转换值，以及根据总采样次数和预设半周期值生成对应的比特数据；和/或，第二信号处理模块，与微控制器的PWM输出定时器连接，用于：将比特数据转换为符合Qi协议的调制数据包，并根据调制数据包和预设的调制配置参数，分别计算PWM输出定时器的重装载值和对应的频率调制参数，以使PWM输出定时器输出相应的脉宽调制信号。本申请的控制装置集成为一个整体，可直接操作定时器，具有高兼容性，高精度及易实现性。

Description

调制信号处理装置、方法、微控制器及电子设备 技术领域
本申请属于电数字技术领域，具体涉及一种调制信号处理装置、方法、微控制器及电子设备。
背景技术
Qi协议是无线充电联盟(Wireless Power Consortium)推出的“无线充电”标准，是无线充电领域的一项通用规范。符合Qi协议规范的无线充通信协议中，数据从电力接收器传输到电力发射器(RX to TX)采用ASK(调制)数据，数据从电力发射器传输到电力接收器(TX to RX)采用FSK调制)数据。其中，RX可以为手机、手表、平板电脑等电子设备；TX可以为移动电源、充电器等电子设。ASK数据或FSK数据在上述TX设备上的数据处理，通过由MCU(MoneyWise Credit Union，微控制器)来控制实现。
在无线充电器系统中，一般通过MCU控制PWM波，通过H桥电路输出信号载波，其中FSK数据实际上是MCU控制调整PWM的频率实现。
随着无线充电的不断发展和人民生活品质的不断提升，市场上出现了数量更多、覆盖更广的无线充电产品。一方面而言，市场上出现了种类繁多的产品，使得无线充电领域的技术和产品市场需求量剧增；而从另一方面来说，为了追求更高的充电性能，有些产品不得不使用性价比更低的较为昂贵的零部件，或采用占用资源更多的数据处理方式。如此，市场上出现了更多的成本敏感型的产品，而高成本的应用方案将极大限制这类产品的发展。
发明内容
本申请提出一种调制信号处理装置、方法、微控制器及电子设备，该调制信号处理装置集成为一个整体，可直接操作微控制器的PWM输出定时器和模拟数字转换器，具有高兼容性，高精度及易实现性。
本申请第一方面实施例提出了一种调制信号处理装置，应用于微控制器，包括第一信号处理模块和/或第二信号处理模块，其中：
所述第一信号处理模块，与所述微控制器的模拟数字转换器连接，用于：接收到所述模拟数字转换器输出的完成标志，并采集所述模拟数字转换器输出的转换值，以及根据总采样次数和预设半周期值生成对应的比特数据；
所述第二信号处理模块，与所述微控制器的PWM输出定时器连接，用于：将所述比特数据转换为符合Qi协议的调制数据包，并根据所述调制数据包和预设的调制配置参数，分别计算所述PWM输出定时器的重装载值和对应的频率调制参数，以使所述PWM输出定时器输出相应的脉宽调制信号。
在本申请一些实施例中，所述第一信号处理模块包括数据采样模块和数据解码模块；
所述数据采样模块接收所述模拟数字转换器输出的完成标志，并采集所述模拟数字转换器输出的转换值，输出记录的总采样次数和第一中断标志；
所述数据解码模块接收所述第一中断标志，并根据接收到的总采样次数和预设半周期值生成对应的比特数据。
在本申请一些实施例中，所述数据采样模块包括逻辑电路和计数器，所述计数器用于记录所述总采样次数；
所述逻辑电路用于根据所述转换值和预设比较值生成逻辑值，所述逻辑值进行边沿跳转时触发所述总采样次数的输出，并将所述总采样次数清零，发出所述第一中断标志。
在本申请一些实施例中，所述预设比较值包括参考值和迟滞值；所述逻辑电路包括第一逻辑电路和第二逻辑电路；
所述第一逻辑电路输入所述参考值、所述迟滞值以及所述逻辑值，并根据预设逻辑条件输出实际比较值；所述第二逻辑电路输入所述实际比较值和所述转换值，并输出所述逻辑值；
其中，所述预设逻辑条件包括：
若所述逻辑值为1，则所述实际比较值等于所述参考值与所述迟滞值的差值；若所述逻辑值为0，则所述实际比较值等于所述参考值与所述迟滞值的和。
在本申请一些实施例中，所述数据采样模块还包括参考值寄存器、迟滞值寄存器、计数值输出寄存器、逻辑值寄存器及第一中断标志寄存器，并分别存储所述参考值、所述迟滞值、所述总采样次数、所述逻辑值及所述第一中断标志。
在本申请一些实施例中，所述数据解码模块包括计算单元，所述计算单元根 据所述总采样次数确定捕获到的半周期个数，并基于预设计算规则，根据所述半周期个数计算对应的比特数据；
其中，所述预设计算规则包括：
若所述半周期个数为2，则确定对应的比特数为1；
若所述半周期个数为3，则确定首次捕获到时对应的比特数为一个0与一个1，下次捕获到时对应的比特数为0；
若所述半周期个数为4，则确定对应的比特数为两个0；
若所述半周期个数大于4，则确定超时、数据包发送错误或结束。
在本申请一些实施例中，所述数据解码模块还包括比特接收状态机，所述计算单元将计算出的比特数据发送至所述比特接收状态机；
所述比特接收状态机对接收到的比特数据进行格式校验，将校验成功的比特数据存入数据缓存寄存器，并在校验结束后置位有效性标志和第二中断标志，以及在校验错误时清除所述有效性标志、置位所述第二中断标志和重置所述比特接收状态机。
在本申请一些实施例中，所述比特接收状态机依次对写入的每个比特数据进行校验，并依次验证数据包的起始位、8个比特值和奇偶校验值，以及终止位。
在本申请一些实施例中，所述数据解码模块还包括半周期值寄存器、计数值接收寄存器、有效性标志寄存器及第二中断标志寄存器，分别用于存储所述半周期值、所述计数值接收、所述有效性标志及所述第二中断标志。
在本申请一些实施例中，所述第二信号处理模块包括数据包构成模块和参数计算模块，其中：
所述数据包构成模块，将待发送的比特数据转换为符合Qi协议的调制数据包，并将所述调制数据包发送至所述参数计算模块；
所述参数计算模块，根据所述调制数据包和预设的调制配置参数，分别计算所述PWM输出定时器的重装载值和对应的频率调制参数，以使所述PWM输出定时器输出相应的脉宽调制信号。
在本申请一些实施例中，所述数据包构成模块包括数据缓存寄存器、中断寄存器和控制寄存器，其中，
所述数据缓存寄存器存储所述微控制器写入的待发送数据；
所述中断寄存器存储所述微控制器写入的中断数据，用于标志所述调制数据 包中单个字节的完成；
所述控制寄存器存储所述微控制器写入的控制数据，用于控制所述数据包构成模块的启闭、比特数据的发送，以及所述调制数据包的格式。
在本申请一些实施例中，所述控制寄存器包括启动使能寄存器和发送使能寄存器；所述启动使能寄存器存储所述微控制器写入的启动使能状态值，用于控制所述数据包构成模块的启闭；
所述发送使能寄存器存储所述微控制器写入的发送使能状态值，用于控制比特数据的发送。
在本申请一些实施例中，所述调制数据包含有引导序言和至少一个字节的比特数据，所述控制寄存器还包括序言个数寄存器，所述序言个数寄存器在所述发送使能状态值为上升沿且数据缓存寄存器中待发送数据为空时，存储所述微控制器写入的序言控制数据，用于控制引导序言的位数。
在本申请一些实施例中，每个字节的比特数据均包括起始位、数据本体位、奇偶检验位及终止位；
所述控制寄存器还包括奇偶控制寄存器，所述奇偶控制寄存器在所述发送使能状态值为高电平且数据缓存寄存器中待发送数据为空时，存储所述微控制器写入的奇偶校验初值，用于控制所述奇偶检验位的初值。
在本申请一些实施例中，所述调制数据包还包括位于数据包末尾的补位数据，所述控制寄存器还包括补位控制寄存器，所述补位控制寄存器在所述发送使能状态值为低电平时，存储所述微控制器写入的补位标志数据，用于标志是否进行末尾补位。
在本申请一些实施例中，所述参数计算模块包括触发周期计数器和计算子模块，所述频率调制参数包括所述触发周期计数器的装载设定值，所述触发周期计数器基于所述装载设定值进行计数，且计数溢出则触发所述计算子模块进行计算；
所述计算子模块被触发后根据所述调制数据包和预设的调制配置参数，分别计算所述PWM输出定时器的重装载值和对应的装载设定值，并将所述装载设定值发送至所述触发周期计数器，将所述重装载值发送至所述PWM输出定时器。
在本申请一些实施例中，所述计算子模块包括配置寄存器和计算单元，所述配置寄存器包括周期数寄存器、周期差寄存器、基频寄存器、调制度寄存器及极性选择寄存器；
所述调制配置参数包括所述周期数寄存器、所述周期差寄存器、所述基频寄存器、所述调制度寄存器及所述极性选择寄存器分别存储的调制周期数、调制周期差、设置基频、调制度及调制极性。
在本申请一些实施例中，所述计算子模块还包括中间变量寄存器，所述计算单元基于所述调制极性，计算待发送的比特数据对应的逻辑值，并将所述逻辑值写入所述中间变量寄存器，记录输出频率的逻辑高低；
根据预设的调制配置参数，计算相应调制极性下所述逻辑值对应的所述重装载值和所述装载设定值。
本申请第二方面的实施例提供了一种调制信号处理方法，所述方法包括：
接收到模拟数字转换器输出的完成标志，并采集所述模拟数字转换器输出的转换值，以及根据总采样次数和预设半周期值生成对应的比特数据；和/或，
将所述比特数据转换为符合Qi协议的调制数据包，并根据所述调制数据包和预设的调制配置参数，分别计算所述PWM输出定时器的重装载值和对应的频率调制参数，以使所述PWM输出定时器输出相应的脉宽调制信号。
本申请第三方面的实施例提供了一种微控制器，其上集成有如第一方面所述的调制信号处理装置。
本申请第四方面的实施例提供了一种电子设备，包括存储器、处理器及存储在所述存储器上并可在所述处理器上运行的计算机程序，还包括数字逻辑电路，所述数字逻辑电路包括如第一方面所述的调制信号处理装置。
本申请实施例中提供的技术方案，至少具有如下技术效果或优点：
本申请实施例提供的调制信号处理装置，应用于微控制器，包括第一信号处理模块和/或第二信号处理模块，第一信号处理模块与所述微控制器的模拟数字转换器连接，用于：接收到所述模拟数字转换器输出的完成标志，并采集所述模拟数字转换器输出的转换值，以及根据总采样次数和预设半周期值生成对应的比特数据。第二信号处理模块与所述微控制器的PWM输出定时器连接，用于：将所述比特数据转换为符合Qi协议的调制数据包，并根据所述调制数据包和预设的调制配置参数，分别计算所述PWM输出定时器的重装载值和对应的频率调制参数，以使所述PWM输出定时器输出相应的脉宽调制信号。如此，可通过配置模块参数，适配市场上绝大部分协议的调制信号处理。且相较于软件实现方案，该调制信号处理装置作为硬件外设，其收发时序不受软件中断时间影响，调制信 号的处理将更加高效、精准便捷。同时，该装置的硬件电路设计较为简单，易于设计实现(可通过直接操作微控制器的PWM输出定时器和模拟数字转换器实现)；软件应用时，只需进行一些简单操作即可完成数据发送，节省MCU运算资源。且本装置可兼顾软硬件优点，在保证其灵活性的情况下可更加高效、准确、便捷地发送数据。
附图说明
通过阅读下文优选实施方式的详细描述，各种其他的优点和益处对于本领域普通技术人员将变得清楚明了。附图仅用于示出优选实施方式的目的，而并不认为是对本申请的限制。而且在整个附图中，用相同的参考符号表示相同的部件。在附图中：
图1示出了本申请实施例提供的调制信号处理装置的框架结构示意图
图2示出了本申请实施例提供的第一信号处理模块的框架结构示意图；
图3示出了本申请实施例中比特“0”和比特“1”输出示意图；
图4示出了现有技术中时间差值的示意图；
图5示出了本申请实施例提供的数据采集模块的执行逻辑示意图；
图6示出了参考值和迟滞值及count值的对应关系示意图；
图7示出了本申请实施例中Qi协议的数据结构示意图；
图8示出了比特数据与半周期个数的对应关系示意图；
图9示出了本申请实施例提供的数据解码模块的执行逻辑示意图；
图10示出了比特状态机的工作过程示意图；
图11示出了本申请实施例提供的第二信号处理模块的框架结构示意图；
图12示出了本申请实施例提供的第二信号处理模块在PWM输出定时器中的应用示意图；
图13示出了本申请实施例中Qi协议的FSK数据的数据结构示意图；
图14示出了本申请实施例提供的第二信号处理模块的执行逻辑示意图；
图15示出了本申请实施例提供的第二信号处理模块的执行逻辑与数据结构的对应关系示意图；
图16示出了本申请实施例提供的参数计算模块的结构示意图；
图17示出了本申请实施例中比特“0”和比特“1”输出示意图；
图18示出了本申请实施例提供的调制信号处理方法的流程示意图。
具体实施方式
下面将参照附图更详细地描述本申请的示例性实施方式。虽然附图中显示了本申请的示例性实施方式，然而应当理解，可以以各种形式实现本申请而不应被这里阐述的实施方式所限制。相反，提供这些实施方式是为了能够更透彻地理解本申请，并且能够将本申请的范围完整的传达给本领域的技术人员。
需要注意的是，除非另有说明，本申请使用的技术术语或者科学术语应当为本申请所属领域技术人员所理解的通常意义。
下面结合附图来描述根据本申请实施例提出的一种调制信号处理装置、方法、微控制器及电子设备。
现有相关技术中，实现ASK数据解码一般有如下几种方案：
1)比较器方案，先通过包络检波电路将ASK信号转化为包络信号，再通过滤波电路与比较器将包络信号转换为逻辑信号，并通过边沿中断与定时器进行时长计数，然后通过MCU软件根据该时长计数进行数据解码，再通过软件接收解码完成的数据包。
2)电压采样方案，与上述比较器方案类似，区别在于采用滤波放大电路生成逻辑信号。
3)电流采样方案，与上述比较器方案类似，区别在于，采用线圈进行电流采样，并采用差分放大电路生成逻辑信号。
4)ADC(模拟数字转换器)采样方案，先通过包络检波电路将ASK信号转化为包络信号，再通过定时器与ADC确定时长计数，然后通过MCU软件根据该时长计数进行数据解码，再通过软件接收解码完成的数据包。
其中，比较器方案对于MCU运算资源需求较低，需要MCU内置比较器外设，且比较器的参数较难通过软件配置调整；电压、电流采样方案，对于MCU运算资源需求较低，需要运放或专用的高度集成的电源管理芯片。ADC采样方案，是软件直接实现的，无需外围电路转换出“逻辑信号”，无需其他芯片，易于通过软件进行参数调整，但该部分高频触发运算，需要大量程序时间执行，对于MCU运算资源需求极高。且各方案中数据解码部分是相同的，可以作为通用模块，减轻MCU运算资源的占用。软件接收部分，需要程序根据各类无线协议的不同而 执行，无法做成通用模块。
另外，市场上出现了种类繁多的无线充电产品，一部分的产品使用了基于Qi的私有协议，由于载波频率不尽相同，参数细则也略有不同，因此FSK的物理层往往由MCU直接控制。又因为FSK需要很高的时序控制精度，因此对MCU的软件设计造成了一定的难度。且出现了更多的成本敏感型的产品，高成本的解调方案将极大限制这类产品的发展。具体地，采用MCU的软件实现方案存在资源占用与时序的矛盾，主要体现在以下几个方面：1)整个FSK发送过程耗时最多长达300ms，软件阻塞执行是不合理的；2)FSK发送时若执行其他例如I2C、UART、SDQ的通讯，低优先级的一方通讯时序会受到中断影响；3)由于FSK发送方式较I2C等更复杂，需要一些判断计算并读写定时器的寄存器，操作周期较长，低架构低频率的MCU较难在此时保证FSK时序的精准。
鉴于上述问题，本实施例提供了一种调制信号处理装置、方法、微控制器及电子设备，其中，该调制信号处理装置应用于微控制器，可用于，接收到微控制器的模拟数字转换器输出的完成标志，并采集模拟数字转换器输出的转换值，以及根据总采样次数和预设半周期值生成对应的比特数据；和/或用于，将比特数据转换为符合Qi协议的调制数据包，并根据调制数据包和预设的调制配置参数，分别计算PWM输出定时器的重装载值和对应的频率调制参数，以使PWM输出定时器输出相应的脉宽调制信号。如此，可通过配置模块参数，适配市场上绝大部分协议的调制信号处理，且相较于软件实现方案，该调制信号处理装置作为硬件外设，其收发时序不受软件中断时间影响，调制信号的处理将更加高效、精准便捷。同时，该装置的硬件电路设计较为简单，易于设计实现(可通过直接操作微控制器的PWM输出定时器和模拟数字转换器实现)；软件应用时，只需进行一些简单操作即可完成数据发送，节省MCU运算资源。且本装置可兼顾软硬件优点，在保证其灵活性的情况下可更加高效、准确、便捷地发送数据。
其中，半周期值可理解为能够表征半周期时长的采样数值，本实施例中的预设半周期值可以为任意数值，本领域技术人员可根据实际情况进行具体设定，本实施例不作具体限定。调制配置参数可包括信号调制过程需要配置的任意参数，包括但不限于周期数寄存器、周期差寄存器、基频寄存器、调制度寄存器及极性选择寄存器分别存储的调制周期数、调制周期差、设置基频、调制度及调制极性等，可通过MCU预先计算并配置到寄存器中。本实施例中的预设调制配置参数 可以为上述任意配置参数，本领域技术人员可根据实际情况进行具体设定，本实施例不作具体限定。
可以理解的是，该调制信号处理装置可以实现上述“接收到微控制器的模拟数字转换器输出的完成标志，并采集模拟数字转换器输出的转换值，以及根据总采样次数和预设半周期值生成对应的比特数据”的功能，以及上述“将比特数据转换为符合Qi协议的调制数据包，并根据调制数据包和预设的调制配置参数，分别计算PWM输出定时器的重装载值和对应的频率调制参数，以使PWM输出定时器输出相应的脉宽调制信号”的功能中的任一功能，也可以用于实现该上述两个功能，本实施例对此不做具体限定。
请参照图1为本申请实施例提供的调制信号处理装置的结构和应用原理示意图，如图1所示，该调制信号处理装置应用于微控制器，可包括第一信号处理模块和/或第二信号处理模块。其中，第一信号处理模块与微控制器的模拟数字转换器连接，用于：接收到模拟数字转换器输出的完成标志，并采集模拟数字转换器输出的转换值，以及根据总采样次数和预设半周期值生成对应的比特数据。第二信号处理模块与微控制器的PWM输出定时器连接，用于：将比特数据转换为符合Qi协议的调制数据包，并根据调制数据包和预设的调制配置参数，分别计算PWM输出定时器的重装载值和对应的频率调制参数，以使PWM输出定时器输出相应的脉宽调制信号。
其中，该第一信号处理模块可作为模拟数字转换器的一个独立硬件外设，集成于MCU中，应用于ASK数据解码过程，使ASK数据解码的过程由软件实现变为硬件实现，该ASK数据解码装置，可在接收到模拟数字转换器输出的完成标志后，采集模拟数字转换器输出的转换值，并根据总采样次数和预设半周期值生成对应的比特数据，实现ASK数据解码。且相较于软件实现方案，该硬件外设的收发时序不受软件中断时间影响，解码过程将更加高效、精准便捷。同时，该装置的逻辑简单，所需硬件电路的设计通常也较为简单，可直接操作ADC外设的寄存器实现；软件应用时，只需进行一些简单操作即可完成ASK数据解码，从而释放MCU中大量软件运算资源的占用。
第二信号处理模块可用于FSK数据发送的控制过程，可作为PWM输出定时器的一个独立硬件外设，功能上是一个数据通信接口模块，集成于MCU中，从而释放MCU中大量软件运算资源的占用，可将待发送的比特数据转换为符合Qi 协议的调制数据包，并根据调制数据包和预设的调制配置参数，分别计算PWM输出定时器的重装载值和对应的频率调制参数，以使PWM输出定时器输出相应的脉宽调制信号，如此，可通过配置模块参数，适配市场上绝大部分协议的FSK发送控制。且相较于软件实现方案，该硬件外设的收发时序不受软件中断时间影响，控制将更精准。同时，该装置的逻辑简单，所需数字逻辑电路的设计通常也较为简单，易于设计实现；软件应用时，只需进行一些简单操作即可完成数据发送，节省MCU运算资源。
下面结合附图对第一信号处理模块和第二信号处理模块的具体结构和功能进行详细阐述。
请参照图2为本申请实施例提供的第一信号处理模块的结构示意图，如图2所示，该第一信号处理模块，应用于微控制器，并与微控制器的模拟数字转换器连接，包括：数据采样模块，若接收到模拟数字转换器输出的完成标志(即ADC中断标志)，则采集模拟数字转换器输出的转换值，并输出记录的总采样次数和第一中断标志；数据解码模块，若接收到第一中断标志，则根据接收到的总采样次数和预设半周期值生成对应的比特数据。
本实施例中，该第一信号处理模块作为一个独立的硬件外设，实现方式类似于I2C外设的接收部分，即，MCU通过总线写入寄存器，配置发送参数、写入数据缓存、响应中断请求等，由ASK硬件外设模块直接操作ADC外设的寄存器。
其中，数据采样模块主要负责将线圈上的模拟电压信号转换为逻辑电平时长数据(即解调)。数据解码模块主要负责接收逻辑电平时长参数(可以是本实施例的数据采样模块输出的，也可以是软件采用其它方式所得)，并解码出字节，输出给软件。
对Qi协议规范的相关内容进行引用与解释可知，ASK信号表示比特“0”和比特“1”的方式如图3所示，采用简化的方波表示传输波形的电压幅值高低变化，比特“0”在一个周期内频率变化一次，比特“1”在一个周期内频率变化两次。频率变化即指从高电平变为低电平，或从低电平变为高电平。
基于上述ASK信号的特征，现有技术除ADC解调方案之外的其他的方案中，MCU接收到逻辑信号的边沿中断，随即通过计数器得到时间差值，例如，设置定时器计数频率为1MHz即周期为1us(第一参数)，若读到的“△Count”值为250(第二参数)，如图4所示，以此计算得到时间差值250us(第三参数)。第 三参数等于第一参数乘以第二参数，第一参数由定时器结合使用场景选择；第三参数由实际通信协议决定，受无线接收通信质量的波动影响。
在本实施例中，鉴于ADC在定时器的触发下进行信号转换，将模拟量的包络信号转换为量化的数字量(该数字量与模拟量呈正比)，数据采样模块可在每次接收到模拟数字转换器输出的完成标志后，采集模拟数字转换器输出的转换值，并记录总采样次数，再结合ADC触发转换的频率，可确定对应的逻辑电平时长数据。例如，逻辑信号的频率是4KHz(一秒内变化4千次)，转换值采样频率设置为逻辑信号频率的8倍，即32KHz(一秒内采样32千次)。也就是每段逻辑信号线变化期间，ADC能采样到8次。也就是理论上，ADC能连续采样到8次高于Vref的电压，随后连续采样到8次低于Vref的电压。采样次数(Count值)即用于记录该连续采样到一样的电压的次数，可根据采样频率，计算出包络信号线该段电压变化的时间长度(等同于上述第三参数)。
在本实施例一些实施方式中，数据采样模块包括逻辑电路和计数器，计数器用于记录总采样次数。逻辑电路用于根据转换值和预设比较值生成逻辑值，逻辑值进行边沿跳转时触发总采样次数的输出，并将总采样次数清零，发出第一中断标志。如此，该数据采样模块的功能实现以ADC外设输出的“转换值”和“完成标志(即定时器中断)”作为输入，定时器中断一次，则触发该数据采样模块运行一次。总采样次数输出后，将总采样次数清零，以备下次采样记录。发出该第一中断标志，可触发上述数据解码模块进行数据解码。
其中，逻辑值进行边沿跳转时触发总采样次数的输出，可以为逻辑值在上升沿触发总采样次数的输出，也可以为逻辑值在下降沿触发总采样次数的输出，只要每次进行相同方向的边沿跳转时才触发即可。
在本实施例另一些实施方式中，预设比较值可包括参考值和迟滞值。如图5所示，逻辑电路包括第一逻辑电路和第二逻辑电路；第一逻辑电路输入参考值、迟滞值以及逻辑值，并根据预设逻辑条件输出实际比较值；第二逻辑电路输入实际比较值和转换值，并输出逻辑值。
具体地，上述预设逻辑条件包括：若逻辑值为1，则实际比较值等于参考值与迟滞值的差值；若逻辑值为0，则实际比较值等于参考值与迟滞值的和。
第一逻辑电路可以为任意能够实现上述逻辑条件的电路，本实施例对其具体电路结构不作具体限定。第二逻辑电路可以为比较器电路，其正向输入为上述转 换值，负向输入为上述实际比较值，输出为上述逻辑值。
如图6所示，在包络信号线上的三条水平线，中间的为基准电压，即参考值，上下两条水平线用于限定迟滞区间，迟滞值即中间的基准电压分别与上下两个水平线对应电压的差值绝对值。即，参考值Vref为比较的中心值，迟滞值delt为正负差值，均由MCU软件配置。通过设置迟滞值，将比较值限定在一个区间的两端，相当于增大了比较值的取值范围，可以增加系统稳定性，减少逻辑不定态与信号波动对输出结果的影响，从而保障该第一信号处理模块的准确性。
需要说明的是，上述参考值和迟滞值可根据实际需要进行设定，本实施例对其具体数值不做具体限定。
相应地，该数据采样模块还包括参考值寄存器、迟滞值寄存器、计数值输出寄存器、逻辑值寄存器、第一中断标志寄存器以及模块使能寄存器等，并分别存储参考值、迟滞值、总采样次数、逻辑值、第一中断标志及使能状态值(通常为0或1的逻辑值)。
基于数据采样模块的上述结构，结合图6，对数据采样模块的工作过程进行详细描述如下：
数据采样模块以ADC外设输出的“转换值”和“完成标志”作为输入，每次接收到该完成标志，将模块使能寄存器的值更改为使能状态值，触发该模块运行一次。每次执行采样，则计数器的“计数值”自动加1。上述参考值和迟滞值经过第一逻辑电路后可生成实际比较值，用于和转换值进行比较，基于比较结果和比较电路可生成逻辑值logic，并写入逻辑值寄存器，用以反应“逻辑信号”的跳变，该逻辑值logic可影响迟滞值delt的正和负，以反作用于实际比较值。然后可在每次逻辑值logic上升沿(或下降沿)时，将计数器的“计数值”输出到计数值输出寄存器，随后将计数值清零，并置位中断(置位即将第一中断标志寄存器值写为1)，后续数据解码模块读取计数值输出寄存器中的总采样次数之后，清除计数值输出寄存器，即为将计数值输出寄存器的值写为0。
在本实施例另一些实施方式中，数据解码模块包括计算单元，计算单元根据总采样次数确定捕获到的半周期个数，并基于预设计算规则，根据半周期个数计算对应的比特数据。
首先，对Qi协议规范的相关内容进行引用与解释可知，ASK协议数的据结构如图7所示，接收的每个“Byte”需要11个bit，包括“起始位‘0’”、“8bit”、 “奇偶校验位”和“终止位‘1’”，每个数据包通常包括起始序言、N个字节及末尾的补位1。根据Qi协议的规律进一步分析可得：当数据bit“1”时，一个周期内边沿变化两次，周期结束时边沿方向不变化；当数据bit“0”时，一个周期内边沿变化一次，周期结束时边沿方向变化。当第二个数据bit“0”时，边沿方向变回。
本实施例以半周期为单位，采用单边沿计数判断，相对于双边沿计数判断更为高效且节省资源。如图8所示，捕获到的半周期值可能性包括以下几种情况：
捕获到“2个半周期”：即收到一个“1”；
捕获到“3个半周期”：首次捕获到时表明为一个“0”与一个“1”，下一次捕获到时表明为一个“0”；
捕获到“4个半周期”：即收到两个“0”；
捕获到“超过4个半周期”：表明超时，数据包发送错误或结束。
相应地，上述预设计算规则包括：若半周期个数为2，则确定对应的比特数为1；若半周期个数为3，则确定首次捕获到时对应的比特数为一个0与一个1，下次捕获到时对应的比特数为0；若半周期个数为4，则确定对应的比特数为两个0；若半周期个数大于4，则确定超时、数据包发送错误或结束。
在本实施例另一些实施方式中，数据解码模块还包括比特接收状态机，计算单元将计算出比特数据发送至比特接收状态机；比特接收状态机对接收到的比特数据进行格式校验，将校验成功的比特数据存入数据缓存寄存器，并在校验结束后置位有效性标志和第二中断标志，以及在校验错误时清除有效性标志、置位第二中断标志和重置比特接收状态机。
进一步地，数据解码模块还包括半周期值寄存器、计数值接收寄存器、有效性标志寄存器及第二中断标志寄存器，分别用于存储半周期值、计数值接收、有效性标志及第二中断标志。
基于数据解码模块的上述结构，结合图9，对数据解码模块的工作过程进行详细描述如下：
数据采样模块的“第一中断标志”(详见上文)可触发数据解码模块(若该模块独立使用时由软件直接写入)进行数据解码，每一次触发，该模块运行一次。随即，可根据软件配置的“半周期值”(配置要求周期值为偶数)，基于上述的预设计算规则，计算出输入的总采样次数(Count)对应捕获到的半周期个数，并对应向比特接收状态机写入对应的比特数据“0”或比特数据“1”(具体的如图8 所示)。比特接收状态机可对写入的每个比特数据进行校验，并依次验证数据包的起始位、8个比特值和奇偶校验值，以及终止位。然后，比特接收状态机将校验成功的比特数据写入数据缓存寄存器(Buff)，并置位(在寄存器中写1)有效性标志寄存器和第二中断标志寄存器。
其中，比特(bit)接收状态机的工作过程如图10所示，其中“p”表示接收到的8bit数据的奇偶校验值，初值由MCU配置。图中的方框代表状态，箭头代表条件，每写入一个比特“0”或比特“1”跳变一次。
另外，上述各寄存器的取值范围和位宽可如下表1所示(表中数值仅为示例，本实施例对各寄存器的取值范围和位宽不做具体限定)
表1
需要说明的是，上述数据采集模块和数据解码模块结构，及各寄存器的设置，只是本实施例的较佳实施方式，本实施例并不以此为限，只要能实现各自功能的结构均属于本申请的保护范围。
请参照图11为本申请实施例提供的第二信号处理模块的结构示意图，如图11所示，该第二信号处理模块应用于微控制器的PWM输出定时器，可包括数据 包构成模块和参数计算模块，其中：数据包构成模块，将待发送的比特数据转换为符合Qi协议的调制数据包，并将调制数据包发送至参数计算模块；参数计算模块，根据调制数据包和预设的调制配置参数，分别计算PWM输出定时器的重装载值和对应的频率调制参数，以使PWM输出定时器输出相应的脉宽调制信号。
第二信号处理模块作为PWM输出定时器的一个独立硬件外设，可设置在PWM输出定时器上如图12所示的位置，功能上相当于一个数据通信接口模块，实现方式类似于I2C外设的发送部分，MCU可通过总线写入第二信号处理模块的寄存器，配置发送参数、写入数据缓存、响应中断请求等，该第二信号处理模块可直接操作定时器的寄存器。
其中，数据包构成模块主要负责FSK通信的协议层控制，负责将软件需要发送的数据包转换为符合Qi协议的控制参数，并将输出结果传输给参数计算模块。参数计算模块主要负责FSK通信的物理层控制。
本实施例提供的第二信号处理模块，包括数据包构成模块和参数计算模块，数据包构成模块可将待发送的比特数据转换为符合Qi协议的调制数据包，并将调制数据包发送至参数计算模块。参数计算模块可根据调制数据包和预设的调制配置参数，分别计算PWM输出定时器的重装载值和对应的频率调制参数，以使PWM输出定时器输出相应的脉宽调制信号，如此，可通过配置模块参数，适配市场上绝大部分协议的调制信号处理。且相较于软件实现方案，该硬件外设的收发时序不受软件中断时间影响，控制将更精准。同时，该装置的硬件电路设计通常较为简单，易于设计实现；软件应用时，只需进行一些简单操作即可完成数据发送，节省MCU运算资源。且本装置可兼顾软硬件优点，在保证其灵活性的情况下可更加高效、准确、便捷地发送数据。
在本实施例一些实施方式中，数据包构成模块可包括数据缓存寄存器、中断寄存器和控制寄存器，其中，数据缓存寄存器存储微控制器写入的待发送数据；中断寄存器存储微控制器写入的中断数据，用于标志调制数据包中单个字节的完成；控制寄存器存储微控制器写入的控制数据，用于控制数据包构成模块的启闭、比特数据的发送，以及调制数据包的格式。
本实施例通过设置上述寄存器，将数据缓存功能从MCU其它硬件上脱离出来，如此，FSK数据发送过程中，采用数据缓存寄存器用于缓存待发送的比特数据，MCU只需发送数据这样简单的操作，从而节省MCU构成数据包所需要 耗费的时间，避免程序运行堵塞，可有效减少MCU资源的占用，便于MCU执行其它功能，继而大幅提高其工作效率。
控制寄存器包括启动使能寄存器和发送使能寄存器(Send)；启动使能寄存器用于存储微控制器写入的启动使能状态值，以控制数据包构成模块的启闭；发送使能寄存器用于存储微控制器写入的发送使能状态值，以控制比特数据的发送。
其中，状态值通常为1或0的逻辑值，1为高电平，表示控制开启状态，即数据包构成模块开启或者能够发送数据；0为低电平，表示控制关闭状态，即数据包构成模块关闭或者不能够发送数据。
该数据包构成模块在构成数据包时，MCU先通过总线更改启动使能寄存器的使能状态，启动数据包构成模块，然后将待发送的一个字节的数据写入到数据缓存寄存器(Buff)，随后置位发送使能寄存器(Send)，使该寄存器值等于1，接收第一信号处理模块发送的比特数据。然后MCU继续通过总线写入控制寄存器，可根据预设的数据包格式控制数据包的具体格式。待生成预设格式数据包，可逐位发送至参数计算模块，然后MCU继续通过总线向中断寄存器(IT)发送中断数据，置位中断标志完成中断IT，触发中断，并硬件控制清除使能状态值(清除可理解为使该寄存器值等于0，控制状态为关闭)。若该数据包未发送完毕，继续写入“Buff”，并置位(置位可理解为使该寄存器值等于1，控制状态为开启)控制寄存器，若发送完毕则不执行。
对Qi协议规范的相关内容进行引用与解释：参考Qi协议规范的定义可知，符合Qi协议的FSK数据通常具有一定的格式，具体数据结构如图13所示，发送的每个“Byte”需要11个bit，包括“起始位‘0’”、“8个bit位”、“奇偶校验位”和“终止位‘1’”。每个数据包前可能包含由几个比特“1”组成的引导(序言pre)，每个数据包结束后可能需要加一个比特“1”，即补位“1”，以防最后一位丢失。
基于上述Qi协议规范的数据包格式，该调制数据可包含有引导序言和至少一个字节的比特数据，控制寄存器还包括序言个数寄存器，序言个数寄存器在发送使能寄存器的状态值为上升沿，且数据缓存寄存器中的待发送数据为空时，存储微控制器写入的序言控制数据，用于控制引导序言的位数，以实现对引导序言位数的灵活配置，进一步提高了该第二信号处理模块的灵活性和通用性。
上述每个字节的比特数据均包括起始位、数据本体位、奇偶检验位及终止位； 控制寄存器还包括奇偶控制寄存器，奇偶控制寄存器在发送使能寄存器的状态值为高电平且待发送数据为空时，存储微控制器写入的奇偶校验初值，用于控制奇偶检验位的初值，继而实现对数据包格式的配置，进一步提高了该第二信号处理模块的灵活性和通用性。
调制数据包还包括位于数据包末尾的补位数据，控制寄存器还包括补位控制寄存器，补位控制寄存器在发送使能寄存器的状态值为低电平时，存储微控制器写入的补位标志数据，用于标志是否进行末尾补位。如此，在发送使能寄存器的状态值为低电平写入补位标志数据，可以不影响比特数据的发送，可进一步保证该第二信号处理模块发送FSK数据的准确性。
其中，补位标志数据也可以为1或0的逻辑值，1为高电平，表示需要补位；0为低电平，表示不需要补位。
由于不同的协议的引导序言个数、奇偶校验初值、结束是否补比特“1”等均不相同，因此，为兼容所有Qi的标准协议和私有通信协议，本实施例分别设置上述序言个数寄存器、奇偶控制寄存器及补位控制寄存器，以使上述引导序言个数、奇偶校验初值、结束是否补比特“1”均可配置，可进一步提高该第二信号处理模块的通用性。
从控制时序上，数据包构成模块的主要执行逻辑如图14和图15所示(模块功能由软件与硬件配合完成，下文描述的“硬件”即为本申请第二信号处理模块的逻辑执行主体)：
首先，MCU通过总线，写入待发送的一个字节到数据缓存寄存器(Buff)，随后置位发送使能寄存器，使该寄存器值等于1。由于此时未在发送数据(数据包的起始)，可根据配置值，增加若干个比特“1”，计算奇偶校验值并生成“11bit”数据包，逐位发送；发送完8bit后，硬件控制清除“Send”(清除即使该寄存器值等于0)，并置位中断标志“完成中断IT”，触发中断，软件处理中断函数(软件清除“IT”标志)；若该数据包未发送完毕，继续写入“Buff”并置位“Send”，若发送完毕则不执行；硬件继续发送奇偶校验位与终止位，终止位发送完毕后，若“Send”为1，跳转第2步；若“Send”为0，跳转至下述补“1”的步骤；补“1”步骤即：根据配置，在末尾需要补比特“1”时进行补位，补“1”，并发送，完成后，清除该模块的补“1”标志位，并发清除该模块的发送使能状态。
在本实施例另一些实施方式中，如图16所示，参数计算模块包括触发周期 计数器和计算子模块，频率调制参数包括触发周期计数器的装载设定值，触发周期计数器基于装载设定值进行计数，且计数溢出则触发计算子模块进行计算；计算子模块被触发后根据调制数据包和预设的调制配置参数，分别计算PWM输出定时器的重装载值和对应的装载设定值，并将装载设定值发送至触发周期计数器，将重装载值发送至PWM输出定时器。
本实施例对Qi协议规范的相关内容进行引用与解释：FSK有“单极性”与“双极性”的区别，有“正调制”、“负调制”的区别，表示比特“0”和比特“1”的方式如图17所示，即“0”在一个周期内频率变化一次，“1”在一个周期内频率变化两次。因此本案设计的模块需要能切换极性、配置调制度，并正确输出比特“0”和比特“1”。
进一步地，例如某FSK信号的“调制周期”为500us(对应频率2KHz)，由于多数情况下，一个“调制周期”内要调整两次频率，因此频率切换控制应以“半个调制周期”为单位，即为250us(即第一参数，对应频率4KHz)。
在调制信号处理过程中，例如PWM频率为100KHz，即周期为10us(第二参数)，即“定时器溢出频率”为100KHz(周期10us)，“触发周期计数器”以此触发自减，等于0时触发下一部分的计算模块。若设置初值，即调制周期数为25(即第三参数)，则可使下一个“调制半周期”为250us。
本实施例提供的参数计算模块，每间隔一个PWM周期(第二参数)会触发一次“定时器溢出触发”，经过“触发周期计数器”分频(从第三参数自减到0)，使得该模块可以固定的每“半个调制周期”(第一参数)时间内执行以下两项工作：1)根据待发送的比特数据，设置PWM输出定时器的“自动重装载值”(该值直接相关于第二参数)，以切换PWM输出定时器的输出频率；2)重新设置该模块内部的“触发周期计数器”的值，以根据第二参数设置第三参数，使FSK数据输出时，可以固定的调制周期(第一参数)切换PWM输出定时器的输出频率。
需要说明的是，以上三个参数数值均由实际通信协议决定，本案可兼容所有通信协议。第三参数等于第一参数除以第二参数。由于FSK通信本质是调制载波频率，周期(第二参数)会随频率变化而变化，第一参数的值相对为固定值，因此第三参数需要随着第一参数值的变化而变化。
在本实施例另一些实施方式中，计算子模块包括配置寄存器和计算单元，配置寄存器包括周期数寄存器、周期差寄存器、基频寄存器、调制度寄存器及极性 选择寄存器；调制配置参数包括周期数寄存器、周期差寄存器、基频寄存器、调制度寄存器及极性选择寄存器分别存储的调制周期数、调制周期差、设置基频、调制度及调制极性等。
在本实施例中，参数计算模块需要配置的调制配置参数包括载波基准频率(与第二参数相关)、调制周期长(与第一参数相关)、极性选择(与第二参数相关)等，可通过MCU预先计算并配置到上述相应的寄存器中，以便于参数计算模块计算出上述频率调制参数。
其中，参数计算模块计算出上述频率调制参数的原理包括：
极性选择包括“+”、“-”、“+-”和“-+”；
自动重装载值＝设置基频+1±调制度；
周期计数器(正)＝调制周期数-正调制周期差；
周期计数器(负)＝调制周期数+负调制周期差。
本实施例可通过配置上述寄存器的值，使得该第二信号处理模块可以兼容所有QI协议的使用需求。例如，某MCU的PWM输出定时器频率为48MHz时，对其各寄存器进行配置的值与实际输出的FSK参数的关系可分别如下面表2和表3所示。
表2
表3
具体地，计算子模块还可包括中间变量寄存器，计算单元基于调制极性，计 算待发送的比特数据对应的逻辑值，并将逻辑值写入中间变量寄存器，记录输出频率的逻辑高低；根据预设的调制配置参数，计算相应调制极性下逻辑值对应的重装载值和装载设定值。
具体地，可先由MCU预设一些寄存器的值，如下表4所示：
表4
其中“极性选择”，可以设置为“+”、“－”和“±”。该模块的输入包括：上一级的触发信号、“待发送的比特数据”；该模块的输出包括：输出到“触发周期计数器”的值“TR1”、输出到PWM定时器的重装载值“TR2”。
设定一个中间变量寄存器“Logic”，记录输出频率的逻辑高低。“Logic”由两个bit组成，数值与含义如下表5所示：
表5
鉴于一个协议周期包括两个“半周期”，所以将上一级的触发信号记录次数，分为第1次触发和第2次触发。根据“极性选择”、“触发次数”以及“待发送的比特数据”，将变量“Logic”的值如下表6a-表6c所示操作。
表6a
表6b
表6c
上述表中，“^＝”表示将两遍的值异或后写入左边的寄存器。
根据上一步的“Logic”值，按照表7所示，作对应的计算操作，并将计算结果“TR1”、“TR2”输出。该第二信号处理模块最终的输出结果的意义是：定时器频率除以TR2就等于PWM输出频率；TR1除以PWM输出频率就等于半周期时长。
表7
更具体地，上述各寄存器的取值范围和位宽可如下表8所示。
表8
需要说明的是，上述数据包构成模块和参数计算模块结构，及各寄存器的设置，只是本实施例的较佳实施方式，本实施例并不以此为限，只要能实现各自功能的结构均属于本申请的保护范围。
可以理解的是，上述第一信号处理模块的各实施方式，均可应用于包括第一信号处理模块但不包括第二处理模块的调制信号处理装置，也可应用于同时包括第一信号处理模块和第二处理模块的调制信号处理装置。同理，上述第二信号处理模块的各实施方式，也均可应用于包括第二信号处理模块但不包括第一处理模块的调制信号处理装置，也可应用于同时包括第一信号处理模块和第二处理模块的调制信号处理装置。具体实施方式可参照上述记载，在此不再一一列举。
基于上述调制信号处理装置相同的构思，本实施例还提供一种调制信号处理方法，如图18所示，该方法包括下述步骤S1和步骤S2中的至少一个步骤，其中：
步骤S1，接收到模拟数字转换器输出的完成标志，并采集模拟数字转换器输出的转换值，以及根据总采样次数和预设半周期值生成对应的比特数据；
步骤S2，将比特数据转换为符合Qi协议的调制数据包，并根据调制数据包和预设的调制配置参数，分别计算PWM输出定时器的重装载值和对应的频率调 制参数，以使PWM输出定时器输出相应的脉宽调制信号；
本实施例提供的调制信号处理方法，基于上述调制信号处理装置相同的构思，故至少能够实现上述调制信号处理装置能够实现的有益效果，在此不再赘述。
基于上述调制信号处理装置相同的构思，本实施例还提供一种微控制器，其上集成有如上述任一实施方式的调制信号处理装置。
本实施例提供的微控制器，基于上述调制信号处理装置相同的构思，故至少能够实现上述调制信号处理装置能够实现的有益效果，在此不再赘述。
基于上述调制信号处理装置相同的构思，本实施例还提供一种电子设备，包括存储器、处理器及存储在存储器上并可在处理器上运行的计算机程序，还包括数字逻辑电路，且数字逻辑电路包括如上述的调制信号处理装置。该电子设备可以为形成有该微控制器的芯片，以及使用该芯片的上述无线充电系统、电机控制系统(或者仅是系统的控制设备)等。
本申请实施例提供的电子设备与本申请实施例提供的调制信号处理装置出于相同的发明构思，具有与其采用、运行或实现的方法相同的有益效果。
需要说明的是：
在此处所提供的说明书中，说明了大量具体细节。然而，能够理解，本申请的实施例可以在没有这些具体细节的情况下实践。在一些实例中，并未详细示出公知的结构和技术，以便不模糊对本说明书的理解。
类似地，应当理解，为了精简本申请并帮助理解各个发明方面中的一个或多个，在上面对本申请的示例性实施例的描述中，本申请的各个特征有时被一起分组到单个实施例、图、或者对其的描述中。然而，并不应将该公开的方法解释成反映如下示意图：即所要求保护的本申请要求比在每个权利要求中所明确记载的特征更多的特征。更确切地说，如下面的权利要求书所反映的那样，发明方面在于少于前面公开的单个实施例的所有特征。因此，遵循具体实施方式的权利要求书由此明确地并入该具体实施方式，其中每个权利要求本身都作为本申请的单独实施例。
此外，本领域的技术人员能够理解，尽管在此的一些实施例包括其它实施例 中所包括的某些特征而不是其他特征，但是不同实施例的特征的组合意味着处于本申请的范围之内并且形成不同的实施例。例如，在下面的权利要求书中，所要求保护的实施例的任意之一都可以以任意的组合方式来使用。
以上，仅为本申请较佳的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到的变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以权利要求的保护范围为准。

Claims (21)

  1. 一种调制信号处理装置，其特征在于，应用于微控制器，包括第一信号处理模块和/或第二信号处理模块，其中：
    所述第一信号处理模块，与所述微控制器的模拟数字转换器连接，用于：接收到所述模拟数字转换器输出的完成标志，并采集所述模拟数字转换器输出的转换值，以及根据总采样次数和预设半周期值生成对应的比特数据；
    所述第二信号处理模块，与所述微控制器的PWM输出定时器连接，用于：将所述比特数据转换为符合Qi协议的调制数据包，并根据所述调制数据包和预设的调制配置参数，分别计算所述PWM输出定时器的重装载值和对应的频率调制参数，以使所述PWM输出定时器输出相应的脉宽调制信号。
  2. 根据权利要求1所述的装置，其特征在于，所述第一信号处理模块包括数据采样模块和数据解码模块；
    所述数据采样模块接收所述模拟数字转换器输出的完成标志，并采集所述模拟数字转换器输出的转换值，输出记录的总采样次数和第一中断标志；
    所述数据解码模块接收所述第一中断标志，并根据接收到的总采样次数和预设半周期值生成对应的比特数据。
  3. 根据权利要求2所述的装置，其特征在于，所述数据采样模块包括逻辑电路和计数器，所述计数器用于记录所述总采样次数；
    所述逻辑电路用于根据所述转换值和预设比较值生成逻辑值，所述逻辑值进行边沿跳转时触发所述总采样次数的输出，并将所述总采样次数清零，发出所述第一中断标志。
  4. 根据权利要求3所述的装置，其特征在于，所述预设比较值包括参考值和迟滞值；所述逻辑电路包括第一逻辑电路和第二逻辑电路；
    所述第一逻辑电路输入所述参考值、所述迟滞值以及所述逻辑值，并根据预设逻辑条件输出实际比较值；所述第二逻辑电路输入所述实际比较值和所述转换值，并输出所述逻辑值；
    其中，所述预设逻辑条件包括：
    若所述逻辑值为1，则所述实际比较值等于所述参考值与所述迟滞值的差值；若所述逻辑值为0，则所述实际比较值等于所述参考值与所述迟滞值的和。
  5. 根据权利要求4所述的装置，其特征在于，所述数据采样模块还包括参考值寄存器、迟滞值寄存器、计数值输出寄存器、逻辑值寄存器及第一中断标志 寄存器，并分别存储所述参考值、所述迟滞值、所述总采样次数、所述逻辑值及所述第一中断标志。
  6. 根据权利要求2所述的装置，其特征在于，所述数据解码模块包括计算单元，所述计算单元根据所述总采样次数确定捕获到的半周期个数，并基于预设计算规则，根据所述半周期个数计算对应的比特数据；
    其中，所述预设计算规则包括：
    若所述半周期个数为2，则确定对应的比特数为1；
    若所述半周期个数为3，则确定首次捕获到时对应的比特数为一个0与一个1，下次捕获到时对应的比特数为0；
    若所述半周期个数为4，则确定对应的比特数为两个0；
    若所述半周期个数大于4，则确定超时、数据包发送错误或结束。
  7. 根据权利要求6所述的装置，其特征在于，所述数据解码模块还包括比特接收状态机，所述计算单元将计算出的比特数据发送至所述比特接收状态机；
    所述比特接收状态机对接收到的比特数据进行格式校验，将校验成功的比特数据存入数据缓存寄存器，并在校验结束后置位有效性标志和第二中断标志，以及在校验错误时清除所述有效性标志、置位所述第二中断标志和重置所述比特接收状态机。
  8. 根据权利要求7所述的装置，其特征在于，所述比特接收状态机依次对写入的每个比特数据进行校验，并依次验证数据包的起始位、8个比特值和奇偶校验值，以及终止位。
  9. 根据权利要求6所述的装置，其特征在于，所述数据解码模块还包括半周期值寄存器、计数值接收寄存器、有效性标志寄存器及第二中断标志寄存器，分别用于存储所述半周期值、所述计数值接收、所述有效性标志及所述第二中断标志。
  10. 根据权利要求1所述的装置，其特征在于，所述第二信号处理模块包括数据包构成模块和参数计算模块，其中：
    所述数据包构成模块，将待发送的比特数据转换为符合Qi协议的调制数据包，并将所述调制数据包发送至所述参数计算模块；
    所述参数计算模块，根据所述调制数据包和预设的调制配置参数，分别计算所述PWM输出定时器的重装载值和对应的频率调制参数，以使所述PWM输出定时 器输出相应的脉宽调制信号。
  11. 根据权利要求10所述的装置，其特征在于，所述数据包构成模块包括数据缓存寄存器、中断寄存器和控制寄存器，其中，
    所述数据缓存寄存器存储所述微控制器写入的待发送数据；
    所述中断寄存器存储所述微控制器写入的中断数据，用于标志所述调制数据包中单个字节的完成；
    所述控制寄存器存储所述微控制器写入的控制数据，用于控制所述数据包构成模块的启闭、比特数据的发送，以及所述调制数据包的格式。
  12. 根据权利要求11所述的装置，其特征在于，所述控制寄存器包括启动使能寄存器和发送使能寄存器；所述启动使能寄存器存储所述微控制器写入的启动使能状态值，用于控制所述数据包构成模块的启闭；
    所述发送使能寄存器存储所述微控制器写入的发送使能状态值，用于控制比特数据的发送。
  13. 根据权利要求12所述的装置，其特征在于，所述调制数据包含有引导序言和至少一个字节的比特数据，所述控制寄存器还包括序言个数寄存器，所述序言个数寄存器在所述发送使能状态值为上升沿且数据缓存寄存器中待发送数据为空时，存储所述微控制器写入的序言控制数据，用于控制引导序言的位数。
  14. 根据权利要求13所述的装置，其特征在于，每个字节的比特数据均包括起始位、数据本体位、奇偶检验位及终止位；
    所述控制寄存器还包括奇偶控制寄存器，所述奇偶控制寄存器在所述发送使能状态值为高电平且数据缓存寄存器中待发送数据为空时，存储所述微控制器写入的奇偶校验初值，用于控制所述奇偶检验位的初值。
  15. 根据权利要求13所述的装置，其特征在于，所述调制数据包还包括位于数据包末尾的补位数据，所述控制寄存器还包括补位控制寄存器，所述补位控制寄存器存器在所述发送使能状态值为低电平时，存储所述微控制器写入的补位标志数据，用于标志是否进行末尾补位。
  16. 根据权利要求10所述的装置，其特征在于，所述参数计算模块包括触发周期计数器和计算子模块，所述频率调制参数包括所述触发周期计数器的装载设定值，所述触发周期计数器基于所述装载设定值进行计数，且计数溢出则触发所述计算子模块进行计算；
    所述计算子模块被触发后根据所述调制数据包和预设的调制配置参数，分别计算所述PWM输出定时器的重装载值和对应的装载设定值，并将所述装载设定值发送至所述触发周期计数器，将所述重装载值发送至所述PWM输出定时器。
  17. 根据权利要求16所述的装置，其特征在于，所述计算子模块包括配置寄存器和计算单元，所述配置寄存器包括周期数寄存器、周期差寄存器、基频寄存器、调制度寄存器及极性选择寄存器；
    所述调制配置参数包括所述周期数寄存器、所述周期差寄存器、所述基频寄存器、所述调制度寄存器及所述极性选择寄存器分别存储的调制周期数、调制周期差、设置基频、调制度及调制极性。
  18. 根据权利要求17所述的装置，其特征在于，所述计算子模块还包括中间变量寄存器，所述计算单元基于所述调制极性，计算待发送的比特数据对应的逻辑值，并将所述逻辑值写入所述中间变量寄存器，记录输出频率的逻辑高低；
    根据预设的调制配置参数，计算相应调制极性下所述逻辑值对应的所述重装载值和所述装载设定值。
  19. 一种调制信号处理方法，其特征在于，所述方法包括：
    接收到模拟数字转换器输出的完成标志，并采集所述模拟数字转换器输出的转换值，以及根据总采样次数和预设半周期值生成对应的比特数据；和/或
    将所述比特数据转换为符合Qi协议的调制数据包，并根据所述调制数据包和预设的调制配置参数，分别计算所述PWM输出定时器的重装载值和对应的频率调制参数，以使所述PWM输出定时器输出相应的脉宽调制信号。
  20. 一种微控制器，其特征在于，其上集成有如权利要求1-18任一项所述的调制信号处理装置。
  21. 一种电子设备，包括存储器、处理器及存储在所述存储器上并可在所述处理器上运行的计算机程序，其特征在于，还包括数字逻辑电路，且所述数字逻辑电路包括如权利要求1-18任一项所述的调制信号处理装置。
PCT/CN2023/075170 2022-03-30 2023-02-09 调制信号处理装置、方法、微控制器及电子设备 WO2023185263A1 (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
CN202210322921.4 2022-03-30
CN202210322921.4A CN114500204B (zh) 2022-03-30 2022-03-30 Fsk数据发送控制装置、方法、定时器、mcu及设备
CN202210338142.3A CN114500201B (zh) 2022-04-01 2022-04-01 Ask数据解码装置、方法、微控制器及设备
CN202210338142.3 2022-04-01

Publications (1)

Publication Number Publication Date
WO2023185263A1 true WO2023185263A1 (zh) 2023-10-05

Family

ID=88199100

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2023/075170 WO2023185263A1 (zh) 2022-03-30 2023-02-09 调制信号处理装置、方法、微控制器及电子设备

Country Status (1)

Country Link
WO (1) WO2023185263A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117596112A (zh) * 2024-01-19 2024-02-23 北京融为科技有限公司 调制度确定方法及装置

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080116841A1 (en) * 2006-11-20 2008-05-22 Matsushita Electric Industrial Co., Ltd. Semiconductor device, motor drive device and air conditioning machine
US20200036287A1 (en) * 2016-09-28 2020-01-30 B.G. Negev Technologies And Applications Ltd., At Ben-Gurion University Digital average current-mode control voltage regulator and a method for tuning compensation coefficients thereof
CN112013957A (zh) * 2020-09-29 2020-12-01 吉林大学 多通道采集快速解调检测系统、检测方法以及光谱仪
CN112106299A (zh) * 2018-06-22 2020-12-18 德州仪器公司 模数转换器的可配置过采样
CN114500204A (zh) * 2022-03-30 2022-05-13 浙江地芯引力科技有限公司 Fsk数据发送控制装置、方法、定时器、mcu及设备
CN114500201A (zh) * 2022-04-01 2022-05-13 浙江地芯引力科技有限公司 Ask数据解码装置、方法、微控制器及设备

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080116841A1 (en) * 2006-11-20 2008-05-22 Matsushita Electric Industrial Co., Ltd. Semiconductor device, motor drive device and air conditioning machine
US20200036287A1 (en) * 2016-09-28 2020-01-30 B.G. Negev Technologies And Applications Ltd., At Ben-Gurion University Digital average current-mode control voltage regulator and a method for tuning compensation coefficients thereof
CN112106299A (zh) * 2018-06-22 2020-12-18 德州仪器公司 模数转换器的可配置过采样
CN112013957A (zh) * 2020-09-29 2020-12-01 吉林大学 多通道采集快速解调检测系统、检测方法以及光谱仪
CN114500204A (zh) * 2022-03-30 2022-05-13 浙江地芯引力科技有限公司 Fsk数据发送控制装置、方法、定时器、mcu及设备
CN114500201A (zh) * 2022-04-01 2022-05-13 浙江地芯引力科技有限公司 Ask数据解码装置、方法、微控制器及设备

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117596112A (zh) * 2024-01-19 2024-02-23 北京融为科技有限公司 调制度确定方法及装置
CN117596112B (zh) * 2024-01-19 2024-04-05 北京融为科技有限公司 调制度确定方法及装置

Similar Documents

Publication Publication Date Title
US10635630B2 (en) Flexible protocol and associated hardware for one-wire radio frequency front-end interface
WO2023185263A1 (zh) 调制信号处理装置、方法、微控制器及电子设备
US20190377703A1 (en) Methods and apparatus for reduced-latency data transmission with an inter-processor communication link between independently operable processors
US11119966B2 (en) Mixed-mode radio frequency front-end interface
US10579581B2 (en) Multilane heterogeneous serial bus
US20170104607A1 (en) Methods to avoid i2c void message in i3c
CN111953629B (zh) 一种基于Qi标准的无线充电设备的FSK解调器及其解调方法
KR20190006487A (ko) 라인 멀티플렉싱된 uart 플로우 제어를 위한 디지털 시그널링 방식들
US9426082B2 (en) Low-voltage differential signaling or 2-wire differential link with symbol transition clocking
WO2023125529A1 (zh) 无线电通信的信号解调方法、电路、装置、设备及介质
US10169273B2 (en) Forced compression of single I2C writes
US10684981B2 (en) Fast termination of multilane single data rate transactions
CN103780350A (zh) 基于音频接口的通信装置及方法
US20190220436A1 (en) Data lane validation procedure for multilane protocols
US20190095273A1 (en) Parity bits location on i3c multilane bus
CN114500201B (zh) Ask数据解码装置、方法、微控制器及设备
US20200097434A1 (en) Enhanced high data rate technique for i3c
CN114500204B (zh) Fsk数据发送控制装置、方法、定时器、mcu及设备
US20230259480A1 (en) Bi-phase Mark Code Asynchronous Decoder using SPI Block
JP6227792B2 (ja) 遷移が最小化された低速データ伝送
CN203761413U (zh) 基于音频接口的通信装置
US20180357121A1 (en) Error correction calculation upon serial bus abort
CN110365710A (zh) 多协议聚合传输装置、系统及方法
CN210405365U (zh) 多协议聚合传输装置及系统
US20190377702A1 (en) I3c single data rate write flow control

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 23777642

Country of ref document: EP

Kind code of ref document: A1