WO2023185016A1 - 一种存储阵列的供电方法、装置及服务器 - Google Patents

一种存储阵列的供电方法、装置及服务器 Download PDF

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WO2023185016A1
WO2023185016A1 PCT/CN2022/133473 CN2022133473W WO2023185016A1 WO 2023185016 A1 WO2023185016 A1 WO 2023185016A1 CN 2022133473 W CN2022133473 W CN 2022133473W WO 2023185016 A1 WO2023185016 A1 WO 2023185016A1
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Prior art keywords
power supply
power
storage array
control
data
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PCT/CN2022/133473
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English (en)
French (fr)
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华要宇
王瑞杰
崔学涛
王鲁泮
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苏州浪潮智能科技有限公司
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Publication of WO2023185016A1 publication Critical patent/WO2023185016A1/zh

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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26Power supply means, e.g. regulation thereof
    • G06F1/30Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26Power supply means, e.g. regulation thereof
    • G06F1/32Means for saving power
    • G06F1/3203Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3206Monitoring of events, devices or parameters that trigger a change in power modality
    • G06F1/3215Monitoring of peripheral devices
    • G06F1/3225Monitoring of peripheral devices of memory devices
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26Power supply means, e.g. regulation thereof
    • G06F1/32Means for saving power
    • G06F1/3203Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234Power saving characterised by the action undertaken
    • G06F1/325Power saving in peripheral device
    • G06F1/3275Power saving in memory, e.g. RAM, cache
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26Power supply means, e.g. regulation thereof
    • G06F1/32Means for saving power
    • G06F1/3203Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234Power saving characterised by the action undertaken
    • G06F1/3293Power saving characterised by the action undertaken by switching to a less power-consuming processor, e.g. sub-CPU
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y04INFORMATION OR COMMUNICATION TECHNOLOGIES HAVING AN IMPACT ON OTHER TECHNOLOGY AREAS
    • Y04SSYSTEMS INTEGRATING TECHNOLOGIES RELATED TO POWER NETWORK OPERATION, COMMUNICATION OR INFORMATION TECHNOLOGIES FOR IMPROVING THE ELECTRICAL POWER GENERATION, TRANSMISSION, DISTRIBUTION, MANAGEMENT OR USAGE, i.e. SMART GRIDS
    • Y04S20/00Management or operation of end-user stationary applications or the last stages of power distribution; Controlling, monitoring or operating thereof
    • Y04S20/20End-user application control systems

Definitions

  • the present application relates to the field of storage, and in particular to a power supply method, device and server for a storage array.
  • Figure 1 is a schematic diagram of the power supply of a storage array in the prior art.
  • the input of the power grid is related to the APFC (Active Power Factor Correction).
  • the input end of the APFC circuit is connected, the output end of the APFC circuit is connected to the first end of the inverter circuit, the second end of the inverter circuit is connected to one end of the rectifier circuit, and the third end of the inverter circuit is connected to the drive circuit connection, the other end of the rectifier circuit is connected to one end of the control circuit of the power module, the other end of the control circuit is connected to the power module, the power module is connected to the storage array, and a controllable switch is also provided in the APFC circuit and the control circuit.
  • the switch participates in realizing the functions of the APFC circuit and the control circuit.
  • the input of the power grid is converted by the APFC circuit, driven by the drive circuit, then inverted and rectified, and output to the control circuit of the power module.
  • the power module is selected through the control circuit to complete the power supply.
  • the module provides power to the storage array.
  • the processor can be used to control the switching of the backup battery to power the storage array.
  • the step of switching the backup battery power supply is after the storage array is powered down.
  • the storage array Data may have been lost, increasing the risk of data loss.
  • the purpose of this application is to provide a power supply method, device and server for a storage array, which reduces the risk of power outage of the storage array and improves data security.
  • this application provides a power supply method for a storage array, which method includes:
  • the current power module is controlled to switch to other power modules or backup batteries.
  • obtaining status data used to characterize the power supply status of the power module includes:
  • Power-down trigger conditions include:
  • the power supply of the power grid stops or the power supply stability threshold is less than the preset threshold, the output of the power module stops, the output voltage does not reach the minimum power supply voltage required by the storage array or exceeds the maximum power supply voltage of the storage array, and is used to control multiple power supply modules.
  • the method before obtaining the status data used to characterize the power supply status of the power module, the method further includes:
  • the method further includes:
  • the power supply control method of the storage array includes:
  • the output data includes the bus output voltage. After obtaining the status data used to characterize the power supply status of the power module, it also includes:
  • PID control is performed on multiple power modules to stabilize the bus output voltages of multiple power modules.
  • the power supply control method is distributed logic parallel control, and the power supply control method of the storage array is re-determined based on the status data, including:
  • this application also provides a power supply device for a storage array, including:
  • Memory used to store computer programs
  • this application also provides a server, including the above-mentioned power supply device for the storage array.
  • This application provides a power supply method, device and server for a storage array.
  • status data used to characterize the power supply status of a power module is obtained. Based on the status data, it is determined whether the storage array reaches the power-down triggering condition. When the storage array reaches the power-down triggering condition, In this case, the current power module is controlled to switch to other power modules or backup batteries.
  • This solution can promptly switch to other power modules or backup batteries without abnormality to continue to supply power to the storage array when the storage array reaches the power-off trigger condition. , so that the power supply to the storage array does not stop, reducing the risk of power outage of the storage array and improving data security.
  • Figure 2 is a flow chart of a power supply method for a storage array provided by this application.
  • FIG. 4 is a schematic structural diagram of an interface protection circuit provided by this application.
  • FIG. 5 is a schematic structural diagram of another interface protection circuit provided by this application.
  • FIG. 6 is a schematic structural diagram of another interface protection circuit provided by this application.
  • FIG. 7 is a schematic structural diagram of another interface protection circuit provided by this application.
  • FIG. 8 is a schematic structural diagram of a power supply device for a storage array provided by this application.
  • the core of this application is to provide a power supply method, device and server for a storage array, which reduces the risk of power outage of the storage array and improves data security.
  • FIG. 2 is a flow chart of a power supply method for a storage array provided by this application.
  • the method includes:
  • S12 Determine whether the storage array reaches the power-down triggering condition based on the status data. If the storage array reaches the power-down triggering condition, enter S13;
  • the power module supplies power to the storage array, if the storage array loses power abnormally, the storage data in the storage array will be lost. If a power module or backup battery that can provide normal power supply is provided for the storage array before the storage array loses power, the storage array will lose power. This prevents the storage array from losing power and continuing to operate.
  • This application obtains status data used to characterize the power supply status of the power module, determines whether the storage array reaches the power-off trigger condition based on the status data, and controls the current power module to switch to other power sources when the storage array reaches the power-down trigger condition. The module or backup battery continues to provide power supply to the storage array before it loses power, allowing the storage array to continue working, reducing the risk of power outage of the storage array and improving data security.
  • the status data refers to the data that can characterize the power supply status of the power module. It can be the data of the power module itself or other data, such as the input of the power grid to the power supply. All the data on the transmission path between modules can represent the power supply status of the power module. These data can also reflect the power supply status of the power module.
  • the status data of the power supply status of the power module reaches the power-off trigger condition, it means that the storage array is about to If a power outage occurs, or the possibility of a power outage is high, the current power module is switched to another non-faulty power module or backup battery according to the specific status data, which improves the reliability of the solution.
  • the time of the power-off trigger condition is before the storage array is powered off, so the switching of the power module and backup power supply for the storage array occurs before the storage array is powered off, which improves the reliability of the solution.
  • This application provides a power supply method for a storage array.
  • status data used to characterize the power supply status of a power module is obtained. Based on the status data, it is determined whether the storage array reaches the power-down triggering condition. When the storage array reaches the power-down triggering condition, Control the current power module to switch to other power modules or backup batteries.
  • This solution can promptly switch to other power modules or backup batteries without abnormality to continue to power the storage array when the storage array reaches the power-off triggering condition, so that the storage array The power supply of the array does not stop, which reduces the risk of power outage of the storage array and improves data security.
  • Figure 3 is a schematic diagram of the power supply of a storage array provided by this application.
  • Figure 4 is a schematic structural diagram of an interface protection circuit provided by this application.
  • Figure 5 is a schematic structural diagram of another interface protection circuit provided by this application.
  • Figure 6 is a schematic structural diagram of another interface protection circuit provided by this application.
  • Figure 7 is a schematic structural diagram of another interface protection circuit provided by this application.
  • obtaining status data used to characterize the power supply status of the power module includes:
  • Power-down trigger conditions include:
  • the power supply of the power grid stops or the power supply stability threshold is less than the preset threshold, the output of the power module stops, the output voltage does not reach the minimum power supply voltage required by the storage array or exceeds the maximum power supply voltage of the storage array, and is used to control multiple power supply modules.
  • the input of the power grid is connected to the input end of APFC circuit 1, the output end of APFC circuit 1 is connected to the first end of inverter circuit 2, the second end of inverter circuit 2 is connected to one end of rectifier circuit 4, and the The third end is connected to the drive circuit 3, the other end of the rectifier circuit 4 is connected to one end of the control circuit 5 of the power module, the other end of the control circuit 5 is connected to the power module, and the power module is connected to the storage array.
  • Between the APFC circuit 1 and the control Circuit 5 is also equipped with a controllable switch, which improves the integrity of the solution.
  • the data of the driving circuit 3 is directly obtained through the processor 21 to determine whether the driving circuit 3 is abnormal, and other data, such as the power supply data of the power grid, the data of the multiple power modules, Output data, control signals for controlling multiple power modules, and temperature data of controllable switches are obtained through the sampling module 6 in the circuit.
  • the sampling module 6 is connected to the processor 21.
  • the sampling module 6 can include different types, such as collecting power grids.
  • the power supply data can include current sampling, voltage sampling and grid input frequency sampling.
  • Collecting the output data of multiple power modules can include current sampling and voltage sampling.
  • Collecting temperature data of controllable switches can use temperature sensors.
  • the sampling here Module 6 can be transformed accordingly according to the type of data that is to be collected, which improves the flexibility and feasibility of the solution.
  • the trigger conditions for power outage include the power supply of the power grid stopping or the power supply stability threshold being less than the preset threshold, the output of the power module stopping, and the output voltage not reaching the required level of the storage array.
  • the minimum supply voltage exceeds the maximum supply voltage of the storage array, the control signals used to control multiple power modules disappear, the temperature of the controllable switch is too high, and the drive of the power module is abnormal.
  • the grid power supply may have 220V power supply, 110V power supply or other power supply voltages depending on the country. If the power supply grid fails, the power module will not provide power and switch to the backup battery power supply. If the voltage of the grid is unstable, the power supply stability threshold Less than the preset threshold, that is, less than the stability value required by the power module and storage array, will also cause the storage array to lose power. At this time, the backup battery also needs to be switched.
  • the output data of multiple power modules is used to control multiple power supplies. Abnormalities in the module's control signals and the drive data of multiple power modules will also cause abnormal power outages of the storage array, improving the reliability and integrity of the solution.
  • the fifth switch Q5, the sixth switch Q6 and the control circuit 5 eliminate the impact of the power-on sequence on the PMUS, prevent abnormal power supply from affecting the storage system PMBUS (Power Management Bus, power management bus) link, and achieve the purpose of true redundant power supply.
  • the transient suppression diode D7 and the eighth transient suppression diode D8 are added to the circuit as TVS tubes to protect the circuit. They can protect the interface signal, prevent the impact of backflow on the circuit, protect the circuit, and improve the safety of the circuit. .
  • the seventh transient suppression diode D7 and the eighth transient suppression diode D8 can suppress the impact of lightning strikes, static electricity and other transient voltages on the SDA/SCl link.
  • the fifth switching tube Q5 and the sixth switching tube Q6 prevent abnormal power modules from communicating with the system. Link influence, the fourth transient suppression diode D4 and the third transient suppression diode D3 suppress the impact of lightning strikes, static electricity and other transient voltages on the Vin good signal.
  • the fourth resistor R4 and the first capacitor C1 form an Rc filter circuit, and the third switch
  • the tube Q3 and the fourth switching tube Q4 form an OR gate, and the hardware and software jointly monitor the working status of the power supply.
  • the sixth transient suppression diode D6 can suppress the impact of transient voltages such as lightning strikes and static electricity on the Pson signal.
  • the fifth transient suppression diode D5 has the same effect.
  • the clamping diode protects the Mcu pin.
  • the processor 21 receives the presence signal of the storage array, and at the same time, the PSON (Power Supply On, power on) debounce determination subroutine detects the PSON signal and performs software filtering and debounce processing. , determine whether the signal is an interference signal, detect the low level of the PSON signal, and the power module starts to work normally, indicating that the signal at this time is not an interference signal. If a non-low level state is detected, return to the initial process of the main program to continue processing the PSON signal. Detection indicates that it may not be a real presence signal, but an interference signal that is falsely triggered.
  • the PSON Power Supply On, power on
  • the steps are used to characterize the status data of the power supply status of the power module to facilitate subsequent steps and improve the reliability of the solution.
  • the method further includes:
  • a power supply control method suitable for the storage array can be re-determined through the status data, and intelligent switching can be performed, improving the reliability and automation of the solution.
  • the status data of the power supply mode determination subroutine is intelligently analyzed, and different control algorithm subroutines are called according to the analysis results.
  • the subroutine corresponding to the storage array is selected based on the status data, which improves the power supply efficiency. Since the appropriate power supply is selected for the storage array
  • the control method can also save electricity and avoid waste of resources.
  • the power supply control method of the storage array includes:
  • Distributed logic parallel control refers to multiple power modules supplying power at the same time.
  • Master-slave redundant parallel control refers to a single power module supplying power, and other power modules are in "standby" mode. ” status, so that power can be saved.
  • the current sharing control subroutine adds the current sharing bus voltage as a control parameter to the PID (proportional-integral-derivative, proportional-integral-derivative) control loop, and at the same time serves as a feedforward signal to improve the current-sharing accuracy when the load changes suddenly. If the control subroutine receives the master and backup host configuration instructions, it sends a cold redundant control signal; if it receives the master and backup slave configuration instructions, it adjusts the output voltage to be 0.3V lower than the normal output voltage to ensure the master-slave redundant parallel control power supply mode.
  • PID proportional-integral-derivative, proportional-integral-derivative
  • distributed logic parallel control is equivalent to the current sharing control subroutine
  • master-slave redundant parallel control is equivalent to the master-standby control subroutine
  • the output data includes the bus output voltage. After obtaining the status data used to characterize the power supply status of the power module, it also includes:
  • PID control is performed on multiple power modules to stabilize the bus output voltages of multiple power modules.
  • PID control can also be performed based on status data through the APFC control subroutine.
  • the output data of the power module includes the bus output voltage.
  • PID control can be performed on multiple power modules.
  • the power supply can be The bus output voltage of the module is stable. For example, if the normal operation of the storage array requires a voltage of 12V, the bus output voltage of the power module can be stabilized through PID control. Under normal circumstances, the output of the power module may have certain fluctuations. By controlling multiple PID control of the power module can reduce fluctuations and stabilize the voltage at 12V, making the power supply to the storage array more reliable and improving the feasibility of the solution.
  • the power supply control method is master-slave redundant parallel control.
  • the power supply control method of the storage array is determined based on the status data, including:
  • Different intelligent control algorithms are called under different power supply modes to ensure the accuracy of power supply parameters in different working modes.
  • the power supply control method is distributed logic parallel control
  • the first algorithm corresponding to distributed logic parallel control is called, and the power supply control method of the storage array is re-determined based on the first algorithm, and a power supply control method suitable for the storage array is determined to ensure that at this time Power supply parameter accuracy.
  • the power supply control mode is master-slave redundant parallel control
  • the second algorithm corresponding to master-slave redundant parallel control is called.
  • the power supply control mode of the storage array is re-determined to determine the power supply control suitable for the storage array. This method ensures the accuracy of the power supply parameters at this time. According to different intelligent control algorithms corresponding to different power supply modes, the accuracy of the power supply parameters at this time can be guaranteed and the reliability of the solution is improved.
  • the power supply control mode of the storage array is other mode control; correspondingly, after redetermining the power supply control mode of the storage array according to the status data, it also includes:
  • the power supply control mode of the storage array When the power supply control mode of the storage array is controlled by other modes, it means that the power supply to the storage array is abnormal at this time and is in a state of preparation for backup battery power supply.
  • the power supply control mode of the storage array is redetermined to be controlled by other modes based on the status data.
  • the abnormality is repaired through the self-diagnosis subroutine. This process is a repair process. If the abnormal problem can be solved at the software level of the processor 21, the abnormality can be repaired and the storage array can continue to be powered through the power module. , if the abnormality is repaired, it turns out to be a hardware problem or other more complex problem. At this time, the backup battery is controlled to power the storage array and the alarm module is controlled to alarm.
  • the self-diagnosis and repair subroutine intelligently controls the power supply working status interface signal based on the intelligent analysis results of the power supply working status and key parameters, updates the power supply status register based on the intelligent analysis results, and makes three attempts to repair the abnormal status, improving The reliability of the scheme.
  • FIG. 8 is a schematic structural diagram of a power supply device for a storage array provided by the present application.
  • Memory 22 used to store computer programs
  • the processor 21 is configured to execute a computer program to implement the steps of the above-mentioned power supply method for the storage array.
  • This application also provides a server, including the above-mentioned power supply device for the storage array.

Abstract

本发明公开了一种存储阵列的供电方法、装置及服务器,首先获取用于表征电源模块供电状态的状态数据,根据状态数据判定存储阵列是否达到掉电触发条件,在存储阵列达到掉电触发条件的情况下,控制当前的电源模块切换为其他的电源模块或者备用电池,本方案可以在存储阵列达到掉电触发条件时,及时的切换其他的没有异常的电源模块或者备用电池继续为存储阵列供电,使得对存储阵列的供电不停止,降低了存储阵列的掉电风险,提高了数据安全性。

Description

一种存储阵列的供电方法、装置及服务器
相关申请的交叉引用
本申请要求于2022年03月29日提交中国专利局、申请号202210315458.0、申请名称为“一种存储阵列的供电方法、装置及服务器”的中国专利申请的优先权,其全部内容通过引用结合在本申请中。
技术领域
本申请涉及存储领域,特别是涉及一种存储阵列的供电方法、装置及服务器。
背景技术
存储阵列正常工作时,需要使用电源模块为其供电,请参照图1,图1为现有技术一种存储阵列的供电示意图,现有技术中,电网的输入与APFC(Active Power Factor Correction,有源功率因数校正)电路的输入端连接,APFC电路的输出端与逆变电路的第一端连接,逆变电路的第二端与整流电路的一端连接,逆变电路的第三端与驱动电路连接,整流电路的另一端与电源模块的控制电路的一端连接,控制电路的另一端与电源模块连接,电源模块与存储阵列连接,在APFC电路和控制电路中还设置有可控开关,可控开关参与实现APFC电路和控制电路的功能,电网的输入经APFC电路转换,经驱动电路的驱动,再进行逆变和整流,输出到电源模块的控制电路,通过控制电路选择电源模块,进而完成电源模块为存储阵列的供电。
在发现存储阵列异常掉电之后,可以通过处理器控制切换备用电池为存储阵列供电,但是此时由于存储阵列已经掉电,切换备用电池供电的步骤在存储阵列掉电之后,此时存储阵列的数据可能已经丢失,提高了数据丢失风险性。
发明内容
本申请的目的是提供一种存储阵列的供电方法、装置及服务器,降低了存储阵列的掉电风险,提高了数据安全性。
为解决上述技术问题,本申请提供了一种存储阵列的供电方法,该方法包括:
获取用于表征电源模块供电状态的状态数据;
根据状态数据判断存储阵列是否达到掉电触发条件;
在存储阵列达到掉电触发条件的情况下,控制当前的电源模块切换为其他的电源模块或 者备用电池。
在一些实施例中,获取用于表征电源模块供电状态的状态数据,包括:
获取电网的供电数据、多个电源模块的输出数据、用于控制多个电源模块的控制信号、可控开关的温度数据及用于驱动多个电源模块的驱动数据;
掉电触发条件,包括:
电网的供电停止或者供电稳定性阈值小于预设阈值、电源模块的输出停止、输出电压未达到存储阵列所需的最小供电电压或者超过存储阵列的最大供电电压、用于控制多个电源模块的控制信号消失、可控开关的温度过高及电源模块的驱动异常。
在一些实施例中,获取用于表征电源模块供电状态的状态数据之前,还包括:
判断是否接收到存储阵列的在位的信号;
若接收到存储阵列的在位的信号,判断信号是否为干扰信号;
若为干扰信号,则返回判断是否接收到存储阵列的在位的信号的步骤;
若不为干扰信号,进入获取用于表征电源模块供电状态的状态数据的步骤。
在一些实施例中,获取用于表征电源模块供电状态的状态数据之后,还包括:
根据状态数据重新确定存储阵列的供电控制方式。
在一些实施例中,存储阵列的供电控制方式,包括:
分布式逻辑并联控制、主从冗余并联控制或者其他模式控制,其他模式控制为根据状态数据判定电源模块供电状态异常时启动的模式。
在一些实施例中,输出数据包括母线输出电压,获取用于表征电源模块供电状态的状态数据之后,还包括:
通过APFC控制子程序,并根据状态数据,对多个电源模块进行PID控制以使多个电源模块的母线输出电压稳定。
在一些实施例中,供电控制方式为分布式逻辑并联控制,根据状态数据重新确定存储阵列的供电控制方式,包括:
调用对应分布式逻辑并联控制的第一算法;
根据第一算法重新确定存储阵列的供电控制方式;
供电控制方式为主从冗余并联控制,根据状态数据确定存储阵列的供电控制方式,包括:
调用对应主从冗余并联控制的第二算法;
根据第二算法重新确定存储阵列的供电控制方式。
在一些实施例中,存储阵列的供电控制方式为其他模式控制;对应的,根据状态数据重新确定存储阵列的供电控制方式之后,还包括:
通过自诊断子程序修复异常;
判断异常是否修复;
若完成异常修复,继续通过电源模块为存储阵列供电;
若没有异常修复,控制备用电池为存储阵列供电并控制报警模块报警。
为解决上述技术问题,本申请还提供了一种存储阵列的供电装置,包括:
存储器,用于存储计算机程序;
处理器,用于执行计算机程序以实现上述存储阵列的供电方法的步骤。
为解决上述技术问题,本申请还提供了一种服务器,包括上述的存储阵列的供电装置。
本申请提供了一种存储阵列的供电方法、装置及服务器,首先获取用于表征电源模块供电状态的状态数据,根据状态数据判定存储阵列是否达到掉电触发条件,在存储阵列达到掉电触发条件的情况下,控制当前的电源模块切换为其他的电源模块或者备用电池,本方案可以在存储阵列达到掉电触发条件时,及时的切换其他的没有异常的电源模块或者备用电池继续为存储阵列供电,使得对存储阵列的供电不停止,降低了存储阵列的掉电风险,提高了数据安全性。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分,示出了符合本申请的实施例,并与说明书一起用于解释本申请的原理。
为了更清楚地说明本申请实施例中的技术方案,下面将对现有技术和实施例中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本申请的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。
图1为现有技术一种存储阵列的供电示意图;
图2为本申请提供的一种存储阵列的供电方法的流程图;
图3为本申请提供的一种存储阵列的供电示意图;
图4为本申请提供的一种接口保护电路的结构示意图;
图5为本申请提供的另一种接口保护电路的结构示意图;
图6为本申请提供的另一种接口保护电路的结构示意图;
图7为本申请提供的另一种接口保护电路的结构示意图;
图8为本申请提供的一种存储阵列的供电装置的结构示意图。
具体实施方式
本申请的核心是提供一种存储阵列的供电方法、装置及服务器,降低了存储阵列的掉电风险,提高了数据安全性。
为使本申请实施例的目的、技术方案和优点更加清楚,下面将结合本申请实施例中的附图,对本申请实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例是本申请一部分实施例,而不是全部的实施例。基于本申请中的实施例,本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例,都属于本申请保护的范围。
请参照图2,图2为本申请提供的一种存储阵列的供电方法的流程图。该方法包括:
S11:获取用于表征电源模块供电状态的状态数据;
S12:根据状态数据判断存储阵列是否达到掉电触发条件,若存储阵列达到掉电触发条件,进入S13;
S13:控制当前的电源模块切换为其他的电源模块或者备用电池。
电源模块为存储阵列供电时,如果存储阵列异常掉电,就会导致存储阵列的存储数据丢失,如果在存储阵列掉电之前,为存储阵列提供一个可以正常供电的电源模块或者备用电池,就会使得存储阵列不掉电,继续运行。本申请通过获取用于表征电源模块供电状态的状态数据,根据状态数据判定存储阵列是否达到掉电触发条件,在存储阵列达到掉电触发条件的情况下,控制当前的电源模块切换为其他的电源模块或者备用电池,在存储阵列掉电之前继续为其提供供电电源,使存储阵列继续工作,降低了存储阵列的掉电风险,提高了数据安全性。
具体的,首先获取用于表征电源模块供电状态的状态数据,状态数据指的是可以表征电源模块供电状态的数据,可以是电源模块本身的数据也可以是其他的数据,比如电网的输入到电源模块之间的传输路径上的所有可以表征电源模块供电状态的数据,通过这些数据也可以反应出电源模块的供电状态,之后电源模块供电状态的状态数据达到掉电触发条件,就说明存储阵列即将会发生掉电,或者发生掉电的可能性较大,就根据状态数据的具体情况切换当前的电源模块为其他的没有故障的电源模块或者备用电池,提高了方案的可靠性。
需要说明的是,掉电触发条件的时间在存储阵列掉电之前,所以为存储阵列切换电源模 块和备用电源的时间发生在存储阵列掉电之前,提高了方案的可靠性。
本申请提供了一种存储阵列的供电方法,首先获取用于表征电源模块供电状态的状态数据,根据状态数据判定存储阵列是否达到掉电触发条件,在存储阵列达到掉电触发条件的情况下,控制当前的电源模块切换为其他的电源模块或者备用电池,本方案可以在存储阵列达到掉电触发条件时,及时的切换其他的没有异常的电源模块或者备用电池继续为存储阵列供电,使得对存储阵列的供电不停止,降低了存储阵列的掉电风险,提高了数据安全性。
在上述实施例的基础上:
请参照图3、图4、图5、图6及图7,图3为本申请提供的一种存储阵列的供电示意图,图4为本申请提供的一种接口保护电路的结构示意图,图5为本申请提供的另一种接口保护电路的结构示意图,图6为本申请提供的另一种接口保护电路的结构示意图,图7为本申请提供的另一种接口保护电路的结构示意图。
在一些实施例中,获取用于表征电源模块供电状态的状态数据,包括:
获取电网的供电数据、多个电源模块的输出数据、用于控制多个电源模块的控制信号、可控开关的温度数据及用于驱动多个电源模块的驱动数据;
掉电触发条件,包括:
电网的供电停止或者供电稳定性阈值小于预设阈值、电源模块的输出停止、输出电压未达到存储阵列所需的最小供电电压或者超过存储阵列的最大供电电压、用于控制多个电源模块的控制信号消失、可控开关的温度过高及电源模块的驱动异常。
电源模块为存储阵列供电的具体实现是,电网的输入经APFC电路1转换,经驱动电路3的驱动,再进行逆变和整流,输出到电源模块的控制电路5,通过控制电路5选择电源模块,进而完成电源模块为存储阵列的供电,可控开关参与实现APFC电路1和控制电路5的功能。从电网的输入到电源模块,中间的过程的数据包括电网的供电数据、多个电源模块的输出数据、用于控制多个电源模块的控制信号、可控开关的温度数据及用于驱动多个电源模块的驱动数据,这些数据都可以用以反应电源模块的供电状态,只要在电网的输入到电源模块之间的电路哪一个出现了影响电源模块为存阵列供电的问题,都视为存储阵列即将掉电,之后在存储阵列掉电之前切换其他的电源模块或者备用电池为存储阵列供电,提高了方案的可靠性。
电网的输入与APFC电路1的输入端连接,APFC电路1的输出端与逆变电路2的第一端连接,逆变电路2的第二端与整流电路4的一端连接,逆变电路2的第三端与驱动电路3连 接,整流电路4的另一端与电源模块的控制电路5的一端连接,控制电路5的另一端与电源模块连接,电源模块与存储阵列连接,在APFC电路1和控制电路5中还设置有可控开关,提高了方案的完整性。
另外,在获取用于驱动多个电源模块的驱动数据时是通过处理器21直接获取驱动电路3的数据,判断驱动电路3是否异常,而其他的数据,电网的供电数据、多个电源模块的输出数据、用于控制多个电源模块的控制信号、可控开关的温度数据通过电路中的采样模块6获取,采样模块6和处理器21连接,采样模块6可以包括不同的种类,比如采集电网的供电数据就可以包括电流采样和电压采样和电网的输入的频率采样,采集多个电源模块的输出数据可以包括电流采样和电压采样,采集可控开关的温度数据可以通过温度传感器,这里的采样模块6可以根据具体想要采集的数据的类型而相适应的变换,提高了方案的灵活性与可行性。
根据获取的电网的供电数据、多个电源模块的输出数据、用于控制多个电源模块的控制信号、可控开关的温度数据及用于驱动多个电源模块的驱动数据的具体情况,就可以分析出是否存在问题需要为存储阵列切换电源模块和备用电池,掉电触发条件,包括电网的供电停止或者供电稳定性阈值小于预设阈值、电源模块的输出停止、输出电压未达到存储阵列所需的最小供电电压或者超过存储阵列的最大供电电压、用于控制多个电源模块的控制信号消失、可控开关的温度过高及电源模块的驱动异常。具体的,电网供电根据国家的不同可能会有220V供电和110V供电或者其他供电电压,如果供电电网故障,电源模块都不会在供电,切换备用电池供电,电网的电压如果不稳定供电稳定性阈值小于预设阈值,也就是小于电源模块和存储阵列所需的稳定性值,也会导致存储阵列掉电,这时候也需要切换备用电池,多个电源模块的输出数据、用于控制多个电源模块的控制信号及多个电源模块的驱动数据异常时,也会导致存储阵列异常掉电,提高了方案的可靠性与完整性。
可控开关设置在APFC电路1和控制电路5中,属于电路中的关键元器件,这些元器件的温度过高时,也会使得存储阵列掉电,同时,电路异常时,关键元器件比较容易发生温度变化,通过检测关键元器件的温度变化可以较好的反映出存储阵列的供电是否异常,提高了方案的可靠性。
另外,本申请在电路中增加多出保护电路,第一瞬态抑制二极管D1、第二瞬态抑制二极管D2、第三瞬态抑制二极管D3、第四瞬态抑制二极管D4、第五瞬态抑制二极管D5、第六瞬态抑制二极管D6、第七瞬态抑制二极管D7、第八瞬态抑制二极管D8是增加的增加TVS(Transient Voltage Suppressor,瞬态抑制二极管),防止静电、热拔损坏电源控制信号 管脚。第五开关管Q5、第六开关管Q6及控制电路5消除上电时序对PMUS影响,防止异常电源影响存储系统PMBUS(Power Management Bus,电源管理总线)链路,达到真正冗余供电目的。智能PWOK(Power ok,电源正常)信号控制电路5,12V出现异常,PWOK异常信号第一时间发出,消除软件延时影响。
第一瞬态抑制二极管D1、第二瞬态抑制二极管D2、第三瞬态抑制二极管D3、第四瞬态抑制二极管D4、第五瞬态抑制二极管D5、第六瞬态抑制二极管D6、第七瞬态抑制二极管D7、第八瞬态抑制二极管D8作为TVS管加入电路,起到保护电路的作用,可以保护接口信号,还有防止回流对电路造成的影响,保护电路,提高了电路的安全性。
第七瞬态抑制二极管D7和第八瞬态抑制二极管D8可以抑制雷击、静电等瞬态电压对SDA/SCl链路影响,第五开关管Q5和第六开关管Q6防止异常电源模块对系统通讯链路影响,第四瞬态抑制二极管D4和第三瞬态抑制二极管D3抑制雷击、静电等瞬态电压对Vin good信号影响,第四电阻R4与第一电容C1组成Rc滤波电路,第三开关管Q3和第四开关管Q4组成或门,硬件软件共同监控电源工作状态,第六瞬态抑制二极管D6可以抑制雷击、静电等瞬态电压对Pson信号影响,第五瞬态抑制二极管D5作用相当于钳位二极管,保护Mcu管脚。
在一些实施例中,获取用于表征电源模块供电状态的状态数据之前,还包括:
判断是否接收到存储阵列的在位的信号;
若接收到存储阵列的在位的信号,判断信号是否为干扰信号;
若为干扰信号,则返回判断是否接收到存储阵列的在位的信号的步骤;
若不为干扰信号,进入获取用于表征电源模块供电状态的状态数据的步骤。
在软件层面,存储阵列与电源模块连接时,处理器21接收存储阵列的在位的信号,同时PSON(Power Supply On,开动电源)消抖判定子程序对PSON信号进行侦测软件滤波消抖处理,判断信号是否为干扰信号,检测到PSON信号低电平,电源模块开始正常工作,说明此时的信号不是干扰信号,检测到非低电平状态,返回到主程序初始流程继续对PSON信号进行侦测,说明可能并不是真正的在位信号,是一种误触发的干扰信号,返回判断是否接收到存储阵列的在位的信号的步骤,继续进行判断,若不为干扰信号,进入获取用于表征电源模块供电状态的状态数据的步骤,以便于后续步骤,提高了方案的可靠性。
在一些实施例中,获取用于表征电源模块供电状态的状态数据之后,还包括:
根据状态数据重新确定存储阵列的供电控制方式。
根据状态数据可以在存储阵列与电源模块连接之后,经过状态数据重新确定一个适合该 存储阵列的供电控制方式,可以进行智能的切换,提高了方案的可靠性和自动化程度。
在软件层面,供电模式判定子程序状态数据进行智能分析,根据分析结果调用不同控制算法子程序,结合状态数据选择与存储阵列对应的子程序,提高了供电效率,由于针对存储阵列选择恰当的供电控制方式,还可以节约电能,避免资源浪费。
在一些实施例中,存储阵列的供电控制方式,包括:
分布式逻辑并联控制、主从冗余并联控制或者其他模式控制,其他模式控制为根据状态数据判定电源模块供电状态异常时启动的模式。
多个电源模块可以有不同的供电控制方式,其中分布式逻辑并联控制指的是多个电源模块同时供电,主从冗余并联控制指的是单独一个电源模块供电,其他的电源模块处于“待机”状态,这样就可以节约电能。
在软件层面,均流控制子程序把均流母线电压作为控制参数加至PID(proportional-integral-derivative,比例积分微分)控制环,同时作为前馈信号提高在负载突变时均流精度,主备控制子程序如收到主备主机配置指令,发出冷冗余控制信号;如收到主备从机配置指令,调整输出电压比正常输出电压低0.3V,保证主从冗余并联控制供电模式。
在软件层面,需要说明的是,分布式逻辑并联控制相当于均流控制子程序,主从冗余并联控制相当于主备控制子程序。
在一些实施例中,输出数据包括母线输出电压,获取用于表征电源模块供电状态的状态数据之后,还包括:
通过APFC控制子程序,并根据状态数据,对多个电源模块进行PID控制以使多个电源模块的母线输出电压稳定。
多个电源模块在供电时,在软件层面,还可以通过APFC控制子程序,根据状态数据进行PID控制,电源模块的输出数据其中包括母线输出电压,对多个电源模块进行PID控制,可以将电源模块的母线输出电压稳定,例如,如果存储阵列的正常工作需要12V的电压,通过PID控制可以使电源模块的母线输出电压稳定,正常情况下电源模块的输出可能存在一定的波动,通过对多个电源模块进行PID控制就可以减少波动将电压稳定在12V,以对存储阵列供电时更加可靠,提高了方案的可行性。
在一些实施例中,供电控制方式为分布式逻辑并联控制,根据状态数据重新确定存储阵列的供电控制方式,包括:
调用对应分布式逻辑并联控制的第一算法;
根据第一算法重新确定存储阵列的供电控制方式;
供电控制方式为主从冗余并联控制,根据状态数据确定存储阵列的供电控制方式,包括:
调用对应主从冗余并联控制的第二算法;
根据第二算法重新确定存储阵列的供电控制方式。
不同供电模式下调用不同智能控制算法,保证不同工作模式电源参数精度。供电控制方式为分布式逻辑并联控制时,调用对应分布式逻辑并联控制的第一算法,根据第一算法重新确定存储阵列的供电控制方式,确定出适合存储阵列的供电控制方式,保证此时的电源参数精度,供电控制方式为主从冗余并联控制时,调用对应主从冗余并联控制的第二算法,根据第二算法重新确定存储阵列的供电控制方式,确定出适合存储阵列的供电控制方式,保证此时的电源参数精度,根据对应不同供电模式下调用不同智能控制算法,可以保证此时的电源参数精度,提高了方案的可靠性。
在一些实施例中,存储阵列的供电控制方式为其他模式控制;对应的,根据状态数据重新确定存储阵列的供电控制方式之后,还包括:
通过自诊断子程序修复异常;
判断异常是否修复;
若完成异常修复,继续通过电源模块为存储阵列供电;
若没有异常修复,控制备用电池为存储阵列供电并控制报警模块报警。
存储阵列的供电控制方式为其他模式控制时,说明此时对存储阵列的供电已经异常,处于一种备用电池供电的准备状态,根据状态数据重新确定存储阵列的供电控制方式为其他模式控制时,在软件层面,通过自诊断子程序修复异常,该过程为尝试修复的过程,如果异常问题是可以在处理器21的软件层面上可以解决的,异常就可以修复,继续通过电源模块为存储阵列供电,如果异常取法修复,证明是硬件上的问题或者其他较为复杂的问题,这时控制备用电池为存储阵列供电并控制报警模块报警,首先要保证存储阵列不断电,保证供电可靠性和存储数据的安全性,然后同时控制报警模块报警,以便于用户及时发现问题,进行相适应的维护,备用电池有一定的使用寿命,维护之后才可以再次利用电源模块供电,提高了方案的完整性。
在软件层面,自诊断修复子程序根据电源工作状态、关键参数智能分析结果,智能控制发出电源工作状态接口信号,同时根据智能分析结果更新电源状态寄存器,并对异常状态进行三次尝试修复,提高了方案的可靠性。
请参照图8,图8为本申请提供的一种存储阵列的供电装置的结构示意图。
本申请还提供了一种存储阵列的供电装置,包括:
存储器22,用于存储计算机程序;
处理器21,用于执行计算机程序以实现上述存储阵列的供电方法的步骤。
对于本申请提供的存储阵列的供电装置的介绍请参考上述存储阵列的供电方法的实施例,此处不再赘述。
本申请还提供了一种服务器,包括上述的存储阵列的供电装置。
对于本申请提供的服务器的介绍请参考上述存储阵列的供电方法的实施例,此处不再赘述。
本说明书中各个实施例采用递进的方式描述,每个实施例重点说明的都是与其他实施例的不同之处,各个实施例之间相同相似部分互相参见即可。对于实施例公开的装置而言,由于其与实施例公开的方法相对应,所以描述的比较简单,相关之处参见方法部分说明即可。
专业人员还可以进一步意识到,结合本文中所公开的实施例描述的各示例的单元及算法步骤,能够以电子硬件、计算机软件或者二者的结合来实现,为了清楚地说明硬件和软件的可互换性,在上述说明中已经按照功能一般性地描述了各示例的组成及步骤。这些功能究竟以硬件还是软件方式来执行,取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能,但是这种实现不应认为超出本申请的范围。

Claims (20)

  1. 一种存储阵列的供电方法,其特征在于,包括:
    获取用于表征电源模块供电状态的状态数据;
    根据所述状态数据判断所述存储阵列是否达到掉电触发条件;
    在所述存储阵列达到所述掉电触发条件的情况下,控制当前的所述电源模块切换为其他的所述电源模块或者备用电池。
  2. 如权利要求1所述的存储阵列的供电方法,其特征在于,获取用于表征电源模块供电状态的状态数据,包括:
    获取电网的供电数据、多个所述电源模块的输出数据、用于控制多个所述电源模块的控制信号、可控开关的温度数据及用于驱动多个所述电源模块的驱动数据;
    所述掉电触发条件,包括:
    电网的供电停止或者供电稳定性阈值小于预设阈值、所述电源模块的输出停止、输出电压未达到所述存储阵列所需的最小供电电压或者超过所述存储阵列的最大供电电压、用于控制多个所述电源模块的控制信号消失、所述可控开关的温度过高及所述电源模块的驱动异常。
  3. 如权利要求1所述的存储阵列的供电方法,其特征在于,获取用于表征电源模块供电状态的状态数据之前,还包括:
    判断是否接收到所述存储阵列的在位的信号;
    若接收到所述存储阵列的在位的信号,判断所述信号是否为干扰信号;
    若为干扰信号,则返回判断是否接收到所述存储阵列的在位的信号的步骤;
    若不为干扰信号,进入获取用于表征电源模块供电状态的状态数据的步骤。
  4. 如权利要求3所述的存储阵列的供电方法,其特征在于,若接收到所述存储阵列的在位的信号,判断所述信号是否为干扰信号,包括:
    若所述信号为低电平状态,确定所述信号为非干扰信号;
    若所述信号为非低电平状态,确定所述信号为干扰信号。
  5. 如权利要求1所述的存储阵列的供电方法,其特征在于,获取用于表征电源模块供电状态的状态数据之后,还包括:
    根据所述状态数据重新确定所述存储阵列的供电控制方式。
  6. 如权利要求1所述的存储阵列的供电方法,其特征在于,根据所述状态数据重新确定所述存储阵列的供电控制方式,包括:
    根据所述状态数据确定控制算法子程序;
    根据控制算法子程序确定所述存储阵列的供电控制方式。
  7. 如权利要求5所述的存储阵列的供电方法,其特征在于,所述存储阵列的供电控制方式,包括:
    分布式逻辑并联控制、主从冗余并联控制或者其他模式控制,所述其他模式控制为根据所述状态数据判定所述电源模块供电状态异常时启动的模式。
  8. 如权利要求7所述的存储阵列的供电方法,其特征在于,所述分布式逻辑并联控制为多个电源模块同时供电的供电控制方式;所述主从冗余并联控制为单独一个电源模块供电,其他的电源模块处于待机状态的供电控制方式。
  9. 如权利要求7所述的存储阵列的供电方法,其特征在于,所述方法还包括:
    所述分布式逻辑并联控制将均流母线电压作为控制参数添加至PID控制环,以及将均流母线电压作为前馈信号以提高在负载突变时的均流精度。
  10. 如权利要求7所述的存储阵列的供电方法,其特征在于,所述方法还包括:
    若所述主从冗余并联控制接收到主备主机配置指令,则发出冷冗余控制信号;
    若所述主从冗余并联控制接收到主备从机配置指令,调整输出电压比正常输出电压低预设电压。
  11. 如权利要求2所述的存储阵列的供电方法,其特征在于,所述输出数据包括母线输出电压,获取用于表征电源模块供电状态的状态数据之后,还包括:
    通过APFC控制子程序,并根据所述状态数据,对多个所述电源模块进行PID控制以使多个所述电源模块的母线输出电压稳定。
  12. 如权利要求7所述的存储阵列的供电方法,其特征在于,所述供电控制方式为所述分布式逻辑并联控制,根据所述状态数据重新确定所述存储阵列的供电控制方式,包括:
    调用对应所述分布式逻辑并联控制的第一算法;
    根据所述第一算法重新确定所述存储阵列的供电控制方式;
    所述供电控制方式为所述主从冗余并联控制,根据所述状态数据确定所述存储阵列的供电控制方式,包括:
    调用对应所述主从冗余并联控制的第二算法;
    根据所述第二算法重新确定所述存储阵列的供电控制方式。
  13. 如权利要求7所述的存储阵列的供电方法,其特征在于,所述存储阵列的供电控制方式为所述其他模式控制;对应的,所述根据所述状态数据重新确定所述存储阵列的供电控制方式之后,还包括:
    通过自诊断子程序修复异常。
  14. 如权利要求13所述的存储阵列的供电方法,其特征在于,所述通过自诊断子程序修复异常的步骤之后,还包括:
    判断所述异常是否修复;
    若完成异常修复,继续通过所述电源模块为所述存储阵列供电;
    若没有异常修复,控制所述备用电池为所述存储阵列供电并控制报警模块报警。
  15. 如权利要求1所述的存储阵列的供电方法,其特征在于,电源模块为存储阵列供电的具体实现过程为:
    电网的输入经APFC电路转换,经驱动电路的驱动,再进行逆变和整流,输出到所述电源模块的控制电路,通过控制电路选择电源模块,所述电源模块为存储阵列的供电。
  16. 如权利要求2所述的存储阵列的供电方法,其特征在于,获取电网的供电数据、多个所述电源模块的输出数据、用于控制多个所述电源模块的控制信号、可控开关的温度数据及用于驱动多个所述电源模块的驱动数据,包括:
    通过电路中的采样模块获取所述电网的供电数据、所述多个所述电源模块的输出数据、所述用于控制多个所述电源模块的控制信号、所述可控开关的温度数据;所述采样模块和处理器连接;
    通过所述处理器获取所述用于驱动多个所述电源模块的驱动数据。
  17. 如权利要求16所述的存储阵列的供电方法,其特征在于,通过电路中的采样模块获取所述电网的供电数据、所述多个所述电源模块的输出数据、所述用于控制多个所述电源模块的控制信号、所述可控开关的温度数据,包括:
    采用电流采样,和/或电压采样,和/或电网的输入的频率采样采集所述电网的供电数据;
    采用电流采样,和/或电压采样采集所述多个所述电源模块的输出数据;
    采用温度传感器采集所述可控开关的温度数据。
  18. 如权利要求1所述的存储阵列的供电方法,其特征在于,所述方法还包括:
    在电路中增加用于防止静电、热拔损坏电源控制信号管脚的第一保护电路、用于消除上电时序的第二保护电路、用于消除软件延时影响的第三保护电路。
  19. 一种存储阵列的供电装置,其特征在于,包括:
    存储器,用于存储计算机程序;
    处理器,用于执行所述计算机程序以实现上述1至17任一项所述存储阵列的供电方法的步骤。
  20. 一种服务器,其特征在于,包括如权利要求19所述的存储阵列的供电装置。
PCT/CN2022/133473 2022-03-29 2022-11-22 一种存储阵列的供电方法、装置及服务器 WO2023185016A1 (zh)

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