WO2023184414A1

WO2023184414A1 - Chip package structure, electronic device, and preparation method for chip package structure

Info

Publication number: WO2023184414A1
Application number: PCT/CN2022/084602
Authority: WO
Inventors: 朱泽; 范吉磊; 郭茂; 赵南
Original assignee: 华为技术有限公司
Priority date: 2022-03-31
Filing date: 2022-03-31
Publication date: 2023-10-05

Abstract

Embodiments of the present application relate to the technical field of chip package, and provide a chip package structure, an electronic device, and a preparation method for a chip package structure, capable of reducing the risk of delamination of a thermal interface material (TIM). The chip package structure comprises a substrate, a plurality of chips disposed on the substrate, a heat dissipation cover disposed on the substrate and configured to dissipate heat of the plurality of chips, and a TIM layer configured to form a heat dissipation channel. The side of the central portion of the heat dissipation cover facing the substrate is provided with a protruding portion. The protruding portion abuts against the TIM layer of the chips to press the TIM layer material. Since there is a protruding portion capable of abutting against the TIM layer, after the heat dissipation cover covers the chip, when other structural parts are mounted on the heat dissipation cover, the structural parts apply pressure towards the chip to the heat dissipation cover. In this way, the protruding portion deforms to generate an abutting force to the TIM layer to be tightly attached to the TIM layer. Therefore, the protruding portion facilitates reducing the possibility of delamination of the TIM.

Description

Chip packaging structure, electronic equipment and preparation method of chip packaging structure

Technical field

The present application relates to the field of chip packaging technology, and in particular to a chip packaging structure, electronic equipment and a method for preparing the chip packaging structure.

Background technique

As the demand for computing power from high-speed data communications and artificial intelligence surges, chip integration has further increased. Among them, multi-chip packaging technology is widely used. Multi-chip packaging can also be called multi-chip module (MCM) packaging. MCM packaging can effectively shorten the interconnection wiring length between traditional single chips, providing high-density and high-reliability packaging. feasibility.

With the development of MCM packaging technology, the mismatch in the coefficient of thermal expansion (CTE) between the chip and the substrate will make it increasingly difficult to control the thermal deformation of the package. Increased thermal deformation of the package will directly lead to changes in the entire chip packaging structure. Large warpage. The thermal expansion coefficient CTE here can be understood as: during the process of installing the chip on the substrate, or after the chip has been integrated on the substrate, the substrate with integrated chip will expand and contract due to temperature changes. During the expansion and contraction, the unit The volume change caused by temperature change can be expressed by the thermal expansion coefficient CTE.

In the chip packaging structure shown in FIG. 1 , two chips 02 are disposed on a substrate 01 , and a heat dissipation cover (Lid) 03 covers the two chips 02 and is fixedly connected to the substrate 01 . Moreover, a thermal interface material (TIM) layer 04 is provided between the chip 02 and the heat dissipation cover 03 .

During the packaging process, there may be a CTE mismatch between the chip 02 and the substrate 01, causing the two chips to warp when the temperature changes after being integrated into the substrate 01. Furthermore, a large distance is likely to occur between the warped substrate 01 and the heat dissipation cover 03 , which may easily lead to the risk of delamination between the TIM layer 04 , the heat dissipation cover 03 , and the chip 02 . The simple understanding is that, as shown in Figure 1, there may be a gap d between the TIM layer 04 and the chip 02, or a gap (Gap) between the TIM layer 04 and the heat dissipation cover 03, or a gap d between the TIM layer 04 and the heat dissipation cover 03. There are gaps between the chips 02 and between the TIM layer 04 and the heat dissipation cover 034 .

As a result, the thermal resistance in the heat dissipation path of chip 02 will be increased, which may easily cause the risk of high temperature in chip 02, thereby affecting the working performance of chip 02.

Contents of the invention

Embodiments of the present application provide a chip packaging structure, electronic equipment, and a method for manufacturing the chip packaging structure. The main purpose is to provide a chip packaging structure that can weaken the risk of TIM layer delamination.

In order to achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

On the one hand, the present application provides a chip packaging structure, which is a multi-chip module MCM packaging structure.

The chip packaging structure may include: a substrate, multiple chips integrated on the substrate, and a heat dissipation cover. The multiple chips are located on the same surface of the substrate, and any one of the multiple chips is connected through an electrical connection structure (such as a soldering layer). ) is disposed on the substrate, and the heat dissipation cover includes a central portion covering the side of the plurality of chips away from the substrate, and an outer edge portion surrounding the periphery of the plurality of chips and fixedly connected to the substrate. In addition, a thermal interface material layer is formed between the surface away from the substrate and the central part of any one of the plurality of chips; wherein the surface of the central part of the heat dissipation cover facing the substrate has one or more protrusions, And one or more protrusions are in contact with the thermal interface material layer of at least one chip among the plurality of chips.

In the chip packaging structure given in this application, since there is a protruding part between the central part of the heat dissipation cover and the thermal interface material layer, that is, the protruding part fixedly connected to the heat dissipation cover can be pressed against the thermal interface material. layer. In this way, when the heat dissipation cover is covered on multiple chips, even if the CTE mismatch between the chip and the substrate causes the substrate carrying the chip to warp, the protrusions will be pressed against the heat sink. on the interface material layer to prevent the risk of delamination between the thermal interface material layer and the chip. In this case, the heat dissipation resistance of the chip can be reduced and the heat dissipation effect of the chip can be improved.

In an implementable manner, the protruding portion has a plurality of pressing surfaces, and the plurality of pressing surfaces abut on the plurality of thermal interface material layers on a one-to-one basis.

It can be understood that since the protrusion has multiple pressing surfaces that can press against the TIM layer, after the heat dissipation cover is covered on the chip, other structural components are installed on the heat dissipation cover, such as installing a heat sink. When the heat sink exerts pressure on the heat dissipation cover towards the chip, in this case, the protruding part will deform and exert a resisting force on the TIM layer to adhere closely to the TIM layer. Therefore, the protruding part with a resisting surface helps Reduce the possibility of TIM delamination.

In an implementable manner, the protruding portion is disposed close to the center of the first area, the plurality of resisting surfaces are arranged along the circumference of the protruding portion, and the rectangle formed by the orthographic projection of the plurality of chips on the substrate is the first area. a region; and, along the direction from the central part of the heat dissipation cover to the substrate, any pressing surface is inclined from the edge of the first region toward the center of the first region. That is to say, the pressing surface is a surface that is inclined relative to the chip.

By using an inclined surface, the pressing surface can be more closely aligned with the TIM layer on the warped chip. In this case, the heat dissipation cover, TIM layer and chip can be further closely aligned.

In an implementable manner, the pressing surface may be an inclined plane or an inclined curved surface.

In an implementable manner, the chip packaging structure further includes an adhesive pillar, the adhesive pillar is located between the protrusion and the substrate, and one end of the adhesive pillar is bonded to the protrusion, and the other end is bonded to the substrate. bonding.

That is to say, the adhesive pillars can be used to pull the protruding part and the substrate together. In this case, the pulling force of the adhesive pillars on the heat dissipation cover and the substrate can be used to avoid the interference between the partial area of the substrate and the heat dissipation cover. There is a large distance between them, that is, the warping of the package is resisted through pulling force.

In an implementable manner, the chip packaging structure also includes one or more dummy chips, one or more dummy chips and multiple chips are located on the same surface of the substrate; the orthographic projection of the multiple chips on the substrate forms a The rectangle is the first area, and the orthographic projection of the dummy chip on the substrate is located in the first area.

In this embodiment, by arranging dummy chips on the substrate, the local warpage of the substrate can be adjusted, thereby suppressing the degree of warpage of the substrate carrying multiple chips. Finally, the delamination phenomenon of the TIM layer between the chip and the heat dissipation cover can also be weakened, which can reduce the heat dissipation resistance of the chip and improve the heat dissipation effect of the chip.

Moreover, since the orthographic projection of the dummy chip on the substrate is located in the first area, in this case, the area of the entire substrate will not be increased by disposing the dummy chip.

In one possible way, the dummy chip is located between the protrusion and the substrate, and is bonded to the protrusion through an adhesive layer.

In other words, through the combination of dummy chips and protrusions, the degree of warpage can be further suppressed.

In an implementable manner, the outer edge part and the central part have an integrally formed structure.

In an implementable manner, the outer edge portion of the heat dissipation cover is fixedly connected to the central portion of the heat dissipation cover through a connecting structure. For example, the reinforcing ring is fixedly connected to the central part of the heat dissipation cover through a welded structure.

On the other hand, the present application also provides a chip packaging structure, which, like the above chip packaging structure, is also a multi-chip module MCM packaging structure.

The chip packaging structure includes a substrate, multiple chips integrated on the substrate and at least one dummy chip, and also includes a heat dissipation cover. The multiple chips are located on the same surface of the substrate, and any one of the multiple chips is electrically connected. The connection structure (such as a soldering layer) is disposed on the substrate, the at least one dummy chip and the plurality of chips are located on the same surface of the substrate, and the heat dissipation cover includes a central portion covering the side of the plurality of chips and the at least one dummy chip away from the substrate, and an outer edge portion surrounding the plurality of chips and at least one dummy chip and fixedly connected to the substrate; wherein the rectangle surrounded by the orthographic projections of the plurality of chips on the substrate is the first area, and the at least one dummy chip The orthographic projection on the substrate is located within the first area.

The chip packaging structure given in this application includes not only chips with electrical functions, but also dummy chips without electrical functions. By arranging dummy chips in local positions of the substrate, the local warpage of the substrate can be adjusted. This can further suppress the degree of warpage of a substrate carrying multiple chips. Finally, the delamination phenomenon of the TIM layer between the chip and the heat dissipation cover can also be weakened, which can reduce the heat dissipation resistance of the chip and improve the heat dissipation effect of the chip.

In addition, since the rectangle surrounded by the orthographic projections of multiple chips on the substrate is the first area, the orthographic projection of at least one dummy chip on the substrate is located in the first area. That is to say, the relationship between chips is fully utilized. The dummy chip is placed in the idle space between them. In this way, on the basis of suppressing the warpage of the entire package, it will not increase the size of the substrate or the entire package structure.

In one possible way, the area of any dummy chip is smaller than the area of the chip.

In other words, the idle space between chips is used to set up smaller-sized dummy chips to achieve the purpose of suppressing the degree of warpage.

In one possible way, the surface of any dummy chip away from the substrate is bonded to the central part through an adhesive layer.

Bonding the dummy chip to the central part of the heat dissipation cover through the adhesive layer can pull the heat dissipation cover and the substrate together through the dummy chip. Through the pulling force, the warpage of the entire package can also be suppressed.

In an implementable manner, the plurality of chips include a first chip, a second chip, a third chip and a fourth chip; at least one dummy chip is a dummy chip; the first chip, the second chip, the third chip and The fourth chip is placed near the corner of the first area; a dummy chip is placed near the center of the first area.

In an implementable manner, the plurality of chips includes a first chip and a second chip; at least one dummy chip includes a first dummy chip and a second dummy chip; the first chip and the second chip are located on the first pair of the rectangular structure On the diagonal line, the first dummy chip and the second dummy chip are located on the second diagonal line of the rectangular structure, and the first diagonal line and the second diagonal line intersect.

On the other hand, this application also provides a chip packaging structure. Like the above two chip packaging structures, the chip packaging structure is also a multi-chip module MCM packaging structure.

The chip packaging structure includes a substrate, multiple chips integrated on the substrate, and a heat dissipation cover. The multiple chips are located on the same surface of the substrate, and any one of the multiple chips is connected through an electrical connection structure (such as The soldering layer) is provided on the substrate, and the heat dissipation cover includes a central part covering the side of the multiple chips away from the substrate, and an outer edge part surrounding the periphery of the multiple chips and fixedly connected to the substrate; in addition, the chip packaging structure also includes The pulling column is located between the central part of the heat dissipation cover and the substrate. The orthographic projection of the pulling column on the substrate is located in the first area. The rectangle formed by the orthographic projection of the multiple chips on the substrate is the first area. , the pulling column is fixedly connected to the central part of the heat dissipation cover and the base plate respectively.

In the chip packaging structure provided by this application, since the central part of the heat dissipation cover is fixedly connected to the substrate through the pulling column, in this way, when multiple chips are integrated on the substrate during preparation, even if there is a gap between the chip and the substrate, When the CTE mismatch phenomenon is about to cause the substrate carrying the chip to warp, the degree of warpage of the substrate carrying the chip will be suppressed due to the pulling force of the pulling column on the substrate and the heat dissipation cover. It can also be understood in this way, Because of the pulling force of the pulling column on the substrate, a large distance between some areas of the substrate and the heat dissipation cover is avoided, that is, the pulling structure is used to resist the warping of the package.

In this case, since the warpage of the substrate carrying the chip is weakened, the TIM layer located between the chip and the heat dissipation cover will basically not have delamination, thereby reducing the heat dissipation thermal resistance of the chip and improving the thermal resistance of the chip. The heat dissipation effect. Among the structures that can be selected, for the materials that can be selected for the TIM layer, you only need to choose materials with high thermal conductivity. There is no need to consider the bonding strength of the TIM layer too much. In this way, the TIM layer will not be selected. The material is too restrictive.

In addition, since the rectangle surrounded by the orthographic projections of the plurality of chips on the substrate is the first region, the orthographic projection of the pulling column on the substrate is located in the first region. Compared with arranging the pulling column outside the first region, , will not produce greater stress on some chips, therefore, it can play a role in protecting the chips.

In an implementable manner, the pulling column includes an adhesive column, one end of the adhesive column is bonded to the central part of the heat dissipation cover, and the other end is bonded to the substrate.

That is to say, the pulling column here can adopt a structure made of adhesive glue, and the central part of the heat dissipation cover and the substrate are pulled together through the adhesive force of the adhesive glue.

In one possible implementation, the outer edge portion is fixedly connected to the substrate through an adhesive layer surrounding the periphery of multiple chips; and the adhesive pillars and the adhesive layer are made of the same material.

In this case, during the preparation process, when the adhesive layer is bonded on the substrate, the adhesive pillars can be bonded at the same time. Therefore, on the basis of suppressing the warpage of the chip and the substrate, the preparation process will not become complicated.

In one possible way, the pulling structure includes a boss and an adhesive pillar. The boss is formed on the surface of the central part of the heat dissipation cover facing the substrate; one end of the adhesive pillar is bonded to the boss, and the other end of the adhesive pillar is bonded to the boss. One end is bonded to the substrate.

It can be understood that a boss protruding toward the substrate can be provided in the central part of the heat dissipation cover. In addition, an adhesive post is provided to bond the boss and the substrate to pull the boss on the heat dissipation cover and the substrate together. .

By forming a boss on the heat dissipation cover, the pulling strength of the pulling column to the heat dissipation cover and the substrate can also be enhanced.

In one possible implementation, the boss and the central part of the heat dissipation cover are an integrally formed structure. For example, it can be an integrally formed metal piece.

In an implementable manner, the distance between the surface of the boss facing the substrate and the substrate is d1; the distance between the surface of the outer edge portion facing the substrate and the substrate is d2; where d1 is greater than or equal to d2.

That is to say, the boss formed on the heat dissipation cover cannot be too high. If it is too high, it may cause greater stress on the package, and this stress may affect the performance of the chip. Furthermore, in an optional structure, the distance d2 between the outer edge part of the heat dissipation cover and the base plate can be smaller than or equal to the distance d1 between the boss and the base plate.

In an implementable manner, the chip packaging structure further includes at least one dummy chip, the at least one dummy chip and the plurality of chips are located on the same surface of the substrate, and the orthographic projection of the at least one dummy chip on the substrate is located on the third within a region.

In other words, by setting up a dummy chip, the warpage of the entire package can be further suppressed.

In an implementable manner, the chip packaging structure further includes an adhesive glue column, one end of the adhesive glue column is bonded to the central part, and the other end is bonded to the dummy chip.

In an implementable manner, the pulling column includes an adhesive glue column and a support column. The adhesive glue column includes a first adhesive glue column and a second adhesive glue column; one end of the support column passes through the first adhesive glue column. The column is bonded to the central part, and the other end of the support column is bonded to the base plate through a second adhesive glue column.

By setting up a strong support column structure as a pulling structure, the strength of the pulling column can also be improved on the premise of meeting the pulling force.

On the other hand, the present application also provides a method for preparing a chip packaging structure. The method for preparing a chip packaging structure includes:

Multiple chips are arranged on the same surface of the substrate, and any one of the multiple chips is arranged on the substrate through an electrical connection structure;

forming a thermal interface material layer on a surface of any one of the plurality of chips away from the substrate;

The heat dissipation cover is provided such that one or more protrusions on the central portion of the heat dissipation cover are in contact with the thermal interface material layer of at least one chip among the plurality of chips; wherein the central portion of the heat dissipation cover is covered by the heat dissipation cover. One or more protrusions are provided on the surface of the central portion of the heat dissipation cover facing the substrate on the portion of the plurality of chips on the side away from the substrate.

In the method for preparing a chip packaging structure provided in this application, since the central part of the heat dissipation cover has one or more protrusions, when the heat dissipation cover is installed, the protrusions will abut against the thermal interface material layer superior. Furthermore, when other structural parts are installed on the heat dissipation cover, such as when installing a radiator, the radiator will exert pressure on the heat dissipation cover. Under the action of this pressure, the protruding portion will deform, giving the thermal interface material layer extrusion force. , to reduce the possibility of delamination of the thermal interface material layer.

In an implementable manner, before setting the heat dissipation cover, the preparation method further includes: dotting adhesive glue on a surface of the substrate that is opposite to the central part of the heat dissipation cover to form an adhesive glue column, so that on After the heat dissipation cover is installed, the adhesive posts are fixedly connected between the base plate and the protruding portion.

By forming sticky adhesive pillars on the substrate to pull the protrusions and the substrate together, this will inhibit the warpage of the entire package and also reduce the risk of delamination of the thermal interface material layer.

In one possible implementation, glue is dotted on the surface of the substrate that is opposite to the central part of the heat dissipation cover. The preparation method further includes: glue is dotted along the circumference of the outer edge of the substrate to form The adhesive layer is bonded so that the outer edge part of the heat dissipation cover is fixedly connected to the substrate through the adhesive adhesive layer, and the material of the adhesive glue pillar and the adhesive adhesive layer is the same; wherein, the outer edge part of the heat dissipation cover is surrounded by the heat dissipation cover On the periphery of multiple chips.

That is to say, among the process steps that can be realized, a dispensing process can be used to form an adhesive layer and an adhesive column at the same time.

In an implementable manner, before arranging the heat dissipation cover, the preparation method further includes: arranging one or more dummy chips on the surface of the substrate on which the plurality of chips are arranged, and the one or more dummy chips are placed on the front side of the substrate. The projection is located in the first area, and the rectangle surrounded by the orthographic projections of the plurality of chips on the substrate is the first area.

It can be said that by arranging a dummy chip without electrical function on the substrate, the local warpage of the substrate can be improved, thereby reducing the risk of delamination of the thermal interface material layer.

In an implementable manner, after arranging one or more dummy chips and before arranging the heat dissipation cover, the preparation method further includes: dotting glue on the surface of the one or more dummy chips away from the substrate, so that After the heat dissipation cover is installed, the dummy chip is fixedly connected to the protruding part through adhesive glue.

One or more dummy chips are arranged on the surface of the substrate on which multiple chips are arranged, and the orthographic projection of the one or more dummy chips on the substrate is located in the first area, and the orthographic projection of the plurality of chips on the substrate forms a rectangle. is the first area;

The heat dissipation cover is arranged so that the central part of the heat dissipation cover covers the side of the plurality of chips away from the substrate.

In the method for preparing a chip packaging structure given in this application, by arranging a dummy chip without electrical function on the substrate, the local warpage of the substrate can be improved, thereby also reducing the risk of delamination of the thermal interface material layer.

Moreover, since the dummy chips are located in the first area, the area of the substrate will not be increased by adding dummy chips.

In an implementable manner, before setting the heat dissipation cover, the preparation method further includes: dotting glue on the surface of one or more dummy chips away from the substrate, so that after the heat dissipation cover is set, the dummy chips pass through the adhesive The glue is firmly connected to the central part of the heat dissipation cover.

In one possible implementation, adhesive is applied on the surface of one or more dummy chips away from the substrate. The preparation method further includes: adhesive is applied along the circumference of the outer edge of the substrate to form an adhesive bond. Adhesive layer, so that the outer edge part of the heat dissipation cover is fixedly connected to the substrate through the adhesive adhesive layer, and the adhesive glue located on the dummy chip and the adhesive adhesive layer are made of the same material; wherein, the outer edge part of the heat dissipation cover is the heat dissipation cover The part surrounding multiple chips.

That is to say, among the process steps that can be realized, a dispensing process can be used to simultaneously form an adhesive layer and an adhesive layer located on the dummy chip.

A pulling column is provided on the surface of a substrate provided with multiple chips, a rectangle surrounded by orthographic projections of the plurality of chips on the substrate is the first region, and the orthographic projection of the pulling column on the substrate is located in the first region;

The heat dissipation cover is arranged so that the heat dissipation cover covers the central portion of the plurality of chips on the side away from the substrate and is fixedly connected to the substrate through the pulling column.

In the method for preparing the chip packaging structure provided by this application, before setting the heat dissipation cover, a pulling column must be set on the substrate, and then the heat dissipation cover can be installed. If designed in this way, the pulling column can ensure the connection between the heat dissipation cover and the substrate. The stability of the distance between the chip and the substrate will not cause the phenomenon of larger distance in some areas and smaller distance in some areas due to the thermal expansion coefficient mismatch between the chip and the substrate. In other words, the pulling column will suppress the degree of warpage and avoid the phenomenon of larger distances due to the larger distance between the chip and the substrate. A large degree of warpage causes some phenomena, such as delamination of the TIM layer between the chip and the heat dissipation cover.

In one possible implementation, arranging a pulling column on the surface of a substrate provided with multiple chips includes: dotting adhesive glue on a surface of the substrate that is opposite to the central part of the heat dissipation cover to form an adhesive. The adhesive posts are fixedly connected between the base plate and the central part of the heat dissipation cover, and the adhesive posts form pulling posts.

It can also be understood that in this embodiment, glue is dispensed on the substrate to form a pulling column that bonds the substrate and the heat dissipation cover together through adhesive force. The pulling column of this structure is not only simple in structure, but also easy to implement in technology.

In one possible implementation, glue is dotted on the surface of the substrate that is opposite to the central part of the heat dissipation cover. The preparation method further includes: glue is dotted along the circumference of the outer edge of the substrate to form The adhesive layer is bonded so that the outer edge part of the heat dissipation cover is fixedly connected to the substrate through the adhesive adhesive layer, and the material of the adhesive glue pillar and the adhesive adhesive layer is the same. The outer edge part of the heat dissipation cover is surrounded by multiple layers of the heat dissipation cover. peripheral part of the chip.

In the specific process flow, a glue dispensing process can be used to form an adhesive layer on the edge of the substrate for bonding to the outer edge of the heat dissipation cover, and an adhesive pillar to form a pulling column.

In an implementable manner, a protruding portion is formed on a surface of the central portion of the heat dissipation cover facing the substrate; before setting the heat dissipation cover, the preparation method further includes: placing a convex portion on a surface of any one of the plurality of chips away from the substrate. A thermal interface material layer is formed on the surface of the chip; setting the heat dissipation cover includes: installing the heat dissipation cover so that the protruding portion of the heat dissipation cover abuts the thermal interface material layer of any chip.

That is to say, the protruding portion fixedly connected to the heat dissipation cover can be located on the thermal interface material layer. In this way, when the heat sink is subsequently installed, the protruding portion can be deformed to press against the thermal interface material layer. , to prevent the thermal interface material layer from delaminating due to the thermal expansion coefficient mismatch between the chip and the substrate, that is, applying pressure to the thermal interface material layer through the protrusions to prevent delamination of the thermal interface material layer.

In an implementable manner, before arranging the heat dissipation cover, the preparation method further includes: arranging dummy chips on the surface of the substrate on which the plurality of chips are arranged.

For example, by integrating a dummy chip without any electrical connection to other chips on the substrate, the degree of warpage of the package can be suppressed.

In another aspect, the present application also provides an electronic device, which includes a printed circuit board and the chip packaging structure in any of the above implementations, and the chip packaging structure is disposed on the printed circuit board and connected with the printed circuit board. Circuit board electrical connections.

The electronic device provided by the embodiment of the present application includes the chip packaging structure in any of the above implementations. Therefore, the electronic device provided by the embodiment of the present application and the chip packaging structure of the above technical solution can solve the same technical problem and achieve the same expected effect. .

Description of drawings

Figure 1 is a schematic structural diagram of a chip packaging structure in the prior art;

Figure 2 is a schematic diagram of a partial structure of an electronic device;

Figure 3 is a schematic structural diagram of a chip packaging structure according to an embodiment of the present application;

Figure 4a is a schematic structural diagram of a substrate in the chip packaging structure according to the embodiment of the present application;

Figure 4b is a schematic structural diagram of another substrate in the chip packaging structure according to the embodiment of the present application;

Figure 4c is a schematic structural diagram of another substrate in the chip packaging structure according to the embodiment of the present application;

Figure 5 is a side view of the heat dissipation cover in the chip packaging structure according to the embodiment of the present application;

Figure 6 is a view in direction A of Figure 5;

Figure 7 is a schematic structural diagram of a chip packaging structure according to an embodiment of the present application;

Figure 8 is a structural schematic diagram of a chip packaging structure in the related art that is warped;

Figure 9 is a schematic structural diagram of a chip packaging structure according to an embodiment of the present application;

Figure 10 is a schematic diagram of the positional relationship between the substrate, the chip and the adhesive pillar in the chip packaging structure according to the embodiment of the present application;

Figure 11 is another schematic diagram of the positional relationship between the substrate, the chip and the adhesive pillar in the chip packaging structure according to the embodiment of the present application;

Figure 12 is another schematic diagram of the positional relationship between the substrate, the chip and the adhesive pillar in the chip packaging structure according to the embodiment of the present application;

Figure 13a is a scanned image of the chip packaging structure without adhesive posts;

Figure 13b is a scanned image of a chip packaging structure provided with adhesive pillars;

Figure 14 is a schematic structural diagram of a chip packaging structure according to an embodiment of the present application;

Figure 15 is a schematic diagram of the connection relationship between the heat dissipation cover and the substrate in the chip packaging structure according to the embodiment of the present application;

Figures 16a and 16b are schematic diagrams of the positional relationship between the boss on the heat dissipation cover and the adhesive pillar according to the embodiment of the present application;

Figures 17a and 17b are another schematic diagram of the positional relationship between the boss on the heat dissipation cover and the adhesive pillar according to the embodiment of the present application;

Figures 18a and 18b are another schematic diagram of the positional relationship between the boss on the heat dissipation cover and the adhesive pillar according to the embodiment of the present application;

Figure 19 is a schematic structural diagram of a chip packaging structure according to an embodiment of the present application;

Figure 20a is a schematic diagram of the positional relationship between the substrate, the chip and the pulling column in the chip packaging structure of the embodiment of the present application;

Figure 20b is a schematic diagram of another positional relationship between the substrate, the chip and the pulling column in the chip packaging structure of the embodiment of the present application;

Figure 20c is a schematic diagram of another positional relationship between the substrate, the chip and the pulling column in the chip packaging structure of the embodiment of the present application;

Figure 21 is a schematic structural diagram of a chip packaging structure according to an embodiment of the present application;

Figure 22 is a schematic structural diagram of a chip packaging structure according to an embodiment of the present application;

Figure 23 is a schematic structural diagram of the protruding portion in the chip packaging structure according to the embodiment of the present application;

Figure 24 is a schematic diagram of the positional relationship between the substrate, the chip and the protruding portion in the chip packaging structure according to the embodiment of the present application;

Figure 25 is a schematic diagram of the positional relationship between the substrate, the chip and the protruding portion in the chip packaging structure according to the embodiment of the present application;

Figure 26 is a schematic diagram of the positional relationship between the substrate, the chip and the protruding portion in the chip packaging structure according to the embodiment of the present application;

Figure 27 is a schematic structural diagram of a chip packaging structure according to an embodiment of the present application;

Figure 28 is a schematic structural diagram of a chip packaging structure according to an embodiment of the present application;

Figure 29 is a schematic structural diagram of a chip packaging structure according to an embodiment of the present application;

Figure 30 is a schematic diagram of the positional relationship between the substrate, the chip and the dummy chip in the chip packaging structure according to the embodiment of the present application;

Figure 31 is a schematic structural diagram of a chip packaging structure according to an embodiment of the present application;

Figure 32 is a schematic diagram of the positional relationship between the substrate, the chip and the dummy chip in the chip packaging structure according to the embodiment of the present application;

Figure 33 is a schematic structural diagram of a chip packaging structure according to an embodiment of the present application;

Figure 34 is a schematic structural diagram of a chip packaging structure according to an embodiment of the present application;

Figure 35 is a flow chart of a method for preparing a chip packaging structure according to an embodiment of the present application;

Figures 36a to 36d are schematic diagrams of the corresponding structures after completion of each step in the method for producing a chip packaging structure according to the embodiment of the present application;

Figure 37 is a flow chart of another method of preparing a chip packaging structure according to an embodiment of the present application;

Figures 38a to 38c are schematic diagrams of the corresponding structures after completion of each step in the method for producing a chip packaging structure according to the embodiment of the present application;

Figure 39 is a flow chart of another preparation method of the chip packaging structure according to the embodiment of the present application;

40a to 40d are schematic structural diagrams of the corresponding structures after completion of each step in the method for manufacturing a chip packaging structure according to an embodiment of the present application.

Reference signs:

100-PCB;

200-Electrical connection structure;

300-chip packaging structure;

400-radiator;

01-Substrate;

01a-Packaging substrate;

01b-rewiring structure;

01c-Adapter board;

011-Substrate;

012-Metal wiring;

013-Dielectric layer;

014-Conductive channel;

02-chip; 021-first chip; 022-second chip; 023-third chip; 024-fourth chip;

03-Heat dissipation cover; 031-Outer edge part; 032-Central part;

04-Thermal interface material layer; 041-The first thermal interface material layer; 042-The second thermal interface material layer;

05-Controllable collapse of chip connection solder joints;

06-Bottom layer;

07-traction column;

071-bonding glue column; 071a-first bonding glue column; 071b-second bonding glue column;

072-Boss;

073-Support column;

08-Adhesive layer;

09-Protruding part; 09a-Resisting surface;

10-Fake chip;

11-Welding layer.

Detailed ways

An embodiment of the present application provides an electronic device. The electronic device may include a mobile phone (mobile phone), a tablet computer (pad), smart wearable products (such as smart watches, smart bracelets), virtual reality (VR) devices, augmented reality (AR), It can also be equipment such as household appliances. The embodiments of the present application do not place special restrictions on the specific forms of the above-mentioned electronic devices.

As shown in Figure 2, the above-mentioned electronic device may include a printed circuit board (PCB) 100 and a chip packaging structure 300. The chip packaging structure 300 is electrically connected to the PCB 100 through the electrical connection structure 200, so that the chip packaging structure 300 can achieve signal interconnection with other chips or other electronic modules on the PCB 100.

In addition, as shown in FIG. 2 , the electronic device may also include a heat sink 400 . The heat sink 400 covers the chip packaging structure 300 and other electronic modules on the PCB 100 , and is fixedly connected to the PCB 100 . The heat sink 400 here serves as a heat dissipation structure and can dissipate and cool down the chip packaging structure 300 and other electronic modules on the PCB 100 . In addition, the heat sink 400 can also provide physical protection to the chip packaging structure 300 .

In alternative embodiments, the electrical connection structure 200 may include a plurality of solder balls, such as a ball grid array (BGA), or a plurality of metal pillars.

The above-mentioned chip packaging structure 300 may be a structure in which multiple dies are packaged. For example, the chip packaging structure 300 may be a processor, including a dynamic random access memory (DRAM) and a system on chip (SOC), or may include a system on chip SOC, an analog chip, etc., or it may Including analog chips and other digital chips.

The structure of the above-mentioned chip packaging structure 300 will be described in detail below.

FIG. 3 is a schematic cross-sectional view of a chip packaging structure 300 provided by an embodiment of the present application. The chip packaging structure 300 includes: multiple chips, which are integrated on the substrate 01 , and the multiple chips are located on the substrate 01 on the same surface. FIG. 3 exemplarily shows that the first chip 021 and the second chip 022 are integrated on the substrate 01 . Of course, FIG. 3 is only an exemplary structure, and more chips can also be provided on the substrate 01 .

Furthermore, this application relates to a chip integrated on the substrate 01, which may be one chip or multiple chips stacked in three dimensions. For example, the first chip 021 in FIG. 3 may refer to one chip, and the second chip 022 may include multiple chips stacked in three dimensions. The three-dimensional stacking here refers to stacking in a direction perpendicular to the substrate 01 .

In some alternative implementations, as shown in Figure 3, any chip can be electrically connected to the substrate 01 through a controlled collapse chip connection (C4) 05, and a metal layer is formed in the substrate 01 , the metal layer includes wiring structures. The substrate 01 establishes signal paths between chips or between chips and other electronic devices through the wiring structure. In other words, the chip here refers to a chip that can realize electrical functions.

When the chip is disposed on the substrate 01, it can use flip-chip ball grid array (FCBGA) technology. To simply understand, the active surface of the chip faces the substrate 01, the passive surface of the chip faces away from the substrate 01, and the active surface of the chip is arranged on the substrate 01 through the BGA electrical connection structure. The passive surface here can be understood as the substrate of the chip, and the active surface can be understood as the part of the chip that integrates electronic devices such as transistors and metal wiring. In other packaging structures, wire bonding technology can also be used to place the chip on the substrate 01.

The substrate 01 involved in this application has a variety of structures that can be implemented.

For example, the substrate 01 may be a packaging substrate 01a shown in FIG. 4a. The packaging substrate 01a includes a substrate 011 and a rewiring structure 01b located on the upper surface and lower surface of the substrate 011.

As another example, the substrate 01 may be a redistribution layer (RDL) 01b produced through a redistribution process as shown in FIG. 4b. The RDL01b includes a multi-layer metal trace 012 and a multi-layer dielectric layer 013. Each adjacent layer The two layers of metal traces 012 are separated by a dielectric layer 013 . In order to electrically connect the metal traces 012 on different layers, a conductive channel 014 can be made in the dielectric layer 013 so that the metal traces 012 on different layers are electrically connected through the conductive channel 014 . When RDL01b is used as the substrate, the flexibility of the substrate can also be improved and the warpage of the package can be suppressed.

As another example, the substrate 01 may be an interposer 01c shown in FIG. 4c. The interposer 01c includes a substrate 011, a rewiring layer RDL01b integrated on the substrate 011, and a conductive channel penetrating the substrate 011. 014, the conductive channel 014 is electrically connected to the metal traces in the redistribution layer RDL01b.

In order to improve the reliability of the connection between the chip and the substrate 01, as shown in Figure 3, in one embodiment, a glue dispensing process can be used to fill an underfill layer (underfill) 06 between the first chip 021 and the substrate 01, and The primer layer 06 is filled between the second chip 022 and the substrate 01 .

In addition, the chip packaging structure 300 also includes a heat dissipation cover (Lid) 03. The heat dissipation cover 03 covers the side of the multiple chips away from the substrate 01 and is fixedly connected to the substrate 01.

As shown in FIG. 3 , when the chip packaging structure 300 includes a heat dissipation cover 03 , the heat dissipation cover 03 is connected to the upper surface of the chip through a thermal interface material (TIM) layer. For example, in FIG. 3 , the upper surface of the first chip 021 is connected to the heat dissipation cover 03 through the first TIM layer 041 , and the upper surface of the second chip 022 is connected to the heat dissipation cover 03 through the second TIM layer 042 .

In this case, the heat dissipated by the first chip 021 and the second chip 022 will be conducted to the heat dissipation cover 03 through the corresponding first TIM layer 041 and the second TIM layer 042, and the heat will be dissipated through the heat dissipation cover 03 with a larger heat conduction area. Diffuse out to cool down the first chip 021 and the second chip 022 to ensure the normal operation of these chips.

In some implementations, the first TIM layer 041 and the second TIM layer 042 in FIG. 3 can be made of the same material or different materials.

Figures 5 and 6 show one possible structure of the heat dissipation cover 03, and Figure 5 shows a axial side view of the heat dissipation cover 03, and Figure 6 shows a view along the A direction of Figure 5. 5 and 6 together, the heat dissipation cover 03 includes an outer edge part 031 and a central part 032. The outer edge part 031 is the part of the heat dissipation cover 03 that is fixedly connected to the substrate 01 as shown in Figure 2, that is, the part surrounding the periphery of multiple chips. The central part 032 is the part of the heat dissipation cover 03 that is located away from the multiple chips from the substrate 01. part of one side.

In the structure that can be realized, the outer edge part 031 and the central part 032 are an integrally formed structure. For example, the heat dissipation cover 03 including the outer edge portion 031 and the central portion 032 can be an integrally formed metal structural member.

In other implementation structures, such as the chip packaging structure 300 shown in FIG. 7 , the outer edge part 031 and the central part 032 are two independent structural members, and the outer edge part 031 and the central part 032 are connected through a connecting structure. For fixed connection, for example, the outer edge portion 031 can be welded together with the central portion 032 through the welding layer 11 .

When the outer edge part 031 and the central part 032 are two independent structural members, the outer edge part 031 here may also be called a reinforcing ring. The materials of the reinforcing ring and central portion 032 may be the same or different. In the chip packaging structure 300 given in this application, since it includes multiple chips, and these chips are integrated on the substrate 01 through electrical connection structures as shown in Figures 3 and 7, such a packaging structure can be called a multi-chip packaging structure. Chip module (multi-chip module, MCM) packaging. With the increase in the number and speed of chip cores, larger chips are gradually being used in MCM packaging structures. The CTE mismatch between larger chips and substrate 01 makes it more difficult to control thermal deformation of the package, and the degree of warpage is getting worse.

FIG. 8 shows a structural diagram of a chip packaging structure 300 in the related art. Obviously, the area of the substrate 01 where the second chip 022 is arranged forms a warped area due to the mismatch in thermal expansion coefficient, which further causes a larger distance between the area of the substrate 01 where the first chip 021 is arranged and the heat dissipation cover 03 . As a result, the third The first TIM layer 041 delaminates, and the second chip 022 will also warp along with the substrate 01, causing delamination to occur at the edge of the second TIM layer 041. Figure 8 is only to illustrate an exemplary structure of the risk of delamination occurring in the TIM layer, and does not include all situations where delamination occurs.

In order to suppress the degree of warpage and reduce the risk of delamination of the TIM layer, as shown in FIGS. 3 and 7 , pulling posts 07 can be provided in the chip packaging structure 300 . The central part 032 of the heat dissipation cover 03 and the substrate 01 are pulled together by using the pulling column 07, so that the degree of warpage can be reduced.

The following is an introduction to the setting position of the pulling column 07, the specific achievable structure, and how to suppress the degree of warping with reference to the accompanying drawings.

FIG. 9 is a structural diagram of a chip packaging structure 300 provided in this application, which includes a pulling column. Specifically, the pulling column includes an adhesive (AD) column 071. The adhesive column 071 is located between the central part 032 of the heat dissipation cover 03 and the substrate 01, and the adhesive column 071 is close to the part of the heat dissipation cover 03. It is bonded to the central part 032, and the part close to the base plate 01 is bonded to the base plate 01.

It should be noted that the shape of the adhesive pillar 071 involved in this application is not limited to a cylindrical structure. The adhesive layer structure located between the central part 032 of the heat dissipation cover 03 and the substrate 01 can be called adhesive. Column 071 structure.

The principle of the adhesive post 071 to suppress the degree of warpage can be understood as follows: As shown in Figure 9, since the adhesive post 071 is bonded to the heat dissipation cover 03 and the substrate 01 respectively, the adhesive post 071 will give the heat dissipation cover The central part 032 of 03 exerts a downward pulling force f1. At the same time, the adhesive pillar 071 will also give the substrate 01 an upward pulling force f2. Then, even if warping occurs due to CTE mismatch between the chip and the substrate 01, for example, in the Q area as shown in Figure 9, the distance d between the heat dissipation cover 03 and the substrate 01 is larger than other areas. , will prevent the distance d from becoming larger under the action of the pulling force f1 and the pulling force f2, which will then inhibit the warpage of the entire package structure. When the warpage is weakened, it will decrease as shown in Figure 9 The probability of delamination between the first TIM layer 041 and the heat dissipation cover 03 and the first chip 021 . Similarly, the probability of delamination between the second TIM layer 042 and the heat dissipation cover 03 and the second chip 022 will also be reduced. In this case, the thermal resistance in the chip heat dissipation path will be reduced and the heat dissipation effect of the chip will be improved.

Continuing to refer to the chip packaging structure 300 shown in FIG. 9 , the chip packaging structure 300 also includes an adhesive layer 08 , through which the outer edge portion 031 of the heat dissipation cover 03 is fixedly connected to the substrate 01 . Therefore, in an achievable structure, the same material can be used to form the adhesive glue pillar 071 and the adhesive glue layer 08 . For example, the material of the adhesive layer may be a silicone material or an epoxy resin material. This application does not specifically limit the material of the adhesive layer.

In addition, the pulling column shown in Figure 9 above is an adhesive column made of adhesive glue. Then, when selecting the material of the TIM layer, you only need to choose a material with a relatively high thermal conductivity. For example, you can choose Polymers, metals or graphene, etc.

There are many options for setting the position of the adhesive post 071 . Here are a few ways this can be done.

For example, as shown in Figure 10, Figure 10 shows a top view of a substrate 01 integrated with two chips. Specifically, the two chips are the first chip 021 and the second chip 022 respectively, and the adhesive post 071 can be disposed between the first chip 021 and the second chip 022 .

For another example, as shown in Figure 11, Figure 11 shows a top view of a substrate 01 integrated with four chips. The four chips are respectively the first chip 021 and the second chip 022, and the third chip 023 and the fourth chip 024. The adhesive pillar 071 is arranged in the center of the area surrounded by the four chips.

The number of adhesive posts 071 can be selected in many ways.

For example, see Figures 10 and 11, both of which have an adhesive post 071 set at the center of the area surrounded by multiple chips.

As another example, as shown in FIG. 12 , FIG. 12 shows a top view of the substrate 01 integrated with two chips. Specifically, the two chips are the first chip 021 and the second chip 022 respectively. A plurality of adhesive glue posts 071 are provided between the first chip 021 and the second chip 022. These multiple adhesive glue posts 071 are arranged at intervals. cloth.

As shown in Figures 13a and 13b, both Figures 13a and 13b show the chip packaging structure 300, and the image is viewed from above the chip packaging structure 300 (ie, the upper side of the heat dissipation cover 03) through an ultrasonic scanning microscope (scanning acoustic microscope, SAM). ) scanned image. Among them, the chip packaging structure 300 shown in FIG. 13a does not have a scanned image of the adhesive glue column 071 involved in this application, while the chip packaging structure shown in FIG. 13b includes a scanned image of the adhesive glue column 701. In addition, Both Figures 13a and 13b show four chips 02. It can be understood that Figure 13b is a structural diagram after adding adhesive posts 071 based on the structure shown in Figure 13a.

Combining Figure 13a and Figure 13b together, it can be easily seen that in Figure 13a, when the adhesive column 071 is not provided in the chip packaging structure, under the scanning of the ultrasonic scanning microscope SAM, the projection of each chip 02 The area is obviously smaller than the projected area of each chip 02 in Figure 13b. It can be deduced that in the chip packaging structure shown in Figure 13a, the TIM layer located between the chip and the heat dissipation cover may be delaminated due to warping, resulting in a relatively small projected area of the chip in the scanned image.

Therefore, by comparing Figure 13a and Figure 13b, it can be concluded that if the adhesive pillar 071 is provided between the central part 032 of the heat dissipation cover 03 and the substrate 01 according to the present application, the risk of delamination of the TIM layer can be reduced. In order to improve the heat dissipation effect of the chip, it can also improve the reliability of the entire package.

FIG. 14 is a structural diagram of another chip packaging structure 300 provided in this application, which also includes a pulling column 07. Specifically, the pulling column 07 includes an adhesive glue column 071 and a boss 072. The boss 072 is formed on the surface of the central part 032 of the heat dissipation cover 03 facing the substrate 01. One end of the adhesive glue column 071 is connected to the boss 072. For bonding, the other end of the bonding glue post 071 is bonded to the substrate 01.

The pulling structure shown in Figure 14 is similar to the pulling column shown in Figure 9 in the above-mentioned principle of suppressing warpage of the package. That is, as shown in Figure 14, since one end of the adhesive glue column 071 is bonded to the boss 072 of the heat dissipation cover 03, a downward pulling force f1 will be exerted on the heat dissipation cover 03, and because the adhesive glue column 071 The other end is bonded to the substrate 01, which will give the substrate 01 an upward pulling force f2. Then, even if warpage occurs due to CTE mismatch between the chip and the substrate 01, when the distance d between the heat dissipation cover 03 and the substrate 01 becomes larger than other areas, the pulling force f1 and the pulling force will Under the action of f2, the blocking distance d becomes larger, which in turn suppresses the warpage of the entire package structure. When the degree of warpage is weakened, the probability of delamination between the TIM layer and the heat dissipation cover 03 and the chip will be reduced.

The adhesive pillar 071 in this embodiment can be the same as the adhesive pillar 071 in FIG. 9 , and the same material as the adhesive layer 08 can be selected.

As shown in FIG. 14 , in some implementation structures, the boss 072 can be an integrally formed structure with the central portion 032 of the heat dissipation cover 03 . It can also be that the boss 072 and the central part 032 of the heat dissipation cover 03 are structural parts independent of each other, and the boss 072 is fixedly connected to the central part 032 of the heat dissipation cover 03 through a connecting structure. For example, the boss 072 is connected to the central part 032 of the heat dissipation cover 03 through a welding structure. The heat sink cover 03 is connected together.

As shown in Figure 15, Figure 15 shows the assembly relationship between the heat dissipation cover 03 and the substrate 01 of the present application. Among them, the distance between the surface of the boss 072 facing the substrate 01 and the substrate 01 is d1. The distance is d2, and d1 is greater than or equal to d2. For example, Figure 15 shows that d1 is greater than d2.

When d1 is greater than or equal to d2, firstly, it can ensure that the adhesive pillar 071 located between the boss 072 and the substrate 01 can produce opposite pulling force on the heat dissipation cover 03 and the substrate 01; secondly, it will not cause any problems due to the setting. The boss 072 causes the heat dissipation cover 03 to exert greater stress on the chip. Furthermore, when the heat dissipation cover 03 shown in Figure 15 is used, the risk of damage to the chip caused by large stress can be eliminated.

Several bosses 072 and adhesive posts 071 with different structures are shown below in conjunction with the accompanying drawings.

For example, see the structures shown in Figures 16a and 16b. Figure 16a shows a top view of the substrate 01 integrated with two chips, and Figure 16b shows a bottom view of the heat dissipation cover 03 with a boss 072 (i.e. View from direction B in Figure 15). As shown in Figure 16a, an adhesive glue post 071 is provided on the substrate 01. Correspondingly, as shown in Figure 16b, a boss 072 bonded to the adhesive glue post 071 can be provided on the central part 032 of the heat dissipation cover 03.

For another example, see the structures shown in Figures 17a and 17b. Figure 17a shows a top view of the substrate 01 integrated with two chips, and Figure 17b shows a bottom view of the heat dissipation cover 03 with the boss 072. In Figure 17a, a plurality of adhesive posts 071 are provided on the substrate 01. Correspondingly, as shown in Figure 17b, a plurality of bosses 072 can be provided on the central part 032 of the heat dissipation cover 03, and the plurality of bosses 072 are connected to The plurality of bonding glue posts 071 are bonded one-to-one.

For another example, see the structures shown in Figures 18a and 18b. Figure 18a shows a top view of the substrate 01 integrated with two chips, and Figure 18b shows a bottom view of the heat dissipation cover 03 with the boss 072. In Figure 18a, a plurality of adhesive posts 071 are provided on the substrate 01. Correspondingly, as shown in Figure 18b, a boss 072 can be provided on the central part 032 of the heat dissipation cover 03, and a plurality of adhesive posts 071 All are bonded to the one boss 072.

FIG. 19 is a structural diagram of another chip packaging structure 300 provided in this application, which also includes a pulling column 07. Specifically, the pulling column 07 includes a first bonding glue column 071a, a second bonding glue column 071b, and a support column 073. The support column 073 is located between the first bonding glue column 071a and the second bonding glue column 071b. , and the first adhesive glue pillar 071a is bonded to the central portion 032 of the heat dissipation cover 03, and the second adhesive glue pillar 071b is bonded to the substrate 01.

In the structure shown in FIG. 19 , as an example, the support pillar 073 can be made of glass; as another example, the support pillar 073 can be made of a metal block. Of course, you can also choose other support pillars 073 with greater hardness.

The first adhesive glue column 071a and the second adhesive glue column 071b here can be selected from the same material as the adhesive glue layer 08.

Based on the above structure of the pulling column 07 that suppresses the degree of warpage, it can be seen that the pulling column 07 is used to form a pulling force between the heat dissipation cover 03 and the substrate 01 to prevent the heat dissipation cover 03 and the substrate from being caused by warping. Some areas of 01 produce larger distances.

In addition, the arrangement position of the pulling column 07 can be understood as: the rectangle enclosed by the orthographic projections of the multiple chips of the present application on the substrate 01 can be called the first area, and the orthogonal position of the pulling column 07 on the substrate 01 The projection is located within this first area.

It should be explained that the rectangle formed by the orthographic projections of the multiple chips involved in this application on the substrate 01 can be understood in this way, as detailed below.

For example, see the structure shown in Figure 20a. Figure 20a shows a top view of the substrate 01 integrated with two chips. The two chips include a first chip 021 and a second chip 022. The orthographic projections of the first chip 021 and the second chip 022 on the substrate 01 have boundaries B1, B2, B3 and B4, and the boundaries B1, B2, The area M enclosed by the boundary B3 and the boundary B4 is a rectangle. It can be understood that the rectangular area M is the above-mentioned first area.

For another example, see the structure shown in Figure 20b. Figure 20b also shows a top view of the substrate 01 integrated with two chips. The two chips include a first chip 021 and a second chip 022, and the orthographic projections of the first chip 021 and the second chip 022 on the substrate 01 have boundaries B1, B2, B3 and B4, and the boundaries B1, B4 The area M enclosed by B2, the boundary B3 and the boundary B4 is a rectangle. It can be understood that the rectangular area M is the above-mentioned first area.

For another example, see the structure shown in Figure 20c. Figure 20c shows a top view of a substrate 01 integrated with three chips. The three chips include the first chip 021, the second chip 022, and the third chip 023, and the orthographic projections of the first chip 021, the second chip 022, and the third chip 023 on the substrate 01 have boundaries B1, B2, The boundary B3 and the boundary B4, and the area M enclosed by the boundary B1, the boundary B2, the boundary B3 and the boundary B4 is a rectangle. It can be understood that the rectangular area M is the above-mentioned first area.

20a, 20b and 20c, the orthographic projection of the central part 032 of the heat dissipation cover 03 and the pulling column of the base plate 01 involved in this application is located in the first area. Compared with arranging the pulling column outside the first area, greater stress will not be generated on some chips, and therefore, the chip can be protected.

Some chip packaging structures 300 that can reduce the risk of delamination in the TIM layer are also given below in conjunction with the accompanying drawings.

As shown in Figure 21, Figure 21 shows a structural diagram of a chip packaging structure 300, and the chip packaging structure 300 includes a protruding portion 09. The protruding portion 09 is formed on the central portion 032 of the heat dissipation cover 03 toward the substrate. 01, and is in contact with the thermal interface material layer. For example, in Figure 20, the protruding portion 09 is formed with a pressing surface 09a, and the pressing surface 09a is in contact with the thermal interface material layer. There may be one or more protrusions 09 .

According to the structure shown in Figure 21, since the central portion 032 of the heat dissipation cover 03 has a protruding portion 09 that can press against the TIM layer, during the process flow, when the first chip 021 and the second chip 022 are both Integrated on the substrate 01, and after covering the heat dissipation cover 03 on the chip, when the heat sink 400 shown in Figure 2 is installed on the heat dissipation cover 03, the heat sink 400 presses the heat dissipation cover 03, and the protruding portion 09 is easily deformed so that the pressing surface presses against the TIM layer and is closely attached to the TIM layer, thereby preventing the delamination of the TIM layer and improving the heat dissipation performance of the chip.

In this embodiment, the protruding portion 09 can be an integrally formed structure with the heat dissipation cover 03, or can be connected with the heat dissipation cover 03 through a welding process.

As shown in Figure 22, Figure 22 shows a structural diagram of yet another chip packaging structure 300. The chip packaging structure 300 also includes a protruding portion 09 that can abut on the TIM layer. The difference from the protruding portion 09 shown in FIG. 21 is that the pressing surface 09a of the protruding portion 09 is opposite to the chip. Inclined surface for tilt settings. For example, along the direction from the central part 032 of the heat dissipation cover 03 to the substrate 01, that is, along the P direction shown in FIG. 22, any of the pressing surfaces 09a extends from the edge of the area surrounded by the plurality of chips toward It is inclined close to the center of the area surrounded by the plurality of chips.

Because in some process structures of chip packaging structures, when the substrate carrying the chip warps, the surface of the chip facing the heat dissipation cover 03 is generally an inclined surface. Furthermore, the pressing surface 09a is designed to be inclined relative to the chip. Inclined surface, in this case, can make the pressing surface 09a fit more closely to the TIM layer to further prevent gaps between the TIM layer, the chip and the heat dissipation cover.

It can also be understood that a protruding portion 09 with a gentle slope as shown in Figure 23 can be formed on the surface of the heat dissipation cover 03 facing the substrate 01, where the gentle slope is the inclined pressing surface 09a shown in Figure 23. In specific design, the number of gentle slopes is equal to the number of chips. For example, when four chips are installed on the substrate 01, it can be designed as a protrusion 09 with four gentle slopes as shown in Figure 23, and Four gentle slopes (that is, the pressing surfaces 09 a ) are arranged along the circumferential direction of the protruding portion 09 .

In some structures that can be implemented, the pressing surface 09a can be an inclined plane; in other structures that can be implemented, the pressing surface 09a can also be an inclined curved surface. If the pressing surface 091a is a curved surface, the curvature of the curved surface can be designed according to the degree of chip warpage.

That is, the area size or the inclination angle of the pressing surface 09a is not specifically limited in this application, and can be determined based on the position where the TIM layer is prone to delamination.

In addition, there are various situations regarding the placement position of the protruding portion 09 . Several possible positions of the protrusion 09 are given below.

For example, see the structure shown in Figure 24. Figure 24 shows a top view of the substrate 01 integrated with two chips, and Figure 24 reflects the positional relationship between the protruding portion 09 and the two chips. The two chips include a first chip 021 and a second chip 022. The orthographic projection of the protruding portion 09 on the substrate 01 is located in the first area. This first area has been introduced above and will not be repeated here. Moreover, the protruding portion 09 is located in the first area. Part 09 is close to the center of the first area. In other words, a structure formed on the heat dissipation cover can act on multiple chips at the same time. In addition, the resisting force exerted by the protruding portion 09 on different chips remains basically the same. In this case, there will be no There is a problem of large stress in parts of the entire packaging structure.

For another example, see the structure shown in Figure 25. Figure 25 shows a top view of the substrate 01 integrated with four chips, and Figure 25 reflects the positional relationship between the protruding portion 09 and the four chips. The four chips include the first chip 021 and the second chip 022, and the third chip 023 and the fourth chip 024. As in Figure 24 above, the orthographic projection of the protrusion 09 on the substrate 01 is located in the first area, and , the protruding portion 09 is close to the center of the first area.

For another example, see the structure shown in Figure 26. Figure 26 shows a top view of the substrate 01 integrated with four chips, and Figure 26 shows the positional relationship between the protruding portion 09 and the four chips. The same thing as Figure 25 is that the first chip 021 and the second chip 022 are also integrated on the substrate 01, as well as the third chip 023 and the fourth chip 024. The difference from the above Figure 25 is that the protruding portion 09 is close to the The edge setting of an area.

The above combined with the accompanying drawings respectively introduce the implementation methods of using two different structures to improve the delamination phenomenon of the TIM layer. Among them, one is to take the above-mentioned Figure 9, Figure 14, and Figure 19 as an example. By setting a pulling column 07, a pulling force is applied to the heat dissipation cover 03 and the substrate 01 to weaken the degree of warpage and thereby improve the TIM delamination. layer; the other is to take Figure 21 and Figure 22 as an example, by setting a protruding portion 09 between the heat dissipation cover 03 and the TIM layer, and through the deformation of the protruding portion 09, the TIM layer delamination is improved.

Of course, in some alternative implementations, as shown in FIG. 27 , the above-mentioned protruding portion 09 and adhesive glue pillar 071 can be integrated into a chip packaging structure 300. Specifically, the protruding portion 09 is formed On the surface of the central portion 032 of the heat dissipation cover 03 facing the substrate 01, and the protruding portion 09 is formed with a pressing surface 09a that presses against the TIM layer, and an adhesive glue column 071 is provided between the protruding portion 09 and the substrate 01 , that is, one end of the adhesive pillar 071 is bonded to the protruding portion 09 , and the other end of the adhesive pillar 071 is bonded to the substrate 01 .

In other ways that can be implemented, the protruding portion 09 in Figure 27 can be located at a position on the heat dissipation cover 03, and the bonding position of the adhesive post 071 and the heat dissipation cover 03 is not on the protruding portion 09, but on the heat dissipation area. Cover 03 at another location.

Figure 28 also shows a chip packaging structure 300, in which the above-mentioned pulling posts and protrusions are integrated. Specifically, a protrusion 09 can be formed on the surface of the central portion 032 of the heat dissipation cover 02 facing the substrate 01 , and a support column 073 is provided on the substrate 01 , and the support column 073 is connected to the protrusion through an adhesive glue column 071 09glued together.

The above-mentioned various implementable embodiments of improving the TIM layer delamination through the pulling column 07 can be arbitrarily combined with the above-mentioned various implementable embodiments of improving the TIM layer delamination through the protruding portion 09 . Figures 27 and 28 only show two implementation structures that can be combined. This application is not limited to the implementation of Figures 27 and 28, and other combination structures are also within the protection scope of this application.

In addition to the several structures for improving the delamination of the TIM layer given above, this application also provides some implementable methods that can suppress the degree of warpage and weaken the delamination of the TIM layer, as detailed below.

As shown in Figures 29 and 31, the chip packaging structure 300 shown in Figures 29 and 31, in addition to including a plurality of chips integrated on the substrate 01 that can communicate with signals, as shown in Figure 29, also includes components that can achieve signal interconnection. The first chip 021 and the second chip 022 are also integrated with a dummy die 10 on the substrate 01, and the dummy die 10 and multiple chips for signal interconnection are integrated on the same surface of the substrate 01.

It should be explained that the fake chip 10 involved in this application is a chip that has no signal interconnection with other chips.

In the chip packaging structure 300 shown in Figure 29, by adding dummy die and using the CTE difference between the die and the substrate 01 to perform local warpage adjustment, the warpage mutation of the entire package can be reduced, and further, the warpage mutation of the entire package can be eliminated. The generation of TIM layering.

The position of the dummy chip 10 on the substrate 01 is: the rectangle surrounded by the orthographic projections of the multiple chips on the substrate 01 is the first area, and the orthographic projection of the dummy chip 10 on the substrate 01 is located in the first area, that is, this The definition of the first area at is the same as the definition of the first area mentioned above.

The first area can also be understood as the structure shown in Figure 30. Figure 30 shows a top view of the substrate 01 integrated with four chips, and Figure 30 reflects the positional relationship between the dummy chip 10 and the four chips. . Specifically, the first chip 021 and the second chip 022, the third chip 023 and the fourth chip 024, the first chip 021 and the second chip 022, and the third chip 023 and the fourth chip 024 are provided on the substrate 01 The orthographic projection on the substrate 01 has boundaries B1, B2, B3 and B4, and the area M enclosed by the boundaries B1, B2, B3 and B4 is a rectangle and can be understood as the above-mentioned first area. The orthographic projection of the dummy chip 10 on the substrate 01 is within the area M.

Referring to the structure shown in Figure 32, Figure 32 shows a top view of the substrate 01 integrated with two chips, and Figure 32 reflects the positional relationship between the two dummy chips 10 and the two chips. Specifically, the first chip 021 and the second chip 022 are provided on the substrate 01, and the orthographic projection of the first chip 021 and the second chip 022 on the substrate 01 has boundaries B1, B2, B3 and B4, And the area M enclosed by the boundaries B1, B2, B3 and B4 is a rectangle, and the orthographic projections of the two dummy chips 10 on the substrate 01 are all within the area M.

By designing the dummy chip 10 in this way, compared with arranging the dummy chip 10 outside the area M, the area of the substrate 01 will not be increased, and further, the size of the entire package structure will not be increased.

In addition, this application does not limit the number of dummy chips 10. As an example, in the structure shown in Figure 30, one dummy chip 10 can be provided on the substrate 01; as another example, see Figure 32, one dummy chip 10 can be provided on the substrate 01. Set at least two dummy chips 10 on it.

When the structure shown in Figure 30 is adopted, specifically: the first chip 021, the second chip 022, the third chip 023 and the fourth chip 023 form a rectangular structure, and the first chip 021, the second chip 022, the third chip 023 and the fourth chip 023 form a rectangular structure. The third chip 023 and the fourth chip 024 are arranged close to the corners of the rectangular structure, and a dummy chip 10 is arranged close to the center of the rectangular structure.

When the structure shown in Figure 32 is adopted, the first chip 021, the second chip 022, and the two dummy chips 10 form a rectangular structure, and the first chip 021 and the second chip 022 are arranged on the first diagonal of the rectangular structure. On A1, two dummy chips 10 are arranged on the second diagonal line A2 of the rectangular structure, and the first diagonal line A1 and the second diagonal line A2 intersect.

In some optional implementation structures, as shown in Figure 30 and Figure 32, the area of the dummy chip 10 can be smaller than the area of the chip. In this case, using a smaller area dummy chip can make full use of the comparison between chips. Small unused space.

In order to suppress the degree of warpage of the package, the dummy chip 10 and the above-mentioned protruding portion 09 can be combined and integrated into a chip packaging structure 300 . For example, the chip packaging structure 300 shown in Figure 33 includes a dummy chip 10 and a protruding portion 09 formed on the heat dissipation cover 03, and an adhesive pillar 071 is used to bond the dummy chip 10 to the protruding portion 09. together.

Or, in other implementations, in the chip packaging structure 300 shown in Figure 34, it can be understood that Figure 34 is a cross-sectional view of Figure 32, that is, the protruding portion 09 may not be provided, but the dummy chip 10 can be directly Bond it with the heat dissipation cover through adhesive glue post 071.

Or, in other implementations, in a chip packaging structure 300 , not only the dummy chip 10 but also the pulling column 07 and the protruding portion 09 can be provided.

The achievable structure of improving the TIM layering by arranging the dummy chip 10 can be combined with the achievable structure of improving the TIM layering by arranging the pulling column 07 and the protruding portion 09 mentioned above. For different combination methods, The obtained chip packaging structures are all within the scope of protection of this application.

The embodiment of the present application also provides a method for preparing the chip packaging structure 300. The preparation method includes:

A pulling column is provided on the surface of a substrate with multiple chips. A rectangle surrounded by orthographic projections of multiple chips on the substrate is the first area, and the orthographic projection of the pulling column on the substrate is located in the first area.

In this preparation method, the pulling column is provided so that the pulling column generates pulling force to the central part of the heat dissipation cover and the substrate respectively. Then, when the substrate integrated with multiple chips changes in temperature, through the The pulling force can prevent the distance between the heat dissipation cover and the substrate from suddenly changing, so that large warping will not occur. In this case, some problems that affect the performance of the chip will not be derived. For example, the distance between the chip and the substrate will not be TIM layering between thermal covers.

An achievable preparation method of the chip packaging structure 300 will be specifically introduced below in conjunction with the process flow chart shown in FIG. 35 and the process structure diagrams of FIGS. 36a to 36d.

Step S11: Referring to Figure 36a, multiple chips 02 are arranged on the substrate 01.

Step S12: Referring to FIG. 36b, dispensing glue along the circumference of the edge of the substrate 01, and dispensing glue at a position of the substrate 01 opposite to the central part of the heat dissipation cover 03.

When dispensing glue at a position opposite to the central portion of the heat dissipation cover of the substrate 01 , the glue may be dispensed at a central position close to the first area of the orthographic projection of the plurality of chips on the substrate.

Step S13: Referring to FIG. 36c, form a TIM layer 04 on the surface of the chip 02 away from the substrate 01.

Step S14: Combined with Figure 36d, install the heat dissipation cover 03.

After the adhesive glue on the substrate 01 in Figure 36b is cured, an adhesive layer 08 for bonding with the outer edge of the heat dissipation cover and a central part of the heat dissipation cover can be formed on the substrate 01 The adhesive glue column 071.

When performing the above step S14, the surface of the heat dissipation cover 03 facing the substrate 01 also has a protrusion. Then, when the heat dissipation cover 03 is covered on the multiple chips 02, the pressing surface of the protrusion will be located at the TIM of the chip. Then, when a heat sink is installed on the heat dissipation cover of the chip packaging structure, the protruding portion will deform under the force of the heat sink to press against the TIM layer.

In addition, when performing step S11, at least one dummy chip may also be integrated on the substrate 01.

The embodiment of the present application also provides another method for preparing the chip packaging structure 300. The preparation method includes:

An achievable preparation method of the chip packaging structure 300 will be specifically introduced below in conjunction with the process flow chart shown in FIG. 37 and the process structure diagrams of FIGS. 38a to 38c.

Step S21: Referring to Figure 38a, multiple chips 02 are arranged on the substrate 01.

Step S22: Referring to FIG. 38b, form a thermal interface material layer 04 on the surface of any chip 02 away from the substrate 01.

Step S23: With reference to Figure 38c, install the heat dissipation cover 03; wherein, the central portion 032 of the heat dissipation cover 03 has a protruding portion 09 on the surface facing the substrate, and the protruding portion 09 abuts the thermal interface of at least one chip among the plurality of chips. on material layer 04.

In some possible process steps, when performing step S21, at least one dummy chip may also be integrated on the substrate 01. That is, the degree of warpage of the package is suppressed by the dummy chip 10 integrated on the substrate 01 .

Furthermore, an adhesive layer may also be formed on the upper surface of the dummy chip 10 so as to be pulled together with the protruding portion through the adhesive layer.

In addition, in some processes, before performing the installation of the heat dissipation cover 03 in step S24, glue can also be dispensed on the substrate 01 at a position facing the protruding portion, so that the protruding portion and the substrate are pulled together by the cured adhesive glue. Together.

In addition, when dispensing glue at the position of the base plate 01 facing the protruding portion 09, you can also place adhesive glue of the same material along the circumference of the outer edge of the base plate 01, so that the outer edge of the heat dissipation cover passes through the outer edge. The adhesive layer 08 at is fixedly connected to the substrate 01.

An achievable preparation method of the chip packaging structure 300 will be specifically introduced below in conjunction with the process flow chart shown in FIG. 39 and the process structure diagrams of FIGS. 40a to 40c.

Step S31: Referring to FIG. 40a, multiple chips 02 and at least one dummy chip 10 are arranged on the substrate 01.

Step S32: Referring to Figure 40b, form a thermal interface material layer 04 on the surface of any chip 02 away from the substrate 01.

Step S33: Referring to Figure 40c, glue is applied to the surface of the dummy chip 10 away from the substrate 01.

In an achievable process, step S32 and step S33 can be executed simultaneously or in two steps one after another.

Step S34: In conjunction with FIG. 40d, install the heat dissipation cover 03 so that the central portion 032 of the heat dissipation cover 03 covers the side of the plurality of chips and one or more dummy chips away from the substrate 01.

In this case, the substrate 01 is pulled together with the heat dissipation cover 03 through the dummy chip 10 and the adhesive glue. Suppress the warpage of the entire package.

In some process methods, when dispensing glue on the dummy chip 10, you can also place adhesive glue of the same material along the circumference of the outer edge of the substrate 01, so that the outer edge part of the heat dissipation cover can be bonded through the outer edge. The glue layer 08 is fixedly connected to the substrate 01. In one structure, the material of the adhesive on the dummy chip 10 may be the same as the material of the adhesive layer 08 on the outer edge of the substrate 01 .

In the description of this specification, specific features, structures, materials or characteristics may be combined in any suitable manner in any one or more embodiments or examples.

The above are only specific embodiments of the present application, but the protection scope of the present application is not limited thereto. Any person familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application. should be covered by the protection scope of this application. Therefore, the protection scope of this application should be subject to the protection scope of the claims.

Claims

A chip packaging structure, which is characterized by including:

substrate;

A plurality of chips are located on the same surface of the substrate, and any one of the plurality of chips is disposed on the substrate through an electrical connection structure;

A heat dissipation cover, the heat dissipation cover includes a central portion covering the side of the plurality of chips away from the substrate, and an outer edge portion surrounding the periphery of the plurality of chips and fixedly connected to the substrate;

A thermal interface material layer formed between a surface of any one of the plurality of chips away from the substrate and the central portion of the heat dissipation cover;

Wherein, a surface of the central part of the heat dissipation cover facing the substrate has one or more protrusions, and the one or more protrusions are in contact with at least one of the plurality of chips. on the thermal interface material layer.
The chip packaging structure according to claim 1, wherein the protruding portion has a plurality of pressing surfaces, and the plurality of pressing surfaces abut on the plurality of thermal interface material layers one by one. .
The chip packaging structure according to claim 2, wherein the protruding portion is disposed close to the center of the first area, the plurality of pressing surfaces are arranged along the circumferential direction of the protruding portion, and the plurality of pressing surfaces are arranged along the circumferential direction of the protruding portion. A rectangle enclosed by orthographic projections of two chips on the substrate is the first area;

Along the direction from the central part of the heat dissipation cover to the substrate, any of the pressing surfaces is inclined from the edge of the first area toward the center of the first area.
The chip packaging structure according to any one of claims 1-3, characterized in that the chip packaging structure further includes:

An adhesive glue post is located between the protruding part and the substrate, and one end of the adhesive glue post is bonded to the protruding part, and the other end is bonded to the substrate.
The chip packaging structure according to any one of claims 1-3, characterized in that the chip packaging structure further includes:

One or more dummy chips, the one or more dummy chips and the plurality of chips are located on the same surface of the substrate;

The orthographic projection of the one or more dummy chips on the substrate is located in the first area, and the rectangle enclosed by the orthographic projections of the plurality of chips on the substrate is the first area.
The chip packaging structure according to claim 5, wherein the dummy chip is located between the protruding part and the substrate, and is bonded to the protruding part through an adhesive layer.
The chip packaging structure according to any one of claims 1 to 6, characterized in that the outer edge part of the heat dissipation cover and the central part of the heat dissipation cover are an integrally formed structure.
The chip packaging structure according to any one of claims 1-6, characterized in that:

The outer edge portion of the heat dissipation cover is fixedly connected to the central portion of the heat dissipation cover through a connecting structure.
A chip packaging structure, which is characterized by including:

substrate;

A plurality of chips are located on the same surface of the substrate, and any one of the plurality of chips is disposed on the substrate through an electrical connection structure;

At least one dummy chip, the at least one dummy chip and the plurality of chips are located on the same surface of the substrate;

The heat dissipation cover includes a central portion covering the plurality of chips and the at least one dummy chip on a side away from the substrate, and a heat dissipation cover surrounding the periphery of the plurality of chips and the at least one dummy chip. , and the outer edge portion fixedly connected to the substrate;

Wherein, the orthographic projection of the at least one dummy chip on the substrate is located in the first area, and the rectangle enclosed by the orthographic projections of the plurality of chips on the substrate is the first area.
The chip packaging structure according to claim 9, wherein the area of any one of the dummy chips is smaller than the area of the chip.
The chip packaging structure according to claim 9 or 10, characterized in that the surface of any of the dummy chips away from the substrate is bonded to the central part through an adhesive layer.
The chip packaging structure according to any one of claims 9-11, wherein the plurality of chips includes a first chip, a second chip, a third chip and a fourth chip;

The at least one dummy chip is a dummy chip;

The first chip, the second chip, the third chip and the fourth chip are arranged close to the corners of the first area;

The one dummy chip is disposed close to the center of the first area.
The chip packaging structure according to any one of claims 9-11, wherein the plurality of chips includes a first chip and a second chip;

The at least one dummy chip includes a first dummy chip and a second dummy chip;

The first chip and the second chip are located on the first diagonal of the rectangle, the first dummy chip and the second dummy chip are located on the second diagonal of the rectangle, and the third One diagonal intersects the second diagonal.
A chip packaging structure, which is characterized by including:

substrate;

A plurality of chips are located on the same surface of the substrate, and any one of the plurality of chips is disposed on the substrate through an electrical connection structure;

A heat dissipation cover, the heat dissipation cover includes a central portion covering the side of the plurality of chips away from the substrate, and an outer edge portion surrounding the periphery of the plurality of chips and fixedly connected to the substrate;

A pulling column located between the central part of the heat dissipation cover and the base plate;

The orthographic projection of the pulling column on the substrate is located in the first area, and the rectangle enclosed by the orthographic projection of the plurality of chips on the substrate is the first area, and the pulling column is respectively connected with The central part of the heat dissipation cover is fixedly connected to the base plate.
The chip packaging structure according to claim 14, wherein the pulling column includes:

Adhesion glue pillar, one end of the adhesive glue pillar is bonded to the central part of the heat dissipation cover, and the other end is bonded to the substrate.
The chip packaging structure according to claim 14, wherein the pulling column includes:

a boss formed on a surface of the central portion of the heat dissipation cover facing the substrate;

Adhesion glue pillar, one end of the adhesive glue pillar is bonded to the boss, and the other end is bonded to the substrate.
The chip packaging structure according to claim 16, characterized in that:

The distance between the surface of the boss facing the substrate and the substrate is d1;

The distance between the surface of the outer edge portion facing the substrate and the substrate is d2;

Among them, d1 is greater than or equal to d2.
The chip packaging structure according to claim 14, characterized in that the chip packaging structure further includes:

At least one dummy chip, the at least one dummy chip and the plurality of chips are located on the same surface of the substrate, and the orthographic projection of the at least one dummy chip on the substrate is located in the first area.
The chip packaging structure according to claim 18, characterized in that the chip packaging structure further includes:

Adhesion glue pillar, one end of the adhesive glue pillar is bonded to the central part of the heat dissipation cover, and the other end is bonded to the dummy chip.
The chip packaging structure according to claim 14, wherein the pulling column includes:

A bonding glue column, the bonding glue column includes a first bonding glue column and a second bonding glue column;

support column;

One end of the support column is bonded to the central part of the heat dissipation cover through the first adhesive glue column, and the other end of the support column is bonded to the substrate through the second adhesive glue column. .
The chip packaging structure according to any one of claims 15-17, 19 or 20, characterized in that:

The chip packaging structure also includes:

An adhesive layer, the outer edge portion is fixedly connected to the substrate through the adhesive layer surrounding the periphery of the plurality of chips;

And the materials of the adhesive glue pillar and the adhesive glue layer are the same.
A method for preparing a chip packaging structure, which is characterized by including:

Multiple chips are arranged on the same surface of the substrate, and any one of the multiple chips is arranged on the substrate through an electrical connection structure;

forming a thermal interface material layer on a surface of any one of the plurality of chips away from the substrate;

The heat dissipation cover is disposed such that one or more protrusions on the central portion of the heat dissipation cover abut against the thermal interface material layer of at least one chip among the plurality of chips; wherein, the heat dissipation cover The central part is the part of the heat dissipation cover covering the side of the plurality of chips away from the substrate, and the one or more protrusions are provided on the central part of the heat dissipation cover facing the substrate. on the surface.
The method for manufacturing a chip packaging structure according to claim 22, wherein before setting the heat dissipation cover, the preparation method further includes:

Dot adhesive glue on the surface of the substrate that is opposite to the central part of the heat dissipation cover to form an adhesive glue column, so that after the heat dissipation cover is set, the adhesive glue column is fixed Connected between the base plate and the protruding portion.
The method of manufacturing a chip packaging structure according to claim 23, wherein adhesive is applied to a surface of the substrate that is opposite to the central part of the heat dissipation cover, and the manufacturing method further includes: :

Adhere glue along the circumferential points of the outer edge of the substrate to form an adhesive glue layer, so that the outer edge part of the heat dissipation cover is fixedly connected to the substrate through the adhesive glue layer, and the The material of the adhesive glue pillar and the adhesive glue layer are the same; wherein, the outer edge part of the heat dissipation cover is the part of the heat dissipation cover surrounding the periphery of the plurality of chips.
The method for manufacturing a chip packaging structure according to claim 22, wherein before setting the heat dissipation cover, the preparation method further includes:

One or more dummy chips are arranged on the surface of the substrate on which the plurality of chips are arranged, and the orthographic projection of the one or more dummy chips on the substrate is located in the first area, and the plurality of chips The rectangle enclosed by the orthographic projection on the substrate is the first area.
The method of manufacturing a chip packaging structure according to claim 25, wherein after arranging the one or more dummy chips and before arranging the heat dissipation cover, the preparation method further includes:

Dot adhesive glue on the surface of the one or more dummy chips away from the substrate, so that after the heat dissipation cover is installed, the dummy chip is fixedly connected to the protruding portion through the adhesive glue .
A method for preparing a chip packaging structure, which is characterized by including:

Multiple chips are arranged on the same surface of the substrate, and any one of the multiple chips is arranged on the substrate through an electrical connection structure;

One or more dummy chips are arranged on the surface of the substrate on which the plurality of chips are arranged, and the orthographic projection of the one or more dummy chips on the substrate is located in the first area, and the plurality of chips The rectangle enclosed by the orthographic projection on the substrate is the first area;

The heat dissipation cover is disposed such that a central portion of the heat dissipation cover covers a side of the plurality of chips and the one or more dummy chips away from the substrate.
The method for manufacturing a chip packaging structure according to claim 27, wherein before setting the heat dissipation cover, the preparation method further includes:

Dot adhesive glue on the surface of the one or more dummy chips away from the substrate, so that after the heat dissipation cover is installed, the dummy chip is connected to the heat dissipation cover through the adhesive glue. The central part is fixedly connected.
The method for preparing a chip packaging structure according to claim 28, wherein adhesive is applied on the surface of the one or more dummy chips away from the substrate, and the preparation method further includes:

Glue is adhered along the circumferential points of the outer edge of the substrate to form an adhesive layer, so that the outer edge portion of the heat dissipation cover is fixedly connected to the substrate through the adhesive layer and is located at the The adhesive on the dummy chip is made of the same material as the adhesive layer; wherein, the outer edge portion of the heat dissipation cover is the portion of the heat dissipation cover surrounding the periphery of the multiple chips.
A method for preparing a chip packaging structure, which is characterized by including:

A pulling column is provided on the surface of a substrate provided with multiple chips. The orthographic projection of the pulling column on the substrate is located in the first area. The orthographic projection of the multiple chips on the substrate encloses a The rectangle is the first area substrate;

A heat dissipation cover is provided such that the heat dissipation cover covers the central portion of the plurality of chips on a side away from the substrate and is fixedly connected to the substrate through the pulling column.
The method for preparing a chip packaging structure according to claim 30, wherein the step of arranging a pulling column on the surface of a substrate provided with multiple chips includes:

Dot adhesive glue on the surface of the substrate that is opposite to the central part of the heat dissipation cover to form an adhesive glue column, so that the adhesive glue column is fixedly connected between the substrate and the heat dissipation cover. Between the central portions of the heat dissipation cover, the adhesive glue columns form the pulling columns.
The method of manufacturing a chip packaging structure according to claim 31, wherein adhesive is applied to a surface of the substrate that is opposite to the central part of the heat dissipation cover, and the manufacturing method further includes: :

Adhere glue along the circumferential points of the outer edge of the substrate to form an adhesive glue layer, so that the outer edge part of the heat dissipation cover is fixedly connected to the substrate through the adhesive glue layer, and the The material of the adhesive glue pillar and the adhesive glue layer are the same; wherein, the outer edge part of the heat dissipation cover is the part of the heat dissipation cover surrounding the periphery of the plurality of chips.
The method for manufacturing a chip packaging structure according to any one of claims 30 to 32, wherein a protruding portion is formed on the surface of the central portion of the heat dissipation cover facing the substrate;

Before setting the heat dissipation cover, the preparation method further includes:

forming a thermal interface material layer on a surface of any one of the plurality of chips away from the substrate;

The heat dissipation cover included in the set includes:

The heat dissipation cover is installed such that the protruding portion of the heat dissipation cover abuts the thermal interface material layer of any of the chips.
The method for preparing a chip packaging structure according to any one of claims 30 to 23, characterized in that, before setting the heat dissipation cover, the preparation method further includes:

At least one dummy chip is disposed on the surface of the substrate on which the plurality of chips are disposed, and the orthographic projection of the at least one dummy chip on the substrate is located in the first area.
An electronic device, characterized by including:

printed circuit board;

The chip packaging structure according to any one of claims 1 to 21, or the chip packaging structure produced by the preparation method of the chip packaging structure according to any one of claims 22 to 34;

Wherein, the chip packaging structure is provided on the printed circuit board.