WO2023182376A1 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
WO2023182376A1
WO2023182376A1 PCT/JP2023/011297 JP2023011297W WO2023182376A1 WO 2023182376 A1 WO2023182376 A1 WO 2023182376A1 JP 2023011297 W JP2023011297 W JP 2023011297W WO 2023182376 A1 WO2023182376 A1 WO 2023182376A1
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WO
WIPO (PCT)
Prior art keywords
contact
insulating film
floating gate
silicon layer
semiconductor device
Prior art date
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PCT/JP2023/011297
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French (fr)
Japanese (ja)
Inventor
哲也 山本
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ラピスセミコンダクタ株式会社
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Publication of WO2023182376A1 publication Critical patent/WO2023182376A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND

Definitions

  • the present disclosure relates to a semiconductor device using silicon (Si), and particularly to a semiconductor device having a PPS (Poly-Si/Insulator/Poly-Si/Insulator/Si-substrate) element structure.
  • Si silicon
  • PPS Poly-Si/Insulator/Poly-Si/Insulator/Si-substrate
  • a PPS element structure in which a polycrystalline silicon layer and an insulating layer are laminated has the effect of suppressing the leakage of charge from the element to the substrate by suppressing the generation of stray capacitance within the element.
  • nonvolatile storage devices such as flash memory.
  • JP 2019-75414 A discloses a method that includes a polycrystalline silicon layer for a control gate and a polycrystalline silicon layer for forming a control gate of a peripheral circuit, and creates a PPS capacitor element by using these polycrystalline silicon layers.
  • a typical structure and manufacturing method of a possible memory cell for a flash memory having a floating gate with a protrusion at one end and a control gate are described.
  • JP 2016-51822 A describes a planar structure and a cross-sectional structure of a PPS capacitor that uses a gate electrode, a memory gate electrode, and silicon of a substrate as electrodes, which are required in the manufacture of nonvolatile memory.
  • the active contact is connected to the N-well over a long distance via the element isolation region, resulting in high resistance and making it difficult to set the potential of the active contact. There was a risk that it would become unstable.
  • the capacitive element disclosed in Japanese Patent Application Laid-open No. 2016-51822 is used in a booster circuit, etc. to generate the high voltage necessary for the operation of flash memory. Since it is assumed that the semiconductor device is formed outside the memory cell area, the area of the entire semiconductor device becomes large.
  • the present disclosure provides a semiconductor device in which a capacitive element used in a booster circuit or the like is arranged adjacent to a cell array of a memory element by using a part of the structure of a flash memory cell for a PPS capacitive element.
  • a first aspect of the present disclosure is a semiconductor device, which includes: a first silicon layer provided with a first contact to which a voltage is applied; a first insulating film formed directly under the first silicon layer; , a second silicon layer formed directly below the first insulating film, a second insulating film formed directly below the second silicon layer, and between the second insulating film and the semiconductor substrate.
  • a floating gate provided on the main surface of the semiconductor substrate substantially parallel to the main surface with a third insulating film interposed therebetween; and a floating gate provided on the floating gate.
  • a spacer provided between the floating gate and the spacer and covering each of the side surface on one end side of the spacer, the side surface on the one end side of the floating gate, and the main surface of the semiconductor substrate.
  • the insulating film No. 4 and the second silicon layer are stretched and formed, and the insulating film is formed on each of the main surface of the semiconductor substrate, the side surface on the one end side of the floating gate, and the side surface on the one end side of the spacer.
  • a control gate that is in contact with a fourth insulating film and has a second contact; a contact portion that is formed by extending the first silicon layer and is electrically connected to the first contact; and a surface layer of the semiconductor substrate.
  • a conductive layer which has one end connected to the diffusion layer, is in contact with the floating gate and the side surface of the other end of the spacer via a fifth insulating film, and has a third contact at the other end; It includes a member.
  • the capacitor element used in the booster circuit or the like can be placed adjacent to the cell array of the memory element.
  • FIG. 1 is a plan view showing an example of the configuration of a semiconductor device according to an exemplary embodiment.
  • FIG. 2 is a sectional view taken along line AA in FIG. 1.
  • FIG. FIG. 2 is a sectional view taken along line BB in FIG. 1.
  • FIG. FIG. 2 is a sectional view taken along line CC in FIG. 1.
  • FIG. FIG. 2 is a sectional view taken along line DD in FIG. 1.
  • FIG. 1 is a schematic diagram showing the configuration of a general memory cell and a booster circuit. 1 is a schematic diagram of a memory cell and a booster circuit to which the semiconductor device according to the exemplary embodiment is applied;
  • FIG. 1 is a plan view showing an example of the configuration of a PPS capacitive element that has been commonly used in the past.
  • 8 is a comparison diagram of a cross-sectional view taken along line EE in FIG. 7 and a capacitive element portion of the semiconductor device according to the exemplary embodiment.
  • FIG. 1 is a plan view showing an example of the configuration of a semiconductor device 10 according to this exemplary embodiment.
  • a memory element section 100 which is a flash memory
  • a capacitive element section 200 are formed on a semiconductor substrate 11.
  • the semiconductor substrate 11 a Si substrate is used, for example.
  • the capacitive element section 200 has a PPS structure in which a first gate polycrystalline silicon layer 107, a memory polysilicon layer 103, which is a polycrystalline silicon layer, and an N-well 114 are stacked with an insulating layer in between. have
  • FIG. 2 is a cross-sectional view taken along line AA in FIG. 1.
  • an HTO (High Temperature Oxide) tunnel 118 which is an insulating film, is provided in the upper layer of the N well 114 formed on the semiconductor substrate 11.
  • a memory poly layer 103 which is a polycrystalline silicon layer, is formed.
  • a first gate polycrystalline silicon layer 107 is formed on the memory poly layer 103 with a first gate oxide film 116, which is an insulating layer, interposed therebetween.
  • the capacitive element section 200 has a PPS element structure in which a polycrystalline silicon layer and an insulating layer are stacked.
  • the first gate polycrystalline silicon layer 107 is Poly-Si
  • the first gate oxide film 116 is an insulator
  • the memory poly layer 103 is Poly-Si
  • the HTO tunnel 118 is an insulator
  • the first gate oxide film 116 is an insulator.
  • the wells 114 correspond to Si-substrate.
  • a first contact 220 which is an electrical contact, is provided at the right end of the first gate polycrystalline silicon layer 107 in FIG.
  • An element isolation insulating film 120A which is an insulating layer, is provided at a portion of the N well 114 and the semiconductor substrate 11 corresponding to the first contact 220.
  • an element isolation insulating film 120B which is an insulating layer, is also provided at a portion where the first gate polycrystalline silicon layer 107 contacts the N well 114 and the semiconductor substrate 11 via the first gate oxide film 116.
  • FIG. 3 is a cross-sectional view taken along line BB in FIG. 1.
  • the memory element section 100 includes a memory cell 111a and a memory cell 111b, which are formed between two element isolation insulating films and are arranged symmetrically to each other. It is composed of a pair of Memory cells 111a and 111b share a source wiring 101 and a source 105 formed by an N+ diffusion layer. Since the memory cells 111a and 111b have the same configuration except for their orientations, the memory cell 111a will be described below as an example.
  • the memory cell 111a formed on the main surface 112 of the semiconductor substrate 11 includes a source 105, a source wiring 101, a gate insulating film 109a, a floating gate 108a, a spacer 102a, a memory poly layer 103, and a sidewall 104a. , a drain 106a, and a first gate polycrystalline silicon layer 107.
  • the memory poly layer 103 is formed by extending the memory poly layer 103 of the capacitive element section 200, and is configured to function as a control gate in the memory element section 100.
  • the first gate polycrystalline silicon layer 107 is formed by stretching the first gate polycrystalline silicon layer 107 of the capacitive element section 200, and functions as a contact section that electrically connects the first contact 220 and the semiconductor substrate 11. is configured to do so.
  • the source 105 is formed by diffusing impurities into the semiconductor substrate 11.
  • the source wiring 101 is connected to the source 105 and constitutes a source line of the memory element section 100.
  • the floating gate 108a is provided on a gate insulating film 109a formed on the semiconductor substrate 11.
  • a spacer 102a is formed on the floating gate 108a.
  • each of the floating gates 108a and 108b has a sharp portion that protrudes upward at a portion corresponding to the memory poly layer 103 via the tunnel insulating films 110a and 110b. Since electric field concentration occurs at the sharp parts of the floating gates 108a and 108b, the memory element section 100 can rewrite data at a relatively low voltage.
  • the memory poly layer 103 is formed on the semiconductor substrate 11 via the tunnel insulating film 110a, and constitutes a word line.
  • the memory poly layer 103 is arranged adjacent to the gate insulating film 109a, the floating gate 108a, and the spacer 102a via the tunnel insulating film 110a.
  • Sidewall 104a is formed adjacent to memory poly layer 103.
  • the drain 106a is formed by diffusing impurities into the semiconductor substrate 11.
  • a bit contact is formed by the drain 106a and the first gate polycrystalline silicon layer 107 connected to the drain 106a.
  • a gate insulating film 109 (109a, 109b) is formed on the surface of the semiconductor substrate 11 on which the source 105 is formed by diffusing impurities into the semiconductor substrate 11, and the surface of the gate insulating film 109 is formed by a CVD (chemical vapor deposition) method or the like.
  • Floating gates 108 (108a, 108b), which are polycrystalline silicon layers, are formed.
  • layers corresponding to the memory poly layer 103, spacers 102a, 102b, sidewalls 104a, 104b, and source wiring 101 are stacked, and etching is performed as appropriate to form memory cells 111a, 111b.
  • the memory element section 100 is formed by forming the first gate polycrystalline silicon layer 107 so as to cover the first gate polycrystalline silicon layer 107.
  • FIG. 4 is a cross-sectional view taken along line CC in FIG. 1.
  • the floating gates 108 (108a, 108b) are disposed in the storage element portion 100 shown in FIG.
  • each of the floating gate 108, the source 105, and one end of the source wiring 101 in contact with the source 105 is provided adjacent to the capacitive element section 200.
  • a portion of each of the floating gate 108, the source 105, and one end of the source wiring 101 may be in a positional relationship overlapping with the N-well 114 forming the capacitive element section 200. Therefore, the floating gate 108 is not provided in the cross-sectional view shown in FIG.
  • the source 105 is not formed on the semiconductor substrate 11 in contact with the source wiring 101.
  • a second contact 222 is provided at the upper end of the memory poly layer 103a, and by applying a voltage through the second contact 222, the memory poly layer 103 (103a, 103b) functions as a control gate in the flash memory. do.
  • FIG. 5 is a cross-sectional view taken along line DD in FIG. 1. Similar to the cross-sectional view shown in FIG. 4, the cross-sectional view shown in FIG. 5 does not include the floating gate 108, but the third contact 224 is connected to the source wiring 101.
  • writing is performed by injecting channel hot electrons generated in the semiconductor substrate 11 into the floating gate 108a. Further, data is erased by extracting electrons from the floating gate 108a to the memory poly layer 103 via the tunnel insulating film 110a. Furthermore, by applying a read voltage to the memory poly layer 103, the state (on, off) of the memory cell 111a is detected.
  • the voltage of the semiconductor substrate 11 is set to 0V, for example, and a predetermined voltage is applied to the memory poly layer 103 via the second contact 222 and to the source wiring 101 via the third contact 224, respectively.
  • a predetermined voltage is applied to the memory poly layer 103 via the second contact 222 and to the source wiring 101 via the third contact 224, respectively.
  • current flows in the channel region directly under the memory poly layer 103 and the floating gates 108 (108a, 108b), and channel hot electrons are injected into the floating gate 108 via the gate insulating films 109a, 109b.
  • the injected channel hot electrons are accumulated in the floating gate 108. Injection of channel hot electrons into the floating gate 108 increases the threshold voltage of the memory element portion 100.
  • the voltage of the drains 106a and 106b is set to 0V, and the third contact 224 is connected to the ground area.
  • a predetermined voltage is applied to the memory poly layer 103 via the second contact 222.
  • a Fowler-Nordheim tunneling current flows through the tunnel insulating films 110a and 110b, and electrons accumulated in the floating gate 108 are extracted to the memory poly layer 103 functioning as a control gate.
  • the threshold voltage of the memory element section 100 becomes lower than when electrons are accumulated in the floating gate 108. Note that a state in which electrons are accumulated in the floating gate 108 may be set as data "1", and a state in which electrons are not accumulated in the floating gate 108 may be set as data "0".
  • FIG. 6A is a schematic diagram showing the configuration of a general memory cell 240 and a booster circuit 242.
  • a booster circuit 242 that generates a voltage to be applied to the memory cell 240 is configured separately from the memory cell 240. If the memory cell 240 is a flash memory, a booster circuit 242 that generates a high voltage is required for operation, but if the booster circuit 242 is provided outside the area of the memory cell 240, the area of the entire device increases.
  • FIG. 6B is a schematic diagram of a memory cell 250 and a booster circuit 252 to which the semiconductor device 10 according to the present exemplary embodiment is applied.
  • the semiconductor device 10 according to the exemplary embodiment has a memory element section 100 and a capacitive element section in which a part of the structure of the memory element section 100, which is a flash memory, is used for a capacitive element section 200, which is a PPS capacitive element. 200 are inseparable from each other.
  • FIG. 6B it is possible to realize a structure in which memory cells 250 and booster circuits 252 are arranged adjacently and alternately on the same semiconductor substrate. With this structure, the area of the semiconductor device can be made smaller than the structure shown in FIG. 6A.
  • FIG. 7 is a plan view showing an example of the configuration of a capacitive element 300, which is a conventionally commonly used PPS capacitive element.
  • the first contact 320 is provided on the first gate polycrystalline silicon layer 307, as in the semiconductor device 10 according to the exemplary embodiment described above.
  • This exemplary embodiment also has a PPS structure in which the first gate polycrystalline silicon layer 307, the memory polysilicon layer 303, which is a polycrystalline silicon layer, and the N-well 314 are stacked with an insulating layer in between. This is common to the semiconductor device 10 according to the above.
  • the second contact 322 is connected to the memory poly layer 303 through the recess 330 created by removing the first gate oxide film 316, and the third contact 324 is connected to the end of the N-well 114. This is different from the semiconductor device 10 according to the exemplary embodiment.
  • FIG. 8(1) is a cross-sectional view taken along line EE in FIG. 7.
  • the capacitive element 300 includes an HTO tunnel 318, which is an insulating film, provided in the upper layer of an N well 314 formed on the main surface 311 of the semiconductor substrate, and the HTO tunnel 318, which is an insulating film, A memory poly layer 303 is formed therein. Furthermore, a first gate polycrystalline silicon layer 307 is formed on the memory poly layer 303 with a first gate oxide film 316, which is an insulating layer, interposed therebetween. As a result, the capacitive element 300 has a PPS element structure in which a polycrystalline silicon layer and an insulating layer are stacked.
  • the first gate polycrystalline silicon layer 307 is Poly-Si
  • the first gate oxide film 316 is an insulator
  • the memory poly layer 303 is Poly-Si
  • the HTO tunnel 318 is an insulator
  • the first gate oxide film 316 is an insulator.
  • the wells 314 correspond to Si-substrate.
  • An element isolation insulating film 326A which is an insulating layer, is provided at a portion of the N-well 114 and the semiconductor substrate 11 corresponding to the first contact 220. Further, an element isolation insulating film 326B, which is an insulating layer, is also provided at each portion of the N well 114 and the semiconductor substrate 11 corresponding to the second contact 322 and the recess 330.
  • the yield of the capacitive element 300 deteriorates due to damage to the memory poly layer 103 or the HTO tunnel 318 due to dry etching or the like when forming the recess 330 and arranging the second contact 322.
  • the element isolation insulating film 326B is enlarged, the area of the N well 314 is reduced, and there is a possibility that the performance as a capacitor element will be degraded.
  • FIG. 8(2) is a cross-sectional view of the capacitive element section 200 of the semiconductor device 10 according to the present exemplary embodiment, and is the same drawing as FIG. 2 described above.
  • the semiconductor device 10 according to the present exemplary embodiment has a recess 330 and a second It is not necessary to provide the contact 222 in the capacitive element section 200.
  • the element isolation insulating film 120B for suppressing deterioration in yield of the semiconductor device 10 can be reduced in size compared to the structure shown in FIG. 8(1).
  • the capacitive element portion 200 of the semiconductor device 10 Comparing (1) and (2) of FIG. 8, the capacitive element portion 200 of the semiconductor device 10 according to the present exemplary embodiment has a larger element size by ⁇ D than the capacitive element 300 shown in (2).
  • the isolation insulating film 120B By reducing the isolation insulating film 120B, the area of the N well 114 can be expanded more than in the configuration shown in (1).
  • each of the second contact 222 and the third contact 224 of the PPS capacitive element is connected to the structure of a part of the storage element section 100 constituting a flash memory.
  • the capacitive element section 200 can be formed adjacent to the cell array of the memory element section 100, which is a flash memory, it is possible not only to reduce the chip area, but also to reduce the chip area. Since a part of the terminal structure of the PPS capacitive element can be shared with the memory element section 100, there is also an effect that voltage drop due to parasitic resistance in the voltage applied to the memory element section 100 can be suppressed.
  • the semiconductor device according to the exemplary embodiment of the present disclosure described above is only an example, and it is possible to omit, add, or modify the configuration, change the materials used, etc. without departing from the spirit of the present disclosure. .
  • first silicon layer is the “first gate polycrystalline silicon layer 107”
  • first insulating film is the “first gate oxide film 116”
  • second silicon layer is the “memory polycrystalline silicon layer 107.”
  • second insulating film is connected to the "HTO tunnel 118”
  • third insulating film is connected to the "gate insulating films 109a, 109b”
  • fourth insulating film is connected to the "tunnel insulating film 110a”.
  • the "diffusion layer” is connected to the "source 105”
  • the "conductive member” is connected to the “source wiring 101”
  • the "first contact” is connected to the “first contact 220”
  • the “second contact” is connected to the “second contact”. 2 contact 222”
  • the "third contact” corresponds to "third contact 224”, respectively.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

In this semiconductor device: each of a source that is formed on a main surface of a semiconductor substrate and a floating gate that contacts the main surface with an insulating film therebetween is provided adjacent to a capacitive element portion, the source and the floating gate forming a storage element portion; a first gate polycrystalline silicon layer of the capacitive element portion is extended to form a contact portion of the storage element portion, and a memory poly-layer of the capacitive element portion is extended to form a control gate of the storage element portion; a first contact is provided on the capacitive element portion side of the first gate polycrystalline silicon layer; a second contact is provided in a position spaced apart from the capacitive element portion in the control gate; and a third contact is provided in a position spaced apart from the capacitive element portion in a source wire in contact with the source.

Description

半導体装置semiconductor equipment
　本開示は、シリコン（Ｓｉ）を用いた半導体装置であり、特にＰＰＳ（Ｐｏｌｙ－Ｓｉ/Ｉｎｓｕｌａｔｏｒ/Ｐｏｌｙ－Ｓｉ/ Ｉｎｓｕｌａｔｏｒ/Ｓｉ－ｓｕｂｓｔｒａｔｅ）素子構造を有する半導体装置に関する。 The present disclosure relates to a semiconductor device using silicon (Si), and particularly to a semiconductor device having a PPS (Poly-Si/Insulator/Poly-Si/Insulator/Si-substrate) element structure.
　多結晶シリコン層と絶縁層とが積層されたＰＰＳ素子構造は、素子内での浮遊容量の発生を抑制することにより、素子からサブストレートへの電荷のリーク抑制する効果があることから、容量素子、又はフラッシュメモリ等の不揮発性記憶装置に応用されている。 A PPS element structure in which a polycrystalline silicon layer and an insulating layer are laminated has the effect of suppressing the leakage of charge from the element to the substrate by suppressing the generation of stray capacitance within the element. , or nonvolatile storage devices such as flash memory.
　特開２０１９－７５４１４号公報には、コントロールゲート用の多結晶シリコン層と、周辺回路の制御ゲート形成用の多結晶シリコン層とを備え、これら多結晶シリコン層を用いることでＰＰＳ容量素子を作成可能な、一端部に突起を持つフローティングゲートとコントロールゲートを持つフラッシュメモリ用のメモリセルの代表的な構造及び製造方法が記載されている。 JP 2019-75414 A discloses a method that includes a polycrystalline silicon layer for a control gate and a polycrystalline silicon layer for forming a control gate of a peripheral circuit, and creates a PPS capacitor element by using these polycrystalline silicon layers. A typical structure and manufacturing method of a possible memory cell for a flash memory having a floating gate with a protrusion at one end and a control gate are described.
　特開２０１６－５１８２２号公報には、不揮発性メモリの製造で必要となるゲート電極とメモリゲート電極と基板のシリコンを電極と使用するＰＰＳ容量の平面構造及び断面構造が記載されている。 JP 2016-51822 A describes a planar structure and a cross-sectional structure of a PPS capacitor that uses a gate electrode, a memory gate electrode, and silicon of a substrate as electrodes, which are required in the manufacture of nonvolatile memory.
　しかしながら、特開２０１９－７５４１４号公報に開示されたフラッシュメモリセルは、メモリ多結晶シリコン層、制御ゲート多結晶シリコン層、アクティブコンタクトの３端子に引き出しのコンタクトを形成する必要がある。その結果、メモリ多結晶シリコン層のエッジ部及び制御ゲート多結晶シリコン層のエッジ部等が容量素子領域内に形成されるため、寄生容量が多くなり、容量素子としての精度の低下、アクティブコンタクトのエッジ部での絶縁膜の薄膜化等によって素子の信頼性低下、又は素子の歩留まり低下のおそれがあった。 However, in the flash memory cell disclosed in Japanese Unexamined Patent Application Publication No. 2019-75414, it is necessary to form lead-out contacts at three terminals: the memory polycrystalline silicon layer, the control gate polycrystalline silicon layer, and the active contact. As a result, the edges of the memory polycrystalline silicon layer and the control gate polycrystalline silicon layer are formed within the capacitive element region, resulting in an increase in parasitic capacitance, a decrease in the accuracy of the capacitive element, and an active contact. There is a risk that the reliability of the device or the yield of the device will decrease due to thinning of the insulating film at the edge portion.
　特開２０１６－５１８２２号公報に開示されたＰＰＳ容量素子は、アクティブコンタクトが素子分離領域を介してＮウェルで長い距離を経て接続されているため、高抵抗となり、アクティブコンタクトの電位の設定が不安定になりやすいおそれがあった。また、特開２０１６－５１８２２号公報に開示された容量素子は、フラッシュメモリの動作に必要な高電圧を形成するための、昇圧回路等に使用されるものの、かかる昇圧回路を含む電源回路をフラッシュメモリセル領域の外に作成することを前提とするため、半導体装置全体の面積が大きくなる。 In the PPS capacitive element disclosed in Japanese Patent Application Laid-open No. 2016-51822, the active contact is connected to the N-well over a long distance via the element isolation region, resulting in high resistance and making it difficult to set the potential of the active contact. There was a risk that it would become unstable. Furthermore, the capacitive element disclosed in Japanese Patent Application Laid-open No. 2016-51822 is used in a booster circuit, etc. to generate the high voltage necessary for the operation of flash memory. Since it is assumed that the semiconductor device is formed outside the memory cell area, the area of the entire semiconductor device becomes large.
　本開示は、フラッシュメモリセルの構造の一部をＰＰＳ容量素子に流用することにより、昇圧回路等に用いる容量素子を記憶素子のセルアレイに隣接して配置した半導体装置を提供する。 The present disclosure provides a semiconductor device in which a capacitive element used in a booster circuit or the like is arranged adjacent to a cell array of a memory element by using a part of the structure of a flash memory cell for a PPS capacitive element.
　本開示の第１の態様は、半導体装置であって、電圧が印加される第１接点が設けられた第１シリコン層と、前記第１シリコン層の直下に形成された第１の絶縁膜と、前記第１の絶縁膜の直下に形成された第２シリコン層と、前記第２シリコン層の直下に形成された第２の絶縁膜と、前記第２の絶縁膜と半導体基板との間に形成されたＮウェルと、を含む容量素子を備え、前記半導体基板の主面上に第３の絶縁膜を介して前記主面と略平行に設けられたフローティングゲートと、前記フローティングゲート上に設けられたスペーサと、前記フローティングゲートと前記スペーサとの間に設けられ、且つ前記スペーサの一端側の側面、前記フローティングゲートの前記一端側の側面、及び前記半導体基板の前記主面の各々を覆う第４の絶縁膜と、前記第２シリコン層が延伸されて形成され、前記半導体基板の前記主面、前記フローティングゲートの前記一端側の側面、及び前記スペーサの前記一端側の側面の各々に、前記第４の絶縁膜を介して接し、第２接点を備えたコントロールゲートと、前記第１シリコン層が延伸されて形成され、前記第１接点と導通するコンタクト部と、前記半導体基板の表層部に設けられた拡散層と、一端が前記拡散層に接続され、且つ前記フローティングゲート及び前記スペーサの他端側の側面に、第５の絶縁膜を介して接し、他端に第３接点を有する導電部材と、を含むものである。 A first aspect of the present disclosure is a semiconductor device, which includes: a first silicon layer provided with a first contact to which a voltage is applied; a first insulating film formed directly under the first silicon layer; , a second silicon layer formed directly below the first insulating film, a second insulating film formed directly below the second silicon layer, and between the second insulating film and the semiconductor substrate. a floating gate provided on the main surface of the semiconductor substrate substantially parallel to the main surface with a third insulating film interposed therebetween; and a floating gate provided on the floating gate. a spacer provided between the floating gate and the spacer and covering each of the side surface on one end side of the spacer, the side surface on the one end side of the floating gate, and the main surface of the semiconductor substrate. The insulating film No. 4 and the second silicon layer are stretched and formed, and the insulating film is formed on each of the main surface of the semiconductor substrate, the side surface on the one end side of the floating gate, and the side surface on the one end side of the spacer. a control gate that is in contact with a fourth insulating film and has a second contact; a contact portion that is formed by extending the first silicon layer and is electrically connected to the first contact; and a surface layer of the semiconductor substrate. a conductive layer, which has one end connected to the diffusion layer, is in contact with the floating gate and the side surface of the other end of the spacer via a fifth insulating film, and has a third contact at the other end; It includes a member.
　上記態様によれば、本開示の半導体装置は、フラッシュメモリセルの構造の一部をＰＰＳ容量素子に流用することにより、昇圧回路等に用いる容量素子を記憶素子のセルアレイに隣接して配置できる。 According to the above aspect, in the semiconductor device of the present disclosure, by using a part of the structure of the flash memory cell for the PPS capacitor element, the capacitor element used in the booster circuit or the like can be placed adjacent to the cell array of the memory element.
本例示的実施形態に係る半導体装置の構成の一例を示した平面図である。1 is a plan view showing an example of the configuration of a semiconductor device according to an exemplary embodiment. 図１のＡＡ線に沿った断面図である。FIG. 2 is a sectional view taken along line AA in FIG. 1. FIG. 図１のＢＢ線に沿った断面図である。FIG. 2 is a sectional view taken along line BB in FIG. 1. FIG. 図１のＣＣ線に沿った断面図である。FIG. 2 is a sectional view taken along line CC in FIG. 1. FIG. 図１のＤＤ線に沿った断面図である。FIG. 2 is a sectional view taken along line DD in FIG. 1. FIG. 一般的なメモリセルと、昇圧回路との構成を示した概略図である。1 is a schematic diagram showing the configuration of a general memory cell and a booster circuit. 本例示的実施形態に係る半導体装置を応用したメモリセルと昇圧回路との概略図である。1 is a schematic diagram of a memory cell and a booster circuit to which the semiconductor device according to the exemplary embodiment is applied; FIG. 従来、一般的に用いられてきたＰＰＳ容量素子の構成の一例を示した平面図である。1 is a plan view showing an example of the configuration of a PPS capacitive element that has been commonly used in the past. 図７のＥＥ線に沿った断面図と、本例示的実施形態に係る半導体装置の容量素子部の比較図である。8 is a comparison diagram of a cross-sectional view taken along line EE in FIG. 7 and a capacitive element portion of the semiconductor device according to the exemplary embodiment. FIG.
　以下、図面を参照して、本開示を実施するための形態について詳細に説明する。図１は、本例示的実施形態に係る半導体装置１０の構成の一例を示した平面図である。図１に示したように、半導体装置１０は、半導体基板１１上に、フラッシュメモリである記憶素子部１００と、容量素子部２００とが形成されている。半導体基板１１は、一例としてＳｉ基板を用いている。後述するように、容量素子部２００は、第１ゲート多結晶シリコン層１０７と、多結晶シリコン層であるメモリポリ層１０３と、Ｎウェル１１４とが、各々絶縁層を介して積層されたＰＰＳ構造を有する。 Hereinafter, embodiments for carrying out the present disclosure will be described in detail with reference to the drawings. FIG. 1 is a plan view showing an example of the configuration of a semiconductor device 10 according to this exemplary embodiment. As shown in FIG. 1, in the semiconductor device 10, a memory element section 100, which is a flash memory, and a capacitive element section 200 are formed on a semiconductor substrate 11. As the semiconductor substrate 11, a Si substrate is used, for example. As will be described later, the capacitive element section 200 has a PPS structure in which a first gate polycrystalline silicon layer 107, a memory polysilicon layer 103, which is a polycrystalline silicon layer, and an N-well 114 are stacked with an insulating layer in between. have
　図２は、図１のＡＡ線に沿った断面図である。図２に示したように、容量素子部２００は、半導体基板１１上に形成されたＮウェル１１４の上層に絶縁膜であるＨＴＯ（Ｈｉｇｈ　Ｔｅｍｐｅｒａｔｕｒｅ　Ｏｘｉｄｅ）トンネル１１８が設けられ、ＨＴＯトンネル１１８の上層には、多結晶シリコン層であるメモリポリ層１０３が形成されている。さらに、メモリポリ層１０３の上層には絶縁層である第１ゲート酸化膜１１６を介して第１ゲート多結晶シリコン層１０７が形成されている。その結果、容量素子部２００は、多結晶シリコン層と絶縁層とが積層されたＰＰＳ素子構造を有する。具体的には、第１ゲート多結晶シリコン層１０７はＰｏｌｙ－Ｓｉであり、第１ゲート酸化膜１１６はＩｎｓｕｌａｔｏｒであり、メモリポリ層１０３はＰｏｌｙ－Ｓｉであり、ＨＴＯトンネル１１８はＩｎｓｕｌａｔｏｒであり、Ｎウェル１１４はＳｉ－ｓｕｂｓｔｒａｔｅに各々該当する。 FIG. 2 is a cross-sectional view taken along line AA in FIG. 1. As shown in FIG. 2, in the capacitive element section 200, an HTO (High Temperature Oxide) tunnel 118, which is an insulating film, is provided in the upper layer of the N well 114 formed on the semiconductor substrate 11. A memory poly layer 103, which is a polycrystalline silicon layer, is formed. Furthermore, a first gate polycrystalline silicon layer 107 is formed on the memory poly layer 103 with a first gate oxide film 116, which is an insulating layer, interposed therebetween. As a result, the capacitive element section 200 has a PPS element structure in which a polycrystalline silicon layer and an insulating layer are stacked. Specifically, the first gate polycrystalline silicon layer 107 is Poly-Si, the first gate oxide film 116 is an insulator, the memory poly layer 103 is Poly-Si, the HTO tunnel 118 is an insulator, and the first gate oxide film 116 is an insulator. The wells 114 correspond to Si-substrate.
　第１ゲート多結晶シリコン層１０７の、図２における右側端部には、電気接点である第１コンタクト２２０が設けられている。第１コンタクト２２０に対応するＮウェル１１４及び半導体基板１１の部位には、絶縁層である素子分離絶縁膜１２０Ａが設けられている。また、第１ゲート多結晶シリコン層１０７が、第１ゲート酸化膜１１６を介してＮウェル１１４及び半導体基板１１に接する部位にも絶縁層である素子分離絶縁膜１２０Ｂが設けられている。 A first contact 220, which is an electrical contact, is provided at the right end of the first gate polycrystalline silicon layer 107 in FIG. An element isolation insulating film 120A, which is an insulating layer, is provided at a portion of the N well 114 and the semiconductor substrate 11 corresponding to the first contact 220. Further, an element isolation insulating film 120B, which is an insulating layer, is also provided at a portion where the first gate polycrystalline silicon layer 107 contacts the N well 114 and the semiconductor substrate 11 via the first gate oxide film 116.
　図３は、図１のＢＢ線に沿った断面図である。図３に示すように、本実施の形態に係る記憶素子部１００は、２つの素子分離絶縁膜の間に形成された、互いに面対称に対向して配置されたメモリセル１１１ａおよびメモリセル１１１ｂからなる対を含んで構成されている。メモリセル１１１ａと１１１ｂとは、ソース配線１０１およびＮ＋拡散層で形成されるソース１０５を共用している。メモリセル１１１ａと１１１ｂとは向きが異なる以外同様の構成であるので、以下メモリセル１１１ａを例示して説明する。 FIG. 3 is a cross-sectional view taken along line BB in FIG. 1. As shown in FIG. 3, the memory element section 100 according to the present embodiment includes a memory cell 111a and a memory cell 111b, which are formed between two element isolation insulating films and are arranged symmetrically to each other. It is composed of a pair of Memory cells 111a and 111b share a source wiring 101 and a source 105 formed by an N+ diffusion layer. Since the memory cells 111a and 111b have the same configuration except for their orientations, the memory cell 111a will be described below as an example.
　図３に示すように、半導体基板１１の主面１１２上に形成されたメモリセル１１１ａは、ソース１０５、ソース配線１０１、ゲート絶縁膜１０９ａ、フローティングゲート１０８ａ、スペーサ１０２ａ、メモリポリ層１０３、サイドウォール１０４ａ、ドレイン１０６ａ、および第１ゲート多結晶シリコン層１０７を含んで構成されている。メモリポリ層１０３は、図１に示したように、容量素子部２００のメモリポリ層１０３が延伸されて形成され、記憶素子部１００においては、コントロールゲートして機能するように構成されている。第１ゲート多結晶シリコン層１０７は、容量素子部２００の第１ゲート多結晶シリコン層１０７が延伸されて形成され、第１コンタクト２２０と、半導体基板１１とを電気的に接続するコンタクト部として機能するように構成されている。 As shown in FIG. 3, the memory cell 111a formed on the main surface 112 of the semiconductor substrate 11 includes a source 105, a source wiring 101, a gate insulating film 109a, a floating gate 108a, a spacer 102a, a memory poly layer 103, and a sidewall 104a. , a drain 106a, and a first gate polycrystalline silicon layer 107. As shown in FIG. 1, the memory poly layer 103 is formed by extending the memory poly layer 103 of the capacitive element section 200, and is configured to function as a control gate in the memory element section 100. The first gate polycrystalline silicon layer 107 is formed by stretching the first gate polycrystalline silicon layer 107 of the capacitive element section 200, and functions as a contact section that electrically connects the first contact 220 and the semiconductor substrate 11. is configured to do so.
　ソース１０５は半導体基板１１に不純物を拡散させて形成されている。ソース配線１０１はソース１０５に接続され、記憶素子部１００のソースラインを構成している。 The source 105 is formed by diffusing impurities into the semiconductor substrate 11. The source wiring 101 is connected to the source 105 and constitutes a source line of the memory element section 100.
フローティングゲート１０８ａは半導体基板１１上に形成されたゲート絶縁膜１０９ａ上に設けられている。フローティングゲート１０８ａ上にはスペーサ１０２ａが形成されている。図３に示したように、フローティングゲート１０８ａ、１０８ｂの各々がトンネル絶縁膜１１０ａ、１１０ｂを介して、メモリポリ層１０３に対応する部位は上部に突き出たような尖鋭部を呈する。フローティングゲート１０８ａ、１０８ｂは、かかる尖鋭部において電界集中が生じるので、記憶素子部１００は、比較的低い電圧でデータの書き替えを行うことが可能である。 The floating gate 108a is provided on a gate insulating film 109a formed on the semiconductor substrate 11. A spacer 102a is formed on the floating gate 108a. As shown in FIG. 3, each of the floating gates 108a and 108b has a sharp portion that protrudes upward at a portion corresponding to the memory poly layer 103 via the tunnel insulating films 110a and 110b. Since electric field concentration occurs at the sharp parts of the floating gates 108a and 108b, the memory element section 100 can rewrite data at a relatively low voltage.
　メモリポリ層１０３は、トンネル絶縁膜１１０ａを介して半導体基板１１上に形成され、ワードラインを構成している。メモリポリ層１０３は、トンネル絶縁膜１１０ａを介して、ゲート絶縁膜１０９ａ、フローティングゲート１０８ａ、およびスペーサ１０２ａに隣接して配置されている。サイドウォール１０４ａは、メモリポリ層１０３に隣接して形成されている。ドレイン１０６ａは半導体基板１１に不純物を拡散させて形成されている。ドレイン１０６ａおよびドレイン１０６ａに接続された第１ゲート多結晶シリコン層１０７によりビットコンタクトが構成されている。 The memory poly layer 103 is formed on the semiconductor substrate 11 via the tunnel insulating film 110a, and constitutes a word line. The memory poly layer 103 is arranged adjacent to the gate insulating film 109a, the floating gate 108a, and the spacer 102a via the tunnel insulating film 110a. Sidewall 104a is formed adjacent to memory poly layer 103. The drain 106a is formed by diffusing impurities into the semiconductor substrate 11. A bit contact is formed by the drain 106a and the first gate polycrystalline silicon layer 107 connected to the drain 106a.
　以下に、図３に示した記憶素子部１００を形成する手順の一例について簡単に説明する。まず、半導体基板１１に不純物を拡散させてソース１０５を形成した半導体基板１１の表面にゲート絶縁膜１０９（１０９ａ、１０９ｂ）を形成し、ＣＶＤ（ｃｈｅｍｉｃａｌｖａｐｏｒ ｄｅｐｏｓｉｔｉｏｎ）法等によりゲート絶縁膜１０９の表面に多結晶シリコン層であるフローティングゲート１０８（１０８ａ、１０８ｂ）を形成する。以後、メモリポリ層１０３、スペーサ１０２ａ、１０２ｂ、サイドウォール１０４ａ、１０４ｂ、及びソース配線１０１に各々該当する層を積層し、適宜、エッチング処理を行うことでメモリセル１１１ａ、１１１ｂを形成し、メモリセル１１１ａ、１１１ｂを覆うように第１ゲート多結晶シリコン層１０７を形成することにより、記憶素子部１００が形成される。 An example of a procedure for forming the memory element section 100 shown in FIG. 3 will be briefly described below. First, a gate insulating film 109 (109a, 109b) is formed on the surface of the semiconductor substrate 11 on which the source 105 is formed by diffusing impurities into the semiconductor substrate 11, and the surface of the gate insulating film 109 is formed by a CVD (chemical vapor deposition) method or the like. Floating gates 108 (108a, 108b), which are polycrystalline silicon layers, are formed. Thereafter, layers corresponding to the memory poly layer 103, spacers 102a, 102b, sidewalls 104a, 104b, and source wiring 101 are stacked, and etching is performed as appropriate to form memory cells 111a, 111b. , 111b, the memory element section 100 is formed by forming the first gate polycrystalline silicon layer 107 so as to cover the first gate polycrystalline silicon layer 107.
　図４は、図１のＣＣ線に沿った断面図である。本例示的実施形態では、図１に示すように、フローティングゲート１０８（１０８ａ、１０８ｂ）は、図１に示した記憶素子部１００に配設されている。具体的には、フローティングゲート１０８、ソース１０５、及びソース１０５と接するソース配線１０１の一端の各々は、容量素子部２００に隣接して設けられる。フローティングゲート１０８、ソース１０５、及びソース配線１０１の一端の各々の一部は、容量素子部２００を構成するＮウェル１１４と重複する位置関係にあってもよい。従って、図４で示した断面図の箇所にフローティングゲート１０８は設けられず、ソース配線１０１が接する半導体基板１１上にはソース１０５は形成されていない。しかしながら、メモリポリ層１０３ａの上端部には第２コンタクト２２２が設けられ、第２コンタクト２２２を介して電圧が印加されることにより、メモリポリ層１０３（１０３ａ、１０３ｂ）は、フラッシュメモリにおけるコントロールゲートとして機能する。 FIG. 4 is a cross-sectional view taken along line CC in FIG. 1. In the exemplary embodiment, as shown in FIG. 1, the floating gates 108 (108a, 108b) are disposed in the storage element portion 100 shown in FIG. Specifically, each of the floating gate 108, the source 105, and one end of the source wiring 101 in contact with the source 105 is provided adjacent to the capacitive element section 200. A portion of each of the floating gate 108, the source 105, and one end of the source wiring 101 may be in a positional relationship overlapping with the N-well 114 forming the capacitive element section 200. Therefore, the floating gate 108 is not provided in the cross-sectional view shown in FIG. 4, and the source 105 is not formed on the semiconductor substrate 11 in contact with the source wiring 101. However, a second contact 222 is provided at the upper end of the memory poly layer 103a, and by applying a voltage through the second contact 222, the memory poly layer 103 (103a, 103b) functions as a control gate in the flash memory. do.
　図５は、図１のＤＤ線に沿った断面図である。図５に示した断面図は、図４に示した断面図と同様に、フローティングゲート１０８は設けられていないが、第３コンタクト２２４がソース配線１０１に接続されている。 FIG. 5 is a cross-sectional view taken along line DD in FIG. 1. Similar to the cross-sectional view shown in FIG. 4, the cross-sectional view shown in FIG. 5 does not include the floating gate 108, but the third contact 224 is connected to the source wiring 101.
　以上のように構成された記憶素子部１００では、半導体基板１１に発生したチャネルホットエレクトロンが、フローティングゲート１０８ａに注入されることで、書き込みが行われる。また、フローティングゲート１０８ａからトンネル絶縁膜１１０ａを介してメモリポリ層１０３に電子を引き抜くことでデータの消去が行われる。さらに、メモリポリ層１０３に読み出し用の電圧を印加することで、メモリセル１１１ａの状態（オン、オフ）を検出している。 In the memory element section 100 configured as described above, writing is performed by injecting channel hot electrons generated in the semiconductor substrate 11 into the floating gate 108a. Further, data is erased by extracting electrons from the floating gate 108a to the memory poly layer 103 via the tunnel insulating film 110a. Furthermore, by applying a read voltage to the memory poly layer 103, the state (on, off) of the memory cell 111a is detected.
　より具体的には、半導体基板１１の電圧を例えば０Ｖとし、第２コンタクト２２２を介してメモリポリ層１０３に、及び第３コンタクト２２４を介してソース配線１０１にそれぞれ、所定の電圧を印加する。これにより、メモリポリ層１０３及びフローティングゲート１０８（１０８ａ、１０８ｂ）の直下のチャネル領域に電流が流れ、ゲート絶縁膜１０９ａ、１０９ｂを介してフローティングゲート１０８にチャネルホットエレクトロンが注入される。注入されたチャネルホットエレクトロンは、フローティングゲート１０８に蓄積される。フローティングゲート１０８へのチャネルホットエレクトロンの注入により記憶素子部１００のスレッショルド電圧が高くなる。一方、記憶素子部１００に書き込まれたデータ“０”を、データ“１”に書き換える場合（データを消去する場合）、ドレイン１０６ａ、１０６ｂの電圧を０Ｖにすると共に、第３コンタクト２２４を接地領域に接続することによりソース１０５の電圧を例えば０Ｖとし、第２コンタクト２２２を介してメモリポリ層１０３に所定の電圧を印加する。これにより、トンネル絶縁膜１１０ａ、１１０ｂに、ファウラー・ノルドハイム・トンネル電流（Ｆｏｗｌｅｒ－Ｎｏｒｄｈｅｉｍ　Ｔｕｎｎｅｌｉｎｇ　Ｃｕｒｒｅｎｔ）が流れ、フローティングゲート１０８に蓄積された電子が、コントロールゲートとして機能するメモリポリ層１０３に引き抜かれる。これにより、フローティングゲート１０８に電子が蓄積されている場合と比較して、記憶素子部１００のスレッショルド電圧が低くなる。なお、フローティングゲート１０８に電子が蓄積されている状態をデータ“１”とし、フローティングゲートに電子が蓄積されていない状態をデータ“０”としてもよい。 More specifically, the voltage of the semiconductor substrate 11 is set to 0V, for example, and a predetermined voltage is applied to the memory poly layer 103 via the second contact 222 and to the source wiring 101 via the third contact 224, respectively. As a result, current flows in the channel region directly under the memory poly layer 103 and the floating gates 108 (108a, 108b), and channel hot electrons are injected into the floating gate 108 via the gate insulating films 109a, 109b. The injected channel hot electrons are accumulated in the floating gate 108. Injection of channel hot electrons into the floating gate 108 increases the threshold voltage of the memory element portion 100. On the other hand, when rewriting data "0" written in the memory element section 100 to data "1" (when erasing data), the voltage of the drains 106a and 106b is set to 0V, and the third contact 224 is connected to the ground area. By connecting the source 105 to, for example, 0V, a predetermined voltage is applied to the memory poly layer 103 via the second contact 222. As a result, a Fowler-Nordheim tunneling current flows through the tunnel insulating films 110a and 110b, and electrons accumulated in the floating gate 108 are extracted to the memory poly layer 103 functioning as a control gate. As a result, the threshold voltage of the memory element section 100 becomes lower than when electrons are accumulated in the floating gate 108. Note that a state in which electrons are accumulated in the floating gate 108 may be set as data "1", and a state in which electrons are not accumulated in the floating gate 108 may be set as data "0".
　図６Ａは、一般的なメモリセル２４０と、昇圧回路２４２との構成を示した概略図である。図６Ａに示したように、メモリセル２４０に印加する電圧を生成する昇圧回
路２４２をメモリセル２４０とは別体で構成している。メモリセル２４０がフラッシュメモリの場合、動作させるには高電圧を生成する昇圧回路２４２が必要となるが、昇圧回路２４２をメモリセル２４０の領域外に設けると、装置全体の面積が大きくなる。 FIG. 6A is a schematic diagram showing the configuration of a general memory cell 240 and a booster circuit 242. As shown in FIG. 6A, a booster circuit 242 that generates a voltage to be applied to the memory cell 240 is configured separately from the memory cell 240. If the memory cell 240 is a flash memory, a booster circuit 242 that generates a high voltage is required for operation, but if the booster circuit 242 is provided outside the area of the memory cell 240, the area of the entire device increases.
　図６Ｂは、本例示的実施形態に係る半導体装置１０を応用したメモリセル２５０と昇圧回路２５２との概略図である。本例示的実施形態に係る半導体装置１０は、フラッシュメモリである記憶素子部１００の構造の一部を、ＰＰＳ容量素子である容量素子部２００に流用するような、記憶素子部１００と容量素子部２００とが一体不可分な構成となっている。その結果、図６Ｂに示したように、同一の半導体基板上にメモリセル２５０と昇圧回路２５２とを各々隣接させて、交互に配設した構造を実現できる。かかる構造により、半導体装置の面積を図６Ａに示した構造よりも縮小できる。 FIG. 6B is a schematic diagram of a memory cell 250 and a booster circuit 252 to which the semiconductor device 10 according to the present exemplary embodiment is applied. The semiconductor device 10 according to the exemplary embodiment has a memory element section 100 and a capacitive element section in which a part of the structure of the memory element section 100, which is a flash memory, is used for a capacitive element section 200, which is a PPS capacitive element. 200 are inseparable from each other. As a result, as shown in FIG. 6B, it is possible to realize a structure in which memory cells 250 and booster circuits 252 are arranged adjacently and alternately on the same semiconductor substrate. With this structure, the area of the semiconductor device can be made smaller than the structure shown in FIG. 6A.
　図７は、従来、一般的に用いられてきたＰＰＳ容量素子である容量素子３００の構成の一例を示した平面図である。図７に示したように、第１ゲート多結晶シリコン層３０７に第１コンタクト３２０が配設されているのは、上述の本例示的実施形態に係る半導体装置１０と同様である。また、第１ゲート多結晶シリコン層３０７と、多結晶シリコン層であるメモリポリ層３０３と、Ｎウェル３１４とが、各々絶縁層を介して積層されたＰＰＳ構造を有する点でも、本例示的実施形態に係る半導体装置１０と共通する。 FIG. 7 is a plan view showing an example of the configuration of a capacitive element 300, which is a conventionally commonly used PPS capacitive element. As shown in FIG. 7, the first contact 320 is provided on the first gate polycrystalline silicon layer 307, as in the semiconductor device 10 according to the exemplary embodiment described above. This exemplary embodiment also has a PPS structure in which the first gate polycrystalline silicon layer 307, the memory polysilicon layer 303, which is a polycrystalline silicon layer, and the N-well 314 are stacked with an insulating layer in between. This is common to the semiconductor device 10 according to the above.
　しかしながら、図７に示した容量素子３００は、大気圧プラズマエッチング、反応性イオンエッチング（ＲＩＥ）、不活性ガスによるプラズマエッチング、レーザー、イオンビーム等によるエッチングで第１ゲート多結晶シリコン層３０７及び第１ゲート酸化膜３１６を除去することによって生成された凹部３３０を介して第２コンタクト３２２がメモリポリ層３０３に接続され、Ｎウェル１１４の端部に第３コンタクト３２４が接続されている点で、本例示的実施形態に係る半導体装置１０とは相違する。 However, the capacitive element 300 shown in FIG. The second contact 322 is connected to the memory poly layer 303 through the recess 330 created by removing the first gate oxide film 316, and the third contact 324 is connected to the end of the N-well 114. This is different from the semiconductor device 10 according to the exemplary embodiment.
　図８の（１）は、図７のＥＥ線に沿った断面図である。図８の（１）に示したように、容量素子３００は、半導体基板の主面３１１上に形成されたＮウェル３１４の上層に絶縁膜であるＨＴＯトンネル３１８が設けられ、ＨＴＯトンネル３１８の上層には、メモリポリ層３０３が形成されている。さらに、メモリポリ層３０３の上層には絶縁層である第１ゲート酸化膜３１６を介して第１ゲート多結晶シリコン層３０７が形成されている。その結果、容量素子３００は、多結晶シリコン層と絶縁層とが積層されたＰＰＳ素子構造を有する。具体的には、第１ゲート多結晶シリコン層３０７はＰｏｌｙ－Ｓｉであり、第１ゲート酸化膜３１６はＩｎｓｕｌａｔｏｒであり、メモリポリ層３０３はＰｏｌｙ－Ｓｉであり、ＨＴＯトンネル３１８はＩｎｓｕｌａｔｏｒであり、Ｎウェル３１４はＳｉ－ｓｕｂｓｔｒａｔｅに各々該当する。 FIG. 8(1) is a cross-sectional view taken along line EE in FIG. 7. As shown in (1) of FIG. 8, the capacitive element 300 includes an HTO tunnel 318, which is an insulating film, provided in the upper layer of an N well 314 formed on the main surface 311 of the semiconductor substrate, and the HTO tunnel 318, which is an insulating film, A memory poly layer 303 is formed therein. Furthermore, a first gate polycrystalline silicon layer 307 is formed on the memory poly layer 303 with a first gate oxide film 316, which is an insulating layer, interposed therebetween. As a result, the capacitive element 300 has a PPS element structure in which a polycrystalline silicon layer and an insulating layer are stacked. Specifically, the first gate polycrystalline silicon layer 307 is Poly-Si, the first gate oxide film 316 is an insulator, the memory poly layer 303 is Poly-Si, the HTO tunnel 318 is an insulator, and the first gate oxide film 316 is an insulator. The wells 314 correspond to Si-substrate.
　第１コンタクト２２０に対応するＮウェル１１４及び半導体基板１１の部位には、絶縁層である素子分離絶縁膜３２６Ａが設けられている。また、第２コンタクト３２２及び凹部３３０に対応するＮウェル１１４及び半導体基板１１の各々の部位にも絶縁層である素子分離絶縁膜３２６Ｂが設けられている。 An element isolation insulating film 326A, which is an insulating layer, is provided at a portion of the N-well 114 and the semiconductor substrate 11 corresponding to the first contact 220. Further, an element isolation insulating film 326B, which is an insulating layer, is also provided at each portion of the N well 114 and the semiconductor substrate 11 corresponding to the second contact 322 and the recess 330.
　図８の（１）に示した構成では、凹部３３０を設けて第２コンタクト３２２を配設する際のドライエッチング等によって、メモリポリ層１０３又はＨＴＯトンネル３１８が損傷する等による容量素子３００の歩留まり悪化を抑制するために、素子分離絶縁膜３２６Ｂを十分な大きさで設ける必要がある。しかしながら、素子分離絶縁膜３２６Ｂを大きくすると、Ｎウェル３１４の領域が減殺され、容量素子としての性能が低下するおそれがある。 In the configuration shown in FIG. 8(1), the yield of the capacitive element 300 deteriorates due to damage to the memory poly layer 103 or the HTO tunnel 318 due to dry etching or the like when forming the recess 330 and arranging the second contact 322. In order to suppress this, it is necessary to provide the element isolation insulating film 326B with a sufficient size. However, if the element isolation insulating film 326B is enlarged, the area of the N well 314 is reduced, and there is a possibility that the performance as a capacitor element will be degraded.
　図８の（２）は、本例示的実施形態に係る半導体装置１０の容量素子部２００の断面図で、前述の図２と同一の図面である。本例示的実施形態に係る半導体装置１０は、第２コンタクト２２２を容量素子部２００から隔離したメモリポリ層１０３ａの上端部に設けることにより、図８の（１）にあるような凹部３３０及び第２コンタクト２２２を容量素子部２００に設けることを要しない。その結果、半導体装置１０の歩留まり悪化を抑制するための素子分離絶縁膜１２０Ｂを、図８の（１）に示した構成に比して縮小することができる。 FIG. 8(2) is a cross-sectional view of the capacitive element section 200 of the semiconductor device 10 according to the present exemplary embodiment, and is the same drawing as FIG. 2 described above. The semiconductor device 10 according to the present exemplary embodiment has a recess 330 and a second It is not necessary to provide the contact 222 in the capacitive element section 200. As a result, the element isolation insulating film 120B for suppressing deterioration in yield of the semiconductor device 10 can be reduced in size compared to the structure shown in FIG. 8(1).
　図８の（１）と（２）とを比較すると、本例示的実施形態に係る半導体装置１０の容量素子部２００は、（２）に示した容量素子３００に比して、ΔＤ分、素子分離絶縁膜１２０Ｂを縮小することにより、（１）に示した構成よりも、Ｎウェル１１４の領域を拡大できる。 Comparing (1) and (2) of FIG. 8, the capacitive element portion 200 of the semiconductor device 10 according to the present exemplary embodiment has a larger element size by ΔD than the capacitive element 300 shown in (2). By reducing the isolation insulating film 120B, the area of the N well 114 can be expanded more than in the configuration shown in (1).
　以上説明したように、本例示的実施形態に係る半導体装置１０は、ＰＰＳ容量素子の第２コンタクト２２２、及び第３コンタクト２２４の各々を、フラッシュメモリを構成する記憶素子部１００の一部の構造を延伸して生成した部位に配設することで、Ｎウェル１１４の領域を従来の容量素子よりも拡大することが可能で、寄生容量の増加、信頼性の低下、及び歩留まりの低下等を抑制できるという効果を奏する。 As described above, in the semiconductor device 10 according to the present exemplary embodiment, each of the second contact 222 and the third contact 224 of the PPS capacitive element is connected to the structure of a part of the storage element section 100 constituting a flash memory. By arranging the N-well 114 in a region created by stretching it, it is possible to expand the area of the N-well 114 compared to conventional capacitive elements, thereby suppressing increases in parasitic capacitance, decreases in reliability, and decreases in yield. It has the effect of being able to do it.
　また、本例示的実施形態に係る半導体装置１０は、容量素子部２００を、フラッシュメモリである記憶素子部１００のセルアレイに隣接して形成できるため、チップ面積の縮小が可能になるだけでなく、ＰＰＳ容量素子の一部の端子構造を記憶素子部１００と共用できることから、記憶素子部１００に印加する電圧の、寄生抵抗による電圧降下を抑制できるという効果も奏する。 Further, in the semiconductor device 10 according to the present exemplary embodiment, since the capacitive element section 200 can be formed adjacent to the cell array of the memory element section 100, which is a flash memory, it is possible not only to reduce the chip area, but also to reduce the chip area. Since a part of the terminal structure of the PPS capacitive element can be shared with the memory element section 100, there is also an effect that voltage drop due to parasitic resistance in the voltage applied to the memory element section 100 can be suppressed.
　上記した本開示の例示的実施形態に係る半導体装置は一例にすぎず、本開示の趣旨を逸脱しない限りにおいて、構成の省略、追加、改変、使用する材料の変更等を行うことが可能である。 The semiconductor device according to the exemplary embodiment of the present disclosure described above is only an example, and it is possible to omit, add, or modify the configuration, change the materials used, etc. without departing from the spirit of the present disclosure. .
　なお、「第１シリコン層」は「第１ゲート多結晶シリコン層１０７」に、「第１の絶縁膜」は同「第１ゲート酸化膜１１６」に、「第２シリコン層」は「メモリポリ層１０３」に、「第２の絶縁膜」は「ＨＴＯトンネル１１８」に、「第３の絶縁膜」は「ゲート絶縁膜１０９ａ、１０９ｂ」に、「第４の絶縁膜」は「トンネル絶縁膜１１０ａ、１１０ｂ」に、「拡散層」は「ソース１０５」に、「導電部材」は「ソース配線１０１」に、「第１接点」は「第１コンタクト２２０」に、「第２接点」は「第２コンタクト２２２」に、「第３接点」は「第３コンタクト２２４」に、各々該当する。 Note that the "first silicon layer" is the "first gate polycrystalline silicon layer 107," the "first insulating film" is the "first gate oxide film 116," and the "second silicon layer" is the "memory polycrystalline silicon layer 107." 103", the "second insulating film" is connected to the "HTO tunnel 118", the "third insulating film" is connected to the "gate insulating films 109a, 109b", and the "fourth insulating film" is connected to the "tunnel insulating film 110a". , 110b", the "diffusion layer" is connected to the "source 105", the "conductive member" is connected to the "source wiring 101", the "first contact" is connected to the "first contact 220", and the "second contact" is connected to the "second contact". 2 contact 222", and the "third contact" corresponds to "third contact 224", respectively.
　２０２２年３月２２日出願の日本国特許出願２０２２－０４６０２５号の開示は、その全体が参照により本明細書に取り込まれる。 The disclosure of Japanese Patent Application No. 2022-046025 filed on March 22, 2022 is incorporated herein by reference in its entirety.
　本明細書に記載された全ての文献、特許出願、および技術規格は、個々の文献、特許出願、および技術規格が参照により取り込まれることが具体的かつ個々に記された場合と同程度に、本明細書中に参照により取り込まれる。 All documents, patent applications, and technical standards mentioned herein are incorporated by reference to the same extent as if each individual document, patent application, and technical standard was specifically and individually indicated to be incorporated by reference. Incorporated herein by reference.

Claims (8)

  1. 　電圧が印加される第１接点が設けられた第１シリコン層と、
    　前記第１シリコン層の直下に形成された第１の絶縁膜と、
    　前記第１の絶縁膜の直下に形成された第２シリコン層と、
    　前記第２シリコン層の直下に形成された第２の絶縁膜と、
    　前記第２の絶縁膜と半導体基板との間に形成されたＮウェルと、
    　を含む容量素子を備え、
    　前記半導体基板の主面上に第３の絶縁膜を介して前記主面と略平行に設けられたフローティングゲートと、
    　前記フローティングゲート上に設けられたスペーサと、
    　前記フローティングゲートと前記スペーサとの間に設けられ、且つ前記スペーサの一端側の側面、前記フローティングゲートの前記一端側の側面、及び前記半導体基板の前記主面の各々を覆う第４の絶縁膜と、
    　前記第２シリコン層が延伸されて形成され、前記半導体基板の前記主面、前記フローティングゲートの前記一端側の側面、及び前記スペーサの前記一端側の側面の各々に、前記第４の絶縁膜を介して接し、第２接点を備えたコントロールゲートと、
    　前記第１シリコン層が延伸されて形成され、前記第１接点と導通するコンタクト部と、
    　前記半導体基板の表層部に設けられた拡散層と、
    　一端が前記拡散層に接続され、且つ前記フローティングゲート及び前記スペーサの他端側の側面に、第５の絶縁膜を介して接し、他端に第３接点を有する導電部材と、
    　を含む記憶素子と、
    　を備えた半導体装置。     a first silicon layer provided with a first contact to which a voltage is applied;
    a first insulating film formed directly under the first silicon layer;
    a second silicon layer formed directly under the first insulating film;
    a second insulating film formed directly under the second silicon layer;
    an N-well formed between the second insulating film and the semiconductor substrate;
    Equipped with a capacitive element including
    a floating gate provided substantially parallel to the main surface of the semiconductor substrate with a third insulating film interposed therebetween;
    a spacer provided on the floating gate;
    a fourth insulating film provided between the floating gate and the spacer and covering each of the side surface on one end side of the spacer, the side surface on the one end side of the floating gate, and the main surface of the semiconductor substrate; ,
    The second silicon layer is stretched and formed, and the fourth insulating film is formed on each of the main surface of the semiconductor substrate, the side surface on the one end side of the floating gate, and the side surface on the one end side of the spacer. a control gate connected through the gate and having a second contact;
    a contact portion formed by stretching the first silicon layer and electrically connected to the first contact point;
    a diffusion layer provided on the surface layer of the semiconductor substrate;
    a conductive member whose one end is connected to the diffusion layer and which is in contact with the other end side of the floating gate and the spacer via a fifth insulating film, and has a third contact at the other end;
    a memory element including;
    A semiconductor device equipped with
  2. 　前記フローティングゲート、前記拡散層、及び前記導電部材の一端の各々は、前記容量素子に隣接して設けられ、
    　前記第２接点、及び前記第３接点は、前記容量素子から離されて設けられた、
    　請求項１に記載の半導体装置。     Each of the floating gate, the diffusion layer, and one end of the conductive member is provided adjacent to the capacitor,
    The second contact and the third contact are provided apart from the capacitive element.
    The semiconductor device according to claim 1.
  3. 　前記容量素子は、
    　前記半導体基板、及び前記Ｎウェルの各々において、前記第１接点に対応する部位と、前記第１シリコン層の端部に対応する部位とに素子分離絶縁膜が各々設けられた、
    　請求項１に記載の半導体装置。     The capacitive element is
    In each of the semiconductor substrate and the N-well, an element isolation insulating film is provided at a portion corresponding to the first contact point and a portion corresponding to an end portion of the first silicon layer, respectively.
    The semiconductor device according to claim 1.
  4. 　前記容量素子は、
    　前記半導体基板、及び前記Ｎウェルの各々において、前記第１接点に対応する部位と、前記第１シリコン層の端部に対応する部位とに素子分離絶縁膜が各々設けられた、
    　請求項２に記載の半導体装置。     The capacitive element is
    In each of the semiconductor substrate and the N-well, an element isolation insulating film is provided at a portion corresponding to the first contact point and a portion corresponding to an end portion of the first silicon layer, respectively.
    The semiconductor device according to claim 2.
  5. 　前記フローティングゲートは、一端側に先端が尖った尖鋭部を有し、
    　前記尖鋭部の先端部分が前記第４の絶縁膜を介して前記コントロールゲートと接している、
    　請求項１に記載の半導体装置。     The floating gate has a sharp tip at one end,
    a tip portion of the sharp portion is in contact with the control gate via the fourth insulating film;
    The semiconductor device according to claim 1.
  6. 　前記フローティングゲートは、一端側に先端が尖った尖鋭部を有し、
    　前記尖鋭部の先端部分が前記第４の絶縁膜を介して前記コントロールゲートと接している、
    　請求項２に記載の半導体装置。     The floating gate has a sharp tip at one end,
    a tip portion of the sharp portion is in contact with the control gate via the fourth insulating film;
    The semiconductor device according to claim 2.
  7. 　前記フローティングゲートは、一端側に先端が尖った尖鋭部を有し、
    　前記尖鋭部の先端部分が前記第４の絶縁膜を介して前記コントロールゲートと接している、
    　請求項３に記載の半導体装置。     The floating gate has a sharp tip at one end,
    a tip portion of the sharp portion is in contact with the control gate via the fourth insulating film;
    The semiconductor device according to claim 3.
  8. 　前記フローティングゲートは、一端側に先端が尖った尖鋭部を有し、
    　前記尖鋭部の先端部分が前記第４の絶縁膜を介して前記コントロールゲートと接している、
    　請求項４に記載の半導体装置。     The floating gate has a sharp tip at one end,
    a tip portion of the sharp portion is in contact with the control gate via the fourth insulating film;
    The semiconductor device according to claim 4.
PCT/JP2023/011297 2022-03-22 2023-03-22 Semiconductor device WO2023182376A1 (en)

Applications Claiming Priority (2)

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JP2022-046025 2022-03-22

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006024604A (en) * 2004-07-06 2006-01-26 Sanyo Electric Co Ltd Method of manufacturing semiconductor device
JP2008041832A (en) * 2006-08-03 2008-02-21 Renesas Technology Corp Semiconductor device and its manufacturing method
JP2011103332A (en) * 2009-11-10 2011-05-26 Renesas Electronics Corp Semiconductor device and method of manufacturing the same
JP2014078661A (en) * 2012-10-12 2014-05-01 Renesas Electronics Corp Semiconductor device and manufacturing method of the same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006024604A (en) * 2004-07-06 2006-01-26 Sanyo Electric Co Ltd Method of manufacturing semiconductor device
JP2008041832A (en) * 2006-08-03 2008-02-21 Renesas Technology Corp Semiconductor device and its manufacturing method
JP2011103332A (en) * 2009-11-10 2011-05-26 Renesas Electronics Corp Semiconductor device and method of manufacturing the same
JP2014078661A (en) * 2012-10-12 2014-05-01 Renesas Electronics Corp Semiconductor device and manufacturing method of the same

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