WO2023179654A1 - 校准控制方法、装置及电子设备 - Google Patents

校准控制方法、装置及电子设备 Download PDF

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Publication number
WO2023179654A1
WO2023179654A1 PCT/CN2023/083051 CN2023083051W WO2023179654A1 WO 2023179654 A1 WO2023179654 A1 WO 2023179654A1 CN 2023083051 W CN2023083051 W CN 2023083051W WO 2023179654 A1 WO2023179654 A1 WO 2023179654A1
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WIPO (PCT)
Prior art keywords
calibration
communication
timing deviation
time period
trigger
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PCT/CN2023/083051
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English (en)
French (fr)
Inventor
谢梓敏
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维沃移动通信有限公司
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Publication of WO2023179654A1 publication Critical patent/WO2023179654A1/zh

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors

Definitions

  • the present application relates to the field of communication technology, and in particular to a calibration control method, device and electronic equipment.
  • MIPI D-PHY is a physical layer serial high-speed interface protocol defined by the MIPI Association, which provides support for display serial interface (DSI) and camera serial Interface (Camera serial interface, CSI) protocol layer support. Between the protocol layer and the physical layer, the MIPI protocol defines a standard physical layer protocol interface (PHY Protocol Interface, PPI) interface. The application layer, protocol layer and physical layer cooperate with each other to complete related control and data transmission.
  • MIPI Mobile Industry Processor Interface
  • PPI physical layer protocol interface
  • D-PHY uses a set of clock channels and no less than one set of data channels. Each data channel can support low-speed communication below 10Mbps and high-speed communication above 80Mbps.
  • the timing deviation calibration communication between the clock channel and the data channel is scheduled by the application layer, which requires the application layer to obtain the communication status of the protocol layer and physical layer in real time, and the scheduling efficiency is low.
  • Embodiments of the present application provide a calibration control method, device and electronic equipment, which can solve the problem in related technologies that timing deviation calibration communications are scheduled by the application layer and the scheduling efficiency is low.
  • embodiments of the present application provide a calibration control method, which is applied to the protocol layer transmitter.
  • the method includes:
  • the timing deviation calibration communication is used to Timing deviation calibration between clock channels and data channels in the physical layer.
  • inventions of the present application provide a calibration control device.
  • the protocol layer sending end includes the calibration control device.
  • the device includes:
  • Acquisition module used to obtain calibration configuration
  • a triggering module configured to trigger timing deviation calibration communication according to the calibration configuration.
  • the timing deviation calibration communication is used for timing deviation calibration between a clock channel and a data channel in the physical layer.
  • inventions of the present application provide an electronic device.
  • the electronic device includes a processor, a memory, and a program or instructions stored on the memory and executable on the processor.
  • the program or instructions are When executed by the processor, the steps in the calibration control method described in the first aspect are implemented.
  • embodiments of the present application provide a readable storage medium.
  • Programs or instructions are stored on the readable storage medium.
  • the calibration control method as described in the first aspect is implemented. steps in.
  • inventions of the present application provide a chip.
  • the chip includes a processor and a communication interface.
  • the communication interface is coupled to the processor.
  • the processor is used to run programs or instructions to implement the first aspect. the method described.
  • embodiments of the present application provide a computer program/program product, the computer program/program product is stored in a storage medium, and the computer program/program product is executed by at least one processor to implement the first methods described in this aspect.
  • the protocol layer sending end obtains the calibration configuration; triggers timing deviation calibration communication based on the calibration configuration, and the timing deviation calibration communication is used for timing deviation calibration between the clock channel and the data channel in the physical layer. In this way, the timing deviation calibration communication between the clock channel and the data channel is scheduled through the protocol layer sending end.
  • the application layer does not need to obtain the communication status of the protocol layer and the physical layer in real time, which can improve the efficiency of scheduling.
  • Figure 1 is a flow chart of a calibration control method provided by an embodiment of the present application.
  • Figure 2 is one of the flow diagrams of a calibration control method provided by an embodiment of the present application.
  • Figure 3 is the second schematic flow chart of a calibration control method provided by an embodiment of the present application.
  • Figure 4 is the third schematic flowchart of a calibration control method provided by an embodiment of the present application.
  • Figure 5 is a communication schematic diagram of an image frame provided by an embodiment of the present application.
  • Figure 6 is a structural diagram of a calibration control device provided by an embodiment of the present application.
  • Figure 7 is one of the structural diagrams of an electronic device provided by an embodiment of the present application.
  • FIG. 8 is the second structural diagram of an electronic device provided by an embodiment of the present application.
  • Figure 1 is a flow chart of a calibration control method provided by an embodiment of the present application. It is applied to the protocol layer transmitter. As shown in Figure 1, it includes the following steps:
  • Step 101 Obtain calibration configuration.
  • the protocol layer sending end can obtain the calibration configuration from the application layer, for example, the calibration configuration can be obtained from the central processor.
  • the protocol layer sending end is a DSI protocol layer sending end, for example, a DSI host (Host); or the protocol layer sending end is a CSI-2 protocol layer sending end, for example, a CSI-2 device (Device).
  • Step 102 Trigger timing deviation calibration communication according to the calibration configuration.
  • the timing deviation calibration communication is used for timing deviation calibration between the clock channel and the data channel in the physical layer.
  • the protocol layer sending end when the protocol layer sending end triggers the timing deviation calibration communication, it sends a timing deviation calibration signal to the physical layer sending end, and the physical layer sending end sends a timing deviation calibration sequence to the physical layer receiving end based on the timing deviation calibration signal.
  • the timing deviation calibration signal is triggered by the protocol layer sending end pulling up the TxSkewCalHS signal through the PPI interface.
  • PPI is a common interface specification between the D-PHY or C-PHY physical layer and the CSI-2 or DSI/DSI2 protocol layer specified by the MIPI protocol.
  • the physical layer transmitter sends a set of repeated 1010 sequences (normal mode) or PRBS9 sequences (alternative mode) specified in advance by both parties.
  • the physical layer receiver adjusts the phase relationship between the clock and the data channel to obtain the ideal Data sampling window to achieve timing deviation calibration.
  • the D-PHY protocol requires timing deviation calibration communication between the clock and the data channel before the first high-speed communication, that is, skew calibration communication.
  • the timing deviation calibration of D-PHY is sent by the TX transmitter to the RX receiver, and the timing deviation calibration sequence is also implemented by D-PHY TX.
  • the timing deviation calibration of D-PHY includes: the PPI interface between the DSI host or CSI-2 device and the physical layer transmitter D-PHY TX pulls up the TxSkewCalHS signal to trigger timing deviation calibration communication; D-PHY TX sends the timing deviation calibration sequence to the management layer receiving end D-PHY RX; D-PHY RX adjusts the phase relationship between the clock and the data channel according to the timing deviation calibration sequence; when D-PHY RX receives the timing deviation calibration sequence, D-PHY The PPI interface between RX and the DSI device or CSI-2 host pulls up the RxSkewCalHS signal.
  • D-PHY is one of the MIPI protocols and is a physical layer specification for high-speed, low-power scalable serial interconnection.
  • D-PHY provides the definition of DSI and CSI-2 at the physical layer.
  • D-PHY uses a pair of source-synchronous two-wire point-to-point clocks and one or more pairs of two-wire point-to-point data lines for data transmission. Each pair of data lines can work in a single-ended low-speed mode of not higher than 10Mbps, or not Differential high-speed mode at 80Mbps.
  • CSI-2 is one of the MIPI protocols. It is a protocol layer interface specification for cameras. It can be used in conjunction with the D-PHY or C-PHY protocol of the physical layer to complete the camera communication solution.
  • the transmitter is CSI- 2 Device
  • the receiving end is CSI-2 Host.
  • DSI is one of the MIPI protocols. It is a protocol layer interface specification for displays. It can cooperate with the D-PHY of the physical layer to complete the camera communication solution.
  • the sending end is DSI Host and the receiving end is DSI Device.
  • Timing deviation calibration if the initiation of the PPI signal TxSkewCalHS for control is also scheduled by the application layer, especially when periodic calibration is selected When the time comes, the application layer needs to grasp the working status of the protocol layer and is limited by the communication status between the protocol layer and the physical layer. This correspondingly increases the cost of software application layer scheduling and reduces the overall control efficiency.
  • timing deviation calibration communication is triggered by the protocol layer sending end, which can reduce the cost of software application layer scheduling and improve the efficiency of calibration control.
  • a mechanism for adaptive management of D-PHY timing deviation calibration communication can be implemented in the CSI-2 Device and DSI Host protocol layer control modules, thereby reducing software application layer scheduling overhead and improving system efficiency.
  • the adaptive control logic that initiates D-PHY Skew Calibration timing deviation calibration communication can be configured. After the initial settings are made at the software application layer, the adaptive logic can be configured based on the configurable setting options and the real-time data communication between the protocol layer and the physical layer when the data channel is idle or at the beginning or end of each frame of image transmitted by the data channel.
  • TxSkewCalHS is automatically raised to trigger the physical layer transmitter to initiate timing deviation calibration communication, thereby achieving periodic calibration communication without application layer scheduling.
  • the protocol layer sender triggers the timing deviation calibration communication and initiates the adaptive control logic in the protocol layer. It executes independently according to the calibration configuration of the application layer and can grasp the adaptive adjustment of the protocol layer's own status in real time. The application layer only needs to Just configure it at startup.
  • the protocol layer sending end can be a DSI host or a CSI-2 device.
  • the protocol layer sending end is a DSI Host
  • the protocol layer sending end is connected to the D-PHY of the physical layer sending end.
  • the protocol layer sending end is a CSI-2 Device
  • the protocol layer sending end is connected to the D-PHY of the physical layer sending end.
  • CSI-2 Device is the protocol layer sender for the camera solution
  • DSI Host is the protocol layer sender for the display solution. They are both connected to the D-PHY TX of the physical layer sender.
  • the CSI-2 Device is taken as an example for explanation.
  • the adaptive control logic of the DSI Host and the CSI-2 Device for timing deviation calibration communication is similar.
  • the implementation of the adaptive control logic of timing deviation calibration communication can be as follows: after the electronic device is started, the software application layer of the electronic device initializes the configuration of relevant modules including the CSI-2 Device, which includes the added adaptive Configuration of control logic.
  • the CSI-2 Device communicates accordingly according to the calibration configuration of the software application layer.
  • the adaptive control logic performs communication according to the calibration configuration of the software application layer, when the conditions for the calibration configuration are met and there is sufficient idle time between it and the D-PHY TX module. During communication, pull up the TxSkewCalHS signal to trigger timing deviation calibration communication.
  • the trigger condition judgment logic is used to judge whether the conditions for triggering timing deviation calibration communication are met based on the calibration configuration and the module status combined with other modules except the adaptive control logic.
  • the module status can Including the communication status between CSI-2 Device and D-PHY TX; the initiation logic is used to trigger timing deviation calibration communication when the trigger conditions are met; the control and status register is used to receive the calibration configuration of the application layer and save the execution status of the calibration configuration.
  • the software application layer is allowed to no longer need to perform periodic scheduling after startup configuration, thereby reducing scheduling overhead and mitigating Application layer burden.
  • CSI-2 Device and DSI Host can grasp their own internal communication status in real time when controlling timing deviation calibration communication, thus reducing the delay introduced through application layer scheduling.
  • CSI-2 Device when CSI-2 Device triggers timing deviation calibration communication, it can provide status information to the application layer. For example, it can be provided through a status register or signal. The application layer can obtain the relevant status of timing deviation calibration communication through the status information. When performing timing deviation calibration communication, the application layer can wait for the timing deviation calibration communication to be completed before starting the next communication with the CSI-2 Device.
  • the protocol layer sending end obtains the calibration configuration; triggers timing deviation calibration communication based on the calibration configuration, and the timing deviation calibration communication is used for timing deviation calibration between the clock channel and the data channel in the physical layer. In this way, the timing deviation calibration communication between the clock channel and the data channel is scheduled through the protocol layer sending end.
  • the application layer does not need to obtain the communication status of the protocol layer and the physical layer in real time, which can improve the efficiency of scheduling.
  • the calibration configuration includes at least one of a calibration mode, a calibration sequence length, a trigger period interval, a trigger allowed time period, and a calibration communication rate.
  • the calibration mode may be a timing deviation calibration mode.
  • the calibration mode may include at least one of initial calibration and periodic calibration.
  • the initial calibration may be to perform timing offset calibration only when the communication rate is first detected to be greater than a preset threshold.
  • Periodic calibration can be performed periodically to calibrate timing deviations.
  • the calibration sequence length may be the length of the timing offset calibration sequence.
  • the trigger period interval can be the time interval for triggering timing deviation calibration communication.
  • the trigger period interval can be triggered by the target number of frames, or it can be triggered by the target number of clock cycles, or it can be triggered by the target duration. Trigger, this embodiment does not limit this.
  • the target number of frames, the target number of clock cycles, and the target duration may be preset in the software program, or may be configured by the user.
  • timing deviation calibration communication can be triggered every 1 second.
  • the triggering allowed time period may be a time period in which timing deviation calibration communication is allowed to be triggered, and the triggering allowed time period may include at least one of a communication idle time period and an inter-frame idle time period.
  • the calibration communication rate is the communication rate at which periodic calibration is performed. For example, when the calibration mode is periodic calibration and the communication rate of the data channel is detected to be greater than the calibration communication rate, the calibration sequence length, trigger cycle interval and trigger allowed time period can be Trigger timing skew calibration communication.
  • the calibration configuration may include any one of the calibration mode, calibration sequence length, trigger cycle interval, trigger allowed time period and calibration communication rate.
  • the calibration configuration may include the calibration mode, and the protocol layer sending end may process it from the central The device obtains the calibration mode.
  • the protocol layer sender can trigger the timing deviation calibration communication according to the calibration mode obtained from the central processor and the default configured calibration communication rate, calibration sequence length, trigger cycle interval and trigger allowed time period; or, calibration
  • the configuration can include any two of the calibration mode, calibration sequence length, trigger cycle interval, trigger allowed time period, and calibration communication rate.
  • the calibration configuration can include the trigger cycle interval and the trigger allowed time period.
  • the protocol layer transmitter can Obtain the trigger period interval and trigger allowed time period from the central processor.
  • the protocol layer sender can obtain the trigger period interval and trigger allowed time period from the central processor, as well as the default configured calibration communication rate, calibration mode and calibration sequence length. Trigger timing deviation calibration communication; alternatively, the calibration configuration may include any three of the calibration mode, calibration sequence length, trigger cycle interval, trigger allowed time period and calibration communication rate. For example, the calibration configuration may include the calibration mode, trigger cycle interval and trigger allowed time period.
  • the protocol layer sender can obtain the calibration mode, trigger cycle interval and trigger allowed time period from the central processor.
  • the protocol layer sender can obtain the calibration mode, trigger cycle interval and trigger time period from the central processor. Allow time period, and default configured calibration sequence length and calibration communication rate to trigger timing deviation calibration communication.
  • the user can choose to configure the following options on the software interface: only support initial calibration, or enable optional period calibration; calibration sequence length; trigger period interval; trigger allowed time period.
  • the calibration configuration includes at least one of calibration mode, calibration sequence length, trigger cycle interval, trigger allowed time period and calibration communication rate, so that the protocol layer sending end can The timing deviation calibration communication is triggered based on at least one of the calibration mode, the calibration sequence length, the trigger cycle interval, and the trigger allowed time period.
  • the calibration configuration includes the calibration mode and calibration sequence length
  • the calibration mode is initial calibration
  • triggering timing deviation calibration communication based on the calibration configuration includes:
  • timing deviation calibration communication is triggered based on the calibration sequence length.
  • the initial calibration may be performed only when the communication rate is detected for the first time to be greater than a preset threshold.
  • the preset threshold is a higher communication rate, and the preset threshold can be set in advance.
  • the preset threshold is 1.5Gbps in accordance with the provisions of the communication protocol.
  • triggering the timing deviation calibration communication based on the calibration sequence length may trigger the timing deviation calibration signal, so that the physical layer sending end sends the timing deviation calibration sequence to the physical layer receiving end according to the calibration sequence length.
  • timing deviation calibration communication is triggered based on the length of the calibration sequence. In this way, Ability to trigger timing deviation calibration communications based on the calibration configuration of the initial calibration.
  • the calibration configuration includes the calibration mode and calibration sequence length, trigger cycle interval and trigger allowed time period, the calibration mode is periodic calibration, and triggering timing deviation calibration communication based on the calibration configuration includes:
  • timing deviation calibration communication is triggered according to the calibration sequence length and the trigger allowed time period.
  • the timing deviation calibration communication can be triggered according to the calibration sequence length and the trigger allowed time period.
  • Periodic calibration may be performed periodically, for example, it may be performed every 1 second.
  • the current time meeting the trigger period interval may be that the difference between the current time and the last time the timing deviation calibration communication is triggered reaches the trigger period interval.
  • the trigger cycle interval is 1 second, and the difference between the current time and the last time the timing deviation calibration communication was triggered is 1 second. It can be considered that the current time meets the trigger cycle interval.
  • the timing deviation calibration communication can be triggered when the trigger cycle interval and the trigger allowed time period are met, and the processing time required for the timing deviation calibration sequence is not greater than the allowed idle period.
  • the CSI-2 Device waits accordingly and synchronously updates the relevant control logic. While waiting, After the communication between CSI-2 Device and D-PHY TX is completed, trigger timing deviation calibration communication is performed.
  • the timing deviation calibration communication is triggered based on the calibration sequence length and the trigger allowed time period. In this way, it is possible to Calibration configuration based on periodic calibration triggers timing deviation calibration communication.
  • the calibration configuration also includes a calibration communication rate, and triggering timing deviation calibration communication based on the calibration sequence length and the triggering allowed time period includes:
  • timing deviation calibration communication is triggered based on the calibration sequence length and the triggering allowed time period.
  • the calibration mode is periodic calibration
  • the calibration sequence length and the The trigger allows the time period to trigger timing deviation calibration communications.
  • the calibration communication rate can be configured as 1.5Gbps, or 2Gbps, or 2.5Gbps, etc., which is not limited in this embodiment.
  • the communication rate for periodic calibration execution can be determined.
  • triggering timing deviation calibration communication based on the calibration sequence length and the triggering allowed time period includes at least one of the following:
  • the first target time period if the calibration sequence length is less than the frame interval length, timing deviation calibration communication is triggered, and the first target time period is the intersection of the communication effective time period and the frame idle time period;
  • the timing deviation calibration communication is triggered when the communication between the protocol layer sending end and the physical layer sending end ends, and the second target time period is when the communication is valid. The intersection of the interval and the frame valid time period.
  • the communication idle time period can be when there is no frame transmission communication between the protocol layer sending end and the physical layer sending end
  • the communication effective time period can be when there is frame transmission communication between the protocol layer sending end and the physical layer sending end
  • the segment may be the frame blank time between two frames in frame transmission communication
  • the frame valid period may be the line blank time in one frame in frame transmission communication.
  • triggering the timing deviation calibration communication based on the calibration sequence length and the triggering allowed time period may include at least one of the following: when the current moment is in the communication idle period, triggering the timing according to the calibration sequence length. Deviation calibration communication; when the current moment is in the communication valid time period and the frame idle time period, if the calibration sequence length is less than the frame interval length, timing deviation calibration communication is triggered; when the current moment is in the communication valid time period and In the case of the frame valid period, the timing deviation calibration communication is triggered when the communication between the protocol layer sending end and the physical layer sending end ends.
  • FS refers to Frame start
  • FE refers to Frame End
  • PF refers to packet footer+filler
  • ED refers to the packet header containing embedded data type code ( packet header containing embedded data type code)
  • D1 refers to the data packet header containing data type 1 image data code (packet header containing data type1 image data code)
  • D2 refers to the data packet header containing data type 2 image data code (packet header containing data type2 image data code).
  • triggering timing deviation calibration communication based on the calibration sequence length and the triggering allowed time period includes at least one of the following: triggering timing deviation calibration communication according to the calibration sequence length during the communication idle period; Within the first target time period, if the calibration sequence length is less than the frame interval length, timing deviation calibration communication is triggered, and the first target time period is the intersection of the communication effective time period and the frame idle time period; in the second target time Within this period, the timing deviation calibration communication is triggered when the communication between the protocol layer sending end and the physical layer sending end ends, and the second target time period is the intersection of the communication valid time period and the frame valid time period. thereby being able to pass Calibration configuration flexibly sets the conditions for triggering timing deviation calibration communications.
  • the protocol layer sending end is a display serial interface DSI protocol layer sending end or a camera serial interface CSI-2 protocol layer sending end;
  • the protocol layer sending end when the protocol layer sending end is DSI Host, the protocol layer sending end is connected to the D-PHY of the physical layer sending end, so that the display solution can be realized; when the protocol layer sending end is CSI-2 In the case of Device, the protocol layer transmitter is connected to the D-PHY of the physical layer transmitter, thereby enabling a camera solution.
  • the protocol layer sending end is communicatively connected to the central processor, and obtaining the calibration configuration includes:
  • the calibration configuration is obtained from the central processor, so the application layer only needs to deliver the calibration configuration to the protocol layer, and the application layer does not need to obtain the communication status of the protocol layer and the physical layer in real time.
  • triggering timing deviation calibration communication based on the calibration configuration includes:
  • the timing deviation calibration signal is triggered according to the calibration configuration, so that the physical layer sending end sends a timing deviation calibration sequence to the physical layer receiving end according to the timing deviation calibration signal.
  • the timing deviation calibration signal can be the TxSkewCalHS signal
  • the protocol layer transmitter is a DSI host or CSI-2 device
  • the physical layer transmitter is D-PHY TX
  • the physical layer receiver is D-PHY RX
  • the PPI interface between the device and D-PHY TX pulls up the TxSkewCalHS signal to trigger timing deviation calibration communication.
  • D-PHY TX sends a timing deviation calibration sequence to D-PHY RX;
  • D-PHY RX adjusts the clock and data according to the timing deviation calibration sequence.
  • the phase relationship of the channels enables timing deviation calibration.
  • the execution subject may be a calibration control device.
  • the method of performing calibration control by the calibration control device is taken as an example to illustrate the calibration control device provided by the embodiment of the present application.
  • FIG 6 is a schematic structural diagram of a calibration control device provided by an embodiment of the present application.
  • the protocol layer sending end includes the calibration control device.
  • the calibration control device 200 includes:
  • Acquisition module 201 used to obtain calibration configuration
  • the trigger module 202 is configured to trigger timing deviation calibration communication according to the calibration configuration.
  • the timing deviation calibration communication is used for timing deviation calibration between the clock channel and the data channel in the physical layer.
  • the calibration configuration includes at least one of a calibration mode, a calibration sequence length, a trigger period interval, a trigger allowed time period, and a calibration communication rate.
  • the calibration configuration includes the calibration mode and the calibration sequence length
  • the calibration mode is initial calibration
  • the trigger module 202 is specifically used to:
  • timing deviation calibration communication is triggered based on the calibration sequence length.
  • the calibration configuration includes the calibration mode, calibration sequence length, trigger cycle interval and trigger allowed time period, the calibration mode is periodic calibration, and the trigger module 202 is specifically used to:
  • timing deviation calibration communication is triggered according to the calibration sequence length and the trigger allowed time period.
  • the calibration configuration also includes the calibration communication rate, and the trigger module 202 is specifically used to:
  • timing deviation calibration communication is triggered according to the calibration sequence length and the trigger allowed time period.
  • the calibration mode is periodic calibration, and when the trigger period interval is met, the trigger module 202 is specifically used for at least one of the following:
  • the first target time period if the calibration sequence length is less than the frame interval length, timing deviation calibration communication is triggered, and the first target time period is the intersection of the communication effective time period and the frame idle time period;
  • timing deviation calibration communication is triggered when the communication between the protocol layer sending end and the physical layer sending end ends, and the second target time period is the communication effective time period and the frame effective time period. intersection of time periods.
  • the protocol layer sending end is a display serial interface DSI protocol layer sending end or a camera serial interface CSI-2 protocol layer sending end;
  • the protocol layer sending end is communicatively connected to the central processor, and the acquisition module 201 is specifically used to:
  • the trigger module 202 is specifically used to:
  • the timing deviation calibration signal is triggered according to the calibration configuration, so that the physical layer sending end sends a timing deviation calibration sequence to the physical layer receiving end according to the timing deviation calibration signal.
  • the acquisition module 201 obtains the calibration configuration; the triggering module 202 triggers timing deviation calibration communication based on the calibration configuration.
  • the timing deviation calibration communication is used for timing deviation calibration between the clock channel and the data channel in the physical layer. In this way, the timing deviation calibration communication between the clock channel and the data channel is scheduled through the protocol layer sending end.
  • the application layer does not need to obtain the communication status of the protocol layer and the physical layer in real time, which can improve the efficiency of scheduling.
  • the calibration control device in the embodiment of the present application may be an electronic device or a component in the electronic device, such as an integrated circuit or chip.
  • the electronic device may be a terminal or other devices other than the terminal.
  • the electronic device can be a mobile phone, a tablet computer, a notebook computer, a handheld computer, a vehicle-mounted electronic device, a mobile internet device (Mobile Internet Device, MID), or augmented reality (AR)/virtual reality (VR).
  • the calibration control device in the embodiment of the present application may be a device with an operating system.
  • the operating system can be an Android operating system, an ios operating system, or other possible operating systems, which are not specifically limited in the embodiments of this application.
  • the calibration control device provided by the embodiments of the present application can implement each process implemented by the above method embodiments. To avoid repetition, details will not be described here.
  • this embodiment of the present application also provides an electronic device 300, including a processor Processor 301 and memory 302.
  • the memory 302 stores programs or instructions that can be run on the processor 301.
  • each step of the above calibration control method embodiment is implemented, and can achieve The same technical effects are not repeated here to avoid repetition.
  • the electronic devices in the embodiments of the present application include the above-mentioned mobile electronic devices and non-mobile electronic devices.
  • FIG. 8 is a schematic diagram of the hardware structure of an electronic device implementing an embodiment of the present application.
  • the electronic device 400 includes but is not limited to: radio frequency unit 401, network module 402, audio output unit 403, input unit 404, sensor 405, display unit 406, user input unit 407, interface unit 408, memory 409, processor 410, etc. part.
  • the electronic device 400 may also include a power supply (such as a battery) that supplies power to various components.
  • the power supply may be logically connected to the processor 410 through a power management system, thereby managing charging, discharging, and function through the power management system. Consumption management and other functions.
  • the structure of the electronic device shown in Figure 8 does not constitute a limitation on the electronic device.
  • the electronic device may include more or less components than shown in the figure, or combine certain components, or arrange different components, which will not be described again here. .
  • the electronic device 400 also includes a protocol layer sending end, and the protocol layer sending end is used for:
  • Timing deviation calibration communication is triggered according to the calibration configuration, and the timing deviation calibration communication is used for timing deviation calibration between the clock channel and the data channel in the physical layer.
  • the calibration configuration includes at least one of a calibration mode, a calibration sequence length, a trigger period interval, a trigger allowed time period, and a calibration communication rate.
  • the calibration configuration includes the calibration mode and the calibration sequence length, the calibration mode is initial calibration, and the protocol layer sending end is used to:
  • timing deviation calibration communication is triggered based on the calibration sequence length.
  • the calibration configuration includes the calibration mode, calibration sequence length, trigger cycle interval and trigger allowed time period, the calibration mode is periodic calibration, and the protocol layer sending end is used to:
  • timing deviation calibration communication is triggered according to the calibration sequence length and the trigger allowed time period.
  • the calibration configuration also includes the calibration communication rate.
  • the protocol layer sending end is used to:
  • timing deviation calibration communication is triggered according to the calibration sequence length and the trigger allowed time period.
  • the protocol layer sending end is used for at least one of the following:
  • the first target time period if the calibration sequence length is less than the frame interval length, timing deviation calibration communication is triggered, and the first target time period is the intersection of the communication effective time period and the frame idle time period;
  • timing deviation calibration communication is triggered when the communication between the protocol layer sending end and the physical layer sending end ends, and the second target time period is the communication effective time period and the frame effective time period. intersection of time periods.
  • the protocol layer sending end is a display serial interface DSI protocol layer sending end or a camera serial interface CSI-2 protocol layer sending end;
  • the protocol layer sending end is communicatively connected to the central processor, and the protocol layer sending end is used for:
  • the protocol layer sending end is used for:
  • the timing deviation calibration signal is triggered according to the calibration configuration, so that the physical layer sending end sends a timing deviation calibration sequence to the physical layer receiving end according to the timing deviation calibration signal.
  • the input unit 404 may include a graphics processor (Graphics Processing Unit, GPU) 4041 and a microphone 4042.
  • the graphics processor 4041 is responsible for the image capture device (GPU) in the video capture mode or the image capture mode. Process the image data of still pictures or videos obtained by cameras (such as cameras).
  • the display unit 406 may include a display panel 4061, which may be configured in the form of a liquid crystal display, an organic light emitting diode, or the like.
  • the user input unit 407 includes a touch panel 4071 and at least one of other input devices 4072 . Touch panel 4071, also called touch screen.
  • the touch panel 4071 may include two touch detection devices and a touch controller. part.
  • Other input devices 4072 may include but are not limited to physical keyboards, function keys (such as volume control keys, switch keys, etc.), trackballs, mice, and joysticks, which will not be described again here.
  • Memory 409 may be used to store software programs as well as various data.
  • the memory 409 may mainly include a first storage area for storing programs or instructions and a second storage area for storing data, wherein the first storage area may store an operating system, an application program or instructions required for at least one function (such as a sound playback function, Image playback function, etc.) etc.
  • memory 409 may include volatile memory or nonvolatile memory, or memory 409 may include both volatile and nonvolatile memory.
  • non-volatile memory can be read-only memory (Read-Only Memory, ROM), programmable read-only memory (Programmable ROM, PROM), erasable programmable read-only memory (ErasablePROM, EPROM), electrically erasable memory. Except programmable read-only memory (Electrically EPROM, EEPROM) or flash memory.
  • Volatile memory can be random access memory (Random Access Memory, RAM), static random access memory (Static RAM, SRAM), dynamic random access memory (DynamicRAM, DRAM), synchronous dynamic random access memory (Synchronous DRAM) , SDRAM), double data rate synchronous dynamic random access memory (Double Data Rate SDRAM, DDRSDRAM), enhanced synchronous dynamic random access memory (Enhanced SDRAM, ESDRAM), synchronous link dynamic random access memory (Synch link DRAM, SLDRAM) and Direct Rambus RAM (DRRAM).
  • RAM Random Access Memory
  • SRAM static random access memory
  • DynamicRAM dynamic random access memory
  • synchronous dynamic random access memory Synchronous DRAM
  • SDRAM double data rate synchronous dynamic random access memory
  • Double Data Rate SDRAM, DDRSDRAM double data rate synchronous dynamic random access memory
  • Enhanced SDRAM, ESDRAM enhanced synchronous dynamic random access memory
  • Synch link DRAM, SLDRAM synchronous link dynamic random access memory
  • DRRAM Direct Rambus RAM
  • the processor 410 may include one or more processing units; optionally, the processor 410 integrates an application processor and a modem processor, where the application processor mainly handles operations related to the operating system, user interface, application programs, etc., Modem processors mainly process wireless communication signals, such as baseband processors. It can be understood that the above modem processor may not be integrated into the processor 410.
  • Embodiments of the present application also provide a readable storage medium. Programs or instructions are stored on the readable storage medium. When the program or instructions are executed by a processor, each process of the above calibration control method embodiment is implemented, and the same can be achieved. The technical effects will not be repeated here to avoid repetition.
  • the processor is the processor in the electronic device described in the above embodiment.
  • the readable storage medium includes computer readable storage media, such as computer read-only memory ROM, random access memory Get memory RAM, disk or CD, etc.
  • An embodiment of the present application further provides a chip.
  • the chip includes a processor and a communication interface.
  • the communication interface is coupled to the processor.
  • the processor is used to run programs or instructions to implement the above calibration control method embodiment. Each process can achieve the same technical effect. To avoid duplication, it will not be described again here.
  • chips mentioned in the embodiments of this application may also be called system-on-chip, system-on-a-chip, system-on-a-chip or system-on-chip, etc.
  • Embodiments of the present application provide a computer program product, which is stored in a storage medium.
  • the computer program product is executed by at least one processor to implement each process of the above calibration control method embodiment, and can achieve the same To avoid repetition, the technical effects will not be repeated here.
  • the methods of the above embodiments can be implemented by means of software plus the necessary general hardware platform. Of course, it can also be implemented by hardware, but in many cases the former is better. implementation.
  • the technical solution of the present application essentially or the part that contributes to the existing technology can be embodied in the form of a computer software product.
  • the computer software product is stored in a storage medium (such as ROM/RAM, magnetic disc, optical disk), including several instructions to cause a terminal (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods described in various embodiments of this application.

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Abstract

本申请提供一种校准控制方法、装置及电子设备，涉及通信技术领域，所述方法应用于协议层发送端，所述方法包括：获取校准配置；依据所述校准配置触发时序偏差校准通信，所述时序偏差校准通信用于物理层中时钟通道与数据通道间的时序偏差校准。

Description

校准控制方法、装置及电子设备
相关申请的交叉引用
本申请主张在2022年03月24日在中国提交的中国专利申请No.202210301512.6的优先权，其全部内容通过引用包含于此。
技术领域
本申请涉及通信技术领域，尤其涉及一种校准控制方法、装置及电子设备。
背景技术
移动工业处理器接口(Mobile Industry Processor Interface，MIPI)D-PHY是MIPI协会所定义的一种物理层串行高速接口协议，提供了对显示串行接口(Display serial interface，DSI)和摄像头串行接口(Camera serial interface，CSI)协议层的支持。在协议层与物理层之间，MIPI协议定义了标准的物理层协议接口(PHY Protocol Interface，PPI)接口，应用层、协议层与物理层相互配合，从而完成相关的控制和数据的传送。
D-PHY采用一组时钟通道和不少于一组的数据通道，每条数据通道可支持10Mbps以下的低速通信和80Mbps以上的高速通信。目前，时钟通道和数据通道间的时序偏差校准通信由应用层进行调度，需要应用层实时获取协议层和物理层的通信状况，进行调度的效率较低。
发明内容
本申请实施例提供一种校准控制方法、装置及电子设备，能够解决相关技术中时序偏差校准通信由应用层进行调度，调度的效率较低的问题。
第一方面，本申请实施例提供了一种校准控制方法，应用于协议层发送端，所述方法包括：
获取校准配置；
依据所述校准配置触发时序偏差校准通信，所述时序偏差校准通信用于 物理层中时钟通道与数据通道间的时序偏差校准。
第二方面，本申请实施例提供了一种校准控制装置，协议层发送端包括所述校准控制装置，所述装置包括：
获取模块，用于获取校准配置；
触发模块，用于依据所述校准配置触发时序偏差校准通信，所述时序偏差校准通信用于物理层中时钟通道与数据通道间的时序偏差校准。
第三方面，本申请实施例提供了一种电子设备，该电子设备包括处理器、存储器及存储在所述存储器上并可在所述处理器上运行的程序或指令，所述程序或指令被所述处理器执行时实现如第一方面所述的校准控制方法中的步骤。
第四方面，本申请实施例提供了一种可读存储介质，所述可读存储介质上存储程序或指令，所述程序或指令被处理器执行时实现如第一方面所述的校准控制方法中的步骤。
第五方面，本申请实施例提供了一种芯片，所述芯片包括处理器和通信接口，所述通信接口和所述处理器耦合，所述处理器用于运行程序或指令，实现如第一方面所述的方法。
第六方面，本申请实施例提供了一种计算机程序/程序产品，所述计算机程序/程序产品被存储在存储介质中，所述计算机程序/程序产品被至少一个处理器执行以实现如第一方面所述的方法。
在本申请实施例中，协议层发送端获取校准配置；依据所述校准配置触发时序偏差校准通信，所述时序偏差校准通信用于物理层中时钟通道与数据通道间的时序偏差校准。这样，通过协议层发送端进行时钟通道和数据通道间的时序偏差校准通信的调度，不需要应用层实时获取协议层和物理层的通信状况，能够提高调度的效率。
附图说明
图1是本申请实施例提供的一种校准控制方法的流程图；
图2是本申请实施例提供的一种校准控制方法的流程示意图之一；
图3是本申请实施例提供的一种校准控制方法的流程示意图之二；
图4是本申请实施例提供的一种校准控制方法的流程示意图之三；
图5是本申请实施例提供的一种图像帧的通信示意图；
图6是本申请实施例提供的一种校准控制装置的结构图；
图7是本申请实施例提供的一种电子设备的结构图之一；
图8是本申请实施例提供的一种电子设备的结构图之二。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员获得的所有其他实施例，都属于本申请保护的范围。
本申请的说明书和权利要求书中的术语“第一”、“第二”等是用于区别类似的对象，而不用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便本申请的实施例能够以除了在这里图示或描述的那些以外的顺序实施，且“第一”、“第二”等所区分的对象通常为一类，并不限定对象的个数。此外，说明书以及权利要求中“和/或”表示所连接对象的至少其中之一，字符“/”，一般表示前后关联对象是一种“或”的关系。
下面结合附图，通过具体的实施例及其应用场景对本申请实施例提供的校准控制方法进行详细地说明。
参见图1，图1是本申请实施例提供的一种校准控制方法的流程图，应用于协议层发送端，如图1所示，包括以下步骤：
步骤101、获取校准配置。
其中，协议层发送端可以从应用层获取校准配置，示例地，可以从中央处理器获取校准配置。协议层发送端为DSI协议层发送端，例如，DSI主机(Host)；或者，协议层发送端为CSI-2协议层发送端，例如，CSI-2设备(Device)。
步骤102、依据所述校准配置触发时序偏差校准通信，所述时序偏差校准通信用于物理层中时钟通道与数据通道间的时序偏差校准。
其中，协议层发送端触发时序偏差校准通信时，向物理层发送端发送时序偏差校准信号，物理层发送端依据所述时序偏差校准信号向物理层接收端发送时序偏差校准序列。该时序偏差校准信号由协议层发送端通过PPI接口拉起TxSkewCalHS信号进行触发。PPI为MIPI协议所规定的、D-PHY或C-PHY物理层与CSI-2或DSI/DSI2协议层之间的通用接口规范。示例地，物理层发送端发送一组双方提前规定好的、重复的1010序列(通常模式)或PRBS9序列(替代模式)，物理层接收端通过调整时钟与数据通道的相位关系、以获得理想的数据采样窗口，从而实现时序偏差校准。
需要说明的是，当数据通道工作在1.5Gbps以上时，D-PHY协议要求在第一次高速通信前，进行时钟与数据通道间的时序偏差校准通信，即倾斜校准(skew calibration)通信。D-PHY的时序偏差校准，由TX发送端发送给RX接收方，时序偏差校准序列也由D-PHY TX负责实现。如图2所示，D-PHY的时序偏差校准包括：DSI主机或CSI-2设备与物理层发送端D-PHY TX之间的PPI接口拉起TxSkewCalHS信号，触发时序偏差校准通信；D-PHY TX向理层接收端D-PHY RX发送时序偏差校准序列；D-PHY RX根据时序偏差校准序列调整时钟与数据通道的相位关系；D-PHY RX在接收到时序偏差校准序列时，D-PHY RX与DSI设备或CSI-2主机之间的PPI接口拉起RxSkewCalHS信号。
D-PHY是MIPI协议中的一项，是一种高速、低功率的可扩展串行互联的物理层规范。D-PHY提供了对DSI和CSI-2在物理层上的定义。D-PHY采用1对源同步的双线点对点时钟和1对或以上的双线点对点数据线来进行数据的传输，每对数据线可工作在不高于10Mbps的单端低速模式、或不低于80Mbps的差分高速模式。CSI-2是MIPI协议中的一项，是针对摄像头的协议层接口规范，可与物理层的D-PHY或C-PHY协议配合完成摄像头通信方案，在CSI-2中，发送端是CSI-2 Device，接收端是CSI-2 Host。DSI是MIPI协议中的一项，是针对显示器的协议层接口规范，可与物理层的D-PHY配合完成摄像头通信方案，在DSI中，发送端是DSI Host，接收端是DSI Device。
发送端的CSI-2或DSI协议层与D-PHY物理层的控制和通信，一般是由更上层的软件应用层进行调度。但对于时序偏差校准，如果控制用的PPI信号TxSkewCalHS的发起也由应用层进行调度，特别是当选择进行周期性校准 的时候，则需要应用层对协议层的工作状态进行把握、并受限于协议层与物理层之间的通信状态，这相应增加了软件应用层调度的成本，并降低了整体控制的效率。本实施例中，由协议层发送端触发时序偏差校准通信，能够降低软件应用层调度的成本，且能够提高校准控制的效率。
一种实施方式中，可以在CSI-2 Device和DSI Host协议层控制模块内，实现对D-PHY时序偏差校准通信进行自适应管理的机制，从而达到减少软件应用层调度开销、提升系统效率的目的。在CSI-2 Device和DSI Host协议层控制模块内，可以配置发起D-PHY Skew Calibration时序偏差校准通信的自适应控制逻辑。在软件应用层进行初始设置后，自适应逻辑可根据可配置的设置选项，根据协议层与物理层实时的数据通信情况，在数据通道空闲时、或数据通道传输的每帧图像的起始或结尾的空闲行，自动拉起TxSkewCalHS以触发物理层发送端发起时序偏差校准通信，从而在无需应用层调度的情况下实现周期性的校准通信。如图3所示，协议层发送端触发时序偏差校准通信，发起自适应控制逻辑在协议层，根据应用层的校准配置自主执行、可以实时把握协议层自身状态自适应调整，应用层只需要在启动时配置即可。
需要说明的是，所述协议层发送端可以为DSI主机或CSI-2设备，在所述协议层发送端为DSI Host的情况下，所述协议层发送端与物理层发送端的D-PHY连接，在所述协议层发送端为CSI-2 Device的情况下，所述协议层发送端与所述物理层发送端的D-PHY连接。CSI-2 Device是摄像头解决方案时的协议层发送端，DSI Host为显示器解决方案时的协议层发送端，它们都与物理层发送端的D-PHY TX连接。
作为一种具体的实施例，以CSI-2 Device为例进行说明，DSI Host与CSI-2Device对时序偏差校准通信的自适应控制逻辑类同。时序偏差校准通信的自适应控制逻辑的实施方式可以如下：电子设备启动后，电子设备的软件应用层对包括CSI-2 Device在内的相关模块进行初始化配置，此时包含了对增加的自适应控制逻辑的配置。CSI-2 Device根据软件应用层的校准配置进行相应的通信，自适应控制逻辑根据软件应用层的校准配置，在满足校准配置的条件、并且与D-PHY TX模块之间有足够的空闲时间进行通信时，拉起TxSkewCalHS信号触发时序偏差校准通信。D-PHY TX在收到TxSkewCalHS 信号后，向D-PHY RX发送时序偏差校准序列。如图4所示，在自适应控制逻辑中，触发条件判断逻辑用于根据校准配置以及结合除自适应控制逻辑外的其他模块的模块状态判断是否满足触发时序偏差校准通信的条件，模块状态可以包括CSI-2 Device与D-PHY TX的通信状态；发起逻辑用于在满足触发条件时触发时序偏差校准通信；控制与状态寄存器用于接收应用层的校准配置，并保存校准配置的执行状态。
本实施例中，通过在CSI-2 Device和DSI Host模块内增加时序偏差校准通信的自适应控制逻辑，允许软件应用层在启动配置后无需再进行周期性的调度，从而能够减少调度开销、减轻应用层负担。同时CSI-2 Device和DSI Host在进行时序偏差校准通信的控制时，能够实时把握自身内部的通信状态，从而也减少了通过应用层调度引入的延迟。
需要说明的是，CSI-2 Device在触发时序偏差校准通信时，可以向应用层提供状态信息，例如，可以通过状态寄存器或信号提供，应用层可以通过状态信息获取时序偏差校准通信的相关状态。在进行时序偏差校准通信时，应用层可以等待时序偏差校准通信完成后再启动与CSI-2 Device的下一次通信。
在本申请实施例中，协议层发送端获取校准配置；依据所述校准配置触发时序偏差校准通信，所述时序偏差校准通信用于物理层中时钟通道与数据通道间的时序偏差校准。这样，通过协议层发送端进行时钟通道和数据通道间的时序偏差校准通信的调度，不需要应用层实时获取协议层和物理层的通信状况，能够提高调度的效率。
可选的，所述校准配置包括校准模式、校准序列长度、触发周期间隔、触发允许时间段及校准通信速率中的至少一项。
其中，校准模式可以为时序偏差校准的模式，示例地，校准模式可以包括初始校准及周期校准中的至少一项。初始校准可以是，仅在初次检测到通信速率大于预设阈值时进行时序偏差校准。周期校准可以是周期性地进行时序偏差校准。校准序列长度可以为时序偏差校准序列的长度。触发周期间隔可以为触发时序偏差校准通信的时间间隔，示例地，触发周期间隔可以是按目标帧数触发，或者可以是按目标时钟周期数触发，或者可以是按目标时长 触发，本实施例对此不进行限定。目标帧数，目标时钟周期数，及目标时长可以是预先设置在软件程序中，或者可以由用户配置。以触发周期间隔为目标时长，目标时长为1秒为例，可以每隔1秒触发一次时序偏差校准通信。触发允许时间段可以是允许触发时序偏差校准通信的时间段，触发允许时间段可以包括通信空闲时间段及帧间空闲时间段中的至少一项。校准通信速率为执行周期校准的通信速率，示例地，可以在校准模式为周期校准且检测到数据通道的通信速率大于校准通信速率的情况下，依据校准序列长度、触发周期间隔及触发允许时间段触发时序偏差校准通信。
另外，校准配置可以包括校准模式、校准序列长度、触发周期间隔、触发允许时间段及校准通信速率中的其中任意一项，示例地，校准配置可以包括校准模式，协议层发送端可以从中央处理器获取校准模式，协议层发送端可以根据从中央处理器获取到的校准模式，及默认配置的校准通信速率、校准序列长度、触发周期间隔及触发允许时间段触发时序偏差校准通信；或者，校准配置可以包括校准模式、校准序列长度、触发周期间隔、触发允许时间段及校准通信速率中的其中任意两项，示例地，校准配置可以包括触发周期间隔及触发允许时间段，协议层发送端可以从中央处理器获取触发周期间隔及触发允许时间段，协议层发送端可以根据从中央处理器获取到的触发周期间隔及触发允许时间段，及默认配置的校准通信速率、校准模式及校准序列长度触发时序偏差校准通信；或者，校准配置可以包括校准模式、校准序列长度、触发周期间隔、触发允许时间段及校准通信速率中的其中任意三项，示例地，校准配置可以包括校准模式、触发周期间隔及触发允许时间段，协议层发送端可以从中央处理器获取校准模式、触发周期间隔及触发允许时间段，协议层发送端可以根据从中央处理器获取到的校准模式、触发周期间隔及触发允许时间段，及默认配置的校准序列长度及校准通信速率触发时序偏差校准通信。
示例地，用户可以在软件界面选择配置如下选项：只支持初始校准，或使能可选的周期校准；校准序列长度；触发周期间隔；触发允许时间段。
该实施方式中，所述校准配置包括校准模式、校准序列长度、触发周期间隔、触发允许时间段及校准通信速率中的至少一项，从而协议层发送端可 以依据校准模式、校准序列长度、触发周期间隔及触发允许时间段中的至少一项触发时序偏差校准通信。
可选的，所述校准配置包括所述校准模式及校准序列长度，所述校准模式为初始校准，所述依据所述校准配置触发时序偏差校准通信，包括：
在初次检测到所述数据通道的通信速率大于预设阈值的情况下，依据所述校准序列长度触发时序偏差校准通信。
其中，初始校准可以是仅在初次检测到通信速率大于预设阈值时进行校准。预设阈值是较高的通信速率，预设阈值可以预先设置。
一种实施方式中，预设阈值按照通信协议的规定为1.5Gbps。
另外，依据所述校准序列长度触发时序偏差校准通信,可以是，触发时序偏差校准信号，以使物理层发送端按照校准序列长度向物理层接收端发送时序偏差校准序列。
该实施方式中，在所述校准模式为初始校准的情况下，在初次检测到所述数据通道的通信速率大于预设阈值的情况下，依据所述校准序列长度触发时序偏差校准通信，这样，能够基于初始校准的校准配置触发时序偏差校准通信。
可选的，所述校准配置包括所述校准模式及校准序列长度、触发周期间隔及触发允许时间段，所述校准模式为周期校准，所述依据所述校准配置触发时序偏差校准通信，包括：
在满足所述触发周期间隔的情况下，依据所述校准序列长度以及所述触发允许时间段触发时序偏差校准通信。
其中，可以在当前时刻满足所述触发周期间隔的情况下，依据所述校准序列长度以及所述触发允许时间段触发时序偏差校准通信。周期校准可以是周期性地进行校准，例如，可以是每隔1秒进行一次校准。当前时刻满足所述触发周期间隔，可以是当前时刻与上一次触发时序偏差校准通信的时刻之间的差值达到触发周期间隔。示例地，触发周期间隔为1秒,当前时刻与上一次触发时序偏差校准通信的时刻之间的差值为1秒，可以认为当前时刻满足触发周期间隔。
一种实施方式中，以CSI-2 Device为例进行说明，当校准模式为周期校 准时，可以在满足触发周期间隔、及触发允许时间段、且时序偏差校准序列所需处理时间不大于允许的空闲时段时可触发时序偏差校准通信。当满足上述可触发时序偏差校准通信的配置条件时，如果CSI-2 Device与D-PHY TX之间还有未完成的通信时，CSI-2 Device相应进行等待并同步更新相关控制逻辑，在等待CSI-2 Device与D-PHY TX之间通信结束后，再执行触发时序偏差校准通信。
该实施方式中，在所述校准模式为周期校准的情况下，在满足所述触发周期间隔的情况下，依据所述校准序列长度以及所述触发允许时间段触发时序偏差校准通信，这样，能够基于周期校准的校准配置触发时序偏差校准通信。
可选的，所述校准配置还包括校准通信速率，所述依据所述校准序列长度以及所述触发允许时间段触发时序偏差校准通信，包括：
在检测到所述数据通道的通信速率大于所述校准通信速率的情况下，依据所述校准序列长度以及所述触发允许时间段触发时序偏差校准通信。
其中，在所述校准模式为周期校准的情况下，可以在检测到所述数据通道的通信速率大于校准通信速率，且满足所述触发周期间隔的情况下，依据所述校准序列长度以及所述触发允许时间段触发时序偏差校准通信。校准通信速率可以配置为1.5Gbps，或者2Gbps，或者2.5Gbps，等等，本实施例对此不进行限定。
该实施方式中，通过校准配置中的校准通信速率，可以确定周期校准执行的通信速率。
可选的，所述依据所述校准序列长度以及所述触发允许时间段触发时序偏差校准通信，包括如下至少一项：
在通信空闲时间段按照所述校准序列长度触发时序偏差校准通信；
在第一目标时间段内，若所述校准序列长度小于帧间隔长度，则触发时序偏差校准通信，所述第一目标时间段为通信有效时间段与帧空闲时间段的交集；
在第二目标时间段内，在所述协议层发送端与物理层发送端之间通信结束的情况下触发时序偏差校准通信，所述第二目标时间段为所述通信有效时 间段与帧有效时间段的交集。
其中，通信空闲时间段可以是协议层发送端与物理层发送端之间未进行帧传输通信，通信有效时间段可以是协议层发送端与物理层发送端之间进行帧传输通信，帧空闲时间段可以是帧传输通信中两帧之间的帧空白时间，帧有效时间段可以是帧传输通信时一帧中的行空白时间。
另外，所述依据所述校准序列长度以及所述触发允许时间段触发时序偏差校准通信，可以包括如下至少一项：在当前时刻处于通信空闲时间段的情况下，按照所述校准序列长度触发时序偏差校准通信；在当前时刻处于通信有效时间段且帧空闲时间段的情况下，若所述校准序列长度小于帧间隔长度，则触发时序偏差校准通信；在当前时刻处于所述通信有效时间段且帧有效时间段的情况下，在所述协议层发送端与物理层发送端之间通信结束的情况下触发时序偏差校准通信。
如图5所示，在两帧之间存在帧空白(Frame blanking)，即帧空闲时间段，若所述校准序列长度小于帧间隔长度，则可以触发时序偏差校准通信；在一帧通信中，即帧有效时间段，存在行空白(line blanking)，即所述协议层发送端与物理层发送端之间通信结束，可以触发时序偏差校准通信。在图5中，FS指帧开始(Frame start)，FE指帧结束(Frame End)，PF指数据包页脚+填充(packet footer+filler)，ED指包含嵌入式数据类型代码的数据包头(packet header containing embedded data type code)，D1指包含数据类型1图像数据代码的数据包头(packet header containing data type1 image data code)，D2指包含数据类型2图像数据代码的数据包头(packet header containing data type2 image data code)。
该实施方式中，所述依据所述校准序列长度以及所述触发允许时间段触发时序偏差校准通信，包括如下至少一项：在通信空闲时间段按照所述校准序列长度触发时序偏差校准通信；在第一目标时间段内，若所述校准序列长度小于帧间隔长度，则触发时序偏差校准通信，所述第一目标时间段为通信有效时间段与帧空闲时间段的交集；在第二目标时间段内，在所述协议层发送端与物理层发送端之间通信结束的情况下触发时序偏差校准通信，所述第二目标时间段为所述通信有效时间段与帧有效时间段的交集。从而能够通过 校准配置灵活设置触发时序偏差校准通信的条件。
可选的，所述协议层发送端为显示串行接口DSI协议层发送端或摄像头串行接口CSI-2协议层发送端；
所述协议层发送端与物理层发送端的D-PHY连接。
其中，在所述协议层发送端为DSI Host的情况下，所述协议层发送端与物理层发送端的D-PHY连接，从而能够实现显示器解决方案；在所述协议层发送端为CSI-2 Device的情况下，所述协议层发送端与所述物理层发送端的D-PHY连接，从而能够实现摄像头解决方案。
可选的，所述协议层发送端与中央处理器通信连接，所述获取校准配置，包括：
从所述中央处理器获取校准配置。
该实施方式中，从所述中央处理器获取校准配置，从而应用层仅需要向协议层下发校准配置，不需要应用层实时获取协议层和物理层的通信状况。
可选的，所述依据所述校准配置触发时序偏差校准通信，包括：
依据所述校准配置触发时序偏差校准信号，以使物理层发送端依据所述时序偏差校准信号向物理层接收端发送时序偏差校准序列。
其中，时序偏差校准信号可以为TxSkewCalHS信号，协议层发送端为DSI主机或CSI-2设备，物理层发送端为D-PHY TX，物理层接收端为D-PHY RX，DSI主机或CSI-2设备与D-PHY TX之间的PPI接口拉起TxSkewCalHS信号，触发时序偏差校准通信，D-PHY TX向D-PHY RX发送时序偏差校准序列；D-PHY RX根据时序偏差校准序列调整时钟与数据通道的相位关系，从而能够实现时序偏差校准。
需要说明的是，本申请实施例提供的校准控制方法，执行主体可以为校准控制装置。本申请实施例中以校准控制装置执行校准控制的方法为例，说明本申请实施例提供的校准控制的装置。
参见图6，图6是本申请实施例提供的一种校准控制装置的结构示意图，协议层发送端包括所述校准控制装置，如图6所示，所述校准控制装置200包括：
获取模块201，用于获取校准配置；
触发模块202，用于依据所述校准配置触发时序偏差校准通信，所述时序偏差校准通信用于物理层中时钟通道与数据通道间的时序偏差校准。
可选的，所述校准配置包括校准模式、校准序列长度、触发周期间隔、触发允许时间段及校准通信速率中的至少一项。
可选的，所述校准配置包括所述校准模式及校准序列长度，所述校准模式为初始校准，所述触发模块202具体用于：
在初次检测到所述数据通道的通信速率大于预设阈值的情况下，依据所述校准序列长度触发时序偏差校准通信。
可选的，所述校准配置包括所述校准模式、校准序列长度、触发周期间隔及触发允许时间段，所述校准模式为周期校准，所述触发模块202具体用于：
在满足所述触发周期间隔的情况下，依据所述校准序列长度以及所述触发允许时间段触发时序偏差校准通信。
可选的，所述校准配置还包括所述校准通信速率，所述触发模块202具体用于：
在满足所述触发周期间隔且在检测到所述数据通道的通信速率大于所述校准通信速率的情况下，依据所述校准序列长度以及所述触发允许时间段触发时序偏差校准通信。
可选的，所述校准模式为周期校准，且在满足所述触发周期间隔的情况下，所述触发模块202具体用于如下至少一项：
在通信空闲时间段按照所述校准序列长度触发时序偏差校准通信；
在第一目标时间段内，若所述校准序列长度小于帧间隔长度，则触发时序偏差校准通信，所述第一目标时间段为通信有效时间段与帧空闲时间段的交集；
在第二目标时间段内，在所述协议层发送端与物理层发送端之间通信结束的情况下触发时序偏差校准通信，所述第二目标时间段为所述通信有效时间段与帧有效时间段的交集。
可选的，所述协议层发送端为显示串行接口DSI协议层发送端或摄像头串行接口CSI-2协议层发送端；
所述协议层发送端与物理层发送端的D-PHY连接。
可选的，所述协议层发送端与中央处理器通信连接，所述获取模块201具体用于：
从所述中央处理器获取校准配置。
可选的，所述触发模块202具体用于：
依据所述校准配置触发时序偏差校准信号，以使物理层发送端依据所述时序偏差校准信号向物理层接收端发送时序偏差校准序列。
在本申请实施例中，获取模块201获取校准配置；触发模块202依据所述校准配置触发时序偏差校准通信，所述时序偏差校准通信用于物理层中时钟通道与数据通道间的时序偏差校准。这样，通过协议层发送端进行时钟通道和数据通道间的时序偏差校准通信的调度，不需要应用层实时获取协议层和物理层的通信状况，能够提高调度的效率。
本申请实施例中的校准控制装置可以是电子设备，也可以是电子设备中的部件，例如集成电路或芯片。该电子设备可以是终端，也可以为除终端之外的其他设备。示例性的，电子设备可以为手机、平板电脑、笔记本电脑、掌上电脑、车载电子设备、移动上网装置(Mobile Internet Device，MID)、增强现实(augmented reality，AR)/虚拟现实(virtual reality，VR)设备、机器人、可穿戴设备、超级移动个人计算机(ultra-mobile personal computer，UMPC)、上网本或者个人数字助理(personal digital assistant，PDA)等，还可以为服务器、网络附属存储器(Network Attached Storage，NAS)、个人计算机(personal computer，PC)、电视机(television，TV)、柜员机或者自助机等，本申请实施例不作具体限定。
本申请实施例中的校准控制装置可以为具有操作系统的装置。该操作系统可以为安卓(Android)操作系统，可以为ios操作系统，还可以为其他可能的操作系统，本申请实施例不作具体限定。
本申请实施例提供的校准控制装置能够实现上述方法实施例实现的各个过程，为避免重复，这里不再赘述。
可选地，如图7所示，本申请实施例还提供一种电子设备300，包括处 理器301和存储器302，存储器302上存储有可在所述处理器301上运行的程序或指令，该程序或指令被处理器301执行时实现上述校准控制方法实施例的各个步骤，且能达到相同的技术效果，为避免重复，这里不再赘述。
需要说明的是，本申请实施例中的电子设备包括上述所述的移动电子设备和非移动电子设备。
图8为实现本申请实施例的一种电子设备的硬件结构示意图。
该电子设备400包括但不限于：射频单元401、网络模块402、音频输出单元403、输入单元404、传感器405、显示单元406、用户输入单元407、接口单元408、存储器409、以及处理器410等部件。
本领域技术人员可以理解，电子设备400还可以包括给各个部件供电的电源(比如电池)，电源可以通过电源管理系统与处理器410逻辑相连，从而通过电源管理系统实现管理充电、放电、以及功耗管理等功能。图8中示出的电子设备结构并不构成对电子设备的限定，电子设备可以包括比图示更多或更少的部件，或者组合某些部件，或者不同的部件布置，在此不再赘述。
其中，电子设备400还包括协议层发送端，所述协议层发送端用于：
获取校准配置；
依据所述校准配置触发时序偏差校准通信，所述时序偏差校准通信用于物理层中时钟通道与数据通道间的时序偏差校准。
可选的，所述校准配置包括校准模式、校准序列长度、触发周期间隔、触发允许时间段及校准通信速率中的至少一项。
可选的，所述校准配置包括所述校准模式及校准序列长度，所述校准模式为初始校准，所述协议层发送端用于：
在初次检测到所述数据通道的通信速率大于预设阈值的情况下，依据所述校准序列长度触发时序偏差校准通信。
可选的，所述校准配置包括所述校准模式、校准序列长度、触发周期间隔及触发允许时间段，所述校准模式为周期校准，所述协议层发送端用于：
在满足所述触发周期间隔的情况下，依据所述校准序列长度以及所述触发允许时间段触发时序偏差校准通信。
可选的，所述校准配置还包括所述校准通信速率，在所述校准模式为周期校准的情况下，所述协议层发送端用于：
在满足所述触发周期间隔且在检测到所述数据通道的通信速率大于所述校准通信速率的情况下，依据所述校准序列长度以及所述触发允许时间段触发时序偏差校准通信。
可选的，所述协议层发送端用于如下至少一项：
在通信空闲时间段按照所述校准序列长度触发时序偏差校准通信；
在第一目标时间段内，若所述校准序列长度小于帧间隔长度，则触发时序偏差校准通信，所述第一目标时间段为通信有效时间段与帧空闲时间段的交集；
在第二目标时间段内，在所述协议层发送端与物理层发送端之间通信结束的情况下触发时序偏差校准通信，所述第二目标时间段为所述通信有效时间段与帧有效时间段的交集。
可选的，所述协议层发送端为显示串行接口DSI协议层发送端或摄像头串行接口CSI-2协议层发送端；
所述协议层发送端与物理层发送端的D-PHY连接。
可选的，所述协议层发送端与中央处理器通信连接，所述协议层发送端用于：
从所述中央处理器获取校准配置。
可选的，所述协议层发送端用于：
依据所述校准配置触发时序偏差校准信号，以使物理层发送端依据所述时序偏差校准信号向物理层接收端发送时序偏差校准序列。
应理解的是，本申请实施例中，输入单元404可以包括图形处理器(Graphics Processing Unit，GPU)4041和麦克风4042，图形处理器4041对在视频捕获模式或图像捕获模式中由图像捕获装置(如摄像头)获得的静态图片或视频的图像数据进行处理。显示单元406可包括显示面板4061，可以采用液晶显示器、有机发光二极管等形式来配置显示面板4061。用户输入单元407包括触控面板4071以及其他输入设备4072中的至少一种。触控面板4071，也称为触摸屏。触控面板4071可包括触摸检测装置和触摸控制器两个 部分。其他输入设备4072可以包括但不限于物理键盘、功能键(比如音量控制按键、开关按键等)、轨迹球、鼠标、操作杆，在此不再赘述。
存储器409可用于存储软件程序以及各种数据。存储器409可主要包括存储程序或指令的第一存储区和存储数据的第二存储区，其中，第一存储区可存储操作系统、至少一个功能所需的应用程序或指令(比如声音播放功能、图像播放功能等)等。此外，存储器409可以包括易失性存储器或非易失性存储器，或者，存储器409可以包括易失性和非易失性存储器两者。其中，非易失性存储器可以是只读存储器(Read-Only Memory，ROM)、可编程只读存储器(Programmable ROM，PROM)、可擦除可编程只读存储器(ErasablePROM，EPROM)、电可擦除可编程只读存储器(Electrically EPROM，EEPROM)或闪存。易失性存储器可以是随机存取存储器(Random Access Memory，RAM)，静态随机存取存储器(Static RAM，SRAM)、动态随机存取存储器(DynamicRAM，DRAM)、同步动态随机存取存储器(Synchronous DRAM，SDRAM)、双倍数据速率同步动态随机存取存储器(Double Data Rate SDRAM，DDRSDRAM)、增强型同步动态随机存取存储器(Enhanced SDRAM，ESDRAM)、同步连接动态随机存取存储器(Synch link DRAM，SLDRAM)和直接内存总线随机存取存储器(Direct Rambus RAM，DRRAM)。本申请实施例中的存储器409包括但不限于这些和任意其它适合类型的存储器。
处理器410可包括一个或多个处理单元；可选的，处理器410集成应用处理器和调制解调处理器，其中，应用处理器主要处理涉及操作系统、用户界面和应用程序等的操作，调制解调处理器主要处理无线通信信号，如基带处理器。可以理解的是，上述调制解调处理器也可以不集成到处理器410中。
本申请实施例还提供一种可读存储介质，所述可读存储介质上存储有程序或指令，该程序或指令被处理器执行时实现上述校准控制方法实施例的各个过程，且能达到相同的技术效果，为避免重复，这里不再赘述。
其中，所述处理器为上述实施例中所述的电子设备中的处理器。所述可读存储介质，包括计算机可读存储介质，如计算机只读存储器ROM、随机存 取存储器RAM、磁碟或者光盘等。
本申请实施例另提供了一种芯片，所述芯片包括处理器和通信接口，所述通信接口和所述处理器耦合，所述处理器用于运行程序或指令，实现上述校准控制方法实施例的各个过程，且能达到相同的技术效果，为避免重复，这里不再赘述。
应理解，本申请实施例提到的芯片还可以称为系统级芯片、系统芯片、芯片系统或片上系统芯片等。
本申请实施例提供一种计算机程序产品，该计算机程序产品被存储在存储介质中，该计算机程序产品被至少一个处理器执行以实现如上述校准控制方法实施例的各个过程，且能达到相同的技术效果，为避免重复，这里不再赘述。
需要说明的是，在本文中，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者装置不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者装置所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括该要素的过程、方法、物品或者装置中还存在另外的相同要素。此外，需要指出的是，本申请实施方式中的方法和装置的范围不限按示出或讨论的顺序来执行功能，还可包括根据所涉及的功能按基本同时的方式或按相反的顺序来执行功能，例如，可以按不同于所描述的次序来执行所描述的方法，并且还可以添加、省去、或组合各种步骤。另外，参照某些示例所描述的特征可在其他示例中被组合。
通过以上的实施方式的描述，本领域的技术人员可以清楚地了解到上述实施例方法可借助软件加必需的通用硬件平台的方式来实现，当然也可以通过硬件，但很多情况下前者是更佳的实施方式。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分可以以计算机软件产品的形式体现出来，该计算机软件产品存储在一个存储介质(如ROM/RAM、磁 碟、光盘)中，包括若干指令用以使得一台终端(可以是手机，计算机，服务器，或者网络设备等)执行本申请各个实施例所述的方法。
上面结合附图对本申请的实施例进行了描述，但是本申请并不局限于上述的具体实施方式，上述的具体实施方式仅仅是示意性的，而不是限制性的，本领域的普通技术人员在本申请的启示下，在不脱离本申请宗旨和权利要求所保护的范围情况下，还可做出很多形式，均属于本申请的保护之内。

Claims (21)

  1. 一种校准控制方法，应用于协议层发送端，所述方法包括：
    获取校准配置；
    依据所述校准配置触发时序偏差校准通信，所述时序偏差校准通信用于物理层中时钟通道与数据通道间的时序偏差校准。
  2. 根据权利要求1所述的方法，其中，所述校准配置包括校准模式、校准序列长度、触发周期间隔、触发允许时间段及校准通信速率中的至少一项。
  3. 根据权利要求2所述的方法，其中，所述校准配置包括所述校准模式及校准序列长度，所述校准模式为初始校准，所述依据所述校准配置触发时序偏差校准通信，包括：
    在初次检测到所述数据通道的通信速率大于预设阈值的情况下，依据所述校准序列长度触发时序偏差校准通信。
  4. 根据权利要求2所述的方法，其中，所述校准配置包括所述校准模式、校准序列长度、触发周期间隔及触发允许时间段，所述校准模式为周期校准，所述依据所述校准配置触发时序偏差校准通信，包括：
    在满足所述触发周期间隔的情况下，依据所述校准序列长度以及所述触发允许时间段触发时序偏差校准通信。
  5. 根据权利要求4所述的方法，其中，所述校准配置还包括所述校准通信速率，所述依据所述校准序列长度以及所述触发允许时间段触发时序偏差校准通信，包括：
    在检测到所述数据通道的通信速率大于所述校准通信速率的情况下，依据所述校准序列长度以及所述触发允许时间段触发时序偏差校准通信。
  6. 根据权利要求4或5所述的方法，其中，所述依据所述校准序列长度以及所述触发允许时间段触发时序偏差校准通信，包括如下至少一项：
    在通信空闲时间段按照所述校准序列长度触发时序偏差校准通信；
    在第一目标时间段内，若所述校准序列长度小于帧间隔长度，则触发时序偏差校准通信，所述第一目标时间段为通信有效时间段与帧空闲时间段的交集；
    在第二目标时间段内，在所述协议层发送端与物理层发送端之间通信结束的情况下触发时序偏差校准通信，所述第二目标时间段为所述通信有效时间段与帧有效时间段的交集。
  7. 根据权利要求1所述的方法，其中，所述协议层发送端为显示串行接口DSI协议层发送端或摄像头串行接口CSI-2协议层发送端；
    所述协议层发送端与物理层发送端的D-PHY连接。
  8. 根据权利要求1所述的方法，其中，所述协议层发送端与中央处理器通信连接，所述获取校准配置，包括：
    从所述中央处理器获取校准配置。
  9. 根据权利要求1所述的方法，其中，所述依据所述校准配置触发时序偏差校准通信，包括：
    依据所述校准配置触发时序偏差校准信号，以使物理层发送端依据所述时序偏差校准信号向物理层接收端发送时序偏差校准序列。
  10. 一种校准控制装置，协议层发送端包括所述校准控制装置，所述装置包括：
    获取模块，用于获取校准配置；
    触发模块，用于依据所述校准配置触发时序偏差校准通信，所述时序偏差校准通信用于物理层中时钟通道与数据通道间的时序偏差校准。
  11. 根据权利要求10所述的装置，其中，所述校准配置包括校准模式、校准序列长度、触发周期间隔、触发允许时间段及校准通信速率中的至少一项。
  12. 根据权利要求11所述的装置，其中，所述校准配置包括所述校准模式及校准序列长度，所述校准模式为初始校准，所述触发模块具体用于：
    在初次检测到所述数据通道的通信速率大于预设阈值的情况下，依据所述校准序列长度触发时序偏差校准通信。
  13. 根据权利要求11所述的装置，其中，所述校准配置包括所述校准模式、校准序列长度、触发周期间隔及触发允许时间段，所述校准模式为周期校准，所述触发模块具体用于：
    在满足所述触发周期间隔的情况下，依据所述校准序列长度以及所述触 发允许时间段触发时序偏差校准通信。
  14. 根据权利要求13所述的装置，其中，所述校准配置还包括所述校准通信速率，所述触发模块具体用于：
    在满足所述触发周期间隔且在检测到所述数据通道的通信速率大于所述校准通信速率的情况下，依据所述校准序列长度以及所述触发允许时间段触发时序偏差校准通信。
  15. 根据权利要求13所述的装置，其中，在所述校准模式为周期校准的情况下，且在满足所述触发周期间隔的情况下，所述触发模块具体用于如下至少一项：
    在通信空闲时间段按照所述校准序列长度触发时序偏差校准通信；
    在第一目标时间段内，若所述校准序列长度小于帧间隔长度，则触发时序偏差校准通信，所述第一目标时间段为通信有效时间段与帧空闲时间段的交集；
    在第二目标时间段内，在所述协议层发送端与物理层发送端之间通信结束的情况下触发时序偏差校准通信，所述第二目标时间段为所述通信有效时间段与帧有效时间段的交集。
  16. 根据权利要求10所述的装置，其中，所述协议层发送端为显示串行接口DSI协议层发送端或摄像头串行接口CSI-2协议层发送端；
    所述协议层发送端与物理层发送端的D-PHY连接。
  17. 根据权利要求10所述的装置，其中，所述协议层发送端与中央处理器通信连接，所述获取模块具体用于：
    从所述中央处理器获取校准配置。
  18. 根据权利要求10所述的装置，其中，所述触发模块具体用于：
    依据所述校准配置触发时序偏差校准信号，以使物理层发送端依据所述时序偏差校准信号向物理层接收端发送时序偏差校准序列。
  19. 一种电子设备，包括处理器，存储器及存储在所述存储器上并可在所述处理器上运行的程序或指令，所述程序或指令被所述处理器执行时实现如权利要求1-9中任一项所述的校准控制方法的步骤。
  20. 一种可读存储介质，所述可读存储介质上存储程序或指令，所述程 序或指令被处理器执行时实现如权利要求1-9中任一项所述的校准控制方法的步骤。
  21. 一种芯片，包括处理器和通信接口，其中，所述通信接口和所述处理器耦合，所述处理器用于运行程序或指令，实现如权利要求1-9中任一项所述的校准控制方法的步骤。
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