Classifications

• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
  • G06F12/02—Addressing or allocation; Relocation
  • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
  • G06F12/10—Address translation
  • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
  • G06F12/02—Addressing or allocation; Relocation
  • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
  • G06F12/10—Address translation
  • G06F12/1009—Address translation using page tables, e.g. page table structures
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
  • G06F12/14—Protection against unauthorised use of memory or access to memory
  • G06F12/1458—Protection against unauthorised use of memory or access to memory by checking the subject access rights
  • G06F12/1466—Key-lock mechanism
  • G06F12/1475—Key-lock mechanism in a virtual system, e.g. with translation means

Definitions

• the memory management circuitry is configured to support two or more variants of the read-as-X property corresponding to different values for the specified value X, to allow use of the read-as-X behaviour for a range of different values to be assigned to regions of virtual memory without consuming physical memory.
• the pipeline stages include a fetch stage 6 for fetching instructions from an instruction cache 8; a decode stage 10 for decoding the fetched program instructions to generate micro-operations (decoded instructions) to be processed by remaining stages of the pipeline; an issue stage 12 for checking whether operands required for the microoperations are available in a register file 14 and issuing micro-operations for execution once the required operands for a given micro-operation are available; an execute stage 16 for executing data processing operations corresponding to the micro-operations, by processing operands read from the register file 14 to generate result values; and a writeback stage 18 for writing the results of the processing back to the register file 14.
• register renaming stage could be included for mapping architectural registers specified by program instructions or microoperations to physical register specifiers identifying physical registers in the register file 14.
• Figure 2 illustrates processing of read and write requests to pages of an address space treated as “normal” memory.
• the “normal” memory type can be used for a page intended to be used for regular random-access data or instruction storage.
• the MMU 28 looks up the virtual address specified by the read request in its TLB 29. If the TLB 29 already includes page table information for the virtual address, then the attributes and address translation mapping information provided by the page table information are used to control translation of the virtual address into a physical address, check access permissions to determine whether the read request can be allowed (with a fault signalled if the read request is not allowed), and control the way in which the read request of service based on the attributes (e.g.
• the MMU 28 does not need to translate the virtual address to a physical address and can suppress any access to the cache 30, 32 or memory 34 which would otherwise be issued to obtain the value of the read data. Note that cache/memory accesses might still be needed if a page table walk is required, to obtain the page table information associated with the read target virtual address, even if cache/memory accesses can be suppressed for obtaining the data value of X.
• the read-as-X property is a new architectural property defined in the page table information supported by the MMU 28. While this may require some additional encoding space in the page table information, this has several benefits over the software-implemented copy-on-write mechanism for filling large regions of memory with a predetermined value.
• Read-as-0 write-ignore a variant of read-as-zero where the write-ignore behaviour of step 160 of Figure 5 is used when a write is requested to a read-as-X page;
• the initial indirection table may specify whether the page is a read-as-X page or a non-read-as-X page, and could specify other properties of the read-as-X property such as the read-as-X write behaviour or the type of system component to be forwarded with write data for a read-as-X page, but for at least some encodings designated as denoting a read-as-X page of memory, the encoding may be interpreted as a reference to the further indirection table 204 where the referenced entry specifies the particular value to be returned four reads to the read-as-X page of memory.

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• Theoretical Computer Science (AREA)
• Physics & Mathematics (AREA)
• General Engineering & Computer Science (AREA)
• General Physics & Mathematics (AREA)
• Memory System Of A Hierarchy Structure (AREA)
• Memory System (AREA)
• Information Retrieval, Db Structures And Fs Structures Therefor (AREA)

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• 2022
  • 2022-03-16 GB GB2203646.1A patent/GB2616643B/en active Active
  • 2022-12-20 KR KR1020247033873A patent/KR20240159950A/ko active Pending
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• 2023
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